content
stringlengths 1
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|---|
entity e is
port ( input : in bit_vector(7 downto 0);
output : out bit_vector(7 downto 0) );
end entity;
architecture a of e is
begin
x: entity work.e
port map (
input(7 downto 0 => blah,
output(7 downto 0) => q );
call(x, y, z); -- Crash here after earlier error
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2195.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p01n02i02195ent IS
END c07s02b00x00p01n02i02195ent;
ARCHITECTURE c07s02b00x00p01n02i02195arch OF c07s02b00x00p01n02i02195ent IS
BEGIN
TESTING: PROCESS
type A_ARRAY is array (1 to 2) of CHARACTER;
variable I : INTEGER;
variable R : REAL;
variable B : BOOLEAN;
variable A : A_ARRAY;
BEGIN
R := I rem - I; -- Failure_here
-- SYNTAX ERROR: signed operator cannot follow multiplying operator.
assert FALSE
report "***FAILED TEST: c07s02b00x00p01n02i02195 - Signed operand cannot follow a mutiplying operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p01n02i02195arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2195.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p01n02i02195ent IS
END c07s02b00x00p01n02i02195ent;
ARCHITECTURE c07s02b00x00p01n02i02195arch OF c07s02b00x00p01n02i02195ent IS
BEGIN
TESTING: PROCESS
type A_ARRAY is array (1 to 2) of CHARACTER;
variable I : INTEGER;
variable R : REAL;
variable B : BOOLEAN;
variable A : A_ARRAY;
BEGIN
R := I rem - I; -- Failure_here
-- SYNTAX ERROR: signed operator cannot follow multiplying operator.
assert FALSE
report "***FAILED TEST: c07s02b00x00p01n02i02195 - Signed operand cannot follow a mutiplying operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p01n02i02195arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2195.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p01n02i02195ent IS
END c07s02b00x00p01n02i02195ent;
ARCHITECTURE c07s02b00x00p01n02i02195arch OF c07s02b00x00p01n02i02195ent IS
BEGIN
TESTING: PROCESS
type A_ARRAY is array (1 to 2) of CHARACTER;
variable I : INTEGER;
variable R : REAL;
variable B : BOOLEAN;
variable A : A_ARRAY;
BEGIN
R := I rem - I; -- Failure_here
-- SYNTAX ERROR: signed operator cannot follow multiplying operator.
assert FALSE
report "***FAILED TEST: c07s02b00x00p01n02i02195 - Signed operand cannot follow a mutiplying operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p01n02i02195arch;
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM, reads the executable from either "code.txt",
-- or for Altera "code[0-3].hex".
-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ADDRESS_WIDTH : natural := 13;
begin
generic_ram:
if memory_type /= "ALTERA_LPM" generate
begin
--Simulate a synchronous RAM
ram_proc: process(clk, enable, write_byte_enable,
address, data_write) --mem_write, mem_sel
variable mem_size : natural := 2 ** ADDRESS_WIDTH;
variable data : std_logic_vector(31 downto 0);
subtype word is std_logic_vector(data_write'length-1 downto 0);
type storage_array is
array(natural range 0 to mem_size/4 - 1) of word;
variable storage : storage_array;
variable index : natural := 0;
file load_file : text open read_mode is "code.txt";
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
--The following two lines had to be commented out for synthesis
readline(load_file, hex_file_line);
hread(hex_file_line, data);
storage(index) := data;
index := index + 1;
end loop;
end if;
if rising_edge(clk) then
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if enable = '1' then
if write_byte_enable(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
end if;
if write_byte_enable /= "0000" then
storage(index) := data;
end if;
end if;
data_read <= data;
end process;
end generate; --generic_ram
altera_ram:
if memory_type = "ALTERA_LPM" generate
signal byte_we : std_logic_vector(3 downto 0);
begin
byte_we <= write_byte_enable when enable = '1' else "0000";
lpm_ram_io_component0 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code0.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(31 downto 24),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => byte_we(3),
q => data_read(31 downto 24));
lpm_ram_io_component1 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code1.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(23 downto 16),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => byte_we(2),
q => data_read(23 downto 16));
lpm_ram_io_component2 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code2.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(15 downto 8),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => byte_we(1),
q => data_read(15 downto 8));
lpm_ram_io_component3 : lpm_ram_dq
GENERIC MAP (
intended_device_family => "UNUSED",
lpm_width => 8,
lpm_widthad => ADDRESS_WIDTH-2,
lpm_indata => "REGISTERED",
lpm_address_control => "REGISTERED",
lpm_outdata => "UNREGISTERED",
lpm_file => "code3.hex",
use_eab => "ON",
lpm_type => "LPM_RAM_DQ")
PORT MAP (
data => data_write(7 downto 0),
address => address(ADDRESS_WIDTH-1 downto 2),
inclock => clk,
we => byte_we(0),
q => data_read(7 downto 0));
end generate; --altera_ram
--For XILINX see ram_xilinx.vhd
end; --architecture logic
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2016 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! @brief Generic Wishbone GPIO Module.
--!
--! The following registers are defined:
--! |---------|---------------------------------------------------------------|
--! | Address | Description |
--! |---------|---------------------------------------------------------------|
--! | 0x00 | Input values, one bit per pin (read-only) |
--! | 0x04 | Output values, one bit per pin (read/write) |
--! | 0x08 | Direction register, one bit per pin. 0 is input, 1 is output. |
--! |---------|---------------------------------------------------------------|
--!
--! Writes to the output register for input pins are ignored.
entity pp_soc_gpio is
generic(
NUM_GPIOS : natural := 32
);
port(
clk : in std_logic;
reset : in std_logic;
-- GPIO interface:
gpio : inout std_logic_vector(NUM_GPIOS - 1 downto 0);
-- Wishbone interface:
wb_adr_in : in std_logic_vector(11 downto 0);
wb_dat_in : in std_logic_vector(31 downto 0);
wb_dat_out : out std_logic_vector(31 downto 0);
wb_cyc_in : in std_logic;
wb_stb_in : in std_logic;
wb_we_in : in std_logic;
wb_ack_out : out std_logic
);
end entity pp_soc_gpio;
architecture behaviour of pp_soc_gpio is
signal direction_register : std_logic_vector(NUM_GPIOS - 1 downto 0);
signal output_register : std_logic_vector(NUM_GPIOS - 1 downto 0);
signal input_register : std_logic_vector(NUM_GPIOS - 1 downto 0);
signal ack : std_logic := '0';
begin
assert NUM_GPIOS > 0 and NUM_GPIOS <= 32
report "Only a number between 1 and 32 (inclusive) GPIOs are supported!"
severity FAILURE;
io_setup: for i in 0 to NUM_GPIOS - 1 generate
gpio(i) <= 'Z' when direction_register(i) = '0' else output_register(i);
input_register(i) <= gpio(i) when direction_register(i) = '0' else '0';
end generate;
wb_ack_out <= ack and wb_cyc_in and wb_stb_in;
wishbone: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
direction_register <= (others => '0');
output_register <= (others => '0');
wb_dat_out <= (others => '0');
ack <= '0';
else
if wb_cyc_in = '1' and wb_stb_in = '1' and ack = '0' then
if wb_we_in = '1' then
case wb_adr_in is
when x"004" =>
output_register <= wb_dat_in(NUM_GPIOS - 1 downto 0);
when x"008" =>
direction_register <= wb_dat_in(NUM_GPIOS - 1 downto 0);
when others =>
end case;
ack <= '1';
else
case wb_adr_in is
when x"000" =>
wb_dat_out <= std_logic_vector(resize(unsigned(input_register), wb_dat_out'length));
when x"004" =>
wb_dat_out <= std_logic_vector(resize(unsigned(output_register), wb_dat_out'length));
when x"008" =>
wb_dat_out <= std_logic_vector(resize(unsigned(direction_register), wb_dat_out'length));
when others =>
end case;
ack <= '1';
end if;
elsif wb_stb_in = '0' then
ack <= '0';
end if;
end if;
end if;
end process wishbone;
end architecture behaviour;
|
entity IMAGE_STREAM_BUFFER_TEST_BENCH is
generic (
NAME : STRING := "test";
SCENARIO_FILE : STRING := "test.snr";
ELEMENT_SIZE : integer := 8*1024;
LINE_SIZE : integer := 0;
BANK_SIZE : integer := 0;
FINISH_ABORT : boolean := FALSE
);
end IMAGE_STREAM_BUFFER_TEST_BENCH;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
architecture MODEL of IMAGE_STREAM_BUFFER_TEST_BENCH is
begin
assert ELEMENT_SIZE > 0;
end MODEL;
-----------------------------------------------------------------------------------
-- ELEM_BITS=2bit, CHANNEL_SIZE=0, I.C=32, I.X=1, I.Y=1, O.C=32, O.X=3, O.Y=3 D_SIZE=8
-----------------------------------------------------------------------------------
entity issue448 is
generic (
NAME : STRING := "test_0_2_32x1x1_32x4x3x3_bug1";
SCENARIO_FILE : STRING := "test_0_2_32x1x1_32x4x3x3_bug1.snr";
BANK_SIZE : integer := 0;
LINE_SIZE : integer := 0;
FINISH_ABORT : boolean := FALSE
);
end issue448;
architecture MODEL of issue448 is
component IMAGE_STREAM_BUFFER_TEST_BENCH is
generic (
NAME : STRING := "test";
SCENARIO_FILE : STRING := "test.snr";
BANK_SIZE : integer := 0;
LINE_SIZE : integer := 0;
FINISH_ABORT : boolean := FALSE
);
end component;
begin
TB: IMAGE_STREAM_BUFFER_TEST_BENCH generic map (
NAME => NAME ,
SCENARIO_FILE => SCENARIO_FILE,
BANK_SIZE => BANK_SIZE ,
LINE_SIZE => LINE_SIZE ,
FINISH_ABORT => FINISH_ABORT
);
end MODEL;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11;
datawidth: integer := 8
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(datawidth-1 downto 0);
read : out std_logic_vector(datawidth-1 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(datawidth-1 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
begin
process is
-- code from book:
type natural_ptr is access natural;
variable count : natural_ptr;
-- end of code from book
begin
-- code from book:
count := new natural;
count.all := 10;
if count.all = 0 then
-- . . .
-- not in book
report "count.all = 0";
-- end not in book
end if;
-- end of code from book
if count.all /= 0 then
report "count.all /= 0";
end if;
-- code from book:
count := new natural'(10);
-- end of code from book
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
begin
process is
-- code from book:
type natural_ptr is access natural;
variable count : natural_ptr;
-- end of code from book
begin
-- code from book:
count := new natural;
count.all := 10;
if count.all = 0 then
-- . . .
-- not in book
report "count.all = 0";
-- end not in book
end if;
-- end of code from book
if count.all /= 0 then
report "count.all /= 0";
end if;
-- code from book:
count := new natural'(10);
-- end of code from book
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
begin
process is
-- code from book:
type natural_ptr is access natural;
variable count : natural_ptr;
-- end of code from book
begin
-- code from book:
count := new natural;
count.all := 10;
if count.all = 0 then
-- . . .
-- not in book
report "count.all = 0";
-- end not in book
end if;
-- end of code from book
if count.all /= 0 then
report "count.all /= 0";
end if;
-- code from book:
count := new natural'(10);
-- end of code from book
wait;
end process;
end architecture test;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_pullup_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END system_axi_gpio_pullup_0;
ARCHITECTURE system_axi_gpio_pullup_0_arch OF system_axi_gpio_pullup_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_pullup_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_pullup_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_pullup_0_arch : ARCHITECTURE IS "system_axi_gpio_pullup_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_pullup_0_arch: ARCHITECTURE IS "system_axi_gpio_pullup_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=2,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 2,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_pullup_0_arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Font Rom ASCII
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Output ASCII value bit by bit
-- ROM with Synchonous read
--
-- Notes:
-- Character ROM STATS:
-- 8x16 char font
-- 128 Characters
-- Size: 512x8 (2^11 x 8) bits
-- 16K bits = 1 BRAM
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FONT_ROM is
port( CLK: in std_logic;
ADDR: in std_logic_vector(10 downto 0);
DATA: out std_logic_vector(7 downto 0)
);
end FONT_ROM;
architecture arch of FONT_ROM is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition: 512x8
constant ROM: rom_type:=(
-- code x00 - Blank
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 - Smile Face
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 - Smile Face Invert
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 - Heart
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 - Diamond
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 - Cloves
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 - Spades
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 - Circle
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 - Circle Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 - Ring
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a - Ring Invert
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b - Male Symbol
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c - Female Symbol
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d - Single Music Note
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e - Double Music Note
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f - Star
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 - Arrow Head Right
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 - Arrow Head Left
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 - UP/DOWN Scroll
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 - Double Esclamation Mark
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 - Paragraph Block
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 - SS Symbol
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 - Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 - Scroll up/down bottom
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 - Scroll up
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 - Scroll Down
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a - Scroll Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b - Scroll Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c - Indent Block
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d - Scroll Left/Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e - Arrow Head Up
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f - Arrow Head Down
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 - Space
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 - Esclimation Mark
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 - Double Quotations
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 - Pound Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 - Dollar Sign
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 - Percent Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 - AND Sign
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 - Single Quotation
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 - Right Parentise
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a - Aserisk
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b - Plus
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c - Comma
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d - Minus Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e - Period
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f - Back Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30 - Zero
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31 - One
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32 - Two
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33 - Three
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34 - Four
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35 - Five
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36 - Six
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37 - Seven
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38 - Eight
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39 - Nine
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a - Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b - Semi-Colin
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c - Arrow Left
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d - Equal Sign
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e - Arrow Right
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f - Question Mark
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 - At Symbol
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41 - A
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42 - B
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43 - C
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44 - D
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45 - E
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46 - F
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47 - G
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48 - H
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49 - I
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a - J
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b - K
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c - L
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d - M
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e - N
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f - O
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50 - P
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x51 - Q
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52 - R
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53 - S
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54 - T
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55 - U
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56 - V
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57 - W
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58 - X
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59 - Y
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a - Z
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b - Left Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c - Foward Slash
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d - Right Bracket
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e - Carot Top
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f - Under Score
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60 - Single Quotation
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61 - a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62 - b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63 - c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64 - d
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65 - e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66 - f
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67 - g
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68 - h
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69 - i
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a - j
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b - k
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c - l
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d - m
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e - n
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f - o
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70 - p
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71 - q
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72 - r
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73 - s
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74 - t
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75 - u
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76 - v
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77 - w
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78 - x
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79 - y
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a - z
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b - Left Parentise
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c - Bracket Bar
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d - Right Parentise
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e - Fly Socer
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f - House
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (CLK)
begin
if (CLK'event and CLK = '1') then
addr_reg <= ADDR;
end if;
end process;
DATA <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect end_protected
|
--------------------------------------------------------------------------------
-- Entity: mem_io_synth
-- Date:2016-07-17
-- Author: Gideon
--
-- Description: Testbench for altera io for ddr
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_io_timing_tb is
generic (
g_in_delay : time := 0.3 ns );
end entity;
architecture arch of mem_io_timing_tb is
signal ref_clock : std_logic := '0';
signal ref_reset : std_logic;
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic;
signal SDRAM_CLK : std_logic := 'Z';
signal SDRAM_CLKn : std_logic := 'Z';
signal SDRAM_A : std_logic_vector(7 downto 0);
signal SDRAM_DQ : std_logic_vector(3 downto 0) := (others => 'Z');
signal SDRAM_DQS : std_logic;
signal write_data : std_logic_vector(15 downto 0);
signal read_data : std_logic_vector(15 downto 0);
signal do_read : std_logic;
signal mode : std_logic_vector(1 downto 0) := "01";
signal correct : std_logic;
signal measurement : std_logic_vector(11 downto 0);
signal latency : integer := 0;
signal rdata_valid : std_logic;
begin
ref_clock <= not ref_clock after 10 ns; -- 20 ns cycle time
ref_reset <= '1', '0' after 100 ns;
i_mut: entity work.mem_io_synth
port map (
ref_clock => ref_clock,
ref_reset => ref_reset,
sys_clock => sys_clock,
sys_reset => sys_reset,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS,
write_data => write_data,
read_data => read_data,
do_read => do_read,
rdata_valid=> rdata_valid,
mode => mode,
measurement => measurement
);
process(SDRAM_CLK)
variable delay : integer := -10;
begin
if rising_edge(SDRAM_CLK) then
if SDRAM_A(7 downto 4) = "0110" then
delay := 7;
end if;
end if;
delay := delay - 1;
case delay is
when 0 =>
SDRAM_DQ <= transport X"2" after g_in_delay;
when -1 =>
SDRAM_DQ <= transport X"3" after g_in_delay;
when -2 =>
SDRAM_DQ <= transport X"4" after g_in_delay;
when -3 =>
SDRAM_DQ <= transport X"5" after g_in_delay;
when others =>
SDRAM_DQ <= transport "ZZZZ" after g_in_delay;
end case;
end process;
process(sys_clock)
variable timer : integer := 0;
begin
if falling_edge(sys_clock) then
if do_read = '1' then
timer := 0;
else
timer := timer + 1;
end if;
if read_data = X"5432" then
correct <= '1';
latency <= timer;
else
correct <= '0';
end if;
end if;
end process;
end arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-a.vhd,v 1.1 2006/04/10 15:42:05 wig Exp $
-- $Date: 2006/04/10 15:42:05 $
-- $Log: inst_b_e-rtl-a.vhd,v $
-- Revision 1.1 2006/04/10 15:42:05 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_b_e
--
architecture rtl of inst_b_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_ba
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_bb
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_ba
inst_ba: ent_ba
;
-- End of Generated Instance Port Map for inst_ba
-- Generated Instance Port Map for inst_bb
inst_bb: ent_bb
;
-- End of Generated Instance Port Map for inst_bb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
entity generic_enabler is
generic(PERIOD:natural := 1000000 ); --1MHz
port(
clk: in std_logic;
rst: in std_logic;
ena_out: out std_logic
);
end;
architecture generic_enabler_arq of generic_enabler is
component generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end component;
begin
genericCounterMap: generic_counter generic map (32,PERIOD) --32 bits son suficientes para hasta 4 GHz
port map(
clk => clk,
rst => rst,
ena => '1',
carry_o => ena_out); --El count_dummy esta conectado siempre a tierra.
end;
|
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|
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13936)
`protect data_block
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc291.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p14n01i00291ent IS
END c03s01b03x00p14n01i00291ent;
ARCHITECTURE c03s01b03x00p14n01i00291arch OF c03s01b03x00p14n01i00291ent IS
type T is
range -2147483647 to 2147483647 -- No_failure_here
units
I ;
J = 2 I;
K = 2 J;
L = 10 K;
M = 1000 L;
end units;
BEGIN
TESTING: PROCESS
variable kk : T := 1 L;
BEGIN
assert NOT( kk = 20 J )
report "***PASSED TEST: c03s01b03x00p14n01i00291"
severity NOTE;
assert ( kk = 20 J )
report "***FAILED TEST: c03s01b03x00p14n01i00291 - The declaration of any physical type whose range is wholly contained within the bounds -2147483647 and +2147483647, inclusive."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p14n01i00291arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc291.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p14n01i00291ent IS
END c03s01b03x00p14n01i00291ent;
ARCHITECTURE c03s01b03x00p14n01i00291arch OF c03s01b03x00p14n01i00291ent IS
type T is
range -2147483647 to 2147483647 -- No_failure_here
units
I ;
J = 2 I;
K = 2 J;
L = 10 K;
M = 1000 L;
end units;
BEGIN
TESTING: PROCESS
variable kk : T := 1 L;
BEGIN
assert NOT( kk = 20 J )
report "***PASSED TEST: c03s01b03x00p14n01i00291"
severity NOTE;
assert ( kk = 20 J )
report "***FAILED TEST: c03s01b03x00p14n01i00291 - The declaration of any physical type whose range is wholly contained within the bounds -2147483647 and +2147483647, inclusive."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p14n01i00291arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc291.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p14n01i00291ent IS
END c03s01b03x00p14n01i00291ent;
ARCHITECTURE c03s01b03x00p14n01i00291arch OF c03s01b03x00p14n01i00291ent IS
type T is
range -2147483647 to 2147483647 -- No_failure_here
units
I ;
J = 2 I;
K = 2 J;
L = 10 K;
M = 1000 L;
end units;
BEGIN
TESTING: PROCESS
variable kk : T := 1 L;
BEGIN
assert NOT( kk = 20 J )
report "***PASSED TEST: c03s01b03x00p14n01i00291"
severity NOTE;
assert ( kk = 20 J )
report "***FAILED TEST: c03s01b03x00p14n01i00291 - The declaration of any physical type whose range is wholly contained within the bounds -2147483647 and +2147483647, inclusive."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p14n01i00291arch;
|
entity tb_dff06 is
end tb_dff06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff06 is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff06
port map (
q => dout,
d => din,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '0';
din <= x"7e";
pulse;
assert dout = x"7e" severity failure;
din <= x"38";
pulse;
assert dout = x"38" severity failure;
rst <= '1';
din <= x"af";
pulse;
assert dout = x"38" severity failure;
rst <= '0';
pulse;
assert dout = x"af" severity failure;
wait;
end process;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_get_offset is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of sample_iterator_get_offset is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal i_sample_read_reg_127 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_127_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_127_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_fu_92_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_reg_138 : STD_LOGIC_VECTOR (31 downto 0);
signal indices_stride_load_new_reg_143 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_81_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_6_fu_112_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_6_fu_112_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_fu_112_p2 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_6_cast_fu_118_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal tmp_6_fu_112_p00 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_6_fu_112_p10 : STD_LOGIC_VECTOR (23 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_sample_read_reg_127_pp0_it1 <= i_sample_read_reg_127;
ap_reg_ppstg_i_sample_read_reg_127_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_127_pp0_it1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_sample_read_reg_127 <= i_sample;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_load_new_reg_143 <= indices_datain(55 downto 48);
tmp_9_reg_138 <= tmp_9_fu_92_p1;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it2 , indices_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, indices_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return <= std_logic_vector(unsigned(tmp_6_cast_fu_118_p1) + unsigned(tmp_9_reg_138));
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
indices_address <= tmp_fu_81_p1(32 - 1 downto 0);
indices_dataout <= ap_const_lv56_0;
indices_req_din <= ap_const_logic_0;
-- indices_req_write assign process. --
indices_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_req_write <= ap_const_logic_1;
else
indices_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_rsp_read assign process. --
indices_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_rsp_read <= ap_const_logic_1;
else
indices_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_size <= ap_const_lv32_1;
tmp_6_cast_fu_118_p1 <= std_logic_vector(resize(unsigned(tmp_6_fu_112_p2),32));
tmp_6_fu_112_p0 <= tmp_6_fu_112_p00(16 - 1 downto 0);
tmp_6_fu_112_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_127_pp0_it2),24));
tmp_6_fu_112_p1 <= tmp_6_fu_112_p10(8 - 1 downto 0);
tmp_6_fu_112_p10 <= std_logic_vector(resize(unsigned(indices_stride_load_new_reg_143),24));
tmp_6_fu_112_p2 <= std_logic_vector(resize(unsigned(tmp_6_fu_112_p0) * unsigned(tmp_6_fu_112_p1), 24));
tmp_9_fu_92_p1 <= indices_datain(32 - 1 downto 0);
tmp_fu_81_p1 <= std_logic_vector(resize(unsigned(i_index),64));
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_get_offset is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_req_din : OUT STD_LOGIC;
indices_req_full_n : IN STD_LOGIC;
indices_req_write : OUT STD_LOGIC;
indices_rsp_empty_n : IN STD_LOGIC;
indices_rsp_read : OUT STD_LOGIC;
indices_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_datain : IN STD_LOGIC_VECTOR (55 downto 0);
indices_dataout : OUT STD_LOGIC_VECTOR (55 downto 0);
indices_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of sample_iterator_get_offset is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal i_sample_read_reg_127 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_127_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_127_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_fu_92_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_reg_138 : STD_LOGIC_VECTOR (31 downto 0);
signal indices_stride_load_new_reg_143 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_81_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_6_fu_112_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_6_fu_112_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_fu_112_p2 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_6_cast_fu_118_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal tmp_6_fu_112_p00 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_6_fu_112_p10 : STD_LOGIC_VECTOR (23 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_sample_read_reg_127_pp0_it1 <= i_sample_read_reg_127;
ap_reg_ppstg_i_sample_read_reg_127_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_127_pp0_it1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_sample_read_reg_127 <= i_sample;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_load_new_reg_143 <= indices_datain(55 downto 48);
tmp_9_reg_138 <= tmp_9_fu_92_p1;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it2 , indices_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, indices_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return <= std_logic_vector(unsigned(tmp_6_cast_fu_118_p1) + unsigned(tmp_9_reg_138));
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
indices_address <= tmp_fu_81_p1(32 - 1 downto 0);
indices_dataout <= ap_const_lv56_0;
indices_req_din <= ap_const_logic_0;
-- indices_req_write assign process. --
indices_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_req_write <= ap_const_logic_1;
else
indices_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_rsp_read assign process. --
indices_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, indices_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (indices_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_rsp_read <= ap_const_logic_1;
else
indices_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_size <= ap_const_lv32_1;
tmp_6_cast_fu_118_p1 <= std_logic_vector(resize(unsigned(tmp_6_fu_112_p2),32));
tmp_6_fu_112_p0 <= tmp_6_fu_112_p00(16 - 1 downto 0);
tmp_6_fu_112_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_127_pp0_it2),24));
tmp_6_fu_112_p1 <= tmp_6_fu_112_p10(8 - 1 downto 0);
tmp_6_fu_112_p10 <= std_logic_vector(resize(unsigned(indices_stride_load_new_reg_143),24));
tmp_6_fu_112_p2 <= std_logic_vector(resize(unsigned(tmp_6_fu_112_p0) * unsigned(tmp_6_fu_112_p1), 24));
tmp_9_fu_92_p1 <= indices_datain(32 - 1 downto 0);
tmp_fu_81_p1 <= std_logic_vector(resize(unsigned(i_index),64));
end behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : WildCard Package (package declaration)
--
-- File name : wild.vhd
--
-- Purpose : WildCard Package
--
-- Library : gaisler
--
-- Authors : Mr Sandi Alexander Habinc
-- Gaisler Research
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.1 SH 1 Jan 2008 New version
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library grlib;
use grlib.amba.all;
package Wild is
-----------------------------------------------------------------------------
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _DS : Data Strobe
-- _WR : Write Select
-- _CS : Chip Select
-- _OE : Output Enable
-- _n : Active low signals (must be last part of name)
--
-- Name Width Dir* Description
-- ==================== ===== ==== =====================================
-- Addr_Data 32 I Shared address/data bus input
-- AS_n 1 I Address strobe
-- DS_n 1 I Data strobe
-- WR_n 1 I Write select
-- CS_n 1 I PE chip select
-- Reg_n 1 I Register mode select
-- Ack_n 1 O Acknowledge strobe
-- Addr_Data 32 O Shared address/data bus output
-- Addr_Data_OE_n 1 O Address/data bus output enable
-- Int_Req_n 1 O Interrupt request
-- DMA_0_Data_OK_n 1 O DMA channel 0 data OK flag
-- DMA_0_Burst_OK_n 1 O DMA channel 0 burst OK flag
-- DMA_1_Data_OK_n 1 O DMA channel 1 data OK flag
-- DMA_1_Burst_OK_n 1 O DMA channel 1 burst OK flag
-- Reg_Data_OK_n 1 O Register space data OK flag
-- Reg_Burst_OK_n 1 O Register space burst OK flag
-- Force_K_Clk_n 1 O Forces K_Clk to run when active
-----------------------------------------------------------------------------
type LAD_In_Type is record
Addr_Data: Std_Logic_Vector(31 downto 0); -- Shared address/data bus
AS_n: Std_Logic; -- Address strobe
DS_n: Std_Logic; -- Data strobe
WR_n: Std_Logic; -- Write select
CS_n: Std_Logic; -- Chip select
Reg_n: Std_Logic; -- Register select
end record;
type LAD_Out_Type is record
Addr_Data: Std_Logic_Vector(31 downto 0); -- Shared address/data bus output
Addr_Data_OE_n: Std_Logic_Vector(31 downto 0); -- Address/data bus output enable
Ack_n: Std_Logic; -- Acknowledge strobe
Int_Req_n: Std_Logic; -- Interrupt request
DMA_0_Data_OK_n: Std_Logic; -- DMA chan 0 data OK flag
DMA_0_Burst_OK: Std_Logic; -- DMA chan 0 burst OK flag
DMA_1_Data_OK_n: Std_Logic; -- DMA chan 1 data OK flag
DMA_1_Burst_OK: Std_Logic; -- DMA chan 1 burst OK flag
Reg_Data_OK_n: Std_Logic; -- Reg space data OK flag
Reg_Burst_OK: Std_Logic; -- Reg space burst OK flag
Force_K_Clk_n: Std_Logic; -- K_Clk forced-run select
Reserved: Std_Logic; -- Reserved for future use
end record;
component Wild2AHB is
generic (
hindex: in Integer := 0;
burst: in Integer := 0;
syncrst: in Integer := 0);
port (
rstkn: in Std_ULogic;
clkk: in Std_ULogic;
rstfn: in Std_ULogic;
clkf: in Std_ULogic;
ahbmi: in AHB_Mst_In_Type;
ahbmo: out AHB_Mst_Out_Type;
ladi: in LAD_In_Type;
lado: out LAD_Out_Type);
end component;
end package Wild; --==========================================================--
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : WildCard Package (package declaration)
--
-- File name : wild.vhd
--
-- Purpose : WildCard Package
--
-- Library : gaisler
--
-- Authors : Mr Sandi Alexander Habinc
-- Gaisler Research
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.1 SH 1 Jan 2008 New version
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library grlib;
use grlib.amba.all;
package Wild is
-----------------------------------------------------------------------------
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _DS : Data Strobe
-- _WR : Write Select
-- _CS : Chip Select
-- _OE : Output Enable
-- _n : Active low signals (must be last part of name)
--
-- Name Width Dir* Description
-- ==================== ===== ==== =====================================
-- Addr_Data 32 I Shared address/data bus input
-- AS_n 1 I Address strobe
-- DS_n 1 I Data strobe
-- WR_n 1 I Write select
-- CS_n 1 I PE chip select
-- Reg_n 1 I Register mode select
-- Ack_n 1 O Acknowledge strobe
-- Addr_Data 32 O Shared address/data bus output
-- Addr_Data_OE_n 1 O Address/data bus output enable
-- Int_Req_n 1 O Interrupt request
-- DMA_0_Data_OK_n 1 O DMA channel 0 data OK flag
-- DMA_0_Burst_OK_n 1 O DMA channel 0 burst OK flag
-- DMA_1_Data_OK_n 1 O DMA channel 1 data OK flag
-- DMA_1_Burst_OK_n 1 O DMA channel 1 burst OK flag
-- Reg_Data_OK_n 1 O Register space data OK flag
-- Reg_Burst_OK_n 1 O Register space burst OK flag
-- Force_K_Clk_n 1 O Forces K_Clk to run when active
-----------------------------------------------------------------------------
type LAD_In_Type is record
Addr_Data: Std_Logic_Vector(31 downto 0); -- Shared address/data bus
AS_n: Std_Logic; -- Address strobe
DS_n: Std_Logic; -- Data strobe
WR_n: Std_Logic; -- Write select
CS_n: Std_Logic; -- Chip select
Reg_n: Std_Logic; -- Register select
end record;
type LAD_Out_Type is record
Addr_Data: Std_Logic_Vector(31 downto 0); -- Shared address/data bus output
Addr_Data_OE_n: Std_Logic_Vector(31 downto 0); -- Address/data bus output enable
Ack_n: Std_Logic; -- Acknowledge strobe
Int_Req_n: Std_Logic; -- Interrupt request
DMA_0_Data_OK_n: Std_Logic; -- DMA chan 0 data OK flag
DMA_0_Burst_OK: Std_Logic; -- DMA chan 0 burst OK flag
DMA_1_Data_OK_n: Std_Logic; -- DMA chan 1 data OK flag
DMA_1_Burst_OK: Std_Logic; -- DMA chan 1 burst OK flag
Reg_Data_OK_n: Std_Logic; -- Reg space data OK flag
Reg_Burst_OK: Std_Logic; -- Reg space burst OK flag
Force_K_Clk_n: Std_Logic; -- K_Clk forced-run select
Reserved: Std_Logic; -- Reserved for future use
end record;
component Wild2AHB is
generic (
hindex: in Integer := 0;
burst: in Integer := 0;
syncrst: in Integer := 0);
port (
rstkn: in Std_ULogic;
clkk: in Std_ULogic;
rstfn: in Std_ULogic;
clkf: in Std_ULogic;
ahbmi: in AHB_Mst_In_Type;
ahbmo: out AHB_Mst_Out_Type;
ladi: in LAD_In_Type;
lado: out LAD_Out_Type);
end component;
end package Wild; --==========================================================--
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/Complex3Multiply_block9.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block9
-- Source Path: hdl_ofdm_tx/ifft/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block9 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din1_re_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din1_im_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din1_vld_dly3 : IN std_logic;
twdl_3_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_15_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_15_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin1_vld : OUT std_logic
);
END Complex3Multiply_block9;
ARCHITECTURE rtl OF Complex3Multiply_block9 IS
-- Signals
SIGNAL din1_re_dly3_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din_re_reg : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly3_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din_im_reg : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL adder_add_cast : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL adder_add_cast_1 : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL din_sum : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL twdl_3_15_re_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_re_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_15_im_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_im_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL adder_add_cast_2 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL adder_add_cast_3 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL twdl_sum : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(18 DOWNTO 0) := to_signed(16#00000#, 19); -- sfix19
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(18 DOWNTO 0) := to_signed(16#00000#, 19); -- sfix19
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(19 DOWNTO 0) := to_signed(16#00000#, 20); -- sfix20
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(34 DOWNTO 0) := to_signed(0, 35); -- sfix35
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(34 DOWNTO 0) := to_signed(0, 35); -- sfix35
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(36 DOWNTO 0) := to_signed(0, 37); -- sfix37
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(15 DOWNTO 0) := to_signed(16#0000#, 16); -- sfix16
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(15 DOWNTO 0) := to_signed(16#0000#, 16); -- sfix16
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(16 DOWNTO 0) := to_signed(16#00000#, 17); -- sfix17
SIGNAL prodOfRe : signed(34 DOWNTO 0) := to_signed(0, 35); -- sfix35_En27
SIGNAL prodOfIm : signed(34 DOWNTO 0) := to_signed(0, 35); -- sfix35_En27
SIGNAL prodOfSum : signed(36 DOWNTO 0) := to_signed(0, 37); -- sfix37_En27
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Add_multRes_re_reg1 : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_multRes_re_reg2 : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_multRes_im_reg : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Add_tmpResult_reg_next : signed(36 DOWNTO 0); -- sfix37_En27
SIGNAL Complex3Add_multRes_re_reg1_next : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_multRes_re_reg2_next : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_multRes_im_reg_next : signed(37 DOWNTO 0); -- sfix38_En27
SIGNAL Complex3Add_sub_cast : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_sub_cast_1 : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_sub_cast_2 : signed(37 DOWNTO 0); -- sfix38_En27
SIGNAL Complex3Add_sub_cast_3 : signed(37 DOWNTO 0); -- sfix38_En27
SIGNAL Complex3Add_add_cast : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_add_cast_1 : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_add_temp : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL multResFP_re : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL multResFP_im : signed(37 DOWNTO 0); -- sfix38_En27
SIGNAL twdlXdin_15_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_15_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
BEGIN
din1_re_dly3_signed <= signed(din1_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 19);
ELSE
din_re_reg <= din1_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din1_im_dly3_signed <= signed(din1_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 19);
ELSE
din_im_reg <= din1_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
adder_add_cast <= resize(din_re_reg, 20);
adder_add_cast_1 <= resize(din_im_reg, 20);
din_sum <= adder_add_cast + adder_add_cast_1;
twdl_3_15_re_signed <= signed(twdl_3_15_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSE
twdl_re_reg <= twdl_3_15_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_15_im_signed <= signed(twdl_3_15_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSE
twdl_im_reg <= twdl_3_15_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast_2 <= resize(twdl_re_reg, 17);
adder_add_cast_3 <= resize(twdl_im_reg, 17);
twdl_sum <= adder_add_cast_2 + adder_add_cast_3;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly1 <= din1_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 37);
Complex3Add_tmpResult_reg <= to_signed(0, 37);
Complex3Add_multRes_re_reg1 <= to_signed(0, 36);
Complex3Add_multRes_re_reg2 <= to_signed(0, 36);
Complex3Add_multRes_im_reg <= to_signed(0, 38);
Complex3Add_prod_vld_reg1 <= '0';
twdlXdin1_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prodOfSum_reg <= prodOfSum;
twdlXdin1_vld <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1 <= prod_vld;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
Complex3Add_sub_cast <= resize(prodOfRe, 36);
Complex3Add_sub_cast_1 <= resize(prodOfIm, 36);
Complex3Add_multRes_re_reg1_next <= Complex3Add_sub_cast - Complex3Add_sub_cast_1;
Complex3Add_sub_cast_2 <= resize(Complex3Add_prodOfSum_reg, 38);
Complex3Add_sub_cast_3 <= resize(Complex3Add_tmpResult_reg, 38);
Complex3Add_multRes_im_reg_next <= Complex3Add_sub_cast_2 - Complex3Add_sub_cast_3;
Complex3Add_add_cast <= resize(prodOfRe, 36);
Complex3Add_add_cast_1 <= resize(prodOfIm, 36);
Complex3Add_add_temp <= Complex3Add_add_cast + Complex3Add_add_cast_1;
Complex3Add_tmpResult_reg_next <= resize(Complex3Add_add_temp, 37);
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin_15_re_tmp <= multResFP_re(32 DOWNTO 14);
twdlXdin_15_re <= std_logic_vector(twdlXdin_15_re_tmp);
twdlXdin_15_im_tmp <= multResFP_im(32 DOWNTO 14);
twdlXdin_15_im <= std_logic_vector(twdlXdin_15_im_tmp);
END rtl;
|
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body fifo_pkg;
|
----------------------------------------------------------------------------------
-- Luke Hsiao
-- ECEN 320 Lab 12
-- Generates a single clk pulse on the rising edge of a button
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity btnpulse is
Port ( btn : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
btnpulse : out STD_LOGIC);
end btnpulse;
architecture state_arch of btnpulse is
type states is (zero, riseEdge, one);
signal state_reg, state_next: states;
begin
process(clk, reset)
begin
if reset='1' then
state_reg <= zero;
elsif clk'event and clk='1' then
state_reg <= state_next;
end if;
end process;
--Next State and Output Logic
process (btn, state_reg)
begin
--Defaults
btnpulse <= '0';
state_next <= state_reg;
case state_reg is
when zero =>
if (btn='0') then
state_next <= zero;
else
state_next <= riseEdge;
end if;
when riseEdge =>
btnpulse <= '1';
state_next <= one;
when one =>
if btn='1' then
state_next <= one;
else
state_next <= zero;
end if;
end case;
end process;
end state_arch;
|
-- NEED RESULT: ARCH00576: Can declare entities with same name as entities declared in a use'd pkg passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00576
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.4 (1)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00574_576
-- PKG00574_576/BODY
-- ENT00576_Test_Bench(ARCH00576_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
package PKG00574_576 is
type T1 is (one, two, three, four) ;
type T2 is (one, two, three, four) ;
type T3 is (one, two, three, four) ;
type T4 is (one, two, three, four) ;
subtype S1 is INTEGER;
subtype S2 is INTEGER;
subtype S3 is INTEGER;
subtype S4 is INTEGER;
function F1 return REAL ;
function F2 return REAL ;
function F3 return REAL ;
function F4 return REAL ;
end PKG00574_576 ;
package body PKG00574_576 is
function F1 return REAL is begin
return 0.0; end;
function F2 return REAL is begin
return 0.0; end;
function F3 return REAL is begin
return 0.0; end;
function F4 return REAL is begin
return 0.0; end;
end PKG00574_576 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00576_Test_Bench is
end ENT00576_Test_Bench ;
architecture ARCH00576_Test_Bench of ENT00576_Test_Bench is
use WORK.PKG00574_576; use PKG00574_576.all;
begin
L_X_1 : block
type T1 is record -- should be able to define new type T1
TE : BOOLEAN;
end record;
subtype T2 is REAL range 0.0 to 256.0; -- ditto for subtype called T2
attribute T3 : PKG00574_576.T3 ; -- ditto for attribute calle
signal T4 : PKG00574_576.T1; -- ditto for object called T
type S1 is record -- should be able to define new type S1
SE : BOOLEAN;
end record;
subtype S2 is REAL range 0.0 to 256.0; -- ditto for subtype called S2
attribute S3 : PKG00574_576.T3 ; -- ditto for attribute calle
signal S4 : PKG00574_576.T1; -- ditto for object called
type F1 is record -- should be able to define new type F1
FE : BOOLEAN;
end record;
subtype F2 is REAL range 0.0 to 256.0; -- ditto for subtype called F2
attribute F3 : PKG00574_576.T3 ; -- ditto for attribute calle
signal F4 : PKG00574_576.T1; -- ditto for object called F
begin
process
variable T1 : PKG00574_576.T1; -- ditto for object called
variable F1 : PKG00574_576.T1; -- ditto for object called
variable S1 : PKG00574_576.T1; -- ditto for object called
begin
test_report ( "ARCH00576" ,
"Can declare entities with same name as entities "&
"declared in a use'd pkg" ,
True ) ;
wait ;
end process;
end block;
end ARCH00576_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc796.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00796ent IS
begin
wait 3 ns; -- illegal location for wait
END c01s01b03x00p03n01i00796ent;
ARCHITECTURE c01s01b03x00p03n01i00796arch OF c01s01b03x00p03n01i00796ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00796 - Wait statement can not appear in entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00796arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc796.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00796ent IS
begin
wait 3 ns; -- illegal location for wait
END c01s01b03x00p03n01i00796ent;
ARCHITECTURE c01s01b03x00p03n01i00796arch OF c01s01b03x00p03n01i00796ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00796 - Wait statement can not appear in entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00796arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc796.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00796ent IS
begin
wait 3 ns; -- illegal location for wait
END c01s01b03x00p03n01i00796ent;
ARCHITECTURE c01s01b03x00p03n01i00796arch OF c01s01b03x00p03n01i00796ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00796 - Wait statement can not appear in entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00796arch;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_b
--
-- Generated
-- by: wig
-- on: Thu Mar 16 07:48:49 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro -nodelta ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-conf-c.vhd,v 1.1 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: ent_b-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.77 2006/03/14 08:10:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- adding lot's of testcases
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
ADD_MY_OWN: overloading my own macro -- adding my own macro
MY_TICK_IN_TEST: has a ' inside -- has a ' inside
MY_TICK_FIRST_TEST: ' start with tick -- ' start with tick
MY_TICK_LAST_TEST: ends with ' -- ends with '
MY_DQUOTE_IN_TEST: has a " inside -- has a " inside
MY_DQUOTE_FIRST_TEST: " start with tick -- " start with tick
MY_DQUOTE_LAST_TEST: ends with " -- ends with "
MY_DQUOTE_TICK_TEST: has a ' and a " here ' " more -- has a ' and a " here ' " more
MY_SOME_SEPS: special " $ & ' \n and more -- special " $ & ' \n and more
-- END
--
-- Start of Generated Configuration ent_b_rtl_conf / ent_b
--
configuration ent_b_rtl_conf of ent_b is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG for inst_ba : ent_ba
-- __I_NO_CONFIG use configuration work.NO_CONFIG;
-- __I_NO_CONFIG end for;
for inst_bb : ent_bb
use configuration work.ent_bb_rtl_conf;
end for;
end for;
end ent_b_rtl_conf;
--
-- End of Generated Configuration ent_b_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/BPF/zero_filling1"
entity zero_filling1_entity_d0ac9899b1 is
port (
in1: in std_logic_vector(15 downto 0);
out1: out std_logic_vector(23 downto 0)
);
end zero_filling1_entity_d0ac9899b1;
architecture structural of zero_filling1_entity_d0ac9899b1 is
signal concat_y_net: std_logic_vector(23 downto 0);
signal constant_op_net: std_logic_vector(7 downto 0);
signal register1_q_net_x0: std_logic_vector(15 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(7 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net: std_logic_vector(15 downto 0);
begin
register1_q_net_x0 <= in1;
out1 <= reinterpret2_output_port_net_x0;
concat: entity work.concat_cd3162dc0d
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => reinterpret_output_port_net,
in1 => reinterpret1_output_port_net,
y => concat_y_net
);
constant_x0: entity work.constant_91ef1678ca
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
reinterpret: entity work.reinterpret_7025463ea8
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register1_q_net_x0,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_f21e7f2ddf
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => constant_op_net,
output_port => reinterpret1_output_port_net
);
reinterpret2: entity work.reinterpret_4bf1ad328a
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => concat_y_net,
output_port => reinterpret2_output_port_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/BPF"
entity bpf_entity_d31c4af409 is
port (
din_ch0: in std_logic_vector(15 downto 0);
din_ch1: in std_logic_vector(15 downto 0);
din_ch2: in std_logic_vector(15 downto 0);
din_ch3: in std_logic_vector(15 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0);
dout_ch2: out std_logic_vector(23 downto 0);
dout_ch3: out std_logic_vector(23 downto 0)
);
end bpf_entity_d31c4af409;
architecture structural of bpf_entity_d31c4af409 is
signal register1_q_net_x1: std_logic_vector(15 downto 0);
signal register2_q_net_x1: std_logic_vector(15 downto 0);
signal register3_q_net_x1: std_logic_vector(15 downto 0);
signal register_q_net_x1: std_logic_vector(15 downto 0);
signal reinterpret2_output_port_net_x4: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x5: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x6: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x7: std_logic_vector(23 downto 0);
begin
register_q_net_x1 <= din_ch0;
register1_q_net_x1 <= din_ch1;
register2_q_net_x1 <= din_ch2;
register3_q_net_x1 <= din_ch3;
dout_ch0 <= reinterpret2_output_port_net_x7;
dout_ch1 <= reinterpret2_output_port_net_x4;
dout_ch2 <= reinterpret2_output_port_net_x5;
dout_ch3 <= reinterpret2_output_port_net_x6;
zero_filling1_d0ac9899b1: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register1_q_net_x1,
out1 => reinterpret2_output_port_net_x4
);
zero_filling2_d7e27e9bae: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register2_q_net_x1,
out1 => reinterpret2_output_port_net_x5
);
zero_filling3_1ae3b6c91e: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register3_q_net_x1,
out1 => reinterpret2_output_port_net_x6
);
zero_filling4_6d7b2d0c57: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register_q_net_x1,
out1 => reinterpret2_output_port_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/DDS_sub/TDM_dds_ch01_cosine"
entity tdm_dds_ch01_cosine_entity_4b8bfc9243 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
rst: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end tdm_dds_ch01_cosine_entity_4b8bfc9243;
architecture structural of tdm_dds_ch01_cosine_entity_4b8bfc9243 is
signal black_box_cos_o_net_x0: std_logic_vector(23 downto 0);
signal ce_1_sg_x0: std_logic;
signal ce_2_sg_x0: std_logic;
signal ce_logic_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal clk_2_sg_x0: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant11_op_net_x0: std_logic;
signal mux_sel1_op_net: std_logic;
signal mux_y_net: std_logic_vector(23 downto 0);
signal register2_q_net: std_logic_vector(23 downto 0);
signal register3_q_net: std_logic_vector(23 downto 0);
signal register4_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x0 <= ce_1;
ce_2_sg_x0 <= ce_2;
ce_logic_1_sg_x0 <= ce_logic_1;
clk_1_sg_x0 <= clk_1;
clk_2_sg_x0 <= clk_2;
black_box_cos_o_net_x0 <= din_ch0;
constant11_op_net_x0 <= rst;
dout <= register_q_net_x0;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_1_sg_x0,
clk => clk_1_sg_x0,
d => register2_q_net,
q(0) => clock_enable_probe_q_net
);
mux: entity work.mux_a2121d82da
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => register2_q_net,
d1 => register3_q_net,
sel(0) => register4_q_net,
y => mux_y_net
);
mux_sel1: entity work.counter_41314d726b
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant11_op_net_x0,
op(0) => mux_sel1_op_net
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => up_sample_ch0_q_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => up_sample_ch1_q_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => mux_sel1_op_net,
en => "1",
rst => "0",
q(0) => register4_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => mux_y_net,
en => "1",
rst => "0",
q => register_q_net_x0
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => black_box_cos_o_net_x0,
dest_ce => ce_1_sg_x0,
dest_clk => clk_1_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x0,
src_clk => clk_2_sg_x0,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => black_box_cos_o_net_x0,
dest_ce => ce_1_sg_x0,
dest_clk => clk_1_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x0,
src_clk => clk_2_sg_x0,
src_clr => '0',
q => up_sample_ch1_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/DDS_sub"
entity dds_sub_entity_a4b6b880f6 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_01_cosine: out std_logic_vector(23 downto 0);
dds_01_sine: out std_logic_vector(23 downto 0);
dds_23_cosine: out std_logic_vector(23 downto 0);
dds_23_sine: out std_logic_vector(23 downto 0)
);
end dds_sub_entity_a4b6b880f6;
architecture structural of dds_sub_entity_a4b6b880f6 is
signal black_box_cos_o_net_x1: std_logic_vector(23 downto 0);
signal black_box_sin_o_net_x1: std_logic_vector(23 downto 0);
signal ce_1_sg_x4: std_logic;
signal ce_2_sg_x4: std_logic;
signal ce_logic_1_sg_x4: std_logic;
signal clk_1_sg_x4: std_logic;
signal clk_2_sg_x4: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant16_op_net_x0: std_logic;
signal constant17_op_net_x0: std_logic;
signal constant3_op_net: std_logic;
signal constant7_op_net_x0: std_logic;
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(23 downto 0);
signal register_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(23 downto 0);
begin
ce_1_sg_x4 <= ce_1;
ce_2_sg_x4 <= ce_2;
ce_logic_1_sg_x4 <= ce_logic_1;
clk_1_sg_x4 <= clk_1;
clk_2_sg_x4 <= clk_2;
dds_01_cosine <= register_q_net_x4;
dds_01_sine <= register_q_net_x5;
dds_23_cosine <= register_q_net_x6;
dds_23_sine <= register_q_net_x7;
black_box: entity work.fixed_dds
generic map (
g_cos_file => "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_cos.ram",
g_dither => false,
g_number_of_points => 148,
g_output_width => 24,
g_sin_file => "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_sin.ram"
)
port map (
ce_i => ce_2_sg_x4,
clk_i => clk_2_sg_x4,
rst_n_i => constant3_op_net,
cos_o => black_box_cos_o_net_x1,
sin_o => black_box_sin_o_net_x1
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
constant16: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant16_op_net_x0
);
constant17: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant17_op_net_x0
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net
);
constant7: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant7_op_net_x0
);
tdm_dds_ch01_cosine_4b8bfc9243: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_cos_o_net_x1,
rst => constant11_op_net_x0,
dout => register_q_net_x4
);
tdm_dds_ch01_sine_1129eb9762: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_sin_o_net_x1,
rst => constant7_op_net_x0,
dout => register_q_net_x5
);
tdm_dds_ch23_cosine_398d5cee32: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_cos_o_net_x1,
rst => constant16_op_net_x0,
dout => register_q_net_x6
);
tdm_dds_ch23_sine_782ff6a42a: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_sin_o_net_x1,
rst => constant17_op_net_x0,
dout => register_q_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/TDDM_fofb_amp_4ch/TDDM_fofb_amp0"
entity tddm_fofb_amp0_entity_fd74c6ad6e is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_fofb_amp0_entity_fd74c6ad6e;
architecture structural of tddm_fofb_amp0_entity_fd74c6ad6e is
signal assert2_dout_net_x0: std_logic_vector(23 downto 0);
signal assert3_dout_net_x0: std_logic;
signal ce_1120_sg_x0: std_logic;
signal ce_2240_sg_x0: std_logic;
signal clk_1120_sg_x0: std_logic;
signal clk_2240_sg_x0: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1120_sg_x0 <= ce_1120;
ce_2240_sg_x0 <= ce_2240;
assert3_dout_net_x0 <= ch_in;
clk_1120_sg_x0 <= clk_1120;
clk_2240_sg_x0 <= clk_2240;
assert2_dout_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2240_sg_x0,
dest_clk => clk_2240_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x0,
src_clk => clk_1120_sg_x0,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2240_sg_x0,
dest_clk => clk_2240_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x0,
src_clk => clk_1120_sg_x0,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
d => assert2_dout_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
d => assert2_dout_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x0,
b(0) => constant_op_net,
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x0,
b(0) => constant1_op_net,
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/TDDM_fofb_amp_4ch"
entity tddm_fofb_amp_4ch_entity_2cc521a83f is
port (
amp_in0: in std_logic_vector(23 downto 0);
amp_in1: in std_logic_vector(23 downto 0);
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0)
);
end tddm_fofb_amp_4ch_entity_2cc521a83f;
architecture structural of tddm_fofb_amp_4ch_entity_2cc521a83f is
signal assert2_dout_net_x2: std_logic_vector(23 downto 0);
signal assert2_dout_net_x3: std_logic_vector(23 downto 0);
signal assert3_dout_net_x2: std_logic;
signal assert3_dout_net_x3: std_logic;
signal ce_1120_sg_x2: std_logic;
signal ce_2240_sg_x2: std_logic;
signal clk_1120_sg_x2: std_logic;
signal clk_2240_sg_x2: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
begin
assert2_dout_net_x2 <= amp_in0;
assert2_dout_net_x3 <= amp_in1;
ce_1120_sg_x2 <= ce_1120;
ce_2240_sg_x2 <= ce_2240;
assert3_dout_net_x2 <= ch_in0;
assert3_dout_net_x3 <= ch_in1;
clk_1120_sg_x2 <= clk_1120;
clk_2240_sg_x2 <= clk_2240;
amp_out0 <= down_sample2_q_net_x2;
amp_out1 <= down_sample1_q_net_x2;
amp_out2 <= down_sample2_q_net_x3;
amp_out3 <= down_sample1_q_net_x3;
tddm_fofb_amp0_fd74c6ad6e: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x2,
ce_2240 => ce_2240_sg_x2,
ch_in => assert3_dout_net_x2,
clk_1120 => clk_1120_sg_x2,
clk_2240 => clk_2240_sg_x2,
din => assert2_dout_net_x2,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_fofb_amp1_61cbc8ec65: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x2,
ce_2240 => ce_2240_sg_x2,
ch_in => assert3_dout_net_x3,
clk_1120 => clk_1120_sg_x2,
clk_2240 => clk_2240_sg_x2,
din => assert2_dout_net_x3,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC/TDDM_tbt_cordic0/TDDM_tbt_cordic1"
entity tddm_tbt_cordic1_entity_b60a69fd9b is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic1_entity_b60a69fd9b;
architecture structural of tddm_tbt_cordic1_entity_b60a69fd9b is
signal assert1_dout_net_x0: std_logic_vector(23 downto 0);
signal assert3_dout_net_x4: std_logic;
signal ce_1120_sg_x4: std_logic;
signal ce_2240_sg_x4: std_logic;
signal clk_1120_sg_x4: std_logic;
signal clk_2240_sg_x4: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1120_sg_x4 <= ce_1120;
ce_2240_sg_x4 <= ce_2240;
assert3_dout_net_x4 <= ch_in;
clk_1120_sg_x4 <= clk_1120;
clk_2240_sg_x4 <= clk_2240;
assert1_dout_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2240_sg_x4,
dest_clk => clk_2240_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x4,
src_clk => clk_1120_sg_x4,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2240_sg_x4,
dest_clk => clk_2240_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x4,
src_clk => clk_1120_sg_x4,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
d => assert1_dout_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
d => assert1_dout_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x4,
b(0) => constant_op_net,
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x4,
b(0) => constant1_op_net,
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC/TDDM_tbt_cordic0"
entity tddm_tbt_cordic0_entity_38de3613fe is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
fofb_cordic_ch_in: in std_logic;
fofb_cordic_din: in std_logic_vector(23 downto 0);
fofb_cordic_pin: in std_logic_vector(23 downto 0);
fofb_cordic_data0_out: out std_logic_vector(23 downto 0);
fofb_cordic_data1_out: out std_logic_vector(23 downto 0);
fofb_cordic_phase0_out: out std_logic_vector(23 downto 0);
fofb_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic0_entity_38de3613fe;
architecture structural of tddm_tbt_cordic0_entity_38de3613fe is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x4: std_logic_vector(23 downto 0);
signal assert3_dout_net_x5: std_logic;
signal ce_1120_sg_x5: std_logic;
signal ce_2240_sg_x5: std_logic;
signal clk_1120_sg_x5: std_logic;
signal clk_2240_sg_x5: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
begin
ce_1120_sg_x5 <= ce_1120;
ce_2240_sg_x5 <= ce_2240;
clk_1120_sg_x5 <= clk_1120;
clk_2240_sg_x5 <= clk_2240;
assert3_dout_net_x5 <= fofb_cordic_ch_in;
assert2_dout_net_x4 <= fofb_cordic_din;
assert1_dout_net_x1 <= fofb_cordic_pin;
fofb_cordic_data0_out <= down_sample2_q_net_x2;
fofb_cordic_data1_out <= down_sample1_q_net_x2;
fofb_cordic_phase0_out <= down_sample2_q_net_x3;
fofb_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_fofb_cordic0_int_516d0c2a22: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x5,
ce_2240 => ce_2240_sg_x5,
ch_in => assert3_dout_net_x5,
clk_1120 => clk_1120_sg_x5,
clk_2240 => clk_2240_sg_x5,
din => assert2_dout_net_x4,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_cordic1_b60a69fd9b: entity work.tddm_tbt_cordic1_entity_b60a69fd9b
port map (
ce_1120 => ce_1120_sg_x5,
ce_2240 => ce_2240_sg_x5,
ch_in => assert3_dout_net_x5,
clk_1120 => clk_1120_sg_x5,
clk_2240 => clk_2240_sg_x5,
din => assert1_dout_net_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC"
entity fofb_cordic_entity_fad57e49ce is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tddm_tbt_cordic0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x2: out std_logic_vector(23 downto 0)
);
end fofb_cordic_entity_fad57e49ce;
architecture structural of fofb_cordic_entity_fad57e49ce is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x5: std_logic_vector(23 downto 0);
signal assert3_dout_net_x6: std_logic;
signal ce_1120_sg_x6: std_logic;
signal ce_1_sg_x5: std_logic;
signal ce_2240_sg_x6: std_logic;
signal clk_1120_sg_x6: std_logic;
signal clk_1_sg_x5: std_logic;
signal clk_2240_sg_x6: std_logic;
signal delay_q_net_x0: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal rect2pol_m_axis_dout_tdata_phase_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tuser_cartesian_tuser_net: std_logic;
signal rect2pol_m_axis_dout_tvalid_net: std_logic;
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic;
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal up_sample1_q_net: std_logic_vector(24 downto 0);
signal up_sample2_q_net: std_logic_vector(24 downto 0);
signal up_sample3_q_net: std_logic;
signal up_sample_q_net: std_logic;
begin
ce_1_sg_x5 <= ce_1;
ce_1120_sg_x6 <= ce_1120;
ce_2240_sg_x6 <= ce_2240;
delay_q_net_x0 <= ch_in;
clk_1_sg_x5 <= clk_1;
clk_1120_sg_x6 <= clk_1120;
clk_2240_sg_x6 <= clk_2240;
register_q_net_x2 <= i_in;
register_q_net_x1 <= q_in;
register1_q_net_x1 <= valid_in;
amp_out <= assert2_dout_net_x5;
ch_out <= assert3_dout_net_x6;
tddm_tbt_cordic0 <= down_sample1_q_net_x4;
tddm_tbt_cordic0_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic0_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic0_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => assert1_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => assert2_dout_net_x5
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert3_dout_net_x6
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_baddbff1b3cb5131976384a2dda9ffff
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
s_axis_cartesian_tdata_imag => up_sample1_q_net,
s_axis_cartesian_tdata_real => up_sample2_q_net,
s_axis_cartesian_tuser_user(0) => up_sample3_q_net,
s_axis_cartesian_tvalid => up_sample_q_net,
m_axis_dout_tdata_phase => rect2pol_m_axis_dout_tdata_phase_net,
m_axis_dout_tdata_real => rect2pol_m_axis_dout_tdata_real_net,
m_axis_dout_tuser_cartesian_tuser(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
m_axis_dout_tvalid => rect2pol_m_axis_dout_tvalid_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d => reinterpret2_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d => reinterpret3_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_phase_net,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_real_net,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic0_38de3613fe: entity work.tddm_tbt_cordic0_entity_38de3613fe
port map (
ce_1120 => ce_1120_sg_x6,
ce_2240 => ce_2240_sg_x6,
clk_1120 => clk_1120_sg_x6,
clk_2240 => clk_2240_sg_x6,
fofb_cordic_ch_in => assert3_dout_net_x6,
fofb_cordic_din => assert2_dout_net_x5,
fofb_cordic_pin => assert1_dout_net_x1,
fofb_cordic_data0_out => down_sample2_q_net_x4,
fofb_cordic_data1_out => down_sample1_q_net_x4,
fofb_cordic_phase0_out => down_sample2_q_net_x5,
fofb_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net_x1,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q(0) => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x1,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q => up_sample1_q_net
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x2,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => delay_q_net_x0,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q(0) => up_sample3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/Reg"
entity reg_entity_cf7aa296b2 is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end reg_entity_cf7aa296b2;
architecture structural of reg_entity_cf7aa296b2 is
signal ce_1120_sg_x7: std_logic;
signal clk_1120_sg_x7: std_logic;
signal convert_dout_net: std_logic_vector(23 downto 0);
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(24 downto 0);
begin
ce_1120_sg_x7 <= ce_1120;
clk_1120_sg_x7 <= clk_1120;
register_q_net_x2 <= din;
dout <= register_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 23,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x7,
clk => clk_1120_sg_x7,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x7,
clk => clk_1120_sg_x7,
d => convert_dout_net,
en => "1",
rst => "0",
q => register_q_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register_q_net_x2,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/TDDM_fofb_cic0"
entity tddm_fofb_cic0_entity_6b909292ff is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
fofb_ch_in: in std_logic;
fofb_i_in: in std_logic_vector(23 downto 0);
fofb_q_in: in std_logic_vector(23 downto 0);
cic_fofb_ch0_i_out: out std_logic_vector(23 downto 0);
cic_fofb_ch0_q_out: out std_logic_vector(23 downto 0);
cic_fofb_ch1_i_out: out std_logic_vector(23 downto 0);
cic_fofb_ch1_q_out: out std_logic_vector(23 downto 0)
);
end tddm_fofb_cic0_entity_6b909292ff;
architecture structural of tddm_fofb_cic0_entity_6b909292ff is
signal ce_1120_sg_x11: std_logic;
signal ce_2240_sg_x9: std_logic;
signal clk_1120_sg_x11: std_logic;
signal clk_2240_sg_x9: std_logic;
signal delay_q_net_x3: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
begin
ce_1120_sg_x11 <= ce_1120;
ce_2240_sg_x9 <= ce_2240;
clk_1120_sg_x11 <= clk_1120;
clk_2240_sg_x9 <= clk_2240;
delay_q_net_x3 <= fofb_ch_in;
register_q_net_x4 <= fofb_i_in;
register_q_net_x3 <= fofb_q_in;
cic_fofb_ch0_i_out <= down_sample2_q_net_x2;
cic_fofb_ch0_q_out <= down_sample2_q_net_x3;
cic_fofb_ch1_i_out <= down_sample1_q_net_x2;
cic_fofb_ch1_q_out <= down_sample1_q_net_x3;
tddm_fofb_cic0_i_06b84397ec: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x11,
ce_2240 => ce_2240_sg_x9,
ch_in => delay_q_net_x3,
clk_1120 => clk_1120_sg_x11,
clk_2240 => clk_2240_sg_x9,
din => register_q_net_x4,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_fofb_cic0_q_a6a1d7c301: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x11,
ce_2240 => ce_2240_sg_x9,
ch_in => delay_q_net_x3,
clk_1120 => clk_1120_sg_x11,
clk_2240 => clk_2240_sg_x9,
din => register_q_net_x3,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb/Reg"
entity reg_entity_71dd029fba is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(57 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0)
);
end reg_entity_71dd029fba;
architecture structural of reg_entity_71dd029fba is
signal ce_1120_sg_x12: std_logic;
signal cic_fofb_q_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_q_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x12: std_logic;
signal convert_dout_net: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(57 downto 0);
begin
ce_1120_sg_x12 <= ce_1120;
clk_1120_sg_x12 <= clk_1120;
cic_fofb_q_m_axis_data_tdata_data_net_x0 <= din;
cic_fofb_q_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x3;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 56,
din_width => 58,
dout_arith => 2,
dout_bin_pt => 23,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x12,
clk => clk_1120_sg_x12,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1120_sg_x12,
clk => clk_1120_sg_x12,
d => convert_dout_net,
en(0) => cic_fofb_q_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x3
);
reinterpret2: entity work.reinterpret_fa01b5fd95
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => cic_fofb_q_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb/Reg1"
entity reg1_entity_b079f30e3c is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(57 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid_out: out std_logic
);
end reg1_entity_b079f30e3c;
architecture structural of reg1_entity_b079f30e3c is
signal ce_1120_sg_x13: std_logic;
signal cic_fofb_i_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_i_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x13: std_logic;
signal convert_dout_net: std_logic_vector(24 downto 0);
signal register1_q_net_x2: std_logic;
signal register_q_net_x4: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(57 downto 0);
begin
ce_1120_sg_x13 <= ce_1120;
clk_1120_sg_x13 <= clk_1120;
cic_fofb_i_m_axis_data_tdata_data_net_x0 <= din;
cic_fofb_i_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x4;
valid_out <= register1_q_net_x2;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 56,
din_width => 58,
dout_arith => 2,
dout_bin_pt => 23,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
d(0) => cic_fofb_i_m_axis_data_tvalid_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x2
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
d => convert_dout_net,
en(0) => cic_fofb_i_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x4
);
reinterpret2: entity work.reinterpret_fa01b5fd95
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => cic_fofb_i_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb"
entity cic_fofb_entity_2ed6a6e00c is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb_q_x0: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
valid_out: out std_logic
);
end cic_fofb_entity_2ed6a6e00c;
architecture structural of cic_fofb_entity_2ed6a6e00c is
signal ce_1120_sg_x14: std_logic;
signal ce_1_sg_x6: std_logic;
signal ce_logic_1_sg_x5: std_logic;
signal cic_fofb_i_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_i_m_axis_data_tuser_chan_out_net: std_logic;
signal cic_fofb_i_m_axis_data_tvalid_net_x0: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x0: std_logic;
signal cic_fofb_q_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_q_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x14: std_logic;
signal clk_1_sg_x6: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal delay_q_net_x4: std_logic;
signal register1_q_net_x3: std_logic;
signal register3_q_net_x0: std_logic;
signal register4_q_net_x0: std_logic_vector(23 downto 0);
signal register5_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(24 downto 0);
signal register_q_net_x6: std_logic_vector(24 downto 0);
signal relational2_op_net: std_logic;
begin
ce_1_sg_x6 <= ce_1;
ce_1120_sg_x14 <= ce_1120;
ce_logic_1_sg_x5 <= ce_logic_1;
register3_q_net_x0 <= ch_in;
clk_1_sg_x6 <= clk_1;
clk_1120_sg_x14 <= clk_1120;
register4_q_net_x0 <= i_in;
register5_q_net_x0 <= q_in;
ch_out <= delay_q_net_x4;
cic_fofb_q_x0 <= cic_fofb_q_event_tlast_missing_net_x0;
i_out <= register_q_net_x6;
q_out <= register_q_net_x5;
valid_out <= register1_q_net_x3;
cic_fofb_i: entity work.xlcic_compiler_2d3b496704eca3daaae85383d488a908
port map (
ce => ce_1_sg_x6,
ce_1120 => ce_1120_sg_x14,
ce_logic_1 => ce_logic_1_sg_x5,
clk => clk_1_sg_x6,
clk_1120 => clk_1120_sg_x14,
clk_logic_1 => clk_1_sg_x6,
s_axis_data_tdata_data => register4_q_net_x0,
s_axis_data_tlast => relational2_op_net,
m_axis_data_tdata_data => cic_fofb_i_m_axis_data_tdata_data_net_x0,
m_axis_data_tuser_chan_out(0) => cic_fofb_i_m_axis_data_tuser_chan_out_net,
m_axis_data_tvalid => cic_fofb_i_m_axis_data_tvalid_net_x0
);
cic_fofb_q: entity work.xlcic_compiler_2d3b496704eca3daaae85383d488a908
port map (
ce => ce_1_sg_x6,
ce_1120 => ce_1120_sg_x14,
ce_logic_1 => ce_logic_1_sg_x5,
clk => clk_1_sg_x6,
clk_1120 => clk_1120_sg_x14,
clk_logic_1 => clk_1_sg_x6,
s_axis_data_tdata_data => register5_q_net_x0,
s_axis_data_tlast => relational2_op_net,
event_tlast_missing => cic_fofb_q_event_tlast_missing_net_x0,
m_axis_data_tdata_data => cic_fofb_q_m_axis_data_tdata_data_net_x0,
m_axis_data_tvalid => cic_fofb_q_m_axis_data_tvalid_net_x0
);
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1120_sg_x14,
clk => clk_1120_sg_x14,
d(0) => cic_fofb_i_m_axis_data_tuser_chan_out_net,
en => '1',
rst => '1',
q(0) => delay_q_net_x4
);
reg1_b079f30e3c: entity work.reg1_entity_b079f30e3c
port map (
ce_1120 => ce_1120_sg_x14,
clk_1120 => clk_1120_sg_x14,
din => cic_fofb_i_m_axis_data_tdata_data_net_x0,
en => cic_fofb_i_m_axis_data_tvalid_net_x0,
dout => register_q_net_x6,
valid_out => register1_q_net_x3
);
reg_71dd029fba: entity work.reg_entity_71dd029fba
port map (
ce_1120 => ce_1120_sg_x14,
clk_1120 => clk_1120_sg_x14,
din => cic_fofb_q_m_axis_data_tdata_data_net_x0,
en => cic_fofb_q_m_axis_data_tvalid_net_x0,
dout => register_q_net_x5
);
relational2: entity work.relational_d29d27b7b3
port map (
a(0) => register3_q_net_x0,
b => constant1_op_net,
ce => ce_1_sg_x6,
clk => clk_1_sg_x6,
clr => '0',
op(0) => relational2_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp"
entity fofb_amp_entity_078cdb1842 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tddm_fofb_cic0: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end fofb_amp_entity_078cdb1842;
architecture structural of fofb_amp_entity_078cdb1842 is
signal ce_1120_sg_x15: std_logic;
signal ce_1_sg_x7: std_logic;
signal ce_2240_sg_x10: std_logic;
signal ce_logic_1_sg_x6: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x1: std_logic;
signal clk_1120_sg_x15: std_logic;
signal clk_1_sg_x7: std_logic;
signal clk_2240_sg_x10: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x1: std_logic;
signal register4_q_net_x1: std_logic_vector(23 downto 0);
signal register5_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x7 <= ce_1;
ce_1120_sg_x15 <= ce_1120;
ce_2240_sg_x10 <= ce_2240;
ce_logic_1_sg_x6 <= ce_logic_1;
register3_q_net_x1 <= ch_in;
clk_1_sg_x7 <= clk_1;
clk_1120_sg_x15 <= clk_1120;
clk_2240_sg_x10 <= clk_2240;
register4_q_net_x1 <= i_in;
register5_q_net_x1 <= q_in;
ch_out <= delay_q_net_x5;
cic_fofb <= cic_fofb_q_event_tlast_missing_net_x1;
i_out <= register_q_net_x8;
q_out <= register_q_net_x7;
tddm_fofb_cic0 <= down_sample1_q_net_x4;
tddm_fofb_cic0_x0 <= down_sample2_q_net_x4;
tddm_fofb_cic0_x1 <= down_sample1_q_net_x5;
tddm_fofb_cic0_x2 <= down_sample2_q_net_x5;
valid_out <= register1_q_net_x4;
cic_fofb_2ed6a6e00c: entity work.cic_fofb_entity_2ed6a6e00c
port map (
ce_1 => ce_1_sg_x7,
ce_1120 => ce_1120_sg_x15,
ce_logic_1 => ce_logic_1_sg_x6,
ch_in => register3_q_net_x1,
clk_1 => clk_1_sg_x7,
clk_1120 => clk_1120_sg_x15,
i_in => register4_q_net_x1,
q_in => register5_q_net_x1,
ch_out => delay_q_net_x5,
cic_fofb_q_x0 => cic_fofb_q_event_tlast_missing_net_x1,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
valid_out => register1_q_net_x4
);
reg1_6375e37e24: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x15,
clk_1120 => clk_1120_sg_x15,
din => register_q_net_x8,
dout => register_q_net_x4
);
reg_cf7aa296b2: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x15,
clk_1120 => clk_1120_sg_x15,
din => register_q_net_x7,
dout => register_q_net_x3
);
tddm_fofb_cic0_6b909292ff: entity work.tddm_fofb_cic0_entity_6b909292ff
port map (
ce_1120 => ce_1120_sg_x15,
ce_2240 => ce_2240_sg_x10,
clk_1120 => clk_1120_sg_x15,
clk_2240 => clk_2240_sg_x10,
fofb_ch_in => delay_q_net_x5,
fofb_i_in => register_q_net_x4,
fofb_q_in => register_q_net_x3,
cic_fofb_ch0_i_out => down_sample2_q_net_x4,
cic_fofb_ch0_q_out => down_sample2_q_net_x5,
cic_fofb_ch1_i_out => down_sample1_q_net_x4,
cic_fofb_ch1_q_out => down_sample1_q_net_x5
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0"
entity fofb_amp0_entity_95b23bfc2c is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
fofb_amp: out std_logic_vector(23 downto 0);
fofb_amp_x0: out std_logic_vector(23 downto 0);
fofb_amp_x1: out std_logic_vector(23 downto 0);
fofb_amp_x2: out std_logic_vector(23 downto 0);
fofb_amp_x3: out std_logic;
fofb_cordic: out std_logic_vector(23 downto 0);
fofb_cordic_x0: out std_logic_vector(23 downto 0);
fofb_cordic_x1: out std_logic_vector(23 downto 0);
fofb_cordic_x2: out std_logic_vector(23 downto 0)
);
end fofb_amp0_entity_95b23bfc2c;
architecture structural of fofb_amp0_entity_95b23bfc2c is
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal ce_1120_sg_x16: std_logic;
signal ce_1_sg_x8: std_logic;
signal ce_2240_sg_x11: std_logic;
signal ce_logic_1_sg_x7: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x2: std_logic;
signal clk_1120_sg_x16: std_logic;
signal clk_1_sg_x8: std_logic;
signal clk_2240_sg_x11: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x2: std_logic;
signal register4_q_net_x2: std_logic_vector(23 downto 0);
signal register5_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x8 <= ce_1;
ce_1120_sg_x16 <= ce_1120;
ce_2240_sg_x11 <= ce_2240;
ce_logic_1_sg_x7 <= ce_logic_1;
register3_q_net_x2 <= ch_in;
clk_1_sg_x8 <= clk_1;
clk_1120_sg_x16 <= clk_1120;
clk_2240_sg_x11 <= clk_2240;
register4_q_net_x2 <= i_in;
register5_q_net_x2 <= q_in;
amp_out <= assert2_dout_net_x6;
ch_out <= assert3_dout_net_x7;
fofb_amp <= down_sample1_q_net_x10;
fofb_amp_x0 <= down_sample2_q_net_x10;
fofb_amp_x1 <= down_sample1_q_net_x11;
fofb_amp_x2 <= down_sample2_q_net_x11;
fofb_amp_x3 <= cic_fofb_q_event_tlast_missing_net_x2;
fofb_cordic <= down_sample1_q_net_x8;
fofb_cordic_x0 <= down_sample2_q_net_x8;
fofb_cordic_x1 <= down_sample1_q_net_x9;
fofb_cordic_x2 <= down_sample2_q_net_x9;
fofb_amp_078cdb1842: entity work.fofb_amp_entity_078cdb1842
port map (
ce_1 => ce_1_sg_x8,
ce_1120 => ce_1120_sg_x16,
ce_2240 => ce_2240_sg_x11,
ce_logic_1 => ce_logic_1_sg_x7,
ch_in => register3_q_net_x2,
clk_1 => clk_1_sg_x8,
clk_1120 => clk_1120_sg_x16,
clk_2240 => clk_2240_sg_x11,
i_in => register4_q_net_x2,
q_in => register5_q_net_x2,
ch_out => delay_q_net_x5,
cic_fofb => cic_fofb_q_event_tlast_missing_net_x2,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
tddm_fofb_cic0 => down_sample1_q_net_x10,
tddm_fofb_cic0_x0 => down_sample2_q_net_x10,
tddm_fofb_cic0_x1 => down_sample1_q_net_x11,
tddm_fofb_cic0_x2 => down_sample2_q_net_x11,
valid_out => register1_q_net_x4
);
fofb_cordic_fad57e49ce: entity work.fofb_cordic_entity_fad57e49ce
port map (
ce_1 => ce_1_sg_x8,
ce_1120 => ce_1120_sg_x16,
ce_2240 => ce_2240_sg_x11,
ch_in => delay_q_net_x5,
clk_1 => clk_1_sg_x8,
clk_1120 => clk_1120_sg_x16,
clk_2240 => clk_2240_sg_x11,
i_in => register_q_net_x8,
q_in => register_q_net_x7,
valid_in => register1_q_net_x4,
amp_out => assert2_dout_net_x6,
ch_out => assert3_dout_net_x7,
tddm_tbt_cordic0 => down_sample1_q_net_x8,
tddm_tbt_cordic0_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic0_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic0_x2 => down_sample2_q_net_x9
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1/FOFB_CORDIC"
entity fofb_cordic_entity_e4c0810ec7 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tddm_fofb_cordic1: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x2: out std_logic_vector(23 downto 0)
);
end fofb_cordic_entity_e4c0810ec7;
architecture structural of fofb_cordic_entity_e4c0810ec7 is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal ce_1120_sg_x20: std_logic;
signal ce_1_sg_x9: std_logic;
signal ce_2240_sg_x15: std_logic;
signal clk_1120_sg_x20: std_logic;
signal clk_1_sg_x9: std_logic;
signal clk_2240_sg_x15: std_logic;
signal delay_q_net_x0: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal rect2pol_m_axis_dout_tdata_phase_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tuser_cartesian_tuser_net: std_logic;
signal rect2pol_m_axis_dout_tvalid_net: std_logic;
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic;
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal up_sample1_q_net: std_logic_vector(24 downto 0);
signal up_sample2_q_net: std_logic_vector(24 downto 0);
signal up_sample3_q_net: std_logic;
signal up_sample_q_net: std_logic;
begin
ce_1_sg_x9 <= ce_1;
ce_1120_sg_x20 <= ce_1120;
ce_2240_sg_x15 <= ce_2240;
delay_q_net_x0 <= ch_in;
clk_1_sg_x9 <= clk_1;
clk_1120_sg_x20 <= clk_1120;
clk_2240_sg_x15 <= clk_2240;
register_q_net_x2 <= i_in;
register_q_net_x1 <= q_in;
register1_q_net_x1 <= valid_in;
amp_out <= assert2_dout_net_x6;
ch_out <= assert3_dout_net_x7;
tddm_fofb_cordic1 <= down_sample1_q_net_x4;
tddm_fofb_cordic1_x0 <= down_sample2_q_net_x4;
tddm_fofb_cordic1_x1 <= down_sample1_q_net_x5;
tddm_fofb_cordic1_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => assert1_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => assert2_dout_net_x6
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert3_dout_net_x7
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_baddbff1b3cb5131976384a2dda9ffff
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
s_axis_cartesian_tdata_imag => up_sample1_q_net,
s_axis_cartesian_tdata_real => up_sample2_q_net,
s_axis_cartesian_tuser_user(0) => up_sample3_q_net,
s_axis_cartesian_tvalid => up_sample_q_net,
m_axis_dout_tdata_phase => rect2pol_m_axis_dout_tdata_phase_net,
m_axis_dout_tdata_real => rect2pol_m_axis_dout_tdata_real_net,
m_axis_dout_tuser_cartesian_tuser(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
m_axis_dout_tvalid => rect2pol_m_axis_dout_tvalid_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d => reinterpret2_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d => reinterpret3_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_phase_net,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_real_net,
output_port => reinterpret3_output_port_net
);
tddm_fofb_cordic1_77b64089dc: entity work.tddm_tbt_cordic0_entity_38de3613fe
port map (
ce_1120 => ce_1120_sg_x20,
ce_2240 => ce_2240_sg_x15,
clk_1120 => clk_1120_sg_x20,
clk_2240 => clk_2240_sg_x15,
fofb_cordic_ch_in => assert3_dout_net_x7,
fofb_cordic_din => assert2_dout_net_x6,
fofb_cordic_pin => assert1_dout_net_x1,
fofb_cordic_data0_out => down_sample2_q_net_x4,
fofb_cordic_data1_out => down_sample1_q_net_x4,
fofb_cordic_phase0_out => down_sample2_q_net_x5,
fofb_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net_x1,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q(0) => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x1,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q => up_sample1_q_net
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x2,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => delay_q_net_x0,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q(0) => up_sample3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1/FOFB_amp"
entity fofb_amp_entity_f70fcc8ed9 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tddm_fofb_cic1: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end fofb_amp_entity_f70fcc8ed9;
architecture structural of fofb_amp_entity_f70fcc8ed9 is
signal ce_1120_sg_x29: std_logic;
signal ce_1_sg_x11: std_logic;
signal ce_2240_sg_x19: std_logic;
signal ce_logic_1_sg_x9: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x1: std_logic;
signal clk_1120_sg_x29: std_logic;
signal clk_1_sg_x11: std_logic;
signal clk_2240_sg_x19: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x1: std_logic;
signal register4_q_net_x1: std_logic_vector(23 downto 0);
signal register5_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x11 <= ce_1;
ce_1120_sg_x29 <= ce_1120;
ce_2240_sg_x19 <= ce_2240;
ce_logic_1_sg_x9 <= ce_logic_1;
register3_q_net_x1 <= ch_in;
clk_1_sg_x11 <= clk_1;
clk_1120_sg_x29 <= clk_1120;
clk_2240_sg_x19 <= clk_2240;
register4_q_net_x1 <= i_in;
register5_q_net_x1 <= q_in;
ch_out <= delay_q_net_x5;
cic_fofb <= cic_fofb_q_event_tlast_missing_net_x1;
i_out <= register_q_net_x8;
q_out <= register_q_net_x7;
tddm_fofb_cic1 <= down_sample1_q_net_x4;
tddm_fofb_cic1_x0 <= down_sample2_q_net_x4;
tddm_fofb_cic1_x1 <= down_sample1_q_net_x5;
tddm_fofb_cic1_x2 <= down_sample2_q_net_x5;
valid_out <= register1_q_net_x4;
cic_fofb_579902476d: entity work.cic_fofb_entity_2ed6a6e00c
port map (
ce_1 => ce_1_sg_x11,
ce_1120 => ce_1120_sg_x29,
ce_logic_1 => ce_logic_1_sg_x9,
ch_in => register3_q_net_x1,
clk_1 => clk_1_sg_x11,
clk_1120 => clk_1120_sg_x29,
i_in => register4_q_net_x1,
q_in => register5_q_net_x1,
ch_out => delay_q_net_x5,
cic_fofb_q_x0 => cic_fofb_q_event_tlast_missing_net_x1,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
valid_out => register1_q_net_x4
);
reg1_a06a1c33b5: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x29,
clk_1120 => clk_1120_sg_x29,
din => register_q_net_x8,
dout => register_q_net_x4
);
reg_b669a3b118: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x29,
clk_1120 => clk_1120_sg_x29,
din => register_q_net_x7,
dout => register_q_net_x3
);
tddm_fofb_cic1_4a640315a5: entity work.tddm_fofb_cic0_entity_6b909292ff
port map (
ce_1120 => ce_1120_sg_x29,
ce_2240 => ce_2240_sg_x19,
clk_1120 => clk_1120_sg_x29,
clk_2240 => clk_2240_sg_x19,
fofb_ch_in => delay_q_net_x5,
fofb_i_in => register_q_net_x4,
fofb_q_in => register_q_net_x3,
cic_fofb_ch0_i_out => down_sample2_q_net_x4,
cic_fofb_ch0_q_out => down_sample2_q_net_x5,
cic_fofb_ch1_i_out => down_sample1_q_net_x4,
cic_fofb_ch1_q_out => down_sample1_q_net_x5
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1"
entity fofb_amp1_entity_a049562dde is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
fofb_amp: out std_logic_vector(23 downto 0);
fofb_amp_x0: out std_logic_vector(23 downto 0);
fofb_amp_x1: out std_logic_vector(23 downto 0);
fofb_amp_x2: out std_logic_vector(23 downto 0);
fofb_amp_x3: out std_logic;
fofb_cordic: out std_logic_vector(23 downto 0);
fofb_cordic_x0: out std_logic_vector(23 downto 0);
fofb_cordic_x1: out std_logic_vector(23 downto 0);
fofb_cordic_x2: out std_logic_vector(23 downto 0)
);
end fofb_amp1_entity_a049562dde;
architecture structural of fofb_amp1_entity_a049562dde is
signal assert2_dout_net_x7: std_logic_vector(23 downto 0);
signal assert3_dout_net_x8: std_logic;
signal ce_1120_sg_x30: std_logic;
signal ce_1_sg_x12: std_logic;
signal ce_2240_sg_x20: std_logic;
signal ce_logic_1_sg_x10: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x2: std_logic;
signal clk_1120_sg_x30: std_logic;
signal clk_1_sg_x12: std_logic;
signal clk_2240_sg_x20: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x2: std_logic;
signal register4_q_net_x2: std_logic_vector(23 downto 0);
signal register5_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x12 <= ce_1;
ce_1120_sg_x30 <= ce_1120;
ce_2240_sg_x20 <= ce_2240;
ce_logic_1_sg_x10 <= ce_logic_1;
register3_q_net_x2 <= ch_in;
clk_1_sg_x12 <= clk_1;
clk_1120_sg_x30 <= clk_1120;
clk_2240_sg_x20 <= clk_2240;
register4_q_net_x2 <= i_in;
register5_q_net_x2 <= q_in;
amp_out <= assert2_dout_net_x7;
ch_out <= assert3_dout_net_x8;
fofb_amp <= down_sample1_q_net_x10;
fofb_amp_x0 <= down_sample2_q_net_x10;
fofb_amp_x1 <= down_sample1_q_net_x11;
fofb_amp_x2 <= down_sample2_q_net_x11;
fofb_amp_x3 <= cic_fofb_q_event_tlast_missing_net_x2;
fofb_cordic <= down_sample1_q_net_x8;
fofb_cordic_x0 <= down_sample2_q_net_x8;
fofb_cordic_x1 <= down_sample1_q_net_x9;
fofb_cordic_x2 <= down_sample2_q_net_x9;
fofb_amp_f70fcc8ed9: entity work.fofb_amp_entity_f70fcc8ed9
port map (
ce_1 => ce_1_sg_x12,
ce_1120 => ce_1120_sg_x30,
ce_2240 => ce_2240_sg_x20,
ce_logic_1 => ce_logic_1_sg_x10,
ch_in => register3_q_net_x2,
clk_1 => clk_1_sg_x12,
clk_1120 => clk_1120_sg_x30,
clk_2240 => clk_2240_sg_x20,
i_in => register4_q_net_x2,
q_in => register5_q_net_x2,
ch_out => delay_q_net_x5,
cic_fofb => cic_fofb_q_event_tlast_missing_net_x2,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
tddm_fofb_cic1 => down_sample1_q_net_x10,
tddm_fofb_cic1_x0 => down_sample2_q_net_x10,
tddm_fofb_cic1_x1 => down_sample1_q_net_x11,
tddm_fofb_cic1_x2 => down_sample2_q_net_x11,
valid_out => register1_q_net_x4
);
fofb_cordic_e4c0810ec7: entity work.fofb_cordic_entity_e4c0810ec7
port map (
ce_1 => ce_1_sg_x12,
ce_1120 => ce_1120_sg_x30,
ce_2240 => ce_2240_sg_x20,
ch_in => delay_q_net_x5,
clk_1 => clk_1_sg_x12,
clk_1120 => clk_1120_sg_x30,
clk_2240 => clk_2240_sg_x20,
i_in => register_q_net_x8,
q_in => register_q_net_x7,
valid_in => register1_q_net_x4,
amp_out => assert2_dout_net_x7,
ch_out => assert3_dout_net_x8,
tddm_fofb_cordic1 => down_sample1_q_net_x8,
tddm_fofb_cordic1_x0 => down_sample2_q_net_x8,
tddm_fofb_cordic1_x1 => down_sample1_q_net_x9,
tddm_fofb_cordic1_x2 => down_sample2_q_net_x9
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp"
entity fofb_amp_entity_8b25d4b0b6 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in0: in std_logic_vector(23 downto 0);
i_in1: in std_logic_vector(23 downto 0);
q_in0: in std_logic_vector(23 downto 0);
q_in1: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
fofb_amp0: out std_logic_vector(23 downto 0);
fofb_amp0_x0: out std_logic_vector(23 downto 0);
fofb_amp0_x1: out std_logic_vector(23 downto 0);
fofb_amp0_x2: out std_logic_vector(23 downto 0);
fofb_amp0_x3: out std_logic_vector(23 downto 0);
fofb_amp0_x4: out std_logic_vector(23 downto 0);
fofb_amp0_x5: out std_logic_vector(23 downto 0);
fofb_amp0_x6: out std_logic_vector(23 downto 0);
fofb_amp0_x7: out std_logic;
fofb_amp1: out std_logic_vector(23 downto 0);
fofb_amp1_x0: out std_logic_vector(23 downto 0);
fofb_amp1_x1: out std_logic_vector(23 downto 0);
fofb_amp1_x2: out std_logic_vector(23 downto 0);
fofb_amp1_x3: out std_logic_vector(23 downto 0);
fofb_amp1_x4: out std_logic_vector(23 downto 0);
fofb_amp1_x5: out std_logic_vector(23 downto 0);
fofb_amp1_x6: out std_logic_vector(23 downto 0);
fofb_amp1_x7: out std_logic
);
end fofb_amp_entity_8b25d4b0b6;
architecture structural of fofb_amp_entity_8b25d4b0b6 is
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert2_dout_net_x7: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal assert3_dout_net_x8: std_logic;
signal ce_1120_sg_x31: std_logic;
signal ce_1_sg_x13: std_logic;
signal ce_2240_sg_x21: std_logic;
signal ce_logic_1_sg_x11: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x4: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x5: std_logic;
signal clk_1120_sg_x31: std_logic;
signal clk_1_sg_x13: std_logic;
signal clk_2240_sg_x21: std_logic;
signal down_sample1_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x25: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x25: std_logic_vector(23 downto 0);
signal register3_q_net_x4: std_logic;
signal register3_q_net_x5: std_logic;
signal register4_q_net_x4: std_logic_vector(23 downto 0);
signal register4_q_net_x5: std_logic_vector(23 downto 0);
signal register5_q_net_x4: std_logic_vector(23 downto 0);
signal register5_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_1_sg_x13 <= ce_1;
ce_1120_sg_x31 <= ce_1120;
ce_2240_sg_x21 <= ce_2240;
ce_logic_1_sg_x11 <= ce_logic_1;
register3_q_net_x4 <= ch_in0;
register3_q_net_x5 <= ch_in1;
clk_1_sg_x13 <= clk_1;
clk_1120_sg_x31 <= clk_1120;
clk_2240_sg_x21 <= clk_2240;
register4_q_net_x4 <= i_in0;
register4_q_net_x5 <= i_in1;
register5_q_net_x4 <= q_in0;
register5_q_net_x5 <= q_in1;
amp_out0 <= down_sample2_q_net_x16;
amp_out1 <= down_sample1_q_net_x16;
amp_out2 <= down_sample2_q_net_x17;
amp_out3 <= down_sample1_q_net_x17;
fofb_amp0 <= down_sample1_q_net_x18;
fofb_amp0_x0 <= down_sample2_q_net_x18;
fofb_amp0_x1 <= down_sample1_q_net_x19;
fofb_amp0_x2 <= down_sample2_q_net_x19;
fofb_amp0_x3 <= down_sample1_q_net_x20;
fofb_amp0_x4 <= down_sample2_q_net_x20;
fofb_amp0_x5 <= down_sample1_q_net_x21;
fofb_amp0_x6 <= down_sample2_q_net_x21;
fofb_amp0_x7 <= cic_fofb_q_event_tlast_missing_net_x4;
fofb_amp1 <= down_sample1_q_net_x22;
fofb_amp1_x0 <= down_sample2_q_net_x22;
fofb_amp1_x1 <= down_sample1_q_net_x23;
fofb_amp1_x2 <= down_sample2_q_net_x23;
fofb_amp1_x3 <= down_sample1_q_net_x24;
fofb_amp1_x4 <= down_sample2_q_net_x24;
fofb_amp1_x5 <= down_sample1_q_net_x25;
fofb_amp1_x6 <= down_sample2_q_net_x25;
fofb_amp1_x7 <= cic_fofb_q_event_tlast_missing_net_x5;
fofb_amp0_95b23bfc2c: entity work.fofb_amp0_entity_95b23bfc2c
port map (
ce_1 => ce_1_sg_x13,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ce_logic_1 => ce_logic_1_sg_x11,
ch_in => register3_q_net_x4,
clk_1 => clk_1_sg_x13,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
i_in => register4_q_net_x4,
q_in => register5_q_net_x4,
amp_out => assert2_dout_net_x6,
ch_out => assert3_dout_net_x7,
fofb_amp => down_sample1_q_net_x20,
fofb_amp_x0 => down_sample2_q_net_x20,
fofb_amp_x1 => down_sample1_q_net_x21,
fofb_amp_x2 => down_sample2_q_net_x21,
fofb_amp_x3 => cic_fofb_q_event_tlast_missing_net_x4,
fofb_cordic => down_sample1_q_net_x18,
fofb_cordic_x0 => down_sample2_q_net_x18,
fofb_cordic_x1 => down_sample1_q_net_x19,
fofb_cordic_x2 => down_sample2_q_net_x19
);
fofb_amp1_a049562dde: entity work.fofb_amp1_entity_a049562dde
port map (
ce_1 => ce_1_sg_x13,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ce_logic_1 => ce_logic_1_sg_x11,
ch_in => register3_q_net_x5,
clk_1 => clk_1_sg_x13,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
i_in => register4_q_net_x5,
q_in => register5_q_net_x5,
amp_out => assert2_dout_net_x7,
ch_out => assert3_dout_net_x8,
fofb_amp => down_sample1_q_net_x24,
fofb_amp_x0 => down_sample2_q_net_x24,
fofb_amp_x1 => down_sample1_q_net_x25,
fofb_amp_x2 => down_sample2_q_net_x25,
fofb_amp_x3 => cic_fofb_q_event_tlast_missing_net_x5,
fofb_cordic => down_sample1_q_net_x22,
fofb_cordic_x0 => down_sample2_q_net_x22,
fofb_cordic_x1 => down_sample1_q_net_x23,
fofb_cordic_x2 => down_sample2_q_net_x23
);
tddm_fofb_amp_4ch_2cc521a83f: entity work.tddm_fofb_amp_4ch_entity_2cc521a83f
port map (
amp_in0 => assert2_dout_net_x6,
amp_in1 => assert2_dout_net_x7,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ch_in0 => assert3_dout_net_x7,
ch_in1 => assert3_dout_net_x8,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
amp_out0 => down_sample2_q_net_x16,
amp_out1 => down_sample1_q_net_x16,
amp_out2 => down_sample2_q_net_x17,
amp_out3 => down_sample1_q_net_x17
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_fofb_mult3/Cast_truncate1"
entity cast_truncate1_entity_56731b7870 is
port (
in1: in std_logic_vector(49 downto 0);
out1: out std_logic_vector(25 downto 0)
);
end cast_truncate1_entity_56731b7870;
architecture structural of cast_truncate1_entity_56731b7870 is
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal slice_y_net: std_logic_vector(25 downto 0);
begin
kx_tbt_p_net_x0 <= in1;
out1 <= reinterpret_output_port_net_x0;
reinterpret: entity work.reinterpret_9934b94a22
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x0
);
slice: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 49,
x_width => 50,
y_width => 26
)
port map (
x => kx_tbt_p_net_x0,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_fofb_mult3"
entity k_fofb_mult3_entity_697accc8e2 is
port (
ce_2: in std_logic;
ce_2240: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_fofb_mult3_entity_697accc8e2;
architecture structural of k_fofb_mult3_entity_697accc8e2 is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_2240_sg_x22: std_logic;
signal ce_2_sg_x5: std_logic;
signal clk_2240_sg_x22: std_logic;
signal clk_2_sg_x5: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x0: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x5 <= ce_2;
ce_2240_sg_x22 <= ce_2240;
clk_2_sg_x5 <= clk_2;
clk_2240_sg_x22 <= clk_2240;
assert5_dout_net_x0 <= in1;
kx_i_net_x0 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_56731b7870: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_2240_sg_x22,
clk => clk_2240_sg_x22,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => kx_i_net_x0,
ce => ce_2_sg_x5,
clk => clk_2_sg_x5,
clr => '0',
core_ce => ce_2_sg_x5,
core_clk => clk_2_sg_x5,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x5,
clk => clk_2_sg_x5,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_monit_1_mult"
entity k_monit_1_mult_entity_016885a3ac is
port (
ce_2: in std_logic;
ce_224000000: in std_logic;
clk_2: in std_logic;
clk_224000000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_monit_1_mult_entity_016885a3ac;
architecture structural of k_monit_1_mult_entity_016885a3ac is
signal ce_224000000_sg_x0: std_logic;
signal ce_2_sg_x8: std_logic;
signal clk_224000000_sg_x0: std_logic;
signal clk_2_sg_x8: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x2: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal ufix_to_bool_dout_net_x0: std_logic;
begin
ce_2_sg_x8 <= ce_2;
ce_224000000_sg_x0 <= ce_224000000;
clk_2_sg_x8 <= clk_2;
clk_224000000_sg_x0 <= clk_224000000;
reinterpret3_output_port_net_x0 <= in1;
kx_i_net_x2 <= in2;
ufix_to_bool_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_fe5c8d5ea5: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_224000000_sg_x0,
clk => clk_224000000_sg_x0,
d(0) => ufix_to_bool_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => reinterpret3_output_port_net_x0,
b => kx_i_net_x2,
ce => ce_2_sg_x8,
clk => clk_2_sg_x8,
clr => '0',
core_ce => ce_2_sg_x8,
core_clk => clk_2_sg_x8,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x8,
clk => clk_2_sg_x8,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_monit_mult3"
entity k_monit_mult3_entity_8a778fb5f4 is
port (
ce_2: in std_logic;
ce_22400000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_monit_mult3_entity_8a778fb5f4;
architecture structural of k_monit_mult3_entity_8a778fb5f4 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_22400000_sg_x0: std_logic;
signal ce_2_sg_x11: std_logic;
signal clk_22400000_sg_x0: std_logic;
signal clk_2_sg_x11: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x4: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x11 <= ce_2;
ce_22400000_sg_x0 <= ce_22400000;
clk_2_sg_x11 <= clk_2;
clk_22400000_sg_x0 <= clk_22400000;
assert11_dout_net_x0 <= in1;
kx_i_net_x4 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_47fd83104e: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_22400000_sg_x0,
clk => clk_22400000_sg_x0,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => kx_i_net_x4,
ce => ce_2_sg_x11,
clk => clk_2_sg_x11,
clr => '0',
core_ce => ce_2_sg_x11,
core_clk => clk_2_sg_x11,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x11,
clk => clk_2_sg_x11,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_tbt_mult"
entity k_tbt_mult_entity_b8fafff255 is
port (
ce_2: in std_logic;
ce_70: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_tbt_mult_entity_b8fafff255;
architecture structural of k_tbt_mult_entity_b8fafff255 is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_2_sg_x14: std_logic;
signal ce_70_sg_x0: std_logic;
signal clk_2_sg_x14: std_logic;
signal clk_70_sg_x0: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x6: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x14 <= ce_2;
ce_70_sg_x0 <= ce_70;
clk_2_sg_x14 <= clk_2;
clk_70_sg_x0 <= clk_70;
assert5_dout_net_x0 <= in1;
kx_i_net_x6 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_4592ea30ee: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_70_sg_x0,
clk => clk_70_sg_x0,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => kx_i_net_x6,
ce => ce_2_sg_x14,
clk => clk_2_sg_x14,
clr => '0',
core_ce => ce_2_sg_x14,
core_clk => clk_2_sg_x14,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x14,
clk => clk_2_sg_x14,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_fofb_mult4/Cast_truncate1"
entity cast_truncate1_entity_18a9b21a64 is
port (
in1: in std_logic_vector(49 downto 0);
out1: out std_logic_vector(25 downto 0)
);
end cast_truncate1_entity_18a9b21a64;
architecture structural of cast_truncate1_entity_18a9b21a64 is
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal slice_y_net: std_logic_vector(25 downto 0);
begin
kx_tbt_p_net_x0 <= in1;
out1 <= reinterpret_output_port_net_x0;
reinterpret: entity work.reinterpret_9934b94a22
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x0
);
slice: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 49,
x_width => 50,
y_width => 26
)
port map (
x => kx_tbt_p_net_x0,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_fofb_mult4"
entity ksum_fofb_mult4_entity_ac3ed97096 is
port (
ce_2: in std_logic;
ce_2240: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_fofb_mult4_entity_ac3ed97096;
architecture structural of ksum_fofb_mult4_entity_ac3ed97096 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_2240_sg_x25: std_logic;
signal ce_2_sg_x17: std_logic;
signal clk_2240_sg_x25: std_logic;
signal clk_2_sg_x17: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x0: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x17 <= ce_2;
ce_2240_sg_x25 <= ce_2240;
clk_2_sg_x17 <= clk_2;
clk_2240_sg_x25 <= clk_2240;
assert11_dout_net_x0 <= in1;
ksum_i_net_x0 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_18a9b21a64: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_2240_sg_x25,
clk => clk_2240_sg_x25,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => ksum_i_net_x0,
ce => ce_2_sg_x17,
clk => clk_2_sg_x17,
clr => '0',
core_ce => ce_2_sg_x17,
core_clk => clk_2_sg_x17,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x17,
clk => clk_2_sg_x17,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_monit_1_mult1"
entity ksum_monit_1_mult1_entity_c66dc07078 is
port (
ce_2: in std_logic;
ce_224000000: in std_logic;
clk_2: in std_logic;
clk_224000000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_monit_1_mult1_entity_c66dc07078;
architecture structural of ksum_monit_1_mult1_entity_c66dc07078 is
signal ce_224000000_sg_x3: std_logic;
signal ce_2_sg_x18: std_logic;
signal clk_224000000_sg_x3: std_logic;
signal clk_2_sg_x18: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x1: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret4_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal ufix_to_bool3_dout_net_x0: std_logic;
begin
ce_2_sg_x18 <= ce_2;
ce_224000000_sg_x3 <= ce_224000000;
clk_2_sg_x18 <= clk_2;
clk_224000000_sg_x3 <= clk_224000000;
reinterpret4_output_port_net_x0 <= in1;
ksum_i_net_x1 <= in2;
ufix_to_bool3_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_92cc22397d: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_224000000_sg_x3,
clk => clk_224000000_sg_x3,
d(0) => ufix_to_bool3_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => reinterpret4_output_port_net_x0,
b => ksum_i_net_x1,
ce => ce_2_sg_x18,
clk => clk_2_sg_x18,
clr => '0',
core_ce => ce_2_sg_x18,
core_clk => clk_2_sg_x18,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x18,
clk => clk_2_sg_x18,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_monit_mult2"
entity ksum_monit_mult2_entity_31877b6d2b is
port (
ce_2: in std_logic;
ce_22400000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_monit_mult2_entity_31877b6d2b;
architecture structural of ksum_monit_mult2_entity_31877b6d2b is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_22400000_sg_x3: std_logic;
signal ce_2_sg_x19: std_logic;
signal clk_22400000_sg_x3: std_logic;
signal clk_2_sg_x19: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x2: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x19 <= ce_2;
ce_22400000_sg_x3 <= ce_22400000;
clk_2_sg_x19 <= clk_2;
clk_22400000_sg_x3 <= clk_22400000;
assert5_dout_net_x0 <= in1;
ksum_i_net_x2 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_4c5b033963: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_22400000_sg_x3,
clk => clk_22400000_sg_x3,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => ksum_i_net_x2,
ce => ce_2_sg_x19,
clk => clk_2_sg_x19,
clr => '0',
core_ce => ce_2_sg_x19,
core_clk => clk_2_sg_x19,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x19,
clk => clk_2_sg_x19,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_tbt_mult3"
entity ksum_tbt_mult3_entity_e0be30d675 is
port (
ce_2: in std_logic;
ce_70: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_tbt_mult3_entity_e0be30d675;
architecture structural of ksum_tbt_mult3_entity_e0be30d675 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_2_sg_x20: std_logic;
signal ce_70_sg_x3: std_logic;
signal clk_2_sg_x20: std_logic;
signal clk_70_sg_x3: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x3: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x20 <= ce_2;
ce_70_sg_x3 <= ce_70;
clk_2_sg_x20 <= clk_2;
clk_70_sg_x3 <= clk_70;
assert11_dout_net_x0 <= in1;
ksum_i_net_x3 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_91bc0d396f: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_70_sg_x3,
clk => clk_70_sg_x3,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => ksum_i_net_x3,
ce => ce_2_sg_x20,
clk => clk_2_sg_x20,
clr => '0',
core_ce => ce_2_sg_x20,
core_clk => clk_2_sg_x20,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x20,
clk => clk_2_sg_x20,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0/DataReg_En"
entity datareg_en_entity_5c82ef2965 is
port (
ce_2: in std_logic;
clk_2: in std_logic;
din: in std_logic_vector(23 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0);
valid: out std_logic
);
end datareg_en_entity_5c82ef2965;
architecture structural of datareg_en_entity_5c82ef2965 is
signal ce_2_sg_x21: std_logic;
signal clk_2_sg_x21: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant12_op_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_2_sg_x21 <= ce_2;
clk_2_sg_x21 <= clk_2;
constant12_op_net_x0 <= din;
constant11_op_net_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_2_sg_x21,
clk => clk_2_sg_x21,
d(0) => constant11_op_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_2_sg_x21,
clk => clk_2_sg_x21,
d => constant12_op_net_x0,
en(0) => constant11_op_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0/DataReg_En1"
entity datareg_en1_entity_8d533fde9e is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(23 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end datareg_en1_entity_8d533fde9e;
architecture structural of datareg_en1_entity_8d533fde9e is
signal ce_1_sg_x14: std_logic;
signal clk_1_sg_x14: std_logic;
signal constant11_op_net_x1: std_logic;
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
begin
ce_1_sg_x14 <= ce_1;
clk_1_sg_x14 <= clk_1;
register_q_net_x1 <= din;
constant11_op_net_x1 <= en;
dout <= register_q_net_x2;
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
d => register_q_net_x1,
en(0) => constant11_op_net_x1,
rst => "0",
q => register_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0"
entity cmixer_0_entity_f630e8d7ec is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_cosine: in std_logic_vector(23 downto 0);
dds_msine: in std_logic_vector(23 downto 0);
dds_valid: in std_logic;
din_i: in std_logic_vector(23 downto 0);
din_q: in std_logic_vector(23 downto 0);
en: in std_logic;
ch_out: out std_logic;
i_out: out std_logic_vector(23 downto 0);
q_out: out std_logic_vector(23 downto 0)
);
end cmixer_0_entity_f630e8d7ec;
architecture structural of cmixer_0_entity_f630e8d7ec is
signal a_i: std_logic_vector(23 downto 0);
signal a_r: std_logic_vector(23 downto 0);
signal b_i: std_logic_vector(23 downto 0);
signal b_r: std_logic_vector(23 downto 0);
signal ce_1_sg_x15: std_logic;
signal ce_2_sg_x22: std_logic;
signal clk_1_sg_x15: std_logic;
signal clk_2_sg_x22: std_logic;
signal complexmult_m_axis_dout_tdata_imag_net: std_logic_vector(23 downto 0);
signal complexmult_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal complexmult_m_axis_dout_tuser_net: std_logic;
signal complexmult_m_axis_dout_tvalid_net: std_logic;
signal constant11_op_net_x2: std_logic;
signal constant12_op_net_x1: std_logic_vector(23 downto 0);
signal constant15_op_net_x0: std_logic;
signal convert1_dout_net: std_logic_vector(23 downto 0);
signal convert2_dout_net: std_logic_vector(23 downto 0);
signal register1_q_net_x0: std_logic;
signal register1_q_net_x1: std_logic;
signal register3_q_net_x5: std_logic;
signal register4_q_net_x5: std_logic_vector(23 downto 0);
signal register5_q_net_x5: std_logic_vector(23 downto 0);
signal register_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(23 downto 0);
signal register_q_net_x8: std_logic_vector(23 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x15 <= ce_1;
ce_2_sg_x22 <= ce_2;
register1_q_net_x1 <= ch_in;
clk_1_sg_x15 <= clk_1;
clk_2_sg_x22 <= clk_2;
register_q_net_x6 <= dds_cosine;
register_q_net_x7 <= dds_msine;
constant15_op_net_x0 <= dds_valid;
register_q_net_x8 <= din_i;
constant12_op_net_x1 <= din_q;
constant11_op_net_x2 <= en;
ch_out <= register3_q_net_x5;
i_out <= register4_q_net_x5;
q_out <= register5_q_net_x5;
complexmult: entity work.xlcomplex_multiplier_456da30af0f77a480cf80f52b29b4396
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
s_axis_a_tdata_imag => a_i,
s_axis_a_tdata_real => a_r,
s_axis_a_tvalid => constant15_op_net_x0,
s_axis_b_tdata_imag => b_i,
s_axis_b_tdata_real => b_r,
s_axis_b_tuser(0) => register_q_net,
s_axis_b_tvalid => register1_q_net_x0,
m_axis_dout_tdata_imag => complexmult_m_axis_dout_tdata_imag_net,
m_axis_dout_tdata_real => complexmult_m_axis_dout_tdata_real_net,
m_axis_dout_tuser(0) => complexmult_m_axis_dout_tuser_net,
m_axis_dout_tvalid => complexmult_m_axis_dout_tvalid_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 19,
din_width => 24,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
clr => '0',
din => reinterpret1_output_port_net,
en => "1",
dout => convert1_dout_net
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 19,
din_width => 24,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert2_dout_net
);
datareg_en1_8d533fde9e: entity work.datareg_en1_entity_8d533fde9e
port map (
ce_1 => ce_1_sg_x15,
clk_1 => clk_1_sg_x15,
din => register_q_net_x8,
en => constant11_op_net_x2,
dout => register_q_net_x2
);
datareg_en_5c82ef2965: entity work.datareg_en_entity_5c82ef2965
port map (
ce_2 => ce_2_sg_x22,
clk_2 => clk_2_sg_x22,
din => constant12_op_net_x1,
en => constant11_op_net_x2,
dout => register_q_net_x0,
valid => register1_q_net_x0
);
delay: entity work.delay_961b43f67a
port map (
ce => '0',
clk => '0',
clr => '0',
d => register_q_net_x0,
q => b_i
);
delay1: entity work.delay_961b43f67a
port map (
ce => '0',
clk => '0',
clr => '0',
d => register_q_net_x2,
q => b_r
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => register_q_net_x6,
en(0) => constant15_op_net_x0,
rst => "0",
q => a_r
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => register_q_net_x7,
en(0) => constant15_op_net_x0,
rst => "0",
q => a_i
);
register3: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d(0) => complexmult_m_axis_dout_tuser_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register3_q_net_x5
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => convert1_dout_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net_x5
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => convert2_dout_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net_x5
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d(0) => register1_q_net_x1,
en(0) => constant11_op_net_x2,
rst => "0",
q(0) => register_q_net
);
reinterpret: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => complexmult_m_axis_dout_tdata_imag_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => complexmult_m_axis_dout_tdata_real_net,
output_port => reinterpret1_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/TDDM_Mixer/TDDM_Mixer0_i"
entity tddm_mixer0_i_entity_f95b8f24ad is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_mixer0_i_entity_f95b8f24ad;
architecture structural of tddm_mixer0_i_entity_f95b8f24ad is
signal ce_1_sg_x18: std_logic;
signal ce_2_sg_x25: std_logic;
signal clk_1_sg_x18: std_logic;
signal clk_2_sg_x25: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register3_q_net_x6: std_logic;
signal register4_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1_sg_x18 <= ce_1;
ce_2_sg_x25 <= ce_2;
register3_q_net_x6 <= ch_in;
clk_1_sg_x18 <= clk_1;
clk_2_sg_x25 <= clk_2;
register4_q_net_x6 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2_sg_x25,
dest_clk => clk_2_sg_x25,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x18,
src_clk => clk_1_sg_x18,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2_sg_x25,
dest_clk => clk_2_sg_x25,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x18,
src_clk => clk_1_sg_x18,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
d => register4_q_net_x6,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
d => register4_q_net_x6,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => register3_q_net_x6,
b(0) => constant_op_net,
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_d29d27b7b3
port map (
a(0) => register3_q_net_x6,
b => constant1_op_net,
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/TDDM_Mixer"
entity tddm_mixer_entity_8537ade7b6 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
mix0_ch_in: in std_logic;
mix0_i_in: in std_logic_vector(23 downto 0);
mix0_q_in: in std_logic_vector(23 downto 0);
mix1_ch_in: in std_logic;
mix1_i_in: in std_logic_vector(23 downto 0);
mix1_q_in: in std_logic_vector(23 downto 0);
mix_ch0_i_out: out std_logic_vector(23 downto 0);
mix_ch0_q_out: out std_logic_vector(23 downto 0);
mix_ch1_i_out: out std_logic_vector(23 downto 0);
mix_ch1_q_out: out std_logic_vector(23 downto 0);
mix_ch2_i_out: out std_logic_vector(23 downto 0);
mix_ch2_q_out: out std_logic_vector(23 downto 0);
mix_ch3_i_out: out std_logic_vector(23 downto 0);
mix_ch3_q_out: out std_logic_vector(23 downto 0)
);
end tddm_mixer_entity_8537ade7b6;
architecture structural of tddm_mixer_entity_8537ade7b6 is
signal ce_1_sg_x22: std_logic;
signal ce_2_sg_x29: std_logic;
signal clk_1_sg_x22: std_logic;
signal clk_2_sg_x29: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x6: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x7: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x6: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x7: std_logic_vector(23 downto 0);
signal register3_q_net_x10: std_logic;
signal register3_q_net_x9: std_logic;
signal register4_q_net_x8: std_logic_vector(23 downto 0);
signal register4_q_net_x9: std_logic_vector(23 downto 0);
signal register5_q_net_x8: std_logic_vector(23 downto 0);
signal register5_q_net_x9: std_logic_vector(23 downto 0);
begin
ce_1_sg_x22 <= ce_1;
ce_2_sg_x29 <= ce_2;
clk_1_sg_x22 <= clk_1;
clk_2_sg_x29 <= clk_2;
register3_q_net_x9 <= mix0_ch_in;
register4_q_net_x8 <= mix0_i_in;
register5_q_net_x8 <= mix0_q_in;
register3_q_net_x10 <= mix1_ch_in;
register4_q_net_x9 <= mix1_i_in;
register5_q_net_x9 <= mix1_q_in;
mix_ch0_i_out <= down_sample2_q_net_x4;
mix_ch0_q_out <= down_sample2_q_net_x5;
mix_ch1_i_out <= down_sample1_q_net_x4;
mix_ch1_q_out <= down_sample1_q_net_x5;
mix_ch2_i_out <= down_sample2_q_net_x6;
mix_ch2_q_out <= down_sample2_q_net_x7;
mix_ch3_i_out <= down_sample1_q_net_x6;
mix_ch3_q_out <= down_sample1_q_net_x7;
tddm_mixer0_i_f95b8f24ad: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x9,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register4_q_net_x8,
dout_ch0 => down_sample2_q_net_x4,
dout_ch1 => down_sample1_q_net_x4
);
tddm_mixer0_q_2c5e18f496: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x9,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register5_q_net_x8,
dout_ch0 => down_sample2_q_net_x5,
dout_ch1 => down_sample1_q_net_x5
);
tddm_mixer1_i_1afc4ccdba: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x10,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register4_q_net_x9,
dout_ch0 => down_sample2_q_net_x6,
dout_ch1 => down_sample1_q_net_x6
);
tddm_mixer1_q_ee4acbed30: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x10,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register5_q_net_x9,
dout_ch0 => down_sample2_q_net_x7,
dout_ch1 => down_sample1_q_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer"
entity mixer_entity_a1cd828545 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_cosine_0: in std_logic_vector(23 downto 0);
dds_cosine_1: in std_logic_vector(23 downto 0);
dds_msine_0: in std_logic_vector(23 downto 0);
dds_msine_1: in std_logic_vector(23 downto 0);
dds_valid_0: in std_logic;
dds_valid_1: in std_logic;
din0: in std_logic_vector(23 downto 0);
din1: in std_logic_vector(23 downto 0);
ch_out0: out std_logic;
ch_out1: out std_logic;
i_out0: out std_logic_vector(23 downto 0);
i_out1: out std_logic_vector(23 downto 0);
q_out0: out std_logic_vector(23 downto 0);
q_out1: out std_logic_vector(23 downto 0);
tddm_mixer: out std_logic_vector(23 downto 0);
tddm_mixer_x0: out std_logic_vector(23 downto 0);
tddm_mixer_x1: out std_logic_vector(23 downto 0);
tddm_mixer_x2: out std_logic_vector(23 downto 0);
tddm_mixer_x3: out std_logic_vector(23 downto 0);
tddm_mixer_x4: out std_logic_vector(23 downto 0);
tddm_mixer_x5: out std_logic_vector(23 downto 0);
tddm_mixer_x6: out std_logic_vector(23 downto 0)
);
end mixer_entity_a1cd828545;
architecture structural of mixer_entity_a1cd828545 is
signal ce_1_sg_x23: std_logic;
signal ce_2_sg_x30: std_logic;
signal clk_1_sg_x23: std_logic;
signal clk_2_sg_x30: std_logic;
signal constant11_op_net_x2: std_logic;
signal constant12_op_net_x1: std_logic_vector(23 downto 0);
signal constant15_op_net_x1: std_logic;
signal constant1_op_net_x2: std_logic;
signal constant2_op_net_x1: std_logic_vector(23 downto 0);
signal constant3_op_net_x1: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register3_q_net_x11: std_logic;
signal register3_q_net_x12: std_logic;
signal register4_q_net_x10: std_logic_vector(23 downto 0);
signal register4_q_net_x11: std_logic_vector(23 downto 0);
signal register5_q_net_x10: std_logic_vector(23 downto 0);
signal register5_q_net_x11: std_logic_vector(23 downto 0);
signal register_q_net_x12: std_logic_vector(23 downto 0);
signal register_q_net_x13: std_logic_vector(23 downto 0);
signal register_q_net_x14: std_logic_vector(23 downto 0);
signal register_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x16: std_logic_vector(23 downto 0);
signal register_q_net_x17: std_logic_vector(23 downto 0);
begin
ce_1_sg_x23 <= ce_1;
ce_2_sg_x30 <= ce_2;
register1_q_net_x3 <= ch_in0;
register1_q_net_x4 <= ch_in1;
clk_1_sg_x23 <= clk_1;
clk_2_sg_x30 <= clk_2;
register_q_net_x12 <= dds_cosine_0;
register_q_net_x14 <= dds_cosine_1;
register_q_net_x13 <= dds_msine_0;
register_q_net_x15 <= dds_msine_1;
constant15_op_net_x1 <= dds_valid_0;
constant3_op_net_x1 <= dds_valid_1;
register_q_net_x16 <= din0;
register_q_net_x17 <= din1;
ch_out0 <= register3_q_net_x11;
ch_out1 <= register3_q_net_x12;
i_out0 <= register4_q_net_x10;
i_out1 <= register4_q_net_x11;
q_out0 <= register5_q_net_x10;
q_out1 <= register5_q_net_x11;
tddm_mixer <= down_sample1_q_net_x8;
tddm_mixer_x0 <= down_sample2_q_net_x8;
tddm_mixer_x1 <= down_sample1_q_net_x9;
tddm_mixer_x2 <= down_sample2_q_net_x9;
tddm_mixer_x3 <= down_sample1_q_net_x10;
tddm_mixer_x4 <= down_sample2_q_net_x10;
tddm_mixer_x5 <= down_sample1_q_net_x11;
tddm_mixer_x6 <= down_sample2_q_net_x11;
cmixer_0_f630e8d7ec: entity work.cmixer_0_entity_f630e8d7ec
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
ch_in => register1_q_net_x3,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
dds_cosine => register_q_net_x12,
dds_msine => register_q_net_x13,
dds_valid => constant15_op_net_x1,
din_i => register_q_net_x16,
din_q => constant12_op_net_x1,
en => constant11_op_net_x2,
ch_out => register3_q_net_x11,
i_out => register4_q_net_x10,
q_out => register5_q_net_x10
);
cmixer_1_61bfc18f90: entity work.cmixer_0_entity_f630e8d7ec
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
ch_in => register1_q_net_x4,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
dds_cosine => register_q_net_x14,
dds_msine => register_q_net_x15,
dds_valid => constant3_op_net_x1,
din_i => register_q_net_x17,
din_q => constant2_op_net_x1,
en => constant1_op_net_x2,
ch_out => register3_q_net_x12,
i_out => register4_q_net_x11,
q_out => register5_q_net_x11
);
constant1: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x2
);
constant11: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x2
);
constant12: entity work.constant_f394f3309c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant12_op_net_x1
);
constant2: entity work.constant_f394f3309c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant2_op_net_x1
);
tddm_mixer_8537ade7b6: entity work.tddm_mixer_entity_8537ade7b6
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
mix0_ch_in => register3_q_net_x11,
mix0_i_in => register4_q_net_x10,
mix0_q_in => register5_q_net_x10,
mix1_ch_in => register3_q_net_x12,
mix1_i_in => register4_q_net_x11,
mix1_q_in => register5_q_net_x11,
mix_ch0_i_out => down_sample2_q_net_x8,
mix_ch0_q_out => down_sample2_q_net_x9,
mix_ch1_i_out => down_sample1_q_net_x8,
mix_ch1_q_out => down_sample1_q_net_x9,
mix_ch2_i_out => down_sample2_q_net_x10,
mix_ch2_q_out => down_sample2_q_net_x11,
mix_ch3_i_out => down_sample1_q_net_x10,
mix_ch3_q_out => down_sample1_q_net_x11
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast2/format1"
entity format1_entity_4e0a69646b is
port (
ce_5600000: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end format1_entity_4e0a69646b;
architecture structural of format1_entity_4e0a69646b is
signal ce_5600000_sg_x0: std_logic;
signal clk_5600000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_pfir_m_axis_data_tdata_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
begin
ce_5600000_sg_x0 <= ce_5600000;
clk_5600000_sg_x0 <= clk_5600000;
monit_pfir_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 21,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_5600000_sg_x0,
clk => clk_5600000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_pfir_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast2"
entity cast2_entity_4b7421c7c9 is
port (
ce_5600000: in std_logic;
clk_5600000: in std_logic;
data_in: in std_logic_vector(24 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(23 downto 0)
);
end cast2_entity_4b7421c7c9;
architecture structural of cast2_entity_4b7421c7c9 is
signal ce_5600000_sg_x1: std_logic;
signal clk_5600000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_pfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_pfir_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_5600000_sg_x1 <= ce_5600000;
clk_5600000_sg_x1 <= clk_5600000;
monit_pfir_m_axis_data_tdata_net_x1 <= data_in;
monit_pfir_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
format1_4e0a69646b: entity work.format1_entity_4e0a69646b
port map (
ce_5600000 => ce_5600000_sg_x1,
clk_5600000 => clk_5600000_sg_x1,
din => monit_pfir_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x1,
clk => clk_5600000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_pfir_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast4/format1"
entity format1_entity_3cf61b0d44 is
port (
ce_2800000: in std_logic;
clk_2800000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end format1_entity_3cf61b0d44;
architecture structural of format1_entity_3cf61b0d44 is
signal ce_2800000_sg_x0: std_logic;
signal clk_2800000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_cfir_m_axis_data_tdata_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
begin
ce_2800000_sg_x0 <= ce_2800000;
clk_2800000_sg_x0 <= clk_2800000;
monit_cfir_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 21,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_2800000_sg_x0,
clk => clk_2800000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_cfir_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast4"
entity cast4_entity_4ed908d7fc is
port (
ce_2800000: in std_logic;
clk_2800000: in std_logic;
data_in: in std_logic_vector(24 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(23 downto 0)
);
end cast4_entity_4ed908d7fc;
architecture structural of cast4_entity_4ed908d7fc is
signal ce_2800000_sg_x1: std_logic;
signal clk_2800000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_cfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_cfir_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_2800000_sg_x1 <= ce_2800000;
clk_2800000_sg_x1 <= clk_2800000;
monit_cfir_m_axis_data_tdata_net_x1 <= data_in;
monit_cfir_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
format1_3cf61b0d44: entity work.format1_entity_3cf61b0d44
port map (
ce_2800000 => ce_2800000_sg_x1,
clk_2800000 => clk_2800000_sg_x1,
din => monit_cfir_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_2800000_sg_x1,
clk => clk_2800000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_cfir_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Reg1"
entity reg1_entity_8661a44192 is
port (
ce_1400000: in std_logic;
clk_1400000: in std_logic;
din: in std_logic_vector(60 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end reg1_entity_8661a44192;
architecture structural of reg1_entity_8661a44192 is
signal ce_1400000_sg_x0: std_logic;
signal clk_1400000_sg_x0: std_logic;
signal convert_dout_net: std_logic_vector(23 downto 0);
signal monit_cic_m_axis_data_tdata_data_net_x0: std_logic_vector(60 downto 0);
signal monit_cic_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(60 downto 0);
begin
ce_1400000_sg_x0 <= ce_1400000;
clk_1400000_sg_x0 <= clk_1400000;
monit_cic_m_axis_data_tdata_data_net_x0 <= din;
monit_cic_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 59,
din_width => 61,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1400000_sg_x0,
clk => clk_1400000_sg_x0,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1400000_sg_x0,
clk => clk_1400000_sg_x0,
d => convert_dout_net,
en(0) => monit_cic_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
reinterpret2: entity work.reinterpret_c88e29aa6b
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_cic_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/TDDM_monit_amp_c/TDDM_monit_amp_c_int"
entity tddm_monit_amp_c_int_entity_554a834349 is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_22400000: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0);
dout_ch2: out std_logic_vector(23 downto 0);
dout_ch3: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_c_int_entity_554a834349;
architecture structural of tddm_monit_amp_c_int_entity_554a834349 is
signal ce_22400000_sg_x4: std_logic;
signal ce_5600000_sg_x2: std_logic;
signal clk_22400000_sg_x4: std_logic;
signal clk_5600000_sg_x2: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant3_op_net: std_logic_vector(1 downto 0);
signal constant4_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic_vector(1 downto 0);
signal delay2_q_net_x0: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register2_q_net: std_logic_vector(23 downto 0);
signal register3_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational3_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_22400000_sg_x4 <= ce_22400000;
ce_5600000_sg_x2 <= ce_5600000;
delay2_q_net_x0 <= ch_in;
clk_22400000_sg_x4 <= clk_22400000;
clk_5600000_sg_x2 <= clk_5600000;
register_q_net_x1 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
dout_ch2 <= down_sample3_q_net_x0;
dout_ch3 <= down_sample4_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant3: entity work.constant_a7e2bb9e12
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant3_op_net
);
constant4: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant_x0: entity work.constant_3a9a3daeb9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample2_q_net_x0
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register2_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample3_q_net_x0
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register3_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample4_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational2_op_net,
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational3_op_net,
rst => "0",
q => register3_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant1_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant3_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational2_op_net
);
relational3: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant4_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational3_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/TDDM_monit_amp_c"
entity tddm_monit_amp_c_entity_5b2613eff7 is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
clk_22400000: in std_logic;
clk_5600000: in std_logic;
monit_ch_in: in std_logic_vector(1 downto 0);
monit_din: in std_logic_vector(23 downto 0);
monit_ch0_out: out std_logic_vector(23 downto 0);
monit_ch1_out: out std_logic_vector(23 downto 0);
monit_ch2_out: out std_logic_vector(23 downto 0);
monit_ch3_out: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_c_entity_5b2613eff7;
architecture structural of tddm_monit_amp_c_entity_5b2613eff7 is
signal ce_22400000_sg_x5: std_logic;
signal ce_5600000_sg_x3: std_logic;
signal clk_22400000_sg_x5: std_logic;
signal clk_5600000_sg_x3: std_logic;
signal delay2_q_net_x1: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
begin
ce_22400000_sg_x5 <= ce_22400000;
ce_5600000_sg_x3 <= ce_5600000;
clk_22400000_sg_x5 <= clk_22400000;
clk_5600000_sg_x3 <= clk_5600000;
delay2_q_net_x1 <= monit_ch_in;
register_q_net_x2 <= monit_din;
monit_ch0_out <= down_sample2_q_net_x1;
monit_ch1_out <= down_sample1_q_net_x1;
monit_ch2_out <= down_sample3_q_net_x1;
monit_ch3_out <= down_sample4_q_net_x1;
tddm_monit_amp_c_int_554a834349: entity work.tddm_monit_amp_c_int_entity_554a834349
port map (
ce_22400000 => ce_22400000_sg_x5,
ce_5600000 => ce_5600000_sg_x3,
ch_in => delay2_q_net_x1,
clk_22400000 => clk_22400000_sg_x5,
clk_5600000 => clk_5600000_sg_x3,
din => register_q_net_x2,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c"
entity monit_amp_c_entity_c83793ea71 is
port (
ce_1: in std_logic;
ce_1400000: in std_logic;
ce_22400000: in std_logic;
ce_2800000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_1400000: in std_logic;
clk_22400000: in std_logic;
clk_2800000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out_x1: out std_logic_vector(1 downto 0);
monit_cfir_x0: out std_logic;
monit_cic_x0: out std_logic;
monit_pfir_x0: out std_logic;
tddm_monit_amp_c: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x0: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x1: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x2: out std_logic_vector(23 downto 0)
);
end monit_amp_c_entity_c83793ea71;
architecture structural of monit_amp_c_entity_c83793ea71 is
signal ce_1400000_sg_x1: std_logic;
signal ce_1_sg_x24: std_logic;
signal ce_22400000_sg_x6: std_logic;
signal ce_2800000_sg_x2: std_logic;
signal ce_5600000_sg_x4: std_logic;
signal ce_560_sg_x0: std_logic;
signal ce_logic_1400000_sg_x0: std_logic;
signal ce_logic_2800000_sg_x0: std_logic;
signal ce_logic_560_sg_x0: std_logic;
signal ch_out_x0: std_logic_vector(1 downto 0);
signal clk_1400000_sg_x1: std_logic;
signal clk_1_sg_x24: std_logic;
signal clk_22400000_sg_x6: std_logic;
signal clk_2800000_sg_x2: std_logic;
signal clk_5600000_sg_x4: std_logic;
signal clk_560_sg_x0: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal delay1_q_net: std_logic_vector(23 downto 0);
signal delay2_q_net_x2: std_logic_vector(1 downto 0);
signal delay3_q_net: std_logic_vector(23 downto 0);
signal delay_q_net: std_logic_vector(1 downto 0);
signal dout_x0: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x2: std_logic_vector(23 downto 0);
signal monit_cfir_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_cfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_cfir_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_cfir_m_axis_data_tvalid_net_x0: std_logic;
signal monit_cic_event_tlast_unexpected_net_x0: std_logic;
signal monit_cic_m_axis_data_tdata_data_net_x0: std_logic_vector(60 downto 0);
signal monit_cic_m_axis_data_tuser_chan_out_net: std_logic_vector(1 downto 0);
signal monit_cic_m_axis_data_tvalid_net_x0: std_logic;
signal monit_pfir_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_pfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_pfir_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_pfir_m_axis_data_tvalid_net_x0: std_logic;
signal register3_q_net: std_logic_vector(1 downto 0);
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal relational2_op_net: std_logic;
begin
ce_1_sg_x24 <= ce_1;
ce_1400000_sg_x1 <= ce_1400000;
ce_22400000_sg_x6 <= ce_22400000;
ce_2800000_sg_x2 <= ce_2800000;
ce_560_sg_x0 <= ce_560;
ce_5600000_sg_x4 <= ce_5600000;
ce_logic_1400000_sg_x0 <= ce_logic_1400000;
ce_logic_2800000_sg_x0 <= ce_logic_2800000;
ce_logic_560_sg_x0 <= ce_logic_560;
ch_out_x0 <= ch_in;
clk_1_sg_x24 <= clk_1;
clk_1400000_sg_x1 <= clk_1400000;
clk_22400000_sg_x6 <= clk_22400000;
clk_2800000_sg_x2 <= clk_2800000;
clk_560_sg_x0 <= clk_560;
clk_5600000_sg_x4 <= clk_5600000;
dout_x0 <= din;
amp_out <= register_q_net_x3;
ch_out_x1 <= delay2_q_net_x2;
monit_cfir_x0 <= monit_cfir_event_s_data_chanid_incorrect_net_x0;
monit_cic_x0 <= monit_cic_event_tlast_unexpected_net_x0;
monit_pfir_x0 <= monit_pfir_event_s_data_chanid_incorrect_net_x0;
tddm_monit_amp_c <= down_sample1_q_net_x2;
tddm_monit_amp_c_x0 <= down_sample2_q_net_x2;
tddm_monit_amp_c_x1 <= down_sample3_q_net_x2;
tddm_monit_amp_c_x2 <= down_sample4_q_net_x2;
cast2_4b7421c7c9: entity work.cast2_entity_4b7421c7c9
port map (
ce_5600000 => ce_5600000_sg_x4,
clk_5600000 => clk_5600000_sg_x4,
data_in => monit_pfir_m_axis_data_tdata_net_x1,
en => monit_pfir_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x3
);
cast4_4ed908d7fc: entity work.cast4_entity_4ed908d7fc
port map (
ce_2800000 => ce_2800000_sg_x2,
clk_2800000 => clk_2800000_sg_x2,
data_in => monit_cfir_m_axis_data_tdata_net_x1,
en => monit_cfir_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x0
);
constant1: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
delay: entity work.xldelay
generic map (
latency => 3,
reg_retiming => 0,
reset => 0,
width => 2
)
port map (
ce => ce_1400000_sg_x1,
clk => clk_1400000_sg_x1,
d => monit_cic_m_axis_data_tuser_chan_out_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 3,
reg_retiming => 0,
reset => 0,
width => 24
)
port map (
ce => ce_560_sg_x0,
clk => clk_560_sg_x0,
d => dout_x0,
en => '1',
rst => '1',
q => delay1_q_net
);
delay2: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
reset => 0,
width => 2
)
port map (
ce => ce_5600000_sg_x4,
clk => clk_5600000_sg_x4,
d => monit_pfir_m_axis_data_tuser_chanid_net,
en => '1',
rst => '1',
q => delay2_q_net_x2
);
delay3: entity work.xldelay
generic map (
latency => 2,
reg_retiming => 0,
reset => 0,
width => 24
)
port map (
ce => ce_1400000_sg_x1,
clk => clk_1400000_sg_x1,
d => register_q_net_x1,
en => '1',
rst => '1',
q => delay3_q_net
);
monit_cfir: entity work.xlfir_compiler_2acadf5a08d72e0ee15ce4e1ac741dc6
port map (
ce => ce_1_sg_x24,
ce_1400000 => ce_1400000_sg_x1,
ce_2800000 => ce_2800000_sg_x2,
ce_logic_1400000 => ce_logic_1400000_sg_x0,
clk => clk_1_sg_x24,
clk_1400000 => clk_1400000_sg_x1,
clk_2800000 => clk_2800000_sg_x2,
clk_logic_1400000 => clk_1400000_sg_x1,
s_axis_data_tdata => delay3_q_net,
s_axis_data_tuser_chanid => delay_q_net,
src_ce => ce_1400000_sg_x1,
src_clk => clk_1400000_sg_x1,
event_s_data_chanid_incorrect => monit_cfir_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_cfir_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_cfir_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_cfir_m_axis_data_tvalid_net_x0
);
monit_cic: entity work.xlcic_compiler_6efc67831a277bdb0701519c5a976f20
port map (
ce => ce_1_sg_x24,
ce_1400000 => ce_1400000_sg_x1,
ce_560 => ce_560_sg_x0,
ce_logic_560 => ce_logic_560_sg_x0,
clk => clk_1_sg_x24,
clk_1400000 => clk_1400000_sg_x1,
clk_560 => clk_560_sg_x0,
clk_logic_560 => clk_560_sg_x0,
s_axis_data_tdata_data => delay1_q_net,
s_axis_data_tlast => relational2_op_net,
event_tlast_unexpected => monit_cic_event_tlast_unexpected_net_x0,
m_axis_data_tdata_data => monit_cic_m_axis_data_tdata_data_net_x0,
m_axis_data_tuser_chan_out => monit_cic_m_axis_data_tuser_chan_out_net,
m_axis_data_tvalid => monit_cic_m_axis_data_tvalid_net_x0
);
monit_pfir: entity work.xlfir_compiler_1da691037bdf8c1b85b3b4502d6e9610
port map (
ce => ce_1_sg_x24,
ce_2800000 => ce_2800000_sg_x2,
ce_5600000 => ce_5600000_sg_x4,
ce_logic_2800000 => ce_logic_2800000_sg_x0,
clk => clk_1_sg_x24,
clk_2800000 => clk_2800000_sg_x2,
clk_5600000 => clk_5600000_sg_x4,
clk_logic_2800000 => clk_2800000_sg_x2,
s_axis_data_tdata => register_q_net_x0,
s_axis_data_tuser_chanid => register3_q_net,
src_ce => ce_2800000_sg_x2,
src_clk => clk_2800000_sg_x2,
event_s_data_chanid_incorrect => monit_pfir_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_pfir_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_pfir_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_pfir_m_axis_data_tvalid_net_x0
);
reg1_8661a44192: entity work.reg1_entity_8661a44192
port map (
ce_1400000 => ce_1400000_sg_x1,
clk_1400000 => clk_1400000_sg_x1,
din => monit_cic_m_axis_data_tdata_data_net_x0,
en => monit_cic_m_axis_data_tvalid_net_x0,
dout => register_q_net_x1
);
register3: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_2800000_sg_x2,
clk => clk_2800000_sg_x2,
d => monit_cfir_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q => register3_q_net
);
relational2: entity work.relational_83ca2c6a3c
port map (
a => ch_out_x0,
b => constant1_op_net,
ce => ce_560_sg_x0,
clk => clk_560_sg_x0,
clr => '0',
op(0) => relational2_op_net
);
tddm_monit_amp_c_5b2613eff7: entity work.tddm_monit_amp_c_entity_5b2613eff7
port map (
ce_22400000 => ce_22400000_sg_x6,
ce_5600000 => ce_5600000_sg_x4,
clk_22400000 => clk_22400000_sg_x6,
clk_5600000 => clk_5600000_sg_x4,
monit_ch_in => delay2_q_net_x2,
monit_din => register_q_net_x3,
monit_ch0_out => down_sample2_q_net_x2,
monit_ch1_out => down_sample1_q_net_x2,
monit_ch2_out => down_sample3_q_net_x2,
monit_ch3_out => down_sample4_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/TDDM_monit_amp_out"
entity tddm_monit_amp_out_entity_521eb373cc is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
clk_22400000: in std_logic;
clk_5600000: in std_logic;
monit_amp_ch_in: in std_logic_vector(1 downto 0);
monit_amp_din: in std_logic_vector(23 downto 0);
monit_amp_data0_out: out std_logic_vector(23 downto 0);
monit_amp_data1_out: out std_logic_vector(23 downto 0);
monit_amp_data2_out: out std_logic_vector(23 downto 0);
monit_amp_data3_out: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_out_entity_521eb373cc;
architecture structural of tddm_monit_amp_out_entity_521eb373cc is
signal ce_22400000_sg_x8: std_logic;
signal ce_5600000_sg_x6: std_logic;
signal clk_22400000_sg_x8: std_logic;
signal clk_5600000_sg_x6: std_logic;
signal delay2_q_net_x4: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_22400000_sg_x8 <= ce_22400000;
ce_5600000_sg_x6 <= ce_5600000;
clk_22400000_sg_x8 <= clk_22400000;
clk_5600000_sg_x6 <= clk_5600000;
delay2_q_net_x4 <= monit_amp_ch_in;
register_q_net_x5 <= monit_amp_din;
monit_amp_data0_out <= down_sample2_q_net_x1;
monit_amp_data1_out <= down_sample1_q_net_x1;
monit_amp_data2_out <= down_sample3_q_net_x1;
monit_amp_data3_out <= down_sample4_q_net_x1;
tddm_monit_amp_out_int_b60196c7a6: entity work.tddm_monit_amp_c_int_entity_554a834349
port map (
ce_22400000 => ce_22400000_sg_x8,
ce_5600000 => ce_5600000_sg_x6,
ch_in => delay2_q_net_x4,
clk_22400000 => clk_22400000_sg_x8,
clk_5600000 => clk_5600000_sg_x6,
din => register_q_net_x5,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp"
entity monit_amp_entity_44da74e268 is
port (
ce_1: in std_logic;
ce_1400000: in std_logic;
ce_22400000: in std_logic;
ce_2800000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_1400000: in std_logic;
clk_22400000: in std_logic;
clk_2800000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
monit_amp_c: out std_logic_vector(23 downto 0);
monit_amp_c_x0: out std_logic_vector(23 downto 0);
monit_amp_c_x1: out std_logic_vector(23 downto 0);
monit_amp_c_x2: out std_logic_vector(23 downto 0);
monit_amp_c_x3: out std_logic;
monit_amp_c_x4: out std_logic;
monit_amp_c_x5: out std_logic
);
end monit_amp_entity_44da74e268;
architecture structural of monit_amp_entity_44da74e268 is
signal ce_1400000_sg_x2: std_logic;
signal ce_1_sg_x25: std_logic;
signal ce_22400000_sg_x9: std_logic;
signal ce_2800000_sg_x3: std_logic;
signal ce_5600000_sg_x7: std_logic;
signal ce_560_sg_x1: std_logic;
signal ce_logic_1400000_sg_x1: std_logic;
signal ce_logic_2800000_sg_x1: std_logic;
signal ce_logic_560_sg_x1: std_logic;
signal ch_out_x1: std_logic_vector(1 downto 0);
signal clk_1400000_sg_x2: std_logic;
signal clk_1_sg_x25: std_logic;
signal clk_22400000_sg_x9: std_logic;
signal clk_2800000_sg_x3: std_logic;
signal clk_5600000_sg_x7: std_logic;
signal clk_560_sg_x1: std_logic;
signal delay2_q_net_x4: std_logic_vector(1 downto 0);
signal dout_x1: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x4: std_logic_vector(23 downto 0);
signal monit_cfir_event_s_data_chanid_incorrect_net_x1: std_logic;
signal monit_cic_event_tlast_unexpected_net_x1: std_logic;
signal monit_pfir_event_s_data_chanid_incorrect_net_x1: std_logic;
signal register_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_1_sg_x25 <= ce_1;
ce_1400000_sg_x2 <= ce_1400000;
ce_22400000_sg_x9 <= ce_22400000;
ce_2800000_sg_x3 <= ce_2800000;
ce_560_sg_x1 <= ce_560;
ce_5600000_sg_x7 <= ce_5600000;
ce_logic_1400000_sg_x1 <= ce_logic_1400000;
ce_logic_2800000_sg_x1 <= ce_logic_2800000;
ce_logic_560_sg_x1 <= ce_logic_560;
ch_out_x1 <= ch_in;
clk_1_sg_x25 <= clk_1;
clk_1400000_sg_x2 <= clk_1400000;
clk_22400000_sg_x9 <= clk_22400000;
clk_2800000_sg_x3 <= clk_2800000;
clk_560_sg_x1 <= clk_560;
clk_5600000_sg_x7 <= clk_5600000;
dout_x1 <= din;
amp_out0 <= down_sample2_q_net_x4;
amp_out1 <= down_sample1_q_net_x4;
amp_out2 <= down_sample3_q_net_x4;
amp_out3 <= down_sample4_q_net_x4;
monit_amp_c <= down_sample1_q_net_x3;
monit_amp_c_x0 <= down_sample2_q_net_x3;
monit_amp_c_x1 <= down_sample3_q_net_x3;
monit_amp_c_x2 <= down_sample4_q_net_x3;
monit_amp_c_x3 <= monit_cfir_event_s_data_chanid_incorrect_net_x1;
monit_amp_c_x4 <= monit_cic_event_tlast_unexpected_net_x1;
monit_amp_c_x5 <= monit_pfir_event_s_data_chanid_incorrect_net_x1;
monit_amp_c_c83793ea71: entity work.monit_amp_c_entity_c83793ea71
port map (
ce_1 => ce_1_sg_x25,
ce_1400000 => ce_1400000_sg_x2,
ce_22400000 => ce_22400000_sg_x9,
ce_2800000 => ce_2800000_sg_x3,
ce_560 => ce_560_sg_x1,
ce_5600000 => ce_5600000_sg_x7,
ce_logic_1400000 => ce_logic_1400000_sg_x1,
ce_logic_2800000 => ce_logic_2800000_sg_x1,
ce_logic_560 => ce_logic_560_sg_x1,
ch_in => ch_out_x1,
clk_1 => clk_1_sg_x25,
clk_1400000 => clk_1400000_sg_x2,
clk_22400000 => clk_22400000_sg_x9,
clk_2800000 => clk_2800000_sg_x3,
clk_560 => clk_560_sg_x1,
clk_5600000 => clk_5600000_sg_x7,
din => dout_x1,
amp_out => register_q_net_x5,
ch_out_x1 => delay2_q_net_x4,
monit_cfir_x0 => monit_cfir_event_s_data_chanid_incorrect_net_x1,
monit_cic_x0 => monit_cic_event_tlast_unexpected_net_x1,
monit_pfir_x0 => monit_pfir_event_s_data_chanid_incorrect_net_x1,
tddm_monit_amp_c => down_sample1_q_net_x3,
tddm_monit_amp_c_x0 => down_sample2_q_net_x3,
tddm_monit_amp_c_x1 => down_sample3_q_net_x3,
tddm_monit_amp_c_x2 => down_sample4_q_net_x3
);
tddm_monit_amp_out_521eb373cc: entity work.tddm_monit_amp_out_entity_521eb373cc
port map (
ce_22400000 => ce_22400000_sg_x9,
ce_5600000 => ce_5600000_sg_x7,
clk_22400000 => clk_22400000_sg_x9,
clk_5600000 => clk_5600000_sg_x7,
monit_amp_ch_in => delay2_q_net_x4,
monit_amp_din => register_q_net_x5,
monit_amp_data0_out => down_sample2_q_net_x4,
monit_amp_data1_out => down_sample1_q_net_x4,
monit_amp_data2_out => down_sample3_q_net_x4,
monit_amp_data3_out => down_sample4_q_net_x4
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_5b94be40c5 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_5b94be40c5;
architecture structural of tddm_tbt_cordic_entity_5b94be40c5 is
signal ce_35_sg_x0: std_logic;
signal ce_70_sg_x4: std_logic;
signal clk_35_sg_x0: std_logic;
signal clk_70_sg_x4: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal p_amp_out_x0: std_logic_vector(23 downto 0);
signal p_ch_out_x0: std_logic;
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x0 <= ce_35;
ce_70_sg_x4 <= ce_70;
p_ch_out_x0 <= ch_in;
clk_35_sg_x0 <= clk_35;
clk_70_sg_x4 <= clk_70;
p_amp_out_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x4,
dest_clk => clk_70_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x0,
src_clk => clk_35_sg_x0,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x4,
dest_clk => clk_70_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x0,
src_clk => clk_35_sg_x0,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
d => p_amp_out_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
d => p_amp_out_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x0,
b(0) => constant_op_net,
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x0,
b(0) => constant1_op_net,
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic/TDDM_tbt_cordic1"
entity tddm_tbt_cordic1_entity_d3f44a687c is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic1_entity_d3f44a687c;
architecture structural of tddm_tbt_cordic1_entity_d3f44a687c is
signal ce_35_sg_x1: std_logic;
signal ce_70_sg_x5: std_logic;
signal clk_35_sg_x1: std_logic;
signal clk_70_sg_x5: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal p_ch_out_x1: std_logic;
signal p_phase_out_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x1 <= ce_35;
ce_70_sg_x5 <= ce_70;
p_ch_out_x1 <= ch_in;
clk_35_sg_x1 <= clk_35;
clk_70_sg_x5 <= clk_70;
p_phase_out_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x5,
dest_clk => clk_70_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x1,
src_clk => clk_35_sg_x1,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x5,
dest_clk => clk_70_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x1,
src_clk => clk_35_sg_x1,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
d => p_phase_out_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
d => p_phase_out_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x1,
b(0) => constant_op_net,
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x1,
b(0) => constant1_op_net,
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_18d3979a26 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_cordic_ch_in: in std_logic;
tbt_cordic_din: in std_logic_vector(23 downto 0);
tbt_cordic_pin: in std_logic_vector(23 downto 0);
tbt_cordic_data0_out: out std_logic_vector(23 downto 0);
tbt_cordic_data1_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase0_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_18d3979a26;
architecture structural of tddm_tbt_cordic_entity_18d3979a26 is
signal ce_35_sg_x2: std_logic;
signal ce_70_sg_x6: std_logic;
signal clk_35_sg_x2: std_logic;
signal clk_70_sg_x6: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x1: std_logic_vector(23 downto 0);
signal p_ch_out_x2: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
begin
ce_35_sg_x2 <= ce_35;
ce_70_sg_x6 <= ce_70;
clk_35_sg_x2 <= clk_35;
clk_70_sg_x6 <= clk_70;
p_ch_out_x2 <= tbt_cordic_ch_in;
p_amp_out_x1 <= tbt_cordic_din;
p_phase_out_x1 <= tbt_cordic_pin;
tbt_cordic_data0_out <= down_sample2_q_net_x2;
tbt_cordic_data1_out <= down_sample1_q_net_x2;
tbt_cordic_phase0_out <= down_sample2_q_net_x3;
tbt_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_tbt_cordic1_d3f44a687c: entity work.tddm_tbt_cordic1_entity_d3f44a687c
port map (
ce_35 => ce_35_sg_x2,
ce_70 => ce_70_sg_x6,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x2,
clk_70 => clk_70_sg_x6,
din => p_phase_out_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
tddm_tbt_cordic_5b94be40c5: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x2,
ce_70 => ce_70_sg_x6,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x2,
clk_70 => clk_70_sg_x6,
din => p_amp_out_x1,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC"
entity tbt_cordic_entity_232cb2e43e is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ch_in_x0: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in_x0: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out_x0: out std_logic;
tddm_tbt_cordic: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x2: out std_logic_vector(23 downto 0)
);
end tbt_cordic_entity_232cb2e43e;
architecture structural of tbt_cordic_entity_232cb2e43e is
signal ce_1_sg_x26: std_logic;
signal ce_35_sg_x3: std_logic;
signal ce_70_sg_x7: std_logic;
signal ch_in: std_logic;
signal ch_out: std_logic;
signal clk_1_sg_x26: std_logic;
signal clk_35_sg_x3: std_logic;
signal clk_70_sg_x7: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal i: std_logic_vector(24 downto 0);
signal p_amp_out_x2: std_logic_vector(23 downto 0);
signal p_ch_out_x3: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
signal phase: std_logic_vector(23 downto 0);
signal q: std_logic_vector(24 downto 0);
signal real_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic_vector(24 downto 0);
signal register2_q_net_x0: std_logic;
signal register3_q_net_x0: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register6_q_net_x0: std_logic;
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal valid_in: std_logic;
signal valid_out: std_logic;
begin
ce_1_sg_x26 <= ce_1;
ce_35_sg_x3 <= ce_35;
ce_70_sg_x7 <= ce_70;
register2_q_net_x0 <= ch_in_x0;
clk_1_sg_x26 <= clk_1;
clk_35_sg_x3 <= clk_35;
clk_70_sg_x7 <= clk_70;
register3_q_net_x0 <= i_in;
register1_q_net_x1 <= q_in;
register6_q_net_x0 <= valid_in_x0;
amp_out <= p_amp_out_x2;
ch_out_x0 <= p_ch_out_x3;
tddm_tbt_cordic <= down_sample1_q_net_x4;
tddm_tbt_cordic_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => p_phase_out_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => p_amp_out_x2
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => p_ch_out_x3
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_baddbff1b3cb5131976384a2dda9ffff
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
s_axis_cartesian_tdata_imag => q,
s_axis_cartesian_tdata_real => i,
s_axis_cartesian_tuser_user(0) => ch_in,
s_axis_cartesian_tvalid => valid_in,
m_axis_dout_tdata_phase => phase,
m_axis_dout_tdata_real => real_x0,
m_axis_dout_tuser_cartesian_tuser(0) => ch_out,
m_axis_dout_tvalid => valid_out
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d(0) => ch_out,
en(0) => valid_out,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d => reinterpret2_output_port_net,
en(0) => valid_out,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d => reinterpret3_output_port_net,
en(0) => valid_out,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => phase,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => real_x0,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic_18d3979a26: entity work.tddm_tbt_cordic_entity_18d3979a26
port map (
ce_35 => ce_35_sg_x3,
ce_70 => ce_70_sg_x7,
clk_35 => clk_35_sg_x3,
clk_70 => clk_70_sg_x7,
tbt_cordic_ch_in => p_ch_out_x3,
tbt_cordic_din => p_amp_out_x2,
tbt_cordic_pin => p_phase_out_x1,
tbt_cordic_data0_out => down_sample2_q_net_x4,
tbt_cordic_data1_out => down_sample1_q_net_x4,
tbt_cordic_phase0_out => down_sample2_q_net_x5,
tbt_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register6_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q(0) => valid_in
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register1_q_net_x1,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q => q
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register3_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q => i
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register2_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q(0) => ch_in
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/TDDM_TBT/TDDM_tbt_poly_i"
entity tddm_tbt_poly_i_entity_469601736c is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_poly_i_entity_469601736c;
architecture structural of tddm_tbt_poly_i_entity_469601736c is
signal ce_35_sg_x4: std_logic;
signal ce_70_sg_x8: std_logic;
signal clk_35_sg_x4: std_logic;
signal clk_70_sg_x8: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register2_q_net_x1: std_logic;
signal register_q_net: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x4 <= ce_35;
ce_70_sg_x8 <= ce_70;
register2_q_net_x1 <= ch_in;
clk_35_sg_x4 <= clk_35;
clk_70_sg_x8 <= clk_70;
reinterpret_output_port_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x8,
dest_clk => clk_70_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x4,
src_clk => clk_35_sg_x4,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x8,
dest_clk => clk_70_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x4,
src_clk => clk_35_sg_x4,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
d => reinterpret_output_port_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
d => reinterpret_output_port_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => register2_q_net_x1,
b(0) => constant_op_net,
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_d29d27b7b3
port map (
a(0) => register2_q_net_x1,
b => constant1_op_net,
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/TDDM_TBT"
entity tddm_tbt_entity_9ac9f65b0b is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_ch_in: in std_logic;
tbt_i_in: in std_logic_vector(23 downto 0);
tbt_q_in: in std_logic_vector(23 downto 0);
poly35_ch0_i_out: out std_logic_vector(23 downto 0);
poly35_ch0_q_out: out std_logic_vector(23 downto 0);
poly35_ch1_i_out: out std_logic_vector(23 downto 0);
poly35_ch1_q_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_entity_9ac9f65b0b;
architecture structural of tddm_tbt_entity_9ac9f65b0b is
signal ce_35_sg_x6: std_logic;
signal ce_70_sg_x10: std_logic;
signal clk_35_sg_x6: std_logic;
signal clk_70_sg_x10: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register2_q_net_x3: std_logic;
signal reinterpret_output_port_net_x2: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
begin
ce_35_sg_x6 <= ce_35;
ce_70_sg_x10 <= ce_70;
clk_35_sg_x6 <= clk_35;
clk_70_sg_x10 <= clk_70;
register2_q_net_x3 <= tbt_ch_in;
reinterpret_output_port_net_x3 <= tbt_i_in;
reinterpret_output_port_net_x2 <= tbt_q_in;
poly35_ch0_i_out <= down_sample2_q_net_x2;
poly35_ch0_q_out <= down_sample2_q_net_x3;
poly35_ch1_i_out <= down_sample1_q_net_x2;
poly35_ch1_q_out <= down_sample1_q_net_x3;
tddm_tbt_poly_i_469601736c: entity work.tddm_tbt_poly_i_entity_469601736c
port map (
ce_35 => ce_35_sg_x6,
ce_70 => ce_70_sg_x10,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x6,
clk_70 => clk_70_sg_x10,
din => reinterpret_output_port_net_x3,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_poly_q_8011b4e29e: entity work.tddm_tbt_poly_i_entity_469601736c
port map (
ce_35 => ce_35_sg_x6,
ce_70 => ce_70_sg_x10,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x6,
clk_70 => clk_70_sg_x10,
din => reinterpret_output_port_net_x2,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/Trunc"
entity trunc_entity_e5eda8a5ac is
port (
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end trunc_entity_e5eda8a5ac;
architecture structural of trunc_entity_e5eda8a5ac is
signal register1_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal slice_y_net: std_logic_vector(23 downto 0);
begin
register1_q_net_x2 <= din;
dout <= reinterpret_output_port_net_x3;
reinterpret: entity work.reinterpret_4bf1ad328a
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x3
);
slice: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 24,
x_width => 25,
y_width => 24
)
port map (
x => register1_q_net_x2,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim"
entity tbt_poly_decim_entity_4477ec06c2 is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tbt_poly_x0: out std_logic;
tddm_tbt: out std_logic_vector(23 downto 0);
tddm_tbt_x0: out std_logic_vector(23 downto 0);
tddm_tbt_x1: out std_logic_vector(23 downto 0);
tddm_tbt_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end tbt_poly_decim_entity_4477ec06c2;
architecture structural of tbt_poly_decim_entity_4477ec06c2 is
signal ce_1_sg_x27: std_logic;
signal ce_35_sg_x7: std_logic;
signal ce_70_sg_x11: std_logic;
signal ce_logic_1_sg_x12: std_logic;
signal clk_1_sg_x27: std_logic;
signal clk_35_sg_x7: std_logic;
signal clk_70_sg_x11: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x12: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x11: std_logic_vector(23 downto 0);
signal register5_q_net_x11: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x4: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x0: std_logic;
signal tbt_poly_m_axis_data_tdata_path0_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tdata_path1_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tuser_chanid_net: std_logic;
signal tbt_poly_m_axis_data_tvalid_net: std_logic;
begin
ce_1_sg_x27 <= ce_1;
ce_35_sg_x7 <= ce_35;
ce_70_sg_x11 <= ce_70;
ce_logic_1_sg_x12 <= ce_logic_1;
register3_q_net_x12 <= ch_in;
clk_1_sg_x27 <= clk_1;
clk_35_sg_x7 <= clk_35;
clk_70_sg_x11 <= clk_70;
register4_q_net_x11 <= i_in;
register5_q_net_x11 <= q_in;
ch_out <= register2_q_net_x4;
i_out <= register3_q_net_x2;
q_out <= register1_q_net_x3;
tbt_poly_x0 <= tbt_poly_event_s_data_chanid_incorrect_net_x0;
tddm_tbt <= down_sample1_q_net_x4;
tddm_tbt_x0 <= down_sample2_q_net_x4;
tddm_tbt_x1 <= down_sample1_q_net_x5;
tddm_tbt_x2 <= down_sample2_q_net_x5;
valid_out <= register6_q_net_x1;
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d => reinterpret_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register1_q_net_x3
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d(0) => tbt_poly_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q(0) => register2_q_net_x4
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d => reinterpret1_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register3_q_net_x2
);
register6: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d(0) => tbt_poly_m_axis_data_tvalid_net,
en => "1",
rst => "0",
q(0) => register6_q_net_x1
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path1_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path0_net,
output_port => reinterpret1_output_port_net
);
tbt_poly: entity work.xlfir_compiler_6508759a07908936c4d12ef4ec464ceb
port map (
ce => ce_1_sg_x27,
ce_35 => ce_35_sg_x7,
ce_logic_1 => ce_logic_1_sg_x12,
clk => clk_1_sg_x27,
clk_35 => clk_35_sg_x7,
clk_logic_1 => clk_1_sg_x27,
s_axis_data_tdata_path0 => register4_q_net_x11,
s_axis_data_tdata_path1 => register5_q_net_x11,
s_axis_data_tuser_chanid(0) => register3_q_net_x12,
src_ce => ce_1_sg_x27,
src_clk => clk_1_sg_x27,
event_s_data_chanid_incorrect => tbt_poly_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata_path0 => tbt_poly_m_axis_data_tdata_path0_net,
m_axis_data_tdata_path1 => tbt_poly_m_axis_data_tdata_path1_net,
m_axis_data_tuser_chanid(0) => tbt_poly_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => tbt_poly_m_axis_data_tvalid_net
);
tddm_tbt_9ac9f65b0b: entity work.tddm_tbt_entity_9ac9f65b0b
port map (
ce_35 => ce_35_sg_x7,
ce_70 => ce_70_sg_x11,
clk_35 => clk_35_sg_x7,
clk_70 => clk_70_sg_x11,
tbt_ch_in => register2_q_net_x4,
tbt_i_in => reinterpret_output_port_net_x4,
tbt_q_in => reinterpret_output_port_net_x3,
poly35_ch0_i_out => down_sample2_q_net_x4,
poly35_ch0_q_out => down_sample2_q_net_x5,
poly35_ch1_i_out => down_sample1_q_net_x4,
poly35_ch1_q_out => down_sample1_q_net_x5
);
trunc1_841a61ebcc: entity work.trunc_entity_e5eda8a5ac
port map (
din => register3_q_net_x2,
dout => reinterpret_output_port_net_x4
);
trunc_e5eda8a5ac: entity work.trunc_entity_e5eda8a5ac
port map (
din => register1_q_net_x3,
dout => reinterpret_output_port_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0"
entity tbt_amp0_entity_88b1c45f0e is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tbt_cordic: out std_logic_vector(23 downto 0);
tbt_cordic_x0: out std_logic_vector(23 downto 0);
tbt_cordic_x1: out std_logic_vector(23 downto 0);
tbt_cordic_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim: out std_logic;
tbt_poly_decim_x0: out std_logic_vector(23 downto 0);
tbt_poly_decim_x1: out std_logic_vector(23 downto 0);
tbt_poly_decim_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim_x3: out std_logic_vector(23 downto 0)
);
end tbt_amp0_entity_88b1c45f0e;
architecture structural of tbt_amp0_entity_88b1c45f0e is
signal ce_1_sg_x28: std_logic;
signal ce_35_sg_x8: std_logic;
signal ce_70_sg_x12: std_logic;
signal ce_logic_1_sg_x13: std_logic;
signal clk_1_sg_x28: std_logic;
signal clk_35_sg_x8: std_logic;
signal clk_70_sg_x12: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal p_amp_out_x3: std_logic_vector(23 downto 0);
signal p_ch_out_x4: std_logic;
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x13: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x12: std_logic_vector(23 downto 0);
signal register5_q_net_x12: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x1: std_logic;
begin
ce_1_sg_x28 <= ce_1;
ce_35_sg_x8 <= ce_35;
ce_70_sg_x12 <= ce_70;
ce_logic_1_sg_x13 <= ce_logic_1;
register3_q_net_x13 <= ch_in;
clk_1_sg_x28 <= clk_1;
clk_35_sg_x8 <= clk_35;
clk_70_sg_x12 <= clk_70;
register4_q_net_x12 <= i_in;
register5_q_net_x12 <= q_in;
amp_out <= p_amp_out_x3;
ch_out <= p_ch_out_x4;
tbt_cordic <= down_sample1_q_net_x8;
tbt_cordic_x0 <= down_sample2_q_net_x8;
tbt_cordic_x1 <= down_sample1_q_net_x9;
tbt_cordic_x2 <= down_sample2_q_net_x9;
tbt_poly_decim <= tbt_poly_event_s_data_chanid_incorrect_net_x1;
tbt_poly_decim_x0 <= down_sample1_q_net_x10;
tbt_poly_decim_x1 <= down_sample2_q_net_x10;
tbt_poly_decim_x2 <= down_sample1_q_net_x11;
tbt_poly_decim_x3 <= down_sample2_q_net_x11;
tbt_cordic_232cb2e43e: entity work.tbt_cordic_entity_232cb2e43e
port map (
ce_1 => ce_1_sg_x28,
ce_35 => ce_35_sg_x8,
ce_70 => ce_70_sg_x12,
ch_in_x0 => register2_q_net_x4,
clk_1 => clk_1_sg_x28,
clk_35 => clk_35_sg_x8,
clk_70 => clk_70_sg_x12,
i_in => register3_q_net_x2,
q_in => register1_q_net_x3,
valid_in_x0 => register6_q_net_x1,
amp_out => p_amp_out_x3,
ch_out_x0 => p_ch_out_x4,
tddm_tbt_cordic => down_sample1_q_net_x8,
tddm_tbt_cordic_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic_x2 => down_sample2_q_net_x9
);
tbt_poly_decim_4477ec06c2: entity work.tbt_poly_decim_entity_4477ec06c2
port map (
ce_1 => ce_1_sg_x28,
ce_35 => ce_35_sg_x8,
ce_70 => ce_70_sg_x12,
ce_logic_1 => ce_logic_1_sg_x13,
ch_in => register3_q_net_x13,
clk_1 => clk_1_sg_x28,
clk_35 => clk_35_sg_x8,
clk_70 => clk_70_sg_x12,
i_in => register4_q_net_x12,
q_in => register5_q_net_x12,
ch_out => register2_q_net_x4,
i_out => register3_q_net_x2,
q_out => register1_q_net_x3,
tbt_poly_x0 => tbt_poly_event_s_data_chanid_incorrect_net_x1,
tddm_tbt => down_sample1_q_net_x10,
tddm_tbt_x0 => down_sample2_q_net_x10,
tddm_tbt_x1 => down_sample1_q_net_x11,
tddm_tbt_x2 => down_sample2_q_net_x11,
valid_out => register6_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_CORDIC/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_9e99bd206d is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_cordic_ch_in: in std_logic;
tbt_cordic_din: in std_logic_vector(23 downto 0);
tbt_cordic_pin: in std_logic_vector(23 downto 0);
tbt_cordic_ch2_out: out std_logic_vector(23 downto 0);
tbt_cordic_ch3_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase0_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_9e99bd206d;
architecture structural of tddm_tbt_cordic_entity_9e99bd206d is
signal ce_35_sg_x11: std_logic;
signal ce_70_sg_x15: std_logic;
signal clk_35_sg_x11: std_logic;
signal clk_70_sg_x15: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x1: std_logic_vector(23 downto 0);
signal p_ch_out_x2: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
begin
ce_35_sg_x11 <= ce_35;
ce_70_sg_x15 <= ce_70;
clk_35_sg_x11 <= clk_35;
clk_70_sg_x15 <= clk_70;
p_ch_out_x2 <= tbt_cordic_ch_in;
p_amp_out_x1 <= tbt_cordic_din;
p_phase_out_x1 <= tbt_cordic_pin;
tbt_cordic_ch2_out <= down_sample2_q_net_x2;
tbt_cordic_ch3_out <= down_sample1_q_net_x2;
tbt_cordic_phase0_out <= down_sample2_q_net_x3;
tbt_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_tbt_cordic1_d22fbdac88: entity work.tddm_tbt_cordic1_entity_d3f44a687c
port map (
ce_35 => ce_35_sg_x11,
ce_70 => ce_70_sg_x15,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x11,
clk_70 => clk_70_sg_x15,
din => p_phase_out_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
tddm_tbt_cordic_f04a48283a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x11,
ce_70 => ce_70_sg_x15,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x11,
clk_70 => clk_70_sg_x15,
din => p_amp_out_x1,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_CORDIC"
entity tbt_cordic_entity_9dc3371de2 is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ch_in_x0: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in_x0: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out_x0: out std_logic;
tddm_tbt_cordic: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x2: out std_logic_vector(23 downto 0)
);
end tbt_cordic_entity_9dc3371de2;
architecture structural of tbt_cordic_entity_9dc3371de2 is
signal ce_1_sg_x29: std_logic;
signal ce_35_sg_x12: std_logic;
signal ce_70_sg_x16: std_logic;
signal ch_in: std_logic;
signal ch_out: std_logic;
signal clk_1_sg_x29: std_logic;
signal clk_35_sg_x12: std_logic;
signal clk_70_sg_x16: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal i: std_logic_vector(24 downto 0);
signal p_amp_out_x2: std_logic_vector(23 downto 0);
signal p_ch_out_x3: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
signal phase: std_logic_vector(23 downto 0);
signal q: std_logic_vector(24 downto 0);
signal real_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic_vector(24 downto 0);
signal register2_q_net_x0: std_logic;
signal register3_q_net_x0: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register6_q_net_x0: std_logic;
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal valid_in: std_logic;
signal valid_out: std_logic;
begin
ce_1_sg_x29 <= ce_1;
ce_35_sg_x12 <= ce_35;
ce_70_sg_x16 <= ce_70;
register2_q_net_x0 <= ch_in_x0;
clk_1_sg_x29 <= clk_1;
clk_35_sg_x12 <= clk_35;
clk_70_sg_x16 <= clk_70;
register3_q_net_x0 <= i_in;
register1_q_net_x1 <= q_in;
register6_q_net_x0 <= valid_in_x0;
amp_out <= p_amp_out_x2;
ch_out_x0 <= p_ch_out_x3;
tddm_tbt_cordic <= down_sample1_q_net_x4;
tddm_tbt_cordic_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => p_phase_out_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => p_amp_out_x2
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => p_ch_out_x3
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_baddbff1b3cb5131976384a2dda9ffff
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
s_axis_cartesian_tdata_imag => q,
s_axis_cartesian_tdata_real => i,
s_axis_cartesian_tuser_user(0) => ch_in,
s_axis_cartesian_tvalid => valid_in,
m_axis_dout_tdata_phase => phase,
m_axis_dout_tdata_real => real_x0,
m_axis_dout_tuser_cartesian_tuser(0) => ch_out,
m_axis_dout_tvalid => valid_out
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d(0) => ch_out,
en(0) => valid_out,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d => reinterpret2_output_port_net,
en(0) => valid_out,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d => reinterpret3_output_port_net,
en(0) => valid_out,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => phase,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => real_x0,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic_9e99bd206d: entity work.tddm_tbt_cordic_entity_9e99bd206d
port map (
ce_35 => ce_35_sg_x12,
ce_70 => ce_70_sg_x16,
clk_35 => clk_35_sg_x12,
clk_70 => clk_70_sg_x16,
tbt_cordic_ch_in => p_ch_out_x3,
tbt_cordic_din => p_amp_out_x2,
tbt_cordic_pin => p_phase_out_x1,
tbt_cordic_ch2_out => down_sample2_q_net_x4,
tbt_cordic_ch3_out => down_sample1_q_net_x4,
tbt_cordic_phase0_out => down_sample2_q_net_x5,
tbt_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register6_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q(0) => valid_in
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register1_q_net_x1,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q => q
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register3_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q => i
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register2_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q(0) => ch_in
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_poly_decim/TDDM_TBT"
entity tddm_tbt_entity_1f4b61e651 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_ch_in: in std_logic;
tbt_i_in: in std_logic_vector(23 downto 0);
tbt_q_in: in std_logic_vector(23 downto 0);
poly35_ch2_i_out: out std_logic_vector(23 downto 0);
poly35_ch2_q_out: out std_logic_vector(23 downto 0);
poly35_ch3_i_out: out std_logic_vector(23 downto 0);
poly35_ch3_q_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_entity_1f4b61e651;
architecture structural of tddm_tbt_entity_1f4b61e651 is
signal ce_35_sg_x15: std_logic;
signal ce_70_sg_x19: std_logic;
signal clk_35_sg_x15: std_logic;
signal clk_70_sg_x19: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register2_q_net_x3: std_logic;
signal reinterpret_output_port_net_x2: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
begin
ce_35_sg_x15 <= ce_35;
ce_70_sg_x19 <= ce_70;
clk_35_sg_x15 <= clk_35;
clk_70_sg_x19 <= clk_70;
register2_q_net_x3 <= tbt_ch_in;
reinterpret_output_port_net_x3 <= tbt_i_in;
reinterpret_output_port_net_x2 <= tbt_q_in;
poly35_ch2_i_out <= down_sample2_q_net_x2;
poly35_ch2_q_out <= down_sample2_q_net_x3;
poly35_ch3_i_out <= down_sample1_q_net_x2;
poly35_ch3_q_out <= down_sample1_q_net_x3;
tddm_tbt_poly_i_b74b709553: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x15,
ce_70 => ce_70_sg_x19,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x15,
clk_70 => clk_70_sg_x19,
din => reinterpret_output_port_net_x3,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_poly_q_4f85d7362a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x15,
ce_70 => ce_70_sg_x19,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x15,
clk_70 => clk_70_sg_x19,
din => reinterpret_output_port_net_x2,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_poly_decim"
entity tbt_poly_decim_entity_bb6f6b5b6a is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tbt_poly_x0: out std_logic;
tddm_tbt: out std_logic_vector(23 downto 0);
tddm_tbt_x0: out std_logic_vector(23 downto 0);
tddm_tbt_x1: out std_logic_vector(23 downto 0);
tddm_tbt_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end tbt_poly_decim_entity_bb6f6b5b6a;
architecture structural of tbt_poly_decim_entity_bb6f6b5b6a is
signal ce_1_sg_x30: std_logic;
signal ce_35_sg_x16: std_logic;
signal ce_70_sg_x20: std_logic;
signal ce_logic_1_sg_x14: std_logic;
signal clk_1_sg_x30: std_logic;
signal clk_35_sg_x16: std_logic;
signal clk_70_sg_x20: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x13: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x12: std_logic_vector(23 downto 0);
signal register5_q_net_x12: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x4: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x0: std_logic;
signal tbt_poly_m_axis_data_tdata_path0_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tdata_path1_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tuser_chanid_net: std_logic;
signal tbt_poly_m_axis_data_tvalid_net: std_logic;
begin
ce_1_sg_x30 <= ce_1;
ce_35_sg_x16 <= ce_35;
ce_70_sg_x20 <= ce_70;
ce_logic_1_sg_x14 <= ce_logic_1;
register3_q_net_x13 <= ch_in;
clk_1_sg_x30 <= clk_1;
clk_35_sg_x16 <= clk_35;
clk_70_sg_x20 <= clk_70;
register4_q_net_x12 <= i_in;
register5_q_net_x12 <= q_in;
ch_out <= register2_q_net_x4;
i_out <= register3_q_net_x2;
q_out <= register1_q_net_x3;
tbt_poly_x0 <= tbt_poly_event_s_data_chanid_incorrect_net_x0;
tddm_tbt <= down_sample1_q_net_x4;
tddm_tbt_x0 <= down_sample2_q_net_x4;
tddm_tbt_x1 <= down_sample1_q_net_x5;
tddm_tbt_x2 <= down_sample2_q_net_x5;
valid_out <= register6_q_net_x1;
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d => reinterpret_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register1_q_net_x3
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d(0) => tbt_poly_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q(0) => register2_q_net_x4
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d => reinterpret1_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register3_q_net_x2
);
register6: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d(0) => tbt_poly_m_axis_data_tvalid_net,
en => "1",
rst => "0",
q(0) => register6_q_net_x1
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path1_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path0_net,
output_port => reinterpret1_output_port_net
);
tbt_poly: entity work.xlfir_compiler_6508759a07908936c4d12ef4ec464ceb
port map (
ce => ce_1_sg_x30,
ce_35 => ce_35_sg_x16,
ce_logic_1 => ce_logic_1_sg_x14,
clk => clk_1_sg_x30,
clk_35 => clk_35_sg_x16,
clk_logic_1 => clk_1_sg_x30,
s_axis_data_tdata_path0 => register4_q_net_x12,
s_axis_data_tdata_path1 => register5_q_net_x12,
s_axis_data_tuser_chanid(0) => register3_q_net_x13,
src_ce => ce_1_sg_x30,
src_clk => clk_1_sg_x30,
event_s_data_chanid_incorrect => tbt_poly_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata_path0 => tbt_poly_m_axis_data_tdata_path0_net,
m_axis_data_tdata_path1 => tbt_poly_m_axis_data_tdata_path1_net,
m_axis_data_tuser_chanid(0) => tbt_poly_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => tbt_poly_m_axis_data_tvalid_net
);
tddm_tbt_1f4b61e651: entity work.tddm_tbt_entity_1f4b61e651
port map (
ce_35 => ce_35_sg_x16,
ce_70 => ce_70_sg_x20,
clk_35 => clk_35_sg_x16,
clk_70 => clk_70_sg_x20,
tbt_ch_in => register2_q_net_x4,
tbt_i_in => reinterpret_output_port_net_x4,
tbt_q_in => reinterpret_output_port_net_x3,
poly35_ch2_i_out => down_sample2_q_net_x4,
poly35_ch2_q_out => down_sample2_q_net_x5,
poly35_ch3_i_out => down_sample1_q_net_x4,
poly35_ch3_q_out => down_sample1_q_net_x5
);
trunc1_c3e3bdeec5: entity work.trunc_entity_e5eda8a5ac
port map (
din => register3_q_net_x2,
dout => reinterpret_output_port_net_x4
);
trunc_6a2a4db298: entity work.trunc_entity_e5eda8a5ac
port map (
din => register1_q_net_x3,
dout => reinterpret_output_port_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1"
entity tbt_amp1_entity_6e98f85f9f is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tbt_cordic: out std_logic_vector(23 downto 0);
tbt_cordic_x0: out std_logic_vector(23 downto 0);
tbt_cordic_x1: out std_logic_vector(23 downto 0);
tbt_cordic_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim: out std_logic;
tbt_poly_decim_x0: out std_logic_vector(23 downto 0);
tbt_poly_decim_x1: out std_logic_vector(23 downto 0);
tbt_poly_decim_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim_x3: out std_logic_vector(23 downto 0)
);
end tbt_amp1_entity_6e98f85f9f;
architecture structural of tbt_amp1_entity_6e98f85f9f is
signal ce_1_sg_x31: std_logic;
signal ce_35_sg_x17: std_logic;
signal ce_70_sg_x21: std_logic;
signal ce_logic_1_sg_x15: std_logic;
signal clk_1_sg_x31: std_logic;
signal clk_35_sg_x17: std_logic;
signal clk_70_sg_x21: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal p_amp_out_x3: std_logic_vector(23 downto 0);
signal p_ch_out_x4: std_logic;
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x14: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x13: std_logic_vector(23 downto 0);
signal register5_q_net_x13: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x1: std_logic;
begin
ce_1_sg_x31 <= ce_1;
ce_35_sg_x17 <= ce_35;
ce_70_sg_x21 <= ce_70;
ce_logic_1_sg_x15 <= ce_logic_1;
register3_q_net_x14 <= ch_in;
clk_1_sg_x31 <= clk_1;
clk_35_sg_x17 <= clk_35;
clk_70_sg_x21 <= clk_70;
register4_q_net_x13 <= i_in;
register5_q_net_x13 <= q_in;
amp_out <= p_amp_out_x3;
ch_out <= p_ch_out_x4;
tbt_cordic <= down_sample1_q_net_x8;
tbt_cordic_x0 <= down_sample2_q_net_x8;
tbt_cordic_x1 <= down_sample1_q_net_x9;
tbt_cordic_x2 <= down_sample2_q_net_x9;
tbt_poly_decim <= tbt_poly_event_s_data_chanid_incorrect_net_x1;
tbt_poly_decim_x0 <= down_sample1_q_net_x10;
tbt_poly_decim_x1 <= down_sample2_q_net_x10;
tbt_poly_decim_x2 <= down_sample1_q_net_x11;
tbt_poly_decim_x3 <= down_sample2_q_net_x11;
tbt_cordic_9dc3371de2: entity work.tbt_cordic_entity_9dc3371de2
port map (
ce_1 => ce_1_sg_x31,
ce_35 => ce_35_sg_x17,
ce_70 => ce_70_sg_x21,
ch_in_x0 => register2_q_net_x4,
clk_1 => clk_1_sg_x31,
clk_35 => clk_35_sg_x17,
clk_70 => clk_70_sg_x21,
i_in => register3_q_net_x2,
q_in => register1_q_net_x3,
valid_in_x0 => register6_q_net_x1,
amp_out => p_amp_out_x3,
ch_out_x0 => p_ch_out_x4,
tddm_tbt_cordic => down_sample1_q_net_x8,
tddm_tbt_cordic_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic_x2 => down_sample2_q_net_x9
);
tbt_poly_decim_bb6f6b5b6a: entity work.tbt_poly_decim_entity_bb6f6b5b6a
port map (
ce_1 => ce_1_sg_x31,
ce_35 => ce_35_sg_x17,
ce_70 => ce_70_sg_x21,
ce_logic_1 => ce_logic_1_sg_x15,
ch_in => register3_q_net_x14,
clk_1 => clk_1_sg_x31,
clk_35 => clk_35_sg_x17,
clk_70 => clk_70_sg_x21,
i_in => register4_q_net_x13,
q_in => register5_q_net_x13,
ch_out => register2_q_net_x4,
i_out => register3_q_net_x2,
q_out => register1_q_net_x3,
tbt_poly_x0 => tbt_poly_event_s_data_chanid_incorrect_net_x1,
tddm_tbt => down_sample1_q_net_x10,
tddm_tbt_x0 => down_sample2_q_net_x10,
tddm_tbt_x1 => down_sample1_q_net_x11,
tddm_tbt_x2 => down_sample2_q_net_x11,
valid_out => register6_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TDDM_tbt_amp_4ch"
entity tddm_tbt_amp_4ch_entity_9f3ac0073e is
port (
amp_in0: in std_logic_vector(23 downto 0);
amp_in1: in std_logic_vector(23 downto 0);
ce_35: in std_logic;
ce_70: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0)
);
end tddm_tbt_amp_4ch_entity_9f3ac0073e;
architecture structural of tddm_tbt_amp_4ch_entity_9f3ac0073e is
signal ce_35_sg_x20: std_logic;
signal ce_70_sg_x24: std_logic;
signal clk_35_sg_x20: std_logic;
signal clk_70_sg_x24: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x6: std_logic_vector(23 downto 0);
signal p_amp_out_x7: std_logic_vector(23 downto 0);
signal p_ch_out_x7: std_logic;
signal p_ch_out_x8: std_logic;
begin
p_amp_out_x6 <= amp_in0;
p_amp_out_x7 <= amp_in1;
ce_35_sg_x20 <= ce_35;
ce_70_sg_x24 <= ce_70;
p_ch_out_x7 <= ch_in0;
p_ch_out_x8 <= ch_in1;
clk_35_sg_x20 <= clk_35;
clk_70_sg_x24 <= clk_70;
amp_out0 <= down_sample2_q_net_x2;
amp_out1 <= down_sample1_q_net_x2;
amp_out2 <= down_sample2_q_net_x3;
amp_out3 <= down_sample1_q_net_x3;
tddm_tbt_amp0_8f2b25894a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x20,
ce_70 => ce_70_sg_x24,
ch_in => p_ch_out_x7,
clk_35 => clk_35_sg_x20,
clk_70 => clk_70_sg_x24,
din => p_amp_out_x6,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_amp1_0c4a2e4770: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x20,
ce_70 => ce_70_sg_x24,
ch_in => p_ch_out_x8,
clk_35 => clk_35_sg_x20,
clk_70 => clk_70_sg_x24,
din => p_amp_out_x7,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp"
entity tbt_amp_entity_cbd277bb0c is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in0: in std_logic_vector(23 downto 0);
i_in1: in std_logic_vector(23 downto 0);
q_in0: in std_logic_vector(23 downto 0);
q_in1: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
tbt_amp0: out std_logic_vector(23 downto 0);
tbt_amp0_x0: out std_logic_vector(23 downto 0);
tbt_amp0_x1: out std_logic_vector(23 downto 0);
tbt_amp0_x2: out std_logic_vector(23 downto 0);
tbt_amp0_x3: out std_logic;
tbt_amp0_x4: out std_logic_vector(23 downto 0);
tbt_amp0_x5: out std_logic_vector(23 downto 0);
tbt_amp0_x6: out std_logic_vector(23 downto 0);
tbt_amp0_x7: out std_logic_vector(23 downto 0);
tbt_amp1: out std_logic_vector(23 downto 0);
tbt_amp1_x0: out std_logic_vector(23 downto 0);
tbt_amp1_x1: out std_logic_vector(23 downto 0);
tbt_amp1_x2: out std_logic_vector(23 downto 0);
tbt_amp1_x3: out std_logic;
tbt_amp1_x4: out std_logic_vector(23 downto 0);
tbt_amp1_x5: out std_logic_vector(23 downto 0);
tbt_amp1_x6: out std_logic_vector(23 downto 0);
tbt_amp1_x7: out std_logic_vector(23 downto 0)
);
end tbt_amp_entity_cbd277bb0c;
architecture structural of tbt_amp_entity_cbd277bb0c is
signal ce_1_sg_x32: std_logic;
signal ce_35_sg_x21: std_logic;
signal ce_70_sg_x25: std_logic;
signal ce_logic_1_sg_x16: std_logic;
signal clk_1_sg_x32: std_logic;
signal clk_35_sg_x21: std_logic;
signal clk_70_sg_x25: std_logic;
signal down_sample1_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x25: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x25: std_logic_vector(23 downto 0);
signal p_amp_out_x6: std_logic_vector(23 downto 0);
signal p_amp_out_x7: std_logic_vector(23 downto 0);
signal p_ch_out_x7: std_logic;
signal p_ch_out_x8: std_logic;
signal register3_q_net_x15: std_logic;
signal register3_q_net_x16: std_logic;
signal register4_q_net_x14: std_logic_vector(23 downto 0);
signal register4_q_net_x15: std_logic_vector(23 downto 0);
signal register5_q_net_x14: std_logic_vector(23 downto 0);
signal register5_q_net_x15: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x3: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x4: std_logic;
begin
ce_1_sg_x32 <= ce_1;
ce_35_sg_x21 <= ce_35;
ce_70_sg_x25 <= ce_70;
ce_logic_1_sg_x16 <= ce_logic_1;
register3_q_net_x15 <= ch_in0;
register3_q_net_x16 <= ch_in1;
clk_1_sg_x32 <= clk_1;
clk_35_sg_x21 <= clk_35;
clk_70_sg_x25 <= clk_70;
register4_q_net_x14 <= i_in0;
register4_q_net_x15 <= i_in1;
register5_q_net_x14 <= q_in0;
register5_q_net_x15 <= q_in1;
amp_out0 <= down_sample2_q_net_x24;
amp_out1 <= down_sample1_q_net_x24;
amp_out2 <= down_sample2_q_net_x25;
amp_out3 <= down_sample1_q_net_x25;
tbt_amp0 <= down_sample1_q_net_x16;
tbt_amp0_x0 <= down_sample2_q_net_x16;
tbt_amp0_x1 <= down_sample1_q_net_x17;
tbt_amp0_x2 <= down_sample2_q_net_x17;
tbt_amp0_x3 <= tbt_poly_event_s_data_chanid_incorrect_net_x3;
tbt_amp0_x4 <= down_sample1_q_net_x18;
tbt_amp0_x5 <= down_sample2_q_net_x18;
tbt_amp0_x6 <= down_sample1_q_net_x19;
tbt_amp0_x7 <= down_sample2_q_net_x19;
tbt_amp1 <= down_sample1_q_net_x20;
tbt_amp1_x0 <= down_sample2_q_net_x20;
tbt_amp1_x1 <= down_sample1_q_net_x21;
tbt_amp1_x2 <= down_sample2_q_net_x21;
tbt_amp1_x3 <= tbt_poly_event_s_data_chanid_incorrect_net_x4;
tbt_amp1_x4 <= down_sample1_q_net_x22;
tbt_amp1_x5 <= down_sample2_q_net_x22;
tbt_amp1_x6 <= down_sample1_q_net_x23;
tbt_amp1_x7 <= down_sample2_q_net_x23;
tbt_amp0_88b1c45f0e: entity work.tbt_amp0_entity_88b1c45f0e
port map (
ce_1 => ce_1_sg_x32,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ce_logic_1 => ce_logic_1_sg_x16,
ch_in => register3_q_net_x15,
clk_1 => clk_1_sg_x32,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
i_in => register4_q_net_x14,
q_in => register5_q_net_x14,
amp_out => p_amp_out_x6,
ch_out => p_ch_out_x7,
tbt_cordic => down_sample1_q_net_x16,
tbt_cordic_x0 => down_sample2_q_net_x16,
tbt_cordic_x1 => down_sample1_q_net_x17,
tbt_cordic_x2 => down_sample2_q_net_x17,
tbt_poly_decim => tbt_poly_event_s_data_chanid_incorrect_net_x3,
tbt_poly_decim_x0 => down_sample1_q_net_x18,
tbt_poly_decim_x1 => down_sample2_q_net_x18,
tbt_poly_decim_x2 => down_sample1_q_net_x19,
tbt_poly_decim_x3 => down_sample2_q_net_x19
);
tbt_amp1_6e98f85f9f: entity work.tbt_amp1_entity_6e98f85f9f
port map (
ce_1 => ce_1_sg_x32,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ce_logic_1 => ce_logic_1_sg_x16,
ch_in => register3_q_net_x16,
clk_1 => clk_1_sg_x32,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
i_in => register4_q_net_x15,
q_in => register5_q_net_x15,
amp_out => p_amp_out_x7,
ch_out => p_ch_out_x8,
tbt_cordic => down_sample1_q_net_x20,
tbt_cordic_x0 => down_sample2_q_net_x20,
tbt_cordic_x1 => down_sample1_q_net_x21,
tbt_cordic_x2 => down_sample2_q_net_x21,
tbt_poly_decim => tbt_poly_event_s_data_chanid_incorrect_net_x4,
tbt_poly_decim_x0 => down_sample1_q_net_x22,
tbt_poly_decim_x1 => down_sample2_q_net_x22,
tbt_poly_decim_x2 => down_sample1_q_net_x23,
tbt_poly_decim_x3 => down_sample2_q_net_x23
);
tddm_tbt_amp_4ch_9f3ac0073e: entity work.tddm_tbt_amp_4ch_entity_9f3ac0073e
port map (
amp_in0 => p_amp_out_x6,
amp_in1 => p_amp_out_x7,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ch_in0 => p_ch_out_x7,
ch_in1 => p_ch_out_x8,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
amp_out0 => down_sample2_q_net_x24,
amp_out1 => down_sample1_q_net_x24,
amp_out2 => down_sample2_q_net_x25,
amp_out3 => down_sample1_q_net_x25
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_mix/TDM_mix_ch0_1"
entity tdm_mix_ch0_1_entity_b9bb73dd5f is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
rst: in std_logic;
ch_out: out std_logic;
dout: out std_logic_vector(23 downto 0)
);
end tdm_mix_ch0_1_entity_b9bb73dd5f;
architecture structural of tdm_mix_ch0_1_entity_b9bb73dd5f is
signal ce_1_sg_x33: std_logic;
signal ce_2_sg_x31: std_logic;
signal ce_logic_1_sg_x17: std_logic;
signal clk_1_sg_x33: std_logic;
signal clk_2_sg_x31: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant10_op_net_x0: std_logic;
signal mux_sel1_op_net: std_logic;
signal mux_y_net: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register_q_net_x17: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x8: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x9: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x33 <= ce_1;
ce_2_sg_x31 <= ce_2;
ce_logic_1_sg_x17 <= ce_logic_1;
clk_1_sg_x33 <= clk_1;
clk_2_sg_x31 <= clk_2;
reinterpret2_output_port_net_x9 <= din_ch0;
reinterpret2_output_port_net_x8 <= din_ch1;
constant10_op_net_x0 <= rst;
ch_out <= register1_q_net_x4;
dout <= register_q_net_x17;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_1_sg_x17,
clk => clk_1_sg_x33,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
mux: entity work.mux_a2121d82da
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
sel(0) => mux_sel1_op_net,
y => mux_y_net
);
mux_sel1: entity work.counter_41314d726b
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant10_op_net_x0,
op(0) => mux_sel1_op_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
d(0) => mux_sel1_op_net,
en => "1",
rst => "0",
q(0) => register1_q_net_x4
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
d => mux_y_net,
en => "1",
rst => "0",
q => register_q_net_x17
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => reinterpret2_output_port_net_x9,
dest_ce => ce_1_sg_x33,
dest_clk => clk_1_sg_x33,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x31,
src_clk => clk_2_sg_x31,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => reinterpret2_output_port_net_x8,
dest_ce => ce_1_sg_x33,
dest_clk => clk_1_sg_x33,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x31,
src_clk => clk_2_sg_x31,
src_clr => '0',
q => up_sample_ch1_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_mix"
entity tdm_mix_entity_54ce67e6e8 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
din_ch2: in std_logic_vector(23 downto 0);
din_ch3: in std_logic_vector(23 downto 0);
ch_out0: out std_logic;
ch_out1: out std_logic;
dout0: out std_logic_vector(23 downto 0);
dout1: out std_logic_vector(23 downto 0)
);
end tdm_mix_entity_54ce67e6e8;
architecture structural of tdm_mix_entity_54ce67e6e8 is
signal ce_1_sg_x35: std_logic;
signal ce_2_sg_x33: std_logic;
signal ce_logic_1_sg_x19: std_logic;
signal clk_1_sg_x35: std_logic;
signal clk_2_sg_x33: std_logic;
signal constant10_op_net_x0: std_logic;
signal constant11_op_net_x0: std_logic;
signal register1_q_net_x6: std_logic;
signal register1_q_net_x7: std_logic;
signal register_q_net_x19: std_logic_vector(23 downto 0);
signal register_q_net_x20: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x11: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x12: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x13: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x14: std_logic_vector(23 downto 0);
begin
ce_1_sg_x35 <= ce_1;
ce_2_sg_x33 <= ce_2;
ce_logic_1_sg_x19 <= ce_logic_1;
clk_1_sg_x35 <= clk_1;
clk_2_sg_x33 <= clk_2;
reinterpret2_output_port_net_x14 <= din_ch0;
reinterpret2_output_port_net_x11 <= din_ch1;
reinterpret2_output_port_net_x12 <= din_ch2;
reinterpret2_output_port_net_x13 <= din_ch3;
ch_out0 <= register1_q_net_x6;
ch_out1 <= register1_q_net_x7;
dout0 <= register_q_net_x19;
dout1 <= register_q_net_x20;
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net_x0
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
tdm_mix_ch0_1_b9bb73dd5f: entity work.tdm_mix_ch0_1_entity_b9bb73dd5f
port map (
ce_1 => ce_1_sg_x35,
ce_2 => ce_2_sg_x33,
ce_logic_1 => ce_logic_1_sg_x19,
clk_1 => clk_1_sg_x35,
clk_2 => clk_2_sg_x33,
din_ch0 => reinterpret2_output_port_net_x14,
din_ch1 => reinterpret2_output_port_net_x11,
rst => constant10_op_net_x0,
ch_out => register1_q_net_x6,
dout => register_q_net_x19
);
tdm_mix_ch0_2_e9327141fc: entity work.tdm_mix_ch0_1_entity_b9bb73dd5f
port map (
ce_1 => ce_1_sg_x35,
ce_2 => ce_2_sg_x33,
ce_logic_1 => ce_logic_1_sg_x19,
clk_1 => clk_1_sg_x35,
clk_2 => clk_2_sg_x33,
din_ch0 => reinterpret2_output_port_net_x12,
din_ch1 => reinterpret2_output_port_net_x13,
rst => constant11_op_net_x0,
ch_out => register1_q_net_x7,
dout => register_q_net_x20
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit"
entity tdm_monit_entity_6e38292ecb is
port (
ce_1: in std_logic;
ce_2240: in std_logic;
ce_560: in std_logic;
ce_logic_560: in std_logic;
clk_1: in std_logic;
clk_2240: in std_logic;
clk_560: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
din_ch2: in std_logic_vector(23 downto 0);
din_ch3: in std_logic_vector(23 downto 0);
rst: in std_logic;
ch_out: out std_logic_vector(1 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end tdm_monit_entity_6e38292ecb;
architecture structural of tdm_monit_entity_6e38292ecb is
signal ce_1_sg_x36: std_logic;
signal ce_2240_sg_x26: std_logic;
signal ce_560_sg_x2: std_logic;
signal ce_logic_560_sg_x2: std_logic;
signal ch_out_x2: std_logic_vector(1 downto 0);
signal clk_1_sg_x36: std_logic;
signal clk_2240_sg_x26: std_logic;
signal clk_560_sg_x2: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant10_op_net_x0: std_logic;
signal dout_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal mux_sel_op_net: std_logic_vector(1 downto 0);
signal mux_y_net: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch2_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch3_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x36 <= ce_1;
ce_2240_sg_x26 <= ce_2240;
ce_560_sg_x2 <= ce_560;
ce_logic_560_sg_x2 <= ce_logic_560;
clk_1_sg_x36 <= clk_1;
clk_2240_sg_x26 <= clk_2240;
clk_560_sg_x2 <= clk_560;
down_sample2_q_net_x18 <= din_ch0;
down_sample1_q_net_x18 <= din_ch1;
down_sample2_q_net_x19 <= din_ch2;
down_sample1_q_net_x19 <= din_ch3;
constant10_op_net_x0 <= rst;
ch_out <= ch_out_x2;
dout <= dout_x2;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_560_sg_x2,
clk => clk_560_sg_x2,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 560,
latency => 1,
phase => 559,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => mux_sel_op_net,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x36,
src_clk => clk_1_sg_x36,
src_clr => '0',
q => ch_out_x2
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 560,
latency => 1,
phase => 559,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => mux_y_net,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x36,
src_clk => clk_1_sg_x36,
src_clr => '0',
q => dout_x2
);
mux: entity work.mux_f062741975
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
d2 => up_sample_ch2_q_net,
d3 => up_sample_ch3_q_net,
sel => mux_sel_op_net,
y => mux_y_net
);
mux_sel: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_eb46eda57512a5a4",
op_arith => xlUnsigned,
op_width => 2
)
port map (
ce => ce_1_sg_x36,
clk => clk_1_sg_x36,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant10_op_net_x0,
op => mux_sel_op_net
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample2_q_net_x18,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample1_q_net_x18,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch1_q_net
);
up_sample_ch2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample2_q_net_x19,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch2_q_net
);
up_sample_ch3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample1_q_net_x19,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1/downsample"
entity downsample_entity_f33f90217c is
port (
ce_1: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
clk_1: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(1 downto 0);
dout: out std_logic_vector(1 downto 0)
);
end downsample_entity_f33f90217c;
architecture structural of downsample_entity_f33f90217c is
signal ce_1_sg_x37: std_logic;
signal ce_2500_sg_x0: std_logic;
signal ce_5600000_sg_x8: std_logic;
signal clk_1_sg_x37: std_logic;
signal clk_2500_sg_x0: std_logic;
signal clk_5600000_sg_x8: std_logic;
signal down_sample5_q_net: std_logic_vector(1 downto 0);
signal down_sample_q_net_x0: std_logic_vector(1 downto 0);
signal mux_sel_op_net_x0: std_logic_vector(1 downto 0);
begin
ce_1_sg_x37 <= ce_1;
ce_2500_sg_x0 <= ce_2500;
ce_5600000_sg_x8 <= ce_5600000;
clk_1_sg_x37 <= clk_1;
clk_2500_sg_x0 <= clk_2500;
clk_5600000_sg_x8 <= clk_5600000;
mux_sel_op_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => down_sample5_q_net,
dest_ce => ce_5600000_sg_x8,
dest_clk => clk_5600000_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_2500_sg_x0,
src_clk => clk_2500_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 2500,
latency => 1,
phase => 2499,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => mux_sel_op_net_x0,
dest_ce => ce_2500_sg_x0,
dest_clk => clk_2500_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x37,
src_clk => clk_1_sg_x37,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1/downsample1"
entity downsample1_entity_312d531c6b is
port (
ce_1: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
clk_1: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end downsample1_entity_312d531c6b;
architecture structural of downsample1_entity_312d531c6b is
signal ce_1_sg_x38: std_logic;
signal ce_2500_sg_x1: std_logic;
signal ce_5600000_sg_x9: std_logic;
signal clk_1_sg_x38: std_logic;
signal clk_2500_sg_x1: std_logic;
signal clk_5600000_sg_x9: std_logic;
signal down_sample5_q_net: std_logic_vector(25 downto 0);
signal down_sample_q_net_x0: std_logic_vector(25 downto 0);
signal mux_y_net_x0: std_logic_vector(25 downto 0);
begin
ce_1_sg_x38 <= ce_1;
ce_2500_sg_x1 <= ce_2500;
ce_5600000_sg_x9 <= ce_5600000;
clk_1_sg_x38 <= clk_1;
clk_2500_sg_x1 <= clk_2500;
clk_5600000_sg_x9 <= clk_5600000;
mux_y_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => down_sample5_q_net,
dest_ce => ce_5600000_sg_x9,
dest_clk => clk_5600000_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_2500_sg_x1,
src_clk => clk_2500_sg_x1,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 2500,
latency => 1,
phase => 2499,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => mux_y_net_x0,
dest_ce => ce_2500_sg_x1,
dest_clk => clk_2500_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x38,
src_clk => clk_1_sg_x38,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1"
entity tdm_monit_1_entity_746ecf54b0 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
ce_logic_5600000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din_ch0: in std_logic_vector(25 downto 0);
din_ch1: in std_logic_vector(25 downto 0);
din_ch2: in std_logic_vector(25 downto 0);
din_ch3: in std_logic_vector(25 downto 0);
rst: in std_logic;
ch_out: out std_logic_vector(1 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end tdm_monit_1_entity_746ecf54b0;
architecture structural of tdm_monit_1_entity_746ecf54b0 is
signal ce_1_sg_x39: std_logic;
signal ce_22400000_sg_x10: std_logic;
signal ce_2500_sg_x2: std_logic;
signal ce_5600000_sg_x10: std_logic;
signal ce_logic_5600000_sg_x0: std_logic;
signal clk_1_sg_x39: std_logic;
signal clk_22400000_sg_x10: std_logic;
signal clk_2500_sg_x2: std_logic;
signal clk_5600000_sg_x10: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal concat1_y_net_x0: std_logic_vector(25 downto 0);
signal concat2_y_net_x0: std_logic_vector(25 downto 0);
signal concat3_y_net_x0: std_logic_vector(25 downto 0);
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant11_op_net_x0: std_logic;
signal down_sample_q_net_x2: std_logic_vector(1 downto 0);
signal down_sample_q_net_x3: std_logic_vector(25 downto 0);
signal mux_sel_op_net_x0: std_logic_vector(1 downto 0);
signal mux_y_net_x0: std_logic_vector(25 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch2_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch3_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x39 <= ce_1;
ce_22400000_sg_x10 <= ce_22400000;
ce_2500_sg_x2 <= ce_2500;
ce_5600000_sg_x10 <= ce_5600000;
ce_logic_5600000_sg_x0 <= ce_logic_5600000;
clk_1_sg_x39 <= clk_1;
clk_22400000_sg_x10 <= clk_22400000;
clk_2500_sg_x2 <= clk_2500;
clk_5600000_sg_x10 <= clk_5600000;
concat_y_net_x0 <= din_ch0;
concat1_y_net_x0 <= din_ch1;
concat2_y_net_x0 <= din_ch2;
concat3_y_net_x0 <= din_ch3;
constant11_op_net_x0 <= rst;
ch_out <= down_sample_q_net_x2;
dout <= down_sample_q_net_x3;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 26,
q_width => 1
)
port map (
ce => ce_logic_5600000_sg_x0,
clk => clk_5600000_sg_x10,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
downsample1_312d531c6b: entity work.downsample1_entity_312d531c6b
port map (
ce_1 => ce_1_sg_x39,
ce_2500 => ce_2500_sg_x2,
ce_5600000 => ce_5600000_sg_x10,
clk_1 => clk_1_sg_x39,
clk_2500 => clk_2500_sg_x2,
clk_5600000 => clk_5600000_sg_x10,
din => mux_y_net_x0,
dout => down_sample_q_net_x3
);
downsample_f33f90217c: entity work.downsample_entity_f33f90217c
port map (
ce_1 => ce_1_sg_x39,
ce_2500 => ce_2500_sg_x2,
ce_5600000 => ce_5600000_sg_x10,
clk_1 => clk_1_sg_x39,
clk_2500 => clk_2500_sg_x2,
clk_5600000 => clk_5600000_sg_x10,
din => mux_sel_op_net_x0,
dout => down_sample_q_net_x2
);
mux: entity work.mux_187c900130
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
d2 => up_sample_ch2_q_net,
d3 => up_sample_ch3_q_net,
sel => mux_sel_op_net_x0,
y => mux_y_net_x0
);
mux_sel: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_eb46eda57512a5a4",
op_arith => xlUnsigned,
op_width => 2
)
port map (
ce => ce_1_sg_x39,
clk => clk_1_sg_x39,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant11_op_net_x0,
op => mux_sel_op_net_x0
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat1_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch1_q_net
);
up_sample_ch2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat2_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch2_q_net
);
up_sample_ch3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat3_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/convert_filt"
entity convert_filt_entity_fda412c1bf is
port (
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end convert_filt_entity_fda412c1bf;
architecture structural of convert_filt_entity_fda412c1bf is
signal down_sample_q_net_x4: std_logic_vector(25 downto 0);
signal extractor1_dout_net: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x0: std_logic_vector(24 downto 0);
begin
down_sample_q_net_x4 <= din;
dout <= reinterpret5_output_port_net_x0;
extractor1: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample_q_net_x4,
dout => extractor1_dout_net
);
reinterpret5: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor1_dout_net,
output_port => reinterpret5_output_port_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/DataReg_En"
entity datareg_en_entity_79473f9ed1 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(24 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid: out std_logic
);
end datareg_en_entity_79473f9ed1;
architecture structural of datareg_en_entity_79473f9ed1 is
signal ce_1_sg_x40: std_logic;
signal clk_1_sg_x40: std_logic;
signal divider_dout_valid_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x40 <= ce_1;
clk_1_sg_x40 <= clk_1;
reinterpret1_output_port_net_x0 <= din;
divider_dout_valid_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x40,
clk => clk_1_sg_x40,
d(0) => divider_dout_valid_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x40,
clk => clk_1_sg_x40,
d => reinterpret1_output_port_net_x0,
en(0) => divider_dout_valid_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/DataReg_En3"
entity datareg_en3_entity_6643090018 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(24 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid: out std_logic
);
end datareg_en3_entity_6643090018;
architecture structural of datareg_en3_entity_6643090018 is
signal ce_1_sg_x43: std_logic;
signal clk_1_sg_x43: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal delay1_q_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x43 <= ce_1;
clk_1_sg_x43 <= clk_1;
convert_dout_net_x0 <= din;
delay1_q_net_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x43,
clk => clk_1_sg_x43,
d(0) => delay1_q_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x43,
clk => clk_1_sg_x43,
d => convert_dout_net_x0,
en(0) => delay1_q_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/pulse_stretcher"
entity pulse_stretcher_entity_9893378b63 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
clr: in std_logic;
pulse_in: in std_logic;
extd_out: out std_logic
);
end pulse_stretcher_entity_9893378b63;
architecture structural of pulse_stretcher_entity_9893378b63 is
signal ce_1_sg_x44: std_logic;
signal ce_70_x0: std_logic;
signal clk_1_sg_x44: std_logic;
signal inverter_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal register1_q_net_x1: std_logic;
signal register_q_net: std_logic;
begin
ce_1_sg_x44 <= ce_1;
clk_1_sg_x44 <= clk_1;
ce_70_x0 <= clr;
register1_q_net_x1 <= pulse_in;
extd_out <= logical3_y_net_x0;
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x44,
clk => clk_1_sg_x44,
clr => '0',
ip(0) => ce_70_x0,
op(0) => inverter_op_net
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register_q_net,
d1(0) => inverter_op_net,
y(0) => logical1_y_net
);
logical2: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register1_q_net_x1,
d1(0) => logical1_y_net,
y(0) => logical2_y_net
);
logical3: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register1_q_net_x1,
d1(0) => register_q_net,
y(0) => logical3_y_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x44,
clk => clk_1_sg_x44,
d(0) => logical2_y_net,
en => "1",
rst => "0",
q(0) => register_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb"
entity delta_sigma_fofb_entity_ee61e649ea is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_2: in std_logic;
ce_2240: in std_logic;
ce_logic_2240: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_fofb_entity_ee61e649ea;
architecture structural of delta_sigma_fofb_entity_ee61e649ea is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert1_dout_net_x0: std_logic;
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert_dout_net: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_1_sg_x52: std_logic;
signal ce_2240_sg_x27: std_logic;
signal ce_2_sg_x34: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_2240_sg_x0: std_logic;
signal clk_1_sg_x52: std_logic;
signal clk_2240_sg_x27: std_logic;
signal clk_2_sg_x34: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_fofb_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal dividend_valid_x0: std_logic;
signal dividend_valid_x1: std_logic;
signal dividend_valid_x2: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal divisor_valid_x0: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch: std_logic_vector(24 downto 0);
signal down_sample1_q_net: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic;
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample3_q_net: std_logic_vector(24 downto 0);
signal down_sample4_q_net: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample6_q_net: std_logic;
signal down_sample7_q_net: std_logic_vector(24 downto 0);
signal down_sample8_q_net: std_logic;
signal down_sample_q_net: std_logic_vector(25 downto 0);
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net: std_logic_vector(25 downto 0);
signal register11_q_net: std_logic_vector(24 downto 0);
signal register12_q_net: std_logic_vector(24 downto 0);
signal register13_q_net: std_logic_vector(24 downto 0);
signal register14_q_net: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample2_q_net: std_logic_vector(25 downto 0);
signal up_sample4_q_net: std_logic_vector(25 downto 0);
signal up_sample6_q_net: std_logic_vector(25 downto 0);
signal up_sample_q_net: std_logic_vector(25 downto 0);
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x20 <= a;
down_sample1_q_net_x20 <= b;
down_sample2_q_net_x21 <= c;
ce_1_sg_x52 <= ce_1;
ce_2_sg_x34 <= ce_2;
ce_2240_sg_x27 <= ce_2240;
ce_logic_2240_sg_x0 <= ce_logic_2240;
clk_1_sg_x52 <= clk_1;
clk_2_sg_x34 <= clk_2;
clk_2240_sg_x27 <= clk_2240;
down_sample1_q_net_x21 <= d;
del_sig_div_fofb_thres_i_net_x0 <= ds_thres;
q <= assert8_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert12_dout_net_x1;
sum_x0 <= assert11_dout_net_x1;
x <= assert5_dout_net_x1;
x_valid <= assert10_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x20,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample2_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert1_dout_net_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample6_q_net,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample7_q_net,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample8_q_net,
dout(0) => assert12_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample1_q_net,
dout => dout_down_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample5_q_net,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample2_q_net,
dout(0) => valid_ds_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample3_q_net,
dout => assert8_dout_net_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert9_dout_net_x1
);
assert_x0: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert_dout_net
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x20,
b => down_sample2_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x20,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x21,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_2240_sg_x0,
clk => clk_2240_sg_x27,
d(0) => assert_dout_net,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_3225c09afc: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_5b5f4b61b7: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_6643090018: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_79473f9ed1: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d(0) => logical3_y_net_x4,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_y_s_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x34,
src_clk => clk_2_sg_x34,
src_clr => '0',
q => down_sample_q_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => dout_stretch,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample2_q_net
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register11_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample3_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x1,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample4_q_net
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample5_q_net
);
down_sample6: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x2,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample6_q_net
);
down_sample7: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample7_q_net
);
down_sample8: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x3,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample8_q_net
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_f6401a1a3d: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x1
);
pulse_stretcher2_38948aaba0: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x2
);
pulse_stretcher3_816d954034: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x3
);
pulse_stretcher4_5d505b900f: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => assert6_dout_net_x0,
pulse_in => divisor_valid_x0,
extd_out => logical3_y_net_x4
);
pulse_stretcher5_bee4540339: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => re_x0,
pulse_in => dividend_valid_x0,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_f82d879b1c: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => assert1_dout_net_x0,
pulse_in => dividend_valid_x1,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_2406c4a105: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => re_x1,
pulse_in => dividend_valid_x2,
extd_out => logical3_y_net_x7
);
pulse_stretcher_9893378b63: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x0
);
q_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x34,
clk => clk_2_sg_x34,
d => del_sig_div_fofb_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample6_q_net,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample2_q_net,
output_port => divisor_data_x0
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample_q_net,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample4_q_net,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data_x0,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data,
b => down_sample_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_3537d66a2361cd1e",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => sum_s_net
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x0
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => divisor_data,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => divisor_valid_x0
);
up_sample4: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample4_q_net
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x1
);
up_sample6: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register7_q_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample6_q_net
);
up_sample7: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x2
);
x_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample1"
entity downsample1_entity_4c88924603 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end downsample1_entity_4c88924603;
architecture structural of downsample1_entity_4c88924603 is
signal ce_1_sg_x57: std_logic;
signal ce_22400000_sg_x11: std_logic;
signal ce_5000_sg_x0: std_logic;
signal clk_1_sg_x57: std_logic;
signal clk_22400000_sg_x11: std_logic;
signal clk_5000_sg_x0: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal register13_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x57 <= ce_1;
ce_22400000_sg_x11 <= ce_22400000;
ce_5000_sg_x0 <= ce_5000;
clk_1_sg_x57 <= clk_1;
clk_22400000_sg_x11 <= clk_22400000;
clk_5000_sg_x0 <= clk_5000;
register13_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => down_sample5_q_net,
dest_ce => ce_22400000_sg_x11,
dest_clk => clk_22400000_sg_x11,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x0,
src_clk => clk_5000_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net_x0,
dest_ce => ce_5000_sg_x0,
dest_clk => clk_5000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x57,
src_clk => clk_1_sg_x57,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample2"
entity downsample2_entity_891f07b1a7 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic;
dout: out std_logic
);
end downsample2_entity_891f07b1a7;
architecture structural of downsample2_entity_891f07b1a7 is
signal ce_1_sg_x58: std_logic;
signal ce_22400000_sg_x12: std_logic;
signal ce_5000_sg_x1: std_logic;
signal clk_1_sg_x58: std_logic;
signal clk_22400000_sg_x12: std_logic;
signal clk_5000_sg_x1: std_logic;
signal down_sample5_q_net: std_logic;
signal down_sample_q_net_x0: std_logic;
signal logical3_y_net_x0: std_logic;
begin
ce_1_sg_x58 <= ce_1;
ce_22400000_sg_x12 <= ce_22400000;
ce_5000_sg_x1 <= ce_5000;
clk_1_sg_x58 <= clk_1;
clk_22400000_sg_x12 <= clk_22400000;
clk_5000_sg_x1 <= clk_5000;
logical3_y_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => down_sample5_q_net,
dest_ce => ce_22400000_sg_x12,
dest_clk => clk_22400000_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x1,
src_clk => clk_5000_sg_x1,
src_clr => '0',
q(0) => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_5000_sg_x1,
dest_clk => clk_5000_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x58,
src_clk => clk_1_sg_x58,
src_clr => '0',
q(0) => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample3"
entity downsample3_entity_dba589aaee is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end downsample3_entity_dba589aaee;
architecture structural of downsample3_entity_dba589aaee is
signal ce_1_sg_x59: std_logic;
signal ce_22400000_sg_x13: std_logic;
signal ce_5000_sg_x2: std_logic;
signal clk_1_sg_x59: std_logic;
signal clk_22400000_sg_x13: std_logic;
signal clk_5000_sg_x2: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal register12_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x59 <= ce_1;
ce_22400000_sg_x13 <= ce_22400000;
ce_5000_sg_x2 <= ce_5000;
clk_1_sg_x59 <= clk_1;
clk_22400000_sg_x13 <= clk_22400000;
clk_5000_sg_x2 <= clk_5000;
register12_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => down_sample5_q_net,
dest_ce => ce_22400000_sg_x13,
dest_clk => clk_22400000_sg_x13,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x2,
src_clk => clk_5000_sg_x2,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net_x0,
dest_ce => ce_5000_sg_x2,
dest_clk => clk_5000_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x59,
src_clk => clk_1_sg_x59,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample7"
entity downsample7_entity_b85055cb62 is
port (
ce_10000: in std_logic;
ce_2: in std_logic;
ce_44800000: in std_logic;
clk_10000: in std_logic;
clk_2: in std_logic;
clk_44800000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end downsample7_entity_b85055cb62;
architecture structural of downsample7_entity_b85055cb62 is
signal ce_10000_sg_x0: std_logic;
signal ce_2_sg_x35: std_logic;
signal ce_44800000_sg_x0: std_logic;
signal clk_10000_sg_x0: std_logic;
signal clk_2_sg_x35: std_logic;
signal clk_44800000_sg_x0: std_logic;
signal down_sample5_q_net: std_logic_vector(25 downto 0);
signal down_sample_q_net_x0: std_logic_vector(25 downto 0);
signal register14_q_net_x0: std_logic_vector(25 downto 0);
begin
ce_10000_sg_x0 <= ce_10000;
ce_2_sg_x35 <= ce_2;
ce_44800000_sg_x0 <= ce_44800000;
clk_10000_sg_x0 <= clk_10000;
clk_2_sg_x35 <= clk_2;
clk_44800000_sg_x0 <= clk_44800000;
register14_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => down_sample5_q_net,
dest_ce => ce_44800000_sg_x0,
dest_clk => clk_44800000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_10000_sg_x0,
src_clk => clk_10000_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net_x0,
dest_ce => ce_10000_sg_x0,
dest_clk => clk_10000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x35,
src_clk => clk_2_sg_x35,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_copy_pad"
entity upsample_copy_pad_entity_86c97eac4f is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end upsample_copy_pad_entity_86c97eac4f;
architecture structural of upsample_copy_pad_entity_86c97eac4f is
signal ce_1_sg_x73: std_logic;
signal ce_22400000_sg_x19: std_logic;
signal ce_4480_sg_x0: std_logic;
signal clk_1_sg_x73: std_logic;
signal clk_22400000_sg_x19: std_logic;
signal clk_4480_sg_x0: std_logic;
signal register10_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample5_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x73 <= ce_1;
ce_22400000_sg_x19 <= ce_22400000;
ce_4480_sg_x0 <= ce_4480;
clk_1_sg_x73 <= clk_1;
clk_22400000_sg_x19 <= clk_22400000;
clk_4480_sg_x0 <= clk_4480;
register10_q_net_x0 <= din;
dout <= up_sample1_q_net_x0;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => up_sample5_q_net,
dest_ce => ce_1_sg_x73,
dest_clk => clk_1_sg_x73,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x0,
src_clk => clk_4480_sg_x0,
src_clr => '0',
q => up_sample1_q_net_x0
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net_x0,
dest_ce => ce_4480_sg_x0,
dest_clk => clk_4480_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x19,
src_clk => clk_22400000_sg_x19,
src_clr => '0',
q => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_copy_pad1"
entity upsample_copy_pad1_entity_edde199d79 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din_x0: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end upsample_copy_pad1_entity_edde199d79;
architecture structural of upsample_copy_pad1_entity_edde199d79 is
signal ce_1_sg_x74: std_logic;
signal ce_22400000_sg_x20: std_logic;
signal ce_4480_sg_x1: std_logic;
signal clk_1_sg_x74: std_logic;
signal clk_22400000_sg_x20: std_logic;
signal clk_4480_sg_x1: std_logic;
signal din_x1: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample5_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x74 <= ce_1;
ce_22400000_sg_x20 <= ce_22400000;
ce_4480_sg_x1 <= ce_4480;
clk_1_sg_x74 <= clk_1;
clk_22400000_sg_x20 <= clk_22400000;
clk_4480_sg_x1 <= clk_4480;
din_x1 <= din_x0;
dout <= up_sample1_q_net_x0;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => up_sample5_q_net,
dest_ce => ce_1_sg_x74,
dest_clk => clk_1_sg_x74,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x1,
src_clk => clk_4480_sg_x1,
src_clr => '0',
q => up_sample1_q_net_x0
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din_x1,
dest_ce => ce_4480_sg_x1,
dest_clk => clk_4480_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x20,
src_clk => clk_22400000_sg_x20,
src_clr => '0',
q => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_zero_pad"
entity upsample_zero_pad_entity_e334b63be9 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din: in std_logic;
dout: out std_logic
);
end upsample_zero_pad_entity_e334b63be9;
architecture structural of upsample_zero_pad_entity_e334b63be9 is
signal assert13_dout_net_x0: std_logic;
signal ce_1_sg_x77: std_logic;
signal ce_22400000_sg_x23: std_logic;
signal ce_4480_sg_x4: std_logic;
signal clk_1_sg_x77: std_logic;
signal clk_22400000_sg_x23: std_logic;
signal clk_4480_sg_x4: std_logic;
signal up_sample1_q_net_x1: std_logic;
signal up_sample5_q_net: std_logic;
begin
ce_1_sg_x77 <= ce_1;
ce_22400000_sg_x23 <= ce_22400000;
ce_4480_sg_x4 <= ce_4480;
clk_1_sg_x77 <= clk_1;
clk_22400000_sg_x23 <= clk_22400000;
clk_4480_sg_x4 <= clk_4480;
assert13_dout_net_x0 <= din;
dout <= up_sample1_q_net_x1;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => up_sample5_q_net,
dest_ce => ce_1_sg_x77,
dest_clk => clk_1_sg_x77,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x4,
src_clk => clk_4480_sg_x4,
src_clr => '0',
q(0) => up_sample1_q_net_x1
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert13_dout_net_x0,
dest_ce => ce_4480_sg_x4,
dest_clk => clk_4480_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x23,
src_clk => clk_22400000_sg_x23,
src_clr => '0',
q(0) => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit"
entity delta_sigma_monit_entity_a8f8b81626 is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_10000: in std_logic;
ce_2: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
ce_44800000: in std_logic;
ce_5000: in std_logic;
ce_logic_22400000: in std_logic;
clk_1: in std_logic;
clk_10000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
clk_44800000: in std_logic;
clk_5000: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_monit_entity_a8f8b81626;
architecture structural of delta_sigma_monit_entity_a8f8b81626 is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert13_dout_net_x3: std_logic;
signal assert2_dout_net_x0: std_logic;
signal assert4_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert9_dout_net_x1: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_10000_sg_x1: std_logic;
signal ce_1_sg_x81: std_logic;
signal ce_22400000_sg_x27: std_logic;
signal ce_2_sg_x36: std_logic;
signal ce_44800000_sg_x1: std_logic;
signal ce_4480_sg_x8: std_logic;
signal ce_5000_sg_x8: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_22400000_sg_x0: std_logic;
signal clk_10000_sg_x1: std_logic;
signal clk_1_sg_x81: std_logic;
signal clk_22400000_sg_x27: std_logic;
signal clk_2_sg_x36: std_logic;
signal clk_44800000_sg_x1: std_logic;
signal clk_4480_sg_x8: std_logic;
signal clk_5000_sg_x8: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_monit_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din_x1: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch_x0: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal down_sample_q_net_x1: std_logic;
signal down_sample_q_net_x2: std_logic_vector(24 downto 0);
signal down_sample_q_net_x3: std_logic;
signal down_sample_q_net_x4: std_logic_vector(24 downto 0);
signal down_sample_q_net_x5: std_logic;
signal down_sample_q_net_x6: std_logic_vector(25 downto 0);
signal down_sample_q_net_x7: std_logic_vector(24 downto 0);
signal down_sample_q_net_x8: std_logic;
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net_x0: std_logic_vector(25 downto 0);
signal register11_q_net_x0: std_logic_vector(24 downto 0);
signal register12_q_net_x0: std_logic_vector(24 downto 0);
signal register13_q_net_x0: std_logic_vector(24 downto 0);
signal register14_q_net_x0: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net_x0: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x2: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x3: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x4: std_logic;
signal up_sample1_q_net_x5: std_logic;
signal up_sample1_q_net_x6: std_logic;
signal up_sample1_q_net_x7: std_logic;
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x5 <= a;
down_sample1_q_net_x5 <= b;
down_sample3_q_net_x5 <= c;
ce_1_sg_x81 <= ce_1;
ce_10000_sg_x1 <= ce_10000;
ce_2_sg_x36 <= ce_2;
ce_22400000_sg_x27 <= ce_22400000;
ce_4480_sg_x8 <= ce_4480;
ce_44800000_sg_x1 <= ce_44800000;
ce_5000_sg_x8 <= ce_5000;
ce_logic_22400000_sg_x0 <= ce_logic_22400000;
clk_1_sg_x81 <= clk_1;
clk_10000_sg_x1 <= clk_10000;
clk_2_sg_x36 <= clk_2;
clk_22400000_sg_x27 <= clk_22400000;
clk_4480_sg_x8 <= clk_4480;
clk_44800000_sg_x1 <= clk_44800000;
clk_5000_sg_x8 <= clk_5000;
down_sample4_q_net_x5 <= d;
del_sig_div_monit_thres_i_net_x0 <= ds_thres;
q <= assert4_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert10_dout_net_x1;
sum_x0 <= assert5_dout_net_x1;
x <= assert11_dout_net_x1;
x_valid <= assert12_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample1_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample3_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x1,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x2,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x3,
dout(0) => assert12_dout_net_x1
);
assert13: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert13_dout_net_x3
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert2_dout_net_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x7,
dout => assert4_dout_net_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x0,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x4,
dout => dout_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x5,
dout(0) => valid_ds_down_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x8,
dout(0) => assert9_dout_net_x1
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x5,
b => down_sample3_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample3_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_22400000_sg_x0,
clk => clk_22400000_sg_x27,
d(0) => assert13_dout_net_x3,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_0658df0e73: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_b216d22f41: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_352b935ccb: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_8be792d5b9: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d(0) => logical3_y_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_y_s_net
);
downsample1_4c88924603: entity work.downsample1_entity_4c88924603
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register13_q_net_x0,
dout => down_sample_q_net_x0
);
downsample2_891f07b1a7: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x4,
dout => down_sample_q_net_x1
);
downsample3_dba589aaee: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register12_q_net_x0,
dout => down_sample_q_net_x2
);
downsample4_c9912c17cb: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x3,
dout => down_sample_q_net_x3
);
downsample5_5d411d5dea: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => dout_stretch_x0,
dout => down_sample_q_net_x4
);
downsample6_d7e68015e5: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x1,
dout => down_sample_q_net_x5
);
downsample7_b85055cb62: entity work.downsample7_entity_b85055cb62
port map (
ce_10000 => ce_10000_sg_x1,
ce_2 => ce_2_sg_x36,
ce_44800000 => ce_44800000_sg_x1,
clk_10000 => clk_10000_sg_x1,
clk_2 => clk_2_sg_x36,
clk_44800000 => clk_44800000_sg_x1,
din => register14_q_net_x0,
dout => down_sample_q_net_x6
);
downsample8_69d7284f0d: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register11_q_net_x0,
dout => down_sample_q_net_x7
);
downsample9_f5ac9b8db2: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x2,
dout => down_sample_q_net_x8
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_427f70e3c7: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x2
);
pulse_stretcher2_9a61283281: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x3
);
pulse_stretcher3_864c3e16a6: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x4
);
pulse_stretcher4_8dfd1c8928: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => assert6_dout_net_x0,
pulse_in => up_sample1_q_net_x6,
extd_out => logical3_y_net_x0
);
pulse_stretcher5_ac376595d0: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => re_x0,
pulse_in => up_sample1_q_net_x5,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_694b81e6b2: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => assert2_dout_net_x0,
pulse_in => up_sample1_q_net_x4,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_bb8174efbd: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => re_x1,
pulse_in => up_sample1_q_net_x7,
extd_out => logical3_y_net_x7
);
pulse_stretcher_6bf297451d: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x1
);
q_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net_x0
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net_x0
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net_x0
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net_x0
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x36,
clk => clk_2_sg_x36,
d => del_sig_div_monit_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net_x0
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net_x0
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data_x0
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din_x1
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch_x0
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x3,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x2,
output_port => divisor_data
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x1,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x0,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data_x0,
b => down_sample_q_net_x6,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_3537d66a2361cd1e",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => sum_s_net
);
upsample_copy_pad1_edde199d79: entity work.upsample_copy_pad1_entity_edde199d79
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din_x0 => din_x1,
dout => up_sample1_q_net_x1
);
upsample_copy_pad2_46599e345b: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => divisor_data_x0,
dout => up_sample1_q_net_x2
);
upsample_copy_pad3_3571daa38f: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => register7_q_net_x0,
dout => up_sample1_q_net_x3
);
upsample_copy_pad_86c97eac4f: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => register10_q_net_x0,
dout => up_sample1_q_net_x0
);
upsample_zero_pad1_2044d1ec3f: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x5
);
upsample_zero_pad2_7f2f8f8620: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x6
);
upsample_zero_pad3_f0b4acbf28: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x7
);
upsample_zero_pad_e334b63be9: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x4
);
x_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_tbt"
entity delta_sigma_tbt_entity_bbfa8a8a69 is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_2: in std_logic;
ce_70: in std_logic;
ce_logic_70: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_tbt_entity_bbfa8a8a69;
architecture structural of delta_sigma_tbt_entity_bbfa8a8a69 is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert1_dout_net_x0: std_logic;
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert_dout_net: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_1_sg_x94: std_logic;
signal ce_2_sg_x37: std_logic;
signal ce_70_sg_x26: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_70_sg_x0: std_logic;
signal clk_1_sg_x94: std_logic;
signal clk_2_sg_x37: std_logic;
signal clk_70_sg_x26: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_tbt_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal dividend_valid_x0: std_logic;
signal dividend_valid_x1: std_logic;
signal dividend_valid_x2: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal divisor_valid_x0: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch: std_logic_vector(24 downto 0);
signal down_sample1_q_net: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x26: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x27: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic;
signal down_sample2_q_net_x26: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x27: std_logic_vector(23 downto 0);
signal down_sample3_q_net: std_logic_vector(24 downto 0);
signal down_sample4_q_net: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample6_q_net: std_logic;
signal down_sample7_q_net: std_logic_vector(24 downto 0);
signal down_sample8_q_net: std_logic;
signal down_sample_q_net: std_logic_vector(25 downto 0);
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net: std_logic_vector(25 downto 0);
signal register11_q_net: std_logic_vector(24 downto 0);
signal register12_q_net: std_logic_vector(24 downto 0);
signal register13_q_net: std_logic_vector(24 downto 0);
signal register14_q_net: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample2_q_net: std_logic_vector(25 downto 0);
signal up_sample4_q_net: std_logic_vector(25 downto 0);
signal up_sample6_q_net: std_logic_vector(25 downto 0);
signal up_sample_q_net: std_logic_vector(25 downto 0);
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x26 <= a;
down_sample1_q_net_x26 <= b;
down_sample2_q_net_x27 <= c;
ce_1_sg_x94 <= ce_1;
ce_2_sg_x37 <= ce_2;
ce_70_sg_x26 <= ce_70;
ce_logic_70_sg_x0 <= ce_logic_70;
clk_1_sg_x94 <= clk_1;
clk_2_sg_x37 <= clk_2;
clk_70_sg_x26 <= clk_70;
down_sample1_q_net_x27 <= d;
del_sig_div_tbt_thres_i_net_x0 <= ds_thres;
q <= assert8_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert12_dout_net_x1;
sum_x0 <= assert11_dout_net_x1;
x <= assert5_dout_net_x1;
x_valid <= assert10_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample1_q_net_x26,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample2_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert1_dout_net_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample6_q_net,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample7_q_net,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample8_q_net,
dout(0) => assert12_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample1_q_net,
dout => dout_down_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample5_q_net,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample2_q_net,
dout(0) => valid_ds_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample3_q_net,
dout => assert8_dout_net_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert9_dout_net_x1
);
assert_x0: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert_dout_net
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x26,
b => down_sample2_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x26,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x27,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_70_sg_x0,
clk => clk_70_sg_x26,
d(0) => assert_dout_net,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_e5d0399944: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_02a2053e69: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_78179f99cc: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_ed948c360a: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d(0) => logical3_y_net_x4,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_y_s_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x37,
src_clk => clk_2_sg_x37,
src_clr => '0',
q => down_sample_q_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => dout_stretch,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample2_q_net
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register11_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample3_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x1,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample4_q_net
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample5_q_net
);
down_sample6: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x2,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample6_q_net
);
down_sample7: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample7_q_net
);
down_sample8: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x3,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample8_q_net
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_eef5ee33be: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x1
);
pulse_stretcher2_6f5c3f41cf: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x2
);
pulse_stretcher3_e720dfd76f: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x3
);
pulse_stretcher4_0a5eb3f903: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => assert6_dout_net_x0,
pulse_in => divisor_valid_x0,
extd_out => logical3_y_net_x4
);
pulse_stretcher5_b95a604b09: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => re_x0,
pulse_in => dividend_valid_x0,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_e7fb2961d9: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => assert1_dout_net_x0,
pulse_in => dividend_valid_x1,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_6e7eb70147: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => re_x1,
pulse_in => dividend_valid_x2,
extd_out => logical3_y_net_x7
);
pulse_stretcher_f661707a58: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x0
);
q_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x37,
clk => clk_2_sg_x37,
d => del_sig_div_tbt_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample6_q_net,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample2_q_net,
output_port => divisor_data_x0
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample_q_net,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample4_q_net,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data_x0,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data,
b => down_sample_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_3537d66a2361cd1e",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => sum_s_net
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x0
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => divisor_data,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => divisor_valid_x0
);
up_sample4: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample4_q_net
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x1
);
up_sample6: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register7_q_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample6_q_net
);
up_sample7: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x2
);
x_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/Cast1/format1"
entity format1_entity_a98b06306e is
port (
ce_56000000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end format1_entity_a98b06306e;
architecture structural of format1_entity_a98b06306e is
signal ce_56000000_sg_x0: std_logic;
signal clk_56000000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal monit_pos_1_c_m_axis_data_tdata_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net: std_logic_vector(25 downto 0);
begin
ce_56000000_sg_x0 <= ce_56000000;
clk_56000000_sg_x0 <= clk_56000000;
monit_pos_1_c_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 24,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 24,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_56000000_sg_x0,
clk => clk_56000000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_pos_1_c_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/Cast1"
entity cast1_entity_3d447d0833 is
port (
ce_56000000: in std_logic;
clk_56000000: in std_logic;
data_in: in std_logic_vector(25 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(24 downto 0);
vld_out: out std_logic
);
end cast1_entity_3d447d0833;
architecture structural of cast1_entity_3d447d0833 is
signal ce_56000000_sg_x1: std_logic;
signal clk_56000000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal monit_pos_1_c_m_axis_data_tdata_net_x1: std_logic_vector(25 downto 0);
signal monit_pos_1_c_m_axis_data_tvalid_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_56000000_sg_x1 <= ce_56000000;
clk_56000000_sg_x1 <= clk_56000000;
monit_pos_1_c_m_axis_data_tdata_net_x1 <= data_in;
monit_pos_1_c_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
vld_out <= register1_q_net_x0;
format1_a98b06306e: entity work.format1_entity_a98b06306e
port map (
ce_56000000 => ce_56000000_sg_x1,
clk_56000000 => clk_56000000_sg_x1,
din => monit_pos_1_c_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_56000000_sg_x1,
clk => clk_56000000_sg_x1,
d(0) => monit_pos_1_c_m_axis_data_tvalid_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x1,
clk => clk_56000000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_pos_1_c_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/TDDM_monit_pos_1_out/TDDM_monit_pos_1_out_int"
entity tddm_monit_pos_1_out_int_entity_3405798202 is
port (
ce_224000000: in std_logic;
ce_56000000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_224000000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout_ch0: out std_logic_vector(25 downto 0);
dout_ch1: out std_logic_vector(25 downto 0);
dout_ch2: out std_logic_vector(25 downto 0);
dout_ch3: out std_logic_vector(25 downto 0)
);
end tddm_monit_pos_1_out_int_entity_3405798202;
architecture structural of tddm_monit_pos_1_out_int_entity_3405798202 is
signal ce_224000000_sg_x4: std_logic;
signal ce_56000000_sg_x2: std_logic;
signal clk_224000000_sg_x4: std_logic;
signal clk_56000000_sg_x2: std_logic;
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant3_op_net: std_logic_vector(1 downto 0);
signal constant4_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x0: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(25 downto 0);
signal register2_q_net: std_logic_vector(25 downto 0);
signal register3_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal register_q_net_x1: std_logic_vector(1 downto 0);
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational3_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_224000000_sg_x4 <= ce_224000000;
ce_56000000_sg_x2 <= ce_56000000;
register_q_net_x1 <= ch_in;
clk_224000000_sg_x4 <= clk_224000000;
clk_56000000_sg_x2 <= clk_56000000;
concat_y_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
dout_ch2 <= down_sample3_q_net_x0;
dout_ch3 <= down_sample4_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant3: entity work.constant_a7e2bb9e12
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant3_op_net
);
constant4: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant_x0: entity work.constant_3a9a3daeb9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register1_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register_q_net_x0,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample2_q_net_x0
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register2_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample3_q_net_x0
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register3_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample4_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register2: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational2_op_net,
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational3_op_net,
rst => "0",
q => register3_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net_x0
);
relational: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant1_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant3_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational2_op_net
);
relational3: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant4_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational3_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/TDDM_monit_pos_1_out"
entity tddm_monit_pos_1_out_entity_1d58a51dbf is
port (
ce_224000000: in std_logic;
ce_56000000: in std_logic;
clk_224000000: in std_logic;
clk_56000000: in std_logic;
monit_pos_1_ch_in: in std_logic_vector(1 downto 0);
monit_pos_1_din: in std_logic_vector(25 downto 0);
monit_pos_1_q_out: out std_logic_vector(25 downto 0);
monit_pos_1_sum_out: out std_logic_vector(25 downto 0);
monit_pos_1_x_out: out std_logic_vector(25 downto 0);
monit_pos_1_y_out: out std_logic_vector(25 downto 0)
);
end tddm_monit_pos_1_out_entity_1d58a51dbf;
architecture structural of tddm_monit_pos_1_out_entity_1d58a51dbf is
signal ce_224000000_sg_x5: std_logic;
signal ce_56000000_sg_x3: std_logic;
signal clk_224000000_sg_x5: std_logic;
signal clk_56000000_sg_x3: std_logic;
signal concat_y_net_x1: std_logic_vector(25 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(25 downto 0);
signal register_q_net_x2: std_logic_vector(1 downto 0);
begin
ce_224000000_sg_x5 <= ce_224000000;
ce_56000000_sg_x3 <= ce_56000000;
clk_224000000_sg_x5 <= clk_224000000;
clk_56000000_sg_x3 <= clk_56000000;
register_q_net_x2 <= monit_pos_1_ch_in;
concat_y_net_x1 <= monit_pos_1_din;
monit_pos_1_q_out <= down_sample3_q_net_x1;
monit_pos_1_sum_out <= down_sample4_q_net_x1;
monit_pos_1_x_out <= down_sample2_q_net_x1;
monit_pos_1_y_out <= down_sample1_q_net_x1;
tddm_monit_pos_1_out_int_3405798202: entity work.tddm_monit_pos_1_out_int_entity_3405798202
port map (
ce_224000000 => ce_224000000_sg_x5,
ce_56000000 => ce_56000000_sg_x3,
ch_in => register_q_net_x2,
clk_224000000 => clk_224000000_sg_x5,
clk_56000000 => clk_56000000_sg_x3,
din => concat_y_net_x1,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1"
entity monit_pos_1_entity_522c8cf08d is
port (
ce_1: in std_logic;
ce_224000000: in std_logic;
ce_5600000: in std_logic;
ce_56000000: in std_logic;
ce_logic_5600000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_224000000: in std_logic;
clk_5600000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(24 downto 0);
monit_1_pos_q: out std_logic_vector(24 downto 0);
monit_1_pos_x: out std_logic_vector(24 downto 0);
monit_1_pos_y: out std_logic_vector(24 downto 0);
monit_1_sum: out std_logic_vector(24 downto 0);
monit_1_vld_q: out std_logic;
monit_1_vld_sum: out std_logic;
monit_1_vld_x: out std_logic;
monit_1_vld_y: out std_logic;
monit_pos_1_c_x0: out std_logic
);
end monit_pos_1_entity_522c8cf08d;
architecture structural of monit_pos_1_entity_522c8cf08d is
signal ce_1_sg_x95: std_logic;
signal ce_224000000_sg_x6: std_logic;
signal ce_56000000_sg_x4: std_logic;
signal ce_5600000_sg_x11: std_logic;
signal ce_logic_5600000_sg_x1: std_logic;
signal clk_1_sg_x95: std_logic;
signal clk_224000000_sg_x6: std_logic;
signal clk_56000000_sg_x4: std_logic;
signal clk_5600000_sg_x11: std_logic;
signal concat_y_net_x1: std_logic_vector(25 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample_q_net_x3: std_logic_vector(1 downto 0);
signal extractor1_dout_net: std_logic_vector(24 downto 0);
signal extractor1_vld_out_net: std_logic;
signal extractor2_dout_net: std_logic_vector(24 downto 0);
signal extractor2_vld_out_net: std_logic;
signal extractor3_dout_net: std_logic_vector(24 downto 0);
signal extractor3_vld_out_net: std_logic;
signal extractor4_dout_net: std_logic_vector(24 downto 0);
signal extractor4_vld_out_net: std_logic;
signal monit_pos_1_c_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_pos_1_c_m_axis_data_tdata_net_x1: std_logic_vector(25 downto 0);
signal monit_pos_1_c_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_pos_1_c_m_axis_data_tvalid_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(1 downto 0);
signal reinterpret1_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x1: std_logic_vector(24 downto 0);
signal ufix_to_bool1_dout_net_x1: std_logic;
signal ufix_to_bool2_dout_net_x1: std_logic;
signal ufix_to_bool3_dout_net_x1: std_logic;
signal ufix_to_bool_dout_net_x1: std_logic;
begin
ce_1_sg_x95 <= ce_1;
ce_224000000_sg_x6 <= ce_224000000;
ce_5600000_sg_x11 <= ce_5600000;
ce_56000000_sg_x4 <= ce_56000000;
ce_logic_5600000_sg_x1 <= ce_logic_5600000;
down_sample_q_net_x3 <= ch_in;
clk_1_sg_x95 <= clk_1;
clk_224000000_sg_x6 <= clk_224000000;
clk_5600000_sg_x11 <= clk_5600000;
clk_56000000_sg_x4 <= clk_56000000;
reinterpret5_output_port_net_x1 <= din;
monit_1_pos_q <= reinterpret2_output_port_net_x1;
monit_1_pos_x <= reinterpret3_output_port_net_x1;
monit_1_pos_y <= reinterpret1_output_port_net_x1;
monit_1_sum <= reinterpret4_output_port_net_x1;
monit_1_vld_q <= ufix_to_bool2_dout_net_x1;
monit_1_vld_sum <= ufix_to_bool3_dout_net_x1;
monit_1_vld_x <= ufix_to_bool_dout_net_x1;
monit_1_vld_y <= ufix_to_bool1_dout_net_x1;
monit_pos_1_c_x0 <= monit_pos_1_c_event_s_data_chanid_incorrect_net_x0;
cast1_3d447d0833: entity work.cast1_entity_3d447d0833
port map (
ce_56000000 => ce_56000000_sg_x4,
clk_56000000 => clk_56000000_sg_x4,
data_in => monit_pos_1_c_m_axis_data_tdata_net_x1,
en => monit_pos_1_c_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x0,
vld_out => register1_q_net_x0
);
concat: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => register1_q_net_x0,
in1 => reinterpret5_output_port_net,
y => concat_y_net_x1
);
extractor1: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample3_q_net_x1,
dout => extractor1_dout_net,
vld_out(0) => extractor1_vld_out_net
);
extractor2: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample1_q_net_x1,
dout => extractor2_dout_net,
vld_out(0) => extractor2_vld_out_net
);
extractor3: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample4_q_net_x1,
dout => extractor3_dout_net,
vld_out(0) => extractor3_vld_out_net
);
extractor4: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample2_q_net_x1,
dout => extractor4_dout_net,
vld_out(0) => extractor4_vld_out_net
);
monit_pos_1_c: entity work.xlfir_compiler_eebfed0cb0075aa32aca169bb967f58b
port map (
ce => ce_1_sg_x95,
ce_5600000 => ce_5600000_sg_x11,
ce_56000000 => ce_56000000_sg_x4,
ce_logic_5600000 => ce_logic_5600000_sg_x1,
clk => clk_1_sg_x95,
clk_5600000 => clk_5600000_sg_x11,
clk_56000000 => clk_56000000_sg_x4,
clk_logic_5600000 => clk_5600000_sg_x11,
s_axis_data_tdata => reinterpret5_output_port_net_x1,
s_axis_data_tuser_chanid => down_sample_q_net_x3,
src_ce => ce_5600000_sg_x11,
src_clk => clk_5600000_sg_x11,
event_s_data_chanid_incorrect => monit_pos_1_c_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_pos_1_c_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_pos_1_c_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_pos_1_c_m_axis_data_tvalid_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_56000000_sg_x4,
clk => clk_56000000_sg_x4,
d => monit_pos_1_c_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q => register_q_net_x2
);
reinterpret1: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor2_dout_net,
output_port => reinterpret1_output_port_net_x1
);
reinterpret2: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor1_dout_net,
output_port => reinterpret2_output_port_net_x1
);
reinterpret3: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor4_dout_net,
output_port => reinterpret3_output_port_net_x1
);
reinterpret4: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor3_dout_net,
output_port => reinterpret4_output_port_net_x1
);
reinterpret5: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register_q_net_x0,
output_port => reinterpret5_output_port_net
);
tddm_monit_pos_1_out_1d58a51dbf: entity work.tddm_monit_pos_1_out_entity_1d58a51dbf
port map (
ce_224000000 => ce_224000000_sg_x6,
ce_56000000 => ce_56000000_sg_x4,
clk_224000000 => clk_224000000_sg_x6,
clk_56000000 => clk_56000000_sg_x4,
monit_pos_1_ch_in => register_q_net_x2,
monit_pos_1_din => concat_y_net_x1,
monit_pos_1_q_out => down_sample3_q_net_x1,
monit_pos_1_sum_out => down_sample4_q_net_x1,
monit_pos_1_x_out => down_sample2_q_net_x1,
monit_pos_1_y_out => down_sample1_q_net_x1
);
ufix_to_bool: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor4_vld_out_net,
en => "1",
dout(0) => ufix_to_bool_dout_net_x1
);
ufix_to_bool1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor2_vld_out_net,
en => "1",
dout(0) => ufix_to_bool1_dout_net_x1
);
ufix_to_bool2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor1_vld_out_net,
en => "1",
dout(0) => ufix_to_bool2_dout_net_x1
);
ufix_to_bool3: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor3_vld_out_net,
en => "1",
dout(0) => ufix_to_bool3_dout_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066"
entity ddc_bpm_476_066 is
port (
adc_ch0_i: in std_logic_vector(15 downto 0);
adc_ch1_i: in std_logic_vector(15 downto 0);
adc_ch2_i: in std_logic_vector(15 downto 0);
adc_ch3_i: in std_logic_vector(15 downto 0);
ce_1: in std_logic;
ce_10000: in std_logic;
ce_1120: in std_logic;
ce_1400000: in std_logic;
ce_2: in std_logic;
ce_2240: in std_logic;
ce_22400000: in std_logic;
ce_224000000: in std_logic;
ce_2500: in std_logic;
ce_2800000: in std_logic;
ce_35: in std_logic;
ce_4480: in std_logic;
ce_44800000: in std_logic;
ce_5000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_56000000: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2240: in std_logic;
ce_logic_22400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ce_logic_5600000: in std_logic;
ce_logic_70: in std_logic;
clk_1: in std_logic;
clk_10000: in std_logic;
clk_1120: in std_logic;
clk_1400000: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
clk_22400000: in std_logic;
clk_224000000: in std_logic;
clk_2500: in std_logic;
clk_2800000: in std_logic;
clk_35: in std_logic;
clk_4480: in std_logic;
clk_44800000: in std_logic;
clk_5000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
clk_56000000: in std_logic;
clk_70: in std_logic;
dds_config_valid_ch0_i: in std_logic;
dds_config_valid_ch1_i: in std_logic;
dds_config_valid_ch2_i: in std_logic;
dds_config_valid_ch3_i: in std_logic;
dds_pinc_ch0_i: in std_logic_vector(29 downto 0);
dds_pinc_ch1_i: in std_logic_vector(29 downto 0);
dds_pinc_ch2_i: in std_logic_vector(29 downto 0);
dds_pinc_ch3_i: in std_logic_vector(29 downto 0);
dds_poff_ch0_i: in std_logic_vector(29 downto 0);
dds_poff_ch1_i: in std_logic_vector(29 downto 0);
dds_poff_ch2_i: in std_logic_vector(29 downto 0);
dds_poff_ch3_i: in std_logic_vector(29 downto 0);
del_sig_div_fofb_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_monit_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_tbt_thres_i: in std_logic_vector(25 downto 0);
ksum_i: in std_logic_vector(24 downto 0);
kx_i: in std_logic_vector(24 downto 0);
ky_i: in std_logic_vector(24 downto 0);
adc_ch0_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o: out std_logic_vector(15 downto 0);
bpf_ch0_o: out std_logic_vector(23 downto 0);
bpf_ch1_o: out std_logic_vector(23 downto 0);
bpf_ch2_o: out std_logic_vector(23 downto 0);
bpf_ch3_o: out std_logic_vector(23 downto 0);
cic_fofb_q_01_missing_o: out std_logic;
cic_fofb_q_23_missing_o: out std_logic;
fofb_amp_ch0_o: out std_logic_vector(23 downto 0);
fofb_amp_ch1_o: out std_logic_vector(23 downto 0);
fofb_amp_ch2_o: out std_logic_vector(23 downto 0);
fofb_amp_ch3_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o: out std_logic_vector(23 downto 0);
fofb_pha_ch0_o: out std_logic_vector(23 downto 0);
fofb_pha_ch1_o: out std_logic_vector(23 downto 0);
fofb_pha_ch2_o: out std_logic_vector(23 downto 0);
fofb_pha_ch3_o: out std_logic_vector(23 downto 0);
mix_ch0_i_o: out std_logic_vector(23 downto 0);
mix_ch0_q_o: out std_logic_vector(23 downto 0);
mix_ch1_i_o: out std_logic_vector(23 downto 0);
mix_ch1_q_o: out std_logic_vector(23 downto 0);
mix_ch2_i_o: out std_logic_vector(23 downto 0);
mix_ch2_q_o: out std_logic_vector(23 downto 0);
mix_ch3_i_o: out std_logic_vector(23 downto 0);
mix_ch3_q_o: out std_logic_vector(23 downto 0);
monit_amp_ch0_o: out std_logic_vector(23 downto 0);
monit_amp_ch1_o: out std_logic_vector(23 downto 0);
monit_amp_ch2_o: out std_logic_vector(23 downto 0);
monit_amp_ch3_o: out std_logic_vector(23 downto 0);
monit_cfir_incorrect_o: out std_logic;
monit_cic_unexpected_o: out std_logic;
monit_pfir_incorrect_o: out std_logic;
monit_pos_1_incorrect_o: out std_logic;
q_fofb_o: out std_logic_vector(25 downto 0);
q_fofb_valid_o: out std_logic;
q_monit_1_o: out std_logic_vector(25 downto 0);
q_monit_1_valid_o: out std_logic;
q_monit_o: out std_logic_vector(25 downto 0);
q_monit_valid_o: out std_logic;
q_tbt_o: out std_logic_vector(25 downto 0);
q_tbt_valid_o: out std_logic;
sum_fofb_o: out std_logic_vector(25 downto 0);
sum_fofb_valid_o: out std_logic;
sum_monit_1_o: out std_logic_vector(25 downto 0);
sum_monit_1_valid_o: out std_logic;
sum_monit_o: out std_logic_vector(25 downto 0);
sum_monit_valid_o: out std_logic;
sum_tbt_o: out std_logic_vector(25 downto 0);
sum_tbt_valid_o: out std_logic;
tbt_amp_ch0_o: out std_logic_vector(23 downto 0);
tbt_amp_ch1_o: out std_logic_vector(23 downto 0);
tbt_amp_ch2_o: out std_logic_vector(23 downto 0);
tbt_amp_ch3_o: out std_logic_vector(23 downto 0);
tbt_decim_ch01_incorrect_o: out std_logic;
tbt_decim_ch0_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch23_incorrect_o: out std_logic;
tbt_decim_ch2_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o: out std_logic_vector(23 downto 0);
tbt_pha_ch0_o: out std_logic_vector(23 downto 0);
tbt_pha_ch1_o: out std_logic_vector(23 downto 0);
tbt_pha_ch2_o: out std_logic_vector(23 downto 0);
tbt_pha_ch3_o: out std_logic_vector(23 downto 0);
x_fofb_o: out std_logic_vector(25 downto 0);
x_fofb_valid_o: out std_logic;
x_monit_1_o: out std_logic_vector(25 downto 0);
x_monit_1_valid_o: out std_logic;
x_monit_o: out std_logic_vector(25 downto 0);
x_monit_valid_o: out std_logic;
x_tbt_o: out std_logic_vector(25 downto 0);
x_tbt_valid_o: out std_logic;
y_fofb_o: out std_logic_vector(25 downto 0);
y_fofb_valid_o: out std_logic;
y_monit_1_o: out std_logic_vector(25 downto 0);
y_monit_1_valid_o: out std_logic;
y_monit_o: out std_logic_vector(25 downto 0);
y_monit_valid_o: out std_logic;
y_tbt_o: out std_logic_vector(25 downto 0);
y_tbt_valid_o: out std_logic
);
end ddc_bpm_476_066;
architecture structural of ddc_bpm_476_066 is
attribute core_generation_info: string;
attribute core_generation_info of structural : architecture is "ddc_bpm_476_066,sysgen_core,{clock_period=4.44116092,clocking=Clock_Enables,compilation=HDL_Netlist,sample_periods=1.00000000000 2.00000000000 35.00000000000 70.00000000000 560.00000000000 1120.00000000000 2240.00000000000 2500.00000000000 4480.00000000000 5000.00000000000 10000.00000000000 1400000.00000000000 2800000.00000000000 5600000.00000000000 22400000.00000000000 44800000.00000000000 56000000.00000000000 224000000.00000000000,testbench=0,total_blocks=3351,xilinx_adder_subtracter_block=30,xilinx_arithmetic_relational_operator_block=66,xilinx_assert_block=55,xilinx_bit_slice_extractor_block=20,xilinx_bitbasher_block=5,xilinx_bitwise_expression_evaluator_block=3,xilinx_black_box_block=1,xilinx_bus_concatenator_block=9,xilinx_bus_multiplexer_block=8,xilinx_cic_compiler_3_0_block=5,xilinx_clock_enable_probe_block=11,xilinx_complex_multiplier_5_0__block=2,xilinx_constant_block_block=83,xilinx_cordic_5_0_block=4,xilinx_counter_block=8,xilinx_delay_block=59,xilinx_divider_generator_4_0_block=9,xilinx_down_sampler_block=118,xilinx_fir_compiler_6_3_block=5,xilinx_gateway_in_block=22,xilinx_gateway_out_block=233,xilinx_inverter_block=24,xilinx_logical_block_block=72,xilinx_multiplier_block=16,xilinx_register_block=264,xilinx_sample_time_block_block=88,xilinx_system_generator_block=1,xilinx_type_converter_block=23,xilinx_type_reinterpreter_block=94,xilinx_up_sampler_block=68,xilinx_wavescope_block=2,}";
signal adc_ch0_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch0_i_net: std_logic_vector(15 downto 0);
signal adc_ch1_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch1_i_net: std_logic_vector(15 downto 0);
signal adc_ch2_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch2_i_net: std_logic_vector(15 downto 0);
signal adc_ch3_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch3_i_net: std_logic_vector(15 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert10_dout_net_x2: std_logic;
signal assert10_dout_net_x3: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert11_dout_net_x2: std_logic_vector(24 downto 0);
signal assert11_dout_net_x3: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert12_dout_net_x2: std_logic;
signal assert12_dout_net_x3: std_logic;
signal assert4_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x2: std_logic_vector(24 downto 0);
signal assert5_dout_net_x3: std_logic_vector(24 downto 0);
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert8_dout_net_x2: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert9_dout_net_x2: std_logic;
signal assert9_dout_net_x3: std_logic;
signal bpf_ch0_o_net: std_logic_vector(23 downto 0);
signal bpf_ch1_o_net: std_logic_vector(23 downto 0);
signal bpf_ch2_o_net: std_logic_vector(23 downto 0);
signal bpf_ch3_o_net: std_logic_vector(23 downto 0);
signal ce_10000_sg_x2: std_logic;
signal ce_1120_sg_x32: std_logic;
signal ce_1400000_sg_x3: std_logic;
signal ce_1_sg_x96: std_logic;
signal ce_224000000_sg_x7: std_logic;
signal ce_22400000_sg_x28: std_logic;
signal ce_2240_sg_x28: std_logic;
signal ce_2500_sg_x3: std_logic;
signal ce_2800000_sg_x4: std_logic;
signal ce_2_sg_x38: std_logic;
signal ce_35_sg_x22: std_logic;
signal ce_44800000_sg_x2: std_logic;
signal ce_4480_sg_x9: std_logic;
signal ce_5000_sg_x9: std_logic;
signal ce_56000000_sg_x5: std_logic;
signal ce_5600000_sg_x12: std_logic;
signal ce_560_sg_x3: std_logic;
signal ce_70_sg_x27: std_logic;
signal ce_logic_1400000_sg_x2: std_logic;
signal ce_logic_1_sg_x20: std_logic;
signal ce_logic_22400000_sg_x1: std_logic;
signal ce_logic_2240_sg_x1: std_logic;
signal ce_logic_2800000_sg_x2: std_logic;
signal ce_logic_5600000_sg_x2: std_logic;
signal ce_logic_560_sg_x3: std_logic;
signal ce_logic_70_sg_x1: std_logic;
signal ch_out_x2: std_logic_vector(1 downto 0);
signal cic_fofb_q_01_missing_o_net: std_logic;
signal cic_fofb_q_23_missing_o_net: std_logic;
signal clk_10000_sg_x2: std_logic;
signal clk_1120_sg_x32: std_logic;
signal clk_1400000_sg_x3: std_logic;
signal clk_1_sg_x96: std_logic;
signal clk_224000000_sg_x7: std_logic;
signal clk_22400000_sg_x28: std_logic;
signal clk_2240_sg_x28: std_logic;
signal clk_2500_sg_x3: std_logic;
signal clk_2800000_sg_x4: std_logic;
signal clk_2_sg_x38: std_logic;
signal clk_35_sg_x22: std_logic;
signal clk_44800000_sg_x2: std_logic;
signal clk_4480_sg_x9: std_logic;
signal clk_5000_sg_x9: std_logic;
signal clk_56000000_sg_x5: std_logic;
signal clk_5600000_sg_x12: std_logic;
signal clk_560_sg_x3: std_logic;
signal clk_70_sg_x27: std_logic;
signal concat1_y_net_x0: std_logic_vector(25 downto 0);
signal concat2_y_net_x0: std_logic_vector(25 downto 0);
signal concat3_y_net_x0: std_logic_vector(25 downto 0);
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant10_op_net_x0: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant15_op_net_x1: std_logic;
signal constant3_op_net_x1: std_logic;
signal dds_config_valid_ch0_i_net: std_logic;
signal dds_config_valid_ch1_i_net: std_logic;
signal dds_config_valid_ch2_i_net: std_logic;
signal dds_config_valid_ch3_i_net: std_logic;
signal dds_pinc_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch3_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch3_i_net: std_logic_vector(29 downto 0);
signal del_sig_div_fofb_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_monit_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_tbt_thres_i_net: std_logic_vector(25 downto 0);
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_down_x2: std_logic_vector(24 downto 0);
signal dout_down_x3: std_logic_vector(24 downto 0);
signal dout_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x34: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x35: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x34: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x35: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample_q_net_x3: std_logic_vector(1 downto 0);
signal down_sample_q_net_x4: std_logic_vector(25 downto 0);
signal fofb_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ksum_i_net: std_logic_vector(24 downto 0);
signal kx_i_net: std_logic_vector(24 downto 0);
signal ky_i_net: std_logic_vector(24 downto 0);
signal mix_ch0_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch0_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_q_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal monit_cfir_incorrect_o_net: std_logic;
signal monit_cic_unexpected_o_net: std_logic;
signal monit_pfir_incorrect_o_net: std_logic;
signal monit_pos_1_incorrect_o_net: std_logic;
signal q_fofb_o_net: std_logic_vector(25 downto 0);
signal q_fofb_valid_o_net: std_logic;
signal q_monit_1_o_net: std_logic_vector(25 downto 0);
signal q_monit_1_valid_o_net: std_logic;
signal q_monit_o_net: std_logic_vector(25 downto 0);
signal q_monit_valid_o_net: std_logic;
signal q_tbt_o_net: std_logic_vector(25 downto 0);
signal q_tbt_valid_o_net: std_logic;
signal register1_q_net_x6: std_logic;
signal register1_q_net_x7: std_logic;
signal register3_q_net_x15: std_logic;
signal register3_q_net_x16: std_logic;
signal register4_q_net_x14: std_logic_vector(23 downto 0);
signal register4_q_net_x15: std_logic_vector(23 downto 0);
signal register5_q_net_x14: std_logic_vector(23 downto 0);
signal register5_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x12: std_logic_vector(23 downto 0);
signal register_q_net_x13: std_logic_vector(23 downto 0);
signal register_q_net_x14: std_logic_vector(23 downto 0);
signal register_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x31: std_logic_vector(23 downto 0);
signal register_q_net_x32: std_logic_vector(23 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x1: std_logic_vector(24 downto 0);
signal sum_fofb_o_net: std_logic_vector(25 downto 0);
signal sum_fofb_valid_o_net: std_logic;
signal sum_monit_1_o_net: std_logic_vector(25 downto 0);
signal sum_monit_1_valid_o_net: std_logic;
signal sum_monit_o_net: std_logic_vector(25 downto 0);
signal sum_monit_valid_o_net: std_logic;
signal sum_tbt_o_net: std_logic_vector(25 downto 0);
signal sum_tbt_valid_o_net: std_logic;
signal tbt_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch01_incorrect_o_net: std_logic;
signal tbt_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch23_incorrect_o_net: std_logic;
signal tbt_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ufix_to_bool1_dout_net_x1: std_logic;
signal ufix_to_bool2_dout_net_x1: std_logic;
signal ufix_to_bool3_dout_net_x1: std_logic;
signal ufix_to_bool_dout_net_x1: std_logic;
signal valid_ds_down_x1: std_logic;
signal valid_ds_down_x2: std_logic;
signal valid_ds_down_x3: std_logic;
signal x_fofb_o_net: std_logic_vector(25 downto 0);
signal x_fofb_valid_o_net: std_logic;
signal x_monit_1_o_net: std_logic_vector(25 downto 0);
signal x_monit_1_valid_o_net: std_logic;
signal x_monit_o_net: std_logic_vector(25 downto 0);
signal x_monit_valid_o_net: std_logic;
signal x_tbt_o_net: std_logic_vector(25 downto 0);
signal x_tbt_valid_o_net: std_logic;
signal y_fofb_o_net: std_logic_vector(25 downto 0);
signal y_fofb_valid_o_net: std_logic;
signal y_monit_1_o_net: std_logic_vector(25 downto 0);
signal y_monit_1_valid_o_net: std_logic;
signal y_monit_o_net: std_logic_vector(25 downto 0);
signal y_monit_valid_o_net: std_logic;
signal y_tbt_o_net: std_logic_vector(25 downto 0);
signal y_tbt_valid_o_net: std_logic;
begin
adc_ch0_i_net <= adc_ch0_i;
adc_ch1_i_net <= adc_ch1_i;
adc_ch2_i_net <= adc_ch2_i;
adc_ch3_i_net <= adc_ch3_i;
ce_1_sg_x96 <= ce_1;
ce_10000_sg_x2 <= ce_10000;
ce_1120_sg_x32 <= ce_1120;
ce_1400000_sg_x3 <= ce_1400000;
ce_2_sg_x38 <= ce_2;
ce_2240_sg_x28 <= ce_2240;
ce_22400000_sg_x28 <= ce_22400000;
ce_224000000_sg_x7 <= ce_224000000;
ce_2500_sg_x3 <= ce_2500;
ce_2800000_sg_x4 <= ce_2800000;
ce_35_sg_x22 <= ce_35;
ce_4480_sg_x9 <= ce_4480;
ce_44800000_sg_x2 <= ce_44800000;
ce_5000_sg_x9 <= ce_5000;
ce_560_sg_x3 <= ce_560;
ce_5600000_sg_x12 <= ce_5600000;
ce_56000000_sg_x5 <= ce_56000000;
ce_70_sg_x27 <= ce_70;
ce_logic_1_sg_x20 <= ce_logic_1;
ce_logic_1400000_sg_x2 <= ce_logic_1400000;
ce_logic_2240_sg_x1 <= ce_logic_2240;
ce_logic_22400000_sg_x1 <= ce_logic_22400000;
ce_logic_2800000_sg_x2 <= ce_logic_2800000;
ce_logic_560_sg_x3 <= ce_logic_560;
ce_logic_5600000_sg_x2 <= ce_logic_5600000;
ce_logic_70_sg_x1 <= ce_logic_70;
clk_1_sg_x96 <= clk_1;
clk_10000_sg_x2 <= clk_10000;
clk_1120_sg_x32 <= clk_1120;
clk_1400000_sg_x3 <= clk_1400000;
clk_2_sg_x38 <= clk_2;
clk_2240_sg_x28 <= clk_2240;
clk_22400000_sg_x28 <= clk_22400000;
clk_224000000_sg_x7 <= clk_224000000;
clk_2500_sg_x3 <= clk_2500;
clk_2800000_sg_x4 <= clk_2800000;
clk_35_sg_x22 <= clk_35;
clk_4480_sg_x9 <= clk_4480;
clk_44800000_sg_x2 <= clk_44800000;
clk_5000_sg_x9 <= clk_5000;
clk_560_sg_x3 <= clk_560;
clk_5600000_sg_x12 <= clk_5600000;
clk_56000000_sg_x5 <= clk_56000000;
clk_70_sg_x27 <= clk_70;
dds_config_valid_ch0_i_net <= dds_config_valid_ch0_i;
dds_config_valid_ch1_i_net <= dds_config_valid_ch1_i;
dds_config_valid_ch2_i_net <= dds_config_valid_ch2_i;
dds_config_valid_ch3_i_net <= dds_config_valid_ch3_i;
dds_pinc_ch0_i_net <= dds_pinc_ch0_i;
dds_pinc_ch1_i_net <= dds_pinc_ch1_i;
dds_pinc_ch2_i_net <= dds_pinc_ch2_i;
dds_pinc_ch3_i_net <= dds_pinc_ch3_i;
dds_poff_ch0_i_net <= dds_poff_ch0_i;
dds_poff_ch1_i_net <= dds_poff_ch1_i;
dds_poff_ch2_i_net <= dds_poff_ch2_i;
dds_poff_ch3_i_net <= dds_poff_ch3_i;
del_sig_div_fofb_thres_i_net <= del_sig_div_fofb_thres_i;
del_sig_div_monit_thres_i_net <= del_sig_div_monit_thres_i;
del_sig_div_tbt_thres_i_net <= del_sig_div_tbt_thres_i;
ksum_i_net <= ksum_i;
kx_i_net <= kx_i;
ky_i_net <= ky_i;
adc_ch0_dbg_data_o <= adc_ch0_dbg_data_o_net;
adc_ch1_dbg_data_o <= adc_ch1_dbg_data_o_net;
adc_ch2_dbg_data_o <= adc_ch2_dbg_data_o_net;
adc_ch3_dbg_data_o <= adc_ch3_dbg_data_o_net;
bpf_ch0_o <= bpf_ch0_o_net;
bpf_ch1_o <= bpf_ch1_o_net;
bpf_ch2_o <= bpf_ch2_o_net;
bpf_ch3_o <= bpf_ch3_o_net;
cic_fofb_q_01_missing_o <= cic_fofb_q_01_missing_o_net;
cic_fofb_q_23_missing_o <= cic_fofb_q_23_missing_o_net;
fofb_amp_ch0_o <= fofb_amp_ch0_o_net;
fofb_amp_ch1_o <= fofb_amp_ch1_o_net;
fofb_amp_ch2_o <= fofb_amp_ch2_o_net;
fofb_amp_ch3_o <= fofb_amp_ch3_o_net;
fofb_decim_ch0_i_o <= fofb_decim_ch0_i_o_net;
fofb_decim_ch0_q_o <= fofb_decim_ch0_q_o_net;
fofb_decim_ch1_i_o <= fofb_decim_ch1_i_o_net;
fofb_decim_ch1_q_o <= fofb_decim_ch1_q_o_net;
fofb_decim_ch2_i_o <= fofb_decim_ch2_i_o_net;
fofb_decim_ch2_q_o <= fofb_decim_ch2_q_o_net;
fofb_decim_ch3_i_o <= fofb_decim_ch3_i_o_net;
fofb_decim_ch3_q_o <= fofb_decim_ch3_q_o_net;
fofb_pha_ch0_o <= fofb_pha_ch0_o_net;
fofb_pha_ch1_o <= fofb_pha_ch1_o_net;
fofb_pha_ch2_o <= fofb_pha_ch2_o_net;
fofb_pha_ch3_o <= fofb_pha_ch3_o_net;
mix_ch0_i_o <= mix_ch0_i_o_net;
mix_ch0_q_o <= mix_ch0_q_o_net;
mix_ch1_i_o <= mix_ch1_i_o_net;
mix_ch1_q_o <= mix_ch1_q_o_net;
mix_ch2_i_o <= mix_ch2_i_o_net;
mix_ch2_q_o <= mix_ch2_q_o_net;
mix_ch3_i_o <= mix_ch3_i_o_net;
mix_ch3_q_o <= mix_ch3_q_o_net;
monit_amp_ch0_o <= monit_amp_ch0_o_net;
monit_amp_ch1_o <= monit_amp_ch1_o_net;
monit_amp_ch2_o <= monit_amp_ch2_o_net;
monit_amp_ch3_o <= monit_amp_ch3_o_net;
monit_cfir_incorrect_o <= monit_cfir_incorrect_o_net;
monit_cic_unexpected_o <= monit_cic_unexpected_o_net;
monit_pfir_incorrect_o <= monit_pfir_incorrect_o_net;
monit_pos_1_incorrect_o <= monit_pos_1_incorrect_o_net;
q_fofb_o <= q_fofb_o_net;
q_fofb_valid_o <= q_fofb_valid_o_net;
q_monit_1_o <= q_monit_1_o_net;
q_monit_1_valid_o <= q_monit_1_valid_o_net;
q_monit_o <= q_monit_o_net;
q_monit_valid_o <= q_monit_valid_o_net;
q_tbt_o <= q_tbt_o_net;
q_tbt_valid_o <= q_tbt_valid_o_net;
sum_fofb_o <= sum_fofb_o_net;
sum_fofb_valid_o <= sum_fofb_valid_o_net;
sum_monit_1_o <= sum_monit_1_o_net;
sum_monit_1_valid_o <= sum_monit_1_valid_o_net;
sum_monit_o <= sum_monit_o_net;
sum_monit_valid_o <= sum_monit_valid_o_net;
sum_tbt_o <= sum_tbt_o_net;
sum_tbt_valid_o <= sum_tbt_valid_o_net;
tbt_amp_ch0_o <= tbt_amp_ch0_o_net;
tbt_amp_ch1_o <= tbt_amp_ch1_o_net;
tbt_amp_ch2_o <= tbt_amp_ch2_o_net;
tbt_amp_ch3_o <= tbt_amp_ch3_o_net;
tbt_decim_ch01_incorrect_o <= tbt_decim_ch01_incorrect_o_net;
tbt_decim_ch0_i_o <= tbt_decim_ch0_i_o_net;
tbt_decim_ch0_q_o <= tbt_decim_ch0_q_o_net;
tbt_decim_ch1_i_o <= tbt_decim_ch1_i_o_net;
tbt_decim_ch1_q_o <= tbt_decim_ch1_q_o_net;
tbt_decim_ch23_incorrect_o <= tbt_decim_ch23_incorrect_o_net;
tbt_decim_ch2_i_o <= tbt_decim_ch2_i_o_net;
tbt_decim_ch2_q_o <= tbt_decim_ch2_q_o_net;
tbt_decim_ch3_i_o <= tbt_decim_ch3_i_o_net;
tbt_decim_ch3_q_o <= tbt_decim_ch3_q_o_net;
tbt_pha_ch0_o <= tbt_pha_ch0_o_net;
tbt_pha_ch1_o <= tbt_pha_ch1_o_net;
tbt_pha_ch2_o <= tbt_pha_ch2_o_net;
tbt_pha_ch3_o <= tbt_pha_ch3_o_net;
x_fofb_o <= x_fofb_o_net;
x_fofb_valid_o <= x_fofb_valid_o_net;
x_monit_1_o <= x_monit_1_o_net;
x_monit_1_valid_o <= x_monit_1_valid_o_net;
x_monit_o <= x_monit_o_net;
x_monit_valid_o <= x_monit_valid_o_net;
x_tbt_o <= x_tbt_o_net;
x_tbt_valid_o <= x_tbt_valid_o_net;
y_fofb_o <= y_fofb_o_net;
y_fofb_valid_o <= y_fofb_valid_o_net;
y_monit_1_o <= y_monit_1_o_net;
y_monit_1_valid_o <= y_monit_1_valid_o_net;
y_monit_o <= y_monit_o_net;
y_monit_valid_o <= y_monit_valid_o_net;
y_tbt_o <= y_tbt_o_net;
y_tbt_valid_o <= y_tbt_valid_o_net;
bpf_d31c4af409: entity work.bpf_entity_d31c4af409
port map (
din_ch0 => adc_ch0_dbg_data_o_net,
din_ch1 => adc_ch1_dbg_data_o_net,
din_ch2 => adc_ch2_dbg_data_o_net,
din_ch3 => adc_ch3_dbg_data_o_net,
dout_ch0 => bpf_ch0_o_net,
dout_ch1 => bpf_ch1_o_net,
dout_ch2 => bpf_ch2_o_net,
dout_ch3 => bpf_ch3_o_net
);
concat: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert12_dout_net_x2,
in1 => reinterpret1_output_port_net,
y => concat_y_net_x0
);
concat1: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => valid_ds_down_x2,
in1 => reinterpret2_output_port_net,
y => concat1_y_net_x0
);
concat2: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert9_dout_net_x2,
in1 => reinterpret3_output_port_net,
y => concat2_y_net_x0
);
concat3: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert10_dout_net_x2,
in1 => reinterpret4_output_port_net,
y => concat3_y_net_x0
);
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net_x0
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
constant15: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant15_op_net_x1
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net_x1
);
convert_filt_fda412c1bf: entity work.convert_filt_entity_fda412c1bf
port map (
din => down_sample_q_net_x4,
dout => reinterpret5_output_port_net_x1
);
dds_sub_a4b6b880f6: entity work.dds_sub_entity_a4b6b880f6
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_logic_1 => ce_logic_1_sg_x20,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
dds_01_cosine => register_q_net_x12,
dds_01_sine => register_q_net_x13,
dds_23_cosine => register_q_net_x14,
dds_23_sine => register_q_net_x15
);
delta_sigma_fofb_ee61e649ea: entity work.delta_sigma_fofb_entity_ee61e649ea
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x20,
c => down_sample2_q_net_x21,
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
ce_logic_2240 => ce_logic_2240_sg_x1,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
d => down_sample1_q_net_x21,
ds_thres => del_sig_div_fofb_thres_i_net,
q => assert8_dout_net_x1,
q_valid => assert9_dout_net_x1,
sum_valid => assert12_dout_net_x1,
sum_x0 => assert11_dout_net_x1,
x => assert5_dout_net_x1,
x_valid => assert10_dout_net_x1,
y => dout_down_x1,
y_valid => valid_ds_down_x1
);
delta_sigma_monit_a8f8b81626: entity work.delta_sigma_monit_entity_a8f8b81626
port map (
a => down_sample2_q_net_x5,
b => down_sample1_q_net_x5,
c => down_sample3_q_net_x5,
ce_1 => ce_1_sg_x96,
ce_10000 => ce_10000_sg_x2,
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
ce_4480 => ce_4480_sg_x9,
ce_44800000 => ce_44800000_sg_x2,
ce_5000 => ce_5000_sg_x9,
ce_logic_22400000 => ce_logic_22400000_sg_x1,
clk_1 => clk_1_sg_x96,
clk_10000 => clk_10000_sg_x2,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
clk_4480 => clk_4480_sg_x9,
clk_44800000 => clk_44800000_sg_x2,
clk_5000 => clk_5000_sg_x9,
d => down_sample4_q_net_x5,
ds_thres => del_sig_div_monit_thres_i_net,
q => assert4_dout_net_x1,
q_valid => assert9_dout_net_x2,
sum_valid => assert10_dout_net_x2,
sum_x0 => assert5_dout_net_x2,
x => assert11_dout_net_x2,
x_valid => assert12_dout_net_x2,
y => dout_down_x2,
y_valid => valid_ds_down_x2
);
delta_sigma_tbt_bbfa8a8a69: entity work.delta_sigma_tbt_entity_bbfa8a8a69
port map (
a => down_sample2_q_net_x34,
b => down_sample1_q_net_x34,
c => down_sample2_q_net_x35,
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
ce_logic_70 => ce_logic_70_sg_x1,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
d => down_sample1_q_net_x35,
ds_thres => del_sig_div_tbt_thres_i_net,
q => assert8_dout_net_x2,
q_valid => assert9_dout_net_x3,
sum_valid => assert12_dout_net_x3,
sum_x0 => assert11_dout_net_x3,
x => assert5_dout_net_x3,
x_valid => assert10_dout_net_x3,
y => dout_down_x3,
y_valid => valid_ds_down_x3
);
fofb_amp_8b25d4b0b6: entity work.fofb_amp_entity_8b25d4b0b6
port map (
ce_1 => ce_1_sg_x96,
ce_1120 => ce_1120_sg_x32,
ce_2240 => ce_2240_sg_x28,
ce_logic_1 => ce_logic_1_sg_x20,
ch_in0 => register3_q_net_x15,
ch_in1 => register3_q_net_x16,
clk_1 => clk_1_sg_x96,
clk_1120 => clk_1120_sg_x32,
clk_2240 => clk_2240_sg_x28,
i_in0 => register4_q_net_x14,
i_in1 => register4_q_net_x15,
q_in0 => register5_q_net_x14,
q_in1 => register5_q_net_x15,
amp_out0 => down_sample2_q_net_x20,
amp_out1 => down_sample1_q_net_x20,
amp_out2 => down_sample2_q_net_x21,
amp_out3 => down_sample1_q_net_x21,
fofb_amp0 => fofb_amp_ch1_o_net,
fofb_amp0_x0 => fofb_amp_ch0_o_net,
fofb_amp0_x1 => fofb_pha_ch1_o_net,
fofb_amp0_x2 => fofb_pha_ch0_o_net,
fofb_amp0_x3 => fofb_decim_ch1_i_o_net,
fofb_amp0_x4 => fofb_decim_ch0_i_o_net,
fofb_amp0_x5 => fofb_decim_ch1_q_o_net,
fofb_amp0_x6 => fofb_decim_ch0_q_o_net,
fofb_amp0_x7 => cic_fofb_q_01_missing_o_net,
fofb_amp1 => fofb_amp_ch3_o_net,
fofb_amp1_x0 => fofb_amp_ch2_o_net,
fofb_amp1_x1 => fofb_pha_ch3_o_net,
fofb_amp1_x2 => fofb_pha_ch2_o_net,
fofb_amp1_x3 => fofb_decim_ch3_i_o_net,
fofb_amp1_x4 => fofb_decim_ch2_i_o_net,
fofb_amp1_x5 => fofb_decim_ch3_q_o_net,
fofb_amp1_x6 => fofb_decim_ch2_q_o_net,
fofb_amp1_x7 => cic_fofb_q_23_missing_o_net
);
k_fofb_mult3_697accc8e2: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert5_dout_net_x1,
in2 => kx_i_net,
vld_in => assert10_dout_net_x1,
out1 => x_fofb_o_net,
vld_out => x_fofb_valid_o_net
);
k_fofb_mult4_102b49a84e: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => dout_down_x1,
in2 => ky_i_net,
vld_in => valid_ds_down_x1,
out1 => y_fofb_o_net,
vld_out => y_fofb_valid_o_net
);
k_fofb_mult5_ed47def699: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert8_dout_net_x1,
in2 => kx_i_net,
vld_in => assert9_dout_net_x1,
out1 => q_fofb_o_net,
vld_out => q_fofb_valid_o_net
);
k_monit_1_mult2_30ad492eba: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret1_output_port_net_x1,
in2 => ky_i_net,
vld_in => ufix_to_bool1_dout_net_x1,
out1 => y_monit_1_o_net,
vld_out => y_monit_1_valid_o_net
);
k_monit_1_mult6_71da64dfef: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret2_output_port_net_x1,
in2 => kx_i_net,
vld_in => ufix_to_bool2_dout_net_x1,
out1 => q_monit_1_o_net,
vld_out => q_monit_1_valid_o_net
);
k_monit_1_mult_016885a3ac: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret3_output_port_net_x1,
in2 => kx_i_net,
vld_in => ufix_to_bool_dout_net_x1,
out1 => x_monit_1_o_net,
vld_out => x_monit_1_valid_o_net
);
k_monit_mult3_8a778fb5f4: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert11_dout_net_x2,
in2 => kx_i_net,
vld_in => assert12_dout_net_x2,
out1 => x_monit_o_net,
vld_out => x_monit_valid_o_net
);
k_monit_mult4_1b07b5102a: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => dout_down_x2,
in2 => ky_i_net,
vld_in => valid_ds_down_x2,
out1 => y_monit_o_net,
vld_out => y_monit_valid_o_net
);
k_monit_mult5_a064f6aaae: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert4_dout_net_x1,
in2 => kx_i_net,
vld_in => assert9_dout_net_x2,
out1 => q_monit_o_net,
vld_out => q_monit_valid_o_net
);
k_tbt_mult1_cebfa469e3: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => dout_down_x3,
in2 => ky_i_net,
vld_in => valid_ds_down_x3,
out1 => y_tbt_o_net,
vld_out => y_tbt_valid_o_net
);
k_tbt_mult2_2b721a52a5: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert8_dout_net_x2,
in2 => kx_i_net,
vld_in => assert9_dout_net_x3,
out1 => q_tbt_o_net,
vld_out => q_tbt_valid_o_net
);
k_tbt_mult_b8fafff255: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert5_dout_net_x3,
in2 => kx_i_net,
vld_in => assert10_dout_net_x3,
out1 => x_tbt_o_net,
vld_out => x_tbt_valid_o_net
);
ksum_fofb_mult4_ac3ed97096: entity work.ksum_fofb_mult4_entity_ac3ed97096
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert11_dout_net_x1,
in2 => ksum_i_net,
vld_in => assert12_dout_net_x1,
out1 => sum_fofb_o_net,
vld_out => sum_fofb_valid_o_net
);
ksum_monit_1_mult1_c66dc07078: entity work.ksum_monit_1_mult1_entity_c66dc07078
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret4_output_port_net_x1,
in2 => ksum_i_net,
vld_in => ufix_to_bool3_dout_net_x1,
out1 => sum_monit_1_o_net,
vld_out => sum_monit_1_valid_o_net
);
ksum_monit_mult2_31877b6d2b: entity work.ksum_monit_mult2_entity_31877b6d2b
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert5_dout_net_x2,
in2 => ksum_i_net,
vld_in => assert10_dout_net_x2,
out1 => sum_monit_o_net,
vld_out => sum_monit_valid_o_net
);
ksum_tbt_mult3_e0be30d675: entity work.ksum_tbt_mult3_entity_e0be30d675
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert11_dout_net_x3,
in2 => ksum_i_net,
vld_in => assert12_dout_net_x3,
out1 => sum_tbt_o_net,
vld_out => sum_tbt_valid_o_net
);
mixer_a1cd828545: entity work.mixer_entity_a1cd828545
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ch_in0 => register1_q_net_x6,
ch_in1 => register1_q_net_x7,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
dds_cosine_0 => register_q_net_x12,
dds_cosine_1 => register_q_net_x14,
dds_msine_0 => register_q_net_x13,
dds_msine_1 => register_q_net_x15,
dds_valid_0 => constant15_op_net_x1,
dds_valid_1 => constant3_op_net_x1,
din0 => register_q_net_x31,
din1 => register_q_net_x32,
ch_out0 => register3_q_net_x15,
ch_out1 => register3_q_net_x16,
i_out0 => register4_q_net_x14,
i_out1 => register4_q_net_x15,
q_out0 => register5_q_net_x14,
q_out1 => register5_q_net_x15,
tddm_mixer => mix_ch1_i_o_net,
tddm_mixer_x0 => mix_ch0_i_o_net,
tddm_mixer_x1 => mix_ch1_q_o_net,
tddm_mixer_x2 => mix_ch0_q_o_net,
tddm_mixer_x3 => mix_ch3_i_o_net,
tddm_mixer_x4 => mix_ch2_i_o_net,
tddm_mixer_x5 => mix_ch3_q_o_net,
tddm_mixer_x6 => mix_ch2_q_o_net
);
monit_amp_44da74e268: entity work.monit_amp_entity_44da74e268
port map (
ce_1 => ce_1_sg_x96,
ce_1400000 => ce_1400000_sg_x3,
ce_22400000 => ce_22400000_sg_x28,
ce_2800000 => ce_2800000_sg_x4,
ce_560 => ce_560_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_logic_1400000 => ce_logic_1400000_sg_x2,
ce_logic_2800000 => ce_logic_2800000_sg_x2,
ce_logic_560 => ce_logic_560_sg_x3,
ch_in => ch_out_x2,
clk_1 => clk_1_sg_x96,
clk_1400000 => clk_1400000_sg_x3,
clk_22400000 => clk_22400000_sg_x28,
clk_2800000 => clk_2800000_sg_x4,
clk_560 => clk_560_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
din => dout_x2,
amp_out0 => down_sample2_q_net_x5,
amp_out1 => down_sample1_q_net_x5,
amp_out2 => down_sample3_q_net_x5,
amp_out3 => down_sample4_q_net_x5,
monit_amp_c => monit_amp_ch1_o_net,
monit_amp_c_x0 => monit_amp_ch0_o_net,
monit_amp_c_x1 => monit_amp_ch2_o_net,
monit_amp_c_x2 => monit_amp_ch3_o_net,
monit_amp_c_x3 => monit_cfir_incorrect_o_net,
monit_amp_c_x4 => monit_cic_unexpected_o_net,
monit_amp_c_x5 => monit_pfir_incorrect_o_net
);
monit_pos_1_522c8cf08d: entity work.monit_pos_1_entity_522c8cf08d
port map (
ce_1 => ce_1_sg_x96,
ce_224000000 => ce_224000000_sg_x7,
ce_5600000 => ce_5600000_sg_x12,
ce_56000000 => ce_56000000_sg_x5,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
ch_in => down_sample_q_net_x3,
clk_1 => clk_1_sg_x96,
clk_224000000 => clk_224000000_sg_x7,
clk_5600000 => clk_5600000_sg_x12,
clk_56000000 => clk_56000000_sg_x5,
din => reinterpret5_output_port_net_x1,
monit_1_pos_q => reinterpret2_output_port_net_x1,
monit_1_pos_x => reinterpret3_output_port_net_x1,
monit_1_pos_y => reinterpret1_output_port_net_x1,
monit_1_sum => reinterpret4_output_port_net_x1,
monit_1_vld_q => ufix_to_bool2_dout_net_x1,
monit_1_vld_sum => ufix_to_bool3_dout_net_x1,
monit_1_vld_x => ufix_to_bool_dout_net_x1,
monit_1_vld_y => ufix_to_bool1_dout_net_x1,
monit_pos_1_c_x0 => monit_pos_1_incorrect_o_net
);
register1: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch1_i_net,
en => "1",
rst => "0",
q => adc_ch1_dbg_data_o_net
);
register2: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch2_i_net,
en => "1",
rst => "0",
q => adc_ch2_dbg_data_o_net
);
register3: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch3_i_net,
en => "1",
rst => "0",
q => adc_ch3_dbg_data_o_net
);
register_x0: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch0_i_net,
en => "1",
rst => "0",
q => adc_ch0_dbg_data_o_net
);
reinterpret1: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert11_dout_net_x2,
output_port => reinterpret1_output_port_net
);
reinterpret2: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => dout_down_x2,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert4_dout_net_x1,
output_port => reinterpret3_output_port_net
);
reinterpret4: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert5_dout_net_x2,
output_port => reinterpret4_output_port_net
);
tbt_amp_cbd277bb0c: entity work.tbt_amp_entity_cbd277bb0c
port map (
ce_1 => ce_1_sg_x96,
ce_35 => ce_35_sg_x22,
ce_70 => ce_70_sg_x27,
ce_logic_1 => ce_logic_1_sg_x20,
ch_in0 => register3_q_net_x15,
ch_in1 => register3_q_net_x16,
clk_1 => clk_1_sg_x96,
clk_35 => clk_35_sg_x22,
clk_70 => clk_70_sg_x27,
i_in0 => register4_q_net_x14,
i_in1 => register4_q_net_x15,
q_in0 => register5_q_net_x14,
q_in1 => register5_q_net_x15,
amp_out0 => down_sample2_q_net_x34,
amp_out1 => down_sample1_q_net_x34,
amp_out2 => down_sample2_q_net_x35,
amp_out3 => down_sample1_q_net_x35,
tbt_amp0 => tbt_amp_ch1_o_net,
tbt_amp0_x0 => tbt_amp_ch0_o_net,
tbt_amp0_x1 => tbt_pha_ch1_o_net,
tbt_amp0_x2 => tbt_pha_ch0_o_net,
tbt_amp0_x3 => tbt_decim_ch01_incorrect_o_net,
tbt_amp0_x4 => tbt_decim_ch1_i_o_net,
tbt_amp0_x5 => tbt_decim_ch0_i_o_net,
tbt_amp0_x6 => tbt_decim_ch1_q_o_net,
tbt_amp0_x7 => tbt_decim_ch0_q_o_net,
tbt_amp1 => tbt_amp_ch3_o_net,
tbt_amp1_x0 => tbt_amp_ch2_o_net,
tbt_amp1_x1 => tbt_pha_ch3_o_net,
tbt_amp1_x2 => tbt_pha_ch2_o_net,
tbt_amp1_x3 => tbt_decim_ch23_incorrect_o_net,
tbt_amp1_x4 => tbt_decim_ch3_i_o_net,
tbt_amp1_x5 => tbt_decim_ch2_i_o_net,
tbt_amp1_x6 => tbt_decim_ch3_q_o_net,
tbt_amp1_x7 => tbt_decim_ch2_q_o_net
);
tdm_mix_54ce67e6e8: entity work.tdm_mix_entity_54ce67e6e8
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_logic_1 => ce_logic_1_sg_x20,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
din_ch0 => bpf_ch0_o_net,
din_ch1 => bpf_ch1_o_net,
din_ch2 => bpf_ch2_o_net,
din_ch3 => bpf_ch3_o_net,
ch_out0 => register1_q_net_x6,
ch_out1 => register1_q_net_x7,
dout0 => register_q_net_x31,
dout1 => register_q_net_x32
);
tdm_monit_1_746ecf54b0: entity work.tdm_monit_1_entity_746ecf54b0
port map (
ce_1 => ce_1_sg_x96,
ce_22400000 => ce_22400000_sg_x28,
ce_2500 => ce_2500_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
clk_1 => clk_1_sg_x96,
clk_22400000 => clk_22400000_sg_x28,
clk_2500 => clk_2500_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
din_ch0 => concat_y_net_x0,
din_ch1 => concat1_y_net_x0,
din_ch2 => concat2_y_net_x0,
din_ch3 => concat3_y_net_x0,
rst => constant11_op_net_x0,
ch_out => down_sample_q_net_x3,
dout => down_sample_q_net_x4
);
tdm_monit_6e38292ecb: entity work.tdm_monit_entity_6e38292ecb
port map (
ce_1 => ce_1_sg_x96,
ce_2240 => ce_2240_sg_x28,
ce_560 => ce_560_sg_x3,
ce_logic_560 => ce_logic_560_sg_x3,
clk_1 => clk_1_sg_x96,
clk_2240 => clk_2240_sg_x28,
clk_560 => clk_560_sg_x3,
din_ch0 => down_sample2_q_net_x20,
din_ch1 => down_sample1_q_net_x20,
din_ch2 => down_sample2_q_net_x21,
din_ch3 => down_sample1_q_net_x21,
rst => constant10_op_net_x0,
ch_out => ch_out_x2,
dout => dout_x2
);
end structural;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_sbi;
use bitvis_vip_sbi.vvc_methods_pkg.all;
use bitvis_vip_sbi.td_vvc_framework_common_methods_pkg.all;
library bitvis_vip_uart;
use bitvis_vip_uart.vvc_methods_pkg.all;
use bitvis_vip_uart.td_vvc_framework_common_methods_pkg.all;
-- Test bench entity
entity uart_vvc_tb is
end entity;
-- Test bench architecture
architecture func of uart_vvc_tb is
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
-- Clock and bit period settings
constant C_CLK_PERIOD : time := 10 ns;
constant C_BIT_PERIOD : time := 16 * C_CLK_PERIOD;
-- Time for one UART transmission to complete
constant C_TIME_OF_ONE_UART_TX : time := 11*C_BIT_PERIOD; -- =1760 ns;
-- Predefined SBI addresses
constant C_ADDR_RX_DATA : unsigned(2 downto 0) := "000";
constant C_ADDR_RX_DATA_VALID : unsigned(2 downto 0) := "001";
constant C_ADDR_TX_DATA : unsigned(2 downto 0) := "010";
constant C_ADDR_TX_READY : unsigned(2 downto 0) := "011";
-- Log overload procedure for simplification
procedure log(
msg : string) is
begin
log(ID_SEQUENCER, msg, C_SCOPE);
end;
begin
-----------------------------------------------------------------------------
-- Instantiate test harness, containing DUT and Executors
-----------------------------------------------------------------------------
i_test_harness : entity work.uart_vvc_th;
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
begin
-- Wait for UVVM to finish initialization
await_uvvm_initialization(VOID);
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
--enable_log_msg(ALL_MESSAGES);
disable_log_msg(ALL_MESSAGES);
enable_log_msg(ID_LOG_HDR);
enable_log_msg(ID_SEQUENCER);
enable_log_msg(ID_UVVM_SEND_CMD);
disable_log_msg(SBI_VVCT, 1, ALL_MESSAGES);
enable_log_msg(SBI_VVCT, 1, ID_BFM);
enable_log_msg(SBI_VVCT, 1, ID_FINISH_OR_STOP);
disable_log_msg(UART_VVCT, 1, RX, ALL_MESSAGES);
enable_log_msg(UART_VVCT, 1, RX, ID_BFM);
disable_log_msg(UART_VVCT, 1, TX, ALL_MESSAGES);
enable_log_msg(UART_VVCT, 1, TX, ID_BFM);
log(ID_LOG_HDR, "Starting simulation of TB for UART using VVCs", C_SCOPE);
------------------------------------------------------------
log("Wait 10 clock period for reset to be turned off");
wait for (10 * C_CLK_PERIOD); -- for reset to be turned off
log(ID_LOG_HDR, "Configure UART VVC 1", C_SCOPE);
------------------------------------------------------------
shared_uart_vvc_config(RX,1).bfm_config.bit_time := C_BIT_PERIOD;
shared_uart_vvc_config(TX,1).bfm_config.bit_time := C_BIT_PERIOD;
log(ID_LOG_HDR, "Check register defaults ", C_SCOPE);
------------------------------------------------------------
-- This test will send three sbi_check commands to the SBI VVC, and then
-- wait for them all to complete before continuing the test sequence.
sbi_check(SBI_VVCT, 1, C_ADDR_RX_DATA, x"00", "RX_DATA default");
sbi_check(SBI_VVCT, 1, C_ADDR_TX_READY, x"01", "TX_READY default");
sbi_check(SBI_VVCT, 1, C_ADDR_RX_DATA_VALID, x"00", "RX_DATA_VALID default");
await_completion(SBI_VVCT,1, 10 * C_CLK_PERIOD);
log(ID_LOG_HDR, "Check simple transmit", C_SCOPE);
------------------------------------------------------------
-- This test case will instruct the SBI VVC to send the data x"55" to the DUT C_ADDR_TX_DATA address.
-- This will cause the DUT to transmit x"55" on the UART line. In order to receive the data, the
-- UART VVC is instructed to expect the data x"55" on the RX port. The test sequence will not continue
-- until the UART VVC has received the data from the DUT, indicated by the await_completion method.
sbi_write(SBI_VVCT,1, C_ADDR_TX_DATA, x"55", "TX_DATA");
uart_expect(UART_VVCT,1,RX, x"55", "Expecting data on UART RX");
await_completion(UART_VVCT,1,RX, 13 * C_BIT_PERIOD);
wait for 200 ns; -- margin
log(ID_LOG_HDR, "Check simple receive", C_SCOPE);
------------------------------------------------------------
-- In this test case the UART VVC (TX channel) is instructed to send the data x"AA" to the DUT.
-- This data should be received and stored to a RX buffer by the DUT. After the UART VVC has completed
-- the transmission, the SBI VVC is instructed to check read and check (sbi_check) the C_ADDR_RX_DATA
-- register, and verify that it is in fact x"AA" that the DUT received. The test sequencer will continue
-- when the SBI VVC is done checking the C_ADDR_RX_DATA register.
uart_transmit(UART_VVCT,1,TX, x"AA", "UART TX");
await_completion(UART_VVCT,1,TX, 13 * C_BIT_PERIOD);
wait for 200 ns; -- margin
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"AA", "RX_DATA");
await_completion(SBI_VVCT,1, 13 * C_BIT_PERIOD);
log(ID_LOG_HDR, "Check single simultaneous transmit and receive", C_SCOPE);
------------------------------------------------------------
-- Since the UART consists of two individual VVCs (TX and RX), it is capable of full duplex operation.
-- This test case will instruct the SBI VVC to write x"B4" to the C_ADDR_TX_DATA register of the DUT,
-- which will cause the DUT to send x"B4" on its UART TX line. Simultaneously, the UART VVC is instructed
-- to both transmit x"87" to the DUT, and expect x"B4" from the DUT. When the UART VVC is done transmitting
-- to the DUT, the SBI VVC will be instructed to read and check the DUT C_ADDR_RX_DATA register and verify
-- that the DUT received the correct data from the UART VVC. After this check is completed, the test sequencer
-- can continue to the next test case.
sbi_write(SBI_VVCT,1, C_ADDR_TX_DATA, x"B4", "TX_DATA");
uart_transmit(UART_VVCT,1,TX, x"87", "UART TX");
uart_expect(UART_VVCT,1,RX, x"B4", "Expecting data on UART RX");
await_completion(UART_VVCT,1,TX, 13 * C_BIT_PERIOD);
wait for 200 ns; -- margin
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"87", "RX_DATA");
await_completion(SBI_VVCT,1, 13 * C_BIT_PERIOD);
log(ID_LOG_HDR, "Check multiple simultaneous receive and read", C_SCOPE);
------------------------------------------------------------
-- This test case will instruct the UART VVC to transmit three messages to the DUT. These UART VVC (TX channel)
-- will add the three "uart_transmit" commands to the command queue, and execute them sequentially when
-- await_completion is called. After the UART VVC is done transmitting, the SBI VVC is instructed to read and
-- verify that the three consecutive bytes from the C_ADDR_RX_DATA register of the DUT are equal to the data
-- transmitted from the UART VVC. When the SBI VVC is done with these checks, the testbench sequencer can continue
-- to the next test case.
uart_transmit(UART_VVCT,1,TX, x"A1", "UART TX");
uart_transmit(UART_VVCT,1,TX, x"A2", "UART TX");
uart_transmit(UART_VVCT,1,TX, x"A3", "UART TX");
await_completion(UART_VVCT,1,TX, 3 * 13 * C_BIT_PERIOD);
wait for 200 ns; -- margin
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"A1", "RX_DATA");
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"A2", "RX_DATA");
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"A3", "RX_DATA");
await_completion(SBI_VVCT,1, 10 * C_CLK_PERIOD);
log(ID_LOG_HDR, "Skew SBI read over UART receive ", C_SCOPE);
------------------------------------------------------------
-- This test case will show how using VVCs in UVVM can be used for simultaneous UART and SBI operation,
-- which enables testing of corner cases. In the UART DUT one of these corner cases often occurs when the UART DUT
-- must handle UART RX data and SBI reads simultaneously. To test if this is handled properly in the DUT,
-- this test case will transmit data from the UART VVC, and check the data received in the C_ADDR_RX_DATA register.
-- The DUT RX buffer will always contain at least one received byte, and the SBI VVC will check the oldest entry in
-- the RX buffer. The UART VVC will be set up to transmit bytes to the DUT continuously. When the SBI_VVC checks the
-- DUT RX buffer, relative to the UART TX operation, will vary on each iteration.
-- First, the UART VVC will transmit a complete frame to the DUT. Then, when the UART VVC is 50 clock periods from
-- completing the transmission of the second byte, the SBI VVC checks the DUT RX buffer for the first received byte.
-- When the UART VVC is 49 clock periods from transmitting the third byte, the SBI VVC will check the DUT RX buffer
-- for the second byte received. This process repeats until the SBI VVC is checking the DUT RX register 50 clock periods
-- after the UART VVC has completed its transmission. At this point there will be two complete bytes in the DUT RX buffer
-- when the SBI VVC reads from it. After the test is completed the two final bytes in the RX buffer are checked. When this
-- is done, the test case is complete.
log("Setting up the UART VVC to transmit 102 samples to the DUT");
for i in 1 to 102 loop
uart_transmit(UART_VVCT,1,TX, std_logic_vector(to_unsigned(16#80# + i, 8)), string'("Set up new data. Now byte # " & to_string(i)));
end loop;
log("Setting up the SBI VVC to read and check the DUT RX register after each completed UART TX operation");
-- 1760 ns is measured time from start of UART receive to received data is available in the DUT C_ADDR_RX_DATA register
-- The SBI VVC will wait until the UART VVC is 50 clock periods away from successfully transmitting the first byte.
insert_delay(SBI_VVCT,1, C_TIME_OF_ONE_UART_TX - 50 * C_CLK_PERIOD, "Inserting delay in SBI VVC to wait for first byte to complete");
for i in 1 to 100 loop
-- Wait for the time of one complete UART transmission + one clock cycle (for skew).
-- Every read will now be 1T later relative to a new byte being valid internally
insert_delay(SBI_VVCT,1, C_TIME_OF_ONE_UART_TX, "Delaying for the time of one uart transmission");
insert_delay(SBI_VVCT,1, C_CLK_PERIOD, "Skewing the SBI read one clock cycle");
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, std_logic_vector(to_unsigned(16#80# + i, 8)), "Reading data number " & to_string(i));
end loop;
await_completion(UART_VVCT,1,TX, 103 * C_TIME_OF_ONE_UART_TX);
wait for 50 ns; -- to assure UART RX complete internally
-- Check the last two bytes in the DUT RX buffer.
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, std_logic_vector(to_unsigned(16#80# + 101, 8)), "Reading data number " & to_string(101));
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, std_logic_vector(to_unsigned(16#80# + 102, 8)), "Reading data number " & to_string(102));
await_completion(SBI_VVCT,1, 10 * C_CLK_PERIOD);
log(ID_LOG_HDR, "Skew SBI read over UART receive with inter-BFM delay functionality", C_SCOPE);
------------------------------------------------------------
-- This test case will test the same as the test case above, but using the built in delay functionality in the SBI VVC
log("Setting up the UART VVC to transmit 102 samples to the DUT");
for i in 1 to 102 loop
uart_transmit(UART_VVCT,1,TX, std_logic_vector(to_unsigned(16#80# + i, 8)), string'("Set up new data. Now byte # " & to_string(i)));
end loop;
log("Setting up the SBI VVC to read and check the DUT RX register after each completed UART TX operation");
-- The SBI VVC will wait until the UART VVC is 50 clock periods away from successfully transmitting the second byte.
insert_delay(SBI_VVCT,1, C_TIME_OF_ONE_UART_TX, "Insert delay in SBI VVC until the first UART transmission has completed");
insert_delay(SBI_VVCT,1, C_TIME_OF_ONE_UART_TX - 50 * C_CLK_PERIOD, "Inserting delay in SBI VVC until second UART transmission has almost completed");
log("Setting the SBI VVC to separate each BFM access with 1760 ns");
shared_sbi_vvc_config(1).inter_bfm_delay.delay_type := TIME_START2START;
shared_sbi_vvc_config(1).inter_bfm_delay.delay_in_time := C_TIME_OF_ONE_UART_TX+C_CLK_PERIOD;
for i in 1 to 100 loop
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, std_logic_vector(to_unsigned(16#80# + i, 8)), "Reading data number " & to_string(i));
end loop;
await_completion(UART_VVCT,1,TX, 103 * C_TIME_OF_ONE_UART_TX);
await_completion(SBI_VVCT,1, 2 * C_TIME_OF_ONE_UART_TX);
wait for 50 ns; -- to assure UART RX complete internally
-- Check the last two bytes in the DUT RX buffer.
log("Setting the SBI VVC back to no delay between BFM accesses");
shared_sbi_vvc_config(1).inter_bfm_delay.delay_type := NO_DELAY;
shared_sbi_vvc_config(1).inter_bfm_delay.delay_in_time := 0 ns;
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, std_logic_vector(to_unsigned(16#80# + 101, 8)), "Reading data number " & to_string(101));
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, std_logic_vector(to_unsigned(16#80# + 102, 8)), "Reading data number " & to_string(102));
await_completion(SBI_VVCT,1, 2*C_TIME_OF_ONE_UART_TX);
-----------------------------------------------------------------------------
-- Ending the simulation
-----------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
end func;
|
Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_23x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A8: buffer std_logic
);
end x25_23x;
architecture x25_23x_behav of x25_23x is
signal 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7647a,a7648a,a7649a,a7653a,a7654a,a7658a,a7659a,a7660a,a7663a,a7667a,a7668a,a7669a,a7673a,a7674a,a7678a,a7679a,a7680a,a7683a,a7687a,a7688a,a7689a,a7693a,a7694a,a7698a,a7699a,a7700a,a7703a,a7707a,a7708a,a7709a,a7713a,a7714a,a7718a,a7719a,a7720a,a7723a,a7727a,a7728a,a7729a,a7733a,a7734a,a7738a,a7739a,a7740a,a7743a,a7747a,a7748a,a7749a,a7753a,a7754a,a7758a,a7759a,a7760a,a7763a,a7767a,a7768a,a7769a,a7773a,a7774a,a7778a,a7779a,a7780a,a7783a,a7787a,a7788a,a7789a,a7793a,a7794a,a7798a,a7799a,a7800a,a7803a,a7807a,a7808a,a7809a,a7813a,a7814a,a7818a,a7819a,a7820a,a7823a,a7827a,a7828a,a7829a,a7833a,a7834a,a7838a,a7839a,a7840a,a7843a,a7847a,a7848a,a7849a,a7853a,a7854a,a7858a,a7859a,a7860a,a7863a,a7867a,a7868a,a7869a,a7873a,a7874a,a7878a,a7879a,a7880a,a7883a,a7887a,a7888a,a7889a,a7893a,a7894a,a7898a,a7899a,a7900a,a7903a,a7907a,a7908a,a7909a,a7913a,a7914a,a7918a,a7919a,a7920a,a7923a,a7927a,a7928a,a7929a,a7933a,a7934a,a7938a,a7939a,a7940a,a7943a,a7947a,a7948a,a7949a,a7953a,a7954a,a7958a,a7959a,a7960a,a7964a,a7965a,a7969a,a7970a,a7971a,a7975a,a7976a,a7980a,a7981a,a7982a,a7986a,a7987a,a7991a,a7992a,a7993a,a7997a,a7998a,a8002a,a8003a,a8004a,a8008a,a8009a,a8013a,a8014a,a8015a,a8019a,a8020a,a8024a,a8025a,a8026a,a8030a,a8031a,a8035a,a8036a,a8037a,a8041a,a8042a,a8046a,a8047a,a8048a,a8052a,a8053a,a8057a,a8058a,a8059a,a8063a,a8064a,a8068a,a8069a,a8070a,a8074a,a8075a,a8079a,a8080a,a8081a,a8085a,a8086a,a8090a,a8091a,a8092a,a8096a,a8097a,a8101a,a8102a,a8103a,a8107a,a8108a,a8112a,a8113a,a8114a,a8118a,a8119a,a8123a,a8124a,a8125a,a8129a,a8130a,a8134a,a8135a,a8136a,a8140a,a8141a,a8145a,a8146a,a8147a,a8151a,a8152a,a8156a,a8157a,a8158a,a8162a,a8163a,a8167a,a8168a,a8169a,a8173a,a8174a,a8178a,a8179a,a8180a,a8184a,a8185a,a8189a,a8190a,a8191a,a8195a,a8196a,a8200a,a8201a,a8202a,a8206a,a8207a,a8211a,a8212a,a8213a,a8217a,a8218a,a8222a,a8223a,a8224a,a8228a,a8229a,a8233a,a8234a,a8235a,a8239a,a8240a,a8244a,a8245a,a8246a,a8250a,a8251a,a8255a,a8256a,a8257a,a8261a,a8262a,a8266a,a8267a,a8268a,a8272a,a8273a,a8277a,a8278a,a8279a,a8283a,a8284a,a8288a,a8289a,a8290a,a8294a,a8295a,a8299a,a8300a,a8301a,a8305a,a8306a,a8310a,a8311a,a8312a,a8316a,a8317a,a8321a,a8322a,a8323a,a8327a,a8328a,a8332a,a8333a,a8334a,a8338a,a8339a,a8343a,a8344a,a8345a,a8349a,a8350a,a8354a,a8355a,a8356a,a8360a,a8361a,a8365a,a8366a,a8367a,a8371a,a8372a,a8376a,a8377a,a8378a,a8382a,a8383a,a8387a,a8388a,a8389a,a8393a,a8394a,a8398a,a8399a,a8400a,a8404a,a8405a,a8409a,a8410a,a8411a,a8415a,a8416a,a8420a,a8421a,a8422a,a8426a,a8427a,a8431a,a8432a,a8433a,a8437a,a8438a,a8442a,a8443a,a8444a,a8448a,a8449a,a8453a,a8454a,a8455a,a8459a,a8460a,a8464a,a8465a,a8466a,a8470a,a8471a,a8475a,a8476a,a8477a,a8481a,a8482a,a8486a,a8487a,a8488a,a8492a,a8493a,a8497a,a8498a,a8499a,a8503a,a8504a,a8508a,a8509a,a8510a,a8514a,a8515a,a8519a,a8520a,a8521a,a8525a,a8526a,a8530a,a8531a,a8532a,a8536a,a8537a,a8541a,a8542a,a8543a,a8547a,a8548a,a8552a,a8553a,a8554a,a8558a,a8559a,a8563a,a8564a,a8565a,a8569a,a8570a,a8574a,a8575a,a8576a,a8580a,a8581a,a8585a,a8586a,a8587a,a8591a,a8592a,a8596a,a8597a,a8598a,a8602a,a8603a,a8607a,a8608a,a8609a,a8613a,a8614a,a8618a,a8619a,a8620a,a8624a,a8625a,a8629a,a8630a,a8631a,a8635a,a8636a,a8640a,a8641a,a8642a,a8646a,a8647a,a8651a,a8652a,a8653a,a8657a,a8658a,a8662a,a8663a,a8664a,a8668a,a8669a,a8673a,a8674a,a8675a,a8679a,a8680a,a8684a,a8685a,a8686a,a8690a,a8691a,a8695a,a8696a,a8697a,a8701a,a8702a,a8706a,a8707a,a8708a,a8712a,a8713a,a8717a,a8718a,a8719a,a8723a,a8724a,a8728a,a8729a,a8730a,a8734a,a8735a,a8739a,a8740a,a8741a,a8745a,a8746a,a8750a,a8751a,a8752a,a8756a,a8757a,a8761a,a8762a,a8763a,a8767a,a8768a,a8772a,a8773a,a8774a,a8778a,a8779a,a8783a,a8784a,a8785a,a8789a,a8790a,a8794a,a8795a,a8796a,a8800a,a8801a,a8805a,a8806a,a8807a,a8811a,a8812a,a8816a,a8817a,a8818a,a8822a,a8823a,a8827a,a8828a,a8829a,a8833a,a8834a,a8838a,a8839a,a8840a,a8844a,a8845a,a8849a,a8850a,a8851a,a8855a,a8856a,a8860a,a8861a,a8862a,a8866a,a8867a,a8871a,a8872a,a8873a,a8877a,a8878a,a8882a,a8883a,a8884a,a8888a,a8889a,a8893a,a8894a,a8895a,a8899a,a8900a,a8904a,a8905a,a8906a,a8910a,a8911a,a8915a,a8916a,a8917a,a8921a,a8922a,a8926a,a8927a,a8928a,a8932a,a8933a,a8937a,a8938a,a8939a,a8943a,a8944a,a8948a,a8949a,a8950a,a8954a,a8955a,a8959a,a8960a,a8961a,a8965a,a8966a,a8970a,a8971a,a8972a,a8976a,a8977a,a8981a,a8982a,a8983a,a8987a,a8988a,a8992a,a8993a,a8994a,a8998a,a8999a,a9003a,a9004a,a9005a,a9009a,a9010a,a9014a,a9015a,a9016a,a9020a,a9021a,a9025a,a9026a,a9027a,a9031a,a9032a,a9036a,a9037a,a9038a,a9042a,a9043a,a9047a,a9048a,a9049a,a9053a,a9054a,a9058a,a9059a,a9060a,a9064a,a9065a,a9069a,a9070a,a9071a,a9075a,a9076a,a9080a,a9081a,a9082a,a9086a,a9087a,a9091a,a9092a,a9093a,a9097a,a9098a,a9102a,a9103a,a9104a,a9108a,a9109a,a9113a,a9114a,a9115a,a9119a,a9120a,a9124a,a9125a,a9126a,a9130a,a9131a,a9135a,a9136a,a9137a,a9141a,a9142a,a9146a,a9147a,a9148a,a9152a,a9153a,a9157a,a9158a,a9159a,a9163a,a9164a,a9168a,a9169a,a9170a,a9174a,a9175a,a9179a,a9180a,a9181a,a9185a,a9186a,a9190a,a9191a,a9192a,a9196a,a9197a,a9201a,a9202a,a9203a,a9207a,a9208a,a9212a,a9213a,a9214a,a9218a,a9219a,a9223a,a9224a,a9225a,a9229a,a9230a,a9234a,a9235a,a9236a,a9240a,a9241a,a9245a,a9246a,a9247a,a9251a,a9252a,a9256a,a9257a,a9258a,a9262a,a9263a,a9267a,a9268a,a9269a,a9273a,a9274a,a9278a,a9279a,a9280a,a9284a,a9285a,a9289a,a9290a,a9291a,a9295a,a9296a,a9300a,a9301a,a9302a,a9306a,a9307a,a9311a,a9312a,a9313a,a9317a,a9318a,a9322a,a9323a,a9324a,a9328a,a9329a,a9333a,a9334a,a9335a,a9339a,a9340a,a9344a,a9345a,a9346a,a9350a,a9351a,a9355a,a9356a,a9357a,a9361a,a9362a,a9366a,a9367a,a9368a,a9372a,a9373a,a9377a,a9378a,a9379a,a9383a,a9384a,a9387a,a9390a,a9391a,a9392a,a9396a,a9397a,a9401a,a9402a,a9403a,a9407a,a9408a,a9411a,a9414a,a9415a,a9416a,a9420a,a9421a,a9425a,a9426a,a9427a,a9431a,a9432a,a9435a,a9438a,a9439a,a9440a,a9444a,a9445a,a9449a,a9450a,a9451a,a9455a,a9456a,a9459a,a9462a,a9463a,a9464a,a9468a,a9469a,a9473a,a9474a,a9475a,a9479a,a9480a,a9483a,a9486a,a9487a,a9488a,a9492a,a9493a,a9497a,a9498a,a9499a,a9503a,a9504a,a9507a,a9510a,a9511a,a9512a,a9516a,a9517a,a9521a,a9522a,a9523a,a9527a,a9528a,a9531a,a9534a,a9535a,a9536a,a9540a,a9541a,a9545a,a9546a,a9547a,a9551a,a9552a,a9555a,a9558a,a9559a,a9560a: std_logic;
begin
A8 <=( a1312a ) or ( a875a );
a1a <=( a9560a and a9547a );
a2a <=( a9536a and a9523a );
a3a <=( a9512a and a9499a );
a4a <=( a9488a and a9475a );
a5a <=( a9464a and a9451a );
a6a <=( a9440a and a9427a );
a7a <=( a9416a and a9403a );
a8a <=( a9392a and a9379a );
a9a <=( a9368a and a9357a );
a10a <=( a9346a and a9335a );
a11a <=( a9324a and a9313a );
a12a <=( a9302a and a9291a );
a13a <=( a9280a and a9269a );
a14a <=( a9258a and a9247a );
a15a <=( a9236a and a9225a );
a16a <=( a9214a and a9203a );
a17a <=( a9192a and a9181a );
a18a <=( a9170a and a9159a );
a19a <=( a9148a and a9137a );
a20a <=( a9126a and a9115a );
a21a <=( a9104a and a9093a );
a22a <=( a9082a and a9071a );
a23a <=( a9060a and a9049a );
a24a <=( a9038a and a9027a );
a25a <=( a9016a and a9005a );
a26a <=( a8994a and a8983a );
a27a <=( a8972a and a8961a );
a28a <=( a8950a and a8939a );
a29a <=( a8928a and a8917a );
a30a <=( a8906a and a8895a );
a31a <=( a8884a and a8873a );
a32a <=( a8862a and a8851a );
a33a <=( a8840a and a8829a );
a34a <=( a8818a and a8807a );
a35a <=( a8796a and a8785a );
a36a <=( a8774a and a8763a );
a37a <=( a8752a and a8741a );
a38a <=( a8730a and a8719a );
a39a <=( a8708a and a8697a );
a40a <=( a8686a and a8675a );
a41a <=( a8664a and a8653a );
a42a <=( a8642a and a8631a );
a43a <=( a8620a and a8609a );
a44a <=( a8598a and a8587a );
a45a <=( a8576a and a8565a );
a46a <=( a8554a and a8543a );
a47a <=( a8532a and a8521a );
a48a <=( a8510a and a8499a );
a49a <=( a8488a and a8477a );
a50a <=( a8466a and a8455a );
a51a <=( a8444a and a8433a );
a52a <=( a8422a and a8411a );
a53a <=( a8400a and a8389a );
a54a <=( a8378a and a8367a );
a55a <=( a8356a and a8345a );
a56a <=( a8334a and a8323a );
a57a <=( a8312a and a8301a );
a58a <=( a8290a and a8279a );
a59a <=( a8268a and a8257a );
a60a <=( a8246a and a8235a );
a61a <=( a8224a and a8213a );
a62a <=( a8202a and a8191a );
a63a <=( a8180a and a8169a );
a64a <=( a8158a and a8147a );
a65a <=( a8136a and a8125a );
a66a <=( a8114a and a8103a );
a67a <=( a8092a and a8081a );
a68a <=( a8070a and a8059a );
a69a <=( a8048a and a8037a );
a70a <=( a8026a and a8015a );
a71a <=( a8004a and a7993a );
a72a <=( a7982a and a7971a );
a73a <=( a7960a and a7949a );
a74a <=( a7940a and a7929a );
a75a <=( a7920a and a7909a );
a76a <=( a7900a and a7889a );
a77a <=( a7880a and a7869a );
a78a <=( a7860a and a7849a );
a79a <=( a7840a and a7829a );
a80a <=( a7820a and a7809a );
a81a <=( a7800a and a7789a );
a82a <=( a7780a and a7769a );
a83a <=( a7760a and a7749a );
a84a <=( a7740a and a7729a );
a85a <=( a7720a and a7709a );
a86a <=( a7700a and a7689a );
a87a <=( a7680a and a7669a );
a88a <=( a7660a and a7649a );
a89a <=( a7640a and a7629a );
a90a <=( a7620a and a7609a );
a91a <=( a7600a and a7589a );
a92a <=( a7580a and a7569a );
a93a <=( a7560a and a7549a );
a94a <=( a7540a and a7529a );
a95a <=( a7520a and a7509a );
a96a <=( a7500a and a7489a );
a97a <=( a7480a and a7469a );
a98a <=( a7460a and a7449a );
a99a <=( a7440a and a7429a );
a100a <=( a7420a and a7409a );
a101a <=( a7400a and a7389a );
a102a <=( a7380a and a7369a );
a103a <=( a7360a and a7349a );
a104a <=( a7340a and a7329a );
a105a <=( a7320a and a7309a );
a106a <=( a7300a and a7289a );
a107a <=( a7280a and a7269a );
a108a <=( a7260a and a7249a );
a109a <=( a7240a and a7229a );
a110a <=( a7220a and a7209a );
a111a <=( a7200a and a7189a );
a112a <=( a7180a and a7169a );
a113a <=( a7160a and a7149a );
a114a <=( a7140a and a7129a );
a115a <=( a7120a and a7109a );
a116a <=( a7100a and a7089a );
a117a <=( a7080a and a7069a );
a118a <=( a7060a and a7049a );
a119a <=( a7040a and a7029a );
a120a <=( a7020a and a7009a );
a121a <=( a7000a and a6989a );
a122a <=( a6980a and a6969a );
a123a <=( a6960a and a6949a );
a124a <=( a6940a and a6929a );
a125a <=( a6920a and a6909a );
a126a <=( a6900a and a6889a );
a127a <=( a6880a and a6869a );
a128a <=( a6860a and a6849a );
a129a <=( a6840a and a6829a );
a130a <=( a6820a and a6809a );
a131a <=( a6800a and a6789a );
a132a <=( a6780a and a6769a );
a133a <=( a6760a and a6749a );
a134a <=( a6740a and a6729a );
a135a <=( a6720a and a6709a );
a136a <=( a6700a and a6689a );
a137a <=( a6680a and a6669a );
a138a <=( a6660a and a6649a );
a139a <=( a6640a and a6629a );
a140a <=( a6620a and a6609a );
a141a <=( a6600a and a6589a );
a142a <=( a6580a and a6569a );
a143a <=( a6560a and a6549a );
a144a <=( a6540a and a6529a );
a145a <=( a6520a and a6509a );
a146a <=( a6500a and a6489a );
a147a <=( a6480a and a6469a );
a148a <=( a6460a and a6449a );
a149a <=( a6440a and a6429a );
a150a <=( a6420a and a6409a );
a151a <=( a6400a and a6389a );
a152a <=( a6380a and a6369a );
a153a <=( a6360a and a6349a );
a154a <=( a6340a and a6329a );
a155a <=( a6320a and a6309a );
a156a <=( a6300a and a6289a );
a157a <=( a6280a and a6269a );
a158a <=( a6260a and a6249a );
a159a <=( a6240a and a6229a );
a160a <=( a6220a and a6209a );
a161a <=( a6200a and a6189a );
a162a <=( a6180a and a6169a );
a163a <=( a6160a and a6149a );
a164a <=( a6140a and a6129a );
a165a <=( a6120a and a6109a );
a166a <=( a6100a and a6089a );
a167a <=( a6080a and a6069a );
a168a <=( a6060a and a6049a );
a169a <=( a6040a and a6029a );
a170a <=( a6020a and a6009a );
a171a <=( a6000a and a5989a );
a172a <=( a5980a and a5969a );
a173a <=( a5960a and a5949a );
a174a <=( a5940a and a5929a );
a175a <=( a5920a and a5909a );
a176a <=( a5900a and a5889a );
a177a <=( a5880a and a5869a );
a178a <=( a5860a and a5849a );
a179a <=( a5840a and a5829a );
a180a <=( a5820a and a5809a );
a181a <=( a5800a and a5789a );
a182a <=( a5780a and a5769a );
a183a <=( a5760a and a5749a );
a184a <=( a5740a and a5729a );
a185a <=( a5720a and a5709a );
a186a <=( a5700a and a5689a );
a187a <=( a5680a and a5669a );
a188a <=( a5660a and a5649a );
a189a <=( a5640a and a5629a );
a190a <=( a5620a and a5609a );
a191a <=( a5600a and a5589a );
a192a <=( a5580a and a5569a );
a193a <=( a5560a and a5549a );
a194a <=( a5540a and a5529a );
a195a <=( a5520a and a5509a );
a196a <=( a5500a and a5489a );
a197a <=( a5480a and a5469a );
a198a <=( a5460a and a5449a );
a199a <=( a5440a and a5429a );
a200a <=( a5420a and a5409a );
a201a <=( a5400a and a5389a );
a202a <=( a5380a and a5369a );
a203a <=( a5360a and a5349a );
a204a <=( a5340a and a5329a );
a205a <=( a5320a and a5309a );
a206a <=( a5300a and a5289a );
a207a <=( a5280a and a5269a );
a208a <=( a5260a and a5249a );
a209a <=( a5240a and a5229a );
a210a <=( a5220a and a5209a );
a211a <=( a5200a and a5189a );
a212a <=( a5180a and a5169a );
a213a <=( a5160a and a5149a );
a214a <=( a5140a and a5129a );
a215a <=( a5120a and a5109a );
a216a <=( a5100a and a5089a );
a217a <=( a5080a and a5069a );
a218a <=( a5060a and a5049a );
a219a <=( a5040a and a5029a );
a220a <=( a5020a and a5009a );
a221a <=( a5000a and a4989a );
a222a <=( a4980a and a4969a );
a223a <=( a4960a and a4949a );
a224a <=( a4940a and a4929a );
a225a <=( a4920a and a4909a );
a226a <=( a4900a and a4889a );
a227a <=( a4880a and a4869a );
a228a <=( a4860a and a4849a );
a229a <=( a4840a and a4829a );
a230a <=( a4820a and a4809a );
a231a <=( a4800a and a4789a );
a232a <=( a4780a and a4769a );
a233a <=( a4760a and a4751a );
a234a <=( a4742a and a4733a );
a235a <=( a4724a and a4715a );
a236a <=( a4706a and a4697a );
a237a <=( a4688a and a4679a );
a238a <=( a4670a and a4661a );
a239a <=( a4652a and a4643a );
a240a <=( a4634a and a4625a );
a241a <=( a4616a and a4607a );
a242a <=( a4598a and a4589a );
a243a <=( a4580a and a4571a );
a244a <=( a4562a and a4553a );
a245a <=( a4544a and a4535a );
a246a <=( a4526a and a4517a );
a247a <=( a4508a and a4499a );
a248a <=( a4490a and a4481a );
a249a <=( a4472a and a4463a );
a250a <=( a4454a and a4445a );
a251a <=( a4436a and a4427a );
a252a <=( a4418a and a4409a );
a253a <=( a4400a and a4391a );
a254a <=( a4382a and a4373a );
a255a <=( a4364a and a4355a );
a256a <=( a4346a and a4337a );
a257a <=( a4328a and a4319a );
a258a <=( a4310a and a4301a );
a259a <=( a4292a and a4283a );
a260a <=( a4274a and a4265a );
a261a <=( a4256a and a4247a );
a262a <=( a4238a and a4229a );
a263a <=( a4220a and a4211a );
a264a <=( a4202a and a4193a );
a265a <=( a4184a and a4175a );
a266a <=( a4166a and a4157a );
a267a <=( a4148a and a4139a );
a268a <=( a4130a and a4121a );
a269a <=( a4112a and a4103a );
a270a <=( a4094a and a4085a );
a271a <=( a4076a and a4067a );
a272a <=( a4058a and a4049a );
a273a <=( a4040a and a4031a );
a274a <=( a4022a and a4013a );
a275a <=( a4004a and a3995a );
a276a <=( a3986a and a3977a );
a277a <=( a3968a and a3959a );
a278a <=( a3950a and a3941a );
a279a <=( a3932a and a3923a );
a280a <=( a3914a and a3905a );
a281a <=( a3896a and a3887a );
a282a <=( a3878a and a3869a );
a283a <=( a3860a and a3851a );
a284a <=( a3842a and a3833a );
a285a <=( a3824a and a3815a );
a286a <=( a3806a and a3797a );
a287a <=( a3788a and a3779a );
a288a <=( a3770a and a3761a );
a289a <=( a3752a and a3743a );
a290a <=( a3734a and a3725a );
a291a <=( a3716a and a3707a );
a292a <=( a3698a and a3689a );
a293a <=( a3680a and a3671a );
a294a <=( a3662a and a3653a );
a295a <=( a3644a and a3635a );
a296a <=( a3626a and a3617a );
a297a <=( a3608a and a3599a );
a298a <=( a3590a and a3581a );
a299a <=( a3572a and a3563a );
a300a <=( a3554a and a3545a );
a301a <=( a3536a and a3527a );
a302a <=( a3518a and a3509a );
a303a <=( a3500a and a3491a );
a304a <=( a3482a and a3473a );
a305a <=( a3464a and a3455a );
a306a <=( a3446a and a3437a );
a307a <=( a3428a and a3419a );
a308a <=( a3410a and a3401a );
a309a <=( a3392a and a3383a );
a310a <=( a3374a and a3365a );
a311a <=( a3356a and a3347a );
a312a <=( a3338a and a3329a );
a313a <=( a3320a and a3311a );
a314a <=( a3302a and a3293a );
a315a <=( a3284a and a3275a );
a316a <=( a3266a and a3257a );
a317a <=( a3248a and a3239a );
a318a <=( a3230a and a3221a );
a319a <=( a3212a and a3203a );
a320a <=( a3194a and a3185a );
a321a <=( a3176a and a3167a );
a322a <=( a3158a and a3149a );
a323a <=( a3140a and a3131a );
a324a <=( a3122a and a3113a );
a325a <=( a3104a and a3095a );
a326a <=( a3086a and a3077a );
a327a <=( a3068a and a3059a );
a328a <=( a3050a and a3041a );
a329a <=( a3032a and a3023a );
a330a <=( a3014a and a3005a );
a331a <=( a2996a and a2987a );
a332a <=( a2978a and a2969a );
a333a <=( a2960a and a2951a );
a334a <=( a2942a and a2933a );
a335a <=( a2924a and a2915a );
a336a <=( a2906a and a2897a );
a337a <=( a2888a and a2879a );
a338a <=( a2870a and a2861a );
a339a <=( a2852a and a2843a );
a340a <=( a2834a and a2825a );
a341a <=( a2816a and a2807a );
a342a <=( a2798a and a2789a );
a343a <=( a2780a and a2771a );
a344a <=( a2762a and a2753a );
a345a <=( a2744a and a2735a );
a346a <=( a2726a and a2717a );
a347a <=( a2708a and a2699a );
a348a <=( a2690a and a2681a );
a349a <=( a2672a and a2663a );
a350a <=( a2654a and a2645a );
a351a <=( a2636a and a2627a );
a352a <=( a2618a and a2609a );
a353a <=( a2600a and a2591a );
a354a <=( a2582a and a2573a );
a355a <=( a2564a and a2555a );
a356a <=( a2546a and a2537a );
a357a <=( a2528a and a2519a );
a358a <=( a2510a and a2501a );
a359a <=( a2492a and a2483a );
a360a <=( a2474a and a2465a );
a361a <=( a2456a and a2447a );
a362a <=( a2438a and a2429a );
a363a <=( a2420a and a2411a );
a364a <=( a2402a and a2393a );
a365a <=( a2384a and a2375a );
a366a <=( a2366a and a2357a );
a367a <=( a2348a and a2339a );
a368a <=( a2330a and a2321a );
a369a <=( a2312a and a2303a );
a370a <=( a2296a and a2287a );
a371a <=( a2280a and a2271a );
a372a <=( a2264a and a2255a );
a373a <=( a2248a and a2239a );
a374a <=( a2232a and a2223a );
a375a <=( a2216a and a2207a );
a376a <=( a2200a and a2191a );
a377a <=( a2184a and a2175a );
a378a <=( a2168a and a2159a );
a379a <=( a2152a and a2143a );
a380a <=( a2136a and a2127a );
a381a <=( a2120a and a2111a );
a382a <=( a2104a and a2095a );
a383a <=( a2088a and a2079a );
a384a <=( a2072a and a2063a );
a385a <=( a2056a and a2047a );
a386a <=( a2040a and a2031a );
a387a <=( a2024a and a2015a );
a388a <=( a2008a and a1999a );
a389a <=( a1992a and a1983a );
a390a <=( a1976a and a1967a );
a391a <=( a1960a and a1951a );
a392a <=( a1944a and a1935a );
a393a <=( a1928a and a1919a );
a394a <=( a1912a and a1903a );
a395a <=( a1896a and a1887a );
a396a <=( a1880a and a1871a );
a397a <=( a1864a and a1855a );
a398a <=( a1848a and a1839a );
a399a <=( a1832a and a1823a );
a400a <=( a1816a and a1807a );
a401a <=( a1800a and a1793a );
a402a <=( a1786a and a1779a );
a403a <=( a1772a and a1765a );
a404a <=( a1758a and a1751a );
a405a <=( a1744a and a1737a );
a406a <=( a1730a and a1723a );
a407a <=( a1716a and a1709a );
a408a <=( a1702a and a1695a );
a409a <=( a1688a and a1681a );
a410a <=( a1674a and a1667a );
a411a <=( a1660a and a1653a );
a412a <=( a1646a and a1639a );
a413a <=( a1632a and a1625a );
a414a <=( a1618a and a1611a );
a415a <=( a1604a and a1597a );
a416a <=( a1590a and a1583a );
a417a <=( a1576a and a1569a );
a418a <=( a1562a and a1555a );
a419a <=( a1548a and a1541a );
a420a <=( a1534a and a1527a );
a421a <=( a1520a and a1513a );
a422a <=( a1506a and a1499a );
a423a <=( a1492a and a1485a );
a424a <=( a1478a and a1471a );
a425a <=( a1464a and a1457a );
a426a <=( a1450a and a1443a );
a427a <=( a1436a and a1429a );
a428a <=( a1422a and a1415a );
a429a <=( a1408a and a1401a );
a430a <=( a1394a and a1387a );
a431a <=( a1380a and a1373a );
a432a <=( a1366a and a1359a );
a433a <=( a1352a and a1347a );
a434a <=( a1344a and a1339a );
a435a <=( a1336a and a1333a );
a436a <=( a1330a and a1327a );
a437a <=( a1324a and a1321a );
a438a <=( a1318a and a1315a );
a442a <=( a436a ) or ( a437a );
a443a <=( a438a ) or ( a442a );
a447a <=( a433a ) or ( a434a );
a448a <=( a435a ) or ( a447a );
a449a <=( a448a ) or ( a443a );
a453a <=( a430a ) or ( a431a );
a454a <=( a432a ) or ( a453a );
a457a <=( a428a ) or ( a429a );
a460a <=( a426a ) or ( a427a );
a461a <=( a460a ) or ( a457a );
a462a <=( a461a ) or ( a454a );
a463a <=( a462a ) or ( a449a );
a467a <=( a423a ) or ( a424a );
a468a <=( a425a ) or ( a467a );
a471a <=( a421a ) or ( a422a );
a474a <=( a419a ) or ( a420a );
a475a <=( a474a ) or ( a471a );
a476a <=( a475a ) or ( a468a );
a480a <=( a416a ) or ( a417a );
a481a <=( a418a ) or ( a480a );
a484a <=( a414a ) or ( a415a );
a487a <=( a412a ) or ( a413a );
a488a <=( a487a ) or ( a484a );
a489a <=( a488a ) or ( a481a );
a490a <=( a489a ) or ( a476a );
a491a <=( a490a ) or ( a463a );
a495a <=( a409a ) or ( a410a );
a496a <=( a411a ) or ( a495a );
a500a <=( a406a ) or ( a407a );
a501a <=( a408a ) or ( a500a );
a502a <=( a501a ) or ( a496a );
a506a <=( a403a ) or ( a404a );
a507a <=( a405a ) or ( a506a );
a510a <=( a401a ) or ( a402a );
a513a <=( a399a ) or ( a400a );
a514a <=( a513a ) or ( a510a );
a515a <=( a514a ) or ( a507a );
a516a <=( a515a ) or ( a502a );
a520a <=( a396a ) or ( a397a );
a521a <=( a398a ) or ( a520a );
a524a <=( a394a ) or ( a395a );
a527a <=( a392a ) or ( a393a );
a528a <=( a527a ) or ( a524a );
a529a <=( a528a ) or ( a521a );
a533a <=( a389a ) or ( a390a );
a534a <=( a391a ) or ( a533a );
a537a <=( a387a ) or ( a388a );
a540a <=( a385a ) or ( a386a );
a541a <=( a540a ) or ( a537a );
a542a <=( a541a ) or ( a534a );
a543a <=( a542a ) or ( a529a );
a544a <=( a543a ) or ( a516a );
a545a <=( a544a ) or ( a491a );
a549a <=( a382a ) or ( a383a );
a550a <=( a384a ) or ( a549a );
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a555a <=( a381a ) or ( a554a );
a556a <=( a555a ) or ( a550a );
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a564a <=( a374a ) or ( a375a );
a567a <=( a372a ) or ( a373a );
a568a <=( a567a ) or ( a564a );
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a575a <=( a371a ) or ( a574a );
a578a <=( a367a ) or ( a368a );
a581a <=( a365a ) or ( a366a );
a582a <=( a581a ) or ( a578a );
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a588a <=( a364a ) or ( a587a );
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a595a <=( a594a ) or ( a591a );
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a597a <=( a596a ) or ( a583a );
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a602a <=( a355a ) or ( a356a );
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a611a <=( a610a ) or ( a603a );
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a616a <=( a350a ) or ( a615a );
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a624a <=( a623a ) or ( a616a );
a625a <=( a624a ) or ( a611a );
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a630a <=( a343a ) or ( a629a );
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a650a <=( a649a ) or ( a646a );
a651a <=( a650a ) or ( a643a );
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a655a <=( a654a ) or ( a545a );
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a665a <=( a326a ) or ( a664a );
a666a <=( a665a ) or ( a660a );
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a671a <=( a323a ) or ( a670a );
a674a <=( a319a ) or ( a320a );
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a678a <=( a677a ) or ( a674a );
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a680a <=( a679a ) or ( a666a );
a684a <=( a314a ) or ( a315a );
a685a <=( a316a ) or ( a684a );
a688a <=( a312a ) or ( a313a );
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a692a <=( a691a ) or ( a688a );
a693a <=( a692a ) or ( a685a );
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a698a <=( a309a ) or ( a697a );
a701a <=( a305a ) or ( a306a );
a704a <=( a303a ) or ( a304a );
a705a <=( a704a ) or ( a701a );
a706a <=( a705a ) or ( a698a );
a707a <=( a706a ) or ( a693a );
a708a <=( a707a ) or ( a680a );
a712a <=( a300a ) or ( a301a );
a713a <=( a302a ) or ( a712a );
a716a <=( a298a ) or ( a299a );
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a720a <=( a719a ) or ( a716a );
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a725a <=( a293a ) or ( a294a );
a726a <=( a295a ) or ( a725a );
a729a <=( a291a ) or ( a292a );
a732a <=( a289a ) or ( a290a );
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a735a <=( a734a ) or ( a721a );
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a740a <=( a288a ) or ( a739a );
a743a <=( a284a ) or ( a285a );
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a747a <=( a746a ) or ( a743a );
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a752a <=( a279a ) or ( a280a );
a753a <=( a281a ) or ( a752a );
a756a <=( a277a ) or ( a278a );
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a760a <=( a759a ) or ( a756a );
a761a <=( a760a ) or ( a753a );
a762a <=( a761a ) or ( a748a );
a763a <=( a762a ) or ( a735a );
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a768a <=( a272a ) or ( a273a );
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a773a <=( a269a ) or ( a270a );
a774a <=( a271a ) or ( a773a );
a775a <=( a774a ) or ( a769a );
a779a <=( a266a ) or ( a267a );
a780a <=( a268a ) or ( a779a );
a783a <=( a264a ) or ( a265a );
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a787a <=( a786a ) or ( a783a );
a788a <=( a787a ) or ( a780a );
a789a <=( a788a ) or ( a775a );
a793a <=( a259a ) or ( a260a );
a794a <=( a261a ) or ( a793a );
a797a <=( a257a ) or ( a258a );
a800a <=( a255a ) or ( a256a );
a801a <=( a800a ) or ( a797a );
a802a <=( a801a ) or ( a794a );
a806a <=( a252a ) or ( a253a );
a807a <=( a254a ) or ( a806a );
a810a <=( a250a ) or ( a251a );
a813a <=( a248a ) or ( a249a );
a814a <=( a813a ) or ( a810a );
a815a <=( a814a ) or ( a807a );
a816a <=( a815a ) or ( a802a );
a817a <=( a816a ) or ( a789a );
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a825a <=( a243a ) or ( a244a );
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a829a <=( a828a ) or ( a825a );
a830a <=( a829a ) or ( a822a );
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a835a <=( a240a ) or ( a834a );
a838a <=( a236a ) or ( a237a );
a841a <=( a234a ) or ( a235a );
a842a <=( a841a ) or ( a838a );
a843a <=( a842a ) or ( a835a );
a844a <=( a843a ) or ( a830a );
a848a <=( a231a ) or ( a232a );
a849a <=( a233a ) or ( a848a );
a852a <=( a229a ) or ( a230a );
a855a <=( a227a ) or ( a228a );
a856a <=( a855a ) or ( a852a );
a857a <=( a856a ) or ( a849a );
a861a <=( a224a ) or ( a225a );
a862a <=( a226a ) or ( a861a );
a865a <=( a222a ) or ( a223a );
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a869a <=( a868a ) or ( a865a );
a870a <=( a869a ) or ( a862a );
a871a <=( a870a ) or ( a857a );
a872a <=( a871a ) or ( a844a );
a873a <=( a872a ) or ( a817a );
a874a <=( a873a ) or ( a764a );
a875a <=( a874a ) or ( a655a );
a879a <=( a217a ) or ( a218a );
a880a <=( a219a ) or ( a879a );
a884a <=( a214a ) or ( a215a );
a885a <=( a216a ) or ( a884a );
a886a <=( a885a ) or ( a880a );
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a891a <=( a213a ) or ( a890a );
a894a <=( a209a ) or ( a210a );
a897a <=( a207a ) or ( a208a );
a898a <=( a897a ) or ( a894a );
a899a <=( a898a ) or ( a891a );
a900a <=( a899a ) or ( a886a );
a904a <=( a204a ) or ( a205a );
a905a <=( a206a ) or ( a904a );
a908a <=( a202a ) or ( a203a );
a911a <=( a200a ) or ( a201a );
a912a <=( a911a ) or ( a908a );
a913a <=( a912a ) or ( a905a );
a917a <=( a197a ) or ( a198a );
a918a <=( a199a ) or ( a917a );
a921a <=( a195a ) or ( a196a );
a924a <=( a193a ) or ( a194a );
a925a <=( a924a ) or ( a921a );
a926a <=( a925a ) or ( a918a );
a927a <=( a926a ) or ( a913a );
a928a <=( a927a ) or ( a900a );
a932a <=( a190a ) or ( a191a );
a933a <=( a192a ) or ( a932a );
a937a <=( a187a ) or ( a188a );
a938a <=( a189a ) or ( a937a );
a939a <=( a938a ) or ( a933a );
a943a <=( a184a ) or ( a185a );
a944a <=( a186a ) or ( a943a );
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a950a <=( a180a ) or ( a181a );
a951a <=( a950a ) or ( a947a );
a952a <=( a951a ) or ( a944a );
a953a <=( a952a ) or ( a939a );
a957a <=( a177a ) or ( a178a );
a958a <=( a179a ) or ( a957a );
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a964a <=( a173a ) or ( a174a );
a965a <=( a964a ) or ( a961a );
a966a <=( a965a ) or ( a958a );
a970a <=( a170a ) or ( a171a );
a971a <=( a172a ) or ( a970a );
a974a <=( a168a ) or ( a169a );
a977a <=( a166a ) or ( a167a );
a978a <=( a977a ) or ( a974a );
a979a <=( a978a ) or ( a971a );
a980a <=( a979a ) or ( a966a );
a981a <=( a980a ) or ( a953a );
a982a <=( a981a ) or ( a928a );
a986a <=( a163a ) or ( a164a );
a987a <=( a165a ) or ( a986a );
a991a <=( a160a ) or ( a161a );
a992a <=( a162a ) or ( a991a );
a993a <=( a992a ) or ( a987a );
a997a <=( a157a ) or ( a158a );
a998a <=( a159a ) or ( a997a );
a1001a <=( a155a ) or ( a156a );
a1004a <=( a153a ) or ( a154a );
a1005a <=( a1004a ) or ( a1001a );
a1006a <=( a1005a ) or ( a998a );
a1007a <=( a1006a ) or ( a993a );
a1011a <=( a150a ) or ( a151a );
a1012a <=( a152a ) or ( a1011a );
a1015a <=( a148a ) or ( a149a );
a1018a <=( a146a ) or ( a147a );
a1019a <=( a1018a ) or ( a1015a );
a1020a <=( a1019a ) or ( a1012a );
a1024a <=( a143a ) or ( a144a );
a1025a <=( a145a ) or ( a1024a );
a1028a <=( a141a ) or ( a142a );
a1031a <=( a139a ) or ( a140a );
a1032a <=( a1031a ) or ( a1028a );
a1033a <=( a1032a ) or ( a1025a );
a1034a <=( a1033a ) or ( a1020a );
a1035a <=( a1034a ) or ( a1007a );
a1039a <=( a136a ) or ( a137a );
a1040a <=( a138a ) or ( a1039a );
a1043a <=( a134a ) or ( a135a );
a1046a <=( a132a ) or ( a133a );
a1047a <=( a1046a ) or ( a1043a );
a1048a <=( a1047a ) or ( a1040a );
a1052a <=( a129a ) or ( a130a );
a1053a <=( a131a ) or ( a1052a );
a1056a <=( a127a ) or ( a128a );
a1059a <=( a125a ) or ( a126a );
a1060a <=( a1059a ) or ( a1056a );
a1061a <=( a1060a ) or ( a1053a );
a1062a <=( a1061a ) or ( a1048a );
a1066a <=( a122a ) or ( a123a );
a1067a <=( a124a ) or ( a1066a );
a1070a <=( a120a ) or ( a121a );
a1073a <=( a118a ) or ( a119a );
a1074a <=( a1073a ) or ( a1070a );
a1075a <=( a1074a ) or ( a1067a );
a1079a <=( a115a ) or ( a116a );
a1080a <=( a117a ) or ( a1079a );
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a1086a <=( a111a ) or ( a112a );
a1087a <=( a1086a ) or ( a1083a );
a1088a <=( a1087a ) or ( a1080a );
a1089a <=( a1088a ) or ( a1075a );
a1090a <=( a1089a ) or ( a1062a );
a1091a <=( a1090a ) or ( a1035a );
a1092a <=( a1091a ) or ( a982a );
a1096a <=( a108a ) or ( a109a );
a1097a <=( a110a ) or ( a1096a );
a1101a <=( a105a ) or ( a106a );
a1102a <=( a107a ) or ( a1101a );
a1103a <=( a1102a ) or ( a1097a );
a1107a <=( a102a ) or ( a103a );
a1108a <=( a104a ) or ( a1107a );
a1111a <=( a100a ) or ( a101a );
a1114a <=( a98a ) or ( a99a );
a1115a <=( a1114a ) or ( a1111a );
a1116a <=( a1115a ) or ( a1108a );
a1117a <=( a1116a ) or ( a1103a );
a1121a <=( a95a ) or ( a96a );
a1122a <=( a97a ) or ( a1121a );
a1125a <=( a93a ) or ( a94a );
a1128a <=( a91a ) or ( a92a );
a1129a <=( a1128a ) or ( a1125a );
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a1135a <=( a90a ) or ( a1134a );
a1138a <=( a86a ) or ( a87a );
a1141a <=( a84a ) or ( a85a );
a1142a <=( a1141a ) or ( a1138a );
a1143a <=( a1142a ) or ( a1135a );
a1144a <=( a1143a ) or ( a1130a );
a1145a <=( a1144a ) or ( a1117a );
a1149a <=( a81a ) or ( a82a );
a1150a <=( a83a ) or ( a1149a );
a1153a <=( a79a ) or ( a80a );
a1156a <=( a77a ) or ( a78a );
a1157a <=( a1156a ) or ( a1153a );
a1158a <=( a1157a ) or ( a1150a );
a1162a <=( a74a ) or ( a75a );
a1163a <=( a76a ) or ( a1162a );
a1166a <=( a72a ) or ( a73a );
a1169a <=( a70a ) or ( a71a );
a1170a <=( a1169a ) or ( a1166a );
a1171a <=( a1170a ) or ( a1163a );
a1172a <=( a1171a ) or ( a1158a );
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a1177a <=( a69a ) or ( a1176a );
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a1183a <=( a63a ) or ( a64a );
a1184a <=( a1183a ) or ( a1180a );
a1185a <=( a1184a ) or ( a1177a );
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a1190a <=( a62a ) or ( a1189a );
a1193a <=( a58a ) or ( a59a );
a1196a <=( a56a ) or ( a57a );
a1197a <=( a1196a ) or ( a1193a );
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a1200a <=( a1199a ) or ( a1172a );
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a1206a <=( a55a ) or ( a1205a );
a1210a <=( a50a ) or ( a51a );
a1211a <=( a52a ) or ( a1210a );
a1212a <=( a1211a ) or ( a1206a );
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a1217a <=( a49a ) or ( a1216a );
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a1225a <=( a1224a ) or ( a1217a );
a1226a <=( a1225a ) or ( a1212a );
a1230a <=( a40a ) or ( a41a );
a1231a <=( a42a ) or ( a1230a );
a1234a <=( a38a ) or ( a39a );
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a1238a <=( a1237a ) or ( a1234a );
a1239a <=( a1238a ) or ( a1231a );
a1243a <=( a33a ) or ( a34a );
a1244a <=( a35a ) or ( a1243a );
a1247a <=( a31a ) or ( a32a );
a1250a <=( a29a ) or ( a30a );
a1251a <=( a1250a ) or ( a1247a );
a1252a <=( a1251a ) or ( a1244a );
a1253a <=( a1252a ) or ( a1239a );
a1254a <=( a1253a ) or ( a1226a );
a1258a <=( a26a ) or ( a27a );
a1259a <=( a28a ) or ( a1258a );
a1262a <=( a24a ) or ( a25a );
a1265a <=( a22a ) or ( a23a );
a1266a <=( a1265a ) or ( a1262a );
a1267a <=( a1266a ) or ( a1259a );
a1271a <=( a19a ) or ( a20a );
a1272a <=( a21a ) or ( a1271a );
a1275a <=( a17a ) or ( a18a );
a1278a <=( a15a ) or ( a16a );
a1279a <=( a1278a ) or ( a1275a );
a1280a <=( a1279a ) or ( a1272a );
a1281a <=( a1280a ) or ( a1267a );
a1285a <=( a12a ) or ( a13a );
a1286a <=( a14a ) or ( a1285a );
a1289a <=( a10a ) or ( a11a );
a1292a <=( a8a ) or ( a9a );
a1293a <=( a1292a ) or ( a1289a );
a1294a <=( a1293a ) or ( a1286a );
a1298a <=( a5a ) or ( a6a );
a1299a <=( a7a ) or ( a1298a );
a1302a <=( a3a ) or ( a4a );
a1305a <=( a1a ) or ( a2a );
a1306a <=( a1305a ) or ( a1302a );
a1307a <=( a1306a ) or ( a1299a );
a1308a <=( a1307a ) or ( a1294a );
a1309a <=( a1308a ) or ( a1281a );
a1310a <=( a1309a ) or ( a1254a );
a1311a <=( a1310a ) or ( a1201a );
a1312a <=( a1311a ) or ( a1092a );
a1315a <=( A200 and (not A199) );
a1318a <=( A202 and A201 );
a1321a <=( A200 and (not A199) );
a1324a <=( (not A203) and A201 );
a1327a <=( (not A200) and A199 );
a1330a <=( A202 and A201 );
a1333a <=( (not A200) and A199 );
a1336a <=( (not A203) and A201 );
a1339a <=( A200 and (not A199) );
a1343a <=( A203 and (not A202) );
a1344a <=( (not A201) and a1343a );
a1347a <=( (not A200) and A199 );
a1351a <=( A203 and (not A202) );
a1352a <=( (not A201) and a1351a );
a1355a <=( A233 and (not A232) );
a1358a <=( A235 and A234 );
a1359a <=( a1358a and a1355a );
a1362a <=( (not A299) and A298 );
a1365a <=( A301 and A300 );
a1366a <=( a1365a and a1362a );
a1369a <=( A233 and (not A232) );
a1372a <=( A235 and A234 );
a1373a <=( a1372a and a1369a );
a1376a <=( (not A299) and A298 );
a1379a <=( (not A302) and A300 );
a1380a <=( a1379a and a1376a );
a1383a <=( A233 and (not A232) );
a1386a <=( A235 and A234 );
a1387a <=( a1386a and a1383a );
a1390a <=( A299 and (not A298) );
a1393a <=( A301 and A300 );
a1394a <=( a1393a and a1390a );
a1397a <=( A233 and (not A232) );
a1400a <=( A235 and A234 );
a1401a <=( a1400a and a1397a );
a1404a <=( A299 and (not A298) );
a1407a <=( (not A302) and A300 );
a1408a <=( a1407a and a1404a );
a1411a <=( A233 and (not A232) );
a1414a <=( A235 and A234 );
a1415a <=( a1414a and a1411a );
a1418a <=( A266 and (not A265) );
a1421a <=( A268 and A267 );
a1422a <=( a1421a and a1418a );
a1425a <=( A233 and (not A232) );
a1428a <=( A235 and A234 );
a1429a <=( a1428a and a1425a );
a1432a <=( A266 and (not A265) );
a1435a <=( (not A269) and A267 );
a1436a <=( a1435a and a1432a );
a1439a <=( A233 and (not A232) );
a1442a <=( A235 and A234 );
a1443a <=( a1442a and a1439a );
a1446a <=( (not A266) and A265 );
a1449a <=( A268 and A267 );
a1450a <=( a1449a and a1446a );
a1453a <=( A233 and (not A232) );
a1456a <=( A235 and A234 );
a1457a <=( a1456a and a1453a );
a1460a <=( (not A266) and A265 );
a1463a <=( (not A269) and A267 );
a1464a <=( a1463a and a1460a );
a1467a <=( A233 and (not A232) );
a1470a <=( (not A236) and A234 );
a1471a <=( a1470a and a1467a );
a1474a <=( (not A299) and A298 );
a1477a <=( A301 and A300 );
a1478a <=( a1477a and a1474a );
a1481a <=( A233 and (not A232) );
a1484a <=( (not A236) and A234 );
a1485a <=( a1484a and a1481a );
a1488a <=( (not A299) and A298 );
a1491a <=( (not A302) and A300 );
a1492a <=( a1491a and a1488a );
a1495a <=( A233 and (not A232) );
a1498a <=( (not A236) and A234 );
a1499a <=( a1498a and a1495a );
a1502a <=( A299 and (not A298) );
a1505a <=( A301 and A300 );
a1506a <=( a1505a and a1502a );
a1509a <=( A233 and (not A232) );
a1512a <=( (not A236) and A234 );
a1513a <=( a1512a and a1509a );
a1516a <=( A299 and (not A298) );
a1519a <=( (not A302) and A300 );
a1520a <=( a1519a and a1516a );
a1523a <=( A233 and (not A232) );
a1526a <=( (not A236) and A234 );
a1527a <=( a1526a and a1523a );
a1530a <=( A266 and (not A265) );
a1533a <=( A268 and A267 );
a1534a <=( a1533a and a1530a );
a1537a <=( A233 and (not A232) );
a1540a <=( (not A236) and A234 );
a1541a <=( a1540a and a1537a );
a1544a <=( A266 and (not A265) );
a1547a <=( (not A269) and A267 );
a1548a <=( a1547a and a1544a );
a1551a <=( A233 and (not A232) );
a1554a <=( (not A236) and A234 );
a1555a <=( a1554a and a1551a );
a1558a <=( (not A266) and A265 );
a1561a <=( A268 and A267 );
a1562a <=( a1561a and a1558a );
a1565a <=( A233 and (not A232) );
a1568a <=( (not A236) and A234 );
a1569a <=( a1568a and a1565a );
a1572a <=( (not A266) and A265 );
a1575a <=( (not A269) and A267 );
a1576a <=( a1575a and a1572a );
a1579a <=( (not A233) and A232 );
a1582a <=( A235 and A234 );
a1583a <=( a1582a and a1579a );
a1586a <=( (not A299) and A298 );
a1589a <=( A301 and A300 );
a1590a <=( a1589a and a1586a );
a1593a <=( (not A233) and A232 );
a1596a <=( A235 and A234 );
a1597a <=( a1596a and a1593a );
a1600a <=( (not A299) and A298 );
a1603a <=( (not A302) and A300 );
a1604a <=( a1603a and a1600a );
a1607a <=( (not A233) and A232 );
a1610a <=( A235 and A234 );
a1611a <=( a1610a and a1607a );
a1614a <=( A299 and (not A298) );
a1617a <=( A301 and A300 );
a1618a <=( a1617a and a1614a );
a1621a <=( (not A233) and A232 );
a1624a <=( A235 and A234 );
a1625a <=( a1624a and a1621a );
a1628a <=( A299 and (not A298) );
a1631a <=( (not A302) and A300 );
a1632a <=( a1631a and a1628a );
a1635a <=( (not A233) and A232 );
a1638a <=( A235 and A234 );
a1639a <=( a1638a and a1635a );
a1642a <=( A266 and (not A265) );
a1645a <=( A268 and A267 );
a1646a <=( a1645a and a1642a );
a1649a <=( (not A233) and A232 );
a1652a <=( A235 and A234 );
a1653a <=( a1652a and a1649a );
a1656a <=( A266 and (not A265) );
a1659a <=( (not A269) and A267 );
a1660a <=( a1659a and a1656a );
a1663a <=( (not A233) and A232 );
a1666a <=( A235 and A234 );
a1667a <=( a1666a and a1663a );
a1670a <=( (not A266) and A265 );
a1673a <=( A268 and A267 );
a1674a <=( a1673a and a1670a );
a1677a <=( (not A233) and A232 );
a1680a <=( A235 and A234 );
a1681a <=( a1680a and a1677a );
a1684a <=( (not A266) and A265 );
a1687a <=( (not A269) and A267 );
a1688a <=( a1687a and a1684a );
a1691a <=( (not A233) and A232 );
a1694a <=( (not A236) and A234 );
a1695a <=( a1694a and a1691a );
a1698a <=( (not A299) and A298 );
a1701a <=( A301 and A300 );
a1702a <=( a1701a and a1698a );
a1705a <=( (not A233) and A232 );
a1708a <=( (not A236) and A234 );
a1709a <=( a1708a and a1705a );
a1712a <=( (not A299) and A298 );
a1715a <=( (not A302) and A300 );
a1716a <=( a1715a and a1712a );
a1719a <=( (not A233) and A232 );
a1722a <=( (not A236) and A234 );
a1723a <=( a1722a and a1719a );
a1726a <=( A299 and (not A298) );
a1729a <=( A301 and A300 );
a1730a <=( a1729a and a1726a );
a1733a <=( (not A233) and A232 );
a1736a <=( (not A236) and A234 );
a1737a <=( a1736a and a1733a );
a1740a <=( A299 and (not A298) );
a1743a <=( (not A302) and A300 );
a1744a <=( a1743a and a1740a );
a1747a <=( (not A233) and A232 );
a1750a <=( (not A236) and A234 );
a1751a <=( a1750a and a1747a );
a1754a <=( A266 and (not A265) );
a1757a <=( A268 and A267 );
a1758a <=( a1757a and a1754a );
a1761a <=( (not A233) and A232 );
a1764a <=( (not A236) and A234 );
a1765a <=( a1764a and a1761a );
a1768a <=( A266 and (not A265) );
a1771a <=( (not A269) and A267 );
a1772a <=( a1771a and a1768a );
a1775a <=( (not A233) and A232 );
a1778a <=( (not A236) and A234 );
a1779a <=( a1778a and a1775a );
a1782a <=( (not A266) and A265 );
a1785a <=( A268 and A267 );
a1786a <=( a1785a and a1782a );
a1789a <=( (not A233) and A232 );
a1792a <=( (not A236) and A234 );
a1793a <=( a1792a and a1789a );
a1796a <=( (not A266) and A265 );
a1799a <=( (not A269) and A267 );
a1800a <=( a1799a and a1796a );
a1803a <=( A233 and (not A232) );
a1806a <=( A235 and A234 );
a1807a <=( a1806a and a1803a );
a1810a <=( (not A299) and A298 );
a1814a <=( A302 and (not A301) );
a1815a <=( (not A300) and a1814a );
a1816a <=( a1815a and a1810a );
a1819a <=( A233 and (not A232) );
a1822a <=( A235 and A234 );
a1823a <=( a1822a and a1819a );
a1826a <=( A299 and (not A298) );
a1830a <=( A302 and (not A301) );
a1831a <=( (not A300) and a1830a );
a1832a <=( a1831a and a1826a );
a1835a <=( A233 and (not A232) );
a1838a <=( A235 and A234 );
a1839a <=( a1838a and a1835a );
a1842a <=( A266 and (not A265) );
a1846a <=( A269 and (not A268) );
a1847a <=( (not A267) and a1846a );
a1848a <=( a1847a and a1842a );
a1851a <=( A233 and (not A232) );
a1854a <=( A235 and A234 );
a1855a <=( a1854a and a1851a );
a1858a <=( (not A266) and A265 );
a1862a <=( A269 and (not A268) );
a1863a <=( (not A267) and a1862a );
a1864a <=( a1863a and a1858a );
a1867a <=( A233 and (not A232) );
a1870a <=( (not A236) and A234 );
a1871a <=( a1870a and a1867a );
a1874a <=( (not A299) and A298 );
a1878a <=( A302 and (not A301) );
a1879a <=( (not A300) and a1878a );
a1880a <=( a1879a and a1874a );
a1883a <=( A233 and (not A232) );
a1886a <=( (not A236) and A234 );
a1887a <=( a1886a and a1883a );
a1890a <=( A299 and (not A298) );
a1894a <=( A302 and (not A301) );
a1895a <=( (not A300) and a1894a );
a1896a <=( a1895a and a1890a );
a1899a <=( A233 and (not A232) );
a1902a <=( (not A236) and A234 );
a1903a <=( a1902a and a1899a );
a1906a <=( A266 and (not A265) );
a1910a <=( A269 and (not A268) );
a1911a <=( (not A267) and a1910a );
a1912a <=( a1911a and a1906a );
a1915a <=( A233 and (not A232) );
a1918a <=( (not A236) and A234 );
a1919a <=( a1918a and a1915a );
a1922a <=( (not A266) and A265 );
a1926a <=( A269 and (not A268) );
a1927a <=( (not A267) and a1926a );
a1928a <=( a1927a and a1922a );
a1931a <=( A233 and (not A232) );
a1934a <=( (not A235) and (not A234) );
a1935a <=( a1934a and a1931a );
a1938a <=( A298 and A236 );
a1942a <=( A301 and A300 );
a1943a <=( (not A299) and a1942a );
a1944a <=( a1943a and a1938a );
a1947a <=( A233 and (not A232) );
a1950a <=( (not A235) and (not A234) );
a1951a <=( a1950a and a1947a );
a1954a <=( A298 and A236 );
a1958a <=( (not A302) and A300 );
a1959a <=( (not A299) and a1958a );
a1960a <=( a1959a and a1954a );
a1963a <=( A233 and (not A232) );
a1966a <=( (not A235) and (not A234) );
a1967a <=( a1966a and a1963a );
a1970a <=( (not A298) and A236 );
a1974a <=( A301 and A300 );
a1975a <=( A299 and a1974a );
a1976a <=( a1975a and a1970a );
a1979a <=( A233 and (not A232) );
a1982a <=( (not A235) and (not A234) );
a1983a <=( a1982a and a1979a );
a1986a <=( (not A298) and A236 );
a1990a <=( (not A302) and A300 );
a1991a <=( A299 and a1990a );
a1992a <=( a1991a and a1986a );
a1995a <=( A233 and (not A232) );
a1998a <=( (not A235) and (not A234) );
a1999a <=( a1998a and a1995a );
a2002a <=( (not A265) and A236 );
a2006a <=( A268 and A267 );
a2007a <=( A266 and a2006a );
a2008a <=( a2007a and a2002a );
a2011a <=( A233 and (not A232) );
a2014a <=( (not A235) and (not A234) );
a2015a <=( a2014a and a2011a );
a2018a <=( (not A265) and A236 );
a2022a <=( (not A269) and A267 );
a2023a <=( A266 and a2022a );
a2024a <=( a2023a and a2018a );
a2027a <=( A233 and (not A232) );
a2030a <=( (not A235) and (not A234) );
a2031a <=( a2030a and a2027a );
a2034a <=( A265 and A236 );
a2038a <=( A268 and A267 );
a2039a <=( (not A266) and a2038a );
a2040a <=( a2039a and a2034a );
a2043a <=( A233 and (not A232) );
a2046a <=( (not A235) and (not A234) );
a2047a <=( a2046a and a2043a );
a2050a <=( A265 and A236 );
a2054a <=( (not A269) and A267 );
a2055a <=( (not A266) and a2054a );
a2056a <=( a2055a and a2050a );
a2059a <=( (not A233) and A232 );
a2062a <=( A235 and A234 );
a2063a <=( a2062a and a2059a );
a2066a <=( (not A299) and A298 );
a2070a <=( A302 and (not A301) );
a2071a <=( (not A300) and a2070a );
a2072a <=( a2071a and a2066a );
a2075a <=( (not A233) and A232 );
a2078a <=( A235 and A234 );
a2079a <=( a2078a and a2075a );
a2082a <=( A299 and (not A298) );
a2086a <=( A302 and (not A301) );
a2087a <=( (not A300) and a2086a );
a2088a <=( a2087a and a2082a );
a2091a <=( (not A233) and A232 );
a2094a <=( A235 and A234 );
a2095a <=( a2094a and a2091a );
a2098a <=( A266 and (not A265) );
a2102a <=( A269 and (not A268) );
a2103a <=( (not A267) and a2102a );
a2104a <=( a2103a and a2098a );
a2107a <=( (not A233) and A232 );
a2110a <=( A235 and A234 );
a2111a <=( a2110a and a2107a );
a2114a <=( (not A266) and A265 );
a2118a <=( A269 and (not A268) );
a2119a <=( (not A267) and a2118a );
a2120a <=( a2119a and a2114a );
a2123a <=( (not A233) and A232 );
a2126a <=( (not A236) and A234 );
a2127a <=( a2126a and a2123a );
a2130a <=( (not A299) and A298 );
a2134a <=( A302 and (not A301) );
a2135a <=( (not A300) and a2134a );
a2136a <=( a2135a and a2130a );
a2139a <=( (not A233) and A232 );
a2142a <=( (not A236) and A234 );
a2143a <=( a2142a and a2139a );
a2146a <=( A299 and (not A298) );
a2150a <=( A302 and (not A301) );
a2151a <=( (not A300) and a2150a );
a2152a <=( a2151a and a2146a );
a2155a <=( (not A233) and A232 );
a2158a <=( (not A236) and A234 );
a2159a <=( a2158a and a2155a );
a2162a <=( A266 and (not A265) );
a2166a <=( A269 and (not A268) );
a2167a <=( (not A267) and a2166a );
a2168a <=( a2167a and a2162a );
a2171a <=( (not A233) and A232 );
a2174a <=( (not A236) and A234 );
a2175a <=( a2174a and a2171a );
a2178a <=( (not A266) and A265 );
a2182a <=( A269 and (not A268) );
a2183a <=( (not A267) and a2182a );
a2184a <=( a2183a and a2178a );
a2187a <=( (not A233) and A232 );
a2190a <=( (not A235) and (not A234) );
a2191a <=( a2190a and a2187a );
a2194a <=( A298 and A236 );
a2198a <=( A301 and A300 );
a2199a <=( (not A299) and a2198a );
a2200a <=( a2199a and a2194a );
a2203a <=( (not A233) and A232 );
a2206a <=( (not A235) and (not A234) );
a2207a <=( a2206a and a2203a );
a2210a <=( A298 and A236 );
a2214a <=( (not A302) and A300 );
a2215a <=( (not A299) and a2214a );
a2216a <=( a2215a and a2210a );
a2219a <=( (not A233) and A232 );
a2222a <=( (not A235) and (not A234) );
a2223a <=( a2222a and a2219a );
a2226a <=( (not A298) and A236 );
a2230a <=( A301 and A300 );
a2231a <=( A299 and a2230a );
a2232a <=( a2231a and a2226a );
a2235a <=( (not A233) and A232 );
a2238a <=( (not A235) and (not A234) );
a2239a <=( a2238a and a2235a );
a2242a <=( (not A298) and A236 );
a2246a <=( (not A302) and A300 );
a2247a <=( A299 and a2246a );
a2248a <=( a2247a and a2242a );
a2251a <=( (not A233) and A232 );
a2254a <=( (not A235) and (not A234) );
a2255a <=( a2254a and a2251a );
a2258a <=( (not A265) and A236 );
a2262a <=( A268 and A267 );
a2263a <=( A266 and a2262a );
a2264a <=( a2263a and a2258a );
a2267a <=( (not A233) and A232 );
a2270a <=( (not A235) and (not A234) );
a2271a <=( a2270a and a2267a );
a2274a <=( (not A265) and A236 );
a2278a <=( (not A269) and A267 );
a2279a <=( A266 and a2278a );
a2280a <=( a2279a and a2274a );
a2283a <=( (not A233) and A232 );
a2286a <=( (not A235) and (not A234) );
a2287a <=( a2286a and a2283a );
a2290a <=( A265 and A236 );
a2294a <=( A268 and A267 );
a2295a <=( (not A266) and a2294a );
a2296a <=( a2295a and a2290a );
a2299a <=( (not A233) and A232 );
a2302a <=( (not A235) and (not A234) );
a2303a <=( a2302a and a2299a );
a2306a <=( A265 and A236 );
a2310a <=( (not A269) and A267 );
a2311a <=( (not A266) and a2310a );
a2312a <=( a2311a and a2306a );
a2315a <=( A233 and (not A232) );
a2319a <=( A236 and (not A235) );
a2320a <=( (not A234) and a2319a );
a2321a <=( a2320a and a2315a );
a2324a <=( (not A299) and A298 );
a2328a <=( A302 and (not A301) );
a2329a <=( (not A300) and a2328a );
a2330a <=( a2329a and a2324a );
a2333a <=( A233 and (not A232) );
a2337a <=( A236 and (not A235) );
a2338a <=( (not A234) and a2337a );
a2339a <=( a2338a and a2333a );
a2342a <=( A299 and (not A298) );
a2346a <=( A302 and (not A301) );
a2347a <=( (not A300) and a2346a );
a2348a <=( a2347a and a2342a );
a2351a <=( A233 and (not A232) );
a2355a <=( A236 and (not A235) );
a2356a <=( (not A234) and a2355a );
a2357a <=( a2356a and a2351a );
a2360a <=( A266 and (not A265) );
a2364a <=( A269 and (not A268) );
a2365a <=( (not A267) and a2364a );
a2366a <=( a2365a and a2360a );
a2369a <=( A233 and (not A232) );
a2373a <=( A236 and (not A235) );
a2374a <=( (not A234) and a2373a );
a2375a <=( a2374a and a2369a );
a2378a <=( (not A266) and A265 );
a2382a <=( A269 and (not A268) );
a2383a <=( (not A267) and a2382a );
a2384a <=( a2383a and a2378a );
a2387a <=( (not A233) and A232 );
a2391a <=( A236 and (not A235) );
a2392a <=( (not A234) and a2391a );
a2393a <=( a2392a and a2387a );
a2396a <=( (not A299) and A298 );
a2400a <=( A302 and (not A301) );
a2401a <=( (not A300) and a2400a );
a2402a <=( a2401a and a2396a );
a2405a <=( (not A233) and A232 );
a2409a <=( A236 and (not A235) );
a2410a <=( (not A234) and a2409a );
a2411a <=( a2410a and a2405a );
a2414a <=( A299 and (not A298) );
a2418a <=( A302 and (not A301) );
a2419a <=( (not A300) and a2418a );
a2420a <=( a2419a and a2414a );
a2423a <=( (not A233) and A232 );
a2427a <=( A236 and (not A235) );
a2428a <=( (not A234) and a2427a );
a2429a <=( a2428a and a2423a );
a2432a <=( A266 and (not A265) );
a2436a <=( A269 and (not A268) );
a2437a <=( (not A267) and a2436a );
a2438a <=( a2437a and a2432a );
a2441a <=( (not A233) and A232 );
a2445a <=( A236 and (not A235) );
a2446a <=( (not A234) and a2445a );
a2447a <=( a2446a and a2441a );
a2450a <=( (not A266) and A265 );
a2454a <=( A269 and (not A268) );
a2455a <=( (not A267) and a2454a );
a2456a <=( a2455a and a2450a );
a2459a <=( A168 and A170 );
a2463a <=( (not A267) and (not A166) );
a2464a <=( A167 and a2463a );
a2465a <=( a2464a and a2459a );
a2468a <=( A298 and A268 );
a2472a <=( A301 and A300 );
a2473a <=( (not A299) and a2472a );
a2474a <=( a2473a and a2468a );
a2477a <=( A168 and A170 );
a2481a <=( (not A267) and (not A166) );
a2482a <=( A167 and a2481a );
a2483a <=( a2482a and a2477a );
a2486a <=( A298 and A268 );
a2490a <=( (not A302) and A300 );
a2491a <=( (not A299) and a2490a );
a2492a <=( a2491a and a2486a );
a2495a <=( A168 and A170 );
a2499a <=( (not A267) and (not A166) );
a2500a <=( A167 and a2499a );
a2501a <=( a2500a and a2495a );
a2504a <=( (not A298) and A268 );
a2508a <=( A301 and A300 );
a2509a <=( A299 and a2508a );
a2510a <=( a2509a and a2504a );
a2513a <=( A168 and A170 );
a2517a <=( (not A267) and (not A166) );
a2518a <=( A167 and a2517a );
a2519a <=( a2518a and a2513a );
a2522a <=( (not A298) and A268 );
a2526a <=( (not A302) and A300 );
a2527a <=( A299 and a2526a );
a2528a <=( a2527a and a2522a );
a2531a <=( A168 and A170 );
a2535a <=( (not A267) and (not A166) );
a2536a <=( A167 and a2535a );
a2537a <=( a2536a and a2531a );
a2540a <=( A298 and (not A269) );
a2544a <=( A301 and A300 );
a2545a <=( (not A299) and a2544a );
a2546a <=( a2545a and a2540a );
a2549a <=( A168 and A170 );
a2553a <=( (not A267) and (not A166) );
a2554a <=( A167 and a2553a );
a2555a <=( a2554a and a2549a );
a2558a <=( A298 and (not A269) );
a2562a <=( (not A302) and A300 );
a2563a <=( (not A299) and a2562a );
a2564a <=( a2563a and a2558a );
a2567a <=( A168 and A170 );
a2571a <=( (not A267) and (not A166) );
a2572a <=( A167 and a2571a );
a2573a <=( a2572a and a2567a );
a2576a <=( (not A298) and (not A269) );
a2580a <=( A301 and A300 );
a2581a <=( A299 and a2580a );
a2582a <=( a2581a and a2576a );
a2585a <=( A168 and A170 );
a2589a <=( (not A267) and (not A166) );
a2590a <=( A167 and a2589a );
a2591a <=( a2590a and a2585a );
a2594a <=( (not A298) and (not A269) );
a2598a <=( (not A302) and A300 );
a2599a <=( A299 and a2598a );
a2600a <=( a2599a and a2594a );
a2603a <=( A168 and A170 );
a2607a <=( A265 and (not A166) );
a2608a <=( A167 and a2607a );
a2609a <=( a2608a and a2603a );
a2612a <=( A298 and A266 );
a2616a <=( A301 and A300 );
a2617a <=( (not A299) and a2616a );
a2618a <=( a2617a and a2612a );
a2621a <=( A168 and A170 );
a2625a <=( A265 and (not A166) );
a2626a <=( A167 and a2625a );
a2627a <=( a2626a and a2621a );
a2630a <=( A298 and A266 );
a2634a <=( (not A302) and A300 );
a2635a <=( (not A299) and a2634a );
a2636a <=( a2635a and a2630a );
a2639a <=( A168 and A170 );
a2643a <=( A265 and (not A166) );
a2644a <=( A167 and a2643a );
a2645a <=( a2644a and a2639a );
a2648a <=( (not A298) and A266 );
a2652a <=( A301 and A300 );
a2653a <=( A299 and a2652a );
a2654a <=( a2653a and a2648a );
a2657a <=( A168 and A170 );
a2661a <=( A265 and (not A166) );
a2662a <=( A167 and a2661a );
a2663a <=( a2662a and a2657a );
a2666a <=( (not A298) and A266 );
a2670a <=( (not A302) and A300 );
a2671a <=( A299 and a2670a );
a2672a <=( a2671a and a2666a );
a2675a <=( A168 and A170 );
a2679a <=( (not A265) and (not A166) );
a2680a <=( A167 and a2679a );
a2681a <=( a2680a and a2675a );
a2684a <=( A267 and A266 );
a2688a <=( A301 and (not A300) );
a2689a <=( A268 and a2688a );
a2690a <=( a2689a and a2684a );
a2693a <=( A168 and A170 );
a2697a <=( (not A265) and (not A166) );
a2698a <=( A167 and a2697a );
a2699a <=( a2698a and a2693a );
a2702a <=( A267 and A266 );
a2706a <=( (not A302) and (not A300) );
a2707a <=( A268 and a2706a );
a2708a <=( a2707a and a2702a );
a2711a <=( A168 and A170 );
a2715a <=( (not A265) and (not A166) );
a2716a <=( A167 and a2715a );
a2717a <=( a2716a and a2711a );
a2720a <=( A267 and A266 );
a2724a <=( A299 and A298 );
a2725a <=( A268 and a2724a );
a2726a <=( a2725a and a2720a );
a2729a <=( A168 and A170 );
a2733a <=( (not A265) and (not A166) );
a2734a <=( A167 and a2733a );
a2735a <=( a2734a and a2729a );
a2738a <=( A267 and A266 );
a2742a <=( (not A299) and (not A298) );
a2743a <=( A268 and a2742a );
a2744a <=( a2743a and a2738a );
a2747a <=( A168 and A170 );
a2751a <=( (not A265) and (not A166) );
a2752a <=( A167 and a2751a );
a2753a <=( a2752a and a2747a );
a2756a <=( A267 and A266 );
a2760a <=( A301 and (not A300) );
a2761a <=( (not A269) and a2760a );
a2762a <=( a2761a and a2756a );
a2765a <=( A168 and A170 );
a2769a <=( (not A265) and (not A166) );
a2770a <=( A167 and a2769a );
a2771a <=( a2770a and a2765a );
a2774a <=( A267 and A266 );
a2778a <=( (not A302) and (not A300) );
a2779a <=( (not A269) and a2778a );
a2780a <=( a2779a and a2774a );
a2783a <=( A168 and A170 );
a2787a <=( (not A265) and (not A166) );
a2788a <=( A167 and a2787a );
a2789a <=( a2788a and a2783a );
a2792a <=( A267 and A266 );
a2796a <=( A299 and A298 );
a2797a <=( (not A269) and a2796a );
a2798a <=( a2797a and a2792a );
a2801a <=( A168 and A170 );
a2805a <=( (not A265) and (not A166) );
a2806a <=( A167 and a2805a );
a2807a <=( a2806a and a2801a );
a2810a <=( A267 and A266 );
a2814a <=( (not A299) and (not A298) );
a2815a <=( (not A269) and a2814a );
a2816a <=( a2815a and a2810a );
a2819a <=( A168 and A170 );
a2823a <=( A265 and (not A166) );
a2824a <=( A167 and a2823a );
a2825a <=( a2824a and a2819a );
a2828a <=( A267 and (not A266) );
a2832a <=( A301 and (not A300) );
a2833a <=( A268 and a2832a );
a2834a <=( a2833a and a2828a );
a2837a <=( A168 and A170 );
a2841a <=( A265 and (not A166) );
a2842a <=( A167 and a2841a );
a2843a <=( a2842a and a2837a );
a2846a <=( A267 and (not A266) );
a2850a <=( (not A302) and (not A300) );
a2851a <=( A268 and a2850a );
a2852a <=( a2851a and a2846a );
a2855a <=( A168 and A170 );
a2859a <=( A265 and (not A166) );
a2860a <=( A167 and a2859a );
a2861a <=( a2860a and a2855a );
a2864a <=( A267 and (not A266) );
a2868a <=( A299 and A298 );
a2869a <=( A268 and a2868a );
a2870a <=( a2869a and a2864a );
a2873a <=( A168 and A170 );
a2877a <=( A265 and (not A166) );
a2878a <=( A167 and a2877a );
a2879a <=( a2878a and a2873a );
a2882a <=( A267 and (not A266) );
a2886a <=( (not A299) and (not A298) );
a2887a <=( A268 and a2886a );
a2888a <=( a2887a and a2882a );
a2891a <=( A168 and A170 );
a2895a <=( A265 and (not A166) );
a2896a <=( A167 and a2895a );
a2897a <=( a2896a and a2891a );
a2900a <=( A267 and (not A266) );
a2904a <=( A301 and (not A300) );
a2905a <=( (not A269) and a2904a );
a2906a <=( a2905a and a2900a );
a2909a <=( A168 and A170 );
a2913a <=( A265 and (not A166) );
a2914a <=( A167 and a2913a );
a2915a <=( a2914a and a2909a );
a2918a <=( A267 and (not A266) );
a2922a <=( (not A302) and (not A300) );
a2923a <=( (not A269) and a2922a );
a2924a <=( a2923a and a2918a );
a2927a <=( A168 and A170 );
a2931a <=( A265 and (not A166) );
a2932a <=( A167 and a2931a );
a2933a <=( a2932a and a2927a );
a2936a <=( A267 and (not A266) );
a2940a <=( A299 and A298 );
a2941a <=( (not A269) and a2940a );
a2942a <=( a2941a and a2936a );
a2945a <=( A168 and A170 );
a2949a <=( A265 and (not A166) );
a2950a <=( A167 and a2949a );
a2951a <=( a2950a and a2945a );
a2954a <=( A267 and (not A266) );
a2958a <=( (not A299) and (not A298) );
a2959a <=( (not A269) and a2958a );
a2960a <=( a2959a and a2954a );
a2963a <=( A168 and A170 );
a2967a <=( (not A265) and (not A166) );
a2968a <=( A167 and a2967a );
a2969a <=( a2968a and a2963a );
a2972a <=( A298 and (not A266) );
a2976a <=( A301 and A300 );
a2977a <=( (not A299) and a2976a );
a2978a <=( a2977a and a2972a );
a2981a <=( A168 and A170 );
a2985a <=( (not A265) and (not A166) );
a2986a <=( A167 and a2985a );
a2987a <=( a2986a and a2981a );
a2990a <=( A298 and (not A266) );
a2994a <=( (not A302) and A300 );
a2995a <=( (not A299) and a2994a );
a2996a <=( a2995a and a2990a );
a2999a <=( A168 and A170 );
a3003a <=( (not A265) and (not A166) );
a3004a <=( A167 and a3003a );
a3005a <=( a3004a and a2999a );
a3008a <=( (not A298) and (not A266) );
a3012a <=( A301 and A300 );
a3013a <=( A299 and a3012a );
a3014a <=( a3013a and a3008a );
a3017a <=( A168 and A170 );
a3021a <=( (not A265) and (not A166) );
a3022a <=( A167 and a3021a );
a3023a <=( a3022a and a3017a );
a3026a <=( (not A298) and (not A266) );
a3030a <=( (not A302) and A300 );
a3031a <=( A299 and a3030a );
a3032a <=( a3031a and a3026a );
a3035a <=( A168 and A170 );
a3039a <=( (not A267) and A166 );
a3040a <=( (not A167) and a3039a );
a3041a <=( a3040a and a3035a );
a3044a <=( A298 and A268 );
a3048a <=( A301 and A300 );
a3049a <=( (not A299) and a3048a );
a3050a <=( a3049a and a3044a );
a3053a <=( A168 and A170 );
a3057a <=( (not A267) and A166 );
a3058a <=( (not A167) and a3057a );
a3059a <=( a3058a and a3053a );
a3062a <=( A298 and A268 );
a3066a <=( (not A302) and A300 );
a3067a <=( (not A299) and a3066a );
a3068a <=( a3067a and a3062a );
a3071a <=( A168 and A170 );
a3075a <=( (not A267) and A166 );
a3076a <=( (not A167) and a3075a );
a3077a <=( a3076a and a3071a );
a3080a <=( (not A298) and A268 );
a3084a <=( A301 and A300 );
a3085a <=( A299 and a3084a );
a3086a <=( a3085a and a3080a );
a3089a <=( A168 and A170 );
a3093a <=( (not A267) and A166 );
a3094a <=( (not A167) and a3093a );
a3095a <=( a3094a and a3089a );
a3098a <=( (not A298) and A268 );
a3102a <=( (not A302) and A300 );
a3103a <=( A299 and a3102a );
a3104a <=( a3103a and a3098a );
a3107a <=( A168 and A170 );
a3111a <=( (not A267) and A166 );
a3112a <=( (not A167) and a3111a );
a3113a <=( a3112a and a3107a );
a3116a <=( A298 and (not A269) );
a3120a <=( A301 and A300 );
a3121a <=( (not A299) and a3120a );
a3122a <=( a3121a and a3116a );
a3125a <=( A168 and A170 );
a3129a <=( (not A267) and A166 );
a3130a <=( (not A167) and a3129a );
a3131a <=( a3130a and a3125a );
a3134a <=( A298 and (not A269) );
a3138a <=( (not A302) and A300 );
a3139a <=( (not A299) and a3138a );
a3140a <=( a3139a and a3134a );
a3143a <=( A168 and A170 );
a3147a <=( (not A267) and A166 );
a3148a <=( (not A167) and a3147a );
a3149a <=( a3148a and a3143a );
a3152a <=( (not A298) and (not A269) );
a3156a <=( A301 and A300 );
a3157a <=( A299 and a3156a );
a3158a <=( a3157a and a3152a );
a3161a <=( A168 and A170 );
a3165a <=( (not A267) and A166 );
a3166a <=( (not A167) and a3165a );
a3167a <=( a3166a and a3161a );
a3170a <=( (not A298) and (not A269) );
a3174a <=( (not A302) and A300 );
a3175a <=( A299 and a3174a );
a3176a <=( a3175a and a3170a );
a3179a <=( A168 and A170 );
a3183a <=( A265 and A166 );
a3184a <=( (not A167) and a3183a );
a3185a <=( a3184a and a3179a );
a3188a <=( A298 and A266 );
a3192a <=( A301 and A300 );
a3193a <=( (not A299) and a3192a );
a3194a <=( a3193a and a3188a );
a3197a <=( A168 and A170 );
a3201a <=( A265 and A166 );
a3202a <=( (not A167) and a3201a );
a3203a <=( a3202a and a3197a );
a3206a <=( A298 and A266 );
a3210a <=( (not A302) and A300 );
a3211a <=( (not A299) and a3210a );
a3212a <=( a3211a and a3206a );
a3215a <=( A168 and A170 );
a3219a <=( A265 and A166 );
a3220a <=( (not A167) and a3219a );
a3221a <=( a3220a and a3215a );
a3224a <=( (not A298) and A266 );
a3228a <=( A301 and A300 );
a3229a <=( A299 and a3228a );
a3230a <=( a3229a and a3224a );
a3233a <=( A168 and A170 );
a3237a <=( A265 and A166 );
a3238a <=( (not A167) and a3237a );
a3239a <=( a3238a and a3233a );
a3242a <=( (not A298) and A266 );
a3246a <=( (not A302) and A300 );
a3247a <=( A299 and a3246a );
a3248a <=( a3247a and a3242a );
a3251a <=( A168 and A170 );
a3255a <=( (not A265) and A166 );
a3256a <=( (not A167) and a3255a );
a3257a <=( a3256a and a3251a );
a3260a <=( A267 and A266 );
a3264a <=( A301 and (not A300) );
a3265a <=( A268 and a3264a );
a3266a <=( a3265a and a3260a );
a3269a <=( A168 and A170 );
a3273a <=( (not A265) and A166 );
a3274a <=( (not A167) and a3273a );
a3275a <=( a3274a and a3269a );
a3278a <=( A267 and A266 );
a3282a <=( (not A302) and (not A300) );
a3283a <=( A268 and a3282a );
a3284a <=( a3283a and a3278a );
a3287a <=( A168 and A170 );
a3291a <=( (not A265) and A166 );
a3292a <=( (not A167) and a3291a );
a3293a <=( a3292a and a3287a );
a3296a <=( A267 and A266 );
a3300a <=( A299 and A298 );
a3301a <=( A268 and a3300a );
a3302a <=( a3301a and a3296a );
a3305a <=( A168 and A170 );
a3309a <=( (not A265) and A166 );
a3310a <=( (not A167) and a3309a );
a3311a <=( a3310a and a3305a );
a3314a <=( A267 and A266 );
a3318a <=( (not A299) and (not A298) );
a3319a <=( A268 and a3318a );
a3320a <=( a3319a and a3314a );
a3323a <=( A168 and A170 );
a3327a <=( (not A265) and A166 );
a3328a <=( (not A167) and a3327a );
a3329a <=( a3328a and a3323a );
a3332a <=( A267 and A266 );
a3336a <=( A301 and (not A300) );
a3337a <=( (not A269) and a3336a );
a3338a <=( a3337a and a3332a );
a3341a <=( A168 and A170 );
a3345a <=( (not A265) and A166 );
a3346a <=( (not A167) and a3345a );
a3347a <=( a3346a and a3341a );
a3350a <=( A267 and A266 );
a3354a <=( (not A302) and (not A300) );
a3355a <=( (not A269) and a3354a );
a3356a <=( a3355a and a3350a );
a3359a <=( A168 and A170 );
a3363a <=( (not A265) and A166 );
a3364a <=( (not A167) and a3363a );
a3365a <=( a3364a and a3359a );
a3368a <=( A267 and A266 );
a3372a <=( A299 and A298 );
a3373a <=( (not A269) and a3372a );
a3374a <=( a3373a and a3368a );
a3377a <=( A168 and A170 );
a3381a <=( (not A265) and A166 );
a3382a <=( (not A167) and a3381a );
a3383a <=( a3382a and a3377a );
a3386a <=( A267 and A266 );
a3390a <=( (not A299) and (not A298) );
a3391a <=( (not A269) and a3390a );
a3392a <=( a3391a and a3386a );
a3395a <=( A168 and A170 );
a3399a <=( A265 and A166 );
a3400a <=( (not A167) and a3399a );
a3401a <=( a3400a and a3395a );
a3404a <=( A267 and (not A266) );
a3408a <=( A301 and (not A300) );
a3409a <=( A268 and a3408a );
a3410a <=( a3409a and a3404a );
a3413a <=( A168 and A170 );
a3417a <=( A265 and A166 );
a3418a <=( (not A167) and a3417a );
a3419a <=( a3418a and a3413a );
a3422a <=( A267 and (not A266) );
a3426a <=( (not A302) and (not A300) );
a3427a <=( A268 and a3426a );
a3428a <=( a3427a and a3422a );
a3431a <=( A168 and A170 );
a3435a <=( A265 and A166 );
a3436a <=( (not A167) and a3435a );
a3437a <=( a3436a and a3431a );
a3440a <=( A267 and (not A266) );
a3444a <=( A299 and A298 );
a3445a <=( A268 and a3444a );
a3446a <=( a3445a and a3440a );
a3449a <=( A168 and A170 );
a3453a <=( A265 and A166 );
a3454a <=( (not A167) and a3453a );
a3455a <=( a3454a and a3449a );
a3458a <=( A267 and (not A266) );
a3462a <=( (not A299) and (not A298) );
a3463a <=( A268 and a3462a );
a3464a <=( a3463a and a3458a );
a3467a <=( A168 and A170 );
a3471a <=( A265 and A166 );
a3472a <=( (not A167) and a3471a );
a3473a <=( a3472a and a3467a );
a3476a <=( A267 and (not A266) );
a3480a <=( A301 and (not A300) );
a3481a <=( (not A269) and a3480a );
a3482a <=( a3481a and a3476a );
a3485a <=( A168 and A170 );
a3489a <=( A265 and A166 );
a3490a <=( (not A167) and a3489a );
a3491a <=( a3490a and a3485a );
a3494a <=( A267 and (not A266) );
a3498a <=( (not A302) and (not A300) );
a3499a <=( (not A269) and a3498a );
a3500a <=( a3499a and a3494a );
a3503a <=( A168 and A170 );
a3507a <=( A265 and A166 );
a3508a <=( (not A167) and a3507a );
a3509a <=( a3508a and a3503a );
a3512a <=( A267 and (not A266) );
a3516a <=( A299 and A298 );
a3517a <=( (not A269) and a3516a );
a3518a <=( a3517a and a3512a );
a3521a <=( A168 and A170 );
a3525a <=( A265 and A166 );
a3526a <=( (not A167) and a3525a );
a3527a <=( a3526a and a3521a );
a3530a <=( A267 and (not A266) );
a3534a <=( (not A299) and (not A298) );
a3535a <=( (not A269) and a3534a );
a3536a <=( a3535a and a3530a );
a3539a <=( A168 and A170 );
a3543a <=( (not A265) and A166 );
a3544a <=( (not A167) and a3543a );
a3545a <=( a3544a and a3539a );
a3548a <=( A298 and (not A266) );
a3552a <=( A301 and A300 );
a3553a <=( (not A299) and a3552a );
a3554a <=( a3553a and a3548a );
a3557a <=( A168 and A170 );
a3561a <=( (not A265) and A166 );
a3562a <=( (not A167) and a3561a );
a3563a <=( a3562a and a3557a );
a3566a <=( A298 and (not A266) );
a3570a <=( (not A302) and A300 );
a3571a <=( (not A299) and a3570a );
a3572a <=( a3571a and a3566a );
a3575a <=( A168 and A170 );
a3579a <=( (not A265) and A166 );
a3580a <=( (not A167) and a3579a );
a3581a <=( a3580a and a3575a );
a3584a <=( (not A298) and (not A266) );
a3588a <=( A301 and A300 );
a3589a <=( A299 and a3588a );
a3590a <=( a3589a and a3584a );
a3593a <=( A168 and A170 );
a3597a <=( (not A265) and A166 );
a3598a <=( (not A167) and a3597a );
a3599a <=( a3598a and a3593a );
a3602a <=( (not A298) and (not A266) );
a3606a <=( (not A302) and A300 );
a3607a <=( A299 and a3606a );
a3608a <=( a3607a and a3602a );
a3611a <=( A168 and A169 );
a3615a <=( (not A267) and (not A166) );
a3616a <=( A167 and a3615a );
a3617a <=( a3616a and a3611a );
a3620a <=( A298 and A268 );
a3624a <=( A301 and A300 );
a3625a <=( (not A299) and a3624a );
a3626a <=( a3625a and a3620a );
a3629a <=( A168 and A169 );
a3633a <=( (not A267) and (not A166) );
a3634a <=( A167 and a3633a );
a3635a <=( a3634a and a3629a );
a3638a <=( A298 and A268 );
a3642a <=( (not A302) and A300 );
a3643a <=( (not A299) and a3642a );
a3644a <=( a3643a and a3638a );
a3647a <=( A168 and A169 );
a3651a <=( (not A267) and (not A166) );
a3652a <=( A167 and a3651a );
a3653a <=( a3652a and a3647a );
a3656a <=( (not A298) and A268 );
a3660a <=( A301 and A300 );
a3661a <=( A299 and a3660a );
a3662a <=( a3661a and a3656a );
a3665a <=( A168 and A169 );
a3669a <=( (not A267) and (not A166) );
a3670a <=( A167 and a3669a );
a3671a <=( a3670a and a3665a );
a3674a <=( (not A298) and A268 );
a3678a <=( (not A302) and A300 );
a3679a <=( A299 and a3678a );
a3680a <=( a3679a and a3674a );
a3683a <=( A168 and A169 );
a3687a <=( (not A267) and (not A166) );
a3688a <=( A167 and a3687a );
a3689a <=( a3688a and a3683a );
a3692a <=( A298 and (not A269) );
a3696a <=( A301 and A300 );
a3697a <=( (not A299) and a3696a );
a3698a <=( a3697a and a3692a );
a3701a <=( A168 and A169 );
a3705a <=( (not A267) and (not A166) );
a3706a <=( A167 and a3705a );
a3707a <=( a3706a and a3701a );
a3710a <=( A298 and (not A269) );
a3714a <=( (not A302) and A300 );
a3715a <=( (not A299) and a3714a );
a3716a <=( a3715a and a3710a );
a3719a <=( A168 and A169 );
a3723a <=( (not A267) and (not A166) );
a3724a <=( A167 and a3723a );
a3725a <=( a3724a and a3719a );
a3728a <=( (not A298) and (not A269) );
a3732a <=( A301 and A300 );
a3733a <=( A299 and a3732a );
a3734a <=( a3733a and a3728a );
a3737a <=( A168 and A169 );
a3741a <=( (not A267) and (not A166) );
a3742a <=( A167 and a3741a );
a3743a <=( a3742a and a3737a );
a3746a <=( (not A298) and (not A269) );
a3750a <=( (not A302) and A300 );
a3751a <=( A299 and a3750a );
a3752a <=( a3751a and a3746a );
a3755a <=( A168 and A169 );
a3759a <=( A265 and (not A166) );
a3760a <=( A167 and a3759a );
a3761a <=( a3760a and a3755a );
a3764a <=( A298 and A266 );
a3768a <=( A301 and A300 );
a3769a <=( (not A299) and a3768a );
a3770a <=( a3769a and a3764a );
a3773a <=( A168 and A169 );
a3777a <=( A265 and (not A166) );
a3778a <=( A167 and a3777a );
a3779a <=( a3778a and a3773a );
a3782a <=( A298 and A266 );
a3786a <=( (not A302) and A300 );
a3787a <=( (not A299) and a3786a );
a3788a <=( a3787a and a3782a );
a3791a <=( A168 and A169 );
a3795a <=( A265 and (not A166) );
a3796a <=( A167 and a3795a );
a3797a <=( a3796a and a3791a );
a3800a <=( (not A298) and A266 );
a3804a <=( A301 and A300 );
a3805a <=( A299 and a3804a );
a3806a <=( a3805a and a3800a );
a3809a <=( A168 and A169 );
a3813a <=( A265 and (not A166) );
a3814a <=( A167 and a3813a );
a3815a <=( a3814a and a3809a );
a3818a <=( (not A298) and A266 );
a3822a <=( (not A302) and A300 );
a3823a <=( A299 and a3822a );
a3824a <=( a3823a and a3818a );
a3827a <=( A168 and A169 );
a3831a <=( (not A265) and (not A166) );
a3832a <=( A167 and a3831a );
a3833a <=( a3832a and a3827a );
a3836a <=( A267 and A266 );
a3840a <=( A301 and (not A300) );
a3841a <=( A268 and a3840a );
a3842a <=( a3841a and a3836a );
a3845a <=( A168 and A169 );
a3849a <=( (not A265) and (not A166) );
a3850a <=( A167 and a3849a );
a3851a <=( a3850a and a3845a );
a3854a <=( A267 and A266 );
a3858a <=( (not A302) and (not A300) );
a3859a <=( A268 and a3858a );
a3860a <=( a3859a and a3854a );
a3863a <=( A168 and A169 );
a3867a <=( (not A265) and (not A166) );
a3868a <=( A167 and a3867a );
a3869a <=( a3868a and a3863a );
a3872a <=( A267 and A266 );
a3876a <=( A299 and A298 );
a3877a <=( A268 and a3876a );
a3878a <=( a3877a and a3872a );
a3881a <=( A168 and A169 );
a3885a <=( (not A265) and (not A166) );
a3886a <=( A167 and a3885a );
a3887a <=( a3886a and a3881a );
a3890a <=( A267 and A266 );
a3894a <=( (not A299) and (not A298) );
a3895a <=( A268 and a3894a );
a3896a <=( a3895a and a3890a );
a3899a <=( A168 and A169 );
a3903a <=( (not A265) and (not A166) );
a3904a <=( A167 and a3903a );
a3905a <=( a3904a and a3899a );
a3908a <=( A267 and A266 );
a3912a <=( A301 and (not A300) );
a3913a <=( (not A269) and a3912a );
a3914a <=( a3913a and a3908a );
a3917a <=( A168 and A169 );
a3921a <=( (not A265) and (not A166) );
a3922a <=( A167 and a3921a );
a3923a <=( a3922a and a3917a );
a3926a <=( A267 and A266 );
a3930a <=( (not A302) and (not A300) );
a3931a <=( (not A269) and a3930a );
a3932a <=( a3931a and a3926a );
a3935a <=( A168 and A169 );
a3939a <=( (not A265) and (not A166) );
a3940a <=( A167 and a3939a );
a3941a <=( a3940a and a3935a );
a3944a <=( A267 and A266 );
a3948a <=( A299 and A298 );
a3949a <=( (not A269) and a3948a );
a3950a <=( a3949a and a3944a );
a3953a <=( A168 and A169 );
a3957a <=( (not A265) and (not A166) );
a3958a <=( A167 and a3957a );
a3959a <=( a3958a and a3953a );
a3962a <=( A267 and A266 );
a3966a <=( (not A299) and (not A298) );
a3967a <=( (not A269) and a3966a );
a3968a <=( a3967a and a3962a );
a3971a <=( A168 and A169 );
a3975a <=( A265 and (not A166) );
a3976a <=( A167 and a3975a );
a3977a <=( a3976a and a3971a );
a3980a <=( A267 and (not A266) );
a3984a <=( A301 and (not A300) );
a3985a <=( A268 and a3984a );
a3986a <=( a3985a and a3980a );
a3989a <=( A168 and A169 );
a3993a <=( A265 and (not A166) );
a3994a <=( A167 and a3993a );
a3995a <=( a3994a and a3989a );
a3998a <=( A267 and (not A266) );
a4002a <=( (not A302) and (not A300) );
a4003a <=( A268 and a4002a );
a4004a <=( a4003a and a3998a );
a4007a <=( A168 and A169 );
a4011a <=( A265 and (not A166) );
a4012a <=( A167 and a4011a );
a4013a <=( a4012a and a4007a );
a4016a <=( A267 and (not A266) );
a4020a <=( A299 and A298 );
a4021a <=( A268 and a4020a );
a4022a <=( a4021a and a4016a );
a4025a <=( A168 and A169 );
a4029a <=( A265 and (not A166) );
a4030a <=( A167 and a4029a );
a4031a <=( a4030a and a4025a );
a4034a <=( A267 and (not A266) );
a4038a <=( (not A299) and (not A298) );
a4039a <=( A268 and a4038a );
a4040a <=( a4039a and a4034a );
a4043a <=( A168 and A169 );
a4047a <=( A265 and (not A166) );
a4048a <=( A167 and a4047a );
a4049a <=( a4048a and a4043a );
a4052a <=( A267 and (not A266) );
a4056a <=( A301 and (not A300) );
a4057a <=( (not A269) and a4056a );
a4058a <=( a4057a and a4052a );
a4061a <=( A168 and A169 );
a4065a <=( A265 and (not A166) );
a4066a <=( A167 and a4065a );
a4067a <=( a4066a and a4061a );
a4070a <=( A267 and (not A266) );
a4074a <=( (not A302) and (not A300) );
a4075a <=( (not A269) and a4074a );
a4076a <=( a4075a and a4070a );
a4079a <=( A168 and A169 );
a4083a <=( A265 and (not A166) );
a4084a <=( A167 and a4083a );
a4085a <=( a4084a and a4079a );
a4088a <=( A267 and (not A266) );
a4092a <=( A299 and A298 );
a4093a <=( (not A269) and a4092a );
a4094a <=( a4093a and a4088a );
a4097a <=( A168 and A169 );
a4101a <=( A265 and (not A166) );
a4102a <=( A167 and a4101a );
a4103a <=( a4102a and a4097a );
a4106a <=( A267 and (not A266) );
a4110a <=( (not A299) and (not A298) );
a4111a <=( (not A269) and a4110a );
a4112a <=( a4111a and a4106a );
a4115a <=( A168 and A169 );
a4119a <=( (not A265) and (not A166) );
a4120a <=( A167 and a4119a );
a4121a <=( a4120a and a4115a );
a4124a <=( A298 and (not A266) );
a4128a <=( A301 and A300 );
a4129a <=( (not A299) and a4128a );
a4130a <=( a4129a and a4124a );
a4133a <=( A168 and A169 );
a4137a <=( (not A265) and (not A166) );
a4138a <=( A167 and a4137a );
a4139a <=( a4138a and a4133a );
a4142a <=( A298 and (not A266) );
a4146a <=( (not A302) and A300 );
a4147a <=( (not A299) and a4146a );
a4148a <=( a4147a and a4142a );
a4151a <=( A168 and A169 );
a4155a <=( (not A265) and (not A166) );
a4156a <=( A167 and a4155a );
a4157a <=( a4156a and a4151a );
a4160a <=( (not A298) and (not A266) );
a4164a <=( A301 and A300 );
a4165a <=( A299 and a4164a );
a4166a <=( a4165a and a4160a );
a4169a <=( A168 and A169 );
a4173a <=( (not A265) and (not A166) );
a4174a <=( A167 and a4173a );
a4175a <=( a4174a and a4169a );
a4178a <=( (not A298) and (not A266) );
a4182a <=( (not A302) and A300 );
a4183a <=( A299 and a4182a );
a4184a <=( a4183a and a4178a );
a4187a <=( A168 and A169 );
a4191a <=( (not A267) and A166 );
a4192a <=( (not A167) and a4191a );
a4193a <=( a4192a and a4187a );
a4196a <=( A298 and A268 );
a4200a <=( A301 and A300 );
a4201a <=( (not A299) and a4200a );
a4202a <=( a4201a and a4196a );
a4205a <=( A168 and A169 );
a4209a <=( (not A267) and A166 );
a4210a <=( (not A167) and a4209a );
a4211a <=( a4210a and a4205a );
a4214a <=( A298 and A268 );
a4218a <=( (not A302) and A300 );
a4219a <=( (not A299) and a4218a );
a4220a <=( a4219a and a4214a );
a4223a <=( A168 and A169 );
a4227a <=( (not A267) and A166 );
a4228a <=( (not A167) and a4227a );
a4229a <=( a4228a and a4223a );
a4232a <=( (not A298) and A268 );
a4236a <=( A301 and A300 );
a4237a <=( A299 and a4236a );
a4238a <=( a4237a and a4232a );
a4241a <=( A168 and A169 );
a4245a <=( (not A267) and A166 );
a4246a <=( (not A167) and a4245a );
a4247a <=( a4246a and a4241a );
a4250a <=( (not A298) and A268 );
a4254a <=( (not A302) and A300 );
a4255a <=( A299 and a4254a );
a4256a <=( a4255a and a4250a );
a4259a <=( A168 and A169 );
a4263a <=( (not A267) and A166 );
a4264a <=( (not A167) and a4263a );
a4265a <=( a4264a and a4259a );
a4268a <=( A298 and (not A269) );
a4272a <=( A301 and A300 );
a4273a <=( (not A299) and a4272a );
a4274a <=( a4273a and a4268a );
a4277a <=( A168 and A169 );
a4281a <=( (not A267) and A166 );
a4282a <=( (not A167) and a4281a );
a4283a <=( a4282a and a4277a );
a4286a <=( A298 and (not A269) );
a4290a <=( (not A302) and A300 );
a4291a <=( (not A299) and a4290a );
a4292a <=( a4291a and a4286a );
a4295a <=( A168 and A169 );
a4299a <=( (not A267) and A166 );
a4300a <=( (not A167) and a4299a );
a4301a <=( a4300a and a4295a );
a4304a <=( (not A298) and (not A269) );
a4308a <=( A301 and A300 );
a4309a <=( A299 and a4308a );
a4310a <=( a4309a and a4304a );
a4313a <=( A168 and A169 );
a4317a <=( (not A267) and A166 );
a4318a <=( (not A167) and a4317a );
a4319a <=( a4318a and a4313a );
a4322a <=( (not A298) and (not A269) );
a4326a <=( (not A302) and A300 );
a4327a <=( A299 and a4326a );
a4328a <=( a4327a and a4322a );
a4331a <=( A168 and A169 );
a4335a <=( A265 and A166 );
a4336a <=( (not A167) and a4335a );
a4337a <=( a4336a and a4331a );
a4340a <=( A298 and A266 );
a4344a <=( A301 and A300 );
a4345a <=( (not A299) and a4344a );
a4346a <=( a4345a and a4340a );
a4349a <=( A168 and A169 );
a4353a <=( A265 and A166 );
a4354a <=( (not A167) and a4353a );
a4355a <=( a4354a and a4349a );
a4358a <=( A298 and A266 );
a4362a <=( (not A302) and A300 );
a4363a <=( (not A299) and a4362a );
a4364a <=( a4363a and a4358a );
a4367a <=( A168 and A169 );
a4371a <=( A265 and A166 );
a4372a <=( (not A167) and a4371a );
a4373a <=( a4372a and a4367a );
a4376a <=( (not A298) and A266 );
a4380a <=( A301 and A300 );
a4381a <=( A299 and a4380a );
a4382a <=( a4381a and a4376a );
a4385a <=( A168 and A169 );
a4389a <=( A265 and A166 );
a4390a <=( (not A167) and a4389a );
a4391a <=( a4390a and a4385a );
a4394a <=( (not A298) and A266 );
a4398a <=( (not A302) and A300 );
a4399a <=( A299 and a4398a );
a4400a <=( a4399a and a4394a );
a4403a <=( A168 and A169 );
a4407a <=( (not A265) and A166 );
a4408a <=( (not A167) and a4407a );
a4409a <=( a4408a and a4403a );
a4412a <=( A267 and A266 );
a4416a <=( A301 and (not A300) );
a4417a <=( A268 and a4416a );
a4418a <=( a4417a and a4412a );
a4421a <=( A168 and A169 );
a4425a <=( (not A265) and A166 );
a4426a <=( (not A167) and a4425a );
a4427a <=( a4426a and a4421a );
a4430a <=( A267 and A266 );
a4434a <=( (not A302) and (not A300) );
a4435a <=( A268 and a4434a );
a4436a <=( a4435a and a4430a );
a4439a <=( A168 and A169 );
a4443a <=( (not A265) and A166 );
a4444a <=( (not A167) and a4443a );
a4445a <=( a4444a and a4439a );
a4448a <=( A267 and A266 );
a4452a <=( A299 and A298 );
a4453a <=( A268 and a4452a );
a4454a <=( a4453a and a4448a );
a4457a <=( A168 and A169 );
a4461a <=( (not A265) and A166 );
a4462a <=( (not A167) and a4461a );
a4463a <=( a4462a and a4457a );
a4466a <=( A267 and A266 );
a4470a <=( (not A299) and (not A298) );
a4471a <=( A268 and a4470a );
a4472a <=( a4471a and a4466a );
a4475a <=( A168 and A169 );
a4479a <=( (not A265) and A166 );
a4480a <=( (not A167) and a4479a );
a4481a <=( a4480a and a4475a );
a4484a <=( A267 and A266 );
a4488a <=( A301 and (not A300) );
a4489a <=( (not A269) and a4488a );
a4490a <=( a4489a and a4484a );
a4493a <=( A168 and A169 );
a4497a <=( (not A265) and A166 );
a4498a <=( (not A167) and a4497a );
a4499a <=( a4498a and a4493a );
a4502a <=( A267 and A266 );
a4506a <=( (not A302) and (not A300) );
a4507a <=( (not A269) and a4506a );
a4508a <=( a4507a and a4502a );
a4511a <=( A168 and A169 );
a4515a <=( (not A265) and A166 );
a4516a <=( (not A167) and a4515a );
a4517a <=( a4516a and a4511a );
a4520a <=( A267 and A266 );
a4524a <=( A299 and A298 );
a4525a <=( (not A269) and a4524a );
a4526a <=( a4525a and a4520a );
a4529a <=( A168 and A169 );
a4533a <=( (not A265) and A166 );
a4534a <=( (not A167) and a4533a );
a4535a <=( a4534a and a4529a );
a4538a <=( A267 and A266 );
a4542a <=( (not A299) and (not A298) );
a4543a <=( (not A269) and a4542a );
a4544a <=( a4543a and a4538a );
a4547a <=( A168 and A169 );
a4551a <=( A265 and A166 );
a4552a <=( (not A167) and a4551a );
a4553a <=( a4552a and a4547a );
a4556a <=( A267 and (not A266) );
a4560a <=( A301 and (not A300) );
a4561a <=( A268 and a4560a );
a4562a <=( a4561a and a4556a );
a4565a <=( A168 and A169 );
a4569a <=( A265 and A166 );
a4570a <=( (not A167) and a4569a );
a4571a <=( a4570a and a4565a );
a4574a <=( A267 and (not A266) );
a4578a <=( (not A302) and (not A300) );
a4579a <=( A268 and a4578a );
a4580a <=( a4579a and a4574a );
a4583a <=( A168 and A169 );
a4587a <=( A265 and A166 );
a4588a <=( (not A167) and a4587a );
a4589a <=( a4588a and a4583a );
a4592a <=( A267 and (not A266) );
a4596a <=( A299 and A298 );
a4597a <=( A268 and a4596a );
a4598a <=( a4597a and a4592a );
a4601a <=( A168 and A169 );
a4605a <=( A265 and A166 );
a4606a <=( (not A167) and a4605a );
a4607a <=( a4606a and a4601a );
a4610a <=( A267 and (not A266) );
a4614a <=( (not A299) and (not A298) );
a4615a <=( A268 and a4614a );
a4616a <=( a4615a and a4610a );
a4619a <=( A168 and A169 );
a4623a <=( A265 and A166 );
a4624a <=( (not A167) and a4623a );
a4625a <=( a4624a and a4619a );
a4628a <=( A267 and (not A266) );
a4632a <=( A301 and (not A300) );
a4633a <=( (not A269) and a4632a );
a4634a <=( a4633a and a4628a );
a4637a <=( A168 and A169 );
a4641a <=( A265 and A166 );
a4642a <=( (not A167) and a4641a );
a4643a <=( a4642a and a4637a );
a4646a <=( A267 and (not A266) );
a4650a <=( (not A302) and (not A300) );
a4651a <=( (not A269) and a4650a );
a4652a <=( a4651a and a4646a );
a4655a <=( A168 and A169 );
a4659a <=( A265 and A166 );
a4660a <=( (not A167) and a4659a );
a4661a <=( a4660a and a4655a );
a4664a <=( A267 and (not A266) );
a4668a <=( A299 and A298 );
a4669a <=( (not A269) and a4668a );
a4670a <=( a4669a and a4664a );
a4673a <=( A168 and A169 );
a4677a <=( A265 and A166 );
a4678a <=( (not A167) and a4677a );
a4679a <=( a4678a and a4673a );
a4682a <=( A267 and (not A266) );
a4686a <=( (not A299) and (not A298) );
a4687a <=( (not A269) and a4686a );
a4688a <=( a4687a and a4682a );
a4691a <=( A168 and A169 );
a4695a <=( (not A265) and A166 );
a4696a <=( (not A167) and a4695a );
a4697a <=( a4696a and a4691a );
a4700a <=( A298 and (not A266) );
a4704a <=( A301 and A300 );
a4705a <=( (not A299) and a4704a );
a4706a <=( a4705a and a4700a );
a4709a <=( A168 and A169 );
a4713a <=( (not A265) and A166 );
a4714a <=( (not A167) and a4713a );
a4715a <=( a4714a and a4709a );
a4718a <=( A298 and (not A266) );
a4722a <=( (not A302) and A300 );
a4723a <=( (not A299) and a4722a );
a4724a <=( a4723a and a4718a );
a4727a <=( A168 and A169 );
a4731a <=( (not A265) and A166 );
a4732a <=( (not A167) and a4731a );
a4733a <=( a4732a and a4727a );
a4736a <=( (not A298) and (not A266) );
a4740a <=( A301 and A300 );
a4741a <=( A299 and a4740a );
a4742a <=( a4741a and a4736a );
a4745a <=( A168 and A169 );
a4749a <=( (not A265) and A166 );
a4750a <=( (not A167) and a4749a );
a4751a <=( a4750a and a4745a );
a4754a <=( (not A298) and (not A266) );
a4758a <=( (not A302) and A300 );
a4759a <=( A299 and a4758a );
a4760a <=( a4759a and a4754a );
a4763a <=( A168 and A170 );
a4767a <=( A267 and (not A166) );
a4768a <=( A167 and a4767a );
a4769a <=( a4768a and a4763a );
a4773a <=( A298 and A269 );
a4774a <=( (not A268) and a4773a );
a4778a <=( A301 and A300 );
a4779a <=( (not A299) and a4778a );
a4780a <=( a4779a and a4774a );
a4783a <=( A168 and A170 );
a4787a <=( A267 and (not A166) );
a4788a <=( A167 and a4787a );
a4789a <=( a4788a and a4783a );
a4793a <=( A298 and A269 );
a4794a <=( (not A268) and a4793a );
a4798a <=( (not A302) and A300 );
a4799a <=( (not A299) and a4798a );
a4800a <=( a4799a and a4794a );
a4803a <=( A168 and A170 );
a4807a <=( A267 and (not A166) );
a4808a <=( A167 and a4807a );
a4809a <=( a4808a and a4803a );
a4813a <=( (not A298) and A269 );
a4814a <=( (not A268) and a4813a );
a4818a <=( A301 and A300 );
a4819a <=( A299 and a4818a );
a4820a <=( a4819a and a4814a );
a4823a <=( A168 and A170 );
a4827a <=( A267 and (not A166) );
a4828a <=( A167 and a4827a );
a4829a <=( a4828a and a4823a );
a4833a <=( (not A298) and A269 );
a4834a <=( (not A268) and a4833a );
a4838a <=( (not A302) and A300 );
a4839a <=( A299 and a4838a );
a4840a <=( a4839a and a4834a );
a4843a <=( A168 and A170 );
a4847a <=( (not A267) and (not A166) );
a4848a <=( A167 and a4847a );
a4849a <=( a4848a and a4843a );
a4853a <=( (not A299) and A298 );
a4854a <=( A268 and a4853a );
a4858a <=( A302 and (not A301) );
a4859a <=( (not A300) and a4858a );
a4860a <=( a4859a and a4854a );
a4863a <=( A168 and A170 );
a4867a <=( (not A267) and (not A166) );
a4868a <=( A167 and a4867a );
a4869a <=( a4868a and a4863a );
a4873a <=( A299 and (not A298) );
a4874a <=( A268 and a4873a );
a4878a <=( A302 and (not A301) );
a4879a <=( (not A300) and a4878a );
a4880a <=( a4879a and a4874a );
a4883a <=( A168 and A170 );
a4887a <=( (not A267) and (not A166) );
a4888a <=( A167 and a4887a );
a4889a <=( a4888a and a4883a );
a4893a <=( (not A299) and A298 );
a4894a <=( (not A269) and a4893a );
a4898a <=( A302 and (not A301) );
a4899a <=( (not A300) and a4898a );
a4900a <=( a4899a and a4894a );
a4903a <=( A168 and A170 );
a4907a <=( (not A267) and (not A166) );
a4908a <=( A167 and a4907a );
a4909a <=( a4908a and a4903a );
a4913a <=( A299 and (not A298) );
a4914a <=( (not A269) and a4913a );
a4918a <=( A302 and (not A301) );
a4919a <=( (not A300) and a4918a );
a4920a <=( a4919a and a4914a );
a4923a <=( A168 and A170 );
a4927a <=( A265 and (not A166) );
a4928a <=( A167 and a4927a );
a4929a <=( a4928a and a4923a );
a4933a <=( (not A299) and A298 );
a4934a <=( A266 and a4933a );
a4938a <=( A302 and (not A301) );
a4939a <=( (not A300) and a4938a );
a4940a <=( a4939a and a4934a );
a4943a <=( A168 and A170 );
a4947a <=( A265 and (not A166) );
a4948a <=( A167 and a4947a );
a4949a <=( a4948a and a4943a );
a4953a <=( A299 and (not A298) );
a4954a <=( A266 and a4953a );
a4958a <=( A302 and (not A301) );
a4959a <=( (not A300) and a4958a );
a4960a <=( a4959a and a4954a );
a4963a <=( A168 and A170 );
a4967a <=( (not A265) and (not A166) );
a4968a <=( A167 and a4967a );
a4969a <=( a4968a and a4963a );
a4973a <=( A268 and A267 );
a4974a <=( A266 and a4973a );
a4978a <=( A302 and (not A301) );
a4979a <=( A300 and a4978a );
a4980a <=( a4979a and a4974a );
a4983a <=( A168 and A170 );
a4987a <=( (not A265) and (not A166) );
a4988a <=( A167 and a4987a );
a4989a <=( a4988a and a4983a );
a4993a <=( (not A269) and A267 );
a4994a <=( A266 and a4993a );
a4998a <=( A302 and (not A301) );
a4999a <=( A300 and a4998a );
a5000a <=( a4999a and a4994a );
a5003a <=( A168 and A170 );
a5007a <=( (not A265) and (not A166) );
a5008a <=( A167 and a5007a );
a5009a <=( a5008a and a5003a );
a5013a <=( (not A268) and (not A267) );
a5014a <=( A266 and a5013a );
a5018a <=( A301 and (not A300) );
a5019a <=( A269 and a5018a );
a5020a <=( a5019a and a5014a );
a5023a <=( A168 and A170 );
a5027a <=( (not A265) and (not A166) );
a5028a <=( A167 and a5027a );
a5029a <=( a5028a and a5023a );
a5033a <=( (not A268) and (not A267) );
a5034a <=( A266 and a5033a );
a5038a <=( (not A302) and (not A300) );
a5039a <=( A269 and a5038a );
a5040a <=( a5039a and a5034a );
a5043a <=( A168 and A170 );
a5047a <=( (not A265) and (not A166) );
a5048a <=( A167 and a5047a );
a5049a <=( a5048a and a5043a );
a5053a <=( (not A268) and (not A267) );
a5054a <=( A266 and a5053a );
a5058a <=( A299 and A298 );
a5059a <=( A269 and a5058a );
a5060a <=( a5059a and a5054a );
a5063a <=( A168 and A170 );
a5067a <=( (not A265) and (not A166) );
a5068a <=( A167 and a5067a );
a5069a <=( a5068a and a5063a );
a5073a <=( (not A268) and (not A267) );
a5074a <=( A266 and a5073a );
a5078a <=( (not A299) and (not A298) );
a5079a <=( A269 and a5078a );
a5080a <=( a5079a and a5074a );
a5083a <=( A168 and A170 );
a5087a <=( A265 and (not A166) );
a5088a <=( A167 and a5087a );
a5089a <=( a5088a and a5083a );
a5093a <=( A268 and A267 );
a5094a <=( (not A266) and a5093a );
a5098a <=( A302 and (not A301) );
a5099a <=( A300 and a5098a );
a5100a <=( a5099a and a5094a );
a5103a <=( A168 and A170 );
a5107a <=( A265 and (not A166) );
a5108a <=( A167 and a5107a );
a5109a <=( a5108a and a5103a );
a5113a <=( (not A269) and A267 );
a5114a <=( (not A266) and a5113a );
a5118a <=( A302 and (not A301) );
a5119a <=( A300 and a5118a );
a5120a <=( a5119a and a5114a );
a5123a <=( A168 and A170 );
a5127a <=( A265 and (not A166) );
a5128a <=( A167 and a5127a );
a5129a <=( a5128a and a5123a );
a5133a <=( (not A268) and (not A267) );
a5134a <=( (not A266) and a5133a );
a5138a <=( A301 and (not A300) );
a5139a <=( A269 and a5138a );
a5140a <=( a5139a and a5134a );
a5143a <=( A168 and A170 );
a5147a <=( A265 and (not A166) );
a5148a <=( A167 and a5147a );
a5149a <=( a5148a and a5143a );
a5153a <=( (not A268) and (not A267) );
a5154a <=( (not A266) and a5153a );
a5158a <=( (not A302) and (not A300) );
a5159a <=( A269 and a5158a );
a5160a <=( a5159a and a5154a );
a5163a <=( A168 and A170 );
a5167a <=( A265 and (not A166) );
a5168a <=( A167 and a5167a );
a5169a <=( a5168a and a5163a );
a5173a <=( (not A268) and (not A267) );
a5174a <=( (not A266) and a5173a );
a5178a <=( A299 and A298 );
a5179a <=( A269 and a5178a );
a5180a <=( a5179a and a5174a );
a5183a <=( A168 and A170 );
a5187a <=( A265 and (not A166) );
a5188a <=( A167 and a5187a );
a5189a <=( a5188a and a5183a );
a5193a <=( (not A268) and (not A267) );
a5194a <=( (not A266) and a5193a );
a5198a <=( (not A299) and (not A298) );
a5199a <=( A269 and a5198a );
a5200a <=( a5199a and a5194a );
a5203a <=( A168 and A170 );
a5207a <=( (not A265) and (not A166) );
a5208a <=( A167 and a5207a );
a5209a <=( a5208a and a5203a );
a5213a <=( (not A299) and A298 );
a5214a <=( (not A266) and a5213a );
a5218a <=( A302 and (not A301) );
a5219a <=( (not A300) and a5218a );
a5220a <=( a5219a and a5214a );
a5223a <=( A168 and A170 );
a5227a <=( (not A265) and (not A166) );
a5228a <=( A167 and a5227a );
a5229a <=( a5228a and a5223a );
a5233a <=( A299 and (not A298) );
a5234a <=( (not A266) and a5233a );
a5238a <=( A302 and (not A301) );
a5239a <=( (not A300) and a5238a );
a5240a <=( a5239a and a5234a );
a5243a <=( A168 and A170 );
a5247a <=( A267 and A166 );
a5248a <=( (not A167) and a5247a );
a5249a <=( a5248a and a5243a );
a5253a <=( A298 and A269 );
a5254a <=( (not A268) and a5253a );
a5258a <=( A301 and A300 );
a5259a <=( (not A299) and a5258a );
a5260a <=( a5259a and a5254a );
a5263a <=( A168 and A170 );
a5267a <=( A267 and A166 );
a5268a <=( (not A167) and a5267a );
a5269a <=( a5268a and a5263a );
a5273a <=( A298 and A269 );
a5274a <=( (not A268) and a5273a );
a5278a <=( (not A302) and A300 );
a5279a <=( (not A299) and a5278a );
a5280a <=( a5279a and a5274a );
a5283a <=( A168 and A170 );
a5287a <=( A267 and A166 );
a5288a <=( (not A167) and a5287a );
a5289a <=( a5288a and a5283a );
a5293a <=( (not A298) and A269 );
a5294a <=( (not A268) and a5293a );
a5298a <=( A301 and A300 );
a5299a <=( A299 and a5298a );
a5300a <=( a5299a and a5294a );
a5303a <=( A168 and A170 );
a5307a <=( A267 and A166 );
a5308a <=( (not A167) and a5307a );
a5309a <=( a5308a and a5303a );
a5313a <=( (not A298) and A269 );
a5314a <=( (not A268) and a5313a );
a5318a <=( (not A302) and A300 );
a5319a <=( A299 and a5318a );
a5320a <=( a5319a and a5314a );
a5323a <=( A168 and A170 );
a5327a <=( (not A267) and A166 );
a5328a <=( (not A167) and a5327a );
a5329a <=( a5328a and a5323a );
a5333a <=( (not A299) and A298 );
a5334a <=( A268 and a5333a );
a5338a <=( A302 and (not A301) );
a5339a <=( (not A300) and a5338a );
a5340a <=( a5339a and a5334a );
a5343a <=( A168 and A170 );
a5347a <=( (not A267) and A166 );
a5348a <=( (not A167) and a5347a );
a5349a <=( a5348a and a5343a );
a5353a <=( A299 and (not A298) );
a5354a <=( A268 and a5353a );
a5358a <=( A302 and (not A301) );
a5359a <=( (not A300) and a5358a );
a5360a <=( a5359a and a5354a );
a5363a <=( A168 and A170 );
a5367a <=( (not A267) and A166 );
a5368a <=( (not A167) and a5367a );
a5369a <=( a5368a and a5363a );
a5373a <=( (not A299) and A298 );
a5374a <=( (not A269) and a5373a );
a5378a <=( A302 and (not A301) );
a5379a <=( (not A300) and a5378a );
a5380a <=( a5379a and a5374a );
a5383a <=( A168 and A170 );
a5387a <=( (not A267) and A166 );
a5388a <=( (not A167) and a5387a );
a5389a <=( a5388a and a5383a );
a5393a <=( A299 and (not A298) );
a5394a <=( (not A269) and a5393a );
a5398a <=( A302 and (not A301) );
a5399a <=( (not A300) and a5398a );
a5400a <=( a5399a and a5394a );
a5403a <=( A168 and A170 );
a5407a <=( A265 and A166 );
a5408a <=( (not A167) and a5407a );
a5409a <=( a5408a and a5403a );
a5413a <=( (not A299) and A298 );
a5414a <=( A266 and a5413a );
a5418a <=( A302 and (not A301) );
a5419a <=( (not A300) and a5418a );
a5420a <=( a5419a and a5414a );
a5423a <=( A168 and A170 );
a5427a <=( A265 and A166 );
a5428a <=( (not A167) and a5427a );
a5429a <=( a5428a and a5423a );
a5433a <=( A299 and (not A298) );
a5434a <=( A266 and a5433a );
a5438a <=( A302 and (not A301) );
a5439a <=( (not A300) and a5438a );
a5440a <=( a5439a and a5434a );
a5443a <=( A168 and A170 );
a5447a <=( (not A265) and A166 );
a5448a <=( (not A167) and a5447a );
a5449a <=( a5448a and a5443a );
a5453a <=( A268 and A267 );
a5454a <=( A266 and a5453a );
a5458a <=( A302 and (not A301) );
a5459a <=( A300 and a5458a );
a5460a <=( a5459a and a5454a );
a5463a <=( A168 and A170 );
a5467a <=( (not A265) and A166 );
a5468a <=( (not A167) and a5467a );
a5469a <=( a5468a and a5463a );
a5473a <=( (not A269) and A267 );
a5474a <=( A266 and a5473a );
a5478a <=( A302 and (not A301) );
a5479a <=( A300 and a5478a );
a5480a <=( a5479a and a5474a );
a5483a <=( A168 and A170 );
a5487a <=( (not A265) and A166 );
a5488a <=( (not A167) and a5487a );
a5489a <=( a5488a and a5483a );
a5493a <=( (not A268) and (not A267) );
a5494a <=( A266 and a5493a );
a5498a <=( A301 and (not A300) );
a5499a <=( A269 and a5498a );
a5500a <=( a5499a and a5494a );
a5503a <=( A168 and A170 );
a5507a <=( (not A265) and A166 );
a5508a <=( (not A167) and a5507a );
a5509a <=( a5508a and a5503a );
a5513a <=( (not A268) and (not A267) );
a5514a <=( A266 and a5513a );
a5518a <=( (not A302) and (not A300) );
a5519a <=( A269 and a5518a );
a5520a <=( a5519a and a5514a );
a5523a <=( A168 and A170 );
a5527a <=( (not A265) and A166 );
a5528a <=( (not A167) and a5527a );
a5529a <=( a5528a and a5523a );
a5533a <=( (not A268) and (not A267) );
a5534a <=( A266 and a5533a );
a5538a <=( A299 and A298 );
a5539a <=( A269 and a5538a );
a5540a <=( a5539a and a5534a );
a5543a <=( A168 and A170 );
a5547a <=( (not A265) and A166 );
a5548a <=( (not A167) and a5547a );
a5549a <=( a5548a and a5543a );
a5553a <=( (not A268) and (not A267) );
a5554a <=( A266 and a5553a );
a5558a <=( (not A299) and (not A298) );
a5559a <=( A269 and a5558a );
a5560a <=( a5559a and a5554a );
a5563a <=( A168 and A170 );
a5567a <=( A265 and A166 );
a5568a <=( (not A167) and a5567a );
a5569a <=( a5568a and a5563a );
a5573a <=( A268 and A267 );
a5574a <=( (not A266) and a5573a );
a5578a <=( A302 and (not A301) );
a5579a <=( A300 and a5578a );
a5580a <=( a5579a and a5574a );
a5583a <=( A168 and A170 );
a5587a <=( A265 and A166 );
a5588a <=( (not A167) and a5587a );
a5589a <=( a5588a and a5583a );
a5593a <=( (not A269) and A267 );
a5594a <=( (not A266) and a5593a );
a5598a <=( A302 and (not A301) );
a5599a <=( A300 and a5598a );
a5600a <=( a5599a and a5594a );
a5603a <=( A168 and A170 );
a5607a <=( A265 and A166 );
a5608a <=( (not A167) and a5607a );
a5609a <=( a5608a and a5603a );
a5613a <=( (not A268) and (not A267) );
a5614a <=( (not A266) and a5613a );
a5618a <=( A301 and (not A300) );
a5619a <=( A269 and a5618a );
a5620a <=( a5619a and a5614a );
a5623a <=( A168 and A170 );
a5627a <=( A265 and A166 );
a5628a <=( (not A167) and a5627a );
a5629a <=( a5628a and a5623a );
a5633a <=( (not A268) and (not A267) );
a5634a <=( (not A266) and a5633a );
a5638a <=( (not A302) and (not A300) );
a5639a <=( A269 and a5638a );
a5640a <=( a5639a and a5634a );
a5643a <=( A168 and A170 );
a5647a <=( A265 and A166 );
a5648a <=( (not A167) and a5647a );
a5649a <=( a5648a and a5643a );
a5653a <=( (not A268) and (not A267) );
a5654a <=( (not A266) and a5653a );
a5658a <=( A299 and A298 );
a5659a <=( A269 and a5658a );
a5660a <=( a5659a and a5654a );
a5663a <=( A168 and A170 );
a5667a <=( A265 and A166 );
a5668a <=( (not A167) and a5667a );
a5669a <=( a5668a and a5663a );
a5673a <=( (not A268) and (not A267) );
a5674a <=( (not A266) and a5673a );
a5678a <=( (not A299) and (not A298) );
a5679a <=( A269 and a5678a );
a5680a <=( a5679a and a5674a );
a5683a <=( A168 and A170 );
a5687a <=( (not A265) and A166 );
a5688a <=( (not A167) and a5687a );
a5689a <=( a5688a and a5683a );
a5693a <=( (not A299) and A298 );
a5694a <=( (not A266) and a5693a );
a5698a <=( A302 and (not A301) );
a5699a <=( (not A300) and a5698a );
a5700a <=( a5699a and a5694a );
a5703a <=( A168 and A170 );
a5707a <=( (not A265) and A166 );
a5708a <=( (not A167) and a5707a );
a5709a <=( a5708a and a5703a );
a5713a <=( A299 and (not A298) );
a5714a <=( (not A266) and a5713a );
a5718a <=( A302 and (not A301) );
a5719a <=( (not A300) and a5718a );
a5720a <=( a5719a and a5714a );
a5723a <=( A168 and A169 );
a5727a <=( A267 and (not A166) );
a5728a <=( A167 and a5727a );
a5729a <=( a5728a and a5723a );
a5733a <=( A298 and A269 );
a5734a <=( (not A268) and a5733a );
a5738a <=( A301 and A300 );
a5739a <=( (not A299) and a5738a );
a5740a <=( a5739a and a5734a );
a5743a <=( A168 and A169 );
a5747a <=( A267 and (not A166) );
a5748a <=( A167 and a5747a );
a5749a <=( a5748a and a5743a );
a5753a <=( A298 and A269 );
a5754a <=( (not A268) and a5753a );
a5758a <=( (not A302) and A300 );
a5759a <=( (not A299) and a5758a );
a5760a <=( a5759a and a5754a );
a5763a <=( A168 and A169 );
a5767a <=( A267 and (not A166) );
a5768a <=( A167 and a5767a );
a5769a <=( a5768a and a5763a );
a5773a <=( (not A298) and A269 );
a5774a <=( (not A268) and a5773a );
a5778a <=( A301 and A300 );
a5779a <=( A299 and a5778a );
a5780a <=( a5779a and a5774a );
a5783a <=( A168 and A169 );
a5787a <=( A267 and (not A166) );
a5788a <=( A167 and a5787a );
a5789a <=( a5788a and a5783a );
a5793a <=( (not A298) and A269 );
a5794a <=( (not A268) and a5793a );
a5798a <=( (not A302) and A300 );
a5799a <=( A299 and a5798a );
a5800a <=( a5799a and a5794a );
a5803a <=( A168 and A169 );
a5807a <=( (not A267) and (not A166) );
a5808a <=( A167 and a5807a );
a5809a <=( a5808a and a5803a );
a5813a <=( (not A299) and A298 );
a5814a <=( A268 and a5813a );
a5818a <=( A302 and (not A301) );
a5819a <=( (not A300) and a5818a );
a5820a <=( a5819a and a5814a );
a5823a <=( A168 and A169 );
a5827a <=( (not A267) and (not A166) );
a5828a <=( A167 and a5827a );
a5829a <=( a5828a and a5823a );
a5833a <=( A299 and (not A298) );
a5834a <=( A268 and a5833a );
a5838a <=( A302 and (not A301) );
a5839a <=( (not A300) and a5838a );
a5840a <=( a5839a and a5834a );
a5843a <=( A168 and A169 );
a5847a <=( (not A267) and (not A166) );
a5848a <=( A167 and a5847a );
a5849a <=( a5848a and a5843a );
a5853a <=( (not A299) and A298 );
a5854a <=( (not A269) and a5853a );
a5858a <=( A302 and (not A301) );
a5859a <=( (not A300) and a5858a );
a5860a <=( a5859a and a5854a );
a5863a <=( A168 and A169 );
a5867a <=( (not A267) and (not A166) );
a5868a <=( A167 and a5867a );
a5869a <=( a5868a and a5863a );
a5873a <=( A299 and (not A298) );
a5874a <=( (not A269) and a5873a );
a5878a <=( A302 and (not A301) );
a5879a <=( (not A300) and a5878a );
a5880a <=( a5879a and a5874a );
a5883a <=( A168 and A169 );
a5887a <=( A265 and (not A166) );
a5888a <=( A167 and a5887a );
a5889a <=( a5888a and a5883a );
a5893a <=( (not A299) and A298 );
a5894a <=( A266 and a5893a );
a5898a <=( A302 and (not A301) );
a5899a <=( (not A300) and a5898a );
a5900a <=( a5899a and a5894a );
a5903a <=( A168 and A169 );
a5907a <=( A265 and (not A166) );
a5908a <=( A167 and a5907a );
a5909a <=( a5908a and a5903a );
a5913a <=( A299 and (not A298) );
a5914a <=( A266 and a5913a );
a5918a <=( A302 and (not A301) );
a5919a <=( (not A300) and a5918a );
a5920a <=( a5919a and a5914a );
a5923a <=( A168 and A169 );
a5927a <=( (not A265) and (not A166) );
a5928a <=( A167 and a5927a );
a5929a <=( a5928a and a5923a );
a5933a <=( A268 and A267 );
a5934a <=( A266 and a5933a );
a5938a <=( A302 and (not A301) );
a5939a <=( A300 and a5938a );
a5940a <=( a5939a and a5934a );
a5943a <=( A168 and A169 );
a5947a <=( (not A265) and (not A166) );
a5948a <=( A167 and a5947a );
a5949a <=( a5948a and a5943a );
a5953a <=( (not A269) and A267 );
a5954a <=( A266 and a5953a );
a5958a <=( A302 and (not A301) );
a5959a <=( A300 and a5958a );
a5960a <=( a5959a and a5954a );
a5963a <=( A168 and A169 );
a5967a <=( (not A265) and (not A166) );
a5968a <=( A167 and a5967a );
a5969a <=( a5968a and a5963a );
a5973a <=( (not A268) and (not A267) );
a5974a <=( A266 and a5973a );
a5978a <=( A301 and (not A300) );
a5979a <=( A269 and a5978a );
a5980a <=( a5979a and a5974a );
a5983a <=( A168 and A169 );
a5987a <=( (not A265) and (not A166) );
a5988a <=( A167 and a5987a );
a5989a <=( a5988a and a5983a );
a5993a <=( (not A268) and (not A267) );
a5994a <=( A266 and a5993a );
a5998a <=( (not A302) and (not A300) );
a5999a <=( A269 and a5998a );
a6000a <=( a5999a and a5994a );
a6003a <=( A168 and A169 );
a6007a <=( (not A265) and (not A166) );
a6008a <=( A167 and a6007a );
a6009a <=( a6008a and a6003a );
a6013a <=( (not A268) and (not A267) );
a6014a <=( A266 and a6013a );
a6018a <=( A299 and A298 );
a6019a <=( A269 and a6018a );
a6020a <=( a6019a and a6014a );
a6023a <=( A168 and A169 );
a6027a <=( (not A265) and (not A166) );
a6028a <=( A167 and a6027a );
a6029a <=( a6028a and a6023a );
a6033a <=( (not A268) and (not A267) );
a6034a <=( A266 and a6033a );
a6038a <=( (not A299) and (not A298) );
a6039a <=( A269 and a6038a );
a6040a <=( a6039a and a6034a );
a6043a <=( A168 and A169 );
a6047a <=( A265 and (not A166) );
a6048a <=( A167 and a6047a );
a6049a <=( a6048a and a6043a );
a6053a <=( A268 and A267 );
a6054a <=( (not A266) and a6053a );
a6058a <=( A302 and (not A301) );
a6059a <=( A300 and a6058a );
a6060a <=( a6059a and a6054a );
a6063a <=( A168 and A169 );
a6067a <=( A265 and (not A166) );
a6068a <=( A167 and a6067a );
a6069a <=( a6068a and a6063a );
a6073a <=( (not A269) and A267 );
a6074a <=( (not A266) and a6073a );
a6078a <=( A302 and (not A301) );
a6079a <=( A300 and a6078a );
a6080a <=( a6079a and a6074a );
a6083a <=( A168 and A169 );
a6087a <=( A265 and (not A166) );
a6088a <=( A167 and a6087a );
a6089a <=( a6088a and a6083a );
a6093a <=( (not A268) and (not A267) );
a6094a <=( (not A266) and a6093a );
a6098a <=( A301 and (not A300) );
a6099a <=( A269 and a6098a );
a6100a <=( a6099a and a6094a );
a6103a <=( A168 and A169 );
a6107a <=( A265 and (not A166) );
a6108a <=( A167 and a6107a );
a6109a <=( a6108a and a6103a );
a6113a <=( (not A268) and (not A267) );
a6114a <=( (not A266) and a6113a );
a6118a <=( (not A302) and (not A300) );
a6119a <=( A269 and a6118a );
a6120a <=( a6119a and a6114a );
a6123a <=( A168 and A169 );
a6127a <=( A265 and (not A166) );
a6128a <=( A167 and a6127a );
a6129a <=( a6128a and a6123a );
a6133a <=( (not A268) and (not A267) );
a6134a <=( (not A266) and a6133a );
a6138a <=( A299 and A298 );
a6139a <=( A269 and a6138a );
a6140a <=( a6139a and a6134a );
a6143a <=( A168 and A169 );
a6147a <=( A265 and (not A166) );
a6148a <=( A167 and a6147a );
a6149a <=( a6148a and a6143a );
a6153a <=( (not A268) and (not A267) );
a6154a <=( (not A266) and a6153a );
a6158a <=( (not A299) and (not A298) );
a6159a <=( A269 and a6158a );
a6160a <=( a6159a and a6154a );
a6163a <=( A168 and A169 );
a6167a <=( (not A265) and (not A166) );
a6168a <=( A167 and a6167a );
a6169a <=( a6168a and a6163a );
a6173a <=( (not A299) and A298 );
a6174a <=( (not A266) and a6173a );
a6178a <=( A302 and (not A301) );
a6179a <=( (not A300) and a6178a );
a6180a <=( a6179a and a6174a );
a6183a <=( A168 and A169 );
a6187a <=( (not A265) and (not A166) );
a6188a <=( A167 and a6187a );
a6189a <=( a6188a and a6183a );
a6193a <=( A299 and (not A298) );
a6194a <=( (not A266) and a6193a );
a6198a <=( A302 and (not A301) );
a6199a <=( (not A300) and a6198a );
a6200a <=( a6199a and a6194a );
a6203a <=( A168 and A169 );
a6207a <=( A267 and A166 );
a6208a <=( (not A167) and a6207a );
a6209a <=( a6208a and a6203a );
a6213a <=( A298 and A269 );
a6214a <=( (not A268) and a6213a );
a6218a <=( A301 and A300 );
a6219a <=( (not A299) and a6218a );
a6220a <=( a6219a and a6214a );
a6223a <=( A168 and A169 );
a6227a <=( A267 and A166 );
a6228a <=( (not A167) and a6227a );
a6229a <=( a6228a and a6223a );
a6233a <=( A298 and A269 );
a6234a <=( (not A268) and a6233a );
a6238a <=( (not A302) and A300 );
a6239a <=( (not A299) and a6238a );
a6240a <=( a6239a and a6234a );
a6243a <=( A168 and A169 );
a6247a <=( A267 and A166 );
a6248a <=( (not A167) and a6247a );
a6249a <=( a6248a and a6243a );
a6253a <=( (not A298) and A269 );
a6254a <=( (not A268) and a6253a );
a6258a <=( A301 and A300 );
a6259a <=( A299 and a6258a );
a6260a <=( a6259a and a6254a );
a6263a <=( A168 and A169 );
a6267a <=( A267 and A166 );
a6268a <=( (not A167) and a6267a );
a6269a <=( a6268a and a6263a );
a6273a <=( (not A298) and A269 );
a6274a <=( (not A268) and a6273a );
a6278a <=( (not A302) and A300 );
a6279a <=( A299 and a6278a );
a6280a <=( a6279a and a6274a );
a6283a <=( A168 and A169 );
a6287a <=( (not A267) and A166 );
a6288a <=( (not A167) and a6287a );
a6289a <=( a6288a and a6283a );
a6293a <=( (not A299) and A298 );
a6294a <=( A268 and a6293a );
a6298a <=( A302 and (not A301) );
a6299a <=( (not A300) and a6298a );
a6300a <=( a6299a and a6294a );
a6303a <=( A168 and A169 );
a6307a <=( (not A267) and A166 );
a6308a <=( (not A167) and a6307a );
a6309a <=( a6308a and a6303a );
a6313a <=( A299 and (not A298) );
a6314a <=( A268 and a6313a );
a6318a <=( A302 and (not A301) );
a6319a <=( (not A300) and a6318a );
a6320a <=( a6319a and a6314a );
a6323a <=( A168 and A169 );
a6327a <=( (not A267) and A166 );
a6328a <=( (not A167) and a6327a );
a6329a <=( a6328a and a6323a );
a6333a <=( (not A299) and A298 );
a6334a <=( (not A269) and a6333a );
a6338a <=( A302 and (not A301) );
a6339a <=( (not A300) and a6338a );
a6340a <=( a6339a and a6334a );
a6343a <=( A168 and A169 );
a6347a <=( (not A267) and A166 );
a6348a <=( (not A167) and a6347a );
a6349a <=( a6348a and a6343a );
a6353a <=( A299 and (not A298) );
a6354a <=( (not A269) and a6353a );
a6358a <=( A302 and (not A301) );
a6359a <=( (not A300) and a6358a );
a6360a <=( a6359a and a6354a );
a6363a <=( A168 and A169 );
a6367a <=( A265 and A166 );
a6368a <=( (not A167) and a6367a );
a6369a <=( a6368a and a6363a );
a6373a <=( (not A299) and A298 );
a6374a <=( A266 and a6373a );
a6378a <=( A302 and (not A301) );
a6379a <=( (not A300) and a6378a );
a6380a <=( a6379a and a6374a );
a6383a <=( A168 and A169 );
a6387a <=( A265 and A166 );
a6388a <=( (not A167) and a6387a );
a6389a <=( a6388a and a6383a );
a6393a <=( A299 and (not A298) );
a6394a <=( A266 and a6393a );
a6398a <=( A302 and (not A301) );
a6399a <=( (not A300) and a6398a );
a6400a <=( a6399a and a6394a );
a6403a <=( A168 and A169 );
a6407a <=( (not A265) and A166 );
a6408a <=( (not A167) and a6407a );
a6409a <=( a6408a and a6403a );
a6413a <=( A268 and A267 );
a6414a <=( A266 and a6413a );
a6418a <=( A302 and (not A301) );
a6419a <=( A300 and a6418a );
a6420a <=( a6419a and a6414a );
a6423a <=( A168 and A169 );
a6427a <=( (not A265) and A166 );
a6428a <=( (not A167) and a6427a );
a6429a <=( a6428a and a6423a );
a6433a <=( (not A269) and A267 );
a6434a <=( A266 and a6433a );
a6438a <=( A302 and (not A301) );
a6439a <=( A300 and a6438a );
a6440a <=( a6439a and a6434a );
a6443a <=( A168 and A169 );
a6447a <=( (not A265) and A166 );
a6448a <=( (not A167) and a6447a );
a6449a <=( a6448a and a6443a );
a6453a <=( (not A268) and (not A267) );
a6454a <=( A266 and a6453a );
a6458a <=( A301 and (not A300) );
a6459a <=( A269 and a6458a );
a6460a <=( a6459a and a6454a );
a6463a <=( A168 and A169 );
a6467a <=( (not A265) and A166 );
a6468a <=( (not A167) and a6467a );
a6469a <=( a6468a and a6463a );
a6473a <=( (not A268) and (not A267) );
a6474a <=( A266 and a6473a );
a6478a <=( (not A302) and (not A300) );
a6479a <=( A269 and a6478a );
a6480a <=( a6479a and a6474a );
a6483a <=( A168 and A169 );
a6487a <=( (not A265) and A166 );
a6488a <=( (not A167) and a6487a );
a6489a <=( a6488a and a6483a );
a6493a <=( (not A268) and (not A267) );
a6494a <=( A266 and a6493a );
a6498a <=( A299 and A298 );
a6499a <=( A269 and a6498a );
a6500a <=( a6499a and a6494a );
a6503a <=( A168 and A169 );
a6507a <=( (not A265) and A166 );
a6508a <=( (not A167) and a6507a );
a6509a <=( a6508a and a6503a );
a6513a <=( (not A268) and (not A267) );
a6514a <=( A266 and a6513a );
a6518a <=( (not A299) and (not A298) );
a6519a <=( A269 and a6518a );
a6520a <=( a6519a and a6514a );
a6523a <=( A168 and A169 );
a6527a <=( A265 and A166 );
a6528a <=( (not A167) and a6527a );
a6529a <=( a6528a and a6523a );
a6533a <=( A268 and A267 );
a6534a <=( (not A266) and a6533a );
a6538a <=( A302 and (not A301) );
a6539a <=( A300 and a6538a );
a6540a <=( a6539a and a6534a );
a6543a <=( A168 and A169 );
a6547a <=( A265 and A166 );
a6548a <=( (not A167) and a6547a );
a6549a <=( a6548a and a6543a );
a6553a <=( (not A269) and A267 );
a6554a <=( (not A266) and a6553a );
a6558a <=( A302 and (not A301) );
a6559a <=( A300 and a6558a );
a6560a <=( a6559a and a6554a );
a6563a <=( A168 and A169 );
a6567a <=( A265 and A166 );
a6568a <=( (not A167) and a6567a );
a6569a <=( a6568a and a6563a );
a6573a <=( (not A268) and (not A267) );
a6574a <=( (not A266) and a6573a );
a6578a <=( A301 and (not A300) );
a6579a <=( A269 and a6578a );
a6580a <=( a6579a and a6574a );
a6583a <=( A168 and A169 );
a6587a <=( A265 and A166 );
a6588a <=( (not A167) and a6587a );
a6589a <=( a6588a and a6583a );
a6593a <=( (not A268) and (not A267) );
a6594a <=( (not A266) and a6593a );
a6598a <=( (not A302) and (not A300) );
a6599a <=( A269 and a6598a );
a6600a <=( a6599a and a6594a );
a6603a <=( A168 and A169 );
a6607a <=( A265 and A166 );
a6608a <=( (not A167) and a6607a );
a6609a <=( a6608a and a6603a );
a6613a <=( (not A268) and (not A267) );
a6614a <=( (not A266) and a6613a );
a6618a <=( A299 and A298 );
a6619a <=( A269 and a6618a );
a6620a <=( a6619a and a6614a );
a6623a <=( A168 and A169 );
a6627a <=( A265 and A166 );
a6628a <=( (not A167) and a6627a );
a6629a <=( a6628a and a6623a );
a6633a <=( (not A268) and (not A267) );
a6634a <=( (not A266) and a6633a );
a6638a <=( (not A299) and (not A298) );
a6639a <=( A269 and a6638a );
a6640a <=( a6639a and a6634a );
a6643a <=( A168 and A169 );
a6647a <=( (not A265) and A166 );
a6648a <=( (not A167) and a6647a );
a6649a <=( a6648a and a6643a );
a6653a <=( (not A299) and A298 );
a6654a <=( (not A266) and a6653a );
a6658a <=( A302 and (not A301) );
a6659a <=( (not A300) and a6658a );
a6660a <=( a6659a and a6654a );
a6663a <=( A168 and A169 );
a6667a <=( (not A265) and A166 );
a6668a <=( (not A167) and a6667a );
a6669a <=( a6668a and a6663a );
a6673a <=( A299 and (not A298) );
a6674a <=( (not A266) and a6673a );
a6678a <=( A302 and (not A301) );
a6679a <=( (not A300) and a6678a );
a6680a <=( a6679a and a6674a );
a6683a <=( (not A169) and (not A170) );
a6687a <=( (not A166) and A167 );
a6688a <=( (not A168) and a6687a );
a6689a <=( a6688a and a6683a );
a6693a <=( A298 and A268 );
a6694a <=( (not A267) and a6693a );
a6698a <=( A301 and A300 );
a6699a <=( (not A299) and a6698a );
a6700a <=( a6699a and a6694a );
a6703a <=( (not A169) and (not A170) );
a6707a <=( (not A166) and A167 );
a6708a <=( (not A168) and a6707a );
a6709a <=( a6708a and a6703a );
a6713a <=( A298 and A268 );
a6714a <=( (not A267) and a6713a );
a6718a <=( (not A302) and A300 );
a6719a <=( (not A299) and a6718a );
a6720a <=( a6719a and a6714a );
a6723a <=( (not A169) and (not A170) );
a6727a <=( (not A166) and A167 );
a6728a <=( (not A168) and a6727a );
a6729a <=( a6728a and a6723a );
a6733a <=( (not A298) and A268 );
a6734a <=( (not A267) and a6733a );
a6738a <=( A301 and A300 );
a6739a <=( A299 and a6738a );
a6740a <=( a6739a and a6734a );
a6743a <=( (not A169) and (not A170) );
a6747a <=( (not A166) and A167 );
a6748a <=( (not A168) and a6747a );
a6749a <=( a6748a and a6743a );
a6753a <=( (not A298) and A268 );
a6754a <=( (not A267) and a6753a );
a6758a <=( (not A302) and A300 );
a6759a <=( A299 and a6758a );
a6760a <=( a6759a and a6754a );
a6763a <=( (not A169) and (not A170) );
a6767a <=( (not A166) and A167 );
a6768a <=( (not A168) and a6767a );
a6769a <=( a6768a and a6763a );
a6773a <=( A298 and (not A269) );
a6774a <=( (not A267) and a6773a );
a6778a <=( A301 and A300 );
a6779a <=( (not A299) and a6778a );
a6780a <=( a6779a and a6774a );
a6783a <=( (not A169) and (not A170) );
a6787a <=( (not A166) and A167 );
a6788a <=( (not A168) and a6787a );
a6789a <=( a6788a and a6783a );
a6793a <=( A298 and (not A269) );
a6794a <=( (not A267) and a6793a );
a6798a <=( (not A302) and A300 );
a6799a <=( (not A299) and a6798a );
a6800a <=( a6799a and a6794a );
a6803a <=( (not A169) and (not A170) );
a6807a <=( (not A166) and A167 );
a6808a <=( (not A168) and a6807a );
a6809a <=( a6808a and a6803a );
a6813a <=( (not A298) and (not A269) );
a6814a <=( (not A267) and a6813a );
a6818a <=( A301 and A300 );
a6819a <=( A299 and a6818a );
a6820a <=( a6819a and a6814a );
a6823a <=( (not A169) and (not A170) );
a6827a <=( (not A166) and A167 );
a6828a <=( (not A168) and a6827a );
a6829a <=( a6828a and a6823a );
a6833a <=( (not A298) and (not A269) );
a6834a <=( (not A267) and a6833a );
a6838a <=( (not A302) and A300 );
a6839a <=( A299 and a6838a );
a6840a <=( a6839a and a6834a );
a6843a <=( (not A169) and (not A170) );
a6847a <=( (not A166) and A167 );
a6848a <=( (not A168) and a6847a );
a6849a <=( a6848a and a6843a );
a6853a <=( A298 and A266 );
a6854a <=( A265 and a6853a );
a6858a <=( A301 and A300 );
a6859a <=( (not A299) and a6858a );
a6860a <=( a6859a and a6854a );
a6863a <=( (not A169) and (not A170) );
a6867a <=( (not A166) and A167 );
a6868a <=( (not A168) and a6867a );
a6869a <=( a6868a and a6863a );
a6873a <=( A298 and A266 );
a6874a <=( A265 and a6873a );
a6878a <=( (not A302) and A300 );
a6879a <=( (not A299) and a6878a );
a6880a <=( a6879a and a6874a );
a6883a <=( (not A169) and (not A170) );
a6887a <=( (not A166) and A167 );
a6888a <=( (not A168) and a6887a );
a6889a <=( a6888a and a6883a );
a6893a <=( (not A298) and A266 );
a6894a <=( A265 and a6893a );
a6898a <=( A301 and A300 );
a6899a <=( A299 and a6898a );
a6900a <=( a6899a and a6894a );
a6903a <=( (not A169) and (not A170) );
a6907a <=( (not A166) and A167 );
a6908a <=( (not A168) and a6907a );
a6909a <=( a6908a and a6903a );
a6913a <=( (not A298) and A266 );
a6914a <=( A265 and a6913a );
a6918a <=( (not A302) and A300 );
a6919a <=( A299 and a6918a );
a6920a <=( a6919a and a6914a );
a6923a <=( (not A169) and (not A170) );
a6927a <=( (not A166) and A167 );
a6928a <=( (not A168) and a6927a );
a6929a <=( a6928a and a6923a );
a6933a <=( A267 and A266 );
a6934a <=( (not A265) and a6933a );
a6938a <=( A301 and (not A300) );
a6939a <=( A268 and a6938a );
a6940a <=( a6939a and a6934a );
a6943a <=( (not A169) and (not A170) );
a6947a <=( (not A166) and A167 );
a6948a <=( (not A168) and a6947a );
a6949a <=( a6948a and a6943a );
a6953a <=( A267 and A266 );
a6954a <=( (not A265) and a6953a );
a6958a <=( (not A302) and (not A300) );
a6959a <=( A268 and a6958a );
a6960a <=( a6959a and a6954a );
a6963a <=( (not A169) and (not A170) );
a6967a <=( (not A166) and A167 );
a6968a <=( (not A168) and a6967a );
a6969a <=( a6968a and a6963a );
a6973a <=( A267 and A266 );
a6974a <=( (not A265) and a6973a );
a6978a <=( A299 and A298 );
a6979a <=( A268 and a6978a );
a6980a <=( a6979a and a6974a );
a6983a <=( (not A169) and (not A170) );
a6987a <=( (not A166) and A167 );
a6988a <=( (not A168) and a6987a );
a6989a <=( a6988a and a6983a );
a6993a <=( A267 and A266 );
a6994a <=( (not A265) and a6993a );
a6998a <=( (not A299) and (not A298) );
a6999a <=( A268 and a6998a );
a7000a <=( a6999a and a6994a );
a7003a <=( (not A169) and (not A170) );
a7007a <=( (not A166) and A167 );
a7008a <=( (not A168) and a7007a );
a7009a <=( a7008a and a7003a );
a7013a <=( A267 and A266 );
a7014a <=( (not A265) and a7013a );
a7018a <=( A301 and (not A300) );
a7019a <=( (not A269) and a7018a );
a7020a <=( a7019a and a7014a );
a7023a <=( (not A169) and (not A170) );
a7027a <=( (not A166) and A167 );
a7028a <=( (not A168) and a7027a );
a7029a <=( a7028a and a7023a );
a7033a <=( A267 and A266 );
a7034a <=( (not A265) and a7033a );
a7038a <=( (not A302) and (not A300) );
a7039a <=( (not A269) and a7038a );
a7040a <=( a7039a and a7034a );
a7043a <=( (not A169) and (not A170) );
a7047a <=( (not A166) and A167 );
a7048a <=( (not A168) and a7047a );
a7049a <=( a7048a and a7043a );
a7053a <=( A267 and A266 );
a7054a <=( (not A265) and a7053a );
a7058a <=( A299 and A298 );
a7059a <=( (not A269) and a7058a );
a7060a <=( a7059a and a7054a );
a7063a <=( (not A169) and (not A170) );
a7067a <=( (not A166) and A167 );
a7068a <=( (not A168) and a7067a );
a7069a <=( a7068a and a7063a );
a7073a <=( A267 and A266 );
a7074a <=( (not A265) and a7073a );
a7078a <=( (not A299) and (not A298) );
a7079a <=( (not A269) and a7078a );
a7080a <=( a7079a and a7074a );
a7083a <=( (not A169) and (not A170) );
a7087a <=( (not A166) and A167 );
a7088a <=( (not A168) and a7087a );
a7089a <=( a7088a and a7083a );
a7093a <=( A267 and (not A266) );
a7094a <=( A265 and a7093a );
a7098a <=( A301 and (not A300) );
a7099a <=( A268 and a7098a );
a7100a <=( a7099a and a7094a );
a7103a <=( (not A169) and (not A170) );
a7107a <=( (not A166) and A167 );
a7108a <=( (not A168) and a7107a );
a7109a <=( a7108a and a7103a );
a7113a <=( A267 and (not A266) );
a7114a <=( A265 and a7113a );
a7118a <=( (not A302) and (not A300) );
a7119a <=( A268 and a7118a );
a7120a <=( a7119a and a7114a );
a7123a <=( (not A169) and (not A170) );
a7127a <=( (not A166) and A167 );
a7128a <=( (not A168) and a7127a );
a7129a <=( a7128a and a7123a );
a7133a <=( A267 and (not A266) );
a7134a <=( A265 and a7133a );
a7138a <=( A299 and A298 );
a7139a <=( A268 and a7138a );
a7140a <=( a7139a and a7134a );
a7143a <=( (not A169) and (not A170) );
a7147a <=( (not A166) and A167 );
a7148a <=( (not A168) and a7147a );
a7149a <=( a7148a and a7143a );
a7153a <=( A267 and (not A266) );
a7154a <=( A265 and a7153a );
a7158a <=( (not A299) and (not A298) );
a7159a <=( A268 and a7158a );
a7160a <=( a7159a and a7154a );
a7163a <=( (not A169) and (not A170) );
a7167a <=( (not A166) and A167 );
a7168a <=( (not A168) and a7167a );
a7169a <=( a7168a and a7163a );
a7173a <=( A267 and (not A266) );
a7174a <=( A265 and a7173a );
a7178a <=( A301 and (not A300) );
a7179a <=( (not A269) and a7178a );
a7180a <=( a7179a and a7174a );
a7183a <=( (not A169) and (not A170) );
a7187a <=( (not A166) and A167 );
a7188a <=( (not A168) and a7187a );
a7189a <=( a7188a and a7183a );
a7193a <=( A267 and (not A266) );
a7194a <=( A265 and a7193a );
a7198a <=( (not A302) and (not A300) );
a7199a <=( (not A269) and a7198a );
a7200a <=( a7199a and a7194a );
a7203a <=( (not A169) and (not A170) );
a7207a <=( (not A166) and A167 );
a7208a <=( (not A168) and a7207a );
a7209a <=( a7208a and a7203a );
a7213a <=( A267 and (not A266) );
a7214a <=( A265 and a7213a );
a7218a <=( A299 and A298 );
a7219a <=( (not A269) and a7218a );
a7220a <=( a7219a and a7214a );
a7223a <=( (not A169) and (not A170) );
a7227a <=( (not A166) and A167 );
a7228a <=( (not A168) and a7227a );
a7229a <=( a7228a and a7223a );
a7233a <=( A267 and (not A266) );
a7234a <=( A265 and a7233a );
a7238a <=( (not A299) and (not A298) );
a7239a <=( (not A269) and a7238a );
a7240a <=( a7239a and a7234a );
a7243a <=( (not A169) and (not A170) );
a7247a <=( (not A166) and A167 );
a7248a <=( (not A168) and a7247a );
a7249a <=( a7248a and a7243a );
a7253a <=( A298 and (not A266) );
a7254a <=( (not A265) and a7253a );
a7258a <=( A301 and A300 );
a7259a <=( (not A299) and a7258a );
a7260a <=( a7259a and a7254a );
a7263a <=( (not A169) and (not A170) );
a7267a <=( (not A166) and A167 );
a7268a <=( (not A168) and a7267a );
a7269a <=( a7268a and a7263a );
a7273a <=( A298 and (not A266) );
a7274a <=( (not A265) and a7273a );
a7278a <=( (not A302) and A300 );
a7279a <=( (not A299) and a7278a );
a7280a <=( a7279a and a7274a );
a7283a <=( (not A169) and (not A170) );
a7287a <=( (not A166) and A167 );
a7288a <=( (not A168) and a7287a );
a7289a <=( a7288a and a7283a );
a7293a <=( (not A298) and (not A266) );
a7294a <=( (not A265) and a7293a );
a7298a <=( A301 and A300 );
a7299a <=( A299 and a7298a );
a7300a <=( a7299a and a7294a );
a7303a <=( (not A169) and (not A170) );
a7307a <=( (not A166) and A167 );
a7308a <=( (not A168) and a7307a );
a7309a <=( a7308a and a7303a );
a7313a <=( (not A298) and (not A266) );
a7314a <=( (not A265) and a7313a );
a7318a <=( (not A302) and A300 );
a7319a <=( A299 and a7318a );
a7320a <=( a7319a and a7314a );
a7323a <=( (not A169) and (not A170) );
a7327a <=( A166 and (not A167) );
a7328a <=( (not A168) and a7327a );
a7329a <=( a7328a and a7323a );
a7333a <=( A298 and A268 );
a7334a <=( (not A267) and a7333a );
a7338a <=( A301 and A300 );
a7339a <=( (not A299) and a7338a );
a7340a <=( a7339a and a7334a );
a7343a <=( (not A169) and (not A170) );
a7347a <=( A166 and (not A167) );
a7348a <=( (not A168) and a7347a );
a7349a <=( a7348a and a7343a );
a7353a <=( A298 and A268 );
a7354a <=( (not A267) and a7353a );
a7358a <=( (not A302) and A300 );
a7359a <=( (not A299) and a7358a );
a7360a <=( a7359a and a7354a );
a7363a <=( (not A169) and (not A170) );
a7367a <=( A166 and (not A167) );
a7368a <=( (not A168) and a7367a );
a7369a <=( a7368a and a7363a );
a7373a <=( (not A298) and A268 );
a7374a <=( (not A267) and a7373a );
a7378a <=( A301 and A300 );
a7379a <=( A299 and a7378a );
a7380a <=( a7379a and a7374a );
a7383a <=( (not A169) and (not A170) );
a7387a <=( A166 and (not A167) );
a7388a <=( (not A168) and a7387a );
a7389a <=( a7388a and a7383a );
a7393a <=( (not A298) and A268 );
a7394a <=( (not A267) and a7393a );
a7398a <=( (not A302) and A300 );
a7399a <=( A299 and a7398a );
a7400a <=( a7399a and a7394a );
a7403a <=( (not A169) and (not A170) );
a7407a <=( A166 and (not A167) );
a7408a <=( (not A168) and a7407a );
a7409a <=( a7408a and a7403a );
a7413a <=( A298 and (not A269) );
a7414a <=( (not A267) and a7413a );
a7418a <=( A301 and A300 );
a7419a <=( (not A299) and a7418a );
a7420a <=( a7419a and a7414a );
a7423a <=( (not A169) and (not A170) );
a7427a <=( A166 and (not A167) );
a7428a <=( (not A168) and a7427a );
a7429a <=( a7428a and a7423a );
a7433a <=( A298 and (not A269) );
a7434a <=( (not A267) and a7433a );
a7438a <=( (not A302) and A300 );
a7439a <=( (not A299) and a7438a );
a7440a <=( a7439a and a7434a );
a7443a <=( (not A169) and (not A170) );
a7447a <=( A166 and (not A167) );
a7448a <=( (not A168) and a7447a );
a7449a <=( a7448a and a7443a );
a7453a <=( (not A298) and (not A269) );
a7454a <=( (not A267) and a7453a );
a7458a <=( A301 and A300 );
a7459a <=( A299 and a7458a );
a7460a <=( a7459a and a7454a );
a7463a <=( (not A169) and (not A170) );
a7467a <=( A166 and (not A167) );
a7468a <=( (not A168) and a7467a );
a7469a <=( a7468a and a7463a );
a7473a <=( (not A298) and (not A269) );
a7474a <=( (not A267) and a7473a );
a7478a <=( (not A302) and A300 );
a7479a <=( A299 and a7478a );
a7480a <=( a7479a and a7474a );
a7483a <=( (not A169) and (not A170) );
a7487a <=( A166 and (not A167) );
a7488a <=( (not A168) and a7487a );
a7489a <=( a7488a and a7483a );
a7493a <=( A298 and A266 );
a7494a <=( A265 and a7493a );
a7498a <=( A301 and A300 );
a7499a <=( (not A299) and a7498a );
a7500a <=( a7499a and a7494a );
a7503a <=( (not A169) and (not A170) );
a7507a <=( A166 and (not A167) );
a7508a <=( (not A168) and a7507a );
a7509a <=( a7508a and a7503a );
a7513a <=( A298 and A266 );
a7514a <=( A265 and a7513a );
a7518a <=( (not A302) and A300 );
a7519a <=( (not A299) and a7518a );
a7520a <=( a7519a and a7514a );
a7523a <=( (not A169) and (not A170) );
a7527a <=( A166 and (not A167) );
a7528a <=( (not A168) and a7527a );
a7529a <=( a7528a and a7523a );
a7533a <=( (not A298) and A266 );
a7534a <=( A265 and a7533a );
a7538a <=( A301 and A300 );
a7539a <=( A299 and a7538a );
a7540a <=( a7539a and a7534a );
a7543a <=( (not A169) and (not A170) );
a7547a <=( A166 and (not A167) );
a7548a <=( (not A168) and a7547a );
a7549a <=( a7548a and a7543a );
a7553a <=( (not A298) and A266 );
a7554a <=( A265 and a7553a );
a7558a <=( (not A302) and A300 );
a7559a <=( A299 and a7558a );
a7560a <=( a7559a and a7554a );
a7563a <=( (not A169) and (not A170) );
a7567a <=( A166 and (not A167) );
a7568a <=( (not A168) and a7567a );
a7569a <=( a7568a and a7563a );
a7573a <=( A267 and A266 );
a7574a <=( (not A265) and a7573a );
a7578a <=( A301 and (not A300) );
a7579a <=( A268 and a7578a );
a7580a <=( a7579a and a7574a );
a7583a <=( (not A169) and (not A170) );
a7587a <=( A166 and (not A167) );
a7588a <=( (not A168) and a7587a );
a7589a <=( a7588a and a7583a );
a7593a <=( A267 and A266 );
a7594a <=( (not A265) and a7593a );
a7598a <=( (not A302) and (not A300) );
a7599a <=( A268 and a7598a );
a7600a <=( a7599a and a7594a );
a7603a <=( (not A169) and (not A170) );
a7607a <=( A166 and (not A167) );
a7608a <=( (not A168) and a7607a );
a7609a <=( a7608a and a7603a );
a7613a <=( A267 and A266 );
a7614a <=( (not A265) and a7613a );
a7618a <=( A299 and A298 );
a7619a <=( A268 and a7618a );
a7620a <=( a7619a and a7614a );
a7623a <=( (not A169) and (not A170) );
a7627a <=( A166 and (not A167) );
a7628a <=( (not A168) and a7627a );
a7629a <=( a7628a and a7623a );
a7633a <=( A267 and A266 );
a7634a <=( (not A265) and a7633a );
a7638a <=( (not A299) and (not A298) );
a7639a <=( A268 and a7638a );
a7640a <=( a7639a and a7634a );
a7643a <=( (not A169) and (not A170) );
a7647a <=( A166 and (not A167) );
a7648a <=( (not A168) and a7647a );
a7649a <=( a7648a and a7643a );
a7653a <=( A267 and A266 );
a7654a <=( (not A265) and a7653a );
a7658a <=( A301 and (not A300) );
a7659a <=( (not A269) and a7658a );
a7660a <=( a7659a and a7654a );
a7663a <=( (not A169) and (not A170) );
a7667a <=( A166 and (not A167) );
a7668a <=( (not A168) and a7667a );
a7669a <=( a7668a and a7663a );
a7673a <=( A267 and A266 );
a7674a <=( (not A265) and a7673a );
a7678a <=( (not A302) and (not A300) );
a7679a <=( (not A269) and a7678a );
a7680a <=( a7679a and a7674a );
a7683a <=( (not A169) and (not A170) );
a7687a <=( A166 and (not A167) );
a7688a <=( (not A168) and a7687a );
a7689a <=( a7688a and a7683a );
a7693a <=( A267 and A266 );
a7694a <=( (not A265) and a7693a );
a7698a <=( A299 and A298 );
a7699a <=( (not A269) and a7698a );
a7700a <=( a7699a and a7694a );
a7703a <=( (not A169) and (not A170) );
a7707a <=( A166 and (not A167) );
a7708a <=( (not A168) and a7707a );
a7709a <=( a7708a and a7703a );
a7713a <=( A267 and A266 );
a7714a <=( (not A265) and a7713a );
a7718a <=( (not A299) and (not A298) );
a7719a <=( (not A269) and a7718a );
a7720a <=( a7719a and a7714a );
a7723a <=( (not A169) and (not A170) );
a7727a <=( A166 and (not A167) );
a7728a <=( (not A168) and a7727a );
a7729a <=( a7728a and a7723a );
a7733a <=( A267 and (not A266) );
a7734a <=( A265 and a7733a );
a7738a <=( A301 and (not A300) );
a7739a <=( A268 and a7738a );
a7740a <=( a7739a and a7734a );
a7743a <=( (not A169) and (not A170) );
a7747a <=( A166 and (not A167) );
a7748a <=( (not A168) and a7747a );
a7749a <=( a7748a and a7743a );
a7753a <=( A267 and (not A266) );
a7754a <=( A265 and a7753a );
a7758a <=( (not A302) and (not A300) );
a7759a <=( A268 and a7758a );
a7760a <=( a7759a and a7754a );
a7763a <=( (not A169) and (not A170) );
a7767a <=( A166 and (not A167) );
a7768a <=( (not A168) and a7767a );
a7769a <=( a7768a and a7763a );
a7773a <=( A267 and (not A266) );
a7774a <=( A265 and a7773a );
a7778a <=( A299 and A298 );
a7779a <=( A268 and a7778a );
a7780a <=( a7779a and a7774a );
a7783a <=( (not A169) and (not A170) );
a7787a <=( A166 and (not A167) );
a7788a <=( (not A168) and a7787a );
a7789a <=( a7788a and a7783a );
a7793a <=( A267 and (not A266) );
a7794a <=( A265 and a7793a );
a7798a <=( (not A299) and (not A298) );
a7799a <=( A268 and a7798a );
a7800a <=( a7799a and a7794a );
a7803a <=( (not A169) and (not A170) );
a7807a <=( A166 and (not A167) );
a7808a <=( (not A168) and a7807a );
a7809a <=( a7808a and a7803a );
a7813a <=( A267 and (not A266) );
a7814a <=( A265 and a7813a );
a7818a <=( A301 and (not A300) );
a7819a <=( (not A269) and a7818a );
a7820a <=( a7819a and a7814a );
a7823a <=( (not A169) and (not A170) );
a7827a <=( A166 and (not A167) );
a7828a <=( (not A168) and a7827a );
a7829a <=( a7828a and a7823a );
a7833a <=( A267 and (not A266) );
a7834a <=( A265 and a7833a );
a7838a <=( (not A302) and (not A300) );
a7839a <=( (not A269) and a7838a );
a7840a <=( a7839a and a7834a );
a7843a <=( (not A169) and (not A170) );
a7847a <=( A166 and (not A167) );
a7848a <=( (not A168) and a7847a );
a7849a <=( a7848a and a7843a );
a7853a <=( A267 and (not A266) );
a7854a <=( A265 and a7853a );
a7858a <=( A299 and A298 );
a7859a <=( (not A269) and a7858a );
a7860a <=( a7859a and a7854a );
a7863a <=( (not A169) and (not A170) );
a7867a <=( A166 and (not A167) );
a7868a <=( (not A168) and a7867a );
a7869a <=( a7868a and a7863a );
a7873a <=( A267 and (not A266) );
a7874a <=( A265 and a7873a );
a7878a <=( (not A299) and (not A298) );
a7879a <=( (not A269) and a7878a );
a7880a <=( a7879a and a7874a );
a7883a <=( (not A169) and (not A170) );
a7887a <=( A166 and (not A167) );
a7888a <=( (not A168) and a7887a );
a7889a <=( a7888a and a7883a );
a7893a <=( A298 and (not A266) );
a7894a <=( (not A265) and a7893a );
a7898a <=( A301 and A300 );
a7899a <=( (not A299) and a7898a );
a7900a <=( a7899a and a7894a );
a7903a <=( (not A169) and (not A170) );
a7907a <=( A166 and (not A167) );
a7908a <=( (not A168) and a7907a );
a7909a <=( a7908a and a7903a );
a7913a <=( A298 and (not A266) );
a7914a <=( (not A265) and a7913a );
a7918a <=( (not A302) and A300 );
a7919a <=( (not A299) and a7918a );
a7920a <=( a7919a and a7914a );
a7923a <=( (not A169) and (not A170) );
a7927a <=( A166 and (not A167) );
a7928a <=( (not A168) and a7927a );
a7929a <=( a7928a and a7923a );
a7933a <=( (not A298) and (not A266) );
a7934a <=( (not A265) and a7933a );
a7938a <=( A301 and A300 );
a7939a <=( A299 and a7938a );
a7940a <=( a7939a and a7934a );
a7943a <=( (not A169) and (not A170) );
a7947a <=( A166 and (not A167) );
a7948a <=( (not A168) and a7947a );
a7949a <=( a7948a and a7943a );
a7953a <=( (not A298) and (not A266) );
a7954a <=( (not A265) and a7953a );
a7958a <=( (not A302) and A300 );
a7959a <=( A299 and a7958a );
a7960a <=( a7959a and a7954a );
a7964a <=( A167 and A168 );
a7965a <=( A170 and a7964a );
a7969a <=( (not A268) and A267 );
a7970a <=( (not A166) and a7969a );
a7971a <=( a7970a and a7965a );
a7975a <=( (not A299) and A298 );
a7976a <=( A269 and a7975a );
a7980a <=( A302 and (not A301) );
a7981a <=( (not A300) and a7980a );
a7982a <=( a7981a and a7976a );
a7986a <=( A167 and A168 );
a7987a <=( A170 and a7986a );
a7991a <=( (not A268) and A267 );
a7992a <=( (not A166) and a7991a );
a7993a <=( a7992a and a7987a );
a7997a <=( A299 and (not A298) );
a7998a <=( A269 and a7997a );
a8002a <=( A302 and (not A301) );
a8003a <=( (not A300) and a8002a );
a8004a <=( a8003a and a7998a );
a8008a <=( A167 and A168 );
a8009a <=( A170 and a8008a );
a8013a <=( A266 and (not A265) );
a8014a <=( (not A166) and a8013a );
a8015a <=( a8014a and a8009a );
a8019a <=( A269 and (not A268) );
a8020a <=( (not A267) and a8019a );
a8024a <=( A302 and (not A301) );
a8025a <=( A300 and a8024a );
a8026a <=( a8025a and a8020a );
a8030a <=( A167 and A168 );
a8031a <=( A170 and a8030a );
a8035a <=( (not A266) and A265 );
a8036a <=( (not A166) and a8035a );
a8037a <=( a8036a and a8031a );
a8041a <=( A269 and (not A268) );
a8042a <=( (not A267) and a8041a );
a8046a <=( A302 and (not A301) );
a8047a <=( A300 and a8046a );
a8048a <=( a8047a and a8042a );
a8052a <=( (not A167) and A168 );
a8053a <=( A170 and a8052a );
a8057a <=( (not A268) and A267 );
a8058a <=( A166 and a8057a );
a8059a <=( a8058a and a8053a );
a8063a <=( (not A299) and A298 );
a8064a <=( A269 and a8063a );
a8068a <=( A302 and (not A301) );
a8069a <=( (not A300) and a8068a );
a8070a <=( a8069a and a8064a );
a8074a <=( (not A167) and A168 );
a8075a <=( A170 and a8074a );
a8079a <=( (not A268) and A267 );
a8080a <=( A166 and a8079a );
a8081a <=( a8080a and a8075a );
a8085a <=( A299 and (not A298) );
a8086a <=( A269 and a8085a );
a8090a <=( A302 and (not A301) );
a8091a <=( (not A300) and a8090a );
a8092a <=( a8091a and a8086a );
a8096a <=( (not A167) and A168 );
a8097a <=( A170 and a8096a );
a8101a <=( A266 and (not A265) );
a8102a <=( A166 and a8101a );
a8103a <=( a8102a and a8097a );
a8107a <=( A269 and (not A268) );
a8108a <=( (not A267) and a8107a );
a8112a <=( A302 and (not A301) );
a8113a <=( A300 and a8112a );
a8114a <=( a8113a and a8108a );
a8118a <=( (not A167) and A168 );
a8119a <=( A170 and a8118a );
a8123a <=( (not A266) and A265 );
a8124a <=( A166 and a8123a );
a8125a <=( a8124a and a8119a );
a8129a <=( A269 and (not A268) );
a8130a <=( (not A267) and a8129a );
a8134a <=( A302 and (not A301) );
a8135a <=( A300 and a8134a );
a8136a <=( a8135a and a8130a );
a8140a <=( A167 and A168 );
a8141a <=( A169 and a8140a );
a8145a <=( (not A268) and A267 );
a8146a <=( (not A166) and a8145a );
a8147a <=( a8146a and a8141a );
a8151a <=( (not A299) and A298 );
a8152a <=( A269 and a8151a );
a8156a <=( A302 and (not A301) );
a8157a <=( (not A300) and a8156a );
a8158a <=( a8157a and a8152a );
a8162a <=( A167 and A168 );
a8163a <=( A169 and a8162a );
a8167a <=( (not A268) and A267 );
a8168a <=( (not A166) and a8167a );
a8169a <=( a8168a and a8163a );
a8173a <=( A299 and (not A298) );
a8174a <=( A269 and a8173a );
a8178a <=( A302 and (not A301) );
a8179a <=( (not A300) and a8178a );
a8180a <=( a8179a and a8174a );
a8184a <=( A167 and A168 );
a8185a <=( A169 and a8184a );
a8189a <=( A266 and (not A265) );
a8190a <=( (not A166) and a8189a );
a8191a <=( a8190a and a8185a );
a8195a <=( A269 and (not A268) );
a8196a <=( (not A267) and a8195a );
a8200a <=( A302 and (not A301) );
a8201a <=( A300 and a8200a );
a8202a <=( a8201a and a8196a );
a8206a <=( A167 and A168 );
a8207a <=( A169 and a8206a );
a8211a <=( (not A266) and A265 );
a8212a <=( (not A166) and a8211a );
a8213a <=( a8212a and a8207a );
a8217a <=( A269 and (not A268) );
a8218a <=( (not A267) and a8217a );
a8222a <=( A302 and (not A301) );
a8223a <=( A300 and a8222a );
a8224a <=( a8223a and a8218a );
a8228a <=( (not A167) and A168 );
a8229a <=( A169 and a8228a );
a8233a <=( (not A268) and A267 );
a8234a <=( A166 and a8233a );
a8235a <=( a8234a and a8229a );
a8239a <=( (not A299) and A298 );
a8240a <=( A269 and a8239a );
a8244a <=( A302 and (not A301) );
a8245a <=( (not A300) and a8244a );
a8246a <=( a8245a and a8240a );
a8250a <=( (not A167) and A168 );
a8251a <=( A169 and a8250a );
a8255a <=( (not A268) and A267 );
a8256a <=( A166 and a8255a );
a8257a <=( a8256a and a8251a );
a8261a <=( A299 and (not A298) );
a8262a <=( A269 and a8261a );
a8266a <=( A302 and (not A301) );
a8267a <=( (not A300) and a8266a );
a8268a <=( a8267a and a8262a );
a8272a <=( (not A167) and A168 );
a8273a <=( A169 and a8272a );
a8277a <=( A266 and (not A265) );
a8278a <=( A166 and a8277a );
a8279a <=( a8278a and a8273a );
a8283a <=( A269 and (not A268) );
a8284a <=( (not A267) and a8283a );
a8288a <=( A302 and (not A301) );
a8289a <=( A300 and a8288a );
a8290a <=( a8289a and a8284a );
a8294a <=( (not A167) and A168 );
a8295a <=( A169 and a8294a );
a8299a <=( (not A266) and A265 );
a8300a <=( A166 and a8299a );
a8301a <=( a8300a and a8295a );
a8305a <=( A269 and (not A268) );
a8306a <=( (not A267) and a8305a );
a8310a <=( A302 and (not A301) );
a8311a <=( A300 and a8310a );
a8312a <=( a8311a and a8306a );
a8316a <=( (not A168) and (not A169) );
a8317a <=( (not A170) and a8316a );
a8321a <=( A267 and (not A166) );
a8322a <=( A167 and a8321a );
a8323a <=( a8322a and a8317a );
a8327a <=( A298 and A269 );
a8328a <=( (not A268) and a8327a );
a8332a <=( A301 and A300 );
a8333a <=( (not A299) and a8332a );
a8334a <=( a8333a and a8328a );
a8338a <=( (not A168) and (not A169) );
a8339a <=( (not A170) and a8338a );
a8343a <=( A267 and (not A166) );
a8344a <=( A167 and a8343a );
a8345a <=( a8344a and a8339a );
a8349a <=( A298 and A269 );
a8350a <=( (not A268) and a8349a );
a8354a <=( (not A302) and A300 );
a8355a <=( (not A299) and a8354a );
a8356a <=( a8355a and a8350a );
a8360a <=( (not A168) and (not A169) );
a8361a <=( (not A170) and a8360a );
a8365a <=( A267 and (not A166) );
a8366a <=( A167 and a8365a );
a8367a <=( a8366a and a8361a );
a8371a <=( (not A298) and A269 );
a8372a <=( (not A268) and a8371a );
a8376a <=( A301 and A300 );
a8377a <=( A299 and a8376a );
a8378a <=( a8377a and a8372a );
a8382a <=( (not A168) and (not A169) );
a8383a <=( (not A170) and a8382a );
a8387a <=( A267 and (not A166) );
a8388a <=( A167 and a8387a );
a8389a <=( a8388a and a8383a );
a8393a <=( (not A298) and A269 );
a8394a <=( (not A268) and a8393a );
a8398a <=( (not A302) and A300 );
a8399a <=( A299 and a8398a );
a8400a <=( a8399a and a8394a );
a8404a <=( (not A168) and (not A169) );
a8405a <=( (not A170) and a8404a );
a8409a <=( (not A267) and (not A166) );
a8410a <=( A167 and a8409a );
a8411a <=( a8410a and a8405a );
a8415a <=( (not A299) and A298 );
a8416a <=( A268 and a8415a );
a8420a <=( A302 and (not A301) );
a8421a <=( (not A300) and a8420a );
a8422a <=( a8421a and a8416a );
a8426a <=( (not A168) and (not A169) );
a8427a <=( (not A170) and a8426a );
a8431a <=( (not A267) and (not A166) );
a8432a <=( A167 and a8431a );
a8433a <=( a8432a and a8427a );
a8437a <=( A299 and (not A298) );
a8438a <=( A268 and a8437a );
a8442a <=( A302 and (not A301) );
a8443a <=( (not A300) and a8442a );
a8444a <=( a8443a and a8438a );
a8448a <=( (not A168) and (not A169) );
a8449a <=( (not A170) and a8448a );
a8453a <=( (not A267) and (not A166) );
a8454a <=( A167 and a8453a );
a8455a <=( a8454a and a8449a );
a8459a <=( (not A299) and A298 );
a8460a <=( (not A269) and a8459a );
a8464a <=( A302 and (not A301) );
a8465a <=( (not A300) and a8464a );
a8466a <=( a8465a and a8460a );
a8470a <=( (not A168) and (not A169) );
a8471a <=( (not A170) and a8470a );
a8475a <=( (not A267) and (not A166) );
a8476a <=( A167 and a8475a );
a8477a <=( a8476a and a8471a );
a8481a <=( A299 and (not A298) );
a8482a <=( (not A269) and a8481a );
a8486a <=( A302 and (not A301) );
a8487a <=( (not A300) and a8486a );
a8488a <=( a8487a and a8482a );
a8492a <=( (not A168) and (not A169) );
a8493a <=( (not A170) and a8492a );
a8497a <=( A265 and (not A166) );
a8498a <=( A167 and a8497a );
a8499a <=( a8498a and a8493a );
a8503a <=( (not A299) and A298 );
a8504a <=( A266 and a8503a );
a8508a <=( A302 and (not A301) );
a8509a <=( (not A300) and a8508a );
a8510a <=( a8509a and a8504a );
a8514a <=( (not A168) and (not A169) );
a8515a <=( (not A170) and a8514a );
a8519a <=( A265 and (not A166) );
a8520a <=( A167 and a8519a );
a8521a <=( a8520a and a8515a );
a8525a <=( A299 and (not A298) );
a8526a <=( A266 and a8525a );
a8530a <=( A302 and (not A301) );
a8531a <=( (not A300) and a8530a );
a8532a <=( a8531a and a8526a );
a8536a <=( (not A168) and (not A169) );
a8537a <=( (not A170) and a8536a );
a8541a <=( (not A265) and (not A166) );
a8542a <=( A167 and a8541a );
a8543a <=( a8542a and a8537a );
a8547a <=( A268 and A267 );
a8548a <=( A266 and a8547a );
a8552a <=( A302 and (not A301) );
a8553a <=( A300 and a8552a );
a8554a <=( a8553a and a8548a );
a8558a <=( (not A168) and (not A169) );
a8559a <=( (not A170) and a8558a );
a8563a <=( (not A265) and (not A166) );
a8564a <=( A167 and a8563a );
a8565a <=( a8564a and a8559a );
a8569a <=( (not A269) and A267 );
a8570a <=( A266 and a8569a );
a8574a <=( A302 and (not A301) );
a8575a <=( A300 and a8574a );
a8576a <=( a8575a and a8570a );
a8580a <=( (not A168) and (not A169) );
a8581a <=( (not A170) and a8580a );
a8585a <=( (not A265) and (not A166) );
a8586a <=( A167 and a8585a );
a8587a <=( a8586a and a8581a );
a8591a <=( (not A268) and (not A267) );
a8592a <=( A266 and a8591a );
a8596a <=( A301 and (not A300) );
a8597a <=( A269 and a8596a );
a8598a <=( a8597a and a8592a );
a8602a <=( (not A168) and (not A169) );
a8603a <=( (not A170) and a8602a );
a8607a <=( (not A265) and (not A166) );
a8608a <=( A167 and a8607a );
a8609a <=( a8608a and a8603a );
a8613a <=( (not A268) and (not A267) );
a8614a <=( A266 and a8613a );
a8618a <=( (not A302) and (not A300) );
a8619a <=( A269 and a8618a );
a8620a <=( a8619a and a8614a );
a8624a <=( (not A168) and (not A169) );
a8625a <=( (not A170) and a8624a );
a8629a <=( (not A265) and (not A166) );
a8630a <=( A167 and a8629a );
a8631a <=( a8630a and a8625a );
a8635a <=( (not A268) and (not A267) );
a8636a <=( A266 and a8635a );
a8640a <=( A299 and A298 );
a8641a <=( A269 and a8640a );
a8642a <=( a8641a and a8636a );
a8646a <=( (not A168) and (not A169) );
a8647a <=( (not A170) and a8646a );
a8651a <=( (not A265) and (not A166) );
a8652a <=( A167 and a8651a );
a8653a <=( a8652a and a8647a );
a8657a <=( (not A268) and (not A267) );
a8658a <=( A266 and a8657a );
a8662a <=( (not A299) and (not A298) );
a8663a <=( A269 and a8662a );
a8664a <=( a8663a and a8658a );
a8668a <=( (not A168) and (not A169) );
a8669a <=( (not A170) and a8668a );
a8673a <=( A265 and (not A166) );
a8674a <=( A167 and a8673a );
a8675a <=( a8674a and a8669a );
a8679a <=( A268 and A267 );
a8680a <=( (not A266) and a8679a );
a8684a <=( A302 and (not A301) );
a8685a <=( A300 and a8684a );
a8686a <=( a8685a and a8680a );
a8690a <=( (not A168) and (not A169) );
a8691a <=( (not A170) and a8690a );
a8695a <=( A265 and (not A166) );
a8696a <=( A167 and a8695a );
a8697a <=( a8696a and a8691a );
a8701a <=( (not A269) and A267 );
a8702a <=( (not A266) and a8701a );
a8706a <=( A302 and (not A301) );
a8707a <=( A300 and a8706a );
a8708a <=( a8707a and a8702a );
a8712a <=( (not A168) and (not A169) );
a8713a <=( (not A170) and a8712a );
a8717a <=( A265 and (not A166) );
a8718a <=( A167 and a8717a );
a8719a <=( a8718a and a8713a );
a8723a <=( (not A268) and (not A267) );
a8724a <=( (not A266) and a8723a );
a8728a <=( A301 and (not A300) );
a8729a <=( A269 and a8728a );
a8730a <=( a8729a and a8724a );
a8734a <=( (not A168) and (not A169) );
a8735a <=( (not A170) and a8734a );
a8739a <=( A265 and (not A166) );
a8740a <=( A167 and a8739a );
a8741a <=( a8740a and a8735a );
a8745a <=( (not A268) and (not A267) );
a8746a <=( (not A266) and a8745a );
a8750a <=( (not A302) and (not A300) );
a8751a <=( A269 and a8750a );
a8752a <=( a8751a and a8746a );
a8756a <=( (not A168) and (not A169) );
a8757a <=( (not A170) and a8756a );
a8761a <=( A265 and (not A166) );
a8762a <=( A167 and a8761a );
a8763a <=( a8762a and a8757a );
a8767a <=( (not A268) and (not A267) );
a8768a <=( (not A266) and a8767a );
a8772a <=( A299 and A298 );
a8773a <=( A269 and a8772a );
a8774a <=( a8773a and a8768a );
a8778a <=( (not A168) and (not A169) );
a8779a <=( (not A170) and a8778a );
a8783a <=( A265 and (not A166) );
a8784a <=( A167 and a8783a );
a8785a <=( a8784a and a8779a );
a8789a <=( (not A268) and (not A267) );
a8790a <=( (not A266) and a8789a );
a8794a <=( (not A299) and (not A298) );
a8795a <=( A269 and a8794a );
a8796a <=( a8795a and a8790a );
a8800a <=( (not A168) and (not A169) );
a8801a <=( (not A170) and a8800a );
a8805a <=( (not A265) and (not A166) );
a8806a <=( A167 and a8805a );
a8807a <=( a8806a and a8801a );
a8811a <=( (not A299) and A298 );
a8812a <=( (not A266) and a8811a );
a8816a <=( A302 and (not A301) );
a8817a <=( (not A300) and a8816a );
a8818a <=( a8817a and a8812a );
a8822a <=( (not A168) and (not A169) );
a8823a <=( (not A170) and a8822a );
a8827a <=( (not A265) and (not A166) );
a8828a <=( A167 and a8827a );
a8829a <=( a8828a and a8823a );
a8833a <=( A299 and (not A298) );
a8834a <=( (not A266) and a8833a );
a8838a <=( A302 and (not A301) );
a8839a <=( (not A300) and a8838a );
a8840a <=( a8839a and a8834a );
a8844a <=( (not A168) and (not A169) );
a8845a <=( (not A170) and a8844a );
a8849a <=( A267 and A166 );
a8850a <=( (not A167) and a8849a );
a8851a <=( a8850a and a8845a );
a8855a <=( A298 and A269 );
a8856a <=( (not A268) and a8855a );
a8860a <=( A301 and A300 );
a8861a <=( (not A299) and a8860a );
a8862a <=( a8861a and a8856a );
a8866a <=( (not A168) and (not A169) );
a8867a <=( (not A170) and a8866a );
a8871a <=( A267 and A166 );
a8872a <=( (not A167) and a8871a );
a8873a <=( a8872a and a8867a );
a8877a <=( A298 and A269 );
a8878a <=( (not A268) and a8877a );
a8882a <=( (not A302) and A300 );
a8883a <=( (not A299) and a8882a );
a8884a <=( a8883a and a8878a );
a8888a <=( (not A168) and (not A169) );
a8889a <=( (not A170) and a8888a );
a8893a <=( A267 and A166 );
a8894a <=( (not A167) and a8893a );
a8895a <=( a8894a and a8889a );
a8899a <=( (not A298) and A269 );
a8900a <=( (not A268) and a8899a );
a8904a <=( A301 and A300 );
a8905a <=( A299 and a8904a );
a8906a <=( a8905a and a8900a );
a8910a <=( (not A168) and (not A169) );
a8911a <=( (not A170) and a8910a );
a8915a <=( A267 and A166 );
a8916a <=( (not A167) and a8915a );
a8917a <=( a8916a and a8911a );
a8921a <=( (not A298) and A269 );
a8922a <=( (not A268) and a8921a );
a8926a <=( (not A302) and A300 );
a8927a <=( A299 and a8926a );
a8928a <=( a8927a and a8922a );
a8932a <=( (not A168) and (not A169) );
a8933a <=( (not A170) and a8932a );
a8937a <=( (not A267) and A166 );
a8938a <=( (not A167) and a8937a );
a8939a <=( a8938a and a8933a );
a8943a <=( (not A299) and A298 );
a8944a <=( A268 and a8943a );
a8948a <=( A302 and (not A301) );
a8949a <=( (not A300) and a8948a );
a8950a <=( a8949a and a8944a );
a8954a <=( (not A168) and (not A169) );
a8955a <=( (not A170) and a8954a );
a8959a <=( (not A267) and A166 );
a8960a <=( (not A167) and a8959a );
a8961a <=( a8960a and a8955a );
a8965a <=( A299 and (not A298) );
a8966a <=( A268 and a8965a );
a8970a <=( A302 and (not A301) );
a8971a <=( (not A300) and a8970a );
a8972a <=( a8971a and a8966a );
a8976a <=( (not A168) and (not A169) );
a8977a <=( (not A170) and a8976a );
a8981a <=( (not A267) and A166 );
a8982a <=( (not A167) and a8981a );
a8983a <=( a8982a and a8977a );
a8987a <=( (not A299) and A298 );
a8988a <=( (not A269) and a8987a );
a8992a <=( A302 and (not A301) );
a8993a <=( (not A300) and a8992a );
a8994a <=( a8993a and a8988a );
a8998a <=( (not A168) and (not A169) );
a8999a <=( (not A170) and a8998a );
a9003a <=( (not A267) and A166 );
a9004a <=( (not A167) and a9003a );
a9005a <=( a9004a and a8999a );
a9009a <=( A299 and (not A298) );
a9010a <=( (not A269) and a9009a );
a9014a <=( A302 and (not A301) );
a9015a <=( (not A300) and a9014a );
a9016a <=( a9015a and a9010a );
a9020a <=( (not A168) and (not A169) );
a9021a <=( (not A170) and a9020a );
a9025a <=( A265 and A166 );
a9026a <=( (not A167) and a9025a );
a9027a <=( a9026a and a9021a );
a9031a <=( (not A299) and A298 );
a9032a <=( A266 and a9031a );
a9036a <=( A302 and (not A301) );
a9037a <=( (not A300) and a9036a );
a9038a <=( a9037a and a9032a );
a9042a <=( (not A168) and (not A169) );
a9043a <=( (not A170) and a9042a );
a9047a <=( A265 and A166 );
a9048a <=( (not A167) and a9047a );
a9049a <=( a9048a and a9043a );
a9053a <=( A299 and (not A298) );
a9054a <=( A266 and a9053a );
a9058a <=( A302 and (not A301) );
a9059a <=( (not A300) and a9058a );
a9060a <=( a9059a and a9054a );
a9064a <=( (not A168) and (not A169) );
a9065a <=( (not A170) and a9064a );
a9069a <=( (not A265) and A166 );
a9070a <=( (not A167) and a9069a );
a9071a <=( a9070a and a9065a );
a9075a <=( A268 and A267 );
a9076a <=( A266 and a9075a );
a9080a <=( A302 and (not A301) );
a9081a <=( A300 and a9080a );
a9082a <=( a9081a and a9076a );
a9086a <=( (not A168) and (not A169) );
a9087a <=( (not A170) and a9086a );
a9091a <=( (not A265) and A166 );
a9092a <=( (not A167) and a9091a );
a9093a <=( a9092a and a9087a );
a9097a <=( (not A269) and A267 );
a9098a <=( A266 and a9097a );
a9102a <=( A302 and (not A301) );
a9103a <=( A300 and a9102a );
a9104a <=( a9103a and a9098a );
a9108a <=( (not A168) and (not A169) );
a9109a <=( (not A170) and a9108a );
a9113a <=( (not A265) and A166 );
a9114a <=( (not A167) and a9113a );
a9115a <=( a9114a and a9109a );
a9119a <=( (not A268) and (not A267) );
a9120a <=( A266 and a9119a );
a9124a <=( A301 and (not A300) );
a9125a <=( A269 and a9124a );
a9126a <=( a9125a and a9120a );
a9130a <=( (not A168) and (not A169) );
a9131a <=( (not A170) and a9130a );
a9135a <=( (not A265) and A166 );
a9136a <=( (not A167) and a9135a );
a9137a <=( a9136a and a9131a );
a9141a <=( (not A268) and (not A267) );
a9142a <=( A266 and a9141a );
a9146a <=( (not A302) and (not A300) );
a9147a <=( A269 and a9146a );
a9148a <=( a9147a and a9142a );
a9152a <=( (not A168) and (not A169) );
a9153a <=( (not A170) and a9152a );
a9157a <=( (not A265) and A166 );
a9158a <=( (not A167) and a9157a );
a9159a <=( a9158a and a9153a );
a9163a <=( (not A268) and (not A267) );
a9164a <=( A266 and a9163a );
a9168a <=( A299 and A298 );
a9169a <=( A269 and a9168a );
a9170a <=( a9169a and a9164a );
a9174a <=( (not A168) and (not A169) );
a9175a <=( (not A170) and a9174a );
a9179a <=( (not A265) and A166 );
a9180a <=( (not A167) and a9179a );
a9181a <=( a9180a and a9175a );
a9185a <=( (not A268) and (not A267) );
a9186a <=( A266 and a9185a );
a9190a <=( (not A299) and (not A298) );
a9191a <=( A269 and a9190a );
a9192a <=( a9191a and a9186a );
a9196a <=( (not A168) and (not A169) );
a9197a <=( (not A170) and a9196a );
a9201a <=( A265 and A166 );
a9202a <=( (not A167) and a9201a );
a9203a <=( a9202a and a9197a );
a9207a <=( A268 and A267 );
a9208a <=( (not A266) and a9207a );
a9212a <=( A302 and (not A301) );
a9213a <=( A300 and a9212a );
a9214a <=( a9213a and a9208a );
a9218a <=( (not A168) and (not A169) );
a9219a <=( (not A170) and a9218a );
a9223a <=( A265 and A166 );
a9224a <=( (not A167) and a9223a );
a9225a <=( a9224a and a9219a );
a9229a <=( (not A269) and A267 );
a9230a <=( (not A266) and a9229a );
a9234a <=( A302 and (not A301) );
a9235a <=( A300 and a9234a );
a9236a <=( a9235a and a9230a );
a9240a <=( (not A168) and (not A169) );
a9241a <=( (not A170) and a9240a );
a9245a <=( A265 and A166 );
a9246a <=( (not A167) and a9245a );
a9247a <=( a9246a and a9241a );
a9251a <=( (not A268) and (not A267) );
a9252a <=( (not A266) and a9251a );
a9256a <=( A301 and (not A300) );
a9257a <=( A269 and a9256a );
a9258a <=( a9257a and a9252a );
a9262a <=( (not A168) and (not A169) );
a9263a <=( (not A170) and a9262a );
a9267a <=( A265 and A166 );
a9268a <=( (not A167) and a9267a );
a9269a <=( a9268a and a9263a );
a9273a <=( (not A268) and (not A267) );
a9274a <=( (not A266) and a9273a );
a9278a <=( (not A302) and (not A300) );
a9279a <=( A269 and a9278a );
a9280a <=( a9279a and a9274a );
a9284a <=( (not A168) and (not A169) );
a9285a <=( (not A170) and a9284a );
a9289a <=( A265 and A166 );
a9290a <=( (not A167) and a9289a );
a9291a <=( a9290a and a9285a );
a9295a <=( (not A268) and (not A267) );
a9296a <=( (not A266) and a9295a );
a9300a <=( A299 and A298 );
a9301a <=( A269 and a9300a );
a9302a <=( a9301a and a9296a );
a9306a <=( (not A168) and (not A169) );
a9307a <=( (not A170) and a9306a );
a9311a <=( A265 and A166 );
a9312a <=( (not A167) and a9311a );
a9313a <=( a9312a and a9307a );
a9317a <=( (not A268) and (not A267) );
a9318a <=( (not A266) and a9317a );
a9322a <=( (not A299) and (not A298) );
a9323a <=( A269 and a9322a );
a9324a <=( a9323a and a9318a );
a9328a <=( (not A168) and (not A169) );
a9329a <=( (not A170) and a9328a );
a9333a <=( (not A265) and A166 );
a9334a <=( (not A167) and a9333a );
a9335a <=( a9334a and a9329a );
a9339a <=( (not A299) and A298 );
a9340a <=( (not A266) and a9339a );
a9344a <=( A302 and (not A301) );
a9345a <=( (not A300) and a9344a );
a9346a <=( a9345a and a9340a );
a9350a <=( (not A168) and (not A169) );
a9351a <=( (not A170) and a9350a );
a9355a <=( (not A265) and A166 );
a9356a <=( (not A167) and a9355a );
a9357a <=( a9356a and a9351a );
a9361a <=( A299 and (not A298) );
a9362a <=( (not A266) and a9361a );
a9366a <=( A302 and (not A301) );
a9367a <=( (not A300) and a9366a );
a9368a <=( a9367a and a9362a );
a9372a <=( (not A168) and (not A169) );
a9373a <=( (not A170) and a9372a );
a9377a <=( A267 and (not A166) );
a9378a <=( A167 and a9377a );
a9379a <=( a9378a and a9373a );
a9383a <=( A298 and A269 );
a9384a <=( (not A268) and a9383a );
a9387a <=( (not A300) and (not A299) );
a9390a <=( A302 and (not A301) );
a9391a <=( a9390a and a9387a );
a9392a <=( a9391a and a9384a );
a9396a <=( (not A168) and (not A169) );
a9397a <=( (not A170) and a9396a );
a9401a <=( A267 and (not A166) );
a9402a <=( A167 and a9401a );
a9403a <=( a9402a and a9397a );
a9407a <=( (not A298) and A269 );
a9408a <=( (not A268) and a9407a );
a9411a <=( (not A300) and A299 );
a9414a <=( A302 and (not A301) );
a9415a <=( a9414a and a9411a );
a9416a <=( a9415a and a9408a );
a9420a <=( (not A168) and (not A169) );
a9421a <=( (not A170) and a9420a );
a9425a <=( (not A265) and (not A166) );
a9426a <=( A167 and a9425a );
a9427a <=( a9426a and a9421a );
a9431a <=( (not A268) and (not A267) );
a9432a <=( A266 and a9431a );
a9435a <=( A300 and A269 );
a9438a <=( A302 and (not A301) );
a9439a <=( a9438a and a9435a );
a9440a <=( a9439a and a9432a );
a9444a <=( (not A168) and (not A169) );
a9445a <=( (not A170) and a9444a );
a9449a <=( A265 and (not A166) );
a9450a <=( A167 and a9449a );
a9451a <=( a9450a and a9445a );
a9455a <=( (not A268) and (not A267) );
a9456a <=( (not A266) and a9455a );
a9459a <=( A300 and A269 );
a9462a <=( A302 and (not A301) );
a9463a <=( a9462a and a9459a );
a9464a <=( a9463a and a9456a );
a9468a <=( (not A168) and (not A169) );
a9469a <=( (not A170) and a9468a );
a9473a <=( A267 and A166 );
a9474a <=( (not A167) and a9473a );
a9475a <=( a9474a and a9469a );
a9479a <=( A298 and A269 );
a9480a <=( (not A268) and a9479a );
a9483a <=( (not A300) and (not A299) );
a9486a <=( A302 and (not A301) );
a9487a <=( a9486a and a9483a );
a9488a <=( a9487a and a9480a );
a9492a <=( (not A168) and (not A169) );
a9493a <=( (not A170) and a9492a );
a9497a <=( A267 and A166 );
a9498a <=( (not A167) and a9497a );
a9499a <=( a9498a and a9493a );
a9503a <=( (not A298) and A269 );
a9504a <=( (not A268) and a9503a );
a9507a <=( (not A300) and A299 );
a9510a <=( A302 and (not A301) );
a9511a <=( a9510a and a9507a );
a9512a <=( a9511a and a9504a );
a9516a <=( (not A168) and (not A169) );
a9517a <=( (not A170) and a9516a );
a9521a <=( (not A265) and A166 );
a9522a <=( (not A167) and a9521a );
a9523a <=( a9522a and a9517a );
a9527a <=( (not A268) and (not A267) );
a9528a <=( A266 and a9527a );
a9531a <=( A300 and A269 );
a9534a <=( A302 and (not A301) );
a9535a <=( a9534a and a9531a );
a9536a <=( a9535a and a9528a );
a9540a <=( (not A168) and (not A169) );
a9541a <=( (not A170) and a9540a );
a9545a <=( A265 and A166 );
a9546a <=( (not A167) and a9545a );
a9547a <=( a9546a and a9541a );
a9551a <=( (not A268) and (not A267) );
a9552a <=( (not A266) and a9551a );
a9555a <=( A300 and A269 );
a9558a <=( A302 and (not A301) );
a9559a <=( a9558a and a9555a );
a9560a <=( a9559a and a9552a );
end x25_23x_behav;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: l2uart
-- File: l2uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Asynchronous UART originally developed for LEON2.
-- Implements 8-bit data frame with one stop-bit.
-- Programmable options:
-- * parity bit (on/off)
-- * parity polarity (odd/even)
-- * baud-rate (12-bit programmable divider)
-- * hardware flow-control (CTS/RTS)
-- * Loop-back testing
--
-- Error-detection in receiver detects parity, framing
-- break and overrun errors.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.uart.all;
use grlib.devices.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity l2uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end;
architecture rtl of l2uart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_UART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, cparity, stopbit);
type txfsmtype is (idle, data, cparity, stopbit);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
parsel : std_ulogic; -- parity select
paren : std_ulogic; -- parity select
flow : std_ulogic; -- flow control enable
loopb : std_ulogic; -- loop back mode enable
dready : std_ulogic; -- data ready
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
thempty : std_ulogic; -- transmitter hold register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
parerr : std_ulogic; -- parity error
frame : std_ulogic; -- framing error
rtsn : std_ulogic; -- request to send
extclken : std_ulogic; -- use external baud rate clock
extclk : std_ulogic; -- rising edge detect register
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(10 downto 0);
thold : std_logic_vector(7 downto 0);
irq : std_ulogic; -- tx/rx interrupt (internal)
tpar : std_ulogic; -- tx data parity (internal)
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx delay
dpar : std_ulogic; -- rx data parity (internal)
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(11 downto 0);
brate : std_logic_vector(11 downto 0);
rxf : std_logic_vector(7 downto 0); -- rx data filtering buffer
txd : std_ulogic; -- transmitter data
end record;
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(11 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable v : uartregs;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0'; v.txtick := '0'; v.rxtick := '0'; v.tick := '0';
rdata := (others => '0'); v.rxdb(1) := r.rxdb(0);
-- scaler
scaler := r.scaler - 1;
if (r.rxen or r.txen) = '1' then
v.scaler := scaler;
v.tick := scaler(11) and not r.scaler(11);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- optional external uart clock
v.extclk := uarti.extclk;
if r.extclken = '1' then v.tick := r.extclk and not uarti.extclk; end if;
-- read/write registers
case apbi.paddr(3 downto 2) is
when "00" =>
rdata(7 downto 0) := r.rhold;
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
v.dready := '0';
end if;
when "01" =>
rdata(6 downto 0) := r.frame & r.parerr & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "10" =>
rdata(8 downto 0) := r.extclken & r.loopb & r.flow & r.paren & r.parsel &
r.tirqen & r.rirqen & r.txen & r.rxen;
when others =>
rdata(11 downto 0) := r.brate;
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.parerr := apbi.pwdata(5);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.extclken := apbi.pwdata(8);
v.loopb := apbi.pwdata(7);
v.flow := apbi.pwdata(6);
v.paren := apbi.pwdata(5);
v.parsel := apbi.pwdata(4);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(11 downto 0);
v.scaler := apbi.pwdata(11 downto 0);
when others =>
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk;
v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk;
v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
v.rxf := r.rxf(6 downto 0) & uarti.rxd;
if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
r.rxf(7)) = r.rxf(6 downto 0))
then v.rxdb(0) := r.rxf(7); end if;
-- loop-back mode
if r.loopb = '1' then
v.rxdb(0) := r.tshift(0); ctsn := r.dready and not r.rsempty;
else
ctsn := uarti.ctsn;
end if;
rxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if ((r.txen and (not r.thempty) and r.txtick) and
((not ctsn) or not r.flow)) = '1' then
v.tshift := "10" & r.thold & '0'; v.txstate := data;
v.tpar := r.parsel; v.irq := r.tirqen; v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmitt data frame
if r.txtick = '1' then
v.tpar := r.tpar xor r.tshift(1);
v.tshift := '1' & r.tshift(10 downto 1);
if r.tshift(10 downto 1) = "1111111110" then
if r.paren = '1' then
v.tshift(0) := r.tpar; v.txstate := cparity;
else
v.tshift(0) := '1'; v.txstate := stopbit;
end if;
end if;
end if;
when cparity => -- transmitt parity bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := stopbit;
end if;
when stopbit => -- transmitt stop bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
v.thold := apbi.pwdata(7 downto 0); v.thempty := '0';
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when others => null;
end case;
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb(1) and (not rxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if rxd = '0' then
v.rshift := rxd & r.rshift(7 downto 1); v.rxstate := data;
v.dpar := r.parsel;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd;
v.rshift := rxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
if r.paren = '1' then v.rxstate := cparity;
else v.rxstate := stopbit; v.dpar := '0'; end if;
end if;
end if;
when cparity => -- receive parity bit
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd; v.rxstate := stopbit;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
v.irq := v.irq or r.rirqen; -- make sure no tx irqs are lost !
if rxd = '1' then
v.parerr := r.dpar; v.rsempty := r.dpar;
if v.dready = '0' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := not r.dpar;
end if;
else
if r.rshift = "00000000" then v.break := '1';
else v.frame := '1'; end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
if r.rxtick = '1' then
v.rtsn := (r.dready and not r.rsempty) or r.loopb;
end if;
v.txd := r.tshift(0) or r.loopb;
-- reset operation
if rst = '0' then
v.frame := '0'; v.rsempty := '1';
v.parerr := '0'; v.ovf := '0'; v.break := '0'; v.thempty := '1';
v.tsempty := '1'; v.dready := '0'; v.txen := '0'; v.rxen := '0';
v.txstate := idle; v.rxstate := idle; v.tshift(0) := '1';
v.extclken := '0'; v.rtsn := '1'; v.flow := '0';
v.txclk := (others => '0'); v.rxclk := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
uarto.txd <= r.txd; uarto.rtsn <= r.rtsn;
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map ("l2uart" & tost(pindex) &
": LEON2 Generic UART rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: l2uart
-- File: l2uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Asynchronous UART originally developed for LEON2.
-- Implements 8-bit data frame with one stop-bit.
-- Programmable options:
-- * parity bit (on/off)
-- * parity polarity (odd/even)
-- * baud-rate (12-bit programmable divider)
-- * hardware flow-control (CTS/RTS)
-- * Loop-back testing
--
-- Error-detection in receiver detects parity, framing
-- break and overrun errors.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.uart.all;
use grlib.devices.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity l2uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end;
architecture rtl of l2uart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_UART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, cparity, stopbit);
type txfsmtype is (idle, data, cparity, stopbit);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
parsel : std_ulogic; -- parity select
paren : std_ulogic; -- parity select
flow : std_ulogic; -- flow control enable
loopb : std_ulogic; -- loop back mode enable
dready : std_ulogic; -- data ready
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
thempty : std_ulogic; -- transmitter hold register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
parerr : std_ulogic; -- parity error
frame : std_ulogic; -- framing error
rtsn : std_ulogic; -- request to send
extclken : std_ulogic; -- use external baud rate clock
extclk : std_ulogic; -- rising edge detect register
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(10 downto 0);
thold : std_logic_vector(7 downto 0);
irq : std_ulogic; -- tx/rx interrupt (internal)
tpar : std_ulogic; -- tx data parity (internal)
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx delay
dpar : std_ulogic; -- rx data parity (internal)
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(11 downto 0);
brate : std_logic_vector(11 downto 0);
rxf : std_logic_vector(7 downto 0); -- rx data filtering buffer
txd : std_ulogic; -- transmitter data
end record;
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(11 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable v : uartregs;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0'; v.txtick := '0'; v.rxtick := '0'; v.tick := '0';
rdata := (others => '0'); v.rxdb(1) := r.rxdb(0);
-- scaler
scaler := r.scaler - 1;
if (r.rxen or r.txen) = '1' then
v.scaler := scaler;
v.tick := scaler(11) and not r.scaler(11);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- optional external uart clock
v.extclk := uarti.extclk;
if r.extclken = '1' then v.tick := r.extclk and not uarti.extclk; end if;
-- read/write registers
case apbi.paddr(3 downto 2) is
when "00" =>
rdata(7 downto 0) := r.rhold;
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
v.dready := '0';
end if;
when "01" =>
rdata(6 downto 0) := r.frame & r.parerr & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "10" =>
rdata(8 downto 0) := r.extclken & r.loopb & r.flow & r.paren & r.parsel &
r.tirqen & r.rirqen & r.txen & r.rxen;
when others =>
rdata(11 downto 0) := r.brate;
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.parerr := apbi.pwdata(5);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.extclken := apbi.pwdata(8);
v.loopb := apbi.pwdata(7);
v.flow := apbi.pwdata(6);
v.paren := apbi.pwdata(5);
v.parsel := apbi.pwdata(4);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(11 downto 0);
v.scaler := apbi.pwdata(11 downto 0);
when others =>
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk;
v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk;
v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
v.rxf := r.rxf(6 downto 0) & uarti.rxd;
if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
r.rxf(7)) = r.rxf(6 downto 0))
then v.rxdb(0) := r.rxf(7); end if;
-- loop-back mode
if r.loopb = '1' then
v.rxdb(0) := r.tshift(0); ctsn := r.dready and not r.rsempty;
else
ctsn := uarti.ctsn;
end if;
rxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if ((r.txen and (not r.thempty) and r.txtick) and
((not ctsn) or not r.flow)) = '1' then
v.tshift := "10" & r.thold & '0'; v.txstate := data;
v.tpar := r.parsel; v.irq := r.tirqen; v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmitt data frame
if r.txtick = '1' then
v.tpar := r.tpar xor r.tshift(1);
v.tshift := '1' & r.tshift(10 downto 1);
if r.tshift(10 downto 1) = "1111111110" then
if r.paren = '1' then
v.tshift(0) := r.tpar; v.txstate := cparity;
else
v.tshift(0) := '1'; v.txstate := stopbit;
end if;
end if;
end if;
when cparity => -- transmitt parity bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := stopbit;
end if;
when stopbit => -- transmitt stop bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
v.thold := apbi.pwdata(7 downto 0); v.thempty := '0';
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when others => null;
end case;
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb(1) and (not rxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if rxd = '0' then
v.rshift := rxd & r.rshift(7 downto 1); v.rxstate := data;
v.dpar := r.parsel;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd;
v.rshift := rxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
if r.paren = '1' then v.rxstate := cparity;
else v.rxstate := stopbit; v.dpar := '0'; end if;
end if;
end if;
when cparity => -- receive parity bit
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd; v.rxstate := stopbit;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
v.irq := v.irq or r.rirqen; -- make sure no tx irqs are lost !
if rxd = '1' then
v.parerr := r.dpar; v.rsempty := r.dpar;
if v.dready = '0' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := not r.dpar;
end if;
else
if r.rshift = "00000000" then v.break := '1';
else v.frame := '1'; end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
if r.rxtick = '1' then
v.rtsn := (r.dready and not r.rsempty) or r.loopb;
end if;
v.txd := r.tshift(0) or r.loopb;
-- reset operation
if rst = '0' then
v.frame := '0'; v.rsempty := '1';
v.parerr := '0'; v.ovf := '0'; v.break := '0'; v.thempty := '1';
v.tsempty := '1'; v.dready := '0'; v.txen := '0'; v.rxen := '0';
v.txstate := idle; v.rxstate := idle; v.tshift(0) := '1';
v.extclken := '0'; v.rtsn := '1'; v.flow := '0';
v.txclk := (others => '0'); v.rxclk := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
uarto.txd <= r.txd; uarto.rtsn <= r.rtsn;
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map ("l2uart" & tost(pindex) &
": LEON2 Generic UART rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
entity leftofrightof is
end entity;
architecture subclass_variable of leftofrightof is
begin
process
variable i: integer := 1;
begin
report "variable i = " & integer'image(i);
report "integer'leftof(i) = " & integer'image(integer'leftof(i));
wait;
end process;
process
variable j: integer := 1;
begin
report "variable j = " & integer'image(j);
report "integer'rightof(j) = " & integer'image(integer'rightof(j));
wait;
end process;
end architecture;
|
entity leftofrightof is
end entity;
architecture subclass_variable of leftofrightof is
begin
process
variable i: integer := 1;
begin
report "variable i = " & integer'image(i);
report "integer'leftof(i) = " & integer'image(integer'leftof(i));
wait;
end process;
process
variable j: integer := 1;
begin
report "variable j = " & integer'image(j);
report "integer'rightof(j) = " & integer'image(integer'rightof(j));
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity qq6_code6_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(5 downto 0)
);
end qq6_code6_table;
architecture augh of qq6_code6_table is
-- Embedded RAM
type ram_type is array (0 to 63) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("11111111111111111111111101111000", "11111111111111111111111101111000", "11111111111111111111111101111000", "11111111111111111111111101111000", "11111111111111111001111100011000", "11111111111111111010101001110000", "11111111111111111011010111000000", "11111111111111111011111011000000", "11111111111111111100010101111000", "11111111111111111100101100111000", "11111111111111111101000000001000", "11111111111111111101010001001000", "11111111111111111101100000001000", "11111111111111111101101101110000", "11111111111111111101111010000000", "11111111111111111110000101010000", "11111111111111111110001111101000", "11111111111111111110011001010000", "11111111111111111110100010010000", "11111111111111111110101010110000", "11111111111111111110110010110000", "11111111111111111110111010010000", "11111111111111111111000001011000", "11111111111111111111001000001000", "11111111111111111111001110100000", "11111111111111111111010100101000", "11111111111111111111011010100000", "11111111111111111111100000010000", "11111111111111111111100101101000", "11111111111111111111101010110000", "11111111111111111111101111110000", "11111111111111111111110100101000", "00000000000000000110000011101000", "00000000000000000101010110010000", "00000000000000000100101001000000", "00000000000000000100000101000000", "00000000000000000011101010001000", "00000000000000000011010011001000", "00000000000000000010111111111000", "00000000000000000010101110111000", "00000000000000000010011111111000", "00000000000000000010010010010000", "00000000000000000010000110000000", "00000000000000000001111010110000", "00000000000000000001110000011000", "00000000000000000001100110110000", "00000000000000000001011101110000", "00000000000000000001010101010000", "00000000000000000001001101010000", "00000000000000000001000101110000", "00000000000000000000111110101000", "00000000000000000000110111111000", "00000000000000000000110001100000", "00000000000000000000101011011000", "00000000000000000000100101100000", "00000000000000000000011111110000", "00000000000000000000011010011000", "00000000000000000000010101010000", "00000000000000000000010000010000", "00000000000000000000001011011000", "00000000000000000000000110110000", "00000000000000000000000010001000", "11111111111111111111111001010000", "11111111111111111111111101111000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity qq6_code6_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(5 downto 0)
);
end qq6_code6_table;
architecture augh of qq6_code6_table is
-- Embedded RAM
type ram_type is array (0 to 63) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("11111111111111111111111101111000", "11111111111111111111111101111000", "11111111111111111111111101111000", "11111111111111111111111101111000", "11111111111111111001111100011000", "11111111111111111010101001110000", "11111111111111111011010111000000", "11111111111111111011111011000000", "11111111111111111100010101111000", "11111111111111111100101100111000", "11111111111111111101000000001000", "11111111111111111101010001001000", "11111111111111111101100000001000", "11111111111111111101101101110000", "11111111111111111101111010000000", "11111111111111111110000101010000", "11111111111111111110001111101000", "11111111111111111110011001010000", "11111111111111111110100010010000", "11111111111111111110101010110000", "11111111111111111110110010110000", "11111111111111111110111010010000", "11111111111111111111000001011000", "11111111111111111111001000001000", "11111111111111111111001110100000", "11111111111111111111010100101000", "11111111111111111111011010100000", "11111111111111111111100000010000", "11111111111111111111100101101000", "11111111111111111111101010110000", "11111111111111111111101111110000", "11111111111111111111110100101000", "00000000000000000110000011101000", "00000000000000000101010110010000", "00000000000000000100101001000000", "00000000000000000100000101000000", "00000000000000000011101010001000", "00000000000000000011010011001000", "00000000000000000010111111111000", "00000000000000000010101110111000", "00000000000000000010011111111000", "00000000000000000010010010010000", "00000000000000000010000110000000", "00000000000000000001111010110000", "00000000000000000001110000011000", "00000000000000000001100110110000", "00000000000000000001011101110000", "00000000000000000001010101010000", "00000000000000000001001101010000", "00000000000000000001000101110000", "00000000000000000000111110101000", "00000000000000000000110111111000", "00000000000000000000110001100000", "00000000000000000000101011011000", "00000000000000000000100101100000", "00000000000000000000011111110000", "00000000000000000000011010011000", "00000000000000000000010101010000", "00000000000000000000010000010000", "00000000000000000000001011011000", "00000000000000000000000110110000", "00000000000000000000000010001000", "11111111111111111111111001010000", "11111111111111111111111101111000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity qq6_code6_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(5 downto 0)
);
end qq6_code6_table;
architecture augh of qq6_code6_table is
-- Embedded RAM
type ram_type is array (0 to 63) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("11111111111111111111111101111000", "11111111111111111111111101111000", "11111111111111111111111101111000", "11111111111111111111111101111000", "11111111111111111001111100011000", "11111111111111111010101001110000", "11111111111111111011010111000000", "11111111111111111011111011000000", "11111111111111111100010101111000", "11111111111111111100101100111000", "11111111111111111101000000001000", "11111111111111111101010001001000", "11111111111111111101100000001000", "11111111111111111101101101110000", "11111111111111111101111010000000", "11111111111111111110000101010000", "11111111111111111110001111101000", "11111111111111111110011001010000", "11111111111111111110100010010000", "11111111111111111110101010110000", "11111111111111111110110010110000", "11111111111111111110111010010000", "11111111111111111111000001011000", "11111111111111111111001000001000", "11111111111111111111001110100000", "11111111111111111111010100101000", "11111111111111111111011010100000", "11111111111111111111100000010000", "11111111111111111111100101101000", "11111111111111111111101010110000", "11111111111111111111101111110000", "11111111111111111111110100101000", "00000000000000000110000011101000", "00000000000000000101010110010000", "00000000000000000100101001000000", "00000000000000000100000101000000", "00000000000000000011101010001000", "00000000000000000011010011001000", "00000000000000000010111111111000", "00000000000000000010101110111000", "00000000000000000010011111111000", "00000000000000000010010010010000", "00000000000000000010000110000000", "00000000000000000001111010110000", "00000000000000000001110000011000", "00000000000000000001100110110000", "00000000000000000001011101110000", "00000000000000000001010101010000", "00000000000000000001001101010000", "00000000000000000001000101110000", "00000000000000000000111110101000", "00000000000000000000110111111000", "00000000000000000000110001100000", "00000000000000000000101011011000", "00000000000000000000100101100000", "00000000000000000000011111110000", "00000000000000000000011010011000", "00000000000000000000010101010000", "00000000000000000000010000010000", "00000000000000000000001011011000", "00000000000000000000000110110000", "00000000000000000000000010001000", "11111111111111111111111001010000", "11111111111111111111111101111000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
process(CLK)
begin
if(CLK = '1' and CLK'event) then
if EN = '1' then
Q <= D;
end if;
end if;
end process;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc909.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00909ent IS
END c10s03b00x00p05n01i00909ent;
ARCHITECTURE c10s03b00x00p05n01i00909arch OF c10s03b00x00p05n01i00909ent IS
BEGIN
TESTING: PROCESS
variable QQ : INTEGER;
BEGIN
for I in 1 to 30 loop
null;
end loop;
QQ := I; -- Failure_here
-- error: entity not within the region it is immediately declared
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00909- Entity is not within the region it is immediately declared in."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00909arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc909.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00909ent IS
END c10s03b00x00p05n01i00909ent;
ARCHITECTURE c10s03b00x00p05n01i00909arch OF c10s03b00x00p05n01i00909ent IS
BEGIN
TESTING: PROCESS
variable QQ : INTEGER;
BEGIN
for I in 1 to 30 loop
null;
end loop;
QQ := I; -- Failure_here
-- error: entity not within the region it is immediately declared
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00909- Entity is not within the region it is immediately declared in."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00909arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc909.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00909ent IS
END c10s03b00x00p05n01i00909ent;
ARCHITECTURE c10s03b00x00p05n01i00909arch OF c10s03b00x00p05n01i00909ent IS
BEGIN
TESTING: PROCESS
variable QQ : INTEGER;
BEGIN
for I in 1 to 30 loop
null;
end loop;
QQ := I; -- Failure_here
-- error: entity not within the region it is immediately declared
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00909- Entity is not within the region it is immediately declared in."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00909arch;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05700_bad.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of gated clocks: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pkg_HBK.all;
--CODE
entity STD_05700_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_Data : in std_logic; -- Input data
o_Data : out std_logic; -- Output data
o_Gated_Clock : out std_logic -- Gated clock
);
end STD_05700_bad;
architecture Behavioral of STD_05700_bad is
signal Enable_r : std_logic;
signal Gated_Clock : std_logic;
signal Data_r : std_logic; -- Data signal registered
signal Data_r2 : std_logic; -- Data signal registered twice
begin
DFF_En : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_Enable,
o_Q => Enable_r,
o_Q_n => open
);
-- Make the Flip-Flop work when Enable signal is at 1
-- Enable signal on clock path
Gated_Clock <= i_Clock and Enable_r;
P_Sync_Data : process(i_Reset_n, Gated_Clock)
begin
if (i_Reset_n = '0') then
Data_r <= '0';
Data_r2 <= '0';
elsif (rising_edge(Gated_Clock)) then
Data_r <= i_Data;
Data_r2 <= Data_r;
end if;
end process;
o_Data <= Data_r2;
end Behavioral;
--CODE
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- David Wilson
-- University of Florida
-- Description:
-- The sga entity implements a simple group adder similar to the architecture
-- described in the paper "Design and implementation of an FPGA-based high-
-- performance improved vector-reduction method" by Song et al. (2011)
-- Used entities:
-- add_wrapper
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
use work.flt_pkg.all;
-------------------------------------------------------------------------------
-- Generics Description
-- width : The width of the input and output in bits
-- add_core_name : A string representing different optimizations for the
-- actual adder core. See add_flt.vhd and flt_pkg.vhd for
-- more information.
-- use_bram : uses bram when true, uses LUTs or FFs when false
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- rst : reset input (asynchronous, active high)
-- hold_output : When asserted, this signal prevents the entity from
-- continuing past a valid output. When not asserted, the
-- output is valid for only a single cycle. This signal
-- makes it possible to stall the sga if downstream
-- components cannot receive another input (active high)
-- ready : when asserted, the sga is ready to accept new inputs. If not
-- asserted, external components must hold the current input or
-- it will be lost (active high)
-- end_of_group : should be asserted on the same cycle as the last input in a
-- group (active high)
-- input : sga input
-- output : sga output
-- valid_in : assert when the input to the sga is valid and ready is
-- asserted (active high)
-- valid_out : asserted when the output from the sga is valid. Unless
-- hold_output is asserted, valid_out is only asserted for
-- one cycle. (active high)
-------------------------------------------------------------------------------
entity sga is
generic (
width : positive := 32;
add_core_name : string := "speed";
use_bram : boolean := true);
port (
clk : in std_logic;
rst : in std_logic;
hold_output : in std_logic; -- '1' keeps outputs from disappearing
ready : out std_logic; -- '1' when sga can accept input
end_of_group : in std_logic; -- specifies last input in group
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0);
valid_in : in std_logic;
valid_out : out std_logic
);
end sga;
architecture RTL of sga is
type buf_array is array (natural range <>) of std_logic_vector(width downto 0);
--control signals
signal is_coalescing : std_logic;
signal stall : std_logic;
signal all_buffers_empty : std_logic;
signal ready_int : std_logic;
--ibuf signals
signal ibuf_sel : std_logic;
signal ibuf_rd : std_logic;
signal ibuf_out : buf_array(1 downto 0);
signal ibuf_ready : std_logic;
signal ibuf_ready_singleton : std_logic;
--buf signals
signal buf_sel : std_logic;
signal buf_rd : std_logic;
signal buf_out : buf_array(1 downto 0);
signal buf0_out : buf_array(1 downto 0);
signal buf0_rd_addr : std_logic;
signal buf0_wr_addr : std_logic;
signal buf_ready : std_logic;
--obuf signals
signal obuf_wr : std_logic;
signal valid_out_int : std_logic;
--adder signals
signal add_in1 : std_logic_vector(width-1 downto 0);
signal add_in2 : std_logic_vector(width-1 downto 0);
signal add_out : std_logic_vector(width-1 downto 0);
signal add_en : std_logic;
signal add_valid_in : std_logic;
signal add_valid_out : std_logic;
signal add_count : std_logic_vector(bitsNeeded(add_flt_latency(add_core_name))-1 downto 0);
begin
------------------------------------------------
-- IBUF
-- ibuf is ready to add when both ready bits of its output registers are asserted
ibuf_ready <= ibuf_out(0)(width) and ibuf_out(1)(width);
-- ibuf is ready to add single element when one ready bit is asserted and no more
-- elements are arriving
ibuf_ready_singleton <= '1' when (ibuf_out(0)(width) = '1' or ibuf_out(1)(width) = '1') and
is_coalescing = '1' else
'0';
-- create ibuf
process(clk, rst)
begin
if (rst = '1') then
ibuf_sel <= '0';
ibuf_out <= (others => (others => '0'));
elsif (rising_edge(clk)) then
if (stall = '0') then
-- zero out previous elements when reading
if (ibuf_rd = '1') then
ibuf_out <= (others => (others => '0'));
end if;
-- write to an ibuf register any time there is
-- valid data
if (valid_in = '1' and ready_int = '1') then
if (ibuf_sel = '0') then
ibuf_out(0) <= '1' & input;
else
ibuf_out(1) <= '1' & input;
end if;
-- switch between writing to ibuf0 and ibuf1
ibuf_sel <= not ibuf_sel;
end if;
end if;
end if;
end process;
------------------------------------------------
-- BUF
-- buf is ready to add when buf0 and buf1 ready bits are asserted
buf_ready <= buf_out(0)(width) and buf_out(1)(width);
-- create buf. Buf0 is implemented as two-register fifo to handle
-- when both ibuf and buf have two elements and two writes in the
-- same cycle.
process(clk, rst)
begin
if (rst = '1') then
buf0_rd_addr <= '0';
buf0_wr_addr <= '0';
buf0_out <= (others => (others => '0'));
buf_sel <= '0';
buf_out(1) <= (others => '0');
elsif (rising_edge(clk)) then
if (stall = '0') then
-- zero out previous elements when reading
if (buf_rd = '1') then
-- zero out only registers used in read
if (buf0_rd_addr = '0') then
buf0_out(0) <= (others => '0');
else
buf0_out(1) <= (others => '0');
end if;
buf_out(1) <= (others => '0');
-- pop the buf0 fifo by changing rd_addr
buf0_rd_addr <= not buf0_rd_addr;
end if;
-- write to buf any time there is valid adder output
-- that isn't the last element in the group
if (add_valid_out = '1' and obuf_wr = '0') then
-- switch between writing to buf0 and buf1
buf_sel <= not buf_sel;
if (buf_sel = '1') then
buf_out(1) <= '1' & add_out;
else
-- push element into buf0 fifo
if (buf0_wr_addr = '0') then
buf0_out(0) <= '1' & add_out;
else
buf0_out(1) <= '1' & add_out;
end if;
buf0_wr_addr <= not buf0_wr_addr;
end if;
end if;
end if;
end if;
end process;
-- multiplexer for buf0 output as a fifo
buf_out(0) <= buf0_out(0) when buf0_rd_addr <= '0' else buf0_out(1);
-------------------------------------------------
-- Control logic
-- determines adder scheduling
process(ibuf_ready, buf_ready, ibuf_ready_singleton)
begin
add_valid_in <= '0';
ibuf_rd <= '0';
buf_rd <= '0';
-- add using inputs from ibuf when ibuf is ready
if(ibuf_ready = '1') then
add_valid_in <= '1';
ibuf_rd <= '1';
-- add using inputs from buf when buf is ready
elsif(buf_ready = '1') then
add_valid_in <= '1';
buf_rd <= '1';
-- add using inputs from ibuf when ibuf has only one element and no more elements are arriving
elsif (ibuf_ready_singleton = '1') then
add_valid_in <= '1';
ibuf_rd <= '1';
end if;
end process;
-- buffers are empty if none of the registers have their ready bits asserted
all_buffers_empty <= '1' when buf0_out(0)(width) = '0' and buf0_out(1)(width) = '0' and buf_out(1)(width) = '0' and
ibuf_out(0)(width) = '0' and ibuf_out(1)(width) = '0' else
'0';
-- inputs are accepted when the architecture is not stalling or is coalescing the final sum of a group
ready_int <= '1' when stall = '0' and is_coalescing = '0' else '0';
ready <= ready_int;
-- stall the architecture when an output is being held and another final sum has been computed
stall <= '1' when (obuf_wr = '1' and valid_out_int = '1' and hold_output = '1') else '0';
-- indicates if the group's elements are being coalesced into one value
process(clk, rst)
begin
if (rst = '1') then
is_coalescing <= '0';
elsif (rising_edge(clk)) then
if (stall = '0') then
-- coalescing begins when the last element has arrived
if (valid_in = '1' and ready_int = '1' and end_of_group = '1') then
is_coalescing <= '1';
-- coalescing ends when the final sum has been computed
elsif (is_coalescing = '1' and obuf_wr = '1') then
is_coalescing <= '0';
end if;
end if;
end if;
end process;
------------------------------------------------
-- OBUF
-- the obuf is written to when the buffers are empty
-- and the adder output has the final sum
obuf_wr <= '1' when (unsigned(add_count) = 1 and
all_buffers_empty = '1' and
add_valid_out = '1' and
is_coalescing = '1') else
'0';
-- create obuf
process(clk, rst)
begin
if (rst = '1') then
output <= (others => '0');
valid_out_int <= '0';
elsif (rising_edge(clk)) then
if (stall = '0') then
-- only deassert valid_out when hold_output is deasserted
if (hold_output = '0') then
valid_out_int <= '0';
end if;
-- the final sum from adder is output when no elements remain in adders
-- and buffers, and no output is being held with hold_output asserted
if (obuf_wr = '1' and (hold_output = '0' or valid_out_int = '0')) then
output <= add_out;
valid_out_int <= '1';
end if;
end if;
end if;
end process;
valid_out <= valid_out_int;
------------------------------------------------
-- OBUF
-- enable adder when the architecture is not stalling
add_en <= not stall;
-- multiplexer for 1st adder input
add_in1 <= ibuf_out(0)(width-1 downto 0) when ibuf_rd = '1' else
buf_out(0)(width-1 downto 0);
-- multiplexer for 2nd adder input
add_in2 <= ibuf_out(1)(width-1 downto 0) when ibuf_rd = '1' else
buf_out(1)(width-1 downto 0);
U_ADD : entity work.add_wrapper
generic map (core_name => add_core_name,
width => width)
port map (clk => clk,
rst => rst,
en => add_en,
input1 => add_in1,
input2 => add_in2,
output => add_out,
valid_in => add_valid_in,
valid_out => add_valid_out,
count => add_count);
end RTL;
|
-- $Id: iob_reg_i.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_i - syn
-- Description: Registered IOB, input only
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_i is -- registered IOB, input
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slbit; -- input data
PAD : in slbit -- i/o pad
);
end iob_reg_i;
architecture syn of iob_reg_i is
begin
IOB : iob_reg_i_gen
generic map (
DWIDTH => 1,
INIT => INIT)
port map (
CLK => CLK,
CE => CE,
DI(0) => DI,
PAD(0) => PAD
);
end syn;
|
library verilog;
use verilog.vl_types.all;
entity TestInitRam is
generic(
ADDR_WIDTH : integer := 4;
DATA_WIDTH : integer := 8;
MEM_DEPTH : integer := 64
);
port(
clk : in vl_logic;
rst : in vl_logic;
key : out vl_logic_vector;
finished : out vl_logic;
addrA : out vl_logic_vector;
addrB : out vl_logic_vector;
wr_enaA : out vl_logic;
wr_enaB : out vl_logic;
data_outA : out vl_logic_vector;
data_outB : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ADDR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1;
attribute mti_svvh_generic_type of MEM_DEPTH : constant is 1;
end TestInitRam;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity average_calculator_u is
generic(
DATA_IMM_AFTER_START_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
S : positive --compulsory
);
port(
input : in u_ufixed_v; --unconstrained array
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out u_ufixed; --unconstrained array
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture average_calculator_u1 of average_calculator_u is
constant P : positive := input'length;
/* constant CHECKS : integer := average_calculator_CHECKS();*/
/*================================================================================================*/
/*================================================================================================*/
begin
average_calculator_core_u1:
entity work.average_calculator_core_u
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
S => S,
P => P,
input_high => input(1)'high,
input_low => input(1)'low
)
port map(
clk => clk,
input => input,
valid_input => valid_input,
start => start,
output => output,
valid_output => valid_output
);
end architecture; |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Presettable synchronous 4-bit binary counter with asynchronous reset
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_74161 is
generic (
latency : integer := 3
);
port (
emuclk : in std_logic;
p1 : in ttl_t; -- MRn
p2 : in ttl_t; -- CP
p3 : in ttl_t; -- D0
p4 : in ttl_t; -- D1
p5 : in ttl_t; -- D2
p6 : in ttl_t; -- D3
p7 : in ttl_t; -- CEP
p9 : in ttl_t; -- PEn
p10 : in ttl_t; -- CET
p11 : out ttl_t; -- Q3
p12 : out ttl_t; -- Q2
p13 : out ttl_t; -- Q1
p14 : out ttl_t; -- Q0
p15 : out ttl_t -- TC
);
end entity;
architecture rtl of ttl_74161 is
signal q0_reg : ttl_t := ZERO;
signal q1_reg : ttl_t := ZERO;
signal q2_reg : ttl_t := ZERO;
signal q3_reg : ttl_t := ZERO;
signal tc_reg : ttl_t := ZERO;
signal cp : std_logic;
signal cp_dly : std_logic := '0';
begin
p11_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => q3_reg, q => p11);
p12_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => q2_reg, q => p12);
p13_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => q1_reg, q => p13);
p14_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => q0_reg, q => p14);
p15_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => tc_reg, q => p15);
cp <= ttl2std(p2);
process(emuclk)
begin
if rising_edge(emuclk) then
cp_dly <= cp;
if is_low(p1) then
-- Asynchronous reset
q0_reg <= ZERO;
q1_reg <= ZERO;
q2_reg <= ZERO;
q3_reg <= ZERO;
elsif (cp = '1') and (cp_dly = '0') then
if is_low(p9) then
-- Load constant
q0_reg <= buffered(p3);
q1_reg <= buffered(p4);
q2_reg <= buffered(p5);
q3_reg <= buffered(p6);
elsif is_high(p7) and is_high(p10) then
-- Count
q0_reg <= not q0_reg;
if is_high(q0_reg) then
q1_reg <= not q1_reg;
end if;
if is_high(q0_reg) and is_high(q1_reg) then
q2_reg <= not q2_reg;
end if;
if is_high(q0_reg) and is_high(q1_reg) and is_high(q2_reg) then
q3_reg <= not q3_reg;
end if;
tc_reg <= ZERO;
if is_low(q0_reg) and is_high(q1_reg) and is_high(q2_reg) and is_high(q3_reg) then
tc_reg <= ONE;
end if;
end if;
end if;
end if;
end process;
end architecture;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:35:18)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_spea2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END arf_spea2_entity;
ARCHITECTURE arf_spea2_description OF arf_spea2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register3 := input3 * 3;
register4 := input4 * 4;
register1 := register2 + register1;
WHEN "00000011" =>
register2 := register3 + register4;
register1 := register1 + 6;
register3 := input5 * 7;
register4 := input6 * 8;
WHEN "00000100" =>
register3 := register3 + register4;
register4 := input7 * 9;
register5 := input8 * 10;
register2 := register2 + 12;
WHEN "00000101" =>
register6 := register1 * 14;
register4 := register5 + register4;
register5 := register2 * 16;
WHEN "00000110" =>
register2 := register2 * 18;
register1 := register1 * 20;
register5 := register5 + register6;
WHEN "00000111" =>
register1 := register2 + register1;
register2 := register5 * 22;
register5 := register5 * 24;
WHEN "00001000" =>
register6 := register1 * 26;
register1 := register1 * 28;
WHEN "00001001" =>
register1 := register1 + register2;
register2 := register6 + register5;
WHEN "00001010" =>
output1 <= register4 + register2;
output2 <= register3 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_spea2_description; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.11.2013 00:20:28
-- Design Name:
-- Module Name: TB2_MultiByte_4ByteAligned - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TB2_MultiByte_4ByteAligned is
end TB2_MultiByte_4ByteAligned;
architecture Behavioral of TB2_MultiByte_4ByteAligned is
-- Signals to evaluate
--ENTRADAS
signal inputBlock : std_logic_vector(31 downto 0);
signal readInput : std_logic;
signal blockLength : std_logic_vector(1 downto 0);
signal finalBlock : std_logic;
signal start : std_logic;
signal operationID : std_logic_vector(31 downto 0);
signal seed : std_logic_vector(31 downto 0);
--SALIDAS
signal canAccept : std_logic;
signal resultReady : std_logic;
signal result : std_logic_vector(31 downto 0);
signal resultID : std_logic_vector(31 downto 0);
--RELOJ
signal clk : std_logic;
--Salidas de depuracion
signal dataStep1_dbg : std_logic_vector(31 downto 0);
signal dataStep2_dbg : std_logic_vector(31 downto 0);
signal dataStep3_dbg : std_logic_vector(31 downto 0);
signal dataStep4_dbg : std_logic_vector(31 downto 0);
signal dataStep5_dbg : std_logic_vector(31 downto 0);
signal dataStep1_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep2_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep3_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep4_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep5_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep1_dbg : std_logic_vector(31 downto 0);
signal finalStep2_dbg : std_logic_vector(31 downto 0);
signal finalStep3_dbg : std_logic_vector(31 downto 0);
signal finalStep4_dbg : std_logic_vector(31 downto 0);
signal finalStep5_dbg : std_logic_vector(31 downto 0);
signal finalStep1_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep2_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep3_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep4_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep5_ID_dbg : std_logic_vector(31 downto 0);
type resultReference is array (0 to 13) of std_logic_vector(31 downto 0);
type input_2e is array (0 to 1) of std_logic_vector(31 downto 0);
type input_3e is array (0 to 2) of std_logic_vector(31 downto 0);
constant entrada1 : input_2e := ( x"2362f9de", x"fbf1402a" );
constant entrada2 : input_3e := ( x"2362f9de", x"fbf1402a", x"3412cdab" );
constant resultsBank : resultReference := ( x"2362f9de", x"fbf1402a", x"2362f9de", x"fbf1402a", x"40b23b7f", x"32850971", x"9994d794", x"4c382e54", x"7117fdd0", x"db55ec24", x"76293b50", x"7e33a1a1", x"82f2c7d0", x"885962c1" );
constant opsIDs : resultReference := ( x"2362f9de", x"fbf1402a", x"2362f9de", x"fbf1402a", x"40b23b7f", x"32850971", x"9994d794", x"4c382e54", x"7117fdd0", x"db55ec24", x"76293b50", x"7e33a1a1", x"82f2c7d0", x"885962c1" );
signal resultsBankCounter : integer := 0;
signal errorDetected : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
--Inicializar el banco de resultados
verification: process (clk, resultReady, result, resultsBankCounter)
begin
-- if( rising_edge(clk) ) then
-- if( resultsBankCounter = resultReference'length ) then
-- errorDetected <= '0';
-- else
-- if (resultReady = '1') then
-- if( (resultsBank(resultsBankCounter)/=result) or (resultID/=opsIDs(resultsBankCounter)) ) then
-- errorDetected <= '1';
-- else
-- errorDetected <= '0';
-- end if;
-- resultsBankCounter <= resultsBankCounter+1;
-- else
-- errorDetected <= '0';
-- end if;
-- end if;
-- end if;
end process verification;
uut: work.MurmurHashUtils.MurmurHash32Generator PORT MAP (
--ENTRADAS
inputBlock => inputBlock,
readInput => readInput,
blockLength => blockLength,
finalBlock => finalBlock,
start => start,
operationID => operationID,
seed => seed,
--SALIDAS
canAccept => canAccept,
resultReady => resultReady,
result => result,
resultID => resultID,
--RELOJ
clk => clk,
--Salidas de depuracion
dataStep1_dbg => dataStep1_dbg,
dataStep2_dbg => dataStep2_dbg,
dataStep3_dbg => dataStep3_dbg,
dataStep4_dbg => dataStep4_dbg,
dataStep5_dbg => dataStep5_dbg,
dataStep1_ID_dbg => dataStep1_ID_dbg,
dataStep2_ID_dbg => dataStep2_ID_dbg,
dataStep3_ID_dbg => dataStep3_ID_dbg,
dataStep4_ID_dbg => dataStep4_ID_dbg,
dataStep5_ID_dbg => dataStep5_ID_dbg,
finalStep1_dbg => finalStep1_dbg,
finalStep2_dbg => finalStep2_dbg,
finalStep3_dbg => finalStep3_dbg,
finalStep4_dbg => finalStep4_dbg,
finalStep5_dbg => finalStep5_dbg,
finalStep1_ID_dbg => finalStep1_ID_dbg,
finalStep2_ID_dbg => finalStep2_ID_dbg,
finalStep3_ID_dbg => finalStep3_ID_dbg,
finalStep4_ID_dbg => finalStep4_ID_dbg,
finalStep5_ID_dbg => finalStep5_ID_dbg
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
blockLength <= "11";
--operationID <= "0101"&"0101"&"0101"&"0101"&"0101"&"0101"&"0101"&"0101";
operationID <= opsIDs(0);
--PRUEBA 1, HASH DEL VECTOR 0
--Se einicializan los datos y
inputBlock <= entrada1(0);
start <= '1';
finalBlock <= '0';
seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
readInput <= '0';
wait for clk_period;
--hacer que realize una lectura de datos
readInput <= '1';
wait for clk_period;
inputBlock <= entrada1(1);
start <= '0';--que lea el segundo byte(final)
finalBlock <= '1';
readInput <= '1';
wait for clk_period;
readInput <= '0';
finalBlock <= '0';
start <= '0';
wait for 3*clk_period;
--SEGUNDA PRUEBA
readInput <= '1';
start <= '1';
finalBlock <= '0';
inputBlock <= entrada2(0);
readInput <= '1';
wait for clk_period;
inputBlock <= entrada2(1);
start <= '0';--que lea el segundo byte(final)
finalBlock <= '0';
wait for clk_period;
inputBlock <= entrada2(2);
start <= '0';--que lea el segundo byte(final)
finalBlock <= '1';
wait for clk_period;
readInput <= '0';
start <= '0';--que lea el segundo byte(final)
finalBlock <= '0';
wait for clk_period;
--TERCERA PRUEBA, los mismos datos de la segunda, pero con espaciados
readInput <= '1';
start <= '1';
finalBlock <= '0';
inputBlock <= entrada2(0);
readInput <= '1';
wait for clk_period;
inputBlock <= entrada2(1);
start <= '0';--que lea el segundo byte(final)
finalBlock <= '0';
wait for clk_period;
readInput <= '0';
wait for clk_period;
readInput <= '0';
wait for clk_period;
readInput <= '1';
inputBlock <= entrada2(2);
start <= '0';--que lea el segundo byte(final)
finalBlock <= '1';
wait for clk_period;
readInput <= '0';
start <= '0';--que lea el segundo byte(final)
finalBlock <= '0';
wait for clk_period;
wait;
end process stim_proc;
end Behavioral;
|
-- $Id: gray_cnt_4.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_4 - syn
-- Description: 4 bit Gray code counter (ROM based)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- LUT Flop clock(xst est.)
-- 4 4 365MHz/ 2.76ns
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray_cnt_4 is -- 4 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv4 -- data out
);
end entity gray_cnt_4;
architecture syn of gray_cnt_4 is
signal R_DATA : slv4 := (others=>'0');
signal N_DATA : slv4 := (others=>'0');
-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm is
-- inferred. For 4 bit the coding was 'Gray', but see remarks in
-- gray_cnt_5. To be save, disallow fsm inferal, enforce reg+rom.
attribute fsm_extract : string;
attribute fsm_extract of R_DATA : signal is "no";
attribute rom_style : string;
attribute rom_style of N_DATA : signal is "distributed";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_DATA <= (others=>'0');
elsif CE = '1' then
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_DATA)
begin
N_DATA <= (others=>'0');
case R_DATA is
when "0000" => N_DATA <= "0001"; -- 0
when "0001" => N_DATA <= "0011"; -- 1
when "0011" => N_DATA <= "0010"; -- 2
when "0010" => N_DATA <= "0110"; -- 3
when "0110" => N_DATA <= "0111"; -- 4
when "0111" => N_DATA <= "0101"; -- 5
when "0101" => N_DATA <= "0100"; -- 6
when "0100" => N_DATA <= "1100"; -- 7
when "1100" => N_DATA <= "1101"; -- 8
when "1101" => N_DATA <= "1111"; -- 9
when "1111" => N_DATA <= "1110"; -- 10
when "1110" => N_DATA <= "1010"; -- 11
when "1010" => N_DATA <= "1011"; -- 12
when "1011" => N_DATA <= "1001"; -- 13
when "1001" => N_DATA <= "1000"; -- 14
when "1000" => N_DATA <= "0000"; -- 15
when others => null;
end case;
end process proc_next;
DATA <= R_DATA;
end syn;
|
-- $Id: gray_cnt_4.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_4 - syn
-- Description: 4 bit Gray code counter (ROM based)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- LUT Flop clock(xst est.)
-- 4 4 365MHz/ 2.76ns
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray_cnt_4 is -- 4 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv4 -- data out
);
end entity gray_cnt_4;
architecture syn of gray_cnt_4 is
signal R_DATA : slv4 := (others=>'0');
signal N_DATA : slv4 := (others=>'0');
-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm is
-- inferred. For 4 bit the coding was 'Gray', but see remarks in
-- gray_cnt_5. To be save, disallow fsm inferal, enforce reg+rom.
attribute fsm_extract : string;
attribute fsm_extract of R_DATA : signal is "no";
attribute rom_style : string;
attribute rom_style of N_DATA : signal is "distributed";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_DATA <= (others=>'0');
elsif CE = '1' then
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_DATA)
begin
N_DATA <= (others=>'0');
case R_DATA is
when "0000" => N_DATA <= "0001"; -- 0
when "0001" => N_DATA <= "0011"; -- 1
when "0011" => N_DATA <= "0010"; -- 2
when "0010" => N_DATA <= "0110"; -- 3
when "0110" => N_DATA <= "0111"; -- 4
when "0111" => N_DATA <= "0101"; -- 5
when "0101" => N_DATA <= "0100"; -- 6
when "0100" => N_DATA <= "1100"; -- 7
when "1100" => N_DATA <= "1101"; -- 8
when "1101" => N_DATA <= "1111"; -- 9
when "1111" => N_DATA <= "1110"; -- 10
when "1110" => N_DATA <= "1010"; -- 11
when "1010" => N_DATA <= "1011"; -- 12
when "1011" => N_DATA <= "1001"; -- 13
when "1001" => N_DATA <= "1000"; -- 14
when "1000" => N_DATA <= "0000"; -- 15
when others => null;
end case;
end process proc_next;
DATA <= R_DATA;
end syn;
|
architecture rtl of fifo is
begin
GEN_LABEL : FOR x in range (3 downto 0) generate
end generate;
GEN_LABEL : FOR x in range (3 downto 0) generate
end generate;
end architecture;
|
--
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
vgaclk: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_ulogic;
signal dcmclock: std_ulogic;
signal rst1_q: std_logic := '1';
signal rst2_q: std_logic := '1';
signal clkout_i: std_ulogic;
signal clkin_i: std_ulogic;
signal clkfb: std_ulogic;
signal clk0: std_ulogic;
signal clk1: std_ulogic;
signal clk2: std_ulogic;
signal clk2x: std_ulogic;
signal clkin_i_2: std_logic;
begin
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, clkout_i, rstin)
begin
if dcmlocked='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => clk0,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
clkfb_inst: BUFG
port map (
I=> dcmclock,
O=> clkfb
);
clk1_inst: BUFG port map ( I => clk1, O => clkout1 );
clk2_inst: BUFG port map ( I => clk2, O => clkout2 );
clk3_inst: BUFG port map ( I => clk2x, O => vgaclk );
pll_base_inst : PLL_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,--30 -- 20,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10,--10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 250.0,--300.0,--155.52,--103.700,--343.125,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 10,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 38, --31,--38,
CLKOUT3_PHASE => 0.0,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 31.250,
REF_JITTER => 0.010,
SIM_DEVICE => "SPARTAN6")
port map
-- Output clocks
(CLKFBOUT => dcmclock,
CLKOUT0 => clk0,
CLKOUT1 => clk1,
CLKOUT2 => clk2,
CLKOUT3 => clk2x,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => dcmlocked,
RST => '0',
-- Input clock control
CLKFBIN => clkfb,
CLKIN1 => clkin_i,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0'
);
end behave;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY FsmExample IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
clk : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF FsmExample IS
TYPE st_t IS (a_0, b_0, aAndB);
SIGNAL st : st_t := a_0;
SIGNAL st_next : st_t;
BEGIN
assig_process_dout: PROCESS(st)
BEGIN
CASE st IS
WHEN a_0 =>
dout <= "001";
WHEN b_0 =>
dout <= "010";
WHEN OTHERS =>
dout <= "011";
END CASE;
END PROCESS;
assig_process_st: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
st <= a_0;
ELSE
st <= st_next;
END IF;
END IF;
END PROCESS;
assig_process_st_next: PROCESS(a, b, st)
BEGIN
CASE st IS
WHEN a_0 =>
IF (a AND b) = '1' THEN
st_next <= aandb;
ELSIF b = '1' THEN
st_next <= b_0;
ELSE
st_next <= st;
END IF;
WHEN b_0 =>
IF (a AND b) = '1' THEN
st_next <= aandb;
ELSIF a = '1' THEN
st_next <= a_0;
ELSE
st_next <= st;
END IF;
WHEN OTHERS =>
IF (a AND NOT b) = '1' THEN
st_next <= a_0;
ELSIF (NOT a AND b) = '1' THEN
st_next <= b_0;
ELSE
st_next <= st;
END IF;
END CASE;
END PROCESS;
END ARCHITECTURE;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
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-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p2_DWIDTH : integer := 32;
constant p3_DWIDTH : integer := 32;
constant p2_PORT_MODE : string := "RD_MODE";
constant p3_PORT_MODE : string := "WR_MODE";
signal p0_mcb_cmd_addr_o_int : std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 DOWNTO 0);
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 DOWNTO 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p2 Signal declarations
signal p2_tg_run_traffic : std_logic;
signal p2_tg_start_addr : std_logic_vector(31 downto 0);
signal p2_tg_end_addr : std_logic_vector(31 downto 0);
signal p2_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p2_tg_data_seed : std_logic_vector(31 downto 0);
signal p2_tg_load_seed : std_logic;
signal p2_tg_addr_mode : std_logic_vector(2 downto 0);
signal p2_tg_instr_mode : std_logic_vector(3 downto 0);
signal p2_tg_bl_mode : std_logic_vector(1 downto 0);
signal p2_tg_data_mode : std_logic_vector(3 downto 0);
signal p2_tg_mode_load : std_logic;
signal p2_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p2_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p2_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p2_error_status : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
signal p2_error : std_logic;
signal p2_cmp_error : std_logic;
signal p2_cmp_data : std_logic_vector(p2_DWIDTH-1 downto 0);
signal p2_cmp_data_valid : std_logic;
signal p2_mcb_cmd_en_o_int : std_logic;
signal p2_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p2_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p2_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p2_mcb_wr_en_o_int : std_logic;
--p3 Signal declarations
signal p3_tg_run_traffic : std_logic;
signal p3_tg_start_addr : std_logic_vector(31 downto 0);
signal p3_tg_end_addr : std_logic_vector(31 downto 0);
signal p3_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p3_tg_data_seed : std_logic_vector(31 downto 0);
signal p3_tg_load_seed : std_logic;
signal p3_tg_addr_mode : std_logic_vector(2 downto 0);
signal p3_tg_instr_mode : std_logic_vector(3 downto 0);
signal p3_tg_bl_mode : std_logic_vector(1 downto 0);
signal p3_tg_data_mode : std_logic_vector(3 downto 0);
signal p3_tg_mode_load : std_logic;
signal p3_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p3_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p3_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p3_error_status : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
signal p3_error : std_logic;
signal p3_cmp_error : std_logic;
signal p3_cmp_data : std_logic_vector(p3_DWIDTH-1 downto 0);
signal p3_cmp_data_valid : std_logic;
signal p3_mcb_cmd_en_o_int : std_logic;
signal p3_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p3_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p3_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p3_mcb_wr_en_o_int : std_logic;
signal p2_mcb_wr_en_o : std_logic;
signal p2_mcb_wr_full_i : std_logic;
signal p2_mcb_wr_data_o : std_logic_vector(31 downto 0);
signal p2_mcb_wr_mask_o : std_logic_vector(3 downto 0);
signal p2_mcb_wr_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_en_o : std_logic;
signal p3_mcb_rd_empty_i : std_logic;
signal p3_mcb_rd_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_data_i : std_logic_vector(31 downto 0);
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p2_cmp_error or p3_cmp_error;
error <= p2_error or p3_error;
error_status <= p2_error_status;
cmp_data <= p2_cmp_data(31 downto 0);
cmp_data_valid <= p2_cmp_data_valid;
p2_mcb_cmd_en_o <= p2_mcb_cmd_en_o_int;
p2_mcb_cmd_instr_o <= p2_mcb_cmd_instr_o_int;
p2_mcb_cmd_bl_o <= p2_mcb_cmd_bl_o_int;
p2_mcb_cmd_addr_o <= p2_mcb_cmd_addr_o_int;
p2_mcb_wr_en_o <= p2_mcb_wr_en_o_int;
init_mem_pattern_ctr_p2 :init_mem_pattern_ctr
generic map
(
DWIDTH => p2_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p2_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p2_error,
run_traffic_o => p2_tg_run_traffic,
start_addr_o => p2_tg_start_addr,
end_addr_o => p2_tg_end_addr ,
cmd_seed_o => p2_tg_cmd_seed ,
data_seed_o => p2_tg_data_seed ,
load_seed_o => p2_tg_load_seed ,
addr_mode_o => p2_tg_addr_mode ,
instr_mode_o => p2_tg_instr_mode ,
bl_mode_o => p2_tg_bl_mode ,
data_mode_o => p2_tg_data_mode ,
mode_load_o => p2_tg_mode_load ,
fixed_bl_o => p2_tg_fixed_bl ,
fixed_instr_o => p2_tg_fixed_instr,
fixed_addr_o => p2_tg_fixed_addr
);
m_traffic_gen_p2 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p2_PORT_MODE,
DWIDTH => p2_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p2_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p2_tg_start_addr ,
end_addr_i => p2_tg_end_addr ,
cmd_seed_i => p2_tg_cmd_seed ,
data_seed_i => p2_tg_data_seed ,
load_seed_i => p2_tg_load_seed,
addr_mode_i => p2_tg_addr_mode,
instr_mode_i => p2_tg_instr_mode ,
bl_mode_i => p2_tg_bl_mode ,
data_mode_i => p2_tg_data_mode ,
mode_load_i => p2_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p2_tg_fixed_bl,
fixed_instr_i => p2_tg_fixed_instr,
fixed_addr_i => p2_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p2_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p2_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p2_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p2_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p2_mcb_cmd_full_i,
mcb_wr_en_o => p2_mcb_wr_en_o_int,
mcb_wr_mask_o => p2_mcb_wr_mask_o,
mcb_wr_data_o => p2_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p2_mcb_wr_full_i,
mcb_wr_fifo_counts => p2_mcb_wr_fifo_counts,
mcb_rd_en_o => p2_mcb_rd_en_o,
mcb_rd_data_i => p2_mcb_rd_data_i,
mcb_rd_empty_i => p2_mcb_rd_empty_i,
mcb_rd_fifo_counts => p2_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p2_cmp_data,
cmp_data_valid => p2_cmp_data_valid,
cmp_error => p2_cmp_error,
error => p2_error,
error_status => p2_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p3_mcb_cmd_en_o <= p3_mcb_cmd_en_o_int;
p3_mcb_cmd_instr_o <= p3_mcb_cmd_instr_o_int;
p3_mcb_cmd_bl_o <= p3_mcb_cmd_bl_o_int;
p3_mcb_cmd_addr_o <= p3_mcb_cmd_addr_o_int;
p3_mcb_wr_en_o <= p3_mcb_wr_en_o_int;
init_mem_pattern_ctr_p3 :init_mem_pattern_ctr
generic map
(
DWIDTH => p3_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p3_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p3_error,
run_traffic_o => p3_tg_run_traffic,
start_addr_o => p3_tg_start_addr,
end_addr_o => p3_tg_end_addr ,
cmd_seed_o => p3_tg_cmd_seed ,
data_seed_o => p3_tg_data_seed ,
load_seed_o => p3_tg_load_seed ,
addr_mode_o => p3_tg_addr_mode ,
instr_mode_o => p3_tg_instr_mode ,
bl_mode_o => p3_tg_bl_mode ,
data_mode_o => p3_tg_data_mode ,
mode_load_o => p3_tg_mode_load ,
fixed_bl_o => p3_tg_fixed_bl ,
fixed_instr_o => p3_tg_fixed_instr,
fixed_addr_o => p3_tg_fixed_addr
);
m_traffic_gen_p3 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p3_PORT_MODE,
DWIDTH => p3_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p3_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p3_tg_start_addr ,
end_addr_i => p3_tg_end_addr ,
cmd_seed_i => p3_tg_cmd_seed ,
data_seed_i => p3_tg_data_seed ,
load_seed_i => p3_tg_load_seed,
addr_mode_i => p3_tg_addr_mode,
instr_mode_i => p3_tg_instr_mode ,
bl_mode_i => p3_tg_bl_mode ,
data_mode_i => p3_tg_data_mode ,
mode_load_i => p3_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p3_tg_fixed_bl,
fixed_instr_i => p3_tg_fixed_instr,
fixed_addr_i => p3_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p3_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p3_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p3_mcb_cmd_full_i,
mcb_wr_en_o => p3_mcb_wr_en_o_int,
mcb_wr_mask_o => p3_mcb_wr_mask_o,
mcb_wr_data_o => p3_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p3_mcb_wr_full_i,
mcb_wr_fifo_counts => p3_mcb_wr_fifo_counts,
mcb_rd_en_o => p3_mcb_rd_en_o,
mcb_rd_data_i => p3_mcb_rd_data_i,
mcb_rd_empty_i => p3_mcb_rd_empty_i,
mcb_rd_fifo_counts => p3_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p3_cmp_data,
cmp_data_valid => p3_cmp_data_valid,
cmp_error => p3_cmp_error,
error => p3_error,
error_status => p3_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p2_DWIDTH : integer := 32;
constant p3_DWIDTH : integer := 32;
constant p2_PORT_MODE : string := "RD_MODE";
constant p3_PORT_MODE : string := "WR_MODE";
signal p0_mcb_cmd_addr_o_int : std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 DOWNTO 0);
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 DOWNTO 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p2 Signal declarations
signal p2_tg_run_traffic : std_logic;
signal p2_tg_start_addr : std_logic_vector(31 downto 0);
signal p2_tg_end_addr : std_logic_vector(31 downto 0);
signal p2_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p2_tg_data_seed : std_logic_vector(31 downto 0);
signal p2_tg_load_seed : std_logic;
signal p2_tg_addr_mode : std_logic_vector(2 downto 0);
signal p2_tg_instr_mode : std_logic_vector(3 downto 0);
signal p2_tg_bl_mode : std_logic_vector(1 downto 0);
signal p2_tg_data_mode : std_logic_vector(3 downto 0);
signal p2_tg_mode_load : std_logic;
signal p2_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p2_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p2_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p2_error_status : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
signal p2_error : std_logic;
signal p2_cmp_error : std_logic;
signal p2_cmp_data : std_logic_vector(p2_DWIDTH-1 downto 0);
signal p2_cmp_data_valid : std_logic;
signal p2_mcb_cmd_en_o_int : std_logic;
signal p2_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p2_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p2_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p2_mcb_wr_en_o_int : std_logic;
--p3 Signal declarations
signal p3_tg_run_traffic : std_logic;
signal p3_tg_start_addr : std_logic_vector(31 downto 0);
signal p3_tg_end_addr : std_logic_vector(31 downto 0);
signal p3_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p3_tg_data_seed : std_logic_vector(31 downto 0);
signal p3_tg_load_seed : std_logic;
signal p3_tg_addr_mode : std_logic_vector(2 downto 0);
signal p3_tg_instr_mode : std_logic_vector(3 downto 0);
signal p3_tg_bl_mode : std_logic_vector(1 downto 0);
signal p3_tg_data_mode : std_logic_vector(3 downto 0);
signal p3_tg_mode_load : std_logic;
signal p3_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p3_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p3_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p3_error_status : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
signal p3_error : std_logic;
signal p3_cmp_error : std_logic;
signal p3_cmp_data : std_logic_vector(p3_DWIDTH-1 downto 0);
signal p3_cmp_data_valid : std_logic;
signal p3_mcb_cmd_en_o_int : std_logic;
signal p3_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p3_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p3_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p3_mcb_wr_en_o_int : std_logic;
signal p2_mcb_wr_en_o : std_logic;
signal p2_mcb_wr_full_i : std_logic;
signal p2_mcb_wr_data_o : std_logic_vector(31 downto 0);
signal p2_mcb_wr_mask_o : std_logic_vector(3 downto 0);
signal p2_mcb_wr_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_en_o : std_logic;
signal p3_mcb_rd_empty_i : std_logic;
signal p3_mcb_rd_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_data_i : std_logic_vector(31 downto 0);
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p2_cmp_error or p3_cmp_error;
error <= p2_error or p3_error;
error_status <= p2_error_status;
cmp_data <= p2_cmp_data(31 downto 0);
cmp_data_valid <= p2_cmp_data_valid;
p2_mcb_cmd_en_o <= p2_mcb_cmd_en_o_int;
p2_mcb_cmd_instr_o <= p2_mcb_cmd_instr_o_int;
p2_mcb_cmd_bl_o <= p2_mcb_cmd_bl_o_int;
p2_mcb_cmd_addr_o <= p2_mcb_cmd_addr_o_int;
p2_mcb_wr_en_o <= p2_mcb_wr_en_o_int;
init_mem_pattern_ctr_p2 :init_mem_pattern_ctr
generic map
(
DWIDTH => p2_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p2_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p2_error,
run_traffic_o => p2_tg_run_traffic,
start_addr_o => p2_tg_start_addr,
end_addr_o => p2_tg_end_addr ,
cmd_seed_o => p2_tg_cmd_seed ,
data_seed_o => p2_tg_data_seed ,
load_seed_o => p2_tg_load_seed ,
addr_mode_o => p2_tg_addr_mode ,
instr_mode_o => p2_tg_instr_mode ,
bl_mode_o => p2_tg_bl_mode ,
data_mode_o => p2_tg_data_mode ,
mode_load_o => p2_tg_mode_load ,
fixed_bl_o => p2_tg_fixed_bl ,
fixed_instr_o => p2_tg_fixed_instr,
fixed_addr_o => p2_tg_fixed_addr
);
m_traffic_gen_p2 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p2_PORT_MODE,
DWIDTH => p2_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p2_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p2_tg_start_addr ,
end_addr_i => p2_tg_end_addr ,
cmd_seed_i => p2_tg_cmd_seed ,
data_seed_i => p2_tg_data_seed ,
load_seed_i => p2_tg_load_seed,
addr_mode_i => p2_tg_addr_mode,
instr_mode_i => p2_tg_instr_mode ,
bl_mode_i => p2_tg_bl_mode ,
data_mode_i => p2_tg_data_mode ,
mode_load_i => p2_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p2_tg_fixed_bl,
fixed_instr_i => p2_tg_fixed_instr,
fixed_addr_i => p2_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p2_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p2_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p2_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p2_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p2_mcb_cmd_full_i,
mcb_wr_en_o => p2_mcb_wr_en_o_int,
mcb_wr_mask_o => p2_mcb_wr_mask_o,
mcb_wr_data_o => p2_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p2_mcb_wr_full_i,
mcb_wr_fifo_counts => p2_mcb_wr_fifo_counts,
mcb_rd_en_o => p2_mcb_rd_en_o,
mcb_rd_data_i => p2_mcb_rd_data_i,
mcb_rd_empty_i => p2_mcb_rd_empty_i,
mcb_rd_fifo_counts => p2_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p2_cmp_data,
cmp_data_valid => p2_cmp_data_valid,
cmp_error => p2_cmp_error,
error => p2_error,
error_status => p2_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p3_mcb_cmd_en_o <= p3_mcb_cmd_en_o_int;
p3_mcb_cmd_instr_o <= p3_mcb_cmd_instr_o_int;
p3_mcb_cmd_bl_o <= p3_mcb_cmd_bl_o_int;
p3_mcb_cmd_addr_o <= p3_mcb_cmd_addr_o_int;
p3_mcb_wr_en_o <= p3_mcb_wr_en_o_int;
init_mem_pattern_ctr_p3 :init_mem_pattern_ctr
generic map
(
DWIDTH => p3_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p3_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p3_error,
run_traffic_o => p3_tg_run_traffic,
start_addr_o => p3_tg_start_addr,
end_addr_o => p3_tg_end_addr ,
cmd_seed_o => p3_tg_cmd_seed ,
data_seed_o => p3_tg_data_seed ,
load_seed_o => p3_tg_load_seed ,
addr_mode_o => p3_tg_addr_mode ,
instr_mode_o => p3_tg_instr_mode ,
bl_mode_o => p3_tg_bl_mode ,
data_mode_o => p3_tg_data_mode ,
mode_load_o => p3_tg_mode_load ,
fixed_bl_o => p3_tg_fixed_bl ,
fixed_instr_o => p3_tg_fixed_instr,
fixed_addr_o => p3_tg_fixed_addr
);
m_traffic_gen_p3 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p3_PORT_MODE,
DWIDTH => p3_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p3_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p3_tg_start_addr ,
end_addr_i => p3_tg_end_addr ,
cmd_seed_i => p3_tg_cmd_seed ,
data_seed_i => p3_tg_data_seed ,
load_seed_i => p3_tg_load_seed,
addr_mode_i => p3_tg_addr_mode,
instr_mode_i => p3_tg_instr_mode ,
bl_mode_i => p3_tg_bl_mode ,
data_mode_i => p3_tg_data_mode ,
mode_load_i => p3_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p3_tg_fixed_bl,
fixed_instr_i => p3_tg_fixed_instr,
fixed_addr_i => p3_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p3_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p3_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p3_mcb_cmd_full_i,
mcb_wr_en_o => p3_mcb_wr_en_o_int,
mcb_wr_mask_o => p3_mcb_wr_mask_o,
mcb_wr_data_o => p3_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p3_mcb_wr_full_i,
mcb_wr_fifo_counts => p3_mcb_wr_fifo_counts,
mcb_rd_en_o => p3_mcb_rd_en_o,
mcb_rd_data_i => p3_mcb_rd_data_i,
mcb_rd_empty_i => p3_mcb_rd_empty_i,
mcb_rd_fifo_counts => p3_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p3_cmp_data,
cmp_data_valid => p3_cmp_data_valid,
cmp_error => p3_cmp_error,
error => p3_error,
error_status => p3_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p2_DWIDTH : integer := 32;
constant p3_DWIDTH : integer := 32;
constant p2_PORT_MODE : string := "RD_MODE";
constant p3_PORT_MODE : string := "WR_MODE";
signal p0_mcb_cmd_addr_o_int : std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 DOWNTO 0);
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 DOWNTO 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p2 Signal declarations
signal p2_tg_run_traffic : std_logic;
signal p2_tg_start_addr : std_logic_vector(31 downto 0);
signal p2_tg_end_addr : std_logic_vector(31 downto 0);
signal p2_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p2_tg_data_seed : std_logic_vector(31 downto 0);
signal p2_tg_load_seed : std_logic;
signal p2_tg_addr_mode : std_logic_vector(2 downto 0);
signal p2_tg_instr_mode : std_logic_vector(3 downto 0);
signal p2_tg_bl_mode : std_logic_vector(1 downto 0);
signal p2_tg_data_mode : std_logic_vector(3 downto 0);
signal p2_tg_mode_load : std_logic;
signal p2_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p2_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p2_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p2_error_status : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
signal p2_error : std_logic;
signal p2_cmp_error : std_logic;
signal p2_cmp_data : std_logic_vector(p2_DWIDTH-1 downto 0);
signal p2_cmp_data_valid : std_logic;
signal p2_mcb_cmd_en_o_int : std_logic;
signal p2_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p2_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p2_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p2_mcb_wr_en_o_int : std_logic;
--p3 Signal declarations
signal p3_tg_run_traffic : std_logic;
signal p3_tg_start_addr : std_logic_vector(31 downto 0);
signal p3_tg_end_addr : std_logic_vector(31 downto 0);
signal p3_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p3_tg_data_seed : std_logic_vector(31 downto 0);
signal p3_tg_load_seed : std_logic;
signal p3_tg_addr_mode : std_logic_vector(2 downto 0);
signal p3_tg_instr_mode : std_logic_vector(3 downto 0);
signal p3_tg_bl_mode : std_logic_vector(1 downto 0);
signal p3_tg_data_mode : std_logic_vector(3 downto 0);
signal p3_tg_mode_load : std_logic;
signal p3_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p3_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p3_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p3_error_status : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
signal p3_error : std_logic;
signal p3_cmp_error : std_logic;
signal p3_cmp_data : std_logic_vector(p3_DWIDTH-1 downto 0);
signal p3_cmp_data_valid : std_logic;
signal p3_mcb_cmd_en_o_int : std_logic;
signal p3_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p3_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p3_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p3_mcb_wr_en_o_int : std_logic;
signal p2_mcb_wr_en_o : std_logic;
signal p2_mcb_wr_full_i : std_logic;
signal p2_mcb_wr_data_o : std_logic_vector(31 downto 0);
signal p2_mcb_wr_mask_o : std_logic_vector(3 downto 0);
signal p2_mcb_wr_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_en_o : std_logic;
signal p3_mcb_rd_empty_i : std_logic;
signal p3_mcb_rd_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_data_i : std_logic_vector(31 downto 0);
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p2_cmp_error or p3_cmp_error;
error <= p2_error or p3_error;
error_status <= p2_error_status;
cmp_data <= p2_cmp_data(31 downto 0);
cmp_data_valid <= p2_cmp_data_valid;
p2_mcb_cmd_en_o <= p2_mcb_cmd_en_o_int;
p2_mcb_cmd_instr_o <= p2_mcb_cmd_instr_o_int;
p2_mcb_cmd_bl_o <= p2_mcb_cmd_bl_o_int;
p2_mcb_cmd_addr_o <= p2_mcb_cmd_addr_o_int;
p2_mcb_wr_en_o <= p2_mcb_wr_en_o_int;
init_mem_pattern_ctr_p2 :init_mem_pattern_ctr
generic map
(
DWIDTH => p2_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p2_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p2_error,
run_traffic_o => p2_tg_run_traffic,
start_addr_o => p2_tg_start_addr,
end_addr_o => p2_tg_end_addr ,
cmd_seed_o => p2_tg_cmd_seed ,
data_seed_o => p2_tg_data_seed ,
load_seed_o => p2_tg_load_seed ,
addr_mode_o => p2_tg_addr_mode ,
instr_mode_o => p2_tg_instr_mode ,
bl_mode_o => p2_tg_bl_mode ,
data_mode_o => p2_tg_data_mode ,
mode_load_o => p2_tg_mode_load ,
fixed_bl_o => p2_tg_fixed_bl ,
fixed_instr_o => p2_tg_fixed_instr,
fixed_addr_o => p2_tg_fixed_addr
);
m_traffic_gen_p2 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p2_PORT_MODE,
DWIDTH => p2_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p2_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p2_tg_start_addr ,
end_addr_i => p2_tg_end_addr ,
cmd_seed_i => p2_tg_cmd_seed ,
data_seed_i => p2_tg_data_seed ,
load_seed_i => p2_tg_load_seed,
addr_mode_i => p2_tg_addr_mode,
instr_mode_i => p2_tg_instr_mode ,
bl_mode_i => p2_tg_bl_mode ,
data_mode_i => p2_tg_data_mode ,
mode_load_i => p2_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p2_tg_fixed_bl,
fixed_instr_i => p2_tg_fixed_instr,
fixed_addr_i => p2_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p2_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p2_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p2_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p2_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p2_mcb_cmd_full_i,
mcb_wr_en_o => p2_mcb_wr_en_o_int,
mcb_wr_mask_o => p2_mcb_wr_mask_o,
mcb_wr_data_o => p2_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p2_mcb_wr_full_i,
mcb_wr_fifo_counts => p2_mcb_wr_fifo_counts,
mcb_rd_en_o => p2_mcb_rd_en_o,
mcb_rd_data_i => p2_mcb_rd_data_i,
mcb_rd_empty_i => p2_mcb_rd_empty_i,
mcb_rd_fifo_counts => p2_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p2_cmp_data,
cmp_data_valid => p2_cmp_data_valid,
cmp_error => p2_cmp_error,
error => p2_error,
error_status => p2_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p3_mcb_cmd_en_o <= p3_mcb_cmd_en_o_int;
p3_mcb_cmd_instr_o <= p3_mcb_cmd_instr_o_int;
p3_mcb_cmd_bl_o <= p3_mcb_cmd_bl_o_int;
p3_mcb_cmd_addr_o <= p3_mcb_cmd_addr_o_int;
p3_mcb_wr_en_o <= p3_mcb_wr_en_o_int;
init_mem_pattern_ctr_p3 :init_mem_pattern_ctr
generic map
(
DWIDTH => p3_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p3_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p3_error,
run_traffic_o => p3_tg_run_traffic,
start_addr_o => p3_tg_start_addr,
end_addr_o => p3_tg_end_addr ,
cmd_seed_o => p3_tg_cmd_seed ,
data_seed_o => p3_tg_data_seed ,
load_seed_o => p3_tg_load_seed ,
addr_mode_o => p3_tg_addr_mode ,
instr_mode_o => p3_tg_instr_mode ,
bl_mode_o => p3_tg_bl_mode ,
data_mode_o => p3_tg_data_mode ,
mode_load_o => p3_tg_mode_load ,
fixed_bl_o => p3_tg_fixed_bl ,
fixed_instr_o => p3_tg_fixed_instr,
fixed_addr_o => p3_tg_fixed_addr
);
m_traffic_gen_p3 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p3_PORT_MODE,
DWIDTH => p3_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p3_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p3_tg_start_addr ,
end_addr_i => p3_tg_end_addr ,
cmd_seed_i => p3_tg_cmd_seed ,
data_seed_i => p3_tg_data_seed ,
load_seed_i => p3_tg_load_seed,
addr_mode_i => p3_tg_addr_mode,
instr_mode_i => p3_tg_instr_mode ,
bl_mode_i => p3_tg_bl_mode ,
data_mode_i => p3_tg_data_mode ,
mode_load_i => p3_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p3_tg_fixed_bl,
fixed_instr_i => p3_tg_fixed_instr,
fixed_addr_i => p3_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p3_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p3_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p3_mcb_cmd_full_i,
mcb_wr_en_o => p3_mcb_wr_en_o_int,
mcb_wr_mask_o => p3_mcb_wr_mask_o,
mcb_wr_data_o => p3_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p3_mcb_wr_full_i,
mcb_wr_fifo_counts => p3_mcb_wr_fifo_counts,
mcb_rd_en_o => p3_mcb_rd_en_o,
mcb_rd_data_i => p3_mcb_rd_data_i,
mcb_rd_empty_i => p3_mcb_rd_empty_i,
mcb_rd_fifo_counts => p3_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p3_cmp_data,
cmp_data_valid => p3_cmp_data_valid,
cmp_error => p3_cmp_error,
error => p3_error,
error_status => p3_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p2_DWIDTH : integer := 32;
constant p3_DWIDTH : integer := 32;
constant p2_PORT_MODE : string := "RD_MODE";
constant p3_PORT_MODE : string := "WR_MODE";
signal p0_mcb_cmd_addr_o_int : std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 DOWNTO 0);
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 DOWNTO 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p2 Signal declarations
signal p2_tg_run_traffic : std_logic;
signal p2_tg_start_addr : std_logic_vector(31 downto 0);
signal p2_tg_end_addr : std_logic_vector(31 downto 0);
signal p2_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p2_tg_data_seed : std_logic_vector(31 downto 0);
signal p2_tg_load_seed : std_logic;
signal p2_tg_addr_mode : std_logic_vector(2 downto 0);
signal p2_tg_instr_mode : std_logic_vector(3 downto 0);
signal p2_tg_bl_mode : std_logic_vector(1 downto 0);
signal p2_tg_data_mode : std_logic_vector(3 downto 0);
signal p2_tg_mode_load : std_logic;
signal p2_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p2_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p2_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p2_error_status : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
signal p2_error : std_logic;
signal p2_cmp_error : std_logic;
signal p2_cmp_data : std_logic_vector(p2_DWIDTH-1 downto 0);
signal p2_cmp_data_valid : std_logic;
signal p2_mcb_cmd_en_o_int : std_logic;
signal p2_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p2_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p2_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p2_mcb_wr_en_o_int : std_logic;
--p3 Signal declarations
signal p3_tg_run_traffic : std_logic;
signal p3_tg_start_addr : std_logic_vector(31 downto 0);
signal p3_tg_end_addr : std_logic_vector(31 downto 0);
signal p3_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p3_tg_data_seed : std_logic_vector(31 downto 0);
signal p3_tg_load_seed : std_logic;
signal p3_tg_addr_mode : std_logic_vector(2 downto 0);
signal p3_tg_instr_mode : std_logic_vector(3 downto 0);
signal p3_tg_bl_mode : std_logic_vector(1 downto 0);
signal p3_tg_data_mode : std_logic_vector(3 downto 0);
signal p3_tg_mode_load : std_logic;
signal p3_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p3_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p3_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p3_error_status : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
signal p3_error : std_logic;
signal p3_cmp_error : std_logic;
signal p3_cmp_data : std_logic_vector(p3_DWIDTH-1 downto 0);
signal p3_cmp_data_valid : std_logic;
signal p3_mcb_cmd_en_o_int : std_logic;
signal p3_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p3_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p3_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p3_mcb_wr_en_o_int : std_logic;
signal p2_mcb_wr_en_o : std_logic;
signal p2_mcb_wr_full_i : std_logic;
signal p2_mcb_wr_data_o : std_logic_vector(31 downto 0);
signal p2_mcb_wr_mask_o : std_logic_vector(3 downto 0);
signal p2_mcb_wr_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_en_o : std_logic;
signal p3_mcb_rd_empty_i : std_logic;
signal p3_mcb_rd_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_data_i : std_logic_vector(31 downto 0);
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p2_cmp_error or p3_cmp_error;
error <= p2_error or p3_error;
error_status <= p2_error_status;
cmp_data <= p2_cmp_data(31 downto 0);
cmp_data_valid <= p2_cmp_data_valid;
p2_mcb_cmd_en_o <= p2_mcb_cmd_en_o_int;
p2_mcb_cmd_instr_o <= p2_mcb_cmd_instr_o_int;
p2_mcb_cmd_bl_o <= p2_mcb_cmd_bl_o_int;
p2_mcb_cmd_addr_o <= p2_mcb_cmd_addr_o_int;
p2_mcb_wr_en_o <= p2_mcb_wr_en_o_int;
init_mem_pattern_ctr_p2 :init_mem_pattern_ctr
generic map
(
DWIDTH => p2_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p2_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p2_error,
run_traffic_o => p2_tg_run_traffic,
start_addr_o => p2_tg_start_addr,
end_addr_o => p2_tg_end_addr ,
cmd_seed_o => p2_tg_cmd_seed ,
data_seed_o => p2_tg_data_seed ,
load_seed_o => p2_tg_load_seed ,
addr_mode_o => p2_tg_addr_mode ,
instr_mode_o => p2_tg_instr_mode ,
bl_mode_o => p2_tg_bl_mode ,
data_mode_o => p2_tg_data_mode ,
mode_load_o => p2_tg_mode_load ,
fixed_bl_o => p2_tg_fixed_bl ,
fixed_instr_o => p2_tg_fixed_instr,
fixed_addr_o => p2_tg_fixed_addr
);
m_traffic_gen_p2 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p2_PORT_MODE,
DWIDTH => p2_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p2_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p2_tg_start_addr ,
end_addr_i => p2_tg_end_addr ,
cmd_seed_i => p2_tg_cmd_seed ,
data_seed_i => p2_tg_data_seed ,
load_seed_i => p2_tg_load_seed,
addr_mode_i => p2_tg_addr_mode,
instr_mode_i => p2_tg_instr_mode ,
bl_mode_i => p2_tg_bl_mode ,
data_mode_i => p2_tg_data_mode ,
mode_load_i => p2_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p2_tg_fixed_bl,
fixed_instr_i => p2_tg_fixed_instr,
fixed_addr_i => p2_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p2_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p2_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p2_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p2_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p2_mcb_cmd_full_i,
mcb_wr_en_o => p2_mcb_wr_en_o_int,
mcb_wr_mask_o => p2_mcb_wr_mask_o,
mcb_wr_data_o => p2_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p2_mcb_wr_full_i,
mcb_wr_fifo_counts => p2_mcb_wr_fifo_counts,
mcb_rd_en_o => p2_mcb_rd_en_o,
mcb_rd_data_i => p2_mcb_rd_data_i,
mcb_rd_empty_i => p2_mcb_rd_empty_i,
mcb_rd_fifo_counts => p2_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p2_cmp_data,
cmp_data_valid => p2_cmp_data_valid,
cmp_error => p2_cmp_error,
error => p2_error,
error_status => p2_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p3_mcb_cmd_en_o <= p3_mcb_cmd_en_o_int;
p3_mcb_cmd_instr_o <= p3_mcb_cmd_instr_o_int;
p3_mcb_cmd_bl_o <= p3_mcb_cmd_bl_o_int;
p3_mcb_cmd_addr_o <= p3_mcb_cmd_addr_o_int;
p3_mcb_wr_en_o <= p3_mcb_wr_en_o_int;
init_mem_pattern_ctr_p3 :init_mem_pattern_ctr
generic map
(
DWIDTH => p3_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p3_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p3_error,
run_traffic_o => p3_tg_run_traffic,
start_addr_o => p3_tg_start_addr,
end_addr_o => p3_tg_end_addr ,
cmd_seed_o => p3_tg_cmd_seed ,
data_seed_o => p3_tg_data_seed ,
load_seed_o => p3_tg_load_seed ,
addr_mode_o => p3_tg_addr_mode ,
instr_mode_o => p3_tg_instr_mode ,
bl_mode_o => p3_tg_bl_mode ,
data_mode_o => p3_tg_data_mode ,
mode_load_o => p3_tg_mode_load ,
fixed_bl_o => p3_tg_fixed_bl ,
fixed_instr_o => p3_tg_fixed_instr,
fixed_addr_o => p3_tg_fixed_addr
);
m_traffic_gen_p3 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p3_PORT_MODE,
DWIDTH => p3_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p3_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p3_tg_start_addr ,
end_addr_i => p3_tg_end_addr ,
cmd_seed_i => p3_tg_cmd_seed ,
data_seed_i => p3_tg_data_seed ,
load_seed_i => p3_tg_load_seed,
addr_mode_i => p3_tg_addr_mode,
instr_mode_i => p3_tg_instr_mode ,
bl_mode_i => p3_tg_bl_mode ,
data_mode_i => p3_tg_data_mode ,
mode_load_i => p3_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p3_tg_fixed_bl,
fixed_instr_i => p3_tg_fixed_instr,
fixed_addr_i => p3_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p3_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p3_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p3_mcb_cmd_full_i,
mcb_wr_en_o => p3_mcb_wr_en_o_int,
mcb_wr_mask_o => p3_mcb_wr_mask_o,
mcb_wr_data_o => p3_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p3_mcb_wr_full_i,
mcb_wr_fifo_counts => p3_mcb_wr_fifo_counts,
mcb_rd_en_o => p3_mcb_rd_en_o,
mcb_rd_data_i => p3_mcb_rd_data_i,
mcb_rd_empty_i => p3_mcb_rd_empty_i,
mcb_rd_fifo_counts => p3_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p3_cmp_data,
cmp_data_valid => p3_cmp_data_valid,
cmp_error => p3_cmp_error,
error => p3_error,
error_status => p3_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p2_DWIDTH : integer := 32;
constant p3_DWIDTH : integer := 32;
constant p2_PORT_MODE : string := "RD_MODE";
constant p3_PORT_MODE : string := "WR_MODE";
signal p0_mcb_cmd_addr_o_int : std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 DOWNTO 0);
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 DOWNTO 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p2 Signal declarations
signal p2_tg_run_traffic : std_logic;
signal p2_tg_start_addr : std_logic_vector(31 downto 0);
signal p2_tg_end_addr : std_logic_vector(31 downto 0);
signal p2_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p2_tg_data_seed : std_logic_vector(31 downto 0);
signal p2_tg_load_seed : std_logic;
signal p2_tg_addr_mode : std_logic_vector(2 downto 0);
signal p2_tg_instr_mode : std_logic_vector(3 downto 0);
signal p2_tg_bl_mode : std_logic_vector(1 downto 0);
signal p2_tg_data_mode : std_logic_vector(3 downto 0);
signal p2_tg_mode_load : std_logic;
signal p2_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p2_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p2_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p2_error_status : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
signal p2_error : std_logic;
signal p2_cmp_error : std_logic;
signal p2_cmp_data : std_logic_vector(p2_DWIDTH-1 downto 0);
signal p2_cmp_data_valid : std_logic;
signal p2_mcb_cmd_en_o_int : std_logic;
signal p2_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p2_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p2_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p2_mcb_wr_en_o_int : std_logic;
--p3 Signal declarations
signal p3_tg_run_traffic : std_logic;
signal p3_tg_start_addr : std_logic_vector(31 downto 0);
signal p3_tg_end_addr : std_logic_vector(31 downto 0);
signal p3_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p3_tg_data_seed : std_logic_vector(31 downto 0);
signal p3_tg_load_seed : std_logic;
signal p3_tg_addr_mode : std_logic_vector(2 downto 0);
signal p3_tg_instr_mode : std_logic_vector(3 downto 0);
signal p3_tg_bl_mode : std_logic_vector(1 downto 0);
signal p3_tg_data_mode : std_logic_vector(3 downto 0);
signal p3_tg_mode_load : std_logic;
signal p3_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p3_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p3_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p3_error_status : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
signal p3_error : std_logic;
signal p3_cmp_error : std_logic;
signal p3_cmp_data : std_logic_vector(p3_DWIDTH-1 downto 0);
signal p3_cmp_data_valid : std_logic;
signal p3_mcb_cmd_en_o_int : std_logic;
signal p3_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p3_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p3_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p3_mcb_wr_en_o_int : std_logic;
signal p2_mcb_wr_en_o : std_logic;
signal p2_mcb_wr_full_i : std_logic;
signal p2_mcb_wr_data_o : std_logic_vector(31 downto 0);
signal p2_mcb_wr_mask_o : std_logic_vector(3 downto 0);
signal p2_mcb_wr_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_en_o : std_logic;
signal p3_mcb_rd_empty_i : std_logic;
signal p3_mcb_rd_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_data_i : std_logic_vector(31 downto 0);
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p2_cmp_error or p3_cmp_error;
error <= p2_error or p3_error;
error_status <= p2_error_status;
cmp_data <= p2_cmp_data(31 downto 0);
cmp_data_valid <= p2_cmp_data_valid;
p2_mcb_cmd_en_o <= p2_mcb_cmd_en_o_int;
p2_mcb_cmd_instr_o <= p2_mcb_cmd_instr_o_int;
p2_mcb_cmd_bl_o <= p2_mcb_cmd_bl_o_int;
p2_mcb_cmd_addr_o <= p2_mcb_cmd_addr_o_int;
p2_mcb_wr_en_o <= p2_mcb_wr_en_o_int;
init_mem_pattern_ctr_p2 :init_mem_pattern_ctr
generic map
(
DWIDTH => p2_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p2_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p2_error,
run_traffic_o => p2_tg_run_traffic,
start_addr_o => p2_tg_start_addr,
end_addr_o => p2_tg_end_addr ,
cmd_seed_o => p2_tg_cmd_seed ,
data_seed_o => p2_tg_data_seed ,
load_seed_o => p2_tg_load_seed ,
addr_mode_o => p2_tg_addr_mode ,
instr_mode_o => p2_tg_instr_mode ,
bl_mode_o => p2_tg_bl_mode ,
data_mode_o => p2_tg_data_mode ,
mode_load_o => p2_tg_mode_load ,
fixed_bl_o => p2_tg_fixed_bl ,
fixed_instr_o => p2_tg_fixed_instr,
fixed_addr_o => p2_tg_fixed_addr
);
m_traffic_gen_p2 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p2_PORT_MODE,
DWIDTH => p2_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p2_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p2_tg_start_addr ,
end_addr_i => p2_tg_end_addr ,
cmd_seed_i => p2_tg_cmd_seed ,
data_seed_i => p2_tg_data_seed ,
load_seed_i => p2_tg_load_seed,
addr_mode_i => p2_tg_addr_mode,
instr_mode_i => p2_tg_instr_mode ,
bl_mode_i => p2_tg_bl_mode ,
data_mode_i => p2_tg_data_mode ,
mode_load_i => p2_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p2_tg_fixed_bl,
fixed_instr_i => p2_tg_fixed_instr,
fixed_addr_i => p2_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p2_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p2_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p2_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p2_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p2_mcb_cmd_full_i,
mcb_wr_en_o => p2_mcb_wr_en_o_int,
mcb_wr_mask_o => p2_mcb_wr_mask_o,
mcb_wr_data_o => p2_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p2_mcb_wr_full_i,
mcb_wr_fifo_counts => p2_mcb_wr_fifo_counts,
mcb_rd_en_o => p2_mcb_rd_en_o,
mcb_rd_data_i => p2_mcb_rd_data_i,
mcb_rd_empty_i => p2_mcb_rd_empty_i,
mcb_rd_fifo_counts => p2_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p2_cmp_data,
cmp_data_valid => p2_cmp_data_valid,
cmp_error => p2_cmp_error,
error => p2_error,
error_status => p2_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p3_mcb_cmd_en_o <= p3_mcb_cmd_en_o_int;
p3_mcb_cmd_instr_o <= p3_mcb_cmd_instr_o_int;
p3_mcb_cmd_bl_o <= p3_mcb_cmd_bl_o_int;
p3_mcb_cmd_addr_o <= p3_mcb_cmd_addr_o_int;
p3_mcb_wr_en_o <= p3_mcb_wr_en_o_int;
init_mem_pattern_ctr_p3 :init_mem_pattern_ctr
generic map
(
DWIDTH => p3_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p3_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p3_error,
run_traffic_o => p3_tg_run_traffic,
start_addr_o => p3_tg_start_addr,
end_addr_o => p3_tg_end_addr ,
cmd_seed_o => p3_tg_cmd_seed ,
data_seed_o => p3_tg_data_seed ,
load_seed_o => p3_tg_load_seed ,
addr_mode_o => p3_tg_addr_mode ,
instr_mode_o => p3_tg_instr_mode ,
bl_mode_o => p3_tg_bl_mode ,
data_mode_o => p3_tg_data_mode ,
mode_load_o => p3_tg_mode_load ,
fixed_bl_o => p3_tg_fixed_bl ,
fixed_instr_o => p3_tg_fixed_instr,
fixed_addr_o => p3_tg_fixed_addr
);
m_traffic_gen_p3 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p3_PORT_MODE,
DWIDTH => p3_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p3_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p3_tg_start_addr ,
end_addr_i => p3_tg_end_addr ,
cmd_seed_i => p3_tg_cmd_seed ,
data_seed_i => p3_tg_data_seed ,
load_seed_i => p3_tg_load_seed,
addr_mode_i => p3_tg_addr_mode,
instr_mode_i => p3_tg_instr_mode ,
bl_mode_i => p3_tg_bl_mode ,
data_mode_i => p3_tg_data_mode ,
mode_load_i => p3_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p3_tg_fixed_bl,
fixed_instr_i => p3_tg_fixed_instr,
fixed_addr_i => p3_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p3_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p3_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p3_mcb_cmd_full_i,
mcb_wr_en_o => p3_mcb_wr_en_o_int,
mcb_wr_mask_o => p3_mcb_wr_mask_o,
mcb_wr_data_o => p3_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p3_mcb_wr_full_i,
mcb_wr_fifo_counts => p3_mcb_wr_fifo_counts,
mcb_rd_en_o => p3_mcb_rd_en_o,
mcb_rd_data_i => p3_mcb_rd_data_i,
mcb_rd_empty_i => p3_mcb_rd_empty_i,
mcb_rd_fifo_counts => p3_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p3_cmp_data,
cmp_data_valid => p3_cmp_data_valid,
cmp_error => p3_cmp_error,
error => p3_error,
error_status => p3_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p2_DWIDTH : integer := 32;
constant p3_DWIDTH : integer := 32;
constant p2_PORT_MODE : string := "RD_MODE";
constant p3_PORT_MODE : string := "WR_MODE";
signal p0_mcb_cmd_addr_o_int : std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 DOWNTO 0);
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 DOWNTO 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p2 Signal declarations
signal p2_tg_run_traffic : std_logic;
signal p2_tg_start_addr : std_logic_vector(31 downto 0);
signal p2_tg_end_addr : std_logic_vector(31 downto 0);
signal p2_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p2_tg_data_seed : std_logic_vector(31 downto 0);
signal p2_tg_load_seed : std_logic;
signal p2_tg_addr_mode : std_logic_vector(2 downto 0);
signal p2_tg_instr_mode : std_logic_vector(3 downto 0);
signal p2_tg_bl_mode : std_logic_vector(1 downto 0);
signal p2_tg_data_mode : std_logic_vector(3 downto 0);
signal p2_tg_mode_load : std_logic;
signal p2_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p2_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p2_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p2_error_status : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
signal p2_error : std_logic;
signal p2_cmp_error : std_logic;
signal p2_cmp_data : std_logic_vector(p2_DWIDTH-1 downto 0);
signal p2_cmp_data_valid : std_logic;
signal p2_mcb_cmd_en_o_int : std_logic;
signal p2_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p2_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p2_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p2_mcb_wr_en_o_int : std_logic;
--p3 Signal declarations
signal p3_tg_run_traffic : std_logic;
signal p3_tg_start_addr : std_logic_vector(31 downto 0);
signal p3_tg_end_addr : std_logic_vector(31 downto 0);
signal p3_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p3_tg_data_seed : std_logic_vector(31 downto 0);
signal p3_tg_load_seed : std_logic;
signal p3_tg_addr_mode : std_logic_vector(2 downto 0);
signal p3_tg_instr_mode : std_logic_vector(3 downto 0);
signal p3_tg_bl_mode : std_logic_vector(1 downto 0);
signal p3_tg_data_mode : std_logic_vector(3 downto 0);
signal p3_tg_mode_load : std_logic;
signal p3_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p3_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p3_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p3_error_status : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
signal p3_error : std_logic;
signal p3_cmp_error : std_logic;
signal p3_cmp_data : std_logic_vector(p3_DWIDTH-1 downto 0);
signal p3_cmp_data_valid : std_logic;
signal p3_mcb_cmd_en_o_int : std_logic;
signal p3_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p3_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p3_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p3_mcb_wr_en_o_int : std_logic;
signal p2_mcb_wr_en_o : std_logic;
signal p2_mcb_wr_full_i : std_logic;
signal p2_mcb_wr_data_o : std_logic_vector(31 downto 0);
signal p2_mcb_wr_mask_o : std_logic_vector(3 downto 0);
signal p2_mcb_wr_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_en_o : std_logic;
signal p3_mcb_rd_empty_i : std_logic;
signal p3_mcb_rd_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_data_i : std_logic_vector(31 downto 0);
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p2_cmp_error or p3_cmp_error;
error <= p2_error or p3_error;
error_status <= p2_error_status;
cmp_data <= p2_cmp_data(31 downto 0);
cmp_data_valid <= p2_cmp_data_valid;
p2_mcb_cmd_en_o <= p2_mcb_cmd_en_o_int;
p2_mcb_cmd_instr_o <= p2_mcb_cmd_instr_o_int;
p2_mcb_cmd_bl_o <= p2_mcb_cmd_bl_o_int;
p2_mcb_cmd_addr_o <= p2_mcb_cmd_addr_o_int;
p2_mcb_wr_en_o <= p2_mcb_wr_en_o_int;
init_mem_pattern_ctr_p2 :init_mem_pattern_ctr
generic map
(
DWIDTH => p2_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p2_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p2_error,
run_traffic_o => p2_tg_run_traffic,
start_addr_o => p2_tg_start_addr,
end_addr_o => p2_tg_end_addr ,
cmd_seed_o => p2_tg_cmd_seed ,
data_seed_o => p2_tg_data_seed ,
load_seed_o => p2_tg_load_seed ,
addr_mode_o => p2_tg_addr_mode ,
instr_mode_o => p2_tg_instr_mode ,
bl_mode_o => p2_tg_bl_mode ,
data_mode_o => p2_tg_data_mode ,
mode_load_o => p2_tg_mode_load ,
fixed_bl_o => p2_tg_fixed_bl ,
fixed_instr_o => p2_tg_fixed_instr,
fixed_addr_o => p2_tg_fixed_addr
);
m_traffic_gen_p2 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p2_PORT_MODE,
DWIDTH => p2_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p2_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p2_tg_start_addr ,
end_addr_i => p2_tg_end_addr ,
cmd_seed_i => p2_tg_cmd_seed ,
data_seed_i => p2_tg_data_seed ,
load_seed_i => p2_tg_load_seed,
addr_mode_i => p2_tg_addr_mode,
instr_mode_i => p2_tg_instr_mode ,
bl_mode_i => p2_tg_bl_mode ,
data_mode_i => p2_tg_data_mode ,
mode_load_i => p2_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p2_tg_fixed_bl,
fixed_instr_i => p2_tg_fixed_instr,
fixed_addr_i => p2_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p2_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p2_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p2_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p2_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p2_mcb_cmd_full_i,
mcb_wr_en_o => p2_mcb_wr_en_o_int,
mcb_wr_mask_o => p2_mcb_wr_mask_o,
mcb_wr_data_o => p2_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p2_mcb_wr_full_i,
mcb_wr_fifo_counts => p2_mcb_wr_fifo_counts,
mcb_rd_en_o => p2_mcb_rd_en_o,
mcb_rd_data_i => p2_mcb_rd_data_i,
mcb_rd_empty_i => p2_mcb_rd_empty_i,
mcb_rd_fifo_counts => p2_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p2_cmp_data,
cmp_data_valid => p2_cmp_data_valid,
cmp_error => p2_cmp_error,
error => p2_error,
error_status => p2_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p3_mcb_cmd_en_o <= p3_mcb_cmd_en_o_int;
p3_mcb_cmd_instr_o <= p3_mcb_cmd_instr_o_int;
p3_mcb_cmd_bl_o <= p3_mcb_cmd_bl_o_int;
p3_mcb_cmd_addr_o <= p3_mcb_cmd_addr_o_int;
p3_mcb_wr_en_o <= p3_mcb_wr_en_o_int;
init_mem_pattern_ctr_p3 :init_mem_pattern_ctr
generic map
(
DWIDTH => p3_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p3_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p3_error,
run_traffic_o => p3_tg_run_traffic,
start_addr_o => p3_tg_start_addr,
end_addr_o => p3_tg_end_addr ,
cmd_seed_o => p3_tg_cmd_seed ,
data_seed_o => p3_tg_data_seed ,
load_seed_o => p3_tg_load_seed ,
addr_mode_o => p3_tg_addr_mode ,
instr_mode_o => p3_tg_instr_mode ,
bl_mode_o => p3_tg_bl_mode ,
data_mode_o => p3_tg_data_mode ,
mode_load_o => p3_tg_mode_load ,
fixed_bl_o => p3_tg_fixed_bl ,
fixed_instr_o => p3_tg_fixed_instr,
fixed_addr_o => p3_tg_fixed_addr
);
m_traffic_gen_p3 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p3_PORT_MODE,
DWIDTH => p3_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p3_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p3_tg_start_addr ,
end_addr_i => p3_tg_end_addr ,
cmd_seed_i => p3_tg_cmd_seed ,
data_seed_i => p3_tg_data_seed ,
load_seed_i => p3_tg_load_seed,
addr_mode_i => p3_tg_addr_mode,
instr_mode_i => p3_tg_instr_mode ,
bl_mode_i => p3_tg_bl_mode ,
data_mode_i => p3_tg_data_mode ,
mode_load_i => p3_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p3_tg_fixed_bl,
fixed_instr_i => p3_tg_fixed_instr,
fixed_addr_i => p3_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p3_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p3_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p3_mcb_cmd_full_i,
mcb_wr_en_o => p3_mcb_wr_en_o_int,
mcb_wr_mask_o => p3_mcb_wr_mask_o,
mcb_wr_data_o => p3_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p3_mcb_wr_full_i,
mcb_wr_fifo_counts => p3_mcb_wr_fifo_counts,
mcb_rd_en_o => p3_mcb_rd_en_o,
mcb_rd_data_i => p3_mcb_rd_data_i,
mcb_rd_empty_i => p3_mcb_rd_empty_i,
mcb_rd_fifo_counts => p3_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p3_cmp_data,
cmp_data_valid => p3_cmp_data_valid,
cmp_error => p3_cmp_error,
error => p3_error,
error_status => p3_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ksoqXXpoADBgea3cNs3hm32MbN+7E2PpkazvHBg3S/blvhmlKCaLNgapz5Djadl75Erlr3L8Vfwz
r/53tldjtA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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Sh5p5Bmfw6TMgF8iGAg=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6592)
`protect data_block
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bM++puPxF7S5fkZtJFwaHCalaWeT4n1bN1sgLDdGDp1p+PwE1dJb5AbGd2Z/pC0/mNPDulTVZ/zt
nBlzl/CF4YKAG6Sz741hEKJLQKT6mLRhSqAtNaKcQSwXktbs5Xx1MmAJ8cqC0DPjFRe1pgAEmcA4
+9ACp06MHmSooOLWCK+AORFResmWqSK0HIhzE2pLmJlGgv6gYh75sjLl7Ih4exIoWvasBMObEO/4
+DByudCpkmupMT8myYB4/PMTuckUU7uBB5hvnEQG81wat0TcYXYwm4f25Gz1Yho+W46iSVXqHczY
WRyY9T2QSpi1qaiXH8b77+Jypcuo8SGhyKI0wEa9d6PfmQriyrEs9w++/60kjkzdTVsycUPHveTr
XmxTpN1kQ57l7t9qwTD5eKq6vHdil4PYlXUioWldi2P2Kfp3EmBs9NXZkleBdQH1WpAgPAgaZzIT
Koe2WVEj6TyNobpWMtftIY55kbhv//f80fmeKkGBBQeLb7EoDhuEJEzwq9VOA9fCnHcDgDZZPvhm
eCNmrnXUD0b87d5Kr6ShDb5dSaF69Hw6b2B4fXhelg77ywWKXQTJGy3s3YIfGVLIkY1ETsH30JF4
CrijEbJU7d2oMf26BCz+E5lvZz2kOUUG6eBqrIs1rLISDBEVn/TnW/KGVM01wcNc+ObaoBvqo4To
qK+9D3dfBNFq1K5dGWZlQnHvYyYl+B7AlvULy4T4/qmITEcPrHZB/KjikKow3LogPZIE0XtfRGzv
1f8d0OyxaM1zBwj47bV2kku6PuX/DKCunIeGp9BgJPnjvYX6ZDrsYGL3npbqYZbi80EVexH9/Od9
pSwBzwfTNhv6UH5AW2kxkxJXOLMBAY3mXY16feheZPwF2kLWpw==
`protect end_protected
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY CHOPLIFTER IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END CHOPLIFTER;
ARCHITECTURE CHOPLIFTER_arch OF CHOPLIFTER IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF CHOPLIFTER_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF CHOPLIFTER_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF CHOPLIFTER_arch : ARCHITECTURE IS "CHOPLIFTER,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF CHOPLIFTER_arch: ARCHITECTURE IS "CHOPLIFTER,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=CHOPLIFTER.mif,C_INIT_FILE=CHOPLIFTER.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=32768,C_READ_DEPTH_A=32768,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=32768,C_READ_DEPTH_B=32768,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "CHOPLIFTER.mif",
C_INIT_FILE => "CHOPLIFTER.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 32768,
C_READ_DEPTH_A => 32768,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 32768,
C_READ_DEPTH_B => 32768,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END CHOPLIFTER_arch;
|
-- *****************************************************************************************
-- Standard libraries
-- Version 0.2
-- Modified 02.12.2006
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package std_library is
type log2array_type is array(0 to 1024) of integer;
constant fn_log2 : log2array_type := (
0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
others => 10);
constant fn_log2x : log2array_type := (
0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
others => 10);
-- *********************************************************************************
function fn_det_x(d : std_logic_vector) return boolean;
function fn_det_x(d : std_logic) return boolean;
function fn_xor_vect(vect : std_logic_vector) return std_logic;
function fn_or_vect(vect : std_logic_vector) return std_logic;
function fn_and_vect(vect : std_logic_vector) return std_logic;
function fn_to_integer(vect : std_logic_vector) return integer;
function fn_to_integer(d : std_logic) return integer;
function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector;
function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector;
function fn_to_std_logic(b : boolean) return std_logic;
function fn_dcd(vect : std_logic_vector) return std_logic_vector;
function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic;
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector;
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector;
function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector;
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector;
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector;
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector;
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector;
end std_library;
package body std_library is
function fn_det_x(d : std_logic_vector) return boolean is
variable result : boolean;
begin
result := FALSE;
-- pragma translate_off
result := is_x(d);
-- pragma translate_on
return (result);
end fn_det_x;
function fn_det_x(d : std_logic) return boolean is
variable result : boolean;
begin
result := FALSE;
-- pragma translate_off
result := is_x(d);
-- pragma translate_on
return (result);
end fn_det_x;
function fn_xor_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '0';
for i in vect'range loop
temp := temp xor vect(i);
end loop;
return(temp);
end fn_xor_vect;
function fn_or_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '0';
for i in vect'range loop
temp := temp or vect(i);
end loop;
return(temp);
end fn_or_vect;
function fn_and_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '1';
for i in vect'range loop
temp := temp and vect(i);
end loop;
return(temp);
end fn_and_vect;
function fn_to_integer(vect : std_logic_vector) return integer is
begin
if (not fn_det_x(vect)) then
return(to_integer(unsigned(vect)));
else
return(0);
end if;
end fn_to_integer;
function fn_to_integer(d : std_logic) return integer is
begin
if (not fn_det_x(d)) then
if (d = '1') then
return(1);
else
return(0);
end if;
else
return(0);
end if;
end fn_to_integer;
function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
begin
temp := std_logic_vector(to_unsigned(int, width));
return(temp);
end fn_to_std_logic_vector;
function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
begin
temp := std_logic_vector(to_signed(int, width));
return(temp);
end fn_to_std_logic_vector_signed;
function fn_to_std_logic(b : boolean) return std_logic is
begin
if (b) then
return('1');
else
return('0');
end if;
end fn_to_std_logic;
function fn_dcd(vect : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector((2**vect'length)-1 downto 0);
variable i : integer range result'range;
begin
result := (others => '0');
i := 0;
if (not fn_det_x(vect)) then
i := to_integer(unsigned(vect));
end if;
result(i) := '1';
return(result);
end fn_dcd;
function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic is
variable result : std_logic_vector(vect'length-1 downto 0);
variable i : integer range result'range;
begin
result := vect;
i := 0;
if (not fn_det_x(sel)) then
i := to_integer(unsigned(sel));
end if;
return(result(i));
end fn_mux;
-- >>>>
function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect_a) or fn_det_x(vect_b)) then
tmp_a := (others =>'X');
tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect_a) + unsigned(vect_b)));
end "+";
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) + int));
end "+";
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
-- pragma translate_off
if (fn_det_x(vect) or fn_det_x(d)) then
tmp_b := (others =>'X');
return(tmp_b);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) + unsigned(tmp_b)));
end "+";
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect_a) or fn_det_x(vect_b)) then
tmp_a := (others =>'X'); tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect_a) - unsigned(vect_b)));
end "-";
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) - int));
end "-";
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(int - unsigned(vect)));
end "-";
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
-- pragma translate_off
if (fn_det_x(vect) or fn_det_x(d)) then
tmp_a := (others =>'X');
return(tmp_a);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) - unsigned(tmp_b)));
end "-";
end std_library;
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