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library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE";
--***************************************************************************
-- Necessary parameters for DDR core support
-- (dependent on memory chip connected to FPGA, not to be modified at will)
--***************************************************************************
constant DDR_DQ_WIDTH : integer := 32;
constant DDR_PAYLOAD_WIDTH : integer := 256;
constant DDR_DQS_WIDTH : integer := 4;
constant DDR_DM_WIDTH : integer := 4;
constant DDR_ROW_WIDTH : integer := 16;
constant DDR_BANK_WIDTH : integer := 3;
constant DDR_CK_WIDTH : integer := 1;
constant DDR_CKE_WIDTH : integer := 1;
constant DDR_ODT_WIDTH : integer := 1
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic;
ddr_sys_clk_n : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_rst_n : in std_logic
);
end entity top;
architecture arch of top is
component bpm_pcie_a7 is
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE"
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
ddr_sys_clk_n : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic; --Reset to PCIe core
-- DDR memory controller interface --
ddr_core_rst : in std_logic;
memc_ui_clk : out std_logic;
memc_ui_rst : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_rd_valid : out std_logic;
---- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ DDR memory controller interface
-- Wishbone interface --
CLK_I : in std_logic;
RST_I : in std_logic;
ACK_I : in std_logic;
DAT_I : in std_logic_vector(63 downto 0);
ADDR_O : out std_logic_vector(28 downto 0);
DAT_O : out std_logic_vector(63 downto 0);
WE_O : out std_logic;
STB_O : out std_logic;
SEL_O : out std_logic;
CYC_O : out std_logic;
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o : out std_logic
);
end component bpm_pcie_a7;
-- WISHBONE SLAVE interface:
-- Single-Port RAM with Asynchronous Read
--
component WB_MEM is
generic(
AWIDTH : natural range 2 to 29 := 7;
DWIDTH : natural range 8 to 128 := 64
);
port(
CLK_I : in std_logic;
ACK_O : out std_logic;
ADR_I : in std_logic_vector(AWIDTH-1 downto 0);
DAT_I : in std_logic_vector(DWIDTH-1 downto 0);
DAT_O : out std_logic_vector(DWIDTH-1 downto 0);
STB_I : in std_logic;
WE_I : in std_logic
);
end component;
signal ddr_sys_clk_i : std_logic;
signal ddr_sys_rst_i : std_logic;
signal pll_clkin : std_logic;
signal pll_clkfbout : std_logic;
signal pll_clkout0 : std_logic;
signal pll_locked : std_logic;
signal wbone_clk : std_logic;
signal wbone_addr : std_logic_vector(31 downto 0);
signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_we : std_logic;
signal wbone_sel : std_logic_vector(0 downto 0);
signal wbone_stb : std_logic;
signal wbone_ack : std_logic;
signal wbone_cyc : std_logic;
signal wbone_rst : std_logic;
begin
bpm_pcie : bpm_pcie_a7
generic map(
SIMULATION => SIMULATION,
-- ****
-- PCIe core parameters
-- ****
pcieLanes => pcieLanes,
PL_FAST_TRAIN => PL_FAST_TRAIN,
PIPE_SIM_MODE => PIPE_SIM_MODE
)
port map(
--DDR3 memory pins
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
-- PCIe transceivers
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
-- Necessity signals
ddr_sys_clk_p => ddr_sys_clk_i,
ddr_sys_clk_n => '0',
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_rst_n => sys_rst_n,
-- DDR memory controller interface --
-- uncomment when instantiating in another project
ddr_core_rst => ddr_sys_rst_i,
memc_ui_clk => open,
memc_ui_rst => open,
memc_cmd_rdy => open,
memc_cmd_en => '0',
memc_cmd_instr => (others => '0'),
memc_cmd_addr => (others => '0'),
memc_wr_en => '0',
memc_wr_end => '0',
memc_wr_mask => (others => '0'),
memc_wr_data => (others => '0'),
memc_wr_rdy => open,
memc_rd_data => open,
memc_rd_valid => open,
---- memory arbiter interface
memarb_acc_req => '0',
memarb_acc_gnt => open,
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I => wbone_clk,
RST_I => wbone_rst,
ACK_I => wbone_ack,
DAT_I => wbone_mdin,
ADDR_O => wbone_addr(28 downto 0),
DAT_O => wbone_mdout,
WE_O => wbone_we,
STB_O => wbone_stb,
SEL_O => wbone_sel(0),
CYC_O => wbone_cyc,
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o => wbone_rst
);
Wishbone_mem_large: if (SIMULATION = "TRUE") generate
wb_mem_sim :
wb_mem
generic map(
AWIDTH => 16,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(16-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
Wishbone_mem_sample: if (SIMULATION = "FALSE") generate
wb_mem_syn :
wb_mem
generic map(
AWIDTH => 7,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(7-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
--temporary clock assignment
wbone_clk <= pll_clkin;
ddr_inclk_buf : IBUFGDS
port map
(o => pll_clkin,
i => ddr_sys_clk_p,
ib => ddr_sys_clk_n
);
plle2_adv_inst : PLLE2_ADV
generic map
(bandwidth => "high",
compensation => "zhold",
divclk_divide => 5,
clkfbout_mult => 64,
clkfbout_phase => 0.000,
clkout0_divide => 8,
clkout0_phase => 0.000,
clkout0_duty_cycle => 0.500,
clkin1_period => 8.000,
ref_jitter1 => 0.010)
port map
-- output clocks
(clkfbout => pll_clkfbout,
clkout0 => pll_clkout0,
clkout1 => open,
clkout2 => open,
clkout3 => open,
clkout4 => open,
clkout5 => open,
-- input clock control
clkfbin => pll_clkfbout,
clkin1 => pll_clkin,
clkin2 => '0',
-- tied to always select the primary input clock
clkinsel => '1',
-- ports for dynamic reconfiguration
daddr => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Other control and status signals
LOCKED => pll_locked,
PWRDWN => '0',
RST => '0');
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => ddr_sys_clk_i,
I => pll_clkout0
);
ddr_sys_rst_i <= not(pll_locked);
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:29:03 01/16/2014
-- Design Name:
-- Module Name: BoothPartProdRed - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library WORK;
use WORK.MyWork.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BoothPartProdRed is
PORT(
prod0: in STD_LOGIC_VECTOR(19 downto 0);
prod1: in STD_LOGIC_VECTOR(20 downto 2);
prod2: in STD_LOGIC_VECTOR(22 downto 4);
prod3: in STD_LOGIC_VECTOR(24 downto 6);
prod4: in STD_LOGIC_VECTOR(26 downto 8);
prod5: in STD_LOGIC_VECTOR(28 downto 10);
prod6: in STD_LOGIC_VECTOR(30 downto 12);
prod7: in STD_LOGIC_VECTOR(31 downto 14);
result: out STD_LOGIC_VECTOR(31 downto 0));
end BoothPartProdRed;
architecture Behavioral of BoothPartProdRed is
COMPONENT HAdder is
port( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
END COMPONENT;
COMPONENT FAdder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
END COMPONENT;
COMPONENT Counter4_2 is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
tin : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC;
tout : out STD_LOGIC
);
END COMPONENT;
SIGNAL tempS1: STD_LOGIC_VECTOR(24 downto 2);
SIGNAL tempC1: STD_LOGIC_VECTOR(23 downto 3);
SIGNAL ctemp1: STD_LOGIC_VECTOR(21 downto 7);
SIGNAL tempS2: STD_LOGIC_VECTOR(31 downto 8);
SIGNAL tempC2: STD_LOGIC_VECTOR(31 downto 11);
SIGNAL ctemp2: STD_LOGIC_VECTOR(31 downto 8);
SIGNAL tempS3: STD_LOGIC_VECTOR(31 downto 3);
SIGNAL tempC3: STD_LOGIC_VECTOR(32 downto 4);
SIGNAL ctemp3: STD_LOGIC_VECTOR(25 downto 12);
begin
result(1 downto 0) <= prod0(1 downto 0);
result(2) <= tempS1(2);
tempS2(9 downto 8) <= prod4(9 downto 8);
tempS1(24 downto 23) <= prod3(24 downto 23);
tempS2(31) <= prod7(31);
result(3) <= tempS3(3);
result(31 downto 4) <= std_logic_vector(unsigned(tempS3(31 downto 4)) + unsigned(tempC3(31 downto 4)));
mainfor: FOR index in 2 to 31 GENERATE
if1_2to3:IF index >= 2 and index <= 3 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod0(index),
b=>prod1(index),
s=>tempS1(index),
c=>tempC1(index+1));
END GENERATE;
if1_4to5:IF index >= 4 and index <= 5 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>prod0(index),
b=>prod1(index),
c=>prod2(index),
s=>tempS1(index),
co=>tempC1(index+1));
END GENERATE;
if1_6:IF index = 6 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => prod0(index),
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => '0',
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_7tp19:IF index >= 7 and index <= 19 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => prod0(index),
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => ctemp1(index),
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_20:IF index = 20 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => '0',
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => ctemp1(index),
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_21:IF index = 21 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp1(index),
b=>prod2(index),
c=>prod3(index),
s=>tempS1(index),
co=>tempC1(index+1));
END GENERATE;
if1_22:IF index = 22 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod2(index),
b=>prod3(index),
s=>tempS1(index),
c=>tempC1(index+1));
END GENERATE;
if1_10to11:IF index >= 10 and index <= 11 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod4(index),
b=>prod5(index),
s=>tempS2(index),
c=>tempC2(index+1));
END GENERATE;
if1_12to13:IF index >= 12 and index <= 13 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>prod4(index),
b=>prod5(index),
c=>prod6(index),
s=>tempS2(index),
co=>tempC2(index+1));
END GENERATE;
if1_14:IF index = 14 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => prod4(index),
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => '0',
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_15to26:IF index >= 15 and index <= 26 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => prod4(index),
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => ctemp2(index),
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_27to28:IF index >= 27 and index <= 28 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => '0',
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => ctemp2(index),
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_29:IF index = 29 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp2(index),
b=>prod6(index),
c=>prod7(index),
s=>tempS2(index),
co=>tempC2(index+1));
END GENERATE;
if1_30:IF index = 30 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod6(index),
b=>prod7(index),
s=>tempS2(index),
c=>tempC2(index+1));
END GENERATE;
if2_3to7:IF index >= 3 and index <= 7 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>tempS1(index),
b=>tempC1(index),
s=>tempS3(index),
c=>tempC3(index+1));
END GENERATE;
if2_8to10:IF index >= 8 and index <= 10 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>tempS1(index),
b=>tempC1(index),
c=>tempS2(index),
s=>tempS3(index),
co=>tempC3(index+1));
END GENERATE;
if2_11:IF index = 11 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => tempC1(index),
c => tempS2(index),
d => tempC2(index),
tin => '0',
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_12to23:IF index >= 12 and index <= 23 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => tempC1(index),
c => tempS2(index),
d => tempC2(index),
tin => ctemp3(index),
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_24:IF index = 24 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => '0',
c => tempS2(index),
d => tempC2(index),
tin => ctemp3(index),
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_25:IF index = 25 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp3(index),
b=>tempS2(index),
c=>tempC2(index),
s=>tempS3(index),
co=>tempC3(index+1));
END GENERATE;
if2_26to31:IF index >= 26 and index <= 31 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>tempS2(index),
b=>tempC2(index),
s=>tempS3(index),
c=>tempC3(index+1));
END GENERATE;
END GENERATE;
end Behavioral; |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component faultify_top
generic (
numInj : integer;
numIn : integer;
numOut : integer);
port (
aclk : in std_logic;
arst_n : in std_logic;
clk : in std_logic;
clk_x32 : in std_logic;
awvalid : in std_logic;
awaddr : in std_logic_vector(31 downto 0);
wvalid : in std_logic;
wdata : in std_logic_vector(31 downto 0);
arvalid : in std_logic;
araddr : in std_logic_vector(31 downto 0);
rvalid : out std_logic;
rdata : out std_logic_vector(31 downto 0));
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal register_write_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_read_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal register_write_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal register_read_address : std_logic_vector(C_NUM_REG-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal faultify_read_valid : std_logic;
signal faultify_read_address_valid : std_logic;
signal faultify_read_address : std_logic_vector(31 downto 0);
signal faultify_write_valid : std_logic;
signal counter, divide : integer := 0;
signal faultify_clk_slow_i : std_logic;
begin
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= faultify_read_valid;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
register_write_data <= (others => '0');
register_write_address <= (others => '0');
faultify_write_valid <= '0';
else
faultify_write_valid <= slv_write_ack;
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(0, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(1, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(2, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(3, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(4, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(5, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(6, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(7, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(8, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(9, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(10, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(11, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(12, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(13, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(14, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(15, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(16, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(17, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(18, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(19, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(20, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(21, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(22, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(23, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(24, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(25, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(26, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(27, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(28, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(29, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(30, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
register_write_address <= std_logic_vector(to_unsigned(31, 32));
register_write_data(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, faultify_read_valid) is
begin
faultify_read_address_valid <= '1';
case slv_reg_read_sel is
when "10000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(0, 32));
when "01000000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(1, 32));
when "00100000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(2, 32));
when "00010000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(3, 32));
when "00001000000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(4, 32));
when "00000100000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(5, 32));
when "00000010000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(6, 32));
when "00000001000000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(7, 32));
when "00000000100000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(8, 32));
when "00000000010000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(9, 32));
when "00000000001000000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(10, 32));
when "00000000000100000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(11, 32));
when "00000000000010000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(12, 32));
when "00000000000001000000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(13, 32));
when "00000000000000100000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(14, 32));
when "00000000000000010000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(15, 32));
when "00000000000000001000000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(16, 32));
when "00000000000000000100000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(17, 32));
when "00000000000000000010000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(18, 32));
when "00000000000000000001000000000000" => faultify_read_address <= std_logic_vector(to_unsigned(19, 32));
when "00000000000000000000100000000000" => faultify_read_address <= std_logic_vector(to_unsigned(20, 32));
when "00000000000000000000010000000000" => faultify_read_address <= std_logic_vector(to_unsigned(21, 32));
when "00000000000000000000001000000000" => faultify_read_address <= std_logic_vector(to_unsigned(22, 32));
when "00000000000000000000000100000000" => faultify_read_address <= std_logic_vector(to_unsigned(23, 32));
when "00000000000000000000000010000000" => faultify_read_address <= std_logic_vector(to_unsigned(24, 32));
when "00000000000000000000000001000000" => faultify_read_address <= std_logic_vector(to_unsigned(25, 32));
when "00000000000000000000000000100000" => faultify_read_address <= std_logic_vector(to_unsigned(26, 32));
when "00000000000000000000000000010000" => faultify_read_address <= std_logic_vector(to_unsigned(27, 32));
when "00000000000000000000000000001000" => faultify_read_address <= std_logic_vector(to_unsigned(28, 32));
when "00000000000000000000000000000100" => faultify_read_address <= std_logic_vector(to_unsigned(29, 32));
when "00000000000000000000000000000010" => faultify_read_address <= std_logic_vector(to_unsigned(30, 32));
when "00000000000000000000000000000001" => faultify_read_address <= std_logic_vector(to_unsigned(31, 32));
when others => faultify_read_address <= (others => '0');
faultify_read_address_valid <= '0';
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= register_read_data when faultify_read_valid = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-----------------------------------------------------------------------------
-- clock divider 32 -> 1
-----------------------------------------------------------------------------
divide <= 32;
process(Bus2IP_Clk, Bus2IP_Resetn)
begin
if Bus2IP_Resetn = '0' then
counter <= 0;
faultify_clk_slow_i <= '0';
elsif(rising_edge(Bus2IP_Clk)) then
if(counter < divide/2-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
faultify_clk_slow_i <= '1';
else
faultify_clk_slow_i <= '0';
counter <= 0;
end if;
end if;
end process;
faultify_top_1 : faultify_top
generic map (
numInj => 321, --631
numIn => 70,
numOut => 41)
port map (
aclk => Bus2IP_Clk,
arst_n => Bus2IP_Resetn,
clk => faultify_clk_slow_i,
clk_x32 => Bus2IP_Clk,
awvalid => faultify_write_valid,
awaddr => register_write_address,
wvalid => faultify_write_valid,
wdata => register_write_data,
arvalid => faultify_read_address_valid,
araddr => faultify_read_address,
rvalid => faultify_read_valid,
rdata => register_read_data);
end IMP;
|
-------------------------------------------------------------------------------
-- pselect.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
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--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
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-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
--
-- History:
-- BLT 2001-04-10 First Version
-- BLT 2001-04-23 Moved function to this file
-- BLT 2001-05-21 Changed library to MicroBlaze
-- BLT 2001-08-13 Changed pragma to synthesis
-- ALS 2001-10-15 C_BAR is now padded to nearest multiple of 4
-- to handle lut equations
-- FLO 2002-03-26 Corrected implementation for case where C_AB
-- is not a multiple of 4 and the C_BAR values
-- at the pad bits are not '0'.
-- Removed implementation restriction that
-- required C_AW = C_BAR'length.
-- Added assertion to flag invalid generic
-- combinations.
-- ALS, FLO 2002-04-09 -Implemented XST workaround for the case
-- that C_AB = 0.
-- -Removed remnants of earlier
-- "instantiated-lut" implementation.
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MUXCY
port map (
O => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
-------------------------------------------------------------------------------
-- gen_dram.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Author: satish
--
-- History:
-- satish 2004-03-24 New Version
-- rikardw 2006-10-19 Single port version
--
-- Description:
-- Code to infer synchronous single port lut ram
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Gen_DRAM is
generic (
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 16
);
port (
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(C_AWIDTH-1 downto 0);
di : in std_logic_vector(C_DWIDTH-1 downto 0);
do : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end entity Gen_DRAM;
architecture syn of Gen_DRAM is
type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
-- signal RAM : ram_type := (others => (others => '0'));
signal RAM : ram_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(a)) <= di;
end if;
end if;
end process;
do <= RAM(conv_integer(a));
end syn;
-------------------------------------------------------------------------------
-- multi_channel_register.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: multi_channel_register.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- multi_channel_register.vhd
-- gen_dram.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2006-10-19 First Version
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library mutex_v2_1_8;
use mutex_v2_1_8.Gen_DRAM;
entity multi_channel_register is
generic (
C_NUM_CHANNELS : natural := 2;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH - 1 downto 0);
Data_Out : out std_logic_vector(C_DWIDTH - 1 downto 0)
);
end entity multi_channel_register;
architecture IMP of multi_channel_register is
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
component Gen_DRAM is
generic (
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 16
);
port (
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(C_AWIDTH-1 downto 0);
di : in std_logic_vector(C_DWIDTH-1 downto 0);
do : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end component Gen_DRAM;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Single channel storage
-----------------------------------------------------------------------------
Use_Single_Ch_Reg: if( C_NUM_CHANNELS = 1 ) generate
begin
Store_Cnt: process(Clk)
begin
if( Clk'event and Clk = '1' ) then
if( Rst = '1' ) then
Data_Out <= (others=>'0');
elsif( Write_Strobe = '1' ) then
Data_Out <= Data_In;
end if;
end if;
end process Store_Cnt;
end generate Use_Single_Ch_Reg;
-----------------------------------------------------------------------------
-- Multiple channel storage
-----------------------------------------------------------------------------
Use_Multi_Ch_Reg: if( C_NUM_CHANNELS > 1 ) generate
begin
-- Counter storage.
RAM_Storage: Gen_DRAM
generic map(
C_DWIDTH => C_DWIDTH,
C_AWIDTH => C_AWIDTH
)
port map(
clk => Clk,
we => Write_Strobe,
a => Channel,
di => Data_In,
do => Data_Out
);
end generate Use_Multi_Ch_Reg;
end architecture IMP;
-------------------------------------------------------------------------------
-- multi_channel_mutex.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: multi_channel_mutex.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- multi_channel_mutex.vhd
-- multi_channel_register.vhd
-- gen_dram.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2006-10-19 First Version
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library mutex_v2_1_8;
use mutex_v2_1_8.multi_channel_register;
entity multi_channel_mutex is
generic (
C_NUM_CHANNELS : natural := 2;
C_OWNER_ID_WIDTH : natural := 0;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
New_Mutex_Out : out std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
Mutex_Out : out std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0)
);
end entity multi_channel_mutex;
architecture IMP of multi_channel_mutex is
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
component multi_channel_register is
generic (
C_NUM_CHANNELS : natural := 2;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH - 1 downto 0);
Data_Out : out std_logic_vector(C_DWIDTH - 1 downto 0)
);
end component multi_channel_register;
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal Mutex_I : std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
signal Mutex_New : std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Channel Counter Storage
-----------------------------------------------------------------------------
Mutex_Store: multi_channel_register
generic map(
C_NUM_CHANNELS => C_NUM_CHANNELS,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH + C_OWNER_ID_WIDTH
)
port map(
-- Clock and reset signals.
Clk => Clk,
Rst => Rst,
-- Control signals.
Write_Strobe => Write_Strobe,
Channel => Channel,
Data_In => Mutex_New,
Data_Out => Mutex_I
);
-----------------------------------------------------------------------------
-- Write to lock and pure write to release function
-----------------------------------------------------------------------------
Write_2_Lock: process(Data_In, Mutex_I)
variable OwnerMatched : boolean;
begin
-- Check if the owner is writing.
if( C_OWNER_ID_WIDTH > 0 ) then
OwnerMatched := Mutex_I(C_OWNER_ID_WIDTH + C_DWIDTH - 1 downto C_DWIDTH) =
Data_In(C_OWNER_ID_WIDTH + C_DWIDTH - 1 downto C_DWIDTH);
else
OwnerMatched := true;
end if;
-- Update mutex accordingly.
if( Mutex_I(0) /= '1' or OwnerMatched ) then
-- Write new value.
if( Data_In(0) = '0' ) then
Mutex_New <= (others=>'0');
else
Mutex_New <= Data_In;
end if;
else
-- Keep old value.
Mutex_New <= Mutex_I;
end if;
end process Write_2_Lock;
-----------------------------------------------------------------------------
-- Rename output signals
-----------------------------------------------------------------------------
New_Mutex_Out <= Mutex_New;
Mutex_Out <= Mutex_I;
end architecture IMP;
-------------------------------------------------------------------------------
-- mutex_core.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mutex_core.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mutex_core.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2006-10-19 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mutex_core is
generic (
-- General.
C_FAMILY : string := "virtex7";
-- Mutex specific.
C_NUM_INTERFACE : integer range 1 to 16 := 1; -- Number of interfaces to access Mutexes.
C_ENABLE_USER : integer range 0 to 1 := 1; -- If USER register is available.
C_OWNER_ID_WIDTH : integer range 0 to 31 := 8; -- Number of bits for id number.
C_HW_ID_WIDTH : integer range 1 to 31 := 8; -- Number of bits for hardware id number.
C_ENABLE_HW_PROT : integer range 0 to 1 := 0; -- If hardware security should be used.
C_NUM_MUTEX : integer := 16; -- Number of mutexes.
C_MUTEX_NUMBER : integer := 0; -- Mutex number.
C_AWIDTH : integer := 8; -- Address bits including register offset.
C_REGISTER_WIDTH : integer := 4; -- Width of register offset.
C_DWIDTH : integer := 32; -- Width of data bus.
C_DWIDTH_USER_REG : integer := 32; -- Width of user data.
C_DWIDTH_MUTEX : integer := 1 -- Width of mutex field (usually 1).
);
port (
-- System signals
Clk : in std_logic;
Rst : in std_logic;
-- Bus slave signals
Mutex_Access : in std_logic_vector(0 to C_NUM_INTERFACE - 1);
Mutex_RnW : in std_logic_vector(0 to C_NUM_INTERFACE - 1);
Mutex_HW_Id : in std_logic_vector(0 to C_NUM_INTERFACE * C_HW_ID_WIDTH - 1);
Mutex_Addr : in std_logic_vector(0 to C_NUM_INTERFACE * C_AWIDTH - 1);
Mutex_Wr_Data : in std_logic_vector(0 to C_NUM_INTERFACE * C_DWIDTH - 1);
Mutex_Rd_Data : out std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Ack : out std_logic_vector(0 to C_NUM_INTERFACE - 1)
);
end entity mutex_core;
library unisim;
use unisim.all;
architecture IMP of mutex_core is
-----------------------------------------------------------------------------
-- Function declaration
-----------------------------------------------------------------------------
function Get_Num_Bits(data : natural) return natural is
variable num_bits : natural:= 1;
begin
while( data > 2**num_bits ) loop
num_bits := num_bits + 1;
end loop;
return num_bits;
end function Get_Num_Bits;
-----------------------------------------------------------------------------
-- Constant declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
component multi_channel_mutex is
generic (
C_NUM_CHANNELS : natural := 2;
C_OWNER_ID_WIDTH : natural := 0;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
New_Mutex_Out : out std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0);
Mutex_Out : out std_logic_vector(C_DWIDTH + C_OWNER_ID_WIDTH - 1 downto 0)
);
end component multi_channel_mutex;
component multi_channel_register is
generic (
C_NUM_CHANNELS : natural := 2;
C_AWIDTH : natural := 4;
C_DWIDTH : natural := 8
);
port (
-- Clock and reset signals.
Clk : in std_logic;
Rst : in std_logic;
-- Control signals.
Write_Strobe : in std_logic;
Channel : in std_logic_vector(C_AWIDTH - 1 downto 0);
Data_In : in std_logic_vector(C_DWIDTH - 1 downto 0);
Data_Out : out std_logic_vector(C_DWIDTH - 1 downto 0)
);
end component multi_channel_register;
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
-- Internal arbitrated signals
signal Mutex_Access_I : std_logic_vector(0 to C_NUM_INTERFACE - 1);
signal Mutex_RnW_I : std_logic;
signal Mutex_HW_Id_I : std_logic_vector(0 to C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE) - 1);
signal Mutex_Addr_I : std_logic_vector(0 to C_AWIDTH - 1);
signal Mutex_Wr_Data_I : std_logic_vector(0 to C_DWIDTH - 1);
signal Mutex_Rd_Data_I : std_logic_vector(0 to C_DWIDTH - 1);
signal Mutex_Ack_I : std_logic;
signal Access_In_Progress : std_logic;
signal Write_Strobe_Mutex : std_logic;
signal Write_Strobe_User : std_logic;
signal Second_Cycle : std_logic;
signal Read_Data_Type : std_logic_vector(0 to 1);
-- Configuration register related.
signal User_Reg : std_logic_vector(0 to C_DWIDTH_USER_REG - 1);
signal User_Reg_I : std_logic_vector(0 to C_DWIDTH - 1);
-- Mutex related.
signal Mutex : std_logic_vector(0 to C_DWIDTH_MUTEX + C_OWNER_ID_WIDTH - 1);
signal Mutex_I : std_logic_vector(0 to C_DWIDTH - 1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Interface arbitration
-----------------------------------------------------------------------------
Using_SingleIf_Mutex: if C_NUM_INTERFACE = 1 generate
begin
-- Only one interface to all Mutexes.
-- => Simply connect w/o any arbitration.
Access_In_Progress <= Mutex_Access(0);
Mutex_Access_I <= Mutex_Access(0 to 0);
Mutex_RnW_I <= Mutex_RnW(0);
Mutex_HW_Id_I <= Mutex_HW_Id(0 to C_HW_ID_WIDTH - 1) & '0';
Mutex_Addr_I <= Mutex_Addr(0 to C_AWIDTH - 1);
Mutex_Wr_Data_I <= Mutex_Wr_Data(0 to C_DWIDTH - 1);
Mutex_Ack <= (others=>Mutex_Ack_I);
end generate Using_SingleIf_Mutex;
-- Multiple interfaces.
Using_MultiIf_Mutex: if C_NUM_INTERFACE > 1 generate
begin
Interface_Arbitration: process(Clk)
begin
if( Clk'event and Clk = '1' ) then
if( Rst = '1' ) then
Access_In_Progress <= '0';
Mutex_Access_I <= (others=>'0');
Mutex_RnW_I <= '0';
Mutex_HW_Id_I <= (others=>'0');
Mutex_Addr_I <= (others=>'0');
Mutex_Wr_Data_I <= (others=>'0');
else
if( Access_In_Progress = '1' ) then
if( ( Mutex_Access_I and Mutex_Access ) = (Mutex_Access'range=>'0') ) then
-- Selected interface has acknowledged that this end
-- has performed all its tasks.
-- => Get ready for the next access.
Access_In_Progress <= '0';
Mutex_Access_I <= (others=>'0');
end if;
else
for I in natural range C_NUM_INTERFACE - 1 downto 0 loop
-- Loop in ascending priority order.
if( Mutex_Access(I) = '1' ) then
-- This interface wants to access a mutexes in this bank.
-- => Forward information to the rest of the core.
Access_In_Progress <= '1';
Mutex_Access_I <= (others=>'0');
Mutex_Access_I(I) <= '1';
Mutex_RnW_I <= Mutex_RnW(I);
Mutex_HW_Id_I <= Mutex_HW_Id(C_HW_ID_WIDTH * I to C_HW_ID_WIDTH * (I + 1) - 1) &
std_logic_vector(to_unsigned(I, Get_Num_Bits(C_NUM_INTERFACE)));
Mutex_Addr_I <= Mutex_Addr(C_AWIDTH * I to C_AWIDTH * (I + 1) - 1);
Mutex_Wr_Data_I <= Mutex_Wr_Data(C_DWIDTH * I to C_DWIDTH * (I + 1) - 1);
end if;
end loop;
end if;
-- Assign the Acknowledge signal.
Mutex_Ack <= (Mutex_Ack'range=>Mutex_Ack_I) and Mutex_Access_I and Mutex_Access;
end if;
end if;
end process Interface_Arbitration;
end generate Using_MultiIf_Mutex;
-----------------------------------------------------------------------------
-- Access control
-----------------------------------------------------------------------------
Access_Handle: process(Clk)
begin
if( Clk'event and Clk = '1' ) then
if( Rst = '1' ) then
-- Reset.
Write_Strobe_User <= '0';
Write_Strobe_Mutex <= '0';
Mutex_Ack_I <= '0';
Second_Cycle <= '0';
Read_Data_Type <= (others=>'0');
else
-- Generate second cycle.
Second_Cycle <= (not Second_Cycle ) and Access_In_Progress and (not Mutex_Ack_I);
-- Default assignment.
Write_Strobe_User <= '0';
Write_Strobe_Mutex <= '0';
-- Control read data mux.
Read_Data_Type <= Mutex_Addr_I(Mutex_Addr_I'right - 1 - 2 to Mutex_Addr_I'right - 2);
-- Create write strobes for resources.
if( Mutex_Addr_I(Mutex_Addr_I'right - 2) = '0' ) then
-- Access mutex registers.
Write_Strobe_Mutex <= Access_In_Progress and (not Mutex_RnW_I);
else
-- Access Configuration/Address register.
if( C_ENABLE_USER /= 0 ) then
Write_Strobe_User <= Access_In_Progress and (not Mutex_RnW_I);
end if;
end if;
-- Finish access.
Mutex_Ack_I <= Second_Cycle or (Access_In_Progress and (not Mutex_RnW_I)) or (Mutex_Ack_I and Access_In_Progress);
end if;
end if;
end process Access_Handle;
-----------------------------------------------------------------------------
-- Instantiating MUTEX Register
-----------------------------------------------------------------------------
Using_HW_Protection: if( C_ENABLE_HW_PROT /= 0 ) generate
signal Mutex_Wr_Data_II : std_logic_vector(0 to C_OWNER_ID_WIDTH + C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE) + C_DWIDTH_MUTEX -1);
signal Mutex_II : std_logic_vector(0 to C_OWNER_ID_WIDTH + C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE) + C_DWIDTH_MUTEX -1);
begin
Protected_Mutex_Inst: multi_channel_mutex
generic map(
C_NUM_CHANNELS => C_NUM_MUTEX,
C_OWNER_ID_WIDTH => C_OWNER_ID_WIDTH + C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE),
C_AWIDTH => C_AWIDTH - C_REGISTER_WIDTH,
C_DWIDTH => C_DWIDTH_MUTEX
)
port map(
-- Clock and reset signals.
Clk => Clk,
Rst => Rst,
-- Control signals.
Write_Strobe => Write_Strobe_Mutex,
Channel => Mutex_Addr_I(0 to C_AWIDTH - C_REGISTER_WIDTH - 1),
Data_In => Mutex_Wr_Data_II,
New_Mutex_Out => open,
Mutex_Out => Mutex_II
);
-- Append and remove hardware information invisibly.
Mutex_Wr_Data_II <= Mutex_HW_Id_I & Mutex_Wr_Data_I(C_DWIDTH - C_DWIDTH_MUTEX - C_OWNER_ID_WIDTH to C_DWIDTH - 1);
Mutex <= Mutex_II(C_HW_ID_WIDTH + Get_Num_Bits(C_NUM_INTERFACE) to Mutex_II'right);
end generate Using_HW_Protection;
No_HW_Protection: if( C_ENABLE_HW_PROT = 0 ) generate
begin
Normal_Mutex_Inst: multi_channel_mutex
generic map(
C_NUM_CHANNELS => C_NUM_MUTEX,
C_OWNER_ID_WIDTH => C_OWNER_ID_WIDTH,
C_AWIDTH => C_AWIDTH - C_REGISTER_WIDTH,
C_DWIDTH => C_DWIDTH_MUTEX
)
port map(
-- Clock and reset signals.
Clk => Clk,
Rst => Rst,
-- Control signals.
Write_Strobe => Write_Strobe_Mutex,
Channel => Mutex_Addr_I(0 to C_AWIDTH - C_REGISTER_WIDTH - 1),
Data_In => Mutex_Wr_Data_I(C_DWIDTH - C_DWIDTH_MUTEX - C_OWNER_ID_WIDTH to C_DWIDTH - 1),
New_Mutex_Out => open,
Mutex_Out => Mutex
);
end generate No_HW_Protection;
-----------------------------------------------------------------------------
-- Instantiating USER Register
-----------------------------------------------------------------------------
Using_User_Reg: if( C_ENABLE_USER /= 0 ) generate
begin
User_Reg_Inst: multi_channel_register
generic map(
C_NUM_CHANNELS => C_NUM_MUTEX,
C_AWIDTH => C_AWIDTH - C_REGISTER_WIDTH,
C_DWIDTH => C_DWIDTH_USER_REG
)
port map(
-- Clock and reset signals.
Clk => Clk,
Rst => Rst,
-- Control signals.
Write_Strobe => Write_Strobe_User,
Channel => Mutex_Addr_I(0 to C_AWIDTH - C_REGISTER_WIDTH - 1),
Data_In => Mutex_Wr_Data_I(C_DWIDTH - C_DWIDTH_USER_REG to C_DWIDTH-1),
Data_Out => User_Reg
);
end generate Using_User_Reg;
No_User_Reg: if( C_ENABLE_USER = 0 ) generate
begin
User_Reg <= (others=>'0');
end generate No_User_Reg;
-----------------------------------------------------------------------------
-- Read multiplexer
-----------------------------------------------------------------------------
ReadDataMux: process(Read_Data_Type, User_Reg, Mutex)
begin
-- Extend the data to full width.
-- User_Reg_I <= (others=>'0');
-- User_Reg_I(C_DWIDTH - C_DWIDTH_USER_REG to C_DWIDTH-1) <= User_Reg;
-- Mutex_I <= (others=>'0');
-- Mutex_I(C_DWIDTH - C_DWIDTH_MUTEX - C_OWNER_ID_WIDTH to C_DWIDTH-1) <= Mutex;
-- Default assignment.
Mutex_Rd_Data_I <= (others=>'0');
case Read_Data_Type is
when "00" =>
Mutex_Rd_Data_I(C_DWIDTH - C_DWIDTH_MUTEX - C_OWNER_ID_WIDTH to C_DWIDTH-1) <= Mutex;
when "01" =>
Mutex_Rd_Data_I(C_DWIDTH - C_DWIDTH_USER_REG to C_DWIDTH-1) <= User_Reg;
when others =>
-- Reserved registers.
null;
end case;
end process ReadDataMux;
ReadDataMux_DFF: process(Clk)
begin
if( Clk'event and Clk = '1' ) then
if( Rst = '1' ) then
Mutex_Rd_Data <= (others=>'0');
elsif( Second_Cycle = '1' ) then
Mutex_Rd_Data <= Mutex_Rd_Data_I;
end if;
end if;
end process ReadDataMux_DFF;
end architecture IMP;
-------------------------------------------------------------------------------
-- axi_decode.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: axi_decode.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_decode.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2007-03-27 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity axi_decode is
generic (
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_ASYNC_CLKS : integer range 0 to 1 := 0;
C_NUM_SYNC_FF : integer range 1 to 8 := 2; -- Number of cycles to synchronize to new clock domain.
C_HW_ID_WIDTH : integer range 1 to 31 := 8; -- Number of bits for hardware id number.
C_AWIDTH : integer := 8; -- Address bits including register offset.
C_DWIDTH : integer := 32 -- Width of data bus.
);
port (
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Mutex signals.
Mutex_Clk : in std_logic;
Mutex_Rst : in std_logic;
Mutex_Access : out std_logic;
Mutex_RnW : out std_logic;
Mutex_HW_Id : out std_logic_vector(0 to C_HW_ID_WIDTH - 1);
Mutex_Addr : out std_logic_vector(0 to C_AWIDTH - 1);
Mutex_Wr_Data : out std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Rd_Data : in std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Ack : in std_logic
);
end entity axi_decode;
library unisim;
use unisim.vcomponents.all;
library mutex_v2_1_8;
use mutex_v2_1_8.all;
architecture IMP of axi_decode is
-----------------------------------------------------------------------------
-- Function declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Constant declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal valid_read_data : std_logic;
signal new_write_access_cmb : std_logic;
signal new_read_access_cmb : std_logic;
signal new_write_access : std_logic;
signal new_read_access : std_logic;
signal end_write : std_logic; -- Write cycle end.
signal end_read : std_logic; -- Read cycle end.
signal completed_write : std_logic; -- Write response acknowledged.
signal completed_read : std_logic; -- Read response acknowledged.
signal access_end : std_logic; -- Access is completed.
signal Mutex_Access_I : std_logic;
signal Mutex_RnW_I : std_logic;
signal Mutex_HW_Id_I : std_logic_vector(0 to C_HW_ID_WIDTH - 1);
signal Mutex_Addr_I : std_logic_vector(0 to C_AWIDTH - 1);
signal Mutex_Wr_Data_I : std_logic_vector(0 to C_DWIDTH - 1);
signal Mutex_Rd_Data_I : std_logic_vector(C_DWIDTH - 1 downto 0);
signal Mutex_Ack_I : std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (AR/AW/W)
-----------------------------------------------------------------------------
-- Detect new transaction.
-- Write has priority.
-- Make sure new write is blocked if it arrives after a read is acknowledged (prior to Mutex_Access_I is set).
new_write_access_cmb <= (not Mutex_Access_I) and (not Mutex_Ack_I) and S_AXI_AWVALID and S_AXI_WVALID and
(not new_read_access);
new_read_access_cmb <= (not Mutex_Access_I) and (not Mutex_Ack_I) and S_AXI_ARVALID and
(not new_write_access_cmb);
Start_of_Transfer_Control : process (S_AXI_ACLK) is
begin -- process End_of_Transfer_Control
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then -- rising clock edge
if S_AXI_ARESETN = '0' then -- synchronous reset (active low)
new_write_access <= '0';
new_read_access <= '0';
else
-- Make sure it is a one cycle pulse only.
new_write_access <= new_write_access_cmb and not new_write_access;
new_read_access <= new_read_access_cmb and not new_read_access;
end if;
end if;
end process Start_of_Transfer_Control;
-- Acknowledge new transaction.
S_AXI_AWREADY <= new_write_access;
S_AXI_WREADY <= new_write_access;
S_AXI_ARREADY <= new_read_access;
-- Capture new access.
AccessAck: process (S_AXI_ACLK) is
begin -- process AddrAck
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then -- rising clock edge
if S_AXI_ARESETN = '0' then -- synchronous reset (active low)
Mutex_Access_I <= '0';
Mutex_RnW_I <= '0';
Mutex_Addr_I <= (others=>'0');
Mutex_HW_Id_I <= (others=>'0');
Mutex_Wr_Data_I <= (others=>'0');
else
if( new_write_access = '1' or new_read_access = '1' ) then
-- Get data for new access.
if( new_write_access = '1' ) then
Mutex_Addr_I <= S_AXI_AWADDR(C_AWIDTH-1 downto 0);
else
Mutex_Addr_I <= S_AXI_ARADDR(C_AWIDTH-1 downto 0);
end if;
Mutex_Wr_Data_I <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
Mutex_HW_Id_I <= (others=>'0');
Mutex_RnW_I <= new_read_access;
Mutex_Access_I <= '1';
elsif( access_end = '1' ) then
Mutex_Access_I <= '0';
end if;
end if;
end if;
end process AccessAck;
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (B/R)
-----------------------------------------------------------------------------
End_of_Transfer_Control : process (S_AXI_ACLK) is
begin -- process End_of_Transfer_Control
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then -- rising clock edge
if S_AXI_ARESETN = '0' then -- synchronous reset (active low)
end_write <= '0';
end_read <= '0';
else
if( completed_write = '1' ) then
end_write <= '0';
elsif( Mutex_Access_I = '1' and Mutex_Ack_I = '1' and Mutex_RnW_I = '0' ) then
end_write <= '1';
end if;
if( completed_read = '1' ) then
end_read <= '0';
elsif( valid_read_data = '1' ) then
end_read <= '1';
end if;
end if;
end if;
end process End_of_Transfer_Control;
valid_read_data <= Mutex_Access_I and Mutex_Ack_I and Mutex_RnW_I;
S_AXI_BVALID <= end_write;
S_AXI_RVALID <= end_read;
S_AXI_BRESP <= (others=>'0');
S_AXI_RRESP <= (others=>'0');
completed_write <= end_write and S_AXI_BREADY;
completed_read <= end_read and S_AXI_RREADY;
access_end <= completed_write or completed_read;
Read_Align: process (Mutex_Rd_Data) is
begin -- process Read_Mux
Mutex_Rd_Data_i <= (others=>'0');
Mutex_Rd_Data_i(C_DWIDTH - 1 downto 0) <= Mutex_Rd_Data;
end process Read_Align;
Not_All_32_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
begin
S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0');
end generate Not_All_32_Bits_Are_Used;
S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
begin
S_AXI_RDATA_FDRE : FDRE
port map (
Q => S_AXI_RDATA(I), -- [out std_logic]
C => S_AXI_ACLK, -- [in std_logic]
CE => valid_read_data, -- [in std_logic]
D => Mutex_Rd_Data_i(I), -- [in std_logic]
R => completed_read); -- [in std_logic]
end generate S_AXI_RDATA_DFF;
-----------------------------------------------------------------------------
-- Domain synchronization
-----------------------------------------------------------------------------
-- Always move the data signals directly accross.
-- Sync signals will guarantee safe crossing.
Mutex_RnW <= Mutex_RnW_I;
Mutex_HW_Id <= Mutex_HW_Id_I;
Mutex_Addr <= Mutex_Addr_I;
Mutex_Wr_Data <= Mutex_Wr_Data_I;
Mutex_Rd_Data_I <= Mutex_Rd_Data;
No_Crossing: if( C_ASYNC_CLKS = 0 ) generate
begin
-- No need to synchronize.
Mutex_Access <= Mutex_Access_I;
Mutex_Ack_I <= Mutex_Ack;
end generate No_Crossing;
Domain_Crossing: if( C_ASYNC_CLKS /= 0 ) generate
signal Mutex_Access_d : std_logic_vector(0 to C_NUM_SYNC_FF);
signal Mutex_Ack_d : std_logic_vector(0 to C_NUM_SYNC_FF);
signal S_AXI_ARESET : std_logic;
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of Mutex_Access_d : signal is "TRUE";
-- attribute ASYNC_REG of Mutex_Ack_d : signal is "TRUE";
begin
-- Handle transfer of asynchronous interface sync signal transfer
-- with unknown clock relation.
--
-- C_NUM_SYNC_FF = 2 (default):
--
-- MutexClk -------+-----+-----------+
-- | | |
-- | | +---------+
-- Event ----FF----FF----FF---->| Mutex |
-- | | |
-- WrData ---FF---------------->| |
-- | | |
-- IfClk ----+-----+-----+ | |
-- | | | |
-- Ack <-----------FF----FF-----| |
-- | |
-- RdData <---------------------| |
-- +---------+
--
--
-- General case for C_NUM_SYNC_FF:
--
-- MutexClk -------+----------------+
-- | |
-- | +---------+
-- Event ----FF----(FF x n)---->| Mutex |
-- | | |
-- WrData ---FF---------------->| |
-- | | |
-- IfClk ----+-----+ | |
-- | | |
-- Ack <-----------(FF x n)-----| |
-- | |
-- RdData <---------------------| |
-- +---------+
--
S_AXI_ARESET <= not S_AXI_ARESETN;
-- Move the out bound access signal to the common domain.
Mutex_Access_d(0) <= Mutex_Access_I;
Cross_Out: for I in 1 to C_NUM_SYNC_FF generate
begin
Block_Gen: block
attribute ASYNC_REG : string;
attribute ASYNC_REG of FDR_INST : label is "TRUE";
begin
FDR_INST: FDR
port map (
Q => Mutex_Access_d(I),
C => Mutex_Clk,
D => Mutex_Access_d(I-1),
R => Mutex_Rst
);
end block Block_Gen;
end generate Cross_Out;
-- Select synchronized bit.
Mutex_Access <= Mutex_Access_d(C_NUM_SYNC_FF);
-- Get back to interface domain.
Mutex_Ack_d(0) <= Mutex_Ack;
Cross_Back: for I in 1 to C_NUM_SYNC_FF generate
begin
Block_Gen: block
attribute ASYNC_REG : string;
attribute ASYNC_REG of FDR_INST : label is "TRUE";
begin
FDR_INST: FDR
port map (
Q => Mutex_Ack_d(I),
C => S_AXI_ACLK,
D => Mutex_Ack_d(I-1),
R => S_AXI_ARESET
);
end block Block_Gen;
end generate Cross_Back;
-- Select synchronized bit.
Mutex_Ack_I <= Mutex_Ack_d(C_NUM_SYNC_FF);
end generate Domain_Crossing;
end architecture IMP;
-------------------------------------------------------------------------------
-- mutex.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mutex.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mutex.vhd
-- axi_decode.vhd
-- multi_channel_mutex.vhd
-- multi_channel_register.vhd
-- gen_dram.vhd
-- mutex_core.vhd
-- multi_channel_mutex.vhd
-- multi_channel_register.vhd
-- gen_dram.vhd
--
-------------------------------------------------------------------------------
-- Author: rikardw
--
-- History:
-- rikardw 2006-10-19 First Version
-- stefana 2012-12-14 Removed legacy interfaces
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mutex is
generic (
-- General.
C_FAMILY : string := "virtex7";
-- AXI4 interface #0 specific.
C_S0_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S0_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S0_AXI_ADDR_WIDTH : integer := 32;
C_S0_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #1 specific.
C_S1_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S1_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S1_AXI_ADDR_WIDTH : integer := 32;
C_S1_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #2 specific.
C_S2_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S2_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S2_AXI_ADDR_WIDTH : integer := 32;
C_S2_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #3 specific.
C_S3_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S3_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S3_AXI_ADDR_WIDTH : integer := 32;
C_S3_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #4 specific.
C_S4_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S4_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S4_AXI_ADDR_WIDTH : integer := 32;
C_S4_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #5 specific.
C_S5_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S5_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S5_AXI_ADDR_WIDTH : integer := 32;
C_S5_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #6 specific.
C_S6_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S6_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S6_AXI_ADDR_WIDTH : integer := 32;
C_S6_AXI_DATA_WIDTH : integer := 32;
-- AXI4 interface #7 specific.
C_S7_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S7_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S7_AXI_ADDR_WIDTH : integer := 32;
C_S7_AXI_DATA_WIDTH : integer := 32;
-- Mutex specific.
C_ASYNC_CLKS : integer range 0 to 1 := 0;
C_NUM_SYNC_FF : integer range 1 to 8 := 2; -- Number of cycles to synchronize to new clock domain.
C_NUM_AXI : integer range 0 to 8 := 2; -- Number of AXI to access Mutexes.
C_ENABLE_USER : integer range 0 to 1 := 0; -- If USER register is available.
C_OWNER_ID_WIDTH : integer range 0 to 31 := 8; -- Number of bits for id number.
C_ENABLE_HW_PROT : integer range 0 to 1 := 0; -- If hardware security should be used.
C_NUM_MUTEX : integer := 16 -- Number of mutexes.
);
port (
-- AXI4-Lite interface #0 slave signals.
S0_AXI_ACLK : in std_logic;
S0_AXI_ARESETN : in std_logic;
S0_AXI_AWADDR : in std_logic_vector(C_S0_AXI_ADDR_WIDTH-1 downto 0);
S0_AXI_AWVALID : in std_logic;
S0_AXI_AWREADY : out std_logic;
S0_AXI_WDATA : in std_logic_vector(C_S0_AXI_DATA_WIDTH-1 downto 0);
S0_AXI_WSTRB : in std_logic_vector((C_S0_AXI_DATA_WIDTH/8)-1 downto 0);
S0_AXI_WVALID : in std_logic;
S0_AXI_WREADY : out std_logic;
S0_AXI_BRESP : out std_logic_vector(1 downto 0);
S0_AXI_BVALID : out std_logic;
S0_AXI_BREADY : in std_logic;
S0_AXI_ARADDR : in std_logic_vector(C_S0_AXI_ADDR_WIDTH-1 downto 0);
S0_AXI_ARVALID : in std_logic;
S0_AXI_ARREADY : out std_logic;
S0_AXI_RDATA : out std_logic_vector(C_S0_AXI_DATA_WIDTH-1 downto 0);
S0_AXI_RRESP : out std_logic_vector(1 downto 0);
S0_AXI_RVALID : out std_logic;
S0_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #1 slave signals.
S1_AXI_ACLK : in std_logic;
S1_AXI_ARESETN : in std_logic;
S1_AXI_AWADDR : in std_logic_vector(C_S1_AXI_ADDR_WIDTH-1 downto 0);
S1_AXI_AWVALID : in std_logic;
S1_AXI_AWREADY : out std_logic;
S1_AXI_WDATA : in std_logic_vector(C_S1_AXI_DATA_WIDTH-1 downto 0);
S1_AXI_WSTRB : in std_logic_vector((C_S1_AXI_DATA_WIDTH/8)-1 downto 0);
S1_AXI_WVALID : in std_logic;
S1_AXI_WREADY : out std_logic;
S1_AXI_BRESP : out std_logic_vector(1 downto 0);
S1_AXI_BVALID : out std_logic;
S1_AXI_BREADY : in std_logic;
S1_AXI_ARADDR : in std_logic_vector(C_S1_AXI_ADDR_WIDTH-1 downto 0);
S1_AXI_ARVALID : in std_logic;
S1_AXI_ARREADY : out std_logic;
S1_AXI_RDATA : out std_logic_vector(C_S1_AXI_DATA_WIDTH-1 downto 0);
S1_AXI_RRESP : out std_logic_vector(1 downto 0);
S1_AXI_RVALID : out std_logic;
S1_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #2 slave signals.
S2_AXI_ACLK : in std_logic;
S2_AXI_ARESETN : in std_logic;
S2_AXI_AWADDR : in std_logic_vector(C_S2_AXI_ADDR_WIDTH-1 downto 0);
S2_AXI_AWVALID : in std_logic;
S2_AXI_AWREADY : out std_logic;
S2_AXI_WDATA : in std_logic_vector(C_S2_AXI_DATA_WIDTH-1 downto 0);
S2_AXI_WSTRB : in std_logic_vector((C_S2_AXI_DATA_WIDTH/8)-1 downto 0);
S2_AXI_WVALID : in std_logic;
S2_AXI_WREADY : out std_logic;
S2_AXI_BRESP : out std_logic_vector(1 downto 0);
S2_AXI_BVALID : out std_logic;
S2_AXI_BREADY : in std_logic;
S2_AXI_ARADDR : in std_logic_vector(C_S2_AXI_ADDR_WIDTH-1 downto 0);
S2_AXI_ARVALID : in std_logic;
S2_AXI_ARREADY : out std_logic;
S2_AXI_RDATA : out std_logic_vector(C_S2_AXI_DATA_WIDTH-1 downto 0);
S2_AXI_RRESP : out std_logic_vector(1 downto 0);
S2_AXI_RVALID : out std_logic;
S2_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #3 slave signals.
S3_AXI_ACLK : in std_logic;
S3_AXI_ARESETN : in std_logic;
S3_AXI_AWADDR : in std_logic_vector(C_S3_AXI_ADDR_WIDTH-1 downto 0);
S3_AXI_AWVALID : in std_logic;
S3_AXI_AWREADY : out std_logic;
S3_AXI_WDATA : in std_logic_vector(C_S3_AXI_DATA_WIDTH-1 downto 0);
S3_AXI_WSTRB : in std_logic_vector((C_S3_AXI_DATA_WIDTH/8)-1 downto 0);
S3_AXI_WVALID : in std_logic;
S3_AXI_WREADY : out std_logic;
S3_AXI_BRESP : out std_logic_vector(1 downto 0);
S3_AXI_BVALID : out std_logic;
S3_AXI_BREADY : in std_logic;
S3_AXI_ARADDR : in std_logic_vector(C_S3_AXI_ADDR_WIDTH-1 downto 0);
S3_AXI_ARVALID : in std_logic;
S3_AXI_ARREADY : out std_logic;
S3_AXI_RDATA : out std_logic_vector(C_S3_AXI_DATA_WIDTH-1 downto 0);
S3_AXI_RRESP : out std_logic_vector(1 downto 0);
S3_AXI_RVALID : out std_logic;
S3_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #4 slave signals.
S4_AXI_ACLK : in std_logic;
S4_AXI_ARESETN : in std_logic;
S4_AXI_AWADDR : in std_logic_vector(C_S4_AXI_ADDR_WIDTH-1 downto 0);
S4_AXI_AWVALID : in std_logic;
S4_AXI_AWREADY : out std_logic;
S4_AXI_WDATA : in std_logic_vector(C_S4_AXI_DATA_WIDTH-1 downto 0);
S4_AXI_WSTRB : in std_logic_vector((C_S4_AXI_DATA_WIDTH/8)-1 downto 0);
S4_AXI_WVALID : in std_logic;
S4_AXI_WREADY : out std_logic;
S4_AXI_BRESP : out std_logic_vector(1 downto 0);
S4_AXI_BVALID : out std_logic;
S4_AXI_BREADY : in std_logic;
S4_AXI_ARADDR : in std_logic_vector(C_S4_AXI_ADDR_WIDTH-1 downto 0);
S4_AXI_ARVALID : in std_logic;
S4_AXI_ARREADY : out std_logic;
S4_AXI_RDATA : out std_logic_vector(C_S4_AXI_DATA_WIDTH-1 downto 0);
S4_AXI_RRESP : out std_logic_vector(1 downto 0);
S4_AXI_RVALID : out std_logic;
S4_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #5 slave signals.
S5_AXI_ACLK : in std_logic;
S5_AXI_ARESETN : in std_logic;
S5_AXI_AWADDR : in std_logic_vector(C_S1_AXI_ADDR_WIDTH-1 downto 0);
S5_AXI_AWVALID : in std_logic;
S5_AXI_AWREADY : out std_logic;
S5_AXI_WDATA : in std_logic_vector(C_S5_AXI_DATA_WIDTH-1 downto 0);
S5_AXI_WSTRB : in std_logic_vector((C_S5_AXI_DATA_WIDTH/8)-1 downto 0);
S5_AXI_WVALID : in std_logic;
S5_AXI_WREADY : out std_logic;
S5_AXI_BRESP : out std_logic_vector(1 downto 0);
S5_AXI_BVALID : out std_logic;
S5_AXI_BREADY : in std_logic;
S5_AXI_ARADDR : in std_logic_vector(C_S5_AXI_ADDR_WIDTH-1 downto 0);
S5_AXI_ARVALID : in std_logic;
S5_AXI_ARREADY : out std_logic;
S5_AXI_RDATA : out std_logic_vector(C_S5_AXI_DATA_WIDTH-1 downto 0);
S5_AXI_RRESP : out std_logic_vector(1 downto 0);
S5_AXI_RVALID : out std_logic;
S5_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #6 slave signals.
S6_AXI_ACLK : in std_logic;
S6_AXI_ARESETN : in std_logic;
S6_AXI_AWADDR : in std_logic_vector(C_S6_AXI_ADDR_WIDTH-1 downto 0);
S6_AXI_AWVALID : in std_logic;
S6_AXI_AWREADY : out std_logic;
S6_AXI_WDATA : in std_logic_vector(C_S6_AXI_DATA_WIDTH-1 downto 0);
S6_AXI_WSTRB : in std_logic_vector((C_S6_AXI_DATA_WIDTH/8)-1 downto 0);
S6_AXI_WVALID : in std_logic;
S6_AXI_WREADY : out std_logic;
S6_AXI_BRESP : out std_logic_vector(1 downto 0);
S6_AXI_BVALID : out std_logic;
S6_AXI_BREADY : in std_logic;
S6_AXI_ARADDR : in std_logic_vector(C_S6_AXI_ADDR_WIDTH-1 downto 0);
S6_AXI_ARVALID : in std_logic;
S6_AXI_ARREADY : out std_logic;
S6_AXI_RDATA : out std_logic_vector(C_S6_AXI_DATA_WIDTH-1 downto 0);
S6_AXI_RRESP : out std_logic_vector(1 downto 0);
S6_AXI_RVALID : out std_logic;
S6_AXI_RREADY : in std_logic;
-- AXI4-Lite interface #7 slave signals.
S7_AXI_ACLK : in std_logic;
S7_AXI_ARESETN : in std_logic;
S7_AXI_AWADDR : in std_logic_vector(C_S7_AXI_ADDR_WIDTH-1 downto 0);
S7_AXI_AWVALID : in std_logic;
S7_AXI_AWREADY : out std_logic;
S7_AXI_WDATA : in std_logic_vector(C_S7_AXI_DATA_WIDTH-1 downto 0);
S7_AXI_WSTRB : in std_logic_vector((C_S7_AXI_DATA_WIDTH/8)-1 downto 0);
S7_AXI_WVALID : in std_logic;
S7_AXI_WREADY : out std_logic;
S7_AXI_BRESP : out std_logic_vector(1 downto 0);
S7_AXI_BVALID : out std_logic;
S7_AXI_BREADY : in std_logic;
S7_AXI_ARADDR : in std_logic_vector(C_S7_AXI_ADDR_WIDTH-1 downto 0);
S7_AXI_ARVALID : in std_logic;
S7_AXI_ARREADY : out std_logic;
S7_AXI_RDATA : out std_logic_vector(C_S7_AXI_DATA_WIDTH-1 downto 0);
S7_AXI_RRESP : out std_logic_vector(1 downto 0);
S7_AXI_RVALID : out std_logic;
S7_AXI_RREADY : in std_logic
);
end entity mutex;
library unisim;
use unisim.all;
architecture IMP of mutex is
-----------------------------------------------------------------------------
-- Function declaration
-----------------------------------------------------------------------------
-- Returns at least 1
function MakePos(a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
-- Returns the minimum value of the two parameters
function IntMin(a, b : integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function IntMin;
-- Returns the maximum value of the two parameters
function IntMax(a, b : integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function IntMax;
-- Returns the maximum value of the two parameters
function IntSelect(s : boolean; a, b : integer) return integer is
begin
if s then
return a;
else
return b;
end if;
end function IntSelect;
function Get_Num_Bits(data : natural) return natural is
variable num_bits : natural:= 1;
begin
while( data > 2**num_bits ) loop
num_bits := num_bits + 1;
end loop;
return num_bits;
end function Get_Num_Bits;
-----------------------------------------------------------------------------
-- Constant declaration
-----------------------------------------------------------------------------
-- Mutex specific.
constant C_NUM_INTERFACE : integer range 1 to 16 := C_NUM_AXI;
-- Number of interfaces to access Mutexes.
constant C_AXI_HW_ID_WIDTH : integer:= IntMax(IntMax(IntMax(IntSelect(C_NUM_AXI>0,1,0),
IntSelect(C_NUM_AXI>1,1,0)),
IntMax(IntSelect(C_NUM_AXI>2,1,0),
IntSelect(C_NUM_AXI>3,1,0))),
IntMax(IntMax(IntSelect(C_NUM_AXI>4,1,0),
IntSelect(C_NUM_AXI>5,1,0)),
IntMax(IntSelect(C_NUM_AXI>6,1,0),
IntSelect(C_NUM_AXI>7,1,0))));
constant C_HW_ID_WIDTH : integer:= C_AXI_HW_ID_WIDTH;
constant C_REGISTER_WIDTH : integer := 8; -- Width of register offset.
constant C_AWIDTH : integer := C_REGISTER_WIDTH + Get_Num_Bits(C_NUM_MUTEX);
-- Address bits including register offset.
constant C_DWIDTH : integer := 32; -- Width of data bus.
constant C_DWIDTH_USER_REG : integer := 32; -- Width of user data.
constant C_DWIDTH_MUTEX : integer := 1; -- Width of mutex field (usually 1).
-----------------------------------------------------------------------------
-- Component declaration
-----------------------------------------------------------------------------
component axi_decode is
generic (
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_ASYNC_CLKS : integer range 0 to 1 := 0;
C_NUM_SYNC_FF : integer range 1 to 8 := 2; -- Number of cycles to synchronize to new clock domain.
C_HW_ID_WIDTH : integer range 1 to 31 := 8; -- Number of bits for hardware id number.
C_AWIDTH : integer := 8; -- Address bits including register offset.
C_DWIDTH : integer := 32 -- Width of data bus.
);
port (
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Mutex signals.
Mutex_Clk : in std_logic;
Mutex_Rst : in std_logic;
Mutex_Access : out std_logic;
Mutex_RnW : out std_logic;
Mutex_HW_Id : out std_logic_vector(0 to C_HW_ID_WIDTH - 1);
Mutex_Addr : out std_logic_vector(0 to C_AWIDTH - 1);
Mutex_Wr_Data : out std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Rd_Data : in std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Ack : in std_logic
);
end component axi_decode;
component mutex_core is
generic (
-- General.
C_FAMILY : string := "virtex7";
-- Mutex specific.
C_NUM_INTERFACE : integer range 1 to 16 := 1; -- Number of interfaces to access Mutexes.
C_ENABLE_USER : integer range 0 to 1 := 1; -- If USER register is available.
C_OWNER_ID_WIDTH : integer range 0 to 31 := 8; -- Number of bits for id number.
C_HW_ID_WIDTH : integer range 1 to 31 := 8; -- Number of bits for hardware id number.
C_ENABLE_HW_PROT : integer range 0 to 1 := 0; -- If hardware security should be used.
C_NUM_MUTEX : integer := 16; -- Number of mutexes.
C_MUTEX_NUMBER : integer := 0; -- Mutex number.
C_AWIDTH : integer := 8; -- Address bits including register offset.
C_REGISTER_WIDTH : integer := 4; -- Width of register offset.
C_DWIDTH : integer := 32; -- Width of data bus.
C_DWIDTH_USER_REG : integer := 32; -- Width of user data.
C_DWIDTH_MUTEX : integer := 1 -- Width of mutex field (usually 1).
);
port (
-- System signals
Clk : in std_logic;
Rst : in std_logic;
-- Bus slave signals
Mutex_Access : in std_logic_vector(0 to C_NUM_INTERFACE - 1);
Mutex_RnW : in std_logic_vector(0 to C_NUM_INTERFACE - 1);
Mutex_HW_Id : in std_logic_vector(0 to C_NUM_INTERFACE * C_HW_ID_WIDTH - 1);
Mutex_Addr : in std_logic_vector(0 to C_NUM_INTERFACE * C_AWIDTH - 1);
Mutex_Wr_Data : in std_logic_vector(0 to C_NUM_INTERFACE * C_DWIDTH - 1);
Mutex_Rd_Data : out std_logic_vector(0 to C_DWIDTH - 1);
Mutex_Ack : out std_logic_vector(0 to C_NUM_INTERFACE - 1)
);
end component mutex_core;
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
-- Internal MUTEX signals.
signal Mutex_Clk : std_logic;
signal Mutex_Rst : std_logic;
signal Mutex_Access : std_logic_vector(0 to C_NUM_INTERFACE - 1);
signal Mutex_RnW : std_logic_vector(0 to C_NUM_INTERFACE - 1);
signal Mutex_HW_Id : std_logic_vector(0 to C_NUM_INTERFACE * C_HW_ID_WIDTH - 1);
signal Mutex_Addr : std_logic_vector(0 to C_NUM_INTERFACE * C_AWIDTH - 1);
signal Mutex_Wr_Data : std_logic_vector(0 to C_NUM_INTERFACE * C_DWIDTH - 1);
signal Mutex_Rd_Data : std_logic_vector(0 to C_NUM_INTERFACE * C_DWIDTH - 1);
signal Mutex_Ack : std_logic_vector(0 to C_NUM_INTERFACE - 1);
signal Mutex_Rd_Data_I : std_logic_vector(0 to C_DWIDTH - 1);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #0
-----------------------------------------------------------------------------
Using_AXI_0: if C_NUM_AXI > 0 generate
begin
AXI_If_0: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S0_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S0_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S0_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S0_AXI_DATA_WIDTH,
C_ASYNC_CLKS => 0,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S0_AXI_ACLK,
S_AXI_ARESETN => S0_AXI_ARESETN,
S_AXI_AWADDR => S0_AXI_AWADDR,
S_AXI_AWVALID => S0_AXI_AWVALID,
S_AXI_AWREADY => S0_AXI_AWREADY,
S_AXI_WDATA => S0_AXI_WDATA,
S_AXI_WSTRB => S0_AXI_WSTRB,
S_AXI_WVALID => S0_AXI_WVALID,
S_AXI_WREADY => S0_AXI_WREADY,
S_AXI_BRESP => S0_AXI_BRESP,
S_AXI_BVALID => S0_AXI_BVALID,
S_AXI_BREADY => S0_AXI_BREADY,
S_AXI_ARADDR => S0_AXI_ARADDR,
S_AXI_ARVALID => S0_AXI_ARVALID,
S_AXI_ARREADY => S0_AXI_ARREADY,
S_AXI_RDATA => S0_AXI_RDATA,
S_AXI_RRESP => S0_AXI_RRESP,
S_AXI_RVALID => S0_AXI_RVALID,
S_AXI_RREADY => S0_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(0),
Mutex_RnW => Mutex_RnW(0),
Mutex_HW_Id => Mutex_HW_Id((0) * C_HW_ID_WIDTH to (1) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((0) * C_AWIDTH to (1) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((0) * C_DWIDTH to (1) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((0) * C_DWIDTH to (1) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(0)
);
end generate Using_AXI_0;
No_AXI_0: if C_NUM_AXI < 1 generate
begin
S0_AXI_AWREADY <= '0';
S0_AXI_WREADY <= '0';
S0_AXI_BRESP <= (others=>'0');
S0_AXI_BVALID <= '0';
S0_AXI_ARREADY <= '0';
S0_AXI_RDATA <= (others=>'0');
S0_AXI_RRESP <= (others=>'0');
S0_AXI_RVALID <= '0';
end generate No_AXI_0;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #1
-----------------------------------------------------------------------------
Using_AXI_1: if C_NUM_AXI > 1 generate
begin
AXI_If_1: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S1_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S1_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S1_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S1_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S1_AXI_ACLK,
S_AXI_ARESETN => S1_AXI_ARESETN,
S_AXI_AWADDR => S1_AXI_AWADDR,
S_AXI_AWVALID => S1_AXI_AWVALID,
S_AXI_AWREADY => S1_AXI_AWREADY,
S_AXI_WDATA => S1_AXI_WDATA,
S_AXI_WSTRB => S1_AXI_WSTRB,
S_AXI_WVALID => S1_AXI_WVALID,
S_AXI_WREADY => S1_AXI_WREADY,
S_AXI_BRESP => S1_AXI_BRESP,
S_AXI_BVALID => S1_AXI_BVALID,
S_AXI_BREADY => S1_AXI_BREADY,
S_AXI_ARADDR => S1_AXI_ARADDR,
S_AXI_ARVALID => S1_AXI_ARVALID,
S_AXI_ARREADY => S1_AXI_ARREADY,
S_AXI_RDATA => S1_AXI_RDATA,
S_AXI_RRESP => S1_AXI_RRESP,
S_AXI_RVALID => S1_AXI_RVALID,
S_AXI_RREADY => S1_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(1),
Mutex_RnW => Mutex_RnW(1),
Mutex_HW_Id => Mutex_HW_Id((1) * C_HW_ID_WIDTH to (2) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((1) * C_AWIDTH to (2) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((1) * C_DWIDTH to (2) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((1) * C_DWIDTH to (2) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(1)
);
end generate Using_AXI_1;
No_AXI_1: if C_NUM_AXI < 2 generate
begin
S1_AXI_AWREADY <= '0';
S1_AXI_WREADY <= '0';
S1_AXI_BRESP <= (others=>'0');
S1_AXI_BVALID <= '0';
S1_AXI_ARREADY <= '0';
S1_AXI_RDATA <= (others=>'0');
S1_AXI_RRESP <= (others=>'0');
S1_AXI_RVALID <= '0';
end generate No_AXI_1;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #2
-----------------------------------------------------------------------------
Using_AXI_2: if C_NUM_AXI > 2 generate
begin
AXI_If_2: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S2_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S2_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S2_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S2_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S2_AXI_ACLK,
S_AXI_ARESETN => S2_AXI_ARESETN,
S_AXI_AWADDR => S2_AXI_AWADDR,
S_AXI_AWVALID => S2_AXI_AWVALID,
S_AXI_AWREADY => S2_AXI_AWREADY,
S_AXI_WDATA => S2_AXI_WDATA,
S_AXI_WSTRB => S2_AXI_WSTRB,
S_AXI_WVALID => S2_AXI_WVALID,
S_AXI_WREADY => S2_AXI_WREADY,
S_AXI_BRESP => S2_AXI_BRESP,
S_AXI_BVALID => S2_AXI_BVALID,
S_AXI_BREADY => S2_AXI_BREADY,
S_AXI_ARADDR => S2_AXI_ARADDR,
S_AXI_ARVALID => S2_AXI_ARVALID,
S_AXI_ARREADY => S2_AXI_ARREADY,
S_AXI_RDATA => S2_AXI_RDATA,
S_AXI_RRESP => S2_AXI_RRESP,
S_AXI_RVALID => S2_AXI_RVALID,
S_AXI_RREADY => S2_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(2),
Mutex_RnW => Mutex_RnW(2),
Mutex_HW_Id => Mutex_HW_Id((2) * C_HW_ID_WIDTH to (3) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((2) * C_AWIDTH to (3) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((2) * C_DWIDTH to (3) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((2) * C_DWIDTH to (3) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(2)
);
end generate Using_AXI_2;
No_AXI_2: if C_NUM_AXI < 3 generate
begin
S2_AXI_AWREADY <= '0';
S2_AXI_WREADY <= '0';
S2_AXI_BRESP <= (others=>'0');
S2_AXI_BVALID <= '0';
S2_AXI_ARREADY <= '0';
S2_AXI_RDATA <= (others=>'0');
S2_AXI_RRESP <= (others=>'0');
S2_AXI_RVALID <= '0';
end generate No_AXI_2;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #3
-----------------------------------------------------------------------------
Using_AXI_3: if C_NUM_AXI > 3 generate
begin
AXI_If_3: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S3_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S3_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S3_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S3_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S3_AXI_ACLK,
S_AXI_ARESETN => S3_AXI_ARESETN,
S_AXI_AWADDR => S3_AXI_AWADDR,
S_AXI_AWVALID => S3_AXI_AWVALID,
S_AXI_AWREADY => S3_AXI_AWREADY,
S_AXI_WDATA => S3_AXI_WDATA,
S_AXI_WSTRB => S3_AXI_WSTRB,
S_AXI_WVALID => S3_AXI_WVALID,
S_AXI_WREADY => S3_AXI_WREADY,
S_AXI_BRESP => S3_AXI_BRESP,
S_AXI_BVALID => S3_AXI_BVALID,
S_AXI_BREADY => S3_AXI_BREADY,
S_AXI_ARADDR => S3_AXI_ARADDR,
S_AXI_ARVALID => S3_AXI_ARVALID,
S_AXI_ARREADY => S3_AXI_ARREADY,
S_AXI_RDATA => S3_AXI_RDATA,
S_AXI_RRESP => S3_AXI_RRESP,
S_AXI_RVALID => S3_AXI_RVALID,
S_AXI_RREADY => S3_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(3),
Mutex_RnW => Mutex_RnW(3),
Mutex_HW_Id => Mutex_HW_Id((3) * C_HW_ID_WIDTH to (4) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((3) * C_AWIDTH to (4) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((3) * C_DWIDTH to (4) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((3) * C_DWIDTH to (4) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(3)
);
end generate Using_AXI_3;
No_AXI_3: if C_NUM_AXI < 4 generate
begin
S3_AXI_AWREADY <= '0';
S3_AXI_WREADY <= '0';
S3_AXI_BRESP <= (others=>'0');
S3_AXI_BVALID <= '0';
S3_AXI_ARREADY <= '0';
S3_AXI_RDATA <= (others=>'0');
S3_AXI_RRESP <= (others=>'0');
S3_AXI_RVALID <= '0';
end generate No_AXI_3;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #4
-----------------------------------------------------------------------------
Using_AXI_4: if C_NUM_AXI > 4 generate
begin
AXI_If_4: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S4_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S4_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S4_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S4_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S4_AXI_ACLK,
S_AXI_ARESETN => S4_AXI_ARESETN,
S_AXI_AWADDR => S4_AXI_AWADDR,
S_AXI_AWVALID => S4_AXI_AWVALID,
S_AXI_AWREADY => S4_AXI_AWREADY,
S_AXI_WDATA => S4_AXI_WDATA,
S_AXI_WSTRB => S4_AXI_WSTRB,
S_AXI_WVALID => S4_AXI_WVALID,
S_AXI_WREADY => S4_AXI_WREADY,
S_AXI_BRESP => S4_AXI_BRESP,
S_AXI_BVALID => S4_AXI_BVALID,
S_AXI_BREADY => S4_AXI_BREADY,
S_AXI_ARADDR => S4_AXI_ARADDR,
S_AXI_ARVALID => S4_AXI_ARVALID,
S_AXI_ARREADY => S4_AXI_ARREADY,
S_AXI_RDATA => S4_AXI_RDATA,
S_AXI_RRESP => S4_AXI_RRESP,
S_AXI_RVALID => S4_AXI_RVALID,
S_AXI_RREADY => S4_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(4),
Mutex_RnW => Mutex_RnW(4),
Mutex_HW_Id => Mutex_HW_Id((4) * C_HW_ID_WIDTH to (5) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((4) * C_AWIDTH to (5) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((4) * C_DWIDTH to (5) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((4) * C_DWIDTH to (5) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(4)
);
end generate Using_AXI_4;
No_AXI_4: if C_NUM_AXI < 5 generate
begin
S4_AXI_AWREADY <= '0';
S4_AXI_WREADY <= '0';
S4_AXI_BRESP <= (others=>'0');
S4_AXI_BVALID <= '0';
S4_AXI_ARREADY <= '0';
S4_AXI_RDATA <= (others=>'0');
S4_AXI_RRESP <= (others=>'0');
S4_AXI_RVALID <= '0';
end generate No_AXI_4;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #5
-----------------------------------------------------------------------------
Using_AXI_5: if C_NUM_AXI > 5 generate
begin
AXI_If_5: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S5_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S5_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S5_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S5_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S5_AXI_ACLK,
S_AXI_ARESETN => S5_AXI_ARESETN,
S_AXI_AWADDR => S5_AXI_AWADDR,
S_AXI_AWVALID => S5_AXI_AWVALID,
S_AXI_AWREADY => S5_AXI_AWREADY,
S_AXI_WDATA => S5_AXI_WDATA,
S_AXI_WSTRB => S5_AXI_WSTRB,
S_AXI_WVALID => S5_AXI_WVALID,
S_AXI_WREADY => S5_AXI_WREADY,
S_AXI_BRESP => S5_AXI_BRESP,
S_AXI_BVALID => S5_AXI_BVALID,
S_AXI_BREADY => S5_AXI_BREADY,
S_AXI_ARADDR => S5_AXI_ARADDR,
S_AXI_ARVALID => S5_AXI_ARVALID,
S_AXI_ARREADY => S5_AXI_ARREADY,
S_AXI_RDATA => S5_AXI_RDATA,
S_AXI_RRESP => S5_AXI_RRESP,
S_AXI_RVALID => S5_AXI_RVALID,
S_AXI_RREADY => S5_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(5),
Mutex_RnW => Mutex_RnW(5),
Mutex_HW_Id => Mutex_HW_Id((5) * C_HW_ID_WIDTH to (6) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((5) * C_AWIDTH to (6) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((5) * C_DWIDTH to (6) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((5) * C_DWIDTH to (6) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(5)
);
end generate Using_AXI_5;
No_AXI_5: if C_NUM_AXI < 6 generate
begin
S5_AXI_AWREADY <= '0';
S5_AXI_WREADY <= '0';
S5_AXI_BRESP <= (others=>'0');
S5_AXI_BVALID <= '0';
S5_AXI_ARREADY <= '0';
S5_AXI_RDATA <= (others=>'0');
S5_AXI_RRESP <= (others=>'0');
S5_AXI_RVALID <= '0';
end generate No_AXI_5;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #6
-----------------------------------------------------------------------------
Using_AXI_6: if C_NUM_AXI > 6 generate
begin
AXI_If_6: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S6_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S6_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S6_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S6_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S6_AXI_ACLK,
S_AXI_ARESETN => S6_AXI_ARESETN,
S_AXI_AWADDR => S6_AXI_AWADDR,
S_AXI_AWVALID => S6_AXI_AWVALID,
S_AXI_AWREADY => S6_AXI_AWREADY,
S_AXI_WDATA => S6_AXI_WDATA,
S_AXI_WSTRB => S6_AXI_WSTRB,
S_AXI_WVALID => S6_AXI_WVALID,
S_AXI_WREADY => S6_AXI_WREADY,
S_AXI_BRESP => S6_AXI_BRESP,
S_AXI_BVALID => S6_AXI_BVALID,
S_AXI_BREADY => S6_AXI_BREADY,
S_AXI_ARADDR => S6_AXI_ARADDR,
S_AXI_ARVALID => S6_AXI_ARVALID,
S_AXI_ARREADY => S6_AXI_ARREADY,
S_AXI_RDATA => S6_AXI_RDATA,
S_AXI_RRESP => S6_AXI_RRESP,
S_AXI_RVALID => S6_AXI_RVALID,
S_AXI_RREADY => S6_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(6),
Mutex_RnW => Mutex_RnW(6),
Mutex_HW_Id => Mutex_HW_Id((6) * C_HW_ID_WIDTH to (7) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((6) * C_AWIDTH to (7) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((6) * C_DWIDTH to (7) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((6) * C_DWIDTH to (7) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(6)
);
end generate Using_AXI_6;
No_AXI_6: if C_NUM_AXI < 7 generate
begin
S6_AXI_AWREADY <= '0';
S6_AXI_WREADY <= '0';
S6_AXI_BRESP <= (others=>'0');
S6_AXI_BVALID <= '0';
S6_AXI_ARREADY <= '0';
S6_AXI_RDATA <= (others=>'0');
S6_AXI_RRESP <= (others=>'0');
S6_AXI_RVALID <= '0';
end generate No_AXI_6;
-----------------------------------------------------------------------------
-- Instantiating MUTEX AXI Interface #7
-----------------------------------------------------------------------------
Using_AXI_7: if C_NUM_AXI > 7 generate
begin
AXI_If_7: axi_decode
generic map(
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR => C_S7_AXI_BASEADDR,
C_S_AXI_HIGHADDR => C_S7_AXI_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S7_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S7_AXI_DATA_WIDTH,
C_ASYNC_CLKS => C_ASYNC_CLKS,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH
)
port map(
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_ACLK => S7_AXI_ACLK,
S_AXI_ARESETN => S7_AXI_ARESETN,
S_AXI_AWADDR => S7_AXI_AWADDR,
S_AXI_AWVALID => S7_AXI_AWVALID,
S_AXI_AWREADY => S7_AXI_AWREADY,
S_AXI_WDATA => S7_AXI_WDATA,
S_AXI_WSTRB => S7_AXI_WSTRB,
S_AXI_WVALID => S7_AXI_WVALID,
S_AXI_WREADY => S7_AXI_WREADY,
S_AXI_BRESP => S7_AXI_BRESP,
S_AXI_BVALID => S7_AXI_BVALID,
S_AXI_BREADY => S7_AXI_BREADY,
S_AXI_ARADDR => S7_AXI_ARADDR,
S_AXI_ARVALID => S7_AXI_ARVALID,
S_AXI_ARREADY => S7_AXI_ARREADY,
S_AXI_RDATA => S7_AXI_RDATA,
S_AXI_RRESP => S7_AXI_RRESP,
S_AXI_RVALID => S7_AXI_RVALID,
S_AXI_RREADY => S7_AXI_RREADY,
-- Mutex signals.
Mutex_Clk => Mutex_Clk,
Mutex_Rst => Mutex_Rst,
Mutex_Access => Mutex_Access(7),
Mutex_RnW => Mutex_RnW(7),
Mutex_HW_Id => Mutex_HW_Id((7) * C_HW_ID_WIDTH to (8) * C_HW_ID_WIDTH - 1),
Mutex_Addr => Mutex_Addr((7) * C_AWIDTH to (8) * C_AWIDTH - 1),
Mutex_Wr_Data => Mutex_Wr_Data((7) * C_DWIDTH to (8) * C_DWIDTH - 1),
Mutex_Rd_Data => Mutex_Rd_Data((7) * C_DWIDTH to (8) * C_DWIDTH - 1),
Mutex_Ack => Mutex_Ack(7)
);
end generate Using_AXI_7;
No_AXI_7: if C_NUM_AXI < 8 generate
begin
S7_AXI_AWREADY <= '0';
S7_AXI_WREADY <= '0';
S7_AXI_BRESP <= (others=>'0');
S7_AXI_BVALID <= '0';
S7_AXI_ARREADY <= '0';
S7_AXI_RDATA <= (others=>'0');
S7_AXI_RRESP <= (others=>'0');
S7_AXI_RVALID <= '0';
end generate No_AXI_7;
-----------------------------------------------------------------------------
-- Instantiating MUTEX Core
-----------------------------------------------------------------------------
Mutex_Clk <= S0_AXI_ACLK;
Mutex_Rst <= not S0_AXI_ARESETN;
SingleAccess: mutex_core
generic map(
-- General.
C_FAMILY => C_FAMILY,
-- Mutex specific.
C_NUM_INTERFACE => C_NUM_INTERFACE,
C_ENABLE_USER => C_ENABLE_USER,
C_OWNER_ID_WIDTH => C_OWNER_ID_WIDTH,
C_HW_ID_WIDTH => C_HW_ID_WIDTH,
C_ENABLE_HW_PROT => C_ENABLE_HW_PROT,
C_NUM_MUTEX => C_NUM_MUTEX,
C_MUTEX_NUMBER => 0,
C_AWIDTH => C_AWIDTH,
C_REGISTER_WIDTH => C_REGISTER_WIDTH,
C_DWIDTH => C_DWIDTH,
C_DWIDTH_MUTEX => C_DWIDTH_MUTEX
)
port map(
-- System signals
Clk => Mutex_Clk,
Rst => Mutex_Rst,
-- Bus slave signals
Mutex_Access => Mutex_Access,
Mutex_RnW => Mutex_RnW,
Mutex_HW_Id => Mutex_HW_Id,
Mutex_Addr => Mutex_Addr,
Mutex_Wr_Data => Mutex_Wr_Data,
Mutex_Rd_Data => Mutex_Rd_Data_I,
Mutex_Ack => Mutex_Ack
);
-- Distribute result to all interfaces.
If_Num_Distr: for I in 0 to C_NUM_INTERFACE - 1 generate
begin
Mutex_Rd_Data(I * C_DWIDTH to (I + 1) * C_DWIDTH - 1) <= Mutex_Rd_Data_I;
end generate If_Num_Distr;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- Title : Infrared Receiver Package
-- Project :
-------------------------------------------------------------------------------
-- File : ir_rx_pkg.vhd
-- Author : strongly-typed
-- Created : 2012-04-15
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bus_pkg.all;
use work.adc_ltc2351_pkg.all;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
package ir_rx_module_pkg is
type ir_rx_module_spi_out_type is array (1 downto 0) of adc_ltc2351_spi_out_type;
type ir_rx_module_spi_in_type is array (1 downto 0) of adc_ltc2351_spi_in_type;
component ir_rx_module is
generic (
BASE_ADDRESS_COEFS : integer range 0 to 16#7FFF#;
BASE_ADDRESS_RESULTS : integer range 0 to 16#7FFF#;
BASE_ADDRESS_TIMESTAMP : integer range 0 to 16#7FFF#);
port (
adc_o_p : out ir_rx_module_spi_out_type;
adc_i_p : in ir_rx_module_spi_in_type;
adc_values_o_p : out adc_ltc2351_values_type(11 downto 0);
sync_o_p : out std_logic;
bus_o_p : out busdevice_out_type;
bus_i_p : in busdevice_in_type;
done_o_p : out std_logic;
ack_i_p : in std_logic;
clk_sample_en_i_p : in std_logic;
timestamp_i_p : in timestamp_type;
clk : in std_logic);
end component ir_rx_module;
component ir_rx_adcs
generic (
CHANNELS : positive);
port (
clk_sample_en_i_p : in std_logic;
adc_o_p : out ir_rx_module_spi_out_type;
adc_i_p : in ir_rx_module_spi_in_type;
adc_values_o_p : out adc_ltc2351_values_type;
adc_done_o_p : out std_logic;
clk : in std_logic);
end component;
end ir_rx_module_pkg;
|
-------------------------------------------------------------------------------
-- Title : Infrared Receiver Package
-- Project :
-------------------------------------------------------------------------------
-- File : ir_rx_pkg.vhd
-- Author : strongly-typed
-- Created : 2012-04-15
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bus_pkg.all;
use work.adc_ltc2351_pkg.all;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
package ir_rx_module_pkg is
type ir_rx_module_spi_out_type is array (1 downto 0) of adc_ltc2351_spi_out_type;
type ir_rx_module_spi_in_type is array (1 downto 0) of adc_ltc2351_spi_in_type;
component ir_rx_module is
generic (
BASE_ADDRESS_COEFS : integer range 0 to 16#7FFF#;
BASE_ADDRESS_RESULTS : integer range 0 to 16#7FFF#;
BASE_ADDRESS_TIMESTAMP : integer range 0 to 16#7FFF#);
port (
adc_o_p : out ir_rx_module_spi_out_type;
adc_i_p : in ir_rx_module_spi_in_type;
adc_values_o_p : out adc_ltc2351_values_type(11 downto 0);
sync_o_p : out std_logic;
bus_o_p : out busdevice_out_type;
bus_i_p : in busdevice_in_type;
done_o_p : out std_logic;
ack_i_p : in std_logic;
clk_sample_en_i_p : in std_logic;
timestamp_i_p : in timestamp_type;
clk : in std_logic);
end component ir_rx_module;
component ir_rx_adcs
generic (
CHANNELS : positive);
port (
clk_sample_en_i_p : in std_logic;
adc_o_p : out ir_rx_module_spi_out_type;
adc_i_p : in ir_rx_module_spi_in_type;
adc_values_o_p : out adc_ltc2351_values_type;
adc_done_o_p : out std_logic;
clk : in std_logic);
end component;
end ir_rx_module_pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1739.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p10n01i01739ent IS
begin
assert false
report "Success:entity assertion with static expression"
severity NOTE;
END c09s04b00x00p10n01i01739ent;
ARCHITECTURE c09s04b00x00p10n01i01739arch OF c09s04b00x00p10n01i01739ent IS
BEGIN
assert false
report "Success:architecture assertion with static expression"
severity NOTE;
b: block
begin
assert false
report "Success:architecture in block: assertion with static expression"
severity NOTE;
end block b;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s04b00x00p10n01i01739 - This test need manual check, three assertion notes of Success should appear."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s04b00x00p10n01i01739arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1739.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p10n01i01739ent IS
begin
assert false
report "Success:entity assertion with static expression"
severity NOTE;
END c09s04b00x00p10n01i01739ent;
ARCHITECTURE c09s04b00x00p10n01i01739arch OF c09s04b00x00p10n01i01739ent IS
BEGIN
assert false
report "Success:architecture assertion with static expression"
severity NOTE;
b: block
begin
assert false
report "Success:architecture in block: assertion with static expression"
severity NOTE;
end block b;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s04b00x00p10n01i01739 - This test need manual check, three assertion notes of Success should appear."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s04b00x00p10n01i01739arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1739.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p10n01i01739ent IS
begin
assert false
report "Success:entity assertion with static expression"
severity NOTE;
END c09s04b00x00p10n01i01739ent;
ARCHITECTURE c09s04b00x00p10n01i01739arch OF c09s04b00x00p10n01i01739ent IS
BEGIN
assert false
report "Success:architecture assertion with static expression"
severity NOTE;
b: block
begin
assert false
report "Success:architecture in block: assertion with static expression"
severity NOTE;
end block b;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s04b00x00p10n01i01739 - This test need manual check, three assertion notes of Success should appear."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s04b00x00p10n01i01739arch;
|
-- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.std_logic_1164.all;
use work.Constants.all;
use IEEE.Numeric_std.all;
use std.textio.all;
entity Memory_TB is
end Memory_TB;
architecture Behavioral of Memory_TB is
component MemoryController
port (
Address : in word;
Enable : in std_logic;
ToWrite : in word;
FromRead : out word;
Instruction : in word;
Reset : in std_logic;
Done : out std_logic);
end component;
signal Address : word := (others => '0');
signal Enable : std_logic := '0';
signal ToWrite : word := (others => '0');
signal FromRead : word;
signal Instruction : word := (others => '0');
begin -- Behavioral
MC : MemoryController port map (
Address => Address,
Enable => Enable,
ToWrite => ToWrite,
FromRead => FromRead,
Instruction => Instruction,
Reset => '0');
file_io:
process is
variable in_line : line;
variable out_line : line;
variable in_vector : bit_vector(7 downto 0) := (others => '0');
variable outputI : integer := 0;
variable Counter : integer := 0;
variable NextByte : Byte := (others => '0');
begin -- process
while not endfile(input) loop
readline(input, in_line);
if in_line'length = 8 then
read(in_line, in_vector);
NextByte := to_stdlogicvector(in_vector);
ToWrite <= std_logic_vector(resize(unsigned(NextByte), 32));
Instruction <= OpcodeMemory & StoreByte & "00000" & "000000000000000000000";
Address <= std_logic_vector(to_unsigned(Counter, 32));
wait for 1 ns;
Enable <= '1';
wait for 1 ns;
Enable <= '0';
Counter := Counter + 1;
else
writeline(output,in_line);
end if;
end loop;
--write(out_line, string'("===============ByteRead================"));
-- write(output, out_line);
for i in 0 to Counter loop
Instruction <= OpcodeMemory & LoadByteUnsigned & "00000" & "000000000000000000000";
Address <= std_logic_vector(to_unsigned(i, 32));
wait for 1 ns;
write(out_line, to_integer(unsigned(Address)));
writeline(output, out_line);
Enable <= '1';
wait for 1 ns;
Enable <= '0';
NextByte := FromRead(7 downto 0);
write(out_line, to_bitvector(NextByte));
writeline(output, out_line);
end loop; -- i
for I in 0 to Counter / 2 loop
Instruction <= OpcodeMemory & LoadHalfWordUnsigned & "00000" & "000000000000000000000";
Address <= std_logic_vector(to_unsigned(i*2, 32));
wait for 1 ns;
write(out_line, to_integer(unsigned(Address)));
writeline(output, out_line);
Enable <= '1';
wait for 1 ns;
Enable <= '0';
write(out_line, to_bitvector(FromRead(15 downto 0)));
writeline(output, out_line);
end loop; -- I
for I in 0 to Counter / 4 loop
Instruction <= OpcodeMemory & LoadWord & "00000" & "000000000000000000000";
Address <= std_logic_vector(to_unsigned(i*4, 32));
wait for 1 ns;
write(out_line, to_integer(unsigned(Address)));
writeline(output, out_line);
Enable <= '1';
wait for 1 ns;
Enable <= '0';
write(out_line, to_bitvector(FromRead(31 downto 0)));
writeline(output, out_line);
end loop; -- I
wait;
end process;
end Behavioral;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:15:30)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END mesahb_alap_entity;
ARCHITECTURE mesahb_alap_description OF mesahb_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
WHEN "00000010" =>
register1 := register1 + 3;
register2 := input2 * 4;
WHEN "00000011" =>
register1 := register1 * 6;
register3 := input3 * 7;
register2 := register2 + 9;
WHEN "00000100" =>
register1 := register1 + 11;
register3 := register3 + 13;
register2 := ((NOT register2) + 1) XOR register2;
register4 := input4 * 16;
WHEN "00000101" =>
register1 := ((NOT register1) + 1) XOR register1;
register3 := register3 * 20;
register2 := register4 * register2;
WHEN "00000110" =>
register1 := register1 * 22;
register3 := register3 + 24;
WHEN "00000111" =>
register1 := register1 + register2;
output1 <= input5 + 25;
WHEN "00001000" =>
output2 <= register1(0 TO 1) & register3(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_alap_description; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:03:41 02/06/2015
-- Design Name:
-- Module Name: adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port( a,b: in std_logic_vector ( 3 downto 0);
s: out std_logic_vector ( 3 downto 0);
cf, ovf: out std_logic);
end adder;
architecture archi of adder is
begin
process(a,b)
variable temp: std_logic_vector(4 downto 0);
begin
temp := ( '0' & a ) + ( '0' & b ) ;
s <= temp (3 downto 0) ;
cf <= temp(4) ;
ovf <= temp(3) xor a(3) xor b(3) xor temp(4) ;
end process;
end archi; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:03:41 02/06/2015
-- Design Name:
-- Module Name: adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port( a,b: in std_logic_vector ( 3 downto 0);
s: out std_logic_vector ( 3 downto 0);
cf, ovf: out std_logic);
end adder;
architecture archi of adder is
begin
process(a,b)
variable temp: std_logic_vector(4 downto 0);
begin
temp := ( '0' & a ) + ( '0' & b ) ;
s <= temp (3 downto 0) ;
cf <= temp(4) ;
ovf <= temp(3) xor a(3) xor b(3) xor temp(4) ;
end process;
end archi; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity ddr2ctrl is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
avl_ready : out std_logic; -- avl.waitrequest_n
avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avl_rdata_valid : out std_logic; -- .readdatavalid
avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
avl_wdata : in std_logic_vector(255 downto 0) := (others => '0'); -- .writedata
avl_be : in std_logic_vector(31 downto 0) := (others => '0'); -- .byteenable
avl_read_req : in std_logic := '0'; -- .read
avl_write_req : in std_logic := '0'; -- .write
avl_size : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end ddr2ctrl;
architecture sim of ddr2ctrl is
signal lafi_clk, lafi_rst_n: std_ulogic;
signal lafi_half_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_half_clk <= lafi_half_clk;
afi_reset_n <= lafi_rst_n;
mem_a <= (others => '0');
mem_ba <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_ras_n <= (others => '1');
mem_cas_n <= (others => '1');
mem_we_n <= (others => '1');
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
mem_odt <= (others => '0');
avl_ready <= '1';
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
-- 200 MHz clock
clkproc: process
begin
lafi_clk <= '0';
lafi_half_clk <= '0';
loop
wait for 2.5 ns;
lafi_clk <= not lafi_clk;
if lafi_clk='0' then
lafi_half_clk <= not lafi_half_clk;
end if;
end loop;
end process;
rstproc: process
begin
lafi_rst_n <= '0';
wait for 10 ns;
loop
if global_reset_n='0' then
lafi_rst_n <= '0';
wait until global_reset_n/='0';
wait until rising_edge(lafi_clk);
end if;
lafi_rst_n <= '1';
wait until global_reset_n='0';
end loop;
end process;
avlproc: process
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**20)-1)) of BYTE;
variable MEMA: MEM;
procedure load_srec is
file TCF : text open read_mode is "ram.srec";
variable L1: line;
variable CH: character;
variable ai: integer;
variable rectype: std_logic_vector(3 downto 0);
variable recaddr: std_logic_vector(31 downto 0);
variable reclen: std_logic_vector(7 downto 0);
variable recdata: std_logic_vector(0 to 16*8-1);
variable len: integer;
begin
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
len := len-2;
when "0010" =>
hread(L1, recaddr(23 downto 0));
len := len-3;
when "0011" =>
hread(L1, recaddr);
len := len-4;
when others => next;
end case;
hread(L1, recdata(0 to 8*len-1));
recaddr(31 downto 20) := (others => '0');
ai := conv_integer(recaddr);
-- print("Setting " & tost(len) & "bytes at " & tost(recaddr));
for i in 0 to len-1 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
end if;
end if;
end if;
end loop;
end load_srec;
constant avldbits: integer := 256;
variable outqueue: std_logic_vector(0 to 4*avldbits-1) := (others => 'X');
variable outqueue_valid: std_logic_vector(0 to 3) := (others => '0');
variable ai,p: integer;
variable wbleft: integer := 0;
begin
load_srec;
loop
wait until rising_edge(lafi_clk);
avl_rdata_valid <= outqueue_valid(0);
avl_rdata <= outqueue(0 to avldbits-1);
outqueue(0 to 3*avldbits-1) := outqueue(avldbits to 4*avldbits-1);
outqueue(3*avldbits to 4*avldbits-1) := (others => 'X');
outqueue_valid := outqueue_valid(1 to 3) & '0';
if avl_burstbegin='1' then wbleft:=0; end if;
if lafi_rst_n='0' then
outqueue_valid := (others => '0');
elsif avl_read_req='1' then
ai := conv_integer(avl_addr(16 downto 0));
p := 0;
while outqueue_valid(p)='1' loop p:=p+1; end loop;
for x in 0 to conv_integer(avl_size)-1 loop
for y in 0 to avldbits/8-1 loop
outqueue((p+x)*avldbits+y*8 to (p+x)*avldbits+y*8+7) := MEMA((ai+x)*avldbits/8+y);
end loop;
outqueue_valid(p+x) := '1';
end loop;
elsif avl_write_req='1' then
if wbleft=0 then
wbleft := conv_integer(avl_size);
ai := conv_integer(avl_addr(16 downto 0));
end if;
for y in 0 to avldbits/8-1 loop
if avl_be(avldbits/8-1-y)='1' then
MEMA(ai*avldbits/8+y) := avl_wdata(avldbits-8*y-1 downto avldbits-8*y-8);
end if;
end loop;
wbleft := wbleft-1;
ai := ai+1;
end if;
end loop;
end process;
end;
|
----------------------------------------------------------------------------------
--
-- Author: Adam Howard - [email protected], Ben Olson - [email protected]
-- ECE-351: Course Project - Greenhouse Monitor
-- Notes: Button debouncing and control logic
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity btn_control is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
btn_bus : in STD_LOGIC_VECTOR (3 downto 0);
output_bus : out STD_LOGIC_VECTOR (3 downto 0));
end btn_control;
architecture btn_control_arch of btn_control is
signal stage1, stage2 : std_logic_vector(3 downto 0) := "0000";
signal lock : std_logic := '0';
begin
--debounce the input buttons, and only allow one to pulse per press
BTN_DEBOUNCE: process(clk, rst) is
begin
if (rst = '1') then
stage1 <= "0000";
stage2 <= "0000";
lock <= '0';
elsif (rising_edge(clk)) then
stage1 <= btn_bus;
stage2 <= stage1;
lock <= (stage2(3) or stage2(2) or stage2(1) or stage2(0));
end if;
end process BTN_DEBOUNCE;
output_bus(3) <= stage1(3) and stage2(3) and (not lock);
output_bus(2) <= stage1(2) and stage2(2) and (not lock);
output_bus(1) <= stage1(1) and stage2(1) and (not lock);
output_bus(0) <= stage1(0) and stage2(0) and (not lock);
end btn_control_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Bus_Arbitter is
port(clk: in std_logic;
rst: in std_logic;
correq: in std_logic;
cordone: in std_logic;
req_1: in std_logic;
req_2: in std_logic;
req_3: in std_logic;
req_4: in std_logic;
grant_1: out std_logic;
grant_2: out std_logic;
grant_3: out std_logic;
grant_4: out std_logic;
corslave: out std_logic;
corgrant: out std_logic);
end entity Bus_Arbitter;
-------------------------------------------------------------------------------
architecture arch of Bus_Arbitter is
type bus_states is (ready,cor_granted,node_granted,stall);
signal state, next_state: bus_states;
type orders_type is array(3 downto 0) of std_logic_vector(1 downto 0);
signal queue: orders_type;
signal shift_queue: std_logic;
signal nodes_requested: std_logic;
signal selected_node: std_logic_vector(1 downto 0);
begin -- architecture arch
nodes_requested <= req_1 or req_2 or req_3 or req_4;
process(queue, req_1, req_2, req_3, req_4)
begin
if(queue(0)="00" and req_1='1') then
selected_node<="00";
elsif(queue(0)="01" and req_2='1') then
selected_node<="00";
elsif(queue(0)="10" and req_3='1') then
selected_node<="00";
elsif(queue(0)="11" and req_2='1') then
selected_node<="00";
elsif(queue(1)="00" and req_1='1') then
selected_node<="01";
elsif(queue(1)="01" and req_2='1') then
selected_node<="01";
elsif(queue(1)="10" and req_3='1') then
selected_node<="01";
elsif(queue(1)="11" and req_2='1') then
selected_node<="01";
elsif(queue(2)="00" and req_1='1') then
selected_node<="10";
elsif(queue(2)="01" and req_2='1') then
selected_node<="10";
elsif(queue(2)="10" and req_3='1') then
selected_node<="10";
elsif(queue(2)="11" and req_2='1') then
selected_node<="10";
elsif(queue(3)="00" and req_1='1') then
selected_node<="11";
elsif(queue(3)="01" and req_2='1') then
selected_node<="11";
elsif(queue(3)="10" and req_3='1') then
selected_node<="11";
elsif(queue(3)="11" and req_2='1') then
selected_node<="11";
end if;
end process;
process (clk,rst)
begin
if(rst='1') then
queue(0) <= "00";
queue(1) <= "01";
queue(2) <= "10";
queue(3) <= "11";
elsif(clk='1' and clk'Event) then
if(shift_queue = '1') then
for i in 0 to 2 loop
if (i >= unsigned(selected_node)) then
queue(i) <= queue(i+1);
end if;
end loop;
queue(3) <= queue(to_integer(unsigned(selected_node)));
end if;
end if;
end process;
process (clk, rst)
begin
if(rst='1') then
state <= ready;
elsif (clk='1' and clk'Event) then
state <= next_state;
end if;
end process;
process (state, correq, cordone, nodes_requested)
begin
case state is
when ready => if(correq='1') then
next_state <= cor_granted;
elsif(nodes_requested='1') then
next_state <= node_granted;
else
next_state <= ready;
end if;
when cor_granted => if(cordone='1') then
next_state <= ready;
else
next_state <= cor_granted;
end if;
when node_granted => next_state <= stall;
when stall => next_state <= ready;
end case;
end process;
process (state)
begin
case state is
when ready => shift_queue<='0'; grant_1<='0'; grant_2<='0'; grant_3<='0'; grant_4<='0'; corslave<='0'; corgrant<='0';
when cor_granted => shift_queue<='0'; grant_1<='0'; grant_2<='0'; grant_3<='0'; grant_4<='0'; corslave<='0'; corgrant<='1';
when node_granted => shift_queue<='1'; grant_1<='0'; grant_2<='0'; grant_3<='0'; grant_4<='0'; corslave<='1'; corgrant<='0';
case queue(to_integer(unsigned(selected_node))) is
when "00" => grant_1<='1';
when "01" => grant_2<='1';
when "10" => grant_3<='1';
when others => grant_4<='1';
end case;
when stall => shift_queue<='0'; grant_1<='0'; grant_2<='0'; grant_3<='0'; grant_4<='0'; corslave<='0'; corgrant<='0';
end case;
end process;
end architecture arch;
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
package main_pack is
constant cpu_width : integer := 32;
constant ram_size : integer := 1935;
subtype word_type is std_logic_vector(cpu_width-1 downto 0);
type ram_type is array(0 to ram_size-1) of word_type;
function load_hex return ram_type;
end package;
package body main_pack is
function load_hex return ram_type is
variable ram_buffer : ram_type := (others=>(others=>'0'));
begin
ram_buffer(0) := X"3C1C1001";
ram_buffer(1) := X"279C9E30";
ram_buffer(2) := X"3C1D1000";
ram_buffer(3) := X"27BD1E88";
ram_buffer(4) := X"0C000110";
ram_buffer(5) := X"00000000";
ram_buffer(6) := X"00000000";
ram_buffer(7) := X"00000000";
ram_buffer(8) := X"00000000";
ram_buffer(9) := X"00000000";
ram_buffer(10) := X"00000000";
ram_buffer(11) := X"00000000";
ram_buffer(12) := X"00000000";
ram_buffer(13) := X"00000000";
ram_buffer(14) := X"00000000";
ram_buffer(15) := X"23BDFF98";
ram_buffer(16) := X"AFA10010";
ram_buffer(17) := X"AFA20014";
ram_buffer(18) := X"AFA30018";
ram_buffer(19) := X"AFA4001C";
ram_buffer(20) := X"AFA50020";
ram_buffer(21) := X"AFA60024";
ram_buffer(22) := X"AFA70028";
ram_buffer(23) := X"AFA8002C";
ram_buffer(24) := X"AFA90030";
ram_buffer(25) := X"AFAA0034";
ram_buffer(26) := X"AFAB0038";
ram_buffer(27) := X"AFAC003C";
ram_buffer(28) := X"AFAD0040";
ram_buffer(29) := X"AFAE0044";
ram_buffer(30) := X"AFAF0048";
ram_buffer(31) := X"AFB8004C";
ram_buffer(32) := X"AFB90050";
ram_buffer(33) := X"AFBF0054";
ram_buffer(34) := X"401A7000";
ram_buffer(35) := X"235AFFFC";
ram_buffer(36) := X"AFBA0058";
ram_buffer(37) := X"0000D810";
ram_buffer(38) := X"AFBB005C";
ram_buffer(39) := X"0000D812";
ram_buffer(40) := X"AFBB0060";
ram_buffer(41) := X"0C0000E6";
ram_buffer(42) := X"23A50000";
ram_buffer(43) := X"8FA10010";
ram_buffer(44) := X"8FA20014";
ram_buffer(45) := X"8FA30018";
ram_buffer(46) := X"8FA4001C";
ram_buffer(47) := X"8FA50020";
ram_buffer(48) := X"8FA60024";
ram_buffer(49) := X"8FA70028";
ram_buffer(50) := X"8FA8002C";
ram_buffer(51) := X"8FA90030";
ram_buffer(52) := X"8FAA0034";
ram_buffer(53) := X"8FAB0038";
ram_buffer(54) := X"8FAC003C";
ram_buffer(55) := X"8FAD0040";
ram_buffer(56) := X"8FAE0044";
ram_buffer(57) := X"8FAF0048";
ram_buffer(58) := X"8FB8004C";
ram_buffer(59) := X"8FB90050";
ram_buffer(60) := X"8FBF0054";
ram_buffer(61) := X"8FBA0058";
ram_buffer(62) := X"8FBB005C";
ram_buffer(63) := X"03600011";
ram_buffer(64) := X"8FBB0060";
ram_buffer(65) := X"03600013";
ram_buffer(66) := X"23BD0068";
ram_buffer(67) := X"341B0001";
ram_buffer(68) := X"03400008";
ram_buffer(69) := X"409B6000";
ram_buffer(70) := X"40026000";
ram_buffer(71) := X"03E00008";
ram_buffer(72) := X"40846000";
ram_buffer(73) := X"3C051000";
ram_buffer(74) := X"24A50150";
ram_buffer(75) := X"8CA60000";
ram_buffer(76) := X"AC06003C";
ram_buffer(77) := X"8CA60004";
ram_buffer(78) := X"AC060040";
ram_buffer(79) := X"8CA60008";
ram_buffer(80) := X"AC060044";
ram_buffer(81) := X"8CA6000C";
ram_buffer(82) := X"03E00008";
ram_buffer(83) := X"AC060048";
ram_buffer(84) := X"3C1A1000";
ram_buffer(85) := X"375A003C";
ram_buffer(86) := X"03400008";
ram_buffer(87) := X"00000000";
ram_buffer(88) := X"00850019";
ram_buffer(89) := X"00001012";
ram_buffer(90) := X"00002010";
ram_buffer(91) := X"03E00008";
ram_buffer(92) := X"ACC40000";
ram_buffer(93) := X"0000000C";
ram_buffer(94) := X"03E00008";
ram_buffer(95) := X"00000000";
ram_buffer(96) := X"AC900000";
ram_buffer(97) := X"AC910004";
ram_buffer(98) := X"AC920008";
ram_buffer(99) := X"AC93000C";
ram_buffer(100) := X"AC940010";
ram_buffer(101) := X"AC950014";
ram_buffer(102) := X"AC960018";
ram_buffer(103) := X"AC97001C";
ram_buffer(104) := X"AC9E0020";
ram_buffer(105) := X"AC9C0024";
ram_buffer(106) := X"AC9D0028";
ram_buffer(107) := X"AC9F002C";
ram_buffer(108) := X"03E00008";
ram_buffer(109) := X"34020000";
ram_buffer(110) := X"8C900000";
ram_buffer(111) := X"8C910004";
ram_buffer(112) := X"8C920008";
ram_buffer(113) := X"8C93000C";
ram_buffer(114) := X"8C940010";
ram_buffer(115) := X"8C950014";
ram_buffer(116) := X"8C960018";
ram_buffer(117) := X"8C97001C";
ram_buffer(118) := X"8C9E0020";
ram_buffer(119) := X"8C9C0024";
ram_buffer(120) := X"8C9D0028";
ram_buffer(121) := X"8C9F002C";
ram_buffer(122) := X"03E00008";
ram_buffer(123) := X"34A20000";
ram_buffer(124) := X"27BDFFE0";
ram_buffer(125) := X"AFBF001C";
ram_buffer(126) := X"AFB10018";
ram_buffer(127) := X"0C000610";
ram_buffer(128) := X"AFB00014";
ram_buffer(129) := X"0C0006BF";
ram_buffer(130) := X"24040001";
ram_buffer(131) := X"3C041000";
ram_buffer(132) := X"0C000701";
ram_buffer(133) := X"2484028C";
ram_buffer(134) := X"3C041000";
ram_buffer(135) := X"24840264";
ram_buffer(136) := X"3C101000";
ram_buffer(137) := X"0C000704";
ram_buffer(138) := X"3C111000";
ram_buffer(139) := X"26101D50";
ram_buffer(140) := X"263102D4";
ram_buffer(141) := X"2404000C";
ram_buffer(142) := X"0C000180";
ram_buffer(143) := X"AE110004";
ram_buffer(144) := X"2404000C";
ram_buffer(145) := X"0C000180";
ram_buffer(146) := X"AE110008";
ram_buffer(147) := X"8FBF001C";
ram_buffer(148) := X"8FB10018";
ram_buffer(149) := X"8FB00014";
ram_buffer(150) := X"00001025";
ram_buffer(151) := X"03E00008";
ram_buffer(152) := X"27BD0020";
ram_buffer(153) := X"3C02F000";
ram_buffer(154) := X"8C420004";
ram_buffer(155) := X"3C031000";
ram_buffer(156) := X"24631D5C";
ram_buffer(157) := X"00021080";
ram_buffer(158) := X"00431021";
ram_buffer(159) := X"8C420000";
ram_buffer(160) := X"24030001";
ram_buffer(161) := X"03E00008";
ram_buffer(162) := X"AC430000";
ram_buffer(163) := X"3C02F000";
ram_buffer(164) := X"8C430004";
ram_buffer(165) := X"24020001";
ram_buffer(166) := X"10620003";
ram_buffer(167) := X"00000000";
ram_buffer(168) := X"03E00008";
ram_buffer(169) := X"00000000";
ram_buffer(170) := X"27BDFFE8";
ram_buffer(171) := X"AFBF0014";
ram_buffer(172) := X"0C0006C8";
ram_buffer(173) := X"00000000";
ram_buffer(174) := X"8FBF0014";
ram_buffer(175) := X"24060004";
ram_buffer(176) := X"27858020";
ram_buffer(177) := X"24040004";
ram_buffer(178) := X"27BD0018";
ram_buffer(179) := X"0800016A";
ram_buffer(180) := X"AF828020";
ram_buffer(181) := X"27BDFFE8";
ram_buffer(182) := X"AFBF0014";
ram_buffer(183) := X"0C00065A";
ram_buffer(184) := X"00000000";
ram_buffer(185) := X"3C02F000";
ram_buffer(186) := X"8C430004";
ram_buffer(187) := X"24020001";
ram_buffer(188) := X"10620016";
ram_buffer(189) := X"00000000";
ram_buffer(190) := X"3C02F000";
ram_buffer(191) := X"8C430004";
ram_buffer(192) := X"24020002";
ram_buffer(193) := X"10620005";
ram_buffer(194) := X"00000000";
ram_buffer(195) := X"8FBF0014";
ram_buffer(196) := X"00000000";
ram_buffer(197) := X"03E00008";
ram_buffer(198) := X"27BD0018";
ram_buffer(199) := X"0C000190";
ram_buffer(200) := X"00000000";
ram_buffer(201) := X"8F848020";
ram_buffer(202) := X"0C0006BF";
ram_buffer(203) := X"00000000";
ram_buffer(204) := X"0C000190";
ram_buffer(205) := X"00000000";
ram_buffer(206) := X"8F848020";
ram_buffer(207) := X"0C0006BF";
ram_buffer(208) := X"00000000";
ram_buffer(209) := X"1000FFF5";
ram_buffer(210) := X"00000000";
ram_buffer(211) := X"0C0006C8";
ram_buffer(212) := X"00000000";
ram_buffer(213) := X"24060004";
ram_buffer(214) := X"27858020";
ram_buffer(215) := X"24040004";
ram_buffer(216) := X"0C00016A";
ram_buffer(217) := X"AF828020";
ram_buffer(218) := X"1000FFE3";
ram_buffer(219) := X"00000000";
ram_buffer(220) := X"3C02F000";
ram_buffer(221) := X"8C420004";
ram_buffer(222) := X"3C031000";
ram_buffer(223) := X"24631D5C";
ram_buffer(224) := X"00021080";
ram_buffer(225) := X"00431021";
ram_buffer(226) := X"8C420000";
ram_buffer(227) := X"24030002";
ram_buffer(228) := X"03E00008";
ram_buffer(229) := X"AC430000";
ram_buffer(230) := X"27BDFFE0";
ram_buffer(231) := X"AFBF001C";
ram_buffer(232) := X"AFB20018";
ram_buffer(233) := X"AFB10014";
ram_buffer(234) := X"AFB00010";
ram_buffer(235) := X"3C02F000";
ram_buffer(236) := X"8C420004";
ram_buffer(237) := X"00000000";
ram_buffer(238) := X"00028100";
ram_buffer(239) := X"02028021";
ram_buffer(240) := X"00108080";
ram_buffer(241) := X"26120004";
ram_buffer(242) := X"3C111000";
ram_buffer(243) := X"26311D68";
ram_buffer(244) := X"02308021";
ram_buffer(245) := X"8E020000";
ram_buffer(246) := X"00000000";
ram_buffer(247) := X"8C420004";
ram_buffer(248) := X"00000000";
ram_buffer(249) := X"2C430008";
ram_buffer(250) := X"1060000F";
ram_buffer(251) := X"00000000";
ram_buffer(252) := X"000210C0";
ram_buffer(253) := X"00521021";
ram_buffer(254) := X"02221021";
ram_buffer(255) := X"8C430000";
ram_buffer(256) := X"8C440004";
ram_buffer(257) := X"0060F809";
ram_buffer(258) := X"00000000";
ram_buffer(259) := X"8E020000";
ram_buffer(260) := X"00000000";
ram_buffer(261) := X"8C420004";
ram_buffer(262) := X"00000000";
ram_buffer(263) := X"2C430008";
ram_buffer(264) := X"1460FFF3";
ram_buffer(265) := X"00000000";
ram_buffer(266) := X"8FBF001C";
ram_buffer(267) := X"8FB20018";
ram_buffer(268) := X"8FB10014";
ram_buffer(269) := X"8FB00010";
ram_buffer(270) := X"03E00008";
ram_buffer(271) := X"27BD0020";
ram_buffer(272) := X"27BDFFE0";
ram_buffer(273) := X"AFBF001C";
ram_buffer(274) := X"AFB20018";
ram_buffer(275) := X"AFB10014";
ram_buffer(276) := X"AFB00010";
ram_buffer(277) := X"3C05F000";
ram_buffer(278) := X"8CA20004";
ram_buffer(279) := X"00000000";
ram_buffer(280) := X"00021240";
ram_buffer(281) := X"244301E8";
ram_buffer(282) := X"3C021000";
ram_buffer(283) := X"24421EA0";
ram_buffer(284) := X"00431021";
ram_buffer(285) := X"0040E825";
ram_buffer(286) := X"8CB00004";
ram_buffer(287) := X"8CA60004";
ram_buffer(288) := X"00000000";
ram_buffer(289) := X"00062100";
ram_buffer(290) := X"8CA50004";
ram_buffer(291) := X"00861021";
ram_buffer(292) := X"3C031000";
ram_buffer(293) := X"3C071000";
ram_buffer(294) := X"00021080";
ram_buffer(295) := X"24631D68";
ram_buffer(296) := X"24E71D5C";
ram_buffer(297) := X"00052880";
ram_buffer(298) := X"00624021";
ram_buffer(299) := X"00A72821";
ram_buffer(300) := X"24420004";
ram_buffer(301) := X"3C09F002";
ram_buffer(302) := X"00621021";
ram_buffer(303) := X"ACA90000";
ram_buffer(304) := X"25070044";
ram_buffer(305) := X"3C05F001";
ram_buffer(306) := X"AD050000";
ram_buffer(307) := X"10470004";
ram_buffer(308) := X"00402825";
ram_buffer(309) := X"24A50008";
ram_buffer(310) := X"14E5FFFE";
ram_buffer(311) := X"ACA0FFF8";
ram_buffer(312) := X"3C051000";
ram_buffer(313) := X"24A5180C";
ram_buffer(314) := X"AC450000";
ram_buffer(315) := X"AC400004";
ram_buffer(316) := X"00861021";
ram_buffer(317) := X"00021080";
ram_buffer(318) := X"00621821";
ram_buffer(319) := X"8C620000";
ram_buffer(320) := X"24030001";
ram_buffer(321) := X"AC430000";
ram_buffer(322) := X"1600000F";
ram_buffer(323) := X"2783800C";
ram_buffer(324) := X"278288B4";
ram_buffer(325) := X"10620008";
ram_buffer(326) := X"24660004";
ram_buffer(327) := X"00463023";
ram_buffer(328) := X"00063082";
ram_buffer(329) := X"24C60001";
ram_buffer(330) := X"00063080";
ram_buffer(331) := X"00002825";
ram_buffer(332) := X"0C000707";
ram_buffer(333) := X"2784800C";
ram_buffer(334) := X"0C00007C";
ram_buffer(335) := X"00000000";
ram_buffer(336) := X"1000FFFF";
ram_buffer(337) := X"00000000";
ram_buffer(338) := X"0C000180";
ram_buffer(339) := X"2404000C";
ram_buffer(340) := X"00101080";
ram_buffer(341) := X"3C101000";
ram_buffer(342) := X"26101D50";
ram_buffer(343) := X"02028021";
ram_buffer(344) := X"02008825";
ram_buffer(345) := X"2412FFFF";
ram_buffer(346) := X"24060004";
ram_buffer(347) := X"02002825";
ram_buffer(348) := X"0C00016A";
ram_buffer(349) := X"00002025";
ram_buffer(350) := X"8E220000";
ram_buffer(351) := X"00000000";
ram_buffer(352) := X"1052FFFA";
ram_buffer(353) := X"24060004";
ram_buffer(354) := X"0C000190";
ram_buffer(355) := X"00000000";
ram_buffer(356) := X"8E220000";
ram_buffer(357) := X"00000000";
ram_buffer(358) := X"0040F809";
ram_buffer(359) := X"00000000";
ram_buffer(360) := X"1000FFE7";
ram_buffer(361) := X"00000000";
ram_buffer(362) := X"10C00013";
ram_buffer(363) := X"00C51821";
ram_buffer(364) := X"2406FFF0";
ram_buffer(365) := X"00661024";
ram_buffer(366) := X"0043182B";
ram_buffer(367) := X"00031900";
ram_buffer(368) := X"24420010";
ram_buffer(369) := X"00A62824";
ram_buffer(370) := X"00431821";
ram_buffer(371) := X"40076000";
ram_buffer(372) := X"40806000";
ram_buffer(373) := X"10A30007";
ram_buffer(374) := X"2484FF00";
ram_buffer(375) := X"00A61024";
ram_buffer(376) := X"AC820000";
ram_buffer(377) := X"AC400000";
ram_buffer(378) := X"24A50010";
ram_buffer(379) := X"14A3FFFC";
ram_buffer(380) := X"00A61024";
ram_buffer(381) := X"40876000";
ram_buffer(382) := X"03E00008";
ram_buffer(383) := X"00000000";
ram_buffer(384) := X"40066000";
ram_buffer(385) := X"40806000";
ram_buffer(386) := X"00001025";
ram_buffer(387) := X"2483FF00";
ram_buffer(388) := X"24050200";
ram_buffer(389) := X"AC620000";
ram_buffer(390) := X"AC400000";
ram_buffer(391) := X"34440200";
ram_buffer(392) := X"AC640000";
ram_buffer(393) := X"AC800000";
ram_buffer(394) := X"24420010";
ram_buffer(395) := X"1445FFF9";
ram_buffer(396) := X"00000000";
ram_buffer(397) := X"40866000";
ram_buffer(398) := X"03E00008";
ram_buffer(399) := X"00000000";
ram_buffer(400) := X"40066000";
ram_buffer(401) := X"40806000";
ram_buffer(402) := X"00000000";
ram_buffer(403) := X"40076000";
ram_buffer(404) := X"40806000";
ram_buffer(405) := X"00001025";
ram_buffer(406) := X"2403FF0C";
ram_buffer(407) := X"24050200";
ram_buffer(408) := X"AC620000";
ram_buffer(409) := X"AC400000";
ram_buffer(410) := X"34440200";
ram_buffer(411) := X"AC640000";
ram_buffer(412) := X"AC800000";
ram_buffer(413) := X"24420010";
ram_buffer(414) := X"1445FFF9";
ram_buffer(415) := X"00000000";
ram_buffer(416) := X"40876000";
ram_buffer(417) := X"00000000";
ram_buffer(418) := X"40076000";
ram_buffer(419) := X"40806000";
ram_buffer(420) := X"00001025";
ram_buffer(421) := X"2403FF08";
ram_buffer(422) := X"24050200";
ram_buffer(423) := X"AC620000";
ram_buffer(424) := X"AC400000";
ram_buffer(425) := X"34440200";
ram_buffer(426) := X"AC640000";
ram_buffer(427) := X"AC800000";
ram_buffer(428) := X"24420010";
ram_buffer(429) := X"1445FFF9";
ram_buffer(430) := X"00000000";
ram_buffer(431) := X"40876000";
ram_buffer(432) := X"00000000";
ram_buffer(433) := X"40866000";
ram_buffer(434) := X"03E00008";
ram_buffer(435) := X"00000000";
ram_buffer(436) := X"27BDFFB8";
ram_buffer(437) := X"AFB60038";
ram_buffer(438) := X"AFB50034";
ram_buffer(439) := X"AFB40030";
ram_buffer(440) := X"AFB20028";
ram_buffer(441) := X"AFB10024";
ram_buffer(442) := X"AFB00020";
ram_buffer(443) := X"AFBF0044";
ram_buffer(444) := X"AFBE0040";
ram_buffer(445) := X"AFB7003C";
ram_buffer(446) := X"AFB3002C";
ram_buffer(447) := X"00809025";
ram_buffer(448) := X"00A08825";
ram_buffer(449) := X"00C08025";
ram_buffer(450) := X"00E0A025";
ram_buffer(451) := X"24150025";
ram_buffer(452) := X"24160030";
ram_buffer(453) := X"82050000";
ram_buffer(454) := X"00000000";
ram_buffer(455) := X"10A00009";
ram_buffer(456) := X"00000000";
ram_buffer(457) := X"10B50013";
ram_buffer(458) := X"02402025";
ram_buffer(459) := X"0220F809";
ram_buffer(460) := X"26100001";
ram_buffer(461) := X"82050000";
ram_buffer(462) := X"00000000";
ram_buffer(463) := X"14A0FFF9";
ram_buffer(464) := X"00000000";
ram_buffer(465) := X"8FBF0044";
ram_buffer(466) := X"8FBE0040";
ram_buffer(467) := X"8FB7003C";
ram_buffer(468) := X"8FB60038";
ram_buffer(469) := X"8FB50034";
ram_buffer(470) := X"8FB40030";
ram_buffer(471) := X"8FB3002C";
ram_buffer(472) := X"8FB20028";
ram_buffer(473) := X"8FB10024";
ram_buffer(474) := X"8FB00020";
ram_buffer(475) := X"03E00008";
ram_buffer(476) := X"27BD0048";
ram_buffer(477) := X"82040001";
ram_buffer(478) := X"00000000";
ram_buffer(479) := X"10960094";
ram_buffer(480) := X"24060001";
ram_buffer(481) := X"26100002";
ram_buffer(482) := X"00003025";
ram_buffer(483) := X"2482FFD0";
ram_buffer(484) := X"304200FF";
ram_buffer(485) := X"2C42000A";
ram_buffer(486) := X"14400073";
ram_buffer(487) := X"00001025";
ram_buffer(488) := X"24030063";
ram_buffer(489) := X"10830080";
ram_buffer(490) := X"28830064";
ram_buffer(491) := X"1460005F";
ram_buffer(492) := X"24030073";
ram_buffer(493) := X"108300C7";
ram_buffer(494) := X"28830074";
ram_buffer(495) := X"14600090";
ram_buffer(496) := X"24030075";
ram_buffer(497) := X"148300F0";
ram_buffer(498) := X"24030078";
ram_buffer(499) := X"8E840000";
ram_buffer(500) := X"00000000";
ram_buffer(501) := X"2C83000A";
ram_buffer(502) := X"146001A7";
ram_buffer(503) := X"26940004";
ram_buffer(504) := X"24030001";
ram_buffer(505) := X"00032880";
ram_buffer(506) := X"00A31821";
ram_buffer(507) := X"00031840";
ram_buffer(508) := X"14600002";
ram_buffer(509) := X"0083001B";
ram_buffer(510) := X"0007000D";
ram_buffer(511) := X"00002812";
ram_buffer(512) := X"2CA5000A";
ram_buffer(513) := X"10A0FFF8";
ram_buffer(514) := X"00032880";
ram_buffer(515) := X"1060001F";
ram_buffer(516) := X"27AB0010";
ram_buffer(517) := X"27A80010";
ram_buffer(518) := X"00005025";
ram_buffer(519) := X"240C000A";
ram_buffer(520) := X"15800002";
ram_buffer(521) := X"006C001B";
ram_buffer(522) := X"0007000D";
ram_buffer(523) := X"250B0001";
ram_buffer(524) := X"24050057";
ram_buffer(525) := X"00004812";
ram_buffer(526) := X"00000000";
ram_buffer(527) := X"00000000";
ram_buffer(528) := X"14600002";
ram_buffer(529) := X"0083001B";
ram_buffer(530) := X"0007000D";
ram_buffer(531) := X"00002010";
ram_buffer(532) := X"00003812";
ram_buffer(533) := X"15400003";
ram_buffer(534) := X"01201825";
ram_buffer(535) := X"18E0005F";
ram_buffer(536) := X"00000000";
ram_buffer(537) := X"28ED000A";
ram_buffer(538) := X"11A00003";
ram_buffer(539) := X"00A72821";
ram_buffer(540) := X"24050030";
ram_buffer(541) := X"00A72821";
ram_buffer(542) := X"254A0001";
ram_buffer(543) := X"11200003";
ram_buffer(544) := X"A1050000";
ram_buffer(545) := X"1000FFE6";
ram_buffer(546) := X"01604025";
ram_buffer(547) := X"14C0012D";
ram_buffer(548) := X"A1600000";
ram_buffer(549) := X"24170020";
ram_buffer(550) := X"83B30010";
ram_buffer(551) := X"00000000";
ram_buffer(552) := X"1260017F";
ram_buffer(553) := X"00000000";
ram_buffer(554) := X"10400015";
ram_buffer(555) := X"27A30011";
ram_buffer(556) := X"10000004";
ram_buffer(557) := X"24630001";
ram_buffer(558) := X"10A00011";
ram_buffer(559) := X"00A01025";
ram_buffer(560) := X"24630001";
ram_buffer(561) := X"8064FFFF";
ram_buffer(562) := X"00000000";
ram_buffer(563) := X"1480FFFA";
ram_buffer(564) := X"2445FFFF";
ram_buffer(565) := X"10A0000A";
ram_buffer(566) := X"245EFFFE";
ram_buffer(567) := X"02E02825";
ram_buffer(568) := X"02402025";
ram_buffer(569) := X"0220F809";
ram_buffer(570) := X"27DEFFFF";
ram_buffer(571) := X"27C20001";
ram_buffer(572) := X"1C40FFFB";
ram_buffer(573) := X"02E02825";
ram_buffer(574) := X"1260FF86";
ram_buffer(575) := X"00000000";
ram_buffer(576) := X"27B70011";
ram_buffer(577) := X"02602825";
ram_buffer(578) := X"02402025";
ram_buffer(579) := X"0220F809";
ram_buffer(580) := X"26F70001";
ram_buffer(581) := X"82F3FFFF";
ram_buffer(582) := X"00000000";
ram_buffer(583) := X"1660FFFA";
ram_buffer(584) := X"02602825";
ram_buffer(585) := X"1000FF7B";
ram_buffer(586) := X"00000000";
ram_buffer(587) := X"109500FE";
ram_buffer(588) := X"24030058";
ram_buffer(589) := X"10830096";
ram_buffer(590) := X"00000000";
ram_buffer(591) := X"1080FF81";
ram_buffer(592) := X"00000000";
ram_buffer(593) := X"1000FF73";
ram_buffer(594) := X"00000000";
ram_buffer(595) := X"2485FFD0";
ram_buffer(596) := X"00021880";
ram_buffer(597) := X"00621021";
ram_buffer(598) := X"26100001";
ram_buffer(599) := X"00021040";
ram_buffer(600) := X"8204FFFF";
ram_buffer(601) := X"00451021";
ram_buffer(602) := X"308300FF";
ram_buffer(603) := X"2465FFD0";
ram_buffer(604) := X"2467FF9F";
ram_buffer(605) := X"2CA5000A";
ram_buffer(606) := X"14A0FFF4";
ram_buffer(607) := X"2CE70006";
ram_buffer(608) := X"2463FFBF";
ram_buffer(609) := X"10E0000E";
ram_buffer(610) := X"2C630006";
ram_buffer(611) := X"2485FFA9";
ram_buffer(612) := X"28A3000B";
ram_buffer(613) := X"1460FFEF";
ram_buffer(614) := X"00021880";
ram_buffer(615) := X"24030063";
ram_buffer(616) := X"1483FF82";
ram_buffer(617) := X"28830064";
ram_buffer(618) := X"82850003";
ram_buffer(619) := X"02402025";
ram_buffer(620) := X"0220F809";
ram_buffer(621) := X"26940004";
ram_buffer(622) := X"1000FF56";
ram_buffer(623) := X"00000000";
ram_buffer(624) := X"1060FF78";
ram_buffer(625) := X"24030063";
ram_buffer(626) := X"1000FFF1";
ram_buffer(627) := X"2485FFC9";
ram_buffer(628) := X"82040002";
ram_buffer(629) := X"1000FF6D";
ram_buffer(630) := X"26100003";
ram_buffer(631) := X"152000D7";
ram_buffer(632) := X"01005825";
ram_buffer(633) := X"24E50030";
ram_buffer(634) := X"250B0001";
ram_buffer(635) := X"A1050000";
ram_buffer(636) := X"10C0FFA8";
ram_buffer(637) := X"A1600000";
ram_buffer(638) := X"1000FFA7";
ram_buffer(639) := X"24170030";
ram_buffer(640) := X"24030064";
ram_buffer(641) := X"1483FF43";
ram_buffer(642) := X"00000000";
ram_buffer(643) := X"8E850000";
ram_buffer(644) := X"00000000";
ram_buffer(645) := X"04A0010D";
ram_buffer(646) := X"26940004";
ram_buffer(647) := X"27A80010";
ram_buffer(648) := X"28A3000A";
ram_buffer(649) := X"14600110";
ram_buffer(650) := X"00A03825";
ram_buffer(651) := X"24030001";
ram_buffer(652) := X"00032080";
ram_buffer(653) := X"00831821";
ram_buffer(654) := X"00031840";
ram_buffer(655) := X"14600002";
ram_buffer(656) := X"00A3001B";
ram_buffer(657) := X"0007000D";
ram_buffer(658) := X"00002012";
ram_buffer(659) := X"2C84000A";
ram_buffer(660) := X"1080FFF8";
ram_buffer(661) := X"00032080";
ram_buffer(662) := X"106000BE";
ram_buffer(663) := X"01005825";
ram_buffer(664) := X"00005025";
ram_buffer(665) := X"240C000A";
ram_buffer(666) := X"15800002";
ram_buffer(667) := X"006C001B";
ram_buffer(668) := X"0007000D";
ram_buffer(669) := X"250B0001";
ram_buffer(670) := X"24040057";
ram_buffer(671) := X"00004812";
ram_buffer(672) := X"00000000";
ram_buffer(673) := X"00000000";
ram_buffer(674) := X"14600002";
ram_buffer(675) := X"00E3001B";
ram_buffer(676) := X"0007000D";
ram_buffer(677) := X"00003810";
ram_buffer(678) := X"00002812";
ram_buffer(679) := X"15400003";
ram_buffer(680) := X"01201825";
ram_buffer(681) := X"18A000D3";
ram_buffer(682) := X"00000000";
ram_buffer(683) := X"28AD000A";
ram_buffer(684) := X"11A00003";
ram_buffer(685) := X"00852021";
ram_buffer(686) := X"24040030";
ram_buffer(687) := X"00852021";
ram_buffer(688) := X"254A0001";
ram_buffer(689) := X"112000A3";
ram_buffer(690) := X"A1040000";
ram_buffer(691) := X"1000FFE6";
ram_buffer(692) := X"01604025";
ram_buffer(693) := X"8E970000";
ram_buffer(694) := X"26940004";
ram_buffer(695) := X"82E50000";
ram_buffer(696) := X"00000000";
ram_buffer(697) := X"10A000EA";
ram_buffer(698) := X"26F30001";
ram_buffer(699) := X"10400017";
ram_buffer(700) := X"02601825";
ram_buffer(701) := X"10000004";
ram_buffer(702) := X"24630001";
ram_buffer(703) := X"10C00013";
ram_buffer(704) := X"00C01025";
ram_buffer(705) := X"24630001";
ram_buffer(706) := X"8064FFFF";
ram_buffer(707) := X"00000000";
ram_buffer(708) := X"1480FFFA";
ram_buffer(709) := X"2446FFFF";
ram_buffer(710) := X"10C0000C";
ram_buffer(711) := X"245EFFFE";
ram_buffer(712) := X"24050020";
ram_buffer(713) := X"02402025";
ram_buffer(714) := X"0220F809";
ram_buffer(715) := X"27DEFFFF";
ram_buffer(716) := X"27C20001";
ram_buffer(717) := X"1C40FFFB";
ram_buffer(718) := X"24050020";
ram_buffer(719) := X"82E50000";
ram_buffer(720) := X"00000000";
ram_buffer(721) := X"10A0FEF3";
ram_buffer(722) := X"00000000";
ram_buffer(723) := X"02402025";
ram_buffer(724) := X"0220F809";
ram_buffer(725) := X"26730001";
ram_buffer(726) := X"8265FFFF";
ram_buffer(727) := X"00000000";
ram_buffer(728) := X"10A0FEEC";
ram_buffer(729) := X"02402025";
ram_buffer(730) := X"0220F809";
ram_buffer(731) := X"26730001";
ram_buffer(732) := X"8265FFFF";
ram_buffer(733) := X"00000000";
ram_buffer(734) := X"14A0FFF5";
ram_buffer(735) := X"02402025";
ram_buffer(736) := X"1000FEE4";
ram_buffer(737) := X"00000000";
ram_buffer(738) := X"1483FEE2";
ram_buffer(739) := X"00000000";
ram_buffer(740) := X"8E850000";
ram_buffer(741) := X"00000000";
ram_buffer(742) := X"2CA30010";
ram_buffer(743) := X"146000B4";
ram_buffer(744) := X"26940004";
ram_buffer(745) := X"24030001";
ram_buffer(746) := X"00031900";
ram_buffer(747) := X"14600002";
ram_buffer(748) := X"00A3001B";
ram_buffer(749) := X"0007000D";
ram_buffer(750) := X"00003812";
ram_buffer(751) := X"2CE70010";
ram_buffer(752) := X"10E0FFF9";
ram_buffer(753) := X"00000000";
ram_buffer(754) := X"106000A5";
ram_buffer(755) := X"00000000";
ram_buffer(756) := X"24070058";
ram_buffer(757) := X"27A90010";
ram_buffer(758) := X"10870019";
ram_buffer(759) := X"00005025";
ram_buffer(760) := X"14600002";
ram_buffer(761) := X"00A3001B";
ram_buffer(762) := X"0007000D";
ram_buffer(763) := X"00002810";
ram_buffer(764) := X"00004012";
ram_buffer(765) := X"15400003";
ram_buffer(766) := X"00031902";
ram_buffer(767) := X"19000082";
ram_buffer(768) := X"00000000";
ram_buffer(769) := X"290B000A";
ram_buffer(770) := X"25240001";
ram_buffer(771) := X"11600002";
ram_buffer(772) := X"24070057";
ram_buffer(773) := X"24070030";
ram_buffer(774) := X"00E83821";
ram_buffer(775) := X"254A0001";
ram_buffer(776) := X"10600019";
ram_buffer(777) := X"A1270000";
ram_buffer(778) := X"1000FFED";
ram_buffer(779) := X"00804825";
ram_buffer(780) := X"10600078";
ram_buffer(781) := X"25070030";
ram_buffer(782) := X"01202025";
ram_buffer(783) := X"00804825";
ram_buffer(784) := X"14600002";
ram_buffer(785) := X"00A3001B";
ram_buffer(786) := X"0007000D";
ram_buffer(787) := X"00002810";
ram_buffer(788) := X"00004012";
ram_buffer(789) := X"15400003";
ram_buffer(790) := X"00031902";
ram_buffer(791) := X"1900FFF4";
ram_buffer(792) := X"00000000";
ram_buffer(793) := X"290B000A";
ram_buffer(794) := X"25240001";
ram_buffer(795) := X"11600002";
ram_buffer(796) := X"24070037";
ram_buffer(797) := X"24070030";
ram_buffer(798) := X"00E83821";
ram_buffer(799) := X"254A0001";
ram_buffer(800) := X"1460FFEE";
ram_buffer(801) := X"A1270000";
ram_buffer(802) := X"14C00030";
ram_buffer(803) := X"A0800000";
ram_buffer(804) := X"24170020";
ram_buffer(805) := X"83B30010";
ram_buffer(806) := X"00000000";
ram_buffer(807) := X"12600084";
ram_buffer(808) := X"00000000";
ram_buffer(809) := X"10400015";
ram_buffer(810) := X"27A30011";
ram_buffer(811) := X"10000004";
ram_buffer(812) := X"24630001";
ram_buffer(813) := X"10A00011";
ram_buffer(814) := X"00A01025";
ram_buffer(815) := X"24630001";
ram_buffer(816) := X"8064FFFF";
ram_buffer(817) := X"00000000";
ram_buffer(818) := X"1480FFFA";
ram_buffer(819) := X"2445FFFF";
ram_buffer(820) := X"10A0000A";
ram_buffer(821) := X"245EFFFE";
ram_buffer(822) := X"02E02825";
ram_buffer(823) := X"02402025";
ram_buffer(824) := X"0220F809";
ram_buffer(825) := X"27DEFFFF";
ram_buffer(826) := X"27C20001";
ram_buffer(827) := X"1C40FFFB";
ram_buffer(828) := X"02E02825";
ram_buffer(829) := X"1260FE87";
ram_buffer(830) := X"00000000";
ram_buffer(831) := X"27B70011";
ram_buffer(832) := X"02602825";
ram_buffer(833) := X"02402025";
ram_buffer(834) := X"0220F809";
ram_buffer(835) := X"26F70001";
ram_buffer(836) := X"82F3FFFF";
ram_buffer(837) := X"00000000";
ram_buffer(838) := X"1660FFFA";
ram_buffer(839) := X"02602825";
ram_buffer(840) := X"1000FE7C";
ram_buffer(841) := X"00000000";
ram_buffer(842) := X"24050025";
ram_buffer(843) := X"0220F809";
ram_buffer(844) := X"02402025";
ram_buffer(845) := X"1000FE77";
ram_buffer(846) := X"00000000";
ram_buffer(847) := X"1000FEB8";
ram_buffer(848) := X"01604025";
ram_buffer(849) := X"1000FED4";
ram_buffer(850) := X"24170030";
ram_buffer(851) := X"1000FFD1";
ram_buffer(852) := X"24170030";
ram_buffer(853) := X"10C00039";
ram_buffer(854) := X"A1600000";
ram_buffer(855) := X"24170030";
ram_buffer(856) := X"83B30010";
ram_buffer(857) := X"00000000";
ram_buffer(858) := X"12600045";
ram_buffer(859) := X"00000000";
ram_buffer(860) := X"10400015";
ram_buffer(861) := X"27A30011";
ram_buffer(862) := X"10000004";
ram_buffer(863) := X"24630001";
ram_buffer(864) := X"10A00011";
ram_buffer(865) := X"00A01025";
ram_buffer(866) := X"24630001";
ram_buffer(867) := X"8064FFFF";
ram_buffer(868) := X"00000000";
ram_buffer(869) := X"1480FFFA";
ram_buffer(870) := X"2445FFFF";
ram_buffer(871) := X"10A0000A";
ram_buffer(872) := X"245EFFFE";
ram_buffer(873) := X"02E02825";
ram_buffer(874) := X"02402025";
ram_buffer(875) := X"0220F809";
ram_buffer(876) := X"27DEFFFF";
ram_buffer(877) := X"27C20001";
ram_buffer(878) := X"1C40FFFB";
ram_buffer(879) := X"02E02825";
ram_buffer(880) := X"1260FE54";
ram_buffer(881) := X"00000000";
ram_buffer(882) := X"27B70011";
ram_buffer(883) := X"02602825";
ram_buffer(884) := X"02402025";
ram_buffer(885) := X"0220F809";
ram_buffer(886) := X"26F70001";
ram_buffer(887) := X"82F3FFFF";
ram_buffer(888) := X"00000000";
ram_buffer(889) := X"1660FFFA";
ram_buffer(890) := X"02602825";
ram_buffer(891) := X"1000FE49";
ram_buffer(892) := X"00000000";
ram_buffer(893) := X"1120000D";
ram_buffer(894) := X"24A40030";
ram_buffer(895) := X"01005825";
ram_buffer(896) := X"1000FF19";
ram_buffer(897) := X"01604025";
ram_buffer(898) := X"1460000E";
ram_buffer(899) := X"01202025";
ram_buffer(900) := X"25070030";
ram_buffer(901) := X"25240001";
ram_buffer(902) := X"A1270000";
ram_buffer(903) := X"10C0FF9C";
ram_buffer(904) := X"A0800000";
ram_buffer(905) := X"1000FF9B";
ram_buffer(906) := X"24170030";
ram_buffer(907) := X"250B0001";
ram_buffer(908) := X"A1040000";
ram_buffer(909) := X"14C0FFC9";
ram_buffer(910) := X"A1600000";
ram_buffer(911) := X"1000FFC8";
ram_buffer(912) := X"24170020";
ram_buffer(913) := X"1000FF66";
ram_buffer(914) := X"00804825";
ram_buffer(915) := X"2403002D";
ram_buffer(916) := X"00052823";
ram_buffer(917) := X"A3A30010";
ram_buffer(918) := X"1000FEF1";
ram_buffer(919) := X"27A80011";
ram_buffer(920) := X"1000FF89";
ram_buffer(921) := X"27A40010";
ram_buffer(922) := X"1000FEFD";
ram_buffer(923) := X"24030001";
ram_buffer(924) := X"1000FF57";
ram_buffer(925) := X"24030001";
ram_buffer(926) := X"1000FE66";
ram_buffer(927) := X"24030001";
ram_buffer(928) := X"1040FE24";
ram_buffer(929) := X"245EFFFF";
ram_buffer(930) := X"1000FFC7";
ram_buffer(931) := X"02E02825";
ram_buffer(932) := X"1040FE20";
ram_buffer(933) := X"245EFFFF";
ram_buffer(934) := X"1000FF22";
ram_buffer(935) := X"24050020";
ram_buffer(936) := X"1040FE1C";
ram_buffer(937) := X"245EFFFF";
ram_buffer(938) := X"1000FE8D";
ram_buffer(939) := X"02E02825";
ram_buffer(940) := X"1040FE18";
ram_buffer(941) := X"245EFFFF";
ram_buffer(942) := X"1000FF88";
ram_buffer(943) := X"02E02825";
ram_buffer(944) := X"AF858010";
ram_buffer(945) := X"03E00008";
ram_buffer(946) := X"AF84800C";
ram_buffer(947) := X"27BDFFE0";
ram_buffer(948) := X"27A20024";
ram_buffer(949) := X"AFA50024";
ram_buffer(950) := X"AFA60028";
ram_buffer(951) := X"8F858010";
ram_buffer(952) := X"00803025";
ram_buffer(953) := X"8F84800C";
ram_buffer(954) := X"AFA7002C";
ram_buffer(955) := X"00403825";
ram_buffer(956) := X"AFBF001C";
ram_buffer(957) := X"0C0001B4";
ram_buffer(958) := X"AFA20010";
ram_buffer(959) := X"8FBF001C";
ram_buffer(960) := X"00000000";
ram_buffer(961) := X"03E00008";
ram_buffer(962) := X"27BD0020";
ram_buffer(963) := X"27BDFFC0";
ram_buffer(964) := X"AFB50034";
ram_buffer(965) := X"27B50048";
ram_buffer(966) := X"AFB3002C";
ram_buffer(967) := X"AFB20028";
ram_buffer(968) := X"AFB10024";
ram_buffer(969) := X"AFBF003C";
ram_buffer(970) := X"AFB60038";
ram_buffer(971) := X"AFB40030";
ram_buffer(972) := X"AFB00020";
ram_buffer(973) := X"00801825";
ram_buffer(974) := X"00A08825";
ram_buffer(975) := X"AFA60048";
ram_buffer(976) := X"AFA7004C";
ram_buffer(977) := X"AFB5001C";
ram_buffer(978) := X"24120025";
ram_buffer(979) := X"24130030";
ram_buffer(980) := X"82220000";
ram_buffer(981) := X"00000000";
ram_buffer(982) := X"10400009";
ram_buffer(983) := X"00000000";
ram_buffer(984) := X"10520012";
ram_buffer(985) := X"00000000";
ram_buffer(986) := X"A0620000";
ram_buffer(987) := X"26310001";
ram_buffer(988) := X"82220000";
ram_buffer(989) := X"00000000";
ram_buffer(990) := X"1440FFF9";
ram_buffer(991) := X"24630001";
ram_buffer(992) := X"A0600000";
ram_buffer(993) := X"8FBF003C";
ram_buffer(994) := X"8FB60038";
ram_buffer(995) := X"8FB50034";
ram_buffer(996) := X"8FB40030";
ram_buffer(997) := X"8FB3002C";
ram_buffer(998) := X"8FB20028";
ram_buffer(999) := X"8FB10024";
ram_buffer(1000) := X"8FB00020";
ram_buffer(1001) := X"03E00008";
ram_buffer(1002) := X"27BD0040";
ram_buffer(1003) := X"82240001";
ram_buffer(1004) := X"00000000";
ram_buffer(1005) := X"10930090";
ram_buffer(1006) := X"24070001";
ram_buffer(1007) := X"26310002";
ram_buffer(1008) := X"00003825";
ram_buffer(1009) := X"2482FFD0";
ram_buffer(1010) := X"304200FF";
ram_buffer(1011) := X"2C42000A";
ram_buffer(1012) := X"14400043";
ram_buffer(1013) := X"00008025";
ram_buffer(1014) := X"24020063";
ram_buffer(1015) := X"10820050";
ram_buffer(1016) := X"28820064";
ram_buffer(1017) := X"1440007C";
ram_buffer(1018) := X"24020073";
ram_buffer(1019) := X"108200C3";
ram_buffer(1020) := X"28820074";
ram_buffer(1021) := X"1440008C";
ram_buffer(1022) := X"24020075";
ram_buffer(1023) := X"148200ED";
ram_buffer(1024) := X"24020078";
ram_buffer(1025) := X"8EA40000";
ram_buffer(1026) := X"00000000";
ram_buffer(1027) := X"2C82000A";
ram_buffer(1028) := X"144001AA";
ram_buffer(1029) := X"26B50004";
ram_buffer(1030) := X"24020001";
ram_buffer(1031) := X"00022880";
ram_buffer(1032) := X"00A21021";
ram_buffer(1033) := X"00021040";
ram_buffer(1034) := X"14400002";
ram_buffer(1035) := X"0082001B";
ram_buffer(1036) := X"0007000D";
ram_buffer(1037) := X"00002812";
ram_buffer(1038) := X"2CA5000A";
ram_buffer(1039) := X"10A0FFF8";
ram_buffer(1040) := X"00022880";
ram_buffer(1041) := X"1040003B";
ram_buffer(1042) := X"27AB0010";
ram_buffer(1043) := X"27A80010";
ram_buffer(1044) := X"00005025";
ram_buffer(1045) := X"240C000A";
ram_buffer(1046) := X"15800002";
ram_buffer(1047) := X"004C001B";
ram_buffer(1048) := X"0007000D";
ram_buffer(1049) := X"250B0001";
ram_buffer(1050) := X"24050057";
ram_buffer(1051) := X"00004812";
ram_buffer(1052) := X"00000000";
ram_buffer(1053) := X"00000000";
ram_buffer(1054) := X"14400002";
ram_buffer(1055) := X"0082001B";
ram_buffer(1056) := X"0007000D";
ram_buffer(1057) := X"00002010";
ram_buffer(1058) := X"00003012";
ram_buffer(1059) := X"15400003";
ram_buffer(1060) := X"01201025";
ram_buffer(1061) := X"18C0005B";
ram_buffer(1062) := X"00000000";
ram_buffer(1063) := X"28CD000A";
ram_buffer(1064) := X"11A00003";
ram_buffer(1065) := X"00A62821";
ram_buffer(1066) := X"24050030";
ram_buffer(1067) := X"00A62821";
ram_buffer(1068) := X"254A0001";
ram_buffer(1069) := X"1120001F";
ram_buffer(1070) := X"A1050000";
ram_buffer(1071) := X"1000FFE6";
ram_buffer(1072) := X"01604025";
ram_buffer(1073) := X"2485FFD0";
ram_buffer(1074) := X"00101080";
ram_buffer(1075) := X"00508021";
ram_buffer(1076) := X"26310001";
ram_buffer(1077) := X"00108040";
ram_buffer(1078) := X"8224FFFF";
ram_buffer(1079) := X"02058021";
ram_buffer(1080) := X"308200FF";
ram_buffer(1081) := X"2445FFD0";
ram_buffer(1082) := X"2446FF9F";
ram_buffer(1083) := X"2CA5000A";
ram_buffer(1084) := X"14A0FFF4";
ram_buffer(1085) := X"2CC60006";
ram_buffer(1086) := X"2442FFBF";
ram_buffer(1087) := X"10C00032";
ram_buffer(1088) := X"2C420006";
ram_buffer(1089) := X"2485FFA9";
ram_buffer(1090) := X"28A2000B";
ram_buffer(1091) := X"1440FFEF";
ram_buffer(1092) := X"00101080";
ram_buffer(1093) := X"24020063";
ram_buffer(1094) := X"1482FFB2";
ram_buffer(1095) := X"28820064";
ram_buffer(1096) := X"8EA20000";
ram_buffer(1097) := X"24630001";
ram_buffer(1098) := X"A062FFFF";
ram_buffer(1099) := X"1000FF88";
ram_buffer(1100) := X"26B50004";
ram_buffer(1101) := X"14E00109";
ram_buffer(1102) := X"A1600000";
ram_buffer(1103) := X"24050020";
ram_buffer(1104) := X"83B40010";
ram_buffer(1105) := X"00000000";
ram_buffer(1106) := X"1280014A";
ram_buffer(1107) := X"00000000";
ram_buffer(1108) := X"12000013";
ram_buffer(1109) := X"27A20011";
ram_buffer(1110) := X"10000004";
ram_buffer(1111) := X"24420001";
ram_buffer(1112) := X"10C0000F";
ram_buffer(1113) := X"00C08025";
ram_buffer(1114) := X"24420001";
ram_buffer(1115) := X"8044FFFF";
ram_buffer(1116) := X"00000000";
ram_buffer(1117) := X"1480FFFA";
ram_buffer(1118) := X"2606FFFF";
ram_buffer(1119) := X"10C00008";
ram_buffer(1120) := X"2610FFFE";
ram_buffer(1121) := X"06000145";
ram_buffer(1122) := X"00000000";
ram_buffer(1123) := X"26100001";
ram_buffer(1124) := X"00602025";
ram_buffer(1125) := X"0C000707";
ram_buffer(1126) := X"02003025";
ram_buffer(1127) := X"00501821";
ram_buffer(1128) := X"27A20011";
ram_buffer(1129) := X"24630001";
ram_buffer(1130) := X"24420001";
ram_buffer(1131) := X"A074FFFF";
ram_buffer(1132) := X"8054FFFF";
ram_buffer(1133) := X"00000000";
ram_buffer(1134) := X"1680FFFB";
ram_buffer(1135) := X"24630001";
ram_buffer(1136) := X"1000FF63";
ram_buffer(1137) := X"2463FFFF";
ram_buffer(1138) := X"1040FF84";
ram_buffer(1139) := X"24020063";
ram_buffer(1140) := X"1000FFCD";
ram_buffer(1141) := X"2485FFC9";
ram_buffer(1142) := X"109200DB";
ram_buffer(1143) := X"24020058";
ram_buffer(1144) := X"10820076";
ram_buffer(1145) := X"00000000";
ram_buffer(1146) := X"1080FF65";
ram_buffer(1147) := X"00000000";
ram_buffer(1148) := X"1000FF57";
ram_buffer(1149) := X"00000000";
ram_buffer(1150) := X"82240002";
ram_buffer(1151) := X"1000FF71";
ram_buffer(1152) := X"26310003";
ram_buffer(1153) := X"152000D3";
ram_buffer(1154) := X"01005825";
ram_buffer(1155) := X"24C50030";
ram_buffer(1156) := X"250B0001";
ram_buffer(1157) := X"A1050000";
ram_buffer(1158) := X"10E0FFC8";
ram_buffer(1159) := X"A1600000";
ram_buffer(1160) := X"1000FFC7";
ram_buffer(1161) := X"24050030";
ram_buffer(1162) := X"24020064";
ram_buffer(1163) := X"1482FF48";
ram_buffer(1164) := X"00000000";
ram_buffer(1165) := X"8EA50000";
ram_buffer(1166) := X"00000000";
ram_buffer(1167) := X"04A00106";
ram_buffer(1168) := X"26B50004";
ram_buffer(1169) := X"27A80010";
ram_buffer(1170) := X"28A2000A";
ram_buffer(1171) := X"14400117";
ram_buffer(1172) := X"00A03025";
ram_buffer(1173) := X"24020001";
ram_buffer(1174) := X"00022080";
ram_buffer(1175) := X"00821021";
ram_buffer(1176) := X"00021040";
ram_buffer(1177) := X"14400002";
ram_buffer(1178) := X"00A2001B";
ram_buffer(1179) := X"0007000D";
ram_buffer(1180) := X"00002012";
ram_buffer(1181) := X"2C84000A";
ram_buffer(1182) := X"1080FFF8";
ram_buffer(1183) := X"00022080";
ram_buffer(1184) := X"104000BA";
ram_buffer(1185) := X"01005825";
ram_buffer(1186) := X"00005025";
ram_buffer(1187) := X"240C000A";
ram_buffer(1188) := X"15800002";
ram_buffer(1189) := X"004C001B";
ram_buffer(1190) := X"0007000D";
ram_buffer(1191) := X"250B0001";
ram_buffer(1192) := X"24040057";
ram_buffer(1193) := X"00004812";
ram_buffer(1194) := X"00000000";
ram_buffer(1195) := X"00000000";
ram_buffer(1196) := X"14400002";
ram_buffer(1197) := X"00C2001B";
ram_buffer(1198) := X"0007000D";
ram_buffer(1199) := X"00003010";
ram_buffer(1200) := X"00002812";
ram_buffer(1201) := X"15400003";
ram_buffer(1202) := X"01201025";
ram_buffer(1203) := X"18A000CC";
ram_buffer(1204) := X"00000000";
ram_buffer(1205) := X"28AD000A";
ram_buffer(1206) := X"11A00003";
ram_buffer(1207) := X"00852021";
ram_buffer(1208) := X"24040030";
ram_buffer(1209) := X"00852021";
ram_buffer(1210) := X"254A0001";
ram_buffer(1211) := X"1120009F";
ram_buffer(1212) := X"A1040000";
ram_buffer(1213) := X"1000FFE6";
ram_buffer(1214) := X"01604025";
ram_buffer(1215) := X"8EB60000";
ram_buffer(1216) := X"26B50004";
ram_buffer(1217) := X"82C20000";
ram_buffer(1218) := X"00000000";
ram_buffer(1219) := X"104000ED";
ram_buffer(1220) := X"26D40001";
ram_buffer(1221) := X"12000018";
ram_buffer(1222) := X"02802025";
ram_buffer(1223) := X"10000004";
ram_buffer(1224) := X"24840001";
ram_buffer(1225) := X"10C00014";
ram_buffer(1226) := X"00C08025";
ram_buffer(1227) := X"24840001";
ram_buffer(1228) := X"8085FFFF";
ram_buffer(1229) := X"00000000";
ram_buffer(1230) := X"14A0FFFA";
ram_buffer(1231) := X"2606FFFF";
ram_buffer(1232) := X"10C0000D";
ram_buffer(1233) := X"2610FFFE";
ram_buffer(1234) := X"060000D0";
ram_buffer(1235) := X"00000000";
ram_buffer(1236) := X"26100001";
ram_buffer(1237) := X"00602025";
ram_buffer(1238) := X"02003025";
ram_buffer(1239) := X"0C000707";
ram_buffer(1240) := X"24050020";
ram_buffer(1241) := X"00401825";
ram_buffer(1242) := X"82C20000";
ram_buffer(1243) := X"00000000";
ram_buffer(1244) := X"1040FEF7";
ram_buffer(1245) := X"00701821";
ram_buffer(1246) := X"24630001";
ram_buffer(1247) := X"A062FFFF";
ram_buffer(1248) := X"26940001";
ram_buffer(1249) := X"8282FFFF";
ram_buffer(1250) := X"00000000";
ram_buffer(1251) := X"1040FEF0";
ram_buffer(1252) := X"26940001";
ram_buffer(1253) := X"24630001";
ram_buffer(1254) := X"A062FFFF";
ram_buffer(1255) := X"8282FFFF";
ram_buffer(1256) := X"00000000";
ram_buffer(1257) := X"1440FFF5";
ram_buffer(1258) := X"24630001";
ram_buffer(1259) := X"1000FEE8";
ram_buffer(1260) := X"2463FFFF";
ram_buffer(1261) := X"1482FEE6";
ram_buffer(1262) := X"00000000";
ram_buffer(1263) := X"8EA50000";
ram_buffer(1264) := X"00000000";
ram_buffer(1265) := X"2CA20010";
ram_buffer(1266) := X"144000BA";
ram_buffer(1267) := X"26B50004";
ram_buffer(1268) := X"24020001";
ram_buffer(1269) := X"00021100";
ram_buffer(1270) := X"14400002";
ram_buffer(1271) := X"00A2001B";
ram_buffer(1272) := X"0007000D";
ram_buffer(1273) := X"00003012";
ram_buffer(1274) := X"2CC60010";
ram_buffer(1275) := X"10C0FFF9";
ram_buffer(1276) := X"00000000";
ram_buffer(1277) := X"1040009D";
ram_buffer(1278) := X"00000000";
ram_buffer(1279) := X"24060058";
ram_buffer(1280) := X"27A90010";
ram_buffer(1281) := X"10860019";
ram_buffer(1282) := X"00005025";
ram_buffer(1283) := X"14400002";
ram_buffer(1284) := X"00A2001B";
ram_buffer(1285) := X"0007000D";
ram_buffer(1286) := X"00002810";
ram_buffer(1287) := X"00004012";
ram_buffer(1288) := X"15400003";
ram_buffer(1289) := X"00021102";
ram_buffer(1290) := X"19000080";
ram_buffer(1291) := X"00000000";
ram_buffer(1292) := X"290B000A";
ram_buffer(1293) := X"25240001";
ram_buffer(1294) := X"11600002";
ram_buffer(1295) := X"24060057";
ram_buffer(1296) := X"24060030";
ram_buffer(1297) := X"00C83021";
ram_buffer(1298) := X"254A0001";
ram_buffer(1299) := X"10400019";
ram_buffer(1300) := X"A1260000";
ram_buffer(1301) := X"1000FFED";
ram_buffer(1302) := X"00804825";
ram_buffer(1303) := X"10400076";
ram_buffer(1304) := X"25060030";
ram_buffer(1305) := X"01202025";
ram_buffer(1306) := X"00804825";
ram_buffer(1307) := X"14400002";
ram_buffer(1308) := X"00A2001B";
ram_buffer(1309) := X"0007000D";
ram_buffer(1310) := X"00002810";
ram_buffer(1311) := X"00004012";
ram_buffer(1312) := X"15400003";
ram_buffer(1313) := X"00021102";
ram_buffer(1314) := X"1900FFF4";
ram_buffer(1315) := X"00000000";
ram_buffer(1316) := X"290B000A";
ram_buffer(1317) := X"25240001";
ram_buffer(1318) := X"11600002";
ram_buffer(1319) := X"24060037";
ram_buffer(1320) := X"24060030";
ram_buffer(1321) := X"00C83021";
ram_buffer(1322) := X"254A0001";
ram_buffer(1323) := X"1440FFEE";
ram_buffer(1324) := X"A1260000";
ram_buffer(1325) := X"14E0002B";
ram_buffer(1326) := X"A0800000";
ram_buffer(1327) := X"24050020";
ram_buffer(1328) := X"83B40010";
ram_buffer(1329) := X"00000000";
ram_buffer(1330) := X"1280006A";
ram_buffer(1331) := X"00000000";
ram_buffer(1332) := X"12000013";
ram_buffer(1333) := X"27A20011";
ram_buffer(1334) := X"10000004";
ram_buffer(1335) := X"24420001";
ram_buffer(1336) := X"10C0000F";
ram_buffer(1337) := X"00C08025";
ram_buffer(1338) := X"24420001";
ram_buffer(1339) := X"8044FFFF";
ram_buffer(1340) := X"00000000";
ram_buffer(1341) := X"1480FFFA";
ram_buffer(1342) := X"2606FFFF";
ram_buffer(1343) := X"10C00008";
ram_buffer(1344) := X"2610FFFE";
ram_buffer(1345) := X"06000063";
ram_buffer(1346) := X"00000000";
ram_buffer(1347) := X"26100001";
ram_buffer(1348) := X"00602025";
ram_buffer(1349) := X"0C000707";
ram_buffer(1350) := X"02003025";
ram_buffer(1351) := X"00501821";
ram_buffer(1352) := X"27A20011";
ram_buffer(1353) := X"24630001";
ram_buffer(1354) := X"24420001";
ram_buffer(1355) := X"A074FFFF";
ram_buffer(1356) := X"8054FFFF";
ram_buffer(1357) := X"00000000";
ram_buffer(1358) := X"1680FFFB";
ram_buffer(1359) := X"24630001";
ram_buffer(1360) := X"1000FE83";
ram_buffer(1361) := X"2463FFFF";
ram_buffer(1362) := X"A0720000";
ram_buffer(1363) := X"1000FE80";
ram_buffer(1364) := X"24630001";
ram_buffer(1365) := X"1000FEC0";
ram_buffer(1366) := X"01604025";
ram_buffer(1367) := X"1000FEF8";
ram_buffer(1368) := X"24050030";
ram_buffer(1369) := X"1000FFD6";
ram_buffer(1370) := X"24050030";
ram_buffer(1371) := X"10E0002D";
ram_buffer(1372) := X"A1600000";
ram_buffer(1373) := X"24050030";
ram_buffer(1374) := X"83B40010";
ram_buffer(1375) := X"00000000";
ram_buffer(1376) := X"1280003C";
ram_buffer(1377) := X"00000000";
ram_buffer(1378) := X"12000013";
ram_buffer(1379) := X"27A20011";
ram_buffer(1380) := X"10000004";
ram_buffer(1381) := X"24420001";
ram_buffer(1382) := X"10C0000F";
ram_buffer(1383) := X"00C08025";
ram_buffer(1384) := X"24420001";
ram_buffer(1385) := X"8044FFFF";
ram_buffer(1386) := X"00000000";
ram_buffer(1387) := X"1480FFFA";
ram_buffer(1388) := X"2606FFFF";
ram_buffer(1389) := X"10C00008";
ram_buffer(1390) := X"2610FFFE";
ram_buffer(1391) := X"06000039";
ram_buffer(1392) := X"00000000";
ram_buffer(1393) := X"26100001";
ram_buffer(1394) := X"00602025";
ram_buffer(1395) := X"0C000707";
ram_buffer(1396) := X"02003025";
ram_buffer(1397) := X"00501821";
ram_buffer(1398) := X"27A20011";
ram_buffer(1399) := X"24630001";
ram_buffer(1400) := X"24420001";
ram_buffer(1401) := X"A074FFFF";
ram_buffer(1402) := X"8054FFFF";
ram_buffer(1403) := X"00000000";
ram_buffer(1404) := X"1680FFFB";
ram_buffer(1405) := X"24630001";
ram_buffer(1406) := X"1000FE55";
ram_buffer(1407) := X"2463FFFF";
ram_buffer(1408) := X"11200004";
ram_buffer(1409) := X"24A40030";
ram_buffer(1410) := X"01005825";
ram_buffer(1411) := X"1000FF20";
ram_buffer(1412) := X"01604025";
ram_buffer(1413) := X"250B0001";
ram_buffer(1414) := X"A1040000";
ram_buffer(1415) := X"14E0FFD5";
ram_buffer(1416) := X"A1600000";
ram_buffer(1417) := X"1000FFD4";
ram_buffer(1418) := X"24050020";
ram_buffer(1419) := X"14400008";
ram_buffer(1420) := X"01202025";
ram_buffer(1421) := X"25060030";
ram_buffer(1422) := X"25240001";
ram_buffer(1423) := X"A1260000";
ram_buffer(1424) := X"10E0FF9E";
ram_buffer(1425) := X"A0800000";
ram_buffer(1426) := X"1000FF9D";
ram_buffer(1427) := X"24050030";
ram_buffer(1428) := X"1000FF6E";
ram_buffer(1429) := X"00804825";
ram_buffer(1430) := X"2402002D";
ram_buffer(1431) := X"00052823";
ram_buffer(1432) := X"A3A20010";
ram_buffer(1433) := X"1000FEF8";
ram_buffer(1434) := X"27A80011";
ram_buffer(1435) := X"1000FF91";
ram_buffer(1436) := X"27A40010";
ram_buffer(1437) := X"1200FE36";
ram_buffer(1438) := X"00602025";
ram_buffer(1439) := X"0C000707";
ram_buffer(1440) := X"02003025";
ram_buffer(1441) := X"1000FE32";
ram_buffer(1442) := X"00501821";
ram_buffer(1443) := X"1000FF30";
ram_buffer(1444) := X"00008025";
ram_buffer(1445) := X"1000FF9D";
ram_buffer(1446) := X"00008025";
ram_buffer(1447) := X"1000FEBB";
ram_buffer(1448) := X"00008025";
ram_buffer(1449) := X"1000FFC7";
ram_buffer(1450) := X"00008025";
ram_buffer(1451) := X"1000FEF6";
ram_buffer(1452) := X"24020001";
ram_buffer(1453) := X"1000FF51";
ram_buffer(1454) := X"24020001";
ram_buffer(1455) := X"1000FE63";
ram_buffer(1456) := X"24020001";
ram_buffer(1457) := X"1200FE22";
ram_buffer(1458) := X"2610FFFF";
ram_buffer(1459) := X"1000FF1E";
ram_buffer(1460) := X"00000000";
ram_buffer(1461) := X"03E00008";
ram_buffer(1462) := X"00000000";
ram_buffer(1463) := X"27BDFFE0";
ram_buffer(1464) := X"AFBF001C";
ram_buffer(1465) := X"AFB10018";
ram_buffer(1466) := X"AFB00014";
ram_buffer(1467) := X"3C111000";
ram_buffer(1468) := X"8E2226A0";
ram_buffer(1469) := X"00000000";
ram_buffer(1470) := X"8C420004";
ram_buffer(1471) := X"00000000";
ram_buffer(1472) := X"2C430008";
ram_buffer(1473) := X"1060000F";
ram_buffer(1474) := X"3C101000";
ram_buffer(1475) := X"261026A4";
ram_buffer(1476) := X"000210C0";
ram_buffer(1477) := X"02021021";
ram_buffer(1478) := X"8C430000";
ram_buffer(1479) := X"8C440004";
ram_buffer(1480) := X"0060F809";
ram_buffer(1481) := X"00000000";
ram_buffer(1482) := X"8E2226A0";
ram_buffer(1483) := X"00000000";
ram_buffer(1484) := X"8C420004";
ram_buffer(1485) := X"00000000";
ram_buffer(1486) := X"2C430008";
ram_buffer(1487) := X"1460FFF4";
ram_buffer(1488) := X"00000000";
ram_buffer(1489) := X"8FBF001C";
ram_buffer(1490) := X"8FB10018";
ram_buffer(1491) := X"8FB00014";
ram_buffer(1492) := X"03E00008";
ram_buffer(1493) := X"27BD0020";
ram_buffer(1494) := X"8F82802C";
ram_buffer(1495) := X"00000000";
ram_buffer(1496) := X"8C430004";
ram_buffer(1497) := X"8F82801C";
ram_buffer(1498) := X"8F848018";
ram_buffer(1499) := X"24420001";
ram_buffer(1500) := X"304201FF";
ram_buffer(1501) := X"10440008";
ram_buffer(1502) := X"00000000";
ram_buffer(1503) := X"8F84801C";
ram_buffer(1504) := X"3C051000";
ram_buffer(1505) := X"24A524A0";
ram_buffer(1506) := X"306300FF";
ram_buffer(1507) := X"00852021";
ram_buffer(1508) := X"A0830000";
ram_buffer(1509) := X"AF82801C";
ram_buffer(1510) := X"03E00008";
ram_buffer(1511) := X"00000000";
ram_buffer(1512) := X"8F828028";
ram_buffer(1513) := X"24030003";
ram_buffer(1514) := X"AC430000";
ram_buffer(1515) := X"8F998004";
ram_buffer(1516) := X"00000000";
ram_buffer(1517) := X"03200008";
ram_buffer(1518) := X"00000000";
ram_buffer(1519) := X"8F83802C";
ram_buffer(1520) := X"00000000";
ram_buffer(1521) := X"8C620000";
ram_buffer(1522) := X"00000000";
ram_buffer(1523) := X"30420002";
ram_buffer(1524) := X"1040FFFC";
ram_buffer(1525) := X"00000000";
ram_buffer(1526) := X"AC650008";
ram_buffer(1527) := X"03E00008";
ram_buffer(1528) := X"00000000";
ram_buffer(1529) := X"8F828024";
ram_buffer(1530) := X"24030007";
ram_buffer(1531) := X"AC430000";
ram_buffer(1532) := X"8F828014";
ram_buffer(1533) := X"24060004";
ram_buffer(1534) := X"24420001";
ram_buffer(1535) := X"27858014";
ram_buffer(1536) := X"24040004";
ram_buffer(1537) := X"0800016A";
ram_buffer(1538) := X"AF828014";
ram_buffer(1539) := X"3C02F000";
ram_buffer(1540) := X"8C420004";
ram_buffer(1541) := X"3C031000";
ram_buffer(1542) := X"24631D5C";
ram_buffer(1543) := X"00021080";
ram_buffer(1544) := X"00431021";
ram_buffer(1545) := X"8C420000";
ram_buffer(1546) := X"24030002";
ram_buffer(1547) := X"AC430000";
ram_buffer(1548) := X"8F998008";
ram_buffer(1549) := X"00000000";
ram_buffer(1550) := X"03200008";
ram_buffer(1551) := X"00000000";
ram_buffer(1552) := X"3C022000";
ram_buffer(1553) := X"AF828030";
ram_buffer(1554) := X"3C022002";
ram_buffer(1555) := X"AF828024";
ram_buffer(1556) := X"3C051000";
ram_buffer(1557) := X"3C022004";
ram_buffer(1558) := X"27BDFFE8";
ram_buffer(1559) := X"AF82802C";
ram_buffer(1560) := X"24A517BC";
ram_buffer(1561) := X"3C022003";
ram_buffer(1562) := X"AF828028";
ram_buffer(1563) := X"AFBF0014";
ram_buffer(1564) := X"0C0003B0";
ram_buffer(1565) := X"00002025";
ram_buffer(1566) := X"8F828024";
ram_buffer(1567) := X"3403C350";
ram_buffer(1568) := X"AC430004";
ram_buffer(1569) := X"8F838028";
ram_buffer(1570) := X"24050001";
ram_buffer(1571) := X"AC650000";
ram_buffer(1572) := X"3C041000";
ram_buffer(1573) := X"3C032001";
ram_buffer(1574) := X"AC8326A0";
ram_buffer(1575) := X"3C031000";
ram_buffer(1576) := X"248226A0";
ram_buffer(1577) := X"24631758";
ram_buffer(1578) := X"AC430014";
ram_buffer(1579) := X"3C031000";
ram_buffer(1580) := X"246317E4";
ram_buffer(1581) := X"AC430004";
ram_buffer(1582) := X"3C031000";
ram_buffer(1583) := X"246317A0";
ram_buffer(1584) := X"AC40001C";
ram_buffer(1585) := X"AC400024";
ram_buffer(1586) := X"AC40002C";
ram_buffer(1587) := X"AC400034";
ram_buffer(1588) := X"AC40003C";
ram_buffer(1589) := X"AC400018";
ram_buffer(1590) := X"AC400008";
ram_buffer(1591) := X"AC43000C";
ram_buffer(1592) := X"AC400010";
ram_buffer(1593) := X"3C06F000";
ram_buffer(1594) := X"8CC30004";
ram_buffer(1595) := X"3C051000";
ram_buffer(1596) := X"00031100";
ram_buffer(1597) := X"00431021";
ram_buffer(1598) := X"00021080";
ram_buffer(1599) := X"3C031000";
ram_buffer(1600) := X"24631D68";
ram_buffer(1601) := X"24420004";
ram_buffer(1602) := X"00621021";
ram_buffer(1603) := X"24A516DC";
ram_buffer(1604) := X"AC450038";
ram_buffer(1605) := X"AC40003C";
ram_buffer(1606) := X"8CC50004";
ram_buffer(1607) := X"00000000";
ram_buffer(1608) := X"00051100";
ram_buffer(1609) := X"00451021";
ram_buffer(1610) := X"00021080";
ram_buffer(1611) := X"00431021";
ram_buffer(1612) := X"8C420000";
ram_buffer(1613) := X"24030081";
ram_buffer(1614) := X"AC430000";
ram_buffer(1615) := X"8C8226A0";
ram_buffer(1616) := X"24030007";
ram_buffer(1617) := X"AC430000";
ram_buffer(1618) := X"8F828024";
ram_buffer(1619) := X"24030003";
ram_buffer(1620) := X"0C000049";
ram_buffer(1621) := X"AC430000";
ram_buffer(1622) := X"8FBF0014";
ram_buffer(1623) := X"24040001";
ram_buffer(1624) := X"08000046";
ram_buffer(1625) := X"27BD0018";
ram_buffer(1626) := X"3C02F000";
ram_buffer(1627) := X"8C430004";
ram_buffer(1628) := X"00000000";
ram_buffer(1629) := X"00031100";
ram_buffer(1630) := X"00431021";
ram_buffer(1631) := X"3C031000";
ram_buffer(1632) := X"24631D68";
ram_buffer(1633) := X"00021080";
ram_buffer(1634) := X"00431021";
ram_buffer(1635) := X"8C430000";
ram_buffer(1636) := X"24040001";
ram_buffer(1637) := X"8C620000";
ram_buffer(1638) := X"00000000";
ram_buffer(1639) := X"34420001";
ram_buffer(1640) := X"08000046";
ram_buffer(1641) := X"AC620000";
ram_buffer(1642) := X"8F83802C";
ram_buffer(1643) := X"00000000";
ram_buffer(1644) := X"8C620000";
ram_buffer(1645) := X"00000000";
ram_buffer(1646) := X"30420002";
ram_buffer(1647) := X"1040FFFC";
ram_buffer(1648) := X"00000000";
ram_buffer(1649) := X"AC640008";
ram_buffer(1650) := X"03E00008";
ram_buffer(1651) := X"00000000";
ram_buffer(1652) := X"10000003";
ram_buffer(1653) := X"00000000";
ram_buffer(1654) := X"40836000";
ram_buffer(1655) := X"00000000";
ram_buffer(1656) := X"40036000";
ram_buffer(1657) := X"40806000";
ram_buffer(1658) := X"8F84801C";
ram_buffer(1659) := X"8F828018";
ram_buffer(1660) := X"00000000";
ram_buffer(1661) := X"1082FFF8";
ram_buffer(1662) := X"00000000";
ram_buffer(1663) := X"8F828018";
ram_buffer(1664) := X"3C041000";
ram_buffer(1665) := X"248424A0";
ram_buffer(1666) := X"00441021";
ram_buffer(1667) := X"90420000";
ram_buffer(1668) := X"8F848018";
ram_buffer(1669) := X"304200FF";
ram_buffer(1670) := X"24840001";
ram_buffer(1671) := X"308401FF";
ram_buffer(1672) := X"AF848018";
ram_buffer(1673) := X"40836000";
ram_buffer(1674) := X"03E00008";
ram_buffer(1675) := X"00000000";
ram_buffer(1676) := X"24050004";
ram_buffer(1677) := X"8F83802C";
ram_buffer(1678) := X"308600FF";
ram_buffer(1679) := X"8C620000";
ram_buffer(1680) := X"00000000";
ram_buffer(1681) := X"30420002";
ram_buffer(1682) := X"1040FFFC";
ram_buffer(1683) := X"00000000";
ram_buffer(1684) := X"24A5FFFF";
ram_buffer(1685) := X"AC660008";
ram_buffer(1686) := X"14A0FFF6";
ram_buffer(1687) := X"00042202";
ram_buffer(1688) := X"03E00008";
ram_buffer(1689) := X"00000000";
ram_buffer(1690) := X"3C071000";
ram_buffer(1691) := X"00003025";
ram_buffer(1692) := X"00001025";
ram_buffer(1693) := X"24E724A0";
ram_buffer(1694) := X"24080020";
ram_buffer(1695) := X"40036000";
ram_buffer(1696) := X"40806000";
ram_buffer(1697) := X"8F85801C";
ram_buffer(1698) := X"8F848018";
ram_buffer(1699) := X"00000000";
ram_buffer(1700) := X"14A4000A";
ram_buffer(1701) := X"00000000";
ram_buffer(1702) := X"40836000";
ram_buffer(1703) := X"00000000";
ram_buffer(1704) := X"40036000";
ram_buffer(1705) := X"40806000";
ram_buffer(1706) := X"8F85801C";
ram_buffer(1707) := X"8F848018";
ram_buffer(1708) := X"00000000";
ram_buffer(1709) := X"10A4FFF8";
ram_buffer(1710) := X"00000000";
ram_buffer(1711) := X"8F848018";
ram_buffer(1712) := X"00000000";
ram_buffer(1713) := X"00E42021";
ram_buffer(1714) := X"90840000";
ram_buffer(1715) := X"8F858018";
ram_buffer(1716) := X"308400FF";
ram_buffer(1717) := X"24A50001";
ram_buffer(1718) := X"30A501FF";
ram_buffer(1719) := X"AF858018";
ram_buffer(1720) := X"40836000";
ram_buffer(1721) := X"00C41804";
ram_buffer(1722) := X"24C60008";
ram_buffer(1723) := X"14C8FFE3";
ram_buffer(1724) := X"00431025";
ram_buffer(1725) := X"03E00008";
ram_buffer(1726) := X"00000000";
ram_buffer(1727) := X"8F828028";
ram_buffer(1728) := X"00000000";
ram_buffer(1729) := X"03E00008";
ram_buffer(1730) := X"AC440008";
ram_buffer(1731) := X"8F828028";
ram_buffer(1732) := X"00000000";
ram_buffer(1733) := X"8C420008";
ram_buffer(1734) := X"03E00008";
ram_buffer(1735) := X"00000000";
ram_buffer(1736) := X"8F828028";
ram_buffer(1737) := X"00000000";
ram_buffer(1738) := X"8C420004";
ram_buffer(1739) := X"03E00008";
ram_buffer(1740) := X"00000000";
ram_buffer(1741) := X"3C03F000";
ram_buffer(1742) := X"8C620004";
ram_buffer(1743) := X"00000000";
ram_buffer(1744) := X"24420001";
ram_buffer(1745) := X"8F848030";
ram_buffer(1746) := X"00000000";
ram_buffer(1747) := X"AC820000";
ram_buffer(1748) := X"8C620004";
ram_buffer(1749) := X"8F848030";
ram_buffer(1750) := X"24420001";
ram_buffer(1751) := X"8C840000";
ram_buffer(1752) := X"00000000";
ram_buffer(1753) := X"1444FFF4";
ram_buffer(1754) := X"00000000";
ram_buffer(1755) := X"08000190";
ram_buffer(1756) := X"00000000";
ram_buffer(1757) := X"27BDFFE8";
ram_buffer(1758) := X"AFBF0014";
ram_buffer(1759) := X"0C000190";
ram_buffer(1760) := X"00000000";
ram_buffer(1761) := X"3C02F000";
ram_buffer(1762) := X"8C420004";
ram_buffer(1763) := X"00000000";
ram_buffer(1764) := X"24420001";
ram_buffer(1765) := X"8FBF0014";
ram_buffer(1766) := X"8F838030";
ram_buffer(1767) := X"00000000";
ram_buffer(1768) := X"AC620000";
ram_buffer(1769) := X"03E00008";
ram_buffer(1770) := X"27BD0018";
ram_buffer(1771) := X"27BDFFE8";
ram_buffer(1772) := X"AFB00010";
ram_buffer(1773) := X"AFBF0014";
ram_buffer(1774) := X"00808025";
ram_buffer(1775) := X"0C000190";
ram_buffer(1776) := X"00000000";
ram_buffer(1777) := X"8F828014";
ram_buffer(1778) := X"00000000";
ram_buffer(1779) := X"1602FFFB";
ram_buffer(1780) := X"00000000";
ram_buffer(1781) := X"8FBF0014";
ram_buffer(1782) := X"8FB00010";
ram_buffer(1783) := X"03E00008";
ram_buffer(1784) := X"27BD0018";
ram_buffer(1785) := X"27BDFFE8";
ram_buffer(1786) := X"AFBF0014";
ram_buffer(1787) := X"0C000190";
ram_buffer(1788) := X"00000000";
ram_buffer(1789) := X"8FBF0014";
ram_buffer(1790) := X"8F828014";
ram_buffer(1791) := X"03E00008";
ram_buffer(1792) := X"27BD0018";
ram_buffer(1793) := X"AF848008";
ram_buffer(1794) := X"03E00008";
ram_buffer(1795) := X"00000000";
ram_buffer(1796) := X"AF848004";
ram_buffer(1797) := X"03E00008";
ram_buffer(1798) := X"00000000";
ram_buffer(1799) := X"28CA0008";
ram_buffer(1800) := X"1540003E";
ram_buffer(1801) := X"00801025";
ram_buffer(1802) := X"10A00007";
ram_buffer(1803) := X"00043823";
ram_buffer(1804) := X"00000000";
ram_buffer(1805) := X"30A500FF";
ram_buffer(1806) := X"00055200";
ram_buffer(1807) := X"00AA2825";
ram_buffer(1808) := X"00055400";
ram_buffer(1809) := X"00AA2825";
ram_buffer(1810) := X"30EA0003";
ram_buffer(1811) := X"11400003";
ram_buffer(1812) := X"00CA3023";
ram_buffer(1813) := X"A8850000";
ram_buffer(1814) := X"008A2021";
ram_buffer(1815) := X"30EA0004";
ram_buffer(1816) := X"11400003";
ram_buffer(1817) := X"00CA3023";
ram_buffer(1818) := X"AC850000";
ram_buffer(1819) := X"008A2021";
ram_buffer(1820) := X"30D8003F";
ram_buffer(1821) := X"10D80016";
ram_buffer(1822) := X"00D83823";
ram_buffer(1823) := X"00873821";
ram_buffer(1824) := X"AC850000";
ram_buffer(1825) := X"AC850004";
ram_buffer(1826) := X"AC850008";
ram_buffer(1827) := X"AC85000C";
ram_buffer(1828) := X"AC850010";
ram_buffer(1829) := X"AC850014";
ram_buffer(1830) := X"AC850018";
ram_buffer(1831) := X"AC85001C";
ram_buffer(1832) := X"AC850020";
ram_buffer(1833) := X"AC850024";
ram_buffer(1834) := X"AC850028";
ram_buffer(1835) := X"AC85002C";
ram_buffer(1836) := X"AC850030";
ram_buffer(1837) := X"AC850034";
ram_buffer(1838) := X"AC850038";
ram_buffer(1839) := X"AC85003C";
ram_buffer(1840) := X"24840040";
ram_buffer(1841) := X"1487FFEE";
ram_buffer(1842) := X"00000000";
ram_buffer(1843) := X"03003025";
ram_buffer(1844) := X"30D8001F";
ram_buffer(1845) := X"10D8000A";
ram_buffer(1846) := X"00000000";
ram_buffer(1847) := X"AC850000";
ram_buffer(1848) := X"AC850004";
ram_buffer(1849) := X"AC850008";
ram_buffer(1850) := X"AC85000C";
ram_buffer(1851) := X"AC850010";
ram_buffer(1852) := X"AC850014";
ram_buffer(1853) := X"AC850018";
ram_buffer(1854) := X"AC85001C";
ram_buffer(1855) := X"24840020";
ram_buffer(1856) := X"33060003";
ram_buffer(1857) := X"10D80005";
ram_buffer(1858) := X"03063823";
ram_buffer(1859) := X"00873821";
ram_buffer(1860) := X"24840004";
ram_buffer(1861) := X"1487FFFE";
ram_buffer(1862) := X"AC85FFFC";
ram_buffer(1863) := X"18C00004";
ram_buffer(1864) := X"00863821";
ram_buffer(1865) := X"24840001";
ram_buffer(1866) := X"1487FFFE";
ram_buffer(1867) := X"A085FFFF";
ram_buffer(1868) := X"03E00008";
ram_buffer(1869) := X"00000000";
ram_buffer(1870) := X"00000100";
ram_buffer(1871) := X"01010001";
ram_buffer(1872) := X"00000000";
ram_buffer(1873) := X"00000000";
ram_buffer(1874) := X"00000000";
ram_buffer(1875) := X"00000000";
ram_buffer(1876) := X"FFFFFFFF";
ram_buffer(1877) := X"FFFFFFFF";
ram_buffer(1878) := X"FFFFFFFF";
ram_buffer(1879) := X"FFFFFFFF";
ram_buffer(1880) := X"FFFFFFFF";
ram_buffer(1881) := X"FFFFFFFF";
ram_buffer(1882) := X"FFFFFFFF";
ram_buffer(1883) := X"00000000";
ram_buffer(1884) := X"00000000";
ram_buffer(1885) := X"00000000";
ram_buffer(1886) := X"00000000";
ram_buffer(1887) := X"00000000";
ram_buffer(1888) := X"00000000";
ram_buffer(1889) := X"00000000";
ram_buffer(1890) := X"00000000";
ram_buffer(1891) := X"00000000";
ram_buffer(1892) := X"00000000";
ram_buffer(1893) := X"00000000";
ram_buffer(1894) := X"00000000";
ram_buffer(1895) := X"00000000";
ram_buffer(1896) := X"00000000";
ram_buffer(1897) := X"00000000";
ram_buffer(1898) := X"00000000";
ram_buffer(1899) := X"FFFFFFFF";
ram_buffer(1900) := X"00000000";
ram_buffer(1901) := X"00000000";
ram_buffer(1902) := X"00000000";
ram_buffer(1903) := X"00000000";
ram_buffer(1904) := X"00000000";
ram_buffer(1905) := X"00000000";
ram_buffer(1906) := X"00000000";
ram_buffer(1907) := X"00000000";
ram_buffer(1908) := X"00000000";
ram_buffer(1909) := X"00000000";
ram_buffer(1910) := X"00000000";
ram_buffer(1911) := X"00000000";
ram_buffer(1912) := X"00000000";
ram_buffer(1913) := X"00000000";
ram_buffer(1914) := X"00000000";
ram_buffer(1915) := X"00000000";
ram_buffer(1916) := X"FFFFFFFF";
ram_buffer(1917) := X"00000000";
ram_buffer(1918) := X"00000000";
ram_buffer(1919) := X"00000000";
ram_buffer(1920) := X"00000000";
ram_buffer(1921) := X"00000000";
ram_buffer(1922) := X"00000000";
ram_buffer(1923) := X"00000000";
ram_buffer(1924) := X"00000000";
ram_buffer(1925) := X"00000000";
ram_buffer(1926) := X"00000000";
ram_buffer(1927) := X"00000000";
ram_buffer(1928) := X"00000000";
ram_buffer(1929) := X"00000000";
ram_buffer(1930) := X"00000000";
ram_buffer(1931) := X"00000000";
ram_buffer(1932) := X"00000000";
ram_buffer(1933) := X"100016D4";
ram_buffer(1934) := X"100016D4";
return ram_buffer;
end;
end;
|
------------------------------------------------------------
-- Notes:
-- Clock on FALLING EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the falling
-- clock cycle.
--
-- Additional Comments:
-- The register latches it's data on the FALLING edge
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use UMDRISC.ALL;
ENTITY Reg24 IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END Reg24;
ARCHITECTURE Behavior OF Reg24 IS
BEGIN
PROCESS(Resetn, Clock)
BEGIN
IF Resetn = '0' THEN
Q <= (OTHERS => '0');
ELSIF Clock'EVENT AND Clock = '0' THEN
IF ENABLE = '1' THEN
Q <= D;
END IF;
END IF;
END PROCESS;
END Behavior;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc541.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b02x00p06n01i00541ent IS
END c03s03b02x00p06n01i00541ent;
ARCHITECTURE c03s03b02x00p06n01i00541arch OF c03s03b02x00p06n01i00541ent IS
BEGIN
TESTING: PROCESS
-- Enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
type AC1 is access SWITCH_LEVEL;
-- Declare a variable.
variable VAR : AC1;
BEGIN
-- Perform the test.
assert( VAR = NULL );
DEALLOCATE( VAR );
assert NOT( VAR = NULL )
report "***PASSED TEST: c03s03b02x00p06n01i00541"
severity NOTE;
assert ( VAR = NULL )
report "***FAILED TEST: c03s03b02x00p06n01i00541 - DEALLOCATE operation test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b02x00p06n01i00541arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc541.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b02x00p06n01i00541ent IS
END c03s03b02x00p06n01i00541ent;
ARCHITECTURE c03s03b02x00p06n01i00541arch OF c03s03b02x00p06n01i00541ent IS
BEGIN
TESTING: PROCESS
-- Enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
type AC1 is access SWITCH_LEVEL;
-- Declare a variable.
variable VAR : AC1;
BEGIN
-- Perform the test.
assert( VAR = NULL );
DEALLOCATE( VAR );
assert NOT( VAR = NULL )
report "***PASSED TEST: c03s03b02x00p06n01i00541"
severity NOTE;
assert ( VAR = NULL )
report "***FAILED TEST: c03s03b02x00p06n01i00541 - DEALLOCATE operation test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b02x00p06n01i00541arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc541.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b02x00p06n01i00541ent IS
END c03s03b02x00p06n01i00541ent;
ARCHITECTURE c03s03b02x00p06n01i00541arch OF c03s03b02x00p06n01i00541ent IS
BEGIN
TESTING: PROCESS
-- Enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
type AC1 is access SWITCH_LEVEL;
-- Declare a variable.
variable VAR : AC1;
BEGIN
-- Perform the test.
assert( VAR = NULL );
DEALLOCATE( VAR );
assert NOT( VAR = NULL )
report "***PASSED TEST: c03s03b02x00p06n01i00541"
severity NOTE;
assert ( VAR = NULL )
report "***FAILED TEST: c03s03b02x00p06n01i00541 - DEALLOCATE operation test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b02x00p06n01i00541arch;
|
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity dsp_mul is
port(
clk: in std_ulogic;
a_i: in std_ulogic_vector(23 downto 0);
b_i: in std_ulogic_vector(16 downto 0);
p_o: out std_ulogic_vector(40 downto 0)
);
end dsp_mul;
architecture behav of dsp_mul is
signal a_lv: std_logic_vector(29 downto 0);
signal b_lv: std_logic_vector(17 downto 0);
signal p_lv: std_logic_vector(47 downto 0);
signal clk_lv: std_logic;
begin
a_lv <= std_logic_vector("000000" & a_i);
b_lv <= std_logic_vector('0'& b_i);
clk_lv <= clk;
DSP48E1_inst : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 0, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 0, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 0, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 0, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 0, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 0, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 0, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 0, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 0, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 0, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => open, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => p_lv, -- 48-bit output: Primary data output -- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others => '0'), -- 30-bit input: A cascade data input
BCIN => (others => '0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => (others => '0'), -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => (others => '0'), -- 4-bit input: ALU control input
CARRYINSEL => (others => '0'), -- 3-bit input: Carry select input
CLK => clk_lv, -- 1-bit input: Clock input
INMODE => (others => '0'), -- 5-bit input: INMODE control input
OPMODE => "0110101", -- 7-bit input: Operation mode input
-- Data: 30-bit (each) input: Data Ports
A => a_lv, -- 30-bit input: A data input
B => b_lv, -- 18-bit input: B data input
C => (others => '0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others => '0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '0', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '0', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '0', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '1', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '1', -- 1-bit input: Clock enable input for DREG
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
-- End of DSP48E1_inst instantiation
p_o <= std_ulogic_vector(p_lv(40 downto 0));
end behav;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:3.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v3_0;
USE axi_bram_ctrl_v3_0.axi_bram_ctrl;
ENTITY zynq_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zynq_1_axi_bram_ctrl_0_0;
ARCHITECTURE zynq_1_axi_bram_ctrl_0_0_arch OF zynq_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_MEMORY_DEPTH : INTEGER;
C_FAMILY : STRING;
C_BRAM_INST_MODE : STRING;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zynq_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zynq_1_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "zynq_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zynq_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "zynq_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=3.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,C_MEMORY_DEPTH=1024,C_FAMILY=zynq,C_BRAM_INST_MODE=EXTERNAL,C_BRAM_ADDR_WIDTH=10,C_S_AXI_ADDR_WIDTH=12,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=12,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_MEMORY_DEPTH => 1024,
C_FAMILY => "zynq",
C_BRAM_INST_MODE => "EXTERNAL",
C_BRAM_ADDR_WIDTH => 10,
C_S_AXI_ADDR_WIDTH => 12,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zynq_1_axi_bram_ctrl_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test is
port(
clk, reset: in std_logic;
data_1, data_2: in std_logic;
clk_out: out std_logic;
ps_control: out std_logic;
LED: out std_logic_vector(7 downto 0)
);
end test;
architecture behaviour of test is
constant DELAY: integer := 500000;
signal counter, counter_next: std_logic_vector(18 downto 0);
type states is (start, count);
signal state, state_next: states;
signal clk_out_1, clk_out_2: std_logic;
signal ps_control_1, ps_control_2: std_logic;
signal nes1_a, nes2_a, nes1_b, nes2_b,
nes1_select, nes2_select, nes1_start, nes2_start,
nes1_up, nes2_up, nes1_down, nes2_down,
nes1_left, nes2_left, nes1_right, nes2_right: std_logic;
signal register_1, register_2: std_logic_vector(7 downto 0);
signal reg_buf, reg_buf_next: std_logic_vector(7 downto 0);
begin
process(clk, reset, state_next)
begin
if reset = '1' then
state <= start;
reg_buf <= (others => '0');
counter <= (others => '0');
elsif falling_edge(clk) then
state <= state_next;
reg_buf <= reg_buf_next;
counter <= counter_next;
end if;
end process;
data_hold: process(state, state_next,
register_1, register_2, reg_buf,
counter)
begin
state_next <= state;
counter_next <= counter;
reg_buf_next <= reg_buf;
case state is
when start =>
reg_buf_next <= (others => '0');
counter_next <= (others => '0');
if (register_1 xor register_2) > 0 then
reg_buf_next <= (register_1 xor register_2);
state_next <= count;
end if;
when count =>
counter_next <= counter + 1;
if counter_next = DELAY then
state_next <= start;
end if;
end case;
end process;
-- my board uses same clk and p/s signals for both controllers
clk_out <= clk_out_1 and clk_out_2;
ps_control <= ps_control_1 and ps_control_2;
NES_1:
entity work.controller(arch)
port map(
clk => clk, reset => reset,
data_in => data_1,
clk_out => clk_out_1,
ps_control => ps_control_1,
gamepad(0) => nes1_a, gamepad(1) => nes1_b,
gamepad(2) => nes1_select, gamepad(3) => nes1_start,
gamepad(4) => nes1_up, gamepad(5) => nes1_down,
gamepad(6) => nes1_left, gamepad(7) => nes1_right
);
NES_2:
entity work.controller(arch)
port map(
clk => clk, reset => reset,
data_in => data_2,
clk_out => clk_out_2,
ps_control => ps_control_2,
gamepad(0) => nes2_a, gamepad(1) => nes2_b,
gamepad(2) => nes2_select, gamepad(3) => nes2_start,
gamepad(4) => nes2_up, gamepad(5) => nes2_down,
gamepad(6) => nes2_left, gamepad(7) => nes2_right
);
register_1 <= nes1_a & nes1_b &
nes1_start & nes1_select &
nes1_up & nes1_down &
nes1_left & nes1_right;
register_2 <= nes2_a & nes2_b &
nes2_start & nes2_select &
nes2_up & nes2_down &
nes2_left & nes2_right;
LED <= reg_buf;
end behaviour;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/21/2015 12:17:45 PM
-- Design Name:
-- Module Name: SRAM16Bytes - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SRAM16Bytes is
Port
(
Load : in BIT;
Sel : in BIT;
Address : in BIT_VECTOR(3 downto 0);
InData : in BIT_VECTOR(7 downto 0);
OutData : out BIT_VECTOR(7 downto 0)
);
end SRAM16Bytes;
architecture Behavioral of SRAM16Bytes is
component Register8Bit is
Port
(
Load : in BIT; -- Load Line
Sel : in BIT; -- Select Line
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end component Register8Bit;
component Decoder2to4 is
Port
(
A : in BIT_VECTOR(1 downto 0); -- 2-Bit Memory Address (Input)
X : out BIT_VECTOR(3 downto 0) -- 4-Bit Address Lines (Output)
);
end component Decoder2to4;
signal AccessLines1: BIT_VECTOR(3 downto 0);
signal AccessLines2: BIT_VECTOR(3 downto 0);
signal OutData1 : BIT_VECTOR(7 downto 0);
signal OutData2 : BIT_VECTOR(7 downto 0);
signal OutData3 : BIT_VECTOR(7 downto 0);
signal OutData4 : BIT_VECTOR(7 downto 0);
signal OutData5 : BIT_VECTOR(7 downto 0);
signal OutData6 : BIT_VECTOR(7 downto 0);
signal OutData7 : BIT_VECTOR(7 downto 0);
signal OutData8 : BIT_VECTOR(7 downto 0);
signal OutData9 : BIT_VECTOR(7 downto 0);
signal OutData10 : BIT_VECTOR(7 downto 0);
signal OutData11 : BIT_VECTOR(7 downto 0);
signal OutData12 : BIT_VECTOR(7 downto 0);
signal OutData13 : BIT_VECTOR(7 downto 0);
signal OutData14 : BIT_VECTOR(7 downto 0);
signal OutData15 : BIT_VECTOR(7 downto 0);
signal OutData16 : BIT_VECTOR(7 downto 0);
signal LoadLine1: BIT;
signal LoadLine2: BIT;
signal LoadLine3: BIT;
signal LoadLine4: BIT;
signal LoadLine5: BIT;
signal LoadLine6: BIT;
signal LoadLine7: BIT;
signal LoadLine8: BIT;
signal LoadLine9: BIT;
signal LoadLine10: BIT;
signal LoadLine11: BIT;
signal LoadLine12: BIT;
signal LoadLine13: BIT;
signal LoadLine14: BIT;
signal LoadLine15: BIT;
signal LoadLine16: BIT;
signal SelectLine1: BIT;
signal SelectLine2: BIT;
signal SelectLine3: BIT;
signal SelectLine4: BIT;
signal SelectLine5: BIT;
signal SelectLine6: BIT;
signal SelectLine7: BIT;
signal SelectLine8: BIT;
signal SelectLine9: BIT;
signal SelectLine10: BIT;
signal SelectLine11: BIT;
signal SelectLine12: BIT;
signal SelectLine13: BIT;
signal SelectLine14: BIT;
signal SelectLine15: BIT;
signal SelectLine16: BIT;
begin
-- The 16 8-bit SRAM memory cells are logically arranged in a 4x4 matrix
-- 1 2 3 4
-- 5 6 7 8
-- 9 10 11 12
-- 13 14 14 16
-- The 1st decoder takes the lower 2 bits of the address and provides the row offset into the 4x4 matrix
Decoder1: Decoder2to4 port map(Address(1 downto 0), AccessLines1);
-- The 2nd decoder takes the upper 2 bits of the address and provides the column offset into the 4x4 matrix
Decoder2: Decoder2to4 port map(Address(3 downto 2), AccessLines2);
-- Create a dedicate Load-Line for every 8-bit SRAM memory cell
LoadLine1 <= Load and AccessLines1(0) and AccessLines2(0);
LoadLine2 <= Load and AccessLines1(1) and AccessLines2(0);
LoadLine3 <= Load and AccessLines1(2) and AccessLines2(0);
LoadLine4 <= Load and AccessLines1(3) and AccessLines2(0);
LoadLine5 <= Load and AccessLines1(0) and AccessLines2(1);
LoadLine6 <= Load and AccessLines1(1) and AccessLines2(1);
LoadLine7 <= Load and AccessLines1(2) and AccessLines2(1);
LoadLine8 <= Load and AccessLines1(3) and AccessLines2(1);
LoadLine9 <= Load and AccessLines1(0) and AccessLines2(2);
LoadLine10 <= Load and AccessLines1(1) and AccessLines2(2);
LoadLine11 <= Load and AccessLines1(2) and AccessLines2(2);
LoadLine12 <= Load and AccessLines1(3) and AccessLines2(2);
LoadLine13 <= Load and AccessLines1(0) and AccessLines2(3);
LoadLine14 <= Load and AccessLines1(1) and AccessLines2(3);
LoadLine15 <= Load and AccessLines1(2) and AccessLines2(3);
LoadLine16 <= Load and AccessLines1(3) and AccessLines2(3);
-- Create a dedicate Select-Line for every 8-bit SRAM memory cell
SelectLine1 <= Sel and AccessLines1(0) and AccessLines2(0);
SelectLine2 <= Sel and AccessLines1(1) and AccessLines2(0);
SelectLine3 <= Sel and AccessLines1(2) and AccessLines2(0);
SelectLine4 <= Sel and AccessLines1(3) and AccessLines2(0);
SelectLine5 <= Sel and AccessLines1(0) and AccessLines2(1);
SelectLine6 <= Sel and AccessLines1(1) and AccessLines2(1);
SelectLine7 <= Sel and AccessLines1(2) and AccessLines2(1);
SelectLine8 <= Sel and AccessLines1(3) and AccessLines2(1);
SelectLine9 <= Sel and AccessLines1(0) and AccessLines2(2);
SelectLine10 <= Sel and AccessLines1(1) and AccessLines2(2);
SelectLine11 <= Sel and AccessLines1(2) and AccessLines2(2);
SelectLine12 <= Sel and AccessLines1(3) and AccessLines2(2);
SelectLine13 <= Sel and AccessLines1(0) and AccessLines2(3);
SelectLine14 <= Sel and AccessLines1(1) and AccessLines2(3);
SelectLine15 <= Sel and AccessLines1(2) and AccessLines2(3);
SelectLine16 <= Sel and AccessLines1(3) and AccessLines2(3);
-- Instantiate the 16 individual 8-bit SRAM memory cells
ram1: Register8Bit port map (LoadLine1, SelectLine1, InData, OutData1);
ram2: Register8Bit port map (LoadLine2, SelectLine2, InData, OutData2);
ram3: Register8Bit port map (LoadLine3, SelectLine3, InData, OutData3);
ram4: Register8Bit port map (LoadLine4, SelectLine4, InData, OutData4);
ram5: Register8Bit port map (LoadLine5, SelectLine5, InData, OutData5);
ram6: Register8Bit port map (LoadLine6, SelectLine6, InData, OutData6);
ram7: Register8Bit port map (LoadLine7, SelectLine7, InData, OutData7);
ram8: Register8Bit port map (LoadLine8, SelectLine8, InData, OutData8);
ram9: Register8Bit port map (LoadLine9, SelectLine9, InData, OutData9);
ram10: Register8Bit port map (LoadLine10, SelectLine10, InData, OutData10);
ram11: Register8Bit port map (LoadLine11, SelectLine11, InData, OutData11);
ram12: Register8Bit port map (LoadLine12, SelectLine12, InData, OutData12);
ram13: Register8Bit port map (LoadLine13, SelectLine13, InData, OutData13);
ram14: Register8Bit port map (LoadLine14, SelectLine14, InData, OutData14);
ram15: Register8Bit port map (LoadLine15, SelectLine15, InData, OutData15);
ram16: Register8Bit port map (LoadLine16, SelectLine16, InData, OutData16);
-- Return the read data
OutData <= OutData1 or
OutData2 or
OutData3 or
OutData4 or
OutData5 or
OutData6 or
OutData7 or
OutData8 or
OutData9 or
OutData10 or
OutData11 or
OutData12 or
OutData13 or
OutData14 or
OutData15 or
OutData16;
end Behavioral;
|
package other_pkg is
type type_t is (value1, value2);
function fun return integer;
procedure proc;
end package;
package body other_pkg is
function fun return integer is
begin
return 0;
end function;
procedure proc is
begin
end procedure;
end package body;
use work.other_pkg.all;
package pkg is
end package;
package body pkg is
-- Error here when work library not called "work"
alias pkg_t is work.other_pkg.type_t;
procedure proc is
variable var : integer;
begin
work.other_pkg.proc;
var := work.other_pkg.fun;
end procedure;
end package body;
|
package other_pkg is
type type_t is (value1, value2);
function fun return integer;
procedure proc;
end package;
package body other_pkg is
function fun return integer is
begin
return 0;
end function;
procedure proc is
begin
end procedure;
end package body;
use work.other_pkg.all;
package pkg is
end package;
package body pkg is
-- Error here when work library not called "work"
alias pkg_t is work.other_pkg.type_t;
procedure proc is
variable var : integer;
begin
work.other_pkg.proc;
var := work.other_pkg.fun;
end procedure;
end package body;
|
package other_pkg is
type type_t is (value1, value2);
function fun return integer;
procedure proc;
end package;
package body other_pkg is
function fun return integer is
begin
return 0;
end function;
procedure proc is
begin
end procedure;
end package body;
use work.other_pkg.all;
package pkg is
end package;
package body pkg is
-- Error here when work library not called "work"
alias pkg_t is work.other_pkg.type_t;
procedure proc is
variable var : integer;
begin
work.other_pkg.proc;
var := work.other_pkg.fun;
end procedure;
end package body;
|
package other_pkg is
type type_t is (value1, value2);
function fun return integer;
procedure proc;
end package;
package body other_pkg is
function fun return integer is
begin
return 0;
end function;
procedure proc is
begin
end procedure;
end package body;
use work.other_pkg.all;
package pkg is
end package;
package body pkg is
-- Error here when work library not called "work"
alias pkg_t is work.other_pkg.type_t;
procedure proc is
variable var : integer;
begin
work.other_pkg.proc;
var := work.other_pkg.fun;
end procedure;
end package body;
|
package other_pkg is
type type_t is (value1, value2);
function fun return integer;
procedure proc;
end package;
package body other_pkg is
function fun return integer is
begin
return 0;
end function;
procedure proc is
begin
end procedure;
end package body;
use work.other_pkg.all;
package pkg is
end package;
package body pkg is
-- Error here when work library not called "work"
alias pkg_t is work.other_pkg.type_t;
procedure proc is
variable var : integer;
begin
work.other_pkg.proc;
var := work.other_pkg.fun;
end procedure;
end package body;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : tb_floppy_stream.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.floppy_emu_pkg.all;
use work.flat_memory_model.all;
entity tb_floppy is
end tb_floppy;
architecture tb of tb_floppy is
signal clock : std_logic := '0';
signal clock_en : std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
signal reset : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal track : std_logic_vector(6 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal read_data : std_logic_vector(7 downto 0);
signal write_data : std_logic_vector(7 downto 0) := X"55";
---
signal mem_clock : std_logic := '0';
signal mem_req : std_logic;
signal mem_rwn : std_logic;
signal mem_rack : std_logic := '0';
signal mem_dack : std_logic := '0';
signal mem_addr : std_logic_vector(31 downto 0) := (others => '0');
signal mem_wdata : std_logic_vector(7 downto 0);
signal mem_rdata : std_logic_vector(7 downto 0) := X"00";
type t_integer_array is array (natural range <>) of integer;
constant rate_table : t_integer_array(0 to 63) := (
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
2, 2, 2, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 );
begin
clock <= not clock after 31.25 ns;
reset <= '1', '0' after 400 ns;
mem_clock <= not mem_clock after 100 ns; -- 5 Mhz
process
begin
wait until clock='1';
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
end process;
mut: entity work.floppy
port map (
drv_clock => clock,
drv_clock_en => clock_en, -- combi clk/cke that yields 4 MHz; eg. 16/4
drv_reset => reset,
motor_on => motor_on,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
soe => soe,
rate_ctrl => rate_ctrl,
write_data => write_data,
read_data => read_data,
track => track,
mem_clock => mem_clock,
mem_reset => reset,
mem_req => mem_req,
mem_rwn => mem_rwn,
mem_rack => mem_rack,
mem_dack => mem_dack,
mem_addr => mem_addr(19 downto 0), -- 1MB
mem_wdata => mem_wdata,
mem_rdata => mem_rdata );
test: process
begin
motor_on <= '1';
mode <= '1';
write_prot_n <= '1';
soe <= '1';
wait for 700 us;
wait until byte_ready='0';
wait for 10 us;
mode <= '0'; -- switch to write
for i in 0 to 255 loop
wait until byte_ready='0';
wait for 10 us;
write_data <= write_data + 1;
end loop;
wait until byte_ready='0';
mode <= '1';
wait;
end process;
move: process
begin
wait for 2 us;
for i in 0 to 100 loop
step <= step + 1;
wait for 2 us;
end loop;
wait for 2 us;
for i in 0 to 100 loop
step <= step - 1;
wait for 2 us;
end loop;
wait;
end process;
rate_ctrl <= conv_std_logic_vector(rate_table(conv_integer(track(6 downto 1))), 2);
memory: process
variable h : h_mem_object;
begin
register_mem_model("my memory", h);
for i in 0 to 15 loop
write_memory_32(h, conv_std_logic_vector(i*4, 32), X"FFFFFFFF");
end loop;
while true loop
wait until mem_clock='1';
if mem_req='1' then
wait until mem_clock='1';
wait until mem_clock='1';
wait until mem_clock='1';
if mem_rwn='0' then -- write
write_memory_8(h, mem_addr, mem_wdata);
mem_ack <= '1';
wait until mem_clock='1';
mem_ack <= '0';
else
mem_rdata <= read_memory_8(h, mem_addr);
mem_ack <= '1';
wait until mem_clock='1';
mem_ack <= '0';
mem_rdata <= X"00";
end if;
end if;
end loop;
end process;
end tb; |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : tb_floppy_stream.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.floppy_emu_pkg.all;
use work.flat_memory_model.all;
entity tb_floppy is
end tb_floppy;
architecture tb of tb_floppy is
signal clock : std_logic := '0';
signal clock_en : std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
signal reset : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal track : std_logic_vector(6 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal read_data : std_logic_vector(7 downto 0);
signal write_data : std_logic_vector(7 downto 0) := X"55";
---
signal mem_clock : std_logic := '0';
signal mem_req : std_logic;
signal mem_rwn : std_logic;
signal mem_rack : std_logic := '0';
signal mem_dack : std_logic := '0';
signal mem_addr : std_logic_vector(31 downto 0) := (others => '0');
signal mem_wdata : std_logic_vector(7 downto 0);
signal mem_rdata : std_logic_vector(7 downto 0) := X"00";
type t_integer_array is array (natural range <>) of integer;
constant rate_table : t_integer_array(0 to 63) := (
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
2, 2, 2, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 );
begin
clock <= not clock after 31.25 ns;
reset <= '1', '0' after 400 ns;
mem_clock <= not mem_clock after 100 ns; -- 5 Mhz
process
begin
wait until clock='1';
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
end process;
mut: entity work.floppy
port map (
drv_clock => clock,
drv_clock_en => clock_en, -- combi clk/cke that yields 4 MHz; eg. 16/4
drv_reset => reset,
motor_on => motor_on,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
soe => soe,
rate_ctrl => rate_ctrl,
write_data => write_data,
read_data => read_data,
track => track,
mem_clock => mem_clock,
mem_reset => reset,
mem_req => mem_req,
mem_rwn => mem_rwn,
mem_rack => mem_rack,
mem_dack => mem_dack,
mem_addr => mem_addr(19 downto 0), -- 1MB
mem_wdata => mem_wdata,
mem_rdata => mem_rdata );
test: process
begin
motor_on <= '1';
mode <= '1';
write_prot_n <= '1';
soe <= '1';
wait for 700 us;
wait until byte_ready='0';
wait for 10 us;
mode <= '0'; -- switch to write
for i in 0 to 255 loop
wait until byte_ready='0';
wait for 10 us;
write_data <= write_data + 1;
end loop;
wait until byte_ready='0';
mode <= '1';
wait;
end process;
move: process
begin
wait for 2 us;
for i in 0 to 100 loop
step <= step + 1;
wait for 2 us;
end loop;
wait for 2 us;
for i in 0 to 100 loop
step <= step - 1;
wait for 2 us;
end loop;
wait;
end process;
rate_ctrl <= conv_std_logic_vector(rate_table(conv_integer(track(6 downto 1))), 2);
memory: process
variable h : h_mem_object;
begin
register_mem_model("my memory", h);
for i in 0 to 15 loop
write_memory_32(h, conv_std_logic_vector(i*4, 32), X"FFFFFFFF");
end loop;
while true loop
wait until mem_clock='1';
if mem_req='1' then
wait until mem_clock='1';
wait until mem_clock='1';
wait until mem_clock='1';
if mem_rwn='0' then -- write
write_memory_8(h, mem_addr, mem_wdata);
mem_ack <= '1';
wait until mem_clock='1';
mem_ack <= '0';
else
mem_rdata <= read_memory_8(h, mem_addr);
mem_ack <= '1';
wait until mem_clock='1';
mem_ack <= '0';
mem_rdata <= X"00";
end if;
end if;
end loop;
end process;
end tb; |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : tb_floppy_stream.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.floppy_emu_pkg.all;
use work.flat_memory_model.all;
entity tb_floppy is
end tb_floppy;
architecture tb of tb_floppy is
signal clock : std_logic := '0';
signal clock_en : std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
signal reset : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal track : std_logic_vector(6 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal read_data : std_logic_vector(7 downto 0);
signal write_data : std_logic_vector(7 downto 0) := X"55";
---
signal mem_clock : std_logic := '0';
signal mem_req : std_logic;
signal mem_rwn : std_logic;
signal mem_rack : std_logic := '0';
signal mem_dack : std_logic := '0';
signal mem_addr : std_logic_vector(31 downto 0) := (others => '0');
signal mem_wdata : std_logic_vector(7 downto 0);
signal mem_rdata : std_logic_vector(7 downto 0) := X"00";
type t_integer_array is array (natural range <>) of integer;
constant rate_table : t_integer_array(0 to 63) := (
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
2, 2, 2, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 );
begin
clock <= not clock after 31.25 ns;
reset <= '1', '0' after 400 ns;
mem_clock <= not mem_clock after 100 ns; -- 5 Mhz
process
begin
wait until clock='1';
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
end process;
mut: entity work.floppy
port map (
drv_clock => clock,
drv_clock_en => clock_en, -- combi clk/cke that yields 4 MHz; eg. 16/4
drv_reset => reset,
motor_on => motor_on,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
soe => soe,
rate_ctrl => rate_ctrl,
write_data => write_data,
read_data => read_data,
track => track,
mem_clock => mem_clock,
mem_reset => reset,
mem_req => mem_req,
mem_rwn => mem_rwn,
mem_rack => mem_rack,
mem_dack => mem_dack,
mem_addr => mem_addr(19 downto 0), -- 1MB
mem_wdata => mem_wdata,
mem_rdata => mem_rdata );
test: process
begin
motor_on <= '1';
mode <= '1';
write_prot_n <= '1';
soe <= '1';
wait for 700 us;
wait until byte_ready='0';
wait for 10 us;
mode <= '0'; -- switch to write
for i in 0 to 255 loop
wait until byte_ready='0';
wait for 10 us;
write_data <= write_data + 1;
end loop;
wait until byte_ready='0';
mode <= '1';
wait;
end process;
move: process
begin
wait for 2 us;
for i in 0 to 100 loop
step <= step + 1;
wait for 2 us;
end loop;
wait for 2 us;
for i in 0 to 100 loop
step <= step - 1;
wait for 2 us;
end loop;
wait;
end process;
rate_ctrl <= conv_std_logic_vector(rate_table(conv_integer(track(6 downto 1))), 2);
memory: process
variable h : h_mem_object;
begin
register_mem_model("my memory", h);
for i in 0 to 15 loop
write_memory_32(h, conv_std_logic_vector(i*4, 32), X"FFFFFFFF");
end loop;
while true loop
wait until mem_clock='1';
if mem_req='1' then
wait until mem_clock='1';
wait until mem_clock='1';
wait until mem_clock='1';
if mem_rwn='0' then -- write
write_memory_8(h, mem_addr, mem_wdata);
mem_ack <= '1';
wait until mem_clock='1';
mem_ack <= '0';
else
mem_rdata <= read_memory_8(h, mem_addr);
mem_ack <= '1';
wait until mem_clock='1';
mem_ack <= '0';
mem_rdata <= X"00";
end if;
end if;
end loop;
end process;
end tb; |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : tb_floppy_stream.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.floppy_emu_pkg.all;
use work.flat_memory_model.all;
entity tb_floppy is
end tb_floppy;
architecture tb of tb_floppy is
signal clock : std_logic := '0';
signal clock_en : std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
signal reset : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal track : std_logic_vector(6 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal read_data : std_logic_vector(7 downto 0);
signal write_data : std_logic_vector(7 downto 0) := X"55";
---
signal mem_clock : std_logic := '0';
signal mem_req : std_logic;
signal mem_rwn : std_logic;
signal mem_rack : std_logic := '0';
signal mem_dack : std_logic := '0';
signal mem_addr : std_logic_vector(31 downto 0) := (others => '0');
signal mem_wdata : std_logic_vector(7 downto 0);
signal mem_rdata : std_logic_vector(7 downto 0) := X"00";
type t_integer_array is array (natural range <>) of integer;
constant rate_table : t_integer_array(0 to 63) := (
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
2, 2, 2, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 );
begin
clock <= not clock after 31.25 ns;
reset <= '1', '0' after 400 ns;
mem_clock <= not mem_clock after 100 ns; -- 5 Mhz
process
begin
wait until clock='1';
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
end process;
mut: entity work.floppy
port map (
drv_clock => clock,
drv_clock_en => clock_en, -- combi clk/cke that yields 4 MHz; eg. 16/4
drv_reset => reset,
motor_on => motor_on,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
soe => soe,
rate_ctrl => rate_ctrl,
write_data => write_data,
read_data => read_data,
track => track,
mem_clock => mem_clock,
mem_reset => reset,
mem_req => mem_req,
mem_rwn => mem_rwn,
mem_rack => mem_rack,
mem_dack => mem_dack,
mem_addr => mem_addr(19 downto 0), -- 1MB
mem_wdata => mem_wdata,
mem_rdata => mem_rdata );
test: process
begin
motor_on <= '1';
mode <= '1';
write_prot_n <= '1';
soe <= '1';
wait for 700 us;
wait until byte_ready='0';
wait for 10 us;
mode <= '0'; -- switch to write
for i in 0 to 255 loop
wait until byte_ready='0';
wait for 10 us;
write_data <= write_data + 1;
end loop;
wait until byte_ready='0';
mode <= '1';
wait;
end process;
move: process
begin
wait for 2 us;
for i in 0 to 100 loop
step <= step + 1;
wait for 2 us;
end loop;
wait for 2 us;
for i in 0 to 100 loop
step <= step - 1;
wait for 2 us;
end loop;
wait;
end process;
rate_ctrl <= conv_std_logic_vector(rate_table(conv_integer(track(6 downto 1))), 2);
memory: process
variable h : h_mem_object;
begin
register_mem_model("my memory", h);
for i in 0 to 15 loop
write_memory_32(h, conv_std_logic_vector(i*4, 32), X"FFFFFFFF");
end loop;
while true loop
wait until mem_clock='1';
if mem_req='1' then
wait until mem_clock='1';
wait until mem_clock='1';
wait until mem_clock='1';
if mem_rwn='0' then -- write
write_memory_8(h, mem_addr, mem_wdata);
mem_ack <= '1';
wait until mem_clock='1';
mem_ack <= '0';
else
mem_rdata <= read_memory_8(h, mem_addr);
mem_ack <= '1';
wait until mem_clock='1';
mem_ack <= '0';
mem_rdata <= X"00";
end if;
end if;
end loop;
end process;
end tb; |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : tb_floppy_stream.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.floppy_emu_pkg.all;
use work.flat_memory_model.all;
entity tb_floppy is
end tb_floppy;
architecture tb of tb_floppy is
signal clock : std_logic := '0';
signal clock_en : std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
signal reset : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal track : std_logic_vector(6 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal read_data : std_logic_vector(7 downto 0);
signal write_data : std_logic_vector(7 downto 0) := X"55";
---
signal mem_clock : std_logic := '0';
signal mem_req : std_logic;
signal mem_rwn : std_logic;
signal mem_rack : std_logic := '0';
signal mem_dack : std_logic := '0';
signal mem_addr : std_logic_vector(31 downto 0) := (others => '0');
signal mem_wdata : std_logic_vector(7 downto 0);
signal mem_rdata : std_logic_vector(7 downto 0) := X"00";
type t_integer_array is array (natural range <>) of integer;
constant rate_table : t_integer_array(0 to 63) := (
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
2, 2, 2, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 );
begin
clock <= not clock after 31.25 ns;
reset <= '1', '0' after 400 ns;
mem_clock <= not mem_clock after 100 ns; -- 5 Mhz
process
begin
wait until clock='1';
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
end process;
mut: entity work.floppy
port map (
drv_clock => clock,
drv_clock_en => clock_en, -- combi clk/cke that yields 4 MHz; eg. 16/4
drv_reset => reset,
motor_on => motor_on,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
soe => soe,
rate_ctrl => rate_ctrl,
write_data => write_data,
read_data => read_data,
track => track,
mem_clock => mem_clock,
mem_reset => reset,
mem_req => mem_req,
mem_rwn => mem_rwn,
mem_rack => mem_rack,
mem_dack => mem_dack,
mem_addr => mem_addr(19 downto 0), -- 1MB
mem_wdata => mem_wdata,
mem_rdata => mem_rdata );
test: process
begin
motor_on <= '1';
mode <= '1';
write_prot_n <= '1';
soe <= '1';
wait for 700 us;
wait until byte_ready='0';
wait for 10 us;
mode <= '0'; -- switch to write
for i in 0 to 255 loop
wait until byte_ready='0';
wait for 10 us;
write_data <= write_data + 1;
end loop;
wait until byte_ready='0';
mode <= '1';
wait;
end process;
move: process
begin
wait for 2 us;
for i in 0 to 100 loop
step <= step + 1;
wait for 2 us;
end loop;
wait for 2 us;
for i in 0 to 100 loop
step <= step - 1;
wait for 2 us;
end loop;
wait;
end process;
rate_ctrl <= conv_std_logic_vector(rate_table(conv_integer(track(6 downto 1))), 2);
memory: process
variable h : h_mem_object;
begin
register_mem_model("my memory", h);
for i in 0 to 15 loop
write_memory_32(h, conv_std_logic_vector(i*4, 32), X"FFFFFFFF");
end loop;
while true loop
wait until mem_clock='1';
if mem_req='1' then
wait until mem_clock='1';
wait until mem_clock='1';
wait until mem_clock='1';
if mem_rwn='0' then -- write
write_memory_8(h, mem_addr, mem_wdata);
mem_ack <= '1';
wait until mem_clock='1';
mem_ack <= '0';
else
mem_rdata <= read_memory_8(h, mem_addr);
mem_ack <= '1';
wait until mem_clock='1';
mem_ack <= '0';
mem_rdata <= X"00";
end if;
end if;
end loop;
end process;
end tb; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync_fifo is
generic (
g_depth : integer := 512; -- Actual depth.
g_data_width : integer := 32;
g_threshold : integer := 13;
g_storage : string := "auto"; -- can also be "blockram" or "distributed"
g_fall_through : boolean := false);
port (
clock : in std_logic;
reset : in std_logic;
rd_en : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(g_data_width-1 downto 0);
dout : out std_logic_vector(g_data_width-1 downto 0);
flush : in std_logic;
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
count : out integer range 0 to g_depth
);
end sync_fifo;
architecture rtl of sync_fifo is
subtype t_data_element is std_logic_vector(g_data_width-1 downto 0);
type t_data_array is array (0 to g_depth-1) of t_data_element;
signal data_array : t_data_array;
attribute ram_style : string;
attribute ram_style of data_array : signal is g_storage;
signal rd_data : std_logic_vector(g_data_width-1 downto 0);
signal din_reg : std_logic_vector(g_data_width-1 downto 0);
signal rd_inhibit : std_logic;
signal rd_inhibit_d : std_logic;
signal rd_en_flt : std_logic;
signal rd_enable : std_logic;
signal rd_pnt : integer range 0 to g_depth-1;
signal rd_pnt_next : integer range 0 to g_depth-1;
signal rd_index : integer range 0 to g_depth-1;
signal wr_en_flt : std_logic;
signal wr_pnt : integer range 0 to g_depth-1;
signal num_el : integer range 0 to g_depth;
begin
-- Check generic values (also for synthesis)
assert(g_threshold <= g_depth) report "Invalid parameter 'g_threshold'" severity failure;
-- Filter fifo read/write enables for full/empty conditions
rd_en_flt <= '1' when (num_el /= 0) and (rd_en='1') else '0';
wr_en_flt <= '1' when (num_el /= g_depth) and (wr_en='1') else '0';
-- Read enable depends on 'fall through' mode. In case fall through: prevent
-- read & write at same address (when fifo is empty)
rd_enable <= rd_en_flt when not(g_fall_through) else
'0' when rd_inhibit = '1' else
'1';
rd_inhibit <= '1' when rd_index = wr_pnt and wr_en_flt = '1' and g_fall_through else '0';
rd_index <= rd_pnt_next when g_fall_through and rd_en_flt = '1' and num_el /= 0 else rd_pnt;
-- FIFO output data. Combinatoric switch to fix simultaneous read/write issues.
dout <= din_reg when rd_inhibit_d = '1' else rd_data;
p_dpram: process(clock)
begin
if rising_edge(clock) then
if (wr_en_flt = '1') then
data_array(wr_pnt) <= din;
end if;
if (rd_enable = '1') then
rd_data <= data_array(rd_index);
end if;
end if;
end process;
rd_pnt_next <= 0 when (rd_pnt=g_depth-1) else rd_pnt + 1;
process(clock)
variable v_new_cnt : integer range 0 to g_depth;
begin
if (clock'event and clock='1') then
rd_inhibit_d <= rd_inhibit;
-- Modify read/write pointers
if (rd_en_flt='1') then
rd_pnt <= rd_pnt_next;
end if;
if (wr_en_flt='1') then
-- Registered din is needed for BlockRAM based 'fall through' FIFO
din_reg <= din;
if (wr_pnt=g_depth-1) then
wr_pnt <= 0;
else
wr_pnt <= wr_pnt + 1;
end if;
end if;
-- Update number of elements in fifo for next clock cycle
if (rd_en_flt = '1') and (wr_en_flt = '0') then
v_new_cnt := num_el - 1;
elsif (rd_en_flt = '0') and (wr_en_flt = '1') then
v_new_cnt := num_el + 1;
elsif (flush='1') then
v_new_cnt := 0;
else
v_new_cnt := num_el;
end if;
num_el <= v_new_cnt;
-- update (almost)full and empty indications
almost_full <= '0';
if (v_new_cnt >= g_threshold) then
almost_full <= '1';
end if;
empty <= '0';
if (v_new_cnt = 0) then
empty <= '1';
end if;
full <= '0';
if (v_new_cnt = g_depth) then
full <= '1';
end if;
if (flush='1') or (reset='1') then
rd_pnt <= 0;
wr_pnt <= 0;
num_el <= 0;
rd_inhibit_d <= '0';
if (reset='1') then
full <= '0';
empty <= '1';
almost_full <= '0';
end if;
end if;
end if;
end process;
count <= num_el;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync_fifo is
generic (
g_depth : integer := 512; -- Actual depth.
g_data_width : integer := 32;
g_threshold : integer := 13;
g_storage : string := "auto"; -- can also be "blockram" or "distributed"
g_fall_through : boolean := false);
port (
clock : in std_logic;
reset : in std_logic;
rd_en : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(g_data_width-1 downto 0);
dout : out std_logic_vector(g_data_width-1 downto 0);
flush : in std_logic;
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
count : out integer range 0 to g_depth
);
end sync_fifo;
architecture rtl of sync_fifo is
subtype t_data_element is std_logic_vector(g_data_width-1 downto 0);
type t_data_array is array (0 to g_depth-1) of t_data_element;
signal data_array : t_data_array;
attribute ram_style : string;
attribute ram_style of data_array : signal is g_storage;
signal rd_data : std_logic_vector(g_data_width-1 downto 0);
signal din_reg : std_logic_vector(g_data_width-1 downto 0);
signal rd_inhibit : std_logic;
signal rd_inhibit_d : std_logic;
signal rd_en_flt : std_logic;
signal rd_enable : std_logic;
signal rd_pnt : integer range 0 to g_depth-1;
signal rd_pnt_next : integer range 0 to g_depth-1;
signal rd_index : integer range 0 to g_depth-1;
signal wr_en_flt : std_logic;
signal wr_pnt : integer range 0 to g_depth-1;
signal num_el : integer range 0 to g_depth;
begin
-- Check generic values (also for synthesis)
assert(g_threshold <= g_depth) report "Invalid parameter 'g_threshold'" severity failure;
-- Filter fifo read/write enables for full/empty conditions
rd_en_flt <= '1' when (num_el /= 0) and (rd_en='1') else '0';
wr_en_flt <= '1' when (num_el /= g_depth) and (wr_en='1') else '0';
-- Read enable depends on 'fall through' mode. In case fall through: prevent
-- read & write at same address (when fifo is empty)
rd_enable <= rd_en_flt when not(g_fall_through) else
'0' when rd_inhibit = '1' else
'1';
rd_inhibit <= '1' when rd_index = wr_pnt and wr_en_flt = '1' and g_fall_through else '0';
rd_index <= rd_pnt_next when g_fall_through and rd_en_flt = '1' and num_el /= 0 else rd_pnt;
-- FIFO output data. Combinatoric switch to fix simultaneous read/write issues.
dout <= din_reg when rd_inhibit_d = '1' else rd_data;
p_dpram: process(clock)
begin
if rising_edge(clock) then
if (wr_en_flt = '1') then
data_array(wr_pnt) <= din;
end if;
if (rd_enable = '1') then
rd_data <= data_array(rd_index);
end if;
end if;
end process;
rd_pnt_next <= 0 when (rd_pnt=g_depth-1) else rd_pnt + 1;
process(clock)
variable v_new_cnt : integer range 0 to g_depth;
begin
if (clock'event and clock='1') then
rd_inhibit_d <= rd_inhibit;
-- Modify read/write pointers
if (rd_en_flt='1') then
rd_pnt <= rd_pnt_next;
end if;
if (wr_en_flt='1') then
-- Registered din is needed for BlockRAM based 'fall through' FIFO
din_reg <= din;
if (wr_pnt=g_depth-1) then
wr_pnt <= 0;
else
wr_pnt <= wr_pnt + 1;
end if;
end if;
-- Update number of elements in fifo for next clock cycle
if (rd_en_flt = '1') and (wr_en_flt = '0') then
v_new_cnt := num_el - 1;
elsif (rd_en_flt = '0') and (wr_en_flt = '1') then
v_new_cnt := num_el + 1;
elsif (flush='1') then
v_new_cnt := 0;
else
v_new_cnt := num_el;
end if;
num_el <= v_new_cnt;
-- update (almost)full and empty indications
almost_full <= '0';
if (v_new_cnt >= g_threshold) then
almost_full <= '1';
end if;
empty <= '0';
if (v_new_cnt = 0) then
empty <= '1';
end if;
full <= '0';
if (v_new_cnt = g_depth) then
full <= '1';
end if;
if (flush='1') or (reset='1') then
rd_pnt <= 0;
wr_pnt <= 0;
num_el <= 0;
rd_inhibit_d <= '0';
if (reset='1') then
full <= '0';
empty <= '1';
almost_full <= '0';
end if;
end if;
end if;
end process;
count <= num_el;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync_fifo is
generic (
g_depth : integer := 512; -- Actual depth.
g_data_width : integer := 32;
g_threshold : integer := 13;
g_storage : string := "auto"; -- can also be "blockram" or "distributed"
g_fall_through : boolean := false);
port (
clock : in std_logic;
reset : in std_logic;
rd_en : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(g_data_width-1 downto 0);
dout : out std_logic_vector(g_data_width-1 downto 0);
flush : in std_logic;
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
count : out integer range 0 to g_depth
);
end sync_fifo;
architecture rtl of sync_fifo is
subtype t_data_element is std_logic_vector(g_data_width-1 downto 0);
type t_data_array is array (0 to g_depth-1) of t_data_element;
signal data_array : t_data_array;
attribute ram_style : string;
attribute ram_style of data_array : signal is g_storage;
signal rd_data : std_logic_vector(g_data_width-1 downto 0);
signal din_reg : std_logic_vector(g_data_width-1 downto 0);
signal rd_inhibit : std_logic;
signal rd_inhibit_d : std_logic;
signal rd_en_flt : std_logic;
signal rd_enable : std_logic;
signal rd_pnt : integer range 0 to g_depth-1;
signal rd_pnt_next : integer range 0 to g_depth-1;
signal rd_index : integer range 0 to g_depth-1;
signal wr_en_flt : std_logic;
signal wr_pnt : integer range 0 to g_depth-1;
signal num_el : integer range 0 to g_depth;
begin
-- Check generic values (also for synthesis)
assert(g_threshold <= g_depth) report "Invalid parameter 'g_threshold'" severity failure;
-- Filter fifo read/write enables for full/empty conditions
rd_en_flt <= '1' when (num_el /= 0) and (rd_en='1') else '0';
wr_en_flt <= '1' when (num_el /= g_depth) and (wr_en='1') else '0';
-- Read enable depends on 'fall through' mode. In case fall through: prevent
-- read & write at same address (when fifo is empty)
rd_enable <= rd_en_flt when not(g_fall_through) else
'0' when rd_inhibit = '1' else
'1';
rd_inhibit <= '1' when rd_index = wr_pnt and wr_en_flt = '1' and g_fall_through else '0';
rd_index <= rd_pnt_next when g_fall_through and rd_en_flt = '1' and num_el /= 0 else rd_pnt;
-- FIFO output data. Combinatoric switch to fix simultaneous read/write issues.
dout <= din_reg when rd_inhibit_d = '1' else rd_data;
p_dpram: process(clock)
begin
if rising_edge(clock) then
if (wr_en_flt = '1') then
data_array(wr_pnt) <= din;
end if;
if (rd_enable = '1') then
rd_data <= data_array(rd_index);
end if;
end if;
end process;
rd_pnt_next <= 0 when (rd_pnt=g_depth-1) else rd_pnt + 1;
process(clock)
variable v_new_cnt : integer range 0 to g_depth;
begin
if (clock'event and clock='1') then
rd_inhibit_d <= rd_inhibit;
-- Modify read/write pointers
if (rd_en_flt='1') then
rd_pnt <= rd_pnt_next;
end if;
if (wr_en_flt='1') then
-- Registered din is needed for BlockRAM based 'fall through' FIFO
din_reg <= din;
if (wr_pnt=g_depth-1) then
wr_pnt <= 0;
else
wr_pnt <= wr_pnt + 1;
end if;
end if;
-- Update number of elements in fifo for next clock cycle
if (rd_en_flt = '1') and (wr_en_flt = '0') then
v_new_cnt := num_el - 1;
elsif (rd_en_flt = '0') and (wr_en_flt = '1') then
v_new_cnt := num_el + 1;
elsif (flush='1') then
v_new_cnt := 0;
else
v_new_cnt := num_el;
end if;
num_el <= v_new_cnt;
-- update (almost)full and empty indications
almost_full <= '0';
if (v_new_cnt >= g_threshold) then
almost_full <= '1';
end if;
empty <= '0';
if (v_new_cnt = 0) then
empty <= '1';
end if;
full <= '0';
if (v_new_cnt = g_depth) then
full <= '1';
end if;
if (flush='1') or (reset='1') then
rd_pnt <= 0;
wr_pnt <= 0;
num_el <= 0;
rd_inhibit_d <= '0';
if (reset='1') then
full <= '0';
empty <= '1';
almost_full <= '0';
end if;
end if;
end if;
end process;
count <= num_el;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync_fifo is
generic (
g_depth : integer := 512; -- Actual depth.
g_data_width : integer := 32;
g_threshold : integer := 13;
g_storage : string := "auto"; -- can also be "blockram" or "distributed"
g_fall_through : boolean := false);
port (
clock : in std_logic;
reset : in std_logic;
rd_en : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(g_data_width-1 downto 0);
dout : out std_logic_vector(g_data_width-1 downto 0);
flush : in std_logic;
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
count : out integer range 0 to g_depth
);
end sync_fifo;
architecture rtl of sync_fifo is
subtype t_data_element is std_logic_vector(g_data_width-1 downto 0);
type t_data_array is array (0 to g_depth-1) of t_data_element;
signal data_array : t_data_array;
attribute ram_style : string;
attribute ram_style of data_array : signal is g_storage;
signal rd_data : std_logic_vector(g_data_width-1 downto 0);
signal din_reg : std_logic_vector(g_data_width-1 downto 0);
signal rd_inhibit : std_logic;
signal rd_inhibit_d : std_logic;
signal rd_en_flt : std_logic;
signal rd_enable : std_logic;
signal rd_pnt : integer range 0 to g_depth-1;
signal rd_pnt_next : integer range 0 to g_depth-1;
signal rd_index : integer range 0 to g_depth-1;
signal wr_en_flt : std_logic;
signal wr_pnt : integer range 0 to g_depth-1;
signal num_el : integer range 0 to g_depth;
begin
-- Check generic values (also for synthesis)
assert(g_threshold <= g_depth) report "Invalid parameter 'g_threshold'" severity failure;
-- Filter fifo read/write enables for full/empty conditions
rd_en_flt <= '1' when (num_el /= 0) and (rd_en='1') else '0';
wr_en_flt <= '1' when (num_el /= g_depth) and (wr_en='1') else '0';
-- Read enable depends on 'fall through' mode. In case fall through: prevent
-- read & write at same address (when fifo is empty)
rd_enable <= rd_en_flt when not(g_fall_through) else
'0' when rd_inhibit = '1' else
'1';
rd_inhibit <= '1' when rd_index = wr_pnt and wr_en_flt = '1' and g_fall_through else '0';
rd_index <= rd_pnt_next when g_fall_through and rd_en_flt = '1' and num_el /= 0 else rd_pnt;
-- FIFO output data. Combinatoric switch to fix simultaneous read/write issues.
dout <= din_reg when rd_inhibit_d = '1' else rd_data;
p_dpram: process(clock)
begin
if rising_edge(clock) then
if (wr_en_flt = '1') then
data_array(wr_pnt) <= din;
end if;
if (rd_enable = '1') then
rd_data <= data_array(rd_index);
end if;
end if;
end process;
rd_pnt_next <= 0 when (rd_pnt=g_depth-1) else rd_pnt + 1;
process(clock)
variable v_new_cnt : integer range 0 to g_depth;
begin
if (clock'event and clock='1') then
rd_inhibit_d <= rd_inhibit;
-- Modify read/write pointers
if (rd_en_flt='1') then
rd_pnt <= rd_pnt_next;
end if;
if (wr_en_flt='1') then
-- Registered din is needed for BlockRAM based 'fall through' FIFO
din_reg <= din;
if (wr_pnt=g_depth-1) then
wr_pnt <= 0;
else
wr_pnt <= wr_pnt + 1;
end if;
end if;
-- Update number of elements in fifo for next clock cycle
if (rd_en_flt = '1') and (wr_en_flt = '0') then
v_new_cnt := num_el - 1;
elsif (rd_en_flt = '0') and (wr_en_flt = '1') then
v_new_cnt := num_el + 1;
elsif (flush='1') then
v_new_cnt := 0;
else
v_new_cnt := num_el;
end if;
num_el <= v_new_cnt;
-- update (almost)full and empty indications
almost_full <= '0';
if (v_new_cnt >= g_threshold) then
almost_full <= '1';
end if;
empty <= '0';
if (v_new_cnt = 0) then
empty <= '1';
end if;
full <= '0';
if (v_new_cnt = g_depth) then
full <= '1';
end if;
if (flush='1') or (reset='1') then
rd_pnt <= 0;
wr_pnt <= 0;
num_el <= 0;
rd_inhibit_d <= '0';
if (reset='1') then
full <= '0';
empty <= '1';
almost_full <= '0';
end if;
end if;
end if;
end process;
count <= num_el;
end rtl;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ae
--
-- Generated
-- by: wig
-- on: Tue Jun 27 05:23:07 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_MIXED ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ae-rtl-a.vhd,v 1.5 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: ent_ae-rtl-a.vhd,v $
-- Revision 1.5 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ae
--
architecture rtl of ent_ae is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- NEED RESULT: ARCH00354.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00354.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00354.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00354: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00354: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00354: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00354: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00354: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00354: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00354
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00354(ARCH00354)
-- ENT00354_Test_Bench(ARCH00354_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00354 is
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00354 ;
--
--
architecture ARCH00354 of ENT00354 is
subtype chk_time_type is Time ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
--
begin
CHG1 :
process ( s_st_rec1 )
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1.f2 <= transport
-- c_st_rec1_2.f2 after 10 ns,
-- c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00354.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1.f2 <= transport
-- c_st_rec1_2.f2 after 10 ns ,
-- c_st_rec1_1.f2 after 20 ns ,
-- c_st_rec1_2.f2 after 30 ns ,
-- c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1.f2 <= transport
-- c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00354" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00354" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00354" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns
when st_rec1_select = 1 else
--
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns
when st_rec1_select = 2 else
--
c_st_rec1_1.f2 after 5 ns ;
--
CHG2 :
process ( s_st_rec2 )
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2.f2 <= transport
-- c_st_rec2_2.f2 after 10 ns,
-- c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00354.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2.f2 <= transport
-- c_st_rec2_2.f2 after 10 ns ,
-- c_st_rec2_1.f2 after 20 ns ,
-- c_st_rec2_2.f2 after 30 ns ,
-- c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2.f2 <= transport
-- c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00354" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00354" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00354" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns
when st_rec2_select = 1 else
--
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns
when st_rec2_select = 2 else
--
c_st_rec2_1.f2 after 5 ns ;
--
CHG3 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2 <= transport
-- c_st_rec3_2.f2 after 10 ns,
-- c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00354.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f2 <= transport
-- c_st_rec3_2.f2 after 10 ns ,
-- c_st_rec3_1.f2 after 20 ns ,
-- c_st_rec3_2.f2 after 30 ns ,
-- c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f2 <= transport
-- c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00354" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00354" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00354" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f2 after 5 ns ;
--
end ARCH00354 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00354_Test_Bench is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00354_Test_Bench ;
--
--
architecture ARCH00354_Test_Bench of ENT00354_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00354 ( ARCH00354 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1
, s_st_rec2
, s_st_rec3
)
;
end block L1 ;
end ARCH00354_Test_Bench ;
|
component wasca is
port (
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- ba
external_sdram_controller_wire_cas_n : out std_logic; -- cas_n
external_sdram_controller_wire_cke : out std_logic; -- cke
external_sdram_controller_wire_cs_n : out std_logic; -- cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
external_sdram_controller_wire_ras_n : out std_logic; -- ras_n
external_sdram_controller_wire_we_n : out std_logic; -- we_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := 'X'; -- read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- interrupt
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
sega_saturn_abus_slave_0_abus_direction : out std_logic; -- direction
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := 'X'; -- saturn_reset
spi_sd_card_MISO : in std_logic := 'X'; -- MISO
spi_sd_card_MOSI : out std_logic; -- MOSI
spi_sd_card_SCLK : out std_logic; -- SCLK
spi_sd_card_SS_n : out std_logic; -- SS_n
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic; -- txd
spi_stm32_MISO : out std_logic; -- MISO
spi_stm32_MOSI : in std_logic := 'X'; -- MOSI
spi_stm32_SCLK : in std_logic := 'X'; -- SCLK
spi_stm32_SS_n : in std_logic := 'X'; -- SS_n
audio_out_BCLK : in std_logic := 'X'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := 'X' -- DACLRCK
);
end component wasca;
u0 : component wasca
port map (
altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export => CONNECTED_TO_altpll_0_phasedone_conduit_export, -- altpll_0_phasedone_conduit.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
external_sdram_controller_wire_addr => CONNECTED_TO_external_sdram_controller_wire_addr, -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => CONNECTED_TO_external_sdram_controller_wire_ba, -- .ba
external_sdram_controller_wire_cas_n => CONNECTED_TO_external_sdram_controller_wire_cas_n, -- .cas_n
external_sdram_controller_wire_cke => CONNECTED_TO_external_sdram_controller_wire_cke, -- .cke
external_sdram_controller_wire_cs_n => CONNECTED_TO_external_sdram_controller_wire_cs_n, -- .cs_n
external_sdram_controller_wire_dq => CONNECTED_TO_external_sdram_controller_wire_dq, -- .dq
external_sdram_controller_wire_dqm => CONNECTED_TO_external_sdram_controller_wire_dqm, -- .dqm
external_sdram_controller_wire_ras_n => CONNECTED_TO_external_sdram_controller_wire_ras_n, -- .ras_n
external_sdram_controller_wire_we_n => CONNECTED_TO_external_sdram_controller_wire_we_n, -- .we_n
sega_saturn_abus_slave_0_abus_address => CONNECTED_TO_sega_saturn_abus_slave_0_abus_address, -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_chipselect => CONNECTED_TO_sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect
sega_saturn_abus_slave_0_abus_read => CONNECTED_TO_sega_saturn_abus_slave_0_abus_read, -- .read
sega_saturn_abus_slave_0_abus_write => CONNECTED_TO_sega_saturn_abus_slave_0_abus_write, -- .write
sega_saturn_abus_slave_0_abus_waitrequest => CONNECTED_TO_sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt => CONNECTED_TO_sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt
sega_saturn_abus_slave_0_abus_addressdata => CONNECTED_TO_sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata
sega_saturn_abus_slave_0_abus_direction => CONNECTED_TO_sega_saturn_abus_slave_0_abus_direction, -- .direction
sega_saturn_abus_slave_0_abus_muxing => CONNECTED_TO_sega_saturn_abus_slave_0_abus_muxing, -- .muxing
sega_saturn_abus_slave_0_abus_disableout => CONNECTED_TO_sega_saturn_abus_slave_0_abus_disableout, -- .disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset => CONNECTED_TO_sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset
spi_sd_card_MISO => CONNECTED_TO_spi_sd_card_MISO, -- spi_sd_card.MISO
spi_sd_card_MOSI => CONNECTED_TO_spi_sd_card_MOSI, -- .MOSI
spi_sd_card_SCLK => CONNECTED_TO_spi_sd_card_SCLK, -- .SCLK
spi_sd_card_SS_n => CONNECTED_TO_spi_sd_card_SS_n, -- .SS_n
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd, -- .txd
spi_stm32_MISO => CONNECTED_TO_spi_stm32_MISO, -- spi_stm32.MISO
spi_stm32_MOSI => CONNECTED_TO_spi_stm32_MOSI, -- .MOSI
spi_stm32_SCLK => CONNECTED_TO_spi_stm32_SCLK, -- .SCLK
spi_stm32_SS_n => CONNECTED_TO_spi_stm32_SS_n, -- .SS_n
audio_out_BCLK => CONNECTED_TO_audio_out_BCLK, -- audio_out.BCLK
audio_out_DACDAT => CONNECTED_TO_audio_out_DACDAT, -- .DACDAT
audio_out_DACLRCK => CONNECTED_TO_audio_out_DACLRCK -- .DACLRCK
);
|
entity top is
generic (width : natural := 8);
end top;
architecture behav of top is
type arr1 is array (1 to width) of natural;
type rec1 is record
i : integer;
a : arr1;
c : character;
end record;
type arr2 is array (1 to width) of rec1;
type arr3 is array (natural range <>) of arr2;
function resolv (vec : arr3) return arr2
is
begin
return vec (vec'left);
end resolv;
signal s : resolv arr2;
begin
end;
|
entity top is
generic (width : natural := 8);
end top;
architecture behav of top is
type arr1 is array (1 to width) of natural;
type rec1 is record
i : integer;
a : arr1;
c : character;
end record;
type arr2 is array (1 to width) of rec1;
type arr3 is array (natural range <>) of arr2;
function resolv (vec : arr3) return arr2
is
begin
return vec (vec'left);
end resolv;
signal s : resolv arr2;
begin
end;
|
entity top is
generic (width : natural := 8);
end top;
architecture behav of top is
type arr1 is array (1 to width) of natural;
type rec1 is record
i : integer;
a : arr1;
c : character;
end record;
type arr2 is array (1 to width) of rec1;
type arr3 is array (natural range <>) of arr2;
function resolv (vec : arr3) return arr2
is
begin
return vec (vec'left);
end resolv;
signal s : resolv arr2;
begin
end;
|
-- Altera Microperipheral Reference Design Version 0802
--------------------------------------------------------
--
-- FILE NAME : portbin.vhd
-- PROJECT : Altera A8255 Peripheral Interface Adapter
-- PURPOSE : This file contains the entity and architecture
-- for the Port B Input Register of the A8255 design.
--
--Copyright © 2002 Altera Corporation. All rights reserved. Altera products are
--protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
--other intellectual property laws.
--This reference design file, and your use thereof, is subject to and governed by
--the terms and conditions of the applicable Altera Reference Design License Agreement.
--By using this reference design file, you indicate your acceptance of such terms and
--conditions between you and Altera Corporation. In the event that you do not agree with
--such terms and conditions, you may not use the reference design file. Please promptly
--destroy any copies you have made.
--This reference design file being provided on an "as-is" basis and as an accommodation
--and therefore all warranties, representations or guarantees of any kind
--(whether express, implied or statutory) including, without limitation, warranties of
--merchantability, non-infringement, or fitness for a particular purpose, are
--specifically disclaimed. By making this reference design file available, Altera
--expressly does not recommend, suggest or require that this reference design file be
--used in combination with any other product not provided by Altera.
--
--------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY portbin IS
PORT(
PBIN : IN std_logic_vector (7 DOWNTO 0);
RESET : IN std_logic;
CLK : IN std_logic;
PortBInLd : IN std_logic;
PortBInReg : OUT std_logic_vector (7 DOWNTO 0)
);
END portbin;
ARCHITECTURE rtl OF portbin IS
SIGNAL PortBInRegQ : std_logic_vector(7 DOWNTO 0);
SIGNAL PortBInRegD : std_logic_vector(7 DOWNTO 0);
BEGIN
PortBInReg <= PortBInRegQ;
PortBInRegProc: PROCESS ( PortBInLd, PBIN, PortBInRegQ )
BEGIN
IF ( PortBInLd = '0') THEN
PortBInRegD <= PBIN (7 DOWNTO 0);
ELSE
PortBInRegD <= PortBInRegQ;
END IF;
END PROCESS;
PortBInRegSynchProc: PROCESS ( RESET, CLK )
BEGIN
IF (RESET = '1') THEN
PortBInRegQ <= "00000000";
ELSIF ( CLK'EVENT and CLK = '1') THEN
PortBInRegQ <= PortBInRegD;
END IF;
END PROCESS;
END rtl;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tcp_engine_seq_generator - Behavioral
--
-- Description: A very bad random SYN number generator
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_engine_seq_generator is
Port ( clk : in STD_LOGIC;
seq : out STD_LOGIC_VECTOR (31 downto 0));
end tcp_engine_seq_generator;
architecture Behavioral of tcp_engine_seq_generator is
signal state : unsigned (31 downto 0) := (others => '0');
begin
seq <= std_logic_vector(state);
process(clk)
begin
if rising_edge(clk) then
state <= state+1;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : RLE --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : RLE.VHD --
-- Created : Wed Mar 04 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Run Length Encoder --
-- Baseline Entropy Coding --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
library work;
use work.JPEG_PKG.all;
entity rle is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
start_pb : in std_logic;
sof : in std_logic;
rle_sm_settings : in T_SM_SETTINGS;
runlength : out STD_LOGIC_VECTOR(3 downto 0);
size : out STD_LOGIC_VECTOR(3 downto 0);
amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out STD_LOGIC;
rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end rle;
architecture rtl of rle is
constant SIZE_REG_C : INTEGER := 4;
constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');
signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0);
signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0);
signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0);
signal prev_dc_reg_3 : SIGNED(RAMDATA_W-1 downto 0);
signal acc_reg : SIGNED(RAMDATA_W downto 0);
signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0);
signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0);
signal runlength_reg : UNSIGNED(3 downto 0);
signal dovalid_reg : STD_LOGIC;
signal zero_cnt : unsigned(5 downto 0);
signal wr_cnt_d1 : unsigned(5 downto 0);
signal wr_cnt : unsigned(5 downto 0);
signal rd_cnt : unsigned(5 downto 0);
signal rd_en : std_logic;
signal divalid : STD_LOGIC;
signal divalid_en : std_logic;
signal zrl_proc : std_logic;
signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
begin
size <= STD_LOGIC_VECTOR(size_reg);
amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
-------------------------------------------
-- MAIN PROCESSING
-------------------------------------------
process(clk,rst)
begin
if rst = '1' then
wr_cnt_d1 <= (others => '0');
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
dovalid_reg <= '0';
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
runlength <= (others => '0');
dovalid <= '0';
zero_cnt <= (others => '0');
zrl_proc <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
divalid_en <= '0';
elsif clk = '1' and clk'event then
dovalid_reg <= '0';
runlength_reg <= (others => '0');
wr_cnt_d1 <= wr_cnt;
runlength <= std_logic_vector(runlength_reg);
dovalid <= dovalid_reg;
divalid <= rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
divalid_en <= '1';
end if;
if divalid = '1' and wr_cnt = 63 then
divalid_en <= '0';
end if;
-- input read enable
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
-- input data valid
if divalid = '1' then
wr_cnt <= wr_cnt + 1;
-- first DCT coefficient received, DC data
if wr_cnt = 0 then
-- differental coding of DC data per component
case rle_sm_settings.cmp_idx is
when "000" | "001" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
prev_dc_reg_0 <= SIGNED(di);
when "010" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
prev_dc_reg_1 <= SIGNED(di);
when "011" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
prev_dc_reg_2 <= SIGNED(di);
when others =>
null;
end case;
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- AC coefficient
else
-- zero AC
if signed(di) = 0 then
-- EOB
if wr_cnt = 63 then
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- no EOB
else
zero_cnt <= zero_cnt + 1;
end if;
-- non-zero AC
else
-- normal RLE case
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
zero_cnt <= (others => '0');
dovalid_reg <= '1';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
-- stall input until ZRL is handled
zrl_proc <= '1';
zrl_di <= di;
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
end if;
end if;
-- ZRL processing
if zrl_proc = '1' then
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
if signed(zrl_di) = 0 then
zero_cnt <= to_unsigned(1,zero_cnt'length);
else
zero_cnt <= (others => '0');
end if;
dovalid_reg <= '1';
divalid <= divalid_en;
-- continue input handling
zrl_proc <= '0';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
-- start of 8x8 block processing
if start_pb = '1' then
zero_cnt <= (others => '0');
wr_cnt <= (others => '0');
end if;
if sof = '1' then
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
end if;
end if;
end process;
-------------------------------------------------------------------
-- Entropy Coder
-------------------------------------------------------------------
p_entropy_coder : process(CLK, RST)
begin
if RST = '1' then
ampli_vli_reg <= (others => '0');
size_reg <= (others => '0');
elsif CLK'event and CLK = '1' then
-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
-- positive input
if acc_reg >= 0 then
ampli_vli_reg <= acc_reg;
else
ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
end if;
-- compute Symbol-1 Size
if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- compute Symbol-1 Size
-- positive input
if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- DC coefficient amplitude=0 case OR EOB
if acc_reg = 0 then
size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : RLE --
-- Design : MDCT CORE --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : RLE.VHD --
-- Created : Wed Mar 04 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Run Length Encoder --
-- Baseline Entropy Coding --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
library work;
use work.JPEG_PKG.all;
entity rle is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
start_pb : in std_logic;
sof : in std_logic;
rle_sm_settings : in T_SM_SETTINGS;
runlength : out STD_LOGIC_VECTOR(3 downto 0);
size : out STD_LOGIC_VECTOR(3 downto 0);
amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dovalid : out STD_LOGIC;
rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
);
end rle;
architecture rtl of rle is
constant SIZE_REG_C : INTEGER := 4;
constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');
signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0);
signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0);
signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0);
signal prev_dc_reg_3 : SIGNED(RAMDATA_W-1 downto 0);
signal acc_reg : SIGNED(RAMDATA_W downto 0);
signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0);
signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0);
signal runlength_reg : UNSIGNED(3 downto 0);
signal dovalid_reg : STD_LOGIC;
signal zero_cnt : unsigned(5 downto 0);
signal wr_cnt_d1 : unsigned(5 downto 0);
signal wr_cnt : unsigned(5 downto 0);
signal rd_cnt : unsigned(5 downto 0);
signal rd_en : std_logic;
signal divalid : STD_LOGIC;
signal divalid_en : std_logic;
signal zrl_proc : std_logic;
signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
begin
size <= STD_LOGIC_VECTOR(size_reg);
amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
-------------------------------------------
-- MAIN PROCESSING
-------------------------------------------
process(clk,rst)
begin
if rst = '1' then
wr_cnt_d1 <= (others => '0');
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
dovalid_reg <= '0';
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
runlength <= (others => '0');
dovalid <= '0';
zero_cnt <= (others => '0');
zrl_proc <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
divalid_en <= '0';
elsif clk = '1' and clk'event then
dovalid_reg <= '0';
runlength_reg <= (others => '0');
wr_cnt_d1 <= wr_cnt;
runlength <= std_logic_vector(runlength_reg);
dovalid <= dovalid_reg;
divalid <= rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
divalid_en <= '1';
end if;
if divalid = '1' and wr_cnt = 63 then
divalid_en <= '0';
end if;
-- input read enable
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
-- input data valid
if divalid = '1' then
wr_cnt <= wr_cnt + 1;
-- first DCT coefficient received, DC data
if wr_cnt = 0 then
-- differental coding of DC data per component
case rle_sm_settings.cmp_idx is
when "000" | "001" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
prev_dc_reg_0 <= SIGNED(di);
when "010" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
prev_dc_reg_1 <= SIGNED(di);
when "011" =>
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
prev_dc_reg_2 <= SIGNED(di);
when others =>
null;
end case;
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- AC coefficient
else
-- zero AC
if signed(di) = 0 then
-- EOB
if wr_cnt = 63 then
acc_reg <= (others => '0');
runlength_reg <= (others => '0');
dovalid_reg <= '1';
-- no EOB
else
zero_cnt <= zero_cnt + 1;
end if;
-- non-zero AC
else
-- normal RLE case
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
zero_cnt <= (others => '0');
dovalid_reg <= '1';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
-- stall input until ZRL is handled
zrl_proc <= '1';
zrl_di <= di;
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
end if;
end if;
-- ZRL processing
if zrl_proc = '1' then
if zero_cnt <= 15 then
acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
runlength_reg <= zero_cnt(3 downto 0);
if signed(zrl_di) = 0 then
zero_cnt <= to_unsigned(1,zero_cnt'length);
else
zero_cnt <= (others => '0');
end if;
dovalid_reg <= '1';
divalid <= divalid_en;
-- continue input handling
zrl_proc <= '0';
-- zero_cnt > 15
else
-- generate ZRL
acc_reg <= (others => '0');
runlength_reg <= X"F";
zero_cnt <= zero_cnt - 16;
dovalid_reg <= '1';
divalid <= '0';
rd_cnt <= rd_cnt;
end if;
end if;
-- start of 8x8 block processing
if start_pb = '1' then
zero_cnt <= (others => '0');
wr_cnt <= (others => '0');
end if;
if sof = '1' then
prev_dc_reg_0 <= (others => '0');
prev_dc_reg_1 <= (others => '0');
prev_dc_reg_2 <= (others => '0');
prev_dc_reg_3 <= (others => '0');
end if;
end if;
end process;
-------------------------------------------------------------------
-- Entropy Coder
-------------------------------------------------------------------
p_entropy_coder : process(CLK, RST)
begin
if RST = '1' then
ampli_vli_reg <= (others => '0');
size_reg <= (others => '0');
elsif CLK'event and CLK = '1' then
-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
-- positive input
if acc_reg >= 0 then
ampli_vli_reg <= acc_reg;
else
ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
end if;
-- compute Symbol-1 Size
if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- compute Symbol-1 Size
-- positive input
if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
end if;
-- DC coefficient amplitude=0 case OR EOB
if acc_reg = 0 then
size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
end if;
end if;
end process;
end rtl;
--------------------------------------------------------------------------------
|
-- file: clk_wiz_v3_6_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clk_wiz_v3_6_tb is
end clk_wiz_v3_6_tb;
architecture test of clk_wiz_v3_6_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 8.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
signal period1 : time := 0 ps;
constant ref_period1_clkin1 : time := (8.000*1*3.125/8.000)*1000 ps;
signal prev_rise1 : time := 0 ps;
component clk_wiz_v3_6_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simfreqprint(period1, 1);
assert (((period1 - ref_period1_clkin1) >= -100 ps) and ((period1 - ref_period1_clkin1) <= 100 ps)) report "ERROR: Freq of CLK_OUT(1) is not correct" severity note;
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clk_wiz_v3_6_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
-- Freq Check
process(CLK_OUT(1))
begin
if (CLK_OUT(1)'event and CLK_OUT(1) = '1') then
if (prev_rise1 /= 0 ps) then
period1 <= NOW - prev_rise1;
end if;
prev_rise1 <= NOW;
end if;
end process;
end test;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLROM_3_6.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_6
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLROM_3_6
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.ifft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_6_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_6_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_6_vld : OUT std_logic
);
END TWDLROM_3_6;
ARCHITECTURE rtl OF TWDLROM_3_6 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_6_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_6_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#1#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#1#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#1#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_6_re_tmp <= twdlIn_re;
twdl_3_6_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_6_re <= std_logic_vector(twdl_3_6_re_tmp);
twdl_3_6_im <= std_logic_vector(twdl_3_6_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_6_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_6_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: Uart
-- Date:2011-11-26
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Uart is
port (
reset : in std_logic;
clk : in std_logic;
---------- UART ---------------
RX : in std_logic;
TX : out std_logic;
---------- gpib ---------------
data_out : out std_logic_vector(7 downto 0);
data_out_ready : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_in_ready : in std_logic;
ready_to_send : out std_logic
);
end Uart;
architecture arch of Uart is
constant BIT_TIME : integer :=
-- 115200
--572
-- 921600
72
;
constant HALF_BIT_TIME : integer := BIT_TIME / 2;
type RX_STATES is (
ST_RX_IDLE,
ST_RX_HALF_START,
ST_RX_RECEIVE_BITS,
ST_RX_RECEIVE_STOP_BIT
);
type TX_STATES is (
ST_TX_IDLE,
ST_TX_SEND_BITS,
ST_TX_SEND_STOP_BIT
);
signal syncRX : std_logic;
signal rxState : RX_STATES;
signal lastRx : std_logic;
signal rxTimeCounter : integer range 0 to BIT_TIME;
signal rxBitCounter : integer range 0 to 7;
signal innerBuf : std_logic_vector(6 downto 0);
signal txState : TX_STATES;
signal lastData_in_ready : std_logic;
signal txTimeCounter : integer range 0 to BIT_TIME;
signal txBitCounter : integer range 0 to 8;
begin
-- RX synchronizer
process(clk, RX) begin
if rising_edge(clk) then
syncRX <= RX;
end if;
end process;
-- RX
process(reset, clk, syncRX) begin
if reset = '1' then
rxState <= ST_RX_IDLE;
lastRx <= syncRX;
data_out_ready <= '0';
elsif rising_edge(clk) then
lastRx <= syncRX;
if rxTimeCounter < BIT_TIME then
rxTimeCounter <= rxTimeCounter + 1;
end if;
case rxState is
when ST_RX_IDLE =>
if lastRx /= syncRX and syncRX = '0' then
rxTimeCounter <= 1;
rxState <= ST_RX_HALF_START;
end if;
when ST_RX_HALF_START =>
if rxTimeCounter >= HALF_BIT_TIME then
rxBitCounter <= 0;
rxTimeCounter <= 1;
rxState <= ST_RX_RECEIVE_BITS;
end if;
when ST_RX_RECEIVE_BITS =>
if rxTimeCounter >= BIT_TIME then
if rxBitCounter < 7 then
innerBuf(rxBitCounter) <= syncRX;
rxBitCounter <= rxBitCounter + 1;
rxTimeCounter <= 1;
elsif rxBitCounter = 7 then
data_out(7) <= syncRX;
data_out(6 downto 0) <= innerBuf;
data_out_ready <= '0';
rxTimeCounter <= 1;
rxState <= ST_RX_RECEIVE_STOP_BIT;
end if;
end if;
when ST_RX_RECEIVE_STOP_BIT =>
if rxTimeCounter >= BIT_TIME then
data_out_ready <= '1';
rxState <= ST_RX_IDLE;
end if;
when others =>
rxState <= ST_RX_IDLE;
end case;
end if;
end process;
-- TX
process(reset, clk, data_in_ready) begin
if reset = '1' then
TX <= '1';
ready_to_send <= '1';
txState <= ST_TX_IDLE;
elsif rising_edge(clk) then
lastData_in_ready <= data_in_ready;
if txTimeCounter < BIT_TIME then
txTimeCounter <= txTimeCounter + 1;
end if;
case txState is
when ST_TX_IDLE =>
if lastData_in_ready /= data_in_ready and
data_in_ready = '1' then
TX <= '0';
txTimeCounter <= 1;
txBitCounter <= 0;
ready_to_send <= '0';
txState <= ST_TX_SEND_BITS;
end if;
when ST_TX_SEND_BITS =>
if txTimeCounter >= BIT_TIME then
if txBitCounter < 8 then
TX <= data_in(txBitCounter);
txBitCounter <= txBitCounter + 1;
txTimeCounter <= 1;
elsif txBitCounter = 8 then
TX <= '1';
txTimeCounter <= 1;
txState <= ST_TX_SEND_STOP_BIT;
end if;
end if;
when ST_TX_SEND_STOP_BIT =>
if txTimeCounter >= BIT_TIME then
ready_to_send <= '1';
txState <= ST_TX_IDLE;
end if;
when others =>
txState <= ST_TX_IDLE;
end case;
end if;
end process;
end arch;
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_salt is
end entity alt_dspbuilder_testbench_salt;
architecture rtl of alt_dspbuilder_testbench_salt is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_salt is
end entity alt_dspbuilder_testbench_salt;
architecture rtl of alt_dspbuilder_testbench_salt is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_salt is
end entity alt_dspbuilder_testbench_salt;
architecture rtl of alt_dspbuilder_testbench_salt is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_salt is
end entity alt_dspbuilder_testbench_salt;
architecture rtl of alt_dspbuilder_testbench_salt is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_salt is
end entity alt_dspbuilder_testbench_salt;
architecture rtl of alt_dspbuilder_testbench_salt is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_salt is
end entity alt_dspbuilder_testbench_salt;
architecture rtl of alt_dspbuilder_testbench_salt is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_salt is
end entity alt_dspbuilder_testbench_salt;
architecture rtl of alt_dspbuilder_testbench_salt is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_salt is
end entity alt_dspbuilder_testbench_salt;
architecture rtl of alt_dspbuilder_testbench_salt is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_salt is
end entity alt_dspbuilder_testbench_salt;
architecture rtl of alt_dspbuilder_testbench_salt is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_salt is
end entity alt_dspbuilder_testbench_salt;
architecture rtl of alt_dspbuilder_testbench_salt is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY genAdderUnsgndSat IS
GENERIC(
value_len : integer
);
PORT(
value0 : IN std_logic_vector(value_len-1 downto 0);
value1 : IN std_logic_vector(value_len-1 downto 0);
output : OUT std_logic_vector(value_len-1 downto 0)
);
END genAdderUnsgndSat;
ARCHITECTURE behavior OF genAdderUnsgndSat IS
COMPONENT genAdder
GENERIC(
value_len : integer
);
PORT(
value0 : IN std_logic_vector(value_len-1 downto 0);
value1 : IN std_logic_vector(value_len-1 downto 0);
output : OUT std_logic_vector(value_len-1 downto 0);
overflow : OUT std_logic
);
END COMPONENT;
SIGNAL result : std_logic_vector(value_len-1 downto 0);
SIGNAL overflow : std_logic;
BEGIN
add : genAdder GENERIC MAP (value_len) PORT MAP (value0, value1, result, overflow);
WITH overflow SELECT
output <= result WHEN '0',
(OTHERS => '1') WHEN '1',
result WHEN OTHERS;
END behavior;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity filesystem_encrypbkb_ram is
generic(
mem_type : string := "block";
dwidth : integer := 128;
awidth : integer := 5;
mem_size : integer := 32
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
d1 : in std_logic_vector(dwidth-1 downto 0);
we1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of filesystem_encrypbkb_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
if (we1 = '1') then
ram(CONV_INTEGER(addr1_tmp)) := d1;
end if;
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity filesystem_encrypbkb is
generic (
DataWidth : INTEGER := 128;
AddressRange : INTEGER := 32;
AddressWidth : INTEGER := 5);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of filesystem_encrypbkb is
component filesystem_encrypbkb_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR;
we1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
filesystem_encrypbkb_ram_U : component filesystem_encrypbkb_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
d1 => d1,
we1 => we1,
q1 => q1);
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package leon3 is
constant LEON3_VERSION : integer := 3;
type l3_irq_in_type is record
irl : std_logic_vector(3 downto 0);
rst : std_ulogic;
run : std_ulogic;
rstvec : std_logic_vector(31 downto 12);
iact : std_ulogic;
index : std_logic_vector(3 downto 0);
hrdrst : std_ulogic;
end record;
type l3_irq_out_type is record
intack : std_ulogic;
irl : std_logic_vector(3 downto 0);
pwd : std_ulogic;
fpen : std_ulogic;
idle : std_ulogic;
end record;
type l3_debug_in_type is record
dsuen : std_ulogic; -- DSU enable
denable : std_ulogic; -- diagnostic register access enable
dbreak : std_ulogic; -- debug break-in
step : std_ulogic; -- single step
halt : std_ulogic; -- halt processor
reset : std_ulogic; -- reset processor
dwrite : std_ulogic; -- read/write
daddr : std_logic_vector(23 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
btrapa : std_ulogic; -- break on IU trap
btrape : std_ulogic; -- break on IU trap
berror : std_ulogic; -- break on IU error mode
bwatch : std_ulogic; -- break on IU watchpoint
bsoft : std_ulogic; -- break on software breakpoint (TA 1)
tenable : std_ulogic;
timer : std_logic_vector(30 downto 0); --
end record;
constant dbgi_none : l3_debug_in_type := ('0', '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0', '0', '0', '0', '0', (others => '0'));
constant l3_dbgi_none : l3_debug_in_type := dbgi_none;
type l3_cstat_type is record
cmiss : std_ulogic; -- cache miss
tmiss : std_ulogic; -- TLB miss
chold : std_ulogic; -- cache hold
mhold : std_ulogic; -- cache mmu hold
end record;
constant cstat_none : l3_cstat_type := ('0', '0', '0', '0');
type l3_debug_out_type is record
data : std_logic_vector(31 downto 0);
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
fcnt : std_ulogic;
optype : std_logic_vector(5 downto 0); -- instruction type
bpmiss : std_ulogic; -- branch predict miss
istat : l3_cstat_type;
dstat : l3_cstat_type;
wbhold : std_ulogic; -- write buffer hold
su : std_ulogic; -- supervisor state
end record;
type l3_debug_in_vector is array (natural range <>) of l3_debug_in_type;
type l3_debug_out_vector is array (natural range <>) of l3_debug_out_type;
constant dbgo_none : l3_debug_out_type := (X"00000000", '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', "000000", '0', cstat_none, cstat_none, '0', '0');
constant l3_dbgo_none : l3_debug_out_type := dbgo_none;
type tracebuf_in_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
diag : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
component tbufmem
generic ( tech : integer := 0; tbuf : integer := 0; testen: integer := 0);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type);
end component;
component leon3s
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end component;
component leon3cg
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
component leon3ft
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0; -- cacheability table
netlist : integer := 0; -- use netlist
scantest : integer := 0; -- enable scan test support
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic
);
end component;
type grfpu_in_type is record
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector(8 downto 0);
op1 : std_logic_vector(63 downto 0);
op2 : std_logic_vector(63 downto 0);
opid : std_logic_vector(7 downto 0);
flush : std_logic;
flushid : std_logic_vector(5 downto 0);
rndmode : std_logic_vector(1 downto 0);
req : std_logic_vector(2 downto 0);
end record;
constant grfpu_in_none : grfpu_in_type :=
('0', '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'),
(others => '0'));
type grfpu_out_type is record
res : std_logic_vector(63 downto 0);
exc : std_logic_vector(5 downto 0);
allow : std_logic_vector(2 downto 0);
rdy : std_logic;
cc : std_logic_vector(1 downto 0);
idout : std_logic_vector(7 downto 0);
end record;
constant grfpu_out_none : grfpu_out_type :=
((others => '0'), (others => '0'), (others => '0'),
'0', (others => '0'), (others => '0'));
type grfpu_out_vector_type is array (integer range 0 to 7) of grfpu_out_type;
type grfpu_in_vector_type is array (integer range 0 to 7) of grfpu_in_type;
component grfpushwx
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end component;
component leon3sh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3s2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 1;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
gclk2 : in std_ulogic;
clk2 : in std_ulogic; -- snoop clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
clken : in std_ulogic
);
end component;
component leon3ft2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
type dsu_in_type is record
enable : std_ulogic;
break : std_ulogic;
end record;
type dsu_out_type is record
active : std_ulogic;
tstop : std_ulogic;
pwd : std_logic_vector(15 downto 0);
end record;
component dsu3
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
component dsu3_2x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
end component;
component dsu3_mb
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end component;
type irq_in_vector is array (Natural range <> ) of l3_irq_in_type;
type irq_out_vector is array (Natural range <> ) of l3_irq_out_type;
component irqmp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end component;
component irqmp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
clkfact : integer := 2
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
hclken : in std_ulogic
);
end component;
component irqamp
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
nctrl : integer range 1 to 16 := 1;
tstamp : integer range 0 to 16 := 0;
wdogen : integer range 0 to 1 := 0;
nwdog : integer range 1 to 16 := 1;
dynrstaddr : integer range 0 to 1 := 0;
rstaddr : integer range 0 to 16#fffff# := 0;
extrun : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
wdog : in std_logic_vector(nwdog-1 downto 0) := (others => '0');
cpurun : in std_logic_vector(ncpu-1 downto 0) := (others => '0')
);
end component;
component irqamp2x
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0;
nctrl : integer range 1 to 16 := 1;
tstamp : integer range 0 to 16 := 0;
wdogen : integer range 0 to 1 := 0;
nwdog : integer range 1 to 16 := 1;
dynrstaddr : integer range 0 to 1 := 0;
rstaddr : integer range 0 to 16#fffff# := 0;
extrun : integer range 0 to 1 := 0;
clkfact : integer := 2
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1);
wdog : in std_logic_vector(nwdog-1 downto 0) := (others => '0');
cpurun : in std_logic_vector(ncpu-1 downto 0) := (others => '0');
hclken : in std_ulogic
);
end component;
component leon3ftsh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- free-running clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic; -- gated clock
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon3x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
iuinj : integer := 0;
ceinj : integer range 0 to 3 := 0;
cached : integer := 0;
clk2x : integer := 1;
netlist : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic; -- free-running clock
gclk2 : in std_ulogic; -- gated 2x clock
gfclk2 : in std_ulogic; -- gated 2x FPU clock
clk2 : in std_ulogic; -- free-running 2x clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
clken : in std_ulogic
);
end component;
-- disassembly dummy module
component cpu_disasx
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result : in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end component;
end;
|
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect end_protected
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity add is
port (
a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0);
c_i: in std_logic;
s: out std_logic_vector(3 downto 0);
c_o: out std_logic );
end add;
architecture add_arch of add is
signal temp : std_logic_vector(4 downto 0);
begin
temp <= ('0' & a) + b + c_i;
s <= temp(3 downto 0);
c_o <= temp(4);
end add_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc897.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s02b00x00p02n02i00897ent IS
port ( x : integer := 2 );
END c10s02b00x00p02n02i00897ent;
ARCHITECTURE c10s02b00x00p02n02i00897arch OF c10s02b00x00p02n02i00897ent IS
BEGIN
-- extended use of declared generic.
assert NOT( x = 2 )
report "***PASSED TEST: c10s02b00x00p02n02i00897"
severity NOTE;
assert ( x = 2 )
report "***FAILED TEST: c10s02b00x00p02n02i00897 - The scope of the declaration that occurs immediately within a formal port declaration in an entity declaration extends beyond the immediate scope."
severity ERROR;
END c10s02b00x00p02n02i00897arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc897.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s02b00x00p02n02i00897ent IS
port ( x : integer := 2 );
END c10s02b00x00p02n02i00897ent;
ARCHITECTURE c10s02b00x00p02n02i00897arch OF c10s02b00x00p02n02i00897ent IS
BEGIN
-- extended use of declared generic.
assert NOT( x = 2 )
report "***PASSED TEST: c10s02b00x00p02n02i00897"
severity NOTE;
assert ( x = 2 )
report "***FAILED TEST: c10s02b00x00p02n02i00897 - The scope of the declaration that occurs immediately within a formal port declaration in an entity declaration extends beyond the immediate scope."
severity ERROR;
END c10s02b00x00p02n02i00897arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc897.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s02b00x00p02n02i00897ent IS
port ( x : integer := 2 );
END c10s02b00x00p02n02i00897ent;
ARCHITECTURE c10s02b00x00p02n02i00897arch OF c10s02b00x00p02n02i00897ent IS
BEGIN
-- extended use of declared generic.
assert NOT( x = 2 )
report "***PASSED TEST: c10s02b00x00p02n02i00897"
severity NOTE;
assert ( x = 2 )
report "***FAILED TEST: c10s02b00x00p02n02i00897 - The scope of the declaration that occurs immediately within a formal port declaration in an entity declaration extends beyond the immediate scope."
severity ERROR;
END c10s02b00x00p02n02i00897arch;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_559 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_559;
architecture augh of mul_559 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_559 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_559;
architecture augh of mul_559 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
|
architecture RTL of ENTITY_NAME is
begin
process
begin
FORCE_LABEL : sig1 <= transport a and c;
FORCE_LABEL : sig1 <= a and c;
sig1 <= a and c;
check_value(to_integer(unsigned(v_normalized_chan)) <= config.max_channel, TB_FAILURE, "Sanity check: Check that channel number is supported.", scope, ID_NEVER, msg_id_panel, proc_call);
end process;
end architecture RTL;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF Memory controller - Top level entity
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The memory controller connectr the memory subsystem of
-- ReconOS to the memory bus of the system as an AXI
-- master.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_master_burst_v1_00_a;
use axi_master_burst_v1_00_a.axi_master_burst;
library reconos_memif_memory_controller_v1_00_a;
use reconos_memif_memory_controller_v1_00_a.user_logic;
entity reconos_memif_memory_controller is
generic (
-- Memory controller parameters
C_MEMIF_FIFO_WIDTH : integer := 32;
C_CTRL_FIFO_WIDTH : integer := 32;
C_MEMIF_LENGTH_WIDTH : integer := 24;
C_USE_MMU_PORT : boolean := true;
-- Bus protocol parameters, do not add to or delete
C_FAMILY : string := "virtex6";
C_M_AXI_ADDR_WIDTH : integer := 32;
C_M_AXI_DATA_WIDTH : integer := 32;
C_MAX_BURST_LEN : integer := 256;
C_ADDR_PIPE_DEPTH : integer := 1;
C_NATIVE_DATA_WIDTH : integer := 32;
C_LENGTH_WIDTH : integer := 12
);
port (
-- Memory controller ports
MEMIF_FIFO_Hwt2Mem_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Hwt2Mem_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Empty : in std_logic;
MEMIF_FIFO_Hwt2Mem_RE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : out std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mem2Hwt_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Full : in std_logic;
MEMIF_FIFO_Mem2Hwt_WE : out std_logic;
CTRL_FIFO_Hwt_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Hwt_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_Hwt_Empty : in std_logic;
CTRL_FIFO_Hwt_RE : out std_logic;
MEMIF_FIFO_Mmu_Data : out std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mmu_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mmu_Full : in std_logic;
MEMIF_FIFO_Mmu_WE : out std_logic;
CTRL_FIFO_Mmu_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Mmu_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_Mmu_Empty : in std_logic;
CTRL_FIFO_Mmu_RE : out std_logic;
MEMCTRL_Clk : in std_logic;
MEMCTRL_Rst : in std_logic;
-- Bus protocol ports, do not add to or delete
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
MD_ERROR : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_ARVALID : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_RREADY : out std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_AWVALID : out std_logic;
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_WREADY : in std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector((C_M_AXI_DATA_WIDTH)/8 - 1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_BVALID : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_ARUSER : out std_logic_vector(4 downto 0)
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of M_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of M_AXI_ARESETN : signal is "10000";
attribute SIGIS of M_AXI_ACLK : signal is "Clk";
attribute SIGIS of MEMCTRL_Clk : signal is "Clk";
attribute SIGIS of M_AXI_ARESETN : signal is "Rst";
attribute SIGIS of MEMCTRL_Rst : signal is "Rst";
end entity reconos_memif_memory_controller;
architecture implementation of reconos_memif_memory_controller is
constant USER_MST_AWIDTH : integer := C_M_AXI_ADDR_WIDTH;
constant USER_MST_DWIDTH : integer := C_M_AXI_DATA_WIDTH;
constant USER_MST_NATIVE_DATA_WIDTH : integer := C_NATIVE_DATA_WIDTH;
constant USER_LENGTH_WIDTH : integer := C_LENGTH_WIDTH;
-- IP Interconnect (IPIC) signal declarations
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_ip2bus_mstrd_req : std_logic;
signal ipif_ip2bus_mstwr_req : std_logic;
signal ipif_ip2bus_mst_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_ip2bus_mst_be : std_logic_vector((C_NATIVE_DATA_WIDTH)/8-1 downto 0);
signal ipif_ip2bus_mst_length : std_logic_vector(C_LENGTH_WIDTH-1 downto 0);
signal ipif_ip2bus_mst_type : std_logic;
signal ipif_ip2bus_mst_lock : std_logic;
signal ipif_ip2bus_mst_reset : std_logic;
signal ipif_bus2ip_mst_cmdack : std_logic;
signal ipif_bus2ip_mst_cmplt : std_logic;
signal ipif_bus2ip_mst_error : std_logic;
signal ipif_bus2ip_mst_rearbitrate : std_logic;
signal ipif_bus2ip_mst_cmd_timeout : std_logic;
signal ipif_bus2ip_mstrd_d : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
signal ipif_bus2ip_mstrd_rem : std_logic_vector((C_NATIVE_DATA_WIDTH)/8-1 downto 0);
signal ipif_bus2ip_mstrd_sof_n : std_logic;
signal ipif_bus2ip_mstrd_eof_n : std_logic;
signal ipif_bus2ip_mstrd_src_rdy_n : std_logic;
signal ipif_bus2ip_mstrd_src_dsc_n : std_logic;
signal ipif_ip2bus_mstrd_dst_rdy_n : std_logic;
signal ipif_ip2bus_mstrd_dst_dsc_n : std_logic;
signal ipif_ip2bus_mstwr_d : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
signal ipif_ip2bus_mstwr_rem : std_logic_vector((C_NATIVE_DATA_WIDTH)/8-1 downto 0);
signal ipif_ip2bus_mstwr_src_rdy_n : std_logic;
signal ipif_ip2bus_mstwr_src_dsc_n : std_logic;
signal ipif_ip2bus_mstwr_sof_n : std_logic;
signal ipif_ip2bus_mstwr_eof_n : std_logic;
signal ipif_bus2ip_mstwr_dst_rdy_n : std_logic;
signal ipif_bus2ip_mstwr_dst_dsc_n : std_logic;
signal ignore : std_logic_vector(3 downto 0);
begin
-- instantiate axi_master_burst
AXI_MASTER_BURST_I : entity axi_master_burst_v1_00_a.axi_master_burst
generic map (
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_MAX_BURST_LEN => C_MAX_BURST_LEN,
C_NATIVE_DATA_WIDTH => C_NATIVE_DATA_WIDTH,
C_LENGTH_WIDTH => C_LENGTH_WIDTH,
C_ADDR_PIPE_DEPTH => C_ADDR_PIPE_DEPTH,
C_FAMILY => C_FAMILY
)
port map
(
m_axi_aclk => M_AXI_ACLK,
m_axi_aresetn => M_AXI_ARESETN,
md_error => MD_ERROR,
m_axi_arready => M_AXI_ARREADY,
m_axi_arvalid => M_AXI_ARVALID,
m_axi_araddr => M_AXI_ARADDR,
m_axi_arlen => M_AXI_ARLEN,
m_axi_arsize => M_AXI_ARSIZE,
m_axi_arburst => M_AXI_ARBURST,
m_axi_arprot => M_AXI_ARPROT,
m_axi_arcache => ignore,
m_axi_rready => M_AXI_RREADY,
m_axi_rvalid => M_AXI_RVALID,
m_axi_rdata => M_AXI_RDATA,
m_axi_rresp => M_AXI_RRESP,
m_axi_rlast => M_AXI_RLAST,
m_axi_awready => M_AXI_AWREADY,
m_axi_awvalid => M_AXI_AWVALID,
m_axi_awaddr => M_AXI_AWADDR,
m_axi_awlen => M_AXI_AWLEN,
m_axi_awsize => M_AXI_AWSIZE,
m_axi_awburst => M_AXI_AWBURST,
m_axi_awprot => M_AXI_AWPROT,
m_axi_awcache => ignore,
m_axi_wready => M_AXI_WREADY,
m_axi_wvalid => M_AXI_WVALID,
m_axi_wdata => M_AXI_WDATA,
m_axi_wstrb => M_AXI_WSTRB,
m_axi_wlast => M_AXI_WLAST,
m_axi_bready => M_AXI_BREADY,
m_axi_bvalid => M_AXI_BVALID,
m_axi_bresp => M_AXI_BRESP,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_length => ipif_ip2bus_mst_length,
ip2bus_mst_type => ipif_ip2bus_mst_type,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_rem => ipif_bus2ip_mstrd_rem,
bus2ip_mstrd_sof_n => ipif_bus2ip_mstrd_sof_n,
bus2ip_mstrd_eof_n => ipif_bus2ip_mstrd_eof_n,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
bus2ip_mstrd_src_dsc_n => ipif_bus2ip_mstrd_src_dsc_n,
ip2bus_mstrd_dst_rdy_n => ipif_ip2bus_mstrd_dst_rdy_n,
ip2bus_mstrd_dst_dsc_n => ipif_ip2bus_mstrd_dst_dsc_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
ip2bus_mstwr_rem => ipif_ip2bus_mstwr_rem,
ip2bus_mstwr_src_rdy_n => ipif_ip2bus_mstwr_src_rdy_n,
ip2bus_mstwr_src_dsc_n => ipif_ip2bus_mstwr_src_dsc_n,
ip2bus_mstwr_sof_n => ipif_ip2bus_mstwr_sof_n,
ip2bus_mstwr_eof_n => ipif_ip2bus_mstwr_eof_n,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n,
bus2ip_mstwr_dst_dsc_n => ipif_bus2ip_mstwr_dst_dsc_n
);
-- instantiate User Logic
USER_LOGIC_I : entity reconos_memif_memory_controller_v1_00_a.user_logic
generic map (
-- Memory controller parameters
C_MEMIF_FIFO_WIDTH => C_MEMIF_FIFO_WIDTH,
C_CTRL_FIFO_WIDTH => C_CTRL_FIFO_WIDTH,
C_MEMIF_LENGTH_WIDTH => C_MEMIF_LENGTH_WIDTH,
C_USE_MMU_PORT => C_USE_MMU_PORT,
-- Bus protocol parameters
C_MST_NATIVE_DATA_WIDTH => USER_MST_NATIVE_DATA_WIDTH,
C_LENGTH_WIDTH => USER_LENGTH_WIDTH,
C_MST_AWIDTH => USER_MST_AWIDTH
)
port map (
-- Memory controller ports
MEMIF_FIFO_Hwt2Mem_Data => MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_Fill => MEMIF_FIFO_Hwt2Mem_Fill,
MEMIF_FIFO_Hwt2Mem_Empty => MEMIF_FIFO_Hwt2Mem_Empty,
MEMIF_FIFO_Hwt2Mem_RE => MEMIF_FIFO_Hwt2Mem_RE,
MEMIF_FIFO_Mem2Hwt_Data => MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Rem => MEMIF_FIFO_Mem2Hwt_Rem,
MEMIF_FIFO_Mem2Hwt_Full => MEMIF_FIFO_Mem2Hwt_Full,
MEMIF_FIFO_Mem2Hwt_WE => MEMIF_FIFO_Mem2Hwt_WE,
CTRL_FIFO_Hwt_Data => CTRL_FIFO_Hwt_Data,
CTRL_FIFO_Hwt_Fill => CTRL_FIFO_Hwt_Fill,
CTRL_FIFO_Hwt_Empty => CTRL_FIFO_Hwt_Empty,
CTRL_FIFO_Hwt_RE => CTRL_FIFO_Hwt_RE,
MEMIF_FIFO_Mmu_Data => MEMIF_FIFO_Mmu_Data,
MEMIF_FIFO_Mmu_Rem => MEMIF_FIFO_Mmu_Rem,
MEMIF_FIFO_Mmu_Full => MEMIF_FIFO_Mmu_Full,
MEMIF_FIFO_Mmu_WE => MEMIF_FIFO_Mmu_WE,
CTRL_FIFO_Mmu_Data => CTRL_FIFO_Mmu_Data,
CTRL_FIFO_Mmu_Fill => CTRL_FIFO_Mmu_Fill,
CTRL_FIFO_Mmu_Empty => CTRL_FIFO_Mmu_Empty,
CTRL_FIFO_Mmu_RE => CTRL_FIFO_Mmu_RE,
MEMCTRL_Clk => MEMCTRL_Clk,
MEMCTRL_Rst => MEMCTRL_Rst,
-- Bus protocol ports
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_length => ipif_ip2bus_mst_length,
ip2bus_mst_type => ipif_ip2bus_mst_type,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_rem => ipif_bus2ip_mstrd_rem,
bus2ip_mstrd_sof_n => ipif_bus2ip_mstrd_sof_n,
bus2ip_mstrd_eof_n => ipif_bus2ip_mstrd_eof_n,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
bus2ip_mstrd_src_dsc_n => ipif_bus2ip_mstrd_src_dsc_n,
ip2bus_mstrd_dst_rdy_n => ipif_ip2bus_mstrd_dst_rdy_n,
ip2bus_mstrd_dst_dsc_n => ipif_ip2bus_mstrd_dst_dsc_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
ip2bus_mstwr_rem => ipif_ip2bus_mstwr_rem,
ip2bus_mstwr_src_rdy_n => ipif_ip2bus_mstwr_src_rdy_n,
ip2bus_mstwr_src_dsc_n => ipif_ip2bus_mstwr_src_dsc_n,
ip2bus_mstwr_sof_n => ipif_ip2bus_mstwr_sof_n,
ip2bus_mstwr_eof_n => ipif_ip2bus_mstwr_eof_n,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n,
bus2ip_mstwr_dst_dsc_n => ipif_bus2ip_mstwr_dst_dsc_n
);
ipif_Bus2IP_Clk <= M_AXI_ACLK;
ipif_Bus2IP_Resetn <= M_AXI_ARESETN;
M_AXI_AWCACHE <= (others => '1');
M_AXI_ARCACHE <= (others => '1');
M_AXI_AWUSER <= (others => '1');
M_AXI_ARUSER <= (others => '1');
end implementation;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF Memory controller - Top level entity
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The memory controller connectr the memory subsystem of
-- ReconOS to the memory bus of the system as an AXI
-- master.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_master_burst_v1_00_a;
use axi_master_burst_v1_00_a.axi_master_burst;
library reconos_memif_memory_controller_v1_00_a;
use reconos_memif_memory_controller_v1_00_a.user_logic;
entity reconos_memif_memory_controller is
generic (
-- Memory controller parameters
C_MEMIF_FIFO_WIDTH : integer := 32;
C_CTRL_FIFO_WIDTH : integer := 32;
C_MEMIF_LENGTH_WIDTH : integer := 24;
C_USE_MMU_PORT : boolean := true;
-- Bus protocol parameters, do not add to or delete
C_FAMILY : string := "virtex6";
C_M_AXI_ADDR_WIDTH : integer := 32;
C_M_AXI_DATA_WIDTH : integer := 32;
C_MAX_BURST_LEN : integer := 256;
C_ADDR_PIPE_DEPTH : integer := 1;
C_NATIVE_DATA_WIDTH : integer := 32;
C_LENGTH_WIDTH : integer := 12
);
port (
-- Memory controller ports
MEMIF_FIFO_Hwt2Mem_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Hwt2Mem_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Empty : in std_logic;
MEMIF_FIFO_Hwt2Mem_RE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : out std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mem2Hwt_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Full : in std_logic;
MEMIF_FIFO_Mem2Hwt_WE : out std_logic;
CTRL_FIFO_Hwt_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Hwt_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_Hwt_Empty : in std_logic;
CTRL_FIFO_Hwt_RE : out std_logic;
MEMIF_FIFO_Mmu_Data : out std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mmu_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mmu_Full : in std_logic;
MEMIF_FIFO_Mmu_WE : out std_logic;
CTRL_FIFO_Mmu_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Mmu_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_Mmu_Empty : in std_logic;
CTRL_FIFO_Mmu_RE : out std_logic;
MEMCTRL_Clk : in std_logic;
MEMCTRL_Rst : in std_logic;
-- Bus protocol ports, do not add to or delete
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
MD_ERROR : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_ARVALID : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_RREADY : out std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_AWVALID : out std_logic;
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_WREADY : in std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector((C_M_AXI_DATA_WIDTH)/8 - 1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_BVALID : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_ARUSER : out std_logic_vector(4 downto 0)
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of M_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of M_AXI_ARESETN : signal is "10000";
attribute SIGIS of M_AXI_ACLK : signal is "Clk";
attribute SIGIS of MEMCTRL_Clk : signal is "Clk";
attribute SIGIS of M_AXI_ARESETN : signal is "Rst";
attribute SIGIS of MEMCTRL_Rst : signal is "Rst";
end entity reconos_memif_memory_controller;
architecture implementation of reconos_memif_memory_controller is
constant USER_MST_AWIDTH : integer := C_M_AXI_ADDR_WIDTH;
constant USER_MST_DWIDTH : integer := C_M_AXI_DATA_WIDTH;
constant USER_MST_NATIVE_DATA_WIDTH : integer := C_NATIVE_DATA_WIDTH;
constant USER_LENGTH_WIDTH : integer := C_LENGTH_WIDTH;
-- IP Interconnect (IPIC) signal declarations
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_ip2bus_mstrd_req : std_logic;
signal ipif_ip2bus_mstwr_req : std_logic;
signal ipif_ip2bus_mst_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_ip2bus_mst_be : std_logic_vector((C_NATIVE_DATA_WIDTH)/8-1 downto 0);
signal ipif_ip2bus_mst_length : std_logic_vector(C_LENGTH_WIDTH-1 downto 0);
signal ipif_ip2bus_mst_type : std_logic;
signal ipif_ip2bus_mst_lock : std_logic;
signal ipif_ip2bus_mst_reset : std_logic;
signal ipif_bus2ip_mst_cmdack : std_logic;
signal ipif_bus2ip_mst_cmplt : std_logic;
signal ipif_bus2ip_mst_error : std_logic;
signal ipif_bus2ip_mst_rearbitrate : std_logic;
signal ipif_bus2ip_mst_cmd_timeout : std_logic;
signal ipif_bus2ip_mstrd_d : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
signal ipif_bus2ip_mstrd_rem : std_logic_vector((C_NATIVE_DATA_WIDTH)/8-1 downto 0);
signal ipif_bus2ip_mstrd_sof_n : std_logic;
signal ipif_bus2ip_mstrd_eof_n : std_logic;
signal ipif_bus2ip_mstrd_src_rdy_n : std_logic;
signal ipif_bus2ip_mstrd_src_dsc_n : std_logic;
signal ipif_ip2bus_mstrd_dst_rdy_n : std_logic;
signal ipif_ip2bus_mstrd_dst_dsc_n : std_logic;
signal ipif_ip2bus_mstwr_d : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
signal ipif_ip2bus_mstwr_rem : std_logic_vector((C_NATIVE_DATA_WIDTH)/8-1 downto 0);
signal ipif_ip2bus_mstwr_src_rdy_n : std_logic;
signal ipif_ip2bus_mstwr_src_dsc_n : std_logic;
signal ipif_ip2bus_mstwr_sof_n : std_logic;
signal ipif_ip2bus_mstwr_eof_n : std_logic;
signal ipif_bus2ip_mstwr_dst_rdy_n : std_logic;
signal ipif_bus2ip_mstwr_dst_dsc_n : std_logic;
signal ignore : std_logic_vector(3 downto 0);
begin
-- instantiate axi_master_burst
AXI_MASTER_BURST_I : entity axi_master_burst_v1_00_a.axi_master_burst
generic map (
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_MAX_BURST_LEN => C_MAX_BURST_LEN,
C_NATIVE_DATA_WIDTH => C_NATIVE_DATA_WIDTH,
C_LENGTH_WIDTH => C_LENGTH_WIDTH,
C_ADDR_PIPE_DEPTH => C_ADDR_PIPE_DEPTH,
C_FAMILY => C_FAMILY
)
port map
(
m_axi_aclk => M_AXI_ACLK,
m_axi_aresetn => M_AXI_ARESETN,
md_error => MD_ERROR,
m_axi_arready => M_AXI_ARREADY,
m_axi_arvalid => M_AXI_ARVALID,
m_axi_araddr => M_AXI_ARADDR,
m_axi_arlen => M_AXI_ARLEN,
m_axi_arsize => M_AXI_ARSIZE,
m_axi_arburst => M_AXI_ARBURST,
m_axi_arprot => M_AXI_ARPROT,
m_axi_arcache => ignore,
m_axi_rready => M_AXI_RREADY,
m_axi_rvalid => M_AXI_RVALID,
m_axi_rdata => M_AXI_RDATA,
m_axi_rresp => M_AXI_RRESP,
m_axi_rlast => M_AXI_RLAST,
m_axi_awready => M_AXI_AWREADY,
m_axi_awvalid => M_AXI_AWVALID,
m_axi_awaddr => M_AXI_AWADDR,
m_axi_awlen => M_AXI_AWLEN,
m_axi_awsize => M_AXI_AWSIZE,
m_axi_awburst => M_AXI_AWBURST,
m_axi_awprot => M_AXI_AWPROT,
m_axi_awcache => ignore,
m_axi_wready => M_AXI_WREADY,
m_axi_wvalid => M_AXI_WVALID,
m_axi_wdata => M_AXI_WDATA,
m_axi_wstrb => M_AXI_WSTRB,
m_axi_wlast => M_AXI_WLAST,
m_axi_bready => M_AXI_BREADY,
m_axi_bvalid => M_AXI_BVALID,
m_axi_bresp => M_AXI_BRESP,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_length => ipif_ip2bus_mst_length,
ip2bus_mst_type => ipif_ip2bus_mst_type,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_rem => ipif_bus2ip_mstrd_rem,
bus2ip_mstrd_sof_n => ipif_bus2ip_mstrd_sof_n,
bus2ip_mstrd_eof_n => ipif_bus2ip_mstrd_eof_n,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
bus2ip_mstrd_src_dsc_n => ipif_bus2ip_mstrd_src_dsc_n,
ip2bus_mstrd_dst_rdy_n => ipif_ip2bus_mstrd_dst_rdy_n,
ip2bus_mstrd_dst_dsc_n => ipif_ip2bus_mstrd_dst_dsc_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
ip2bus_mstwr_rem => ipif_ip2bus_mstwr_rem,
ip2bus_mstwr_src_rdy_n => ipif_ip2bus_mstwr_src_rdy_n,
ip2bus_mstwr_src_dsc_n => ipif_ip2bus_mstwr_src_dsc_n,
ip2bus_mstwr_sof_n => ipif_ip2bus_mstwr_sof_n,
ip2bus_mstwr_eof_n => ipif_ip2bus_mstwr_eof_n,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n,
bus2ip_mstwr_dst_dsc_n => ipif_bus2ip_mstwr_dst_dsc_n
);
-- instantiate User Logic
USER_LOGIC_I : entity reconos_memif_memory_controller_v1_00_a.user_logic
generic map (
-- Memory controller parameters
C_MEMIF_FIFO_WIDTH => C_MEMIF_FIFO_WIDTH,
C_CTRL_FIFO_WIDTH => C_CTRL_FIFO_WIDTH,
C_MEMIF_LENGTH_WIDTH => C_MEMIF_LENGTH_WIDTH,
C_USE_MMU_PORT => C_USE_MMU_PORT,
-- Bus protocol parameters
C_MST_NATIVE_DATA_WIDTH => USER_MST_NATIVE_DATA_WIDTH,
C_LENGTH_WIDTH => USER_LENGTH_WIDTH,
C_MST_AWIDTH => USER_MST_AWIDTH
)
port map (
-- Memory controller ports
MEMIF_FIFO_Hwt2Mem_Data => MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_Fill => MEMIF_FIFO_Hwt2Mem_Fill,
MEMIF_FIFO_Hwt2Mem_Empty => MEMIF_FIFO_Hwt2Mem_Empty,
MEMIF_FIFO_Hwt2Mem_RE => MEMIF_FIFO_Hwt2Mem_RE,
MEMIF_FIFO_Mem2Hwt_Data => MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Rem => MEMIF_FIFO_Mem2Hwt_Rem,
MEMIF_FIFO_Mem2Hwt_Full => MEMIF_FIFO_Mem2Hwt_Full,
MEMIF_FIFO_Mem2Hwt_WE => MEMIF_FIFO_Mem2Hwt_WE,
CTRL_FIFO_Hwt_Data => CTRL_FIFO_Hwt_Data,
CTRL_FIFO_Hwt_Fill => CTRL_FIFO_Hwt_Fill,
CTRL_FIFO_Hwt_Empty => CTRL_FIFO_Hwt_Empty,
CTRL_FIFO_Hwt_RE => CTRL_FIFO_Hwt_RE,
MEMIF_FIFO_Mmu_Data => MEMIF_FIFO_Mmu_Data,
MEMIF_FIFO_Mmu_Rem => MEMIF_FIFO_Mmu_Rem,
MEMIF_FIFO_Mmu_Full => MEMIF_FIFO_Mmu_Full,
MEMIF_FIFO_Mmu_WE => MEMIF_FIFO_Mmu_WE,
CTRL_FIFO_Mmu_Data => CTRL_FIFO_Mmu_Data,
CTRL_FIFO_Mmu_Fill => CTRL_FIFO_Mmu_Fill,
CTRL_FIFO_Mmu_Empty => CTRL_FIFO_Mmu_Empty,
CTRL_FIFO_Mmu_RE => CTRL_FIFO_Mmu_RE,
MEMCTRL_Clk => MEMCTRL_Clk,
MEMCTRL_Rst => MEMCTRL_Rst,
-- Bus protocol ports
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_length => ipif_ip2bus_mst_length,
ip2bus_mst_type => ipif_ip2bus_mst_type,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_rem => ipif_bus2ip_mstrd_rem,
bus2ip_mstrd_sof_n => ipif_bus2ip_mstrd_sof_n,
bus2ip_mstrd_eof_n => ipif_bus2ip_mstrd_eof_n,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
bus2ip_mstrd_src_dsc_n => ipif_bus2ip_mstrd_src_dsc_n,
ip2bus_mstrd_dst_rdy_n => ipif_ip2bus_mstrd_dst_rdy_n,
ip2bus_mstrd_dst_dsc_n => ipif_ip2bus_mstrd_dst_dsc_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
ip2bus_mstwr_rem => ipif_ip2bus_mstwr_rem,
ip2bus_mstwr_src_rdy_n => ipif_ip2bus_mstwr_src_rdy_n,
ip2bus_mstwr_src_dsc_n => ipif_ip2bus_mstwr_src_dsc_n,
ip2bus_mstwr_sof_n => ipif_ip2bus_mstwr_sof_n,
ip2bus_mstwr_eof_n => ipif_ip2bus_mstwr_eof_n,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n,
bus2ip_mstwr_dst_dsc_n => ipif_bus2ip_mstwr_dst_dsc_n
);
ipif_Bus2IP_Clk <= M_AXI_ACLK;
ipif_Bus2IP_Resetn <= M_AXI_ARESETN;
M_AXI_AWCACHE <= (others => '1');
M_AXI_ARCACHE <= (others => '1');
M_AXI_AWUSER <= (others => '1');
M_AXI_ARUSER <= (others => '1');
end implementation;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
use work.dspalu_pac.all;
use work.Bit_Manipulation.all;
-------------------------------------------------------------------------------
entity dotcmul is
port (
--@inputs
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
length_kern_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
result1 : in std_logic_vector((sig_width - 1) downto 0);
result2 : in std_logic_vector((sig_width - 1) downto 0);
--@outputs;
dsp_bus : out t_dsp_bus
);
end dotcmul;
--=----------------------------------------------------------------------------
architecture archi_dotcmul of dotcmul is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_addr_pipe_depth : integer := 11;
constant c_ind_width : integer := cmdreg_width - 2;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_bus : t_dsp_bus;
type t_dotcmul_state is (st_init, st_startpipe, st_performop, st_copy);
type t_datastate is (st_data_y1, st_data_y2);
signal s_state : t_dotcmul_state;
signal s_length : unsigned((cmdreg_width - 1) downto 0);
signal s_data_y1_r : std_logic_vector((sig_width - 1) downto 0);
signal s_data_y2_r : std_logic_vector((sig_width - 1) downto 0);
signal s_data_u1_r : std_logic_vector((sig_width - 1) downto 0);
signal s_data_y1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_y2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_u1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_u2 : std_logic_vector((sig_width - 1) downto 0);
signal s_out_y2_r : std_logic_vector((sig_width - 1) downto 0);
signal s_out_u1_r : std_logic_vector((sig_width - 1) downto 0);
signal s_out_u2_r : std_logic_vector((sig_width - 1) downto 0);
signal s_out_y1 : std_logic_vector((sig_width - 1) downto 0);
signal s_out_y2 : std_logic_vector((sig_width - 1) downto 0);
signal s_out_u1 : std_logic_vector((sig_width - 1) downto 0);
signal s_out_u2 : std_logic_vector((sig_width - 1) downto 0);
signal s_datastate : t_datastate;
signal s_datastate_n1 : t_datastate;
type t_addr_pipe is array(0 to c_addr_pipe_depth - 1) of unsigned((cmdreg_width - 1) downto 0);
type t_wr_pipe is array(0 to c_addr_pipe_depth - 1) of std_logic;
signal s_addr_pipe : t_addr_pipe;
signal s_wr_pipe : t_wr_pipe;
signal s_next_index : unsigned((c_ind_width - 1) downto 0);
signal s_next_group : unsigned((c_ind_width - 1) downto 0);
signal s_sample_index : unsigned((c_ind_width - 1) downto 0);
signal s_sample_index_rev : unsigned((c_ind_width - 1) downto 0);
signal s_addr_r_m0_tmp : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_r_m1_tmp : unsigned((cmdreg_width - 1) downto 0);
signal s_imag_part : std_logic;
-- signal s_module : integer;
signal s_mask_reg : unsigned((cmdreg_width - 1) downto 0);
signal s_length_kern : unsigned((cmdreg_width - 1) downto 0);
begin -- archs_dotcmul
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_dotcmul : process (clk)
begin -- process p_dotcmul
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_state <= st_init;
--s_dsp_bus <= c_dsp_bus_init;
s_dsp_bus.op_done <= '0';
-- memory 0
-- s_dsp_bus.data_out_m0 <= (others => '0');
-- s_dsp_bus.addr_r_m0 <= (others => '0');
-- s_dsp_bus.addr_w_m0 <= (others => '0');
-- s_dsp_bus.wr_en_m0 <= '0';
--s_dsp_bus.c_en_m0 <= '0';
-- memory 1
-- s_dsp_bus.data_out_m1 <= (others => '0');
s_dsp_bus.wr_en_m1 <= '0';
--s_dsp_bus.c_en_m1 <= '0';
-- memory 2
-- s_dsp_bus.data_out_m2 <= (others => '0');
s_dsp_bus.addr_m2 <= (others => '0');
s_dsp_bus.wr_en_m2 <= '0';
-------------------------------------------------------------------------------
-- operation management
-------------------------------------------------------------------------------
else
case s_state is
when st_init =>
-- s_count <= 0;
if s_dsp_bus.op_done = '0' then
s_state <= st_performop;
end if;
when st_performop =>
-- In this state : reading, complex multiplication and writting
-- are done concurently
if s_sample_index = s_length then
--s_dsp_bus.wr_en_m1 <= '1';
s_state <= st_copy;
end if;
when st_copy =>
-- write last words to memory
-- s_count <= s_count + 1;
-- if(s_count = 10) then
if(s_dsp_bus.wr_en_m0 = '0') then
s_state <= st_init;
s_dsp_bus.op_done <= '1';
end if;
when others => null;
end case;
end if;
end if;
end process p_dotcmul;
-------------------------------------------------------------------------------
-- Data states
-------------------------------------------------------------------------------
p_data : process (clk)
begin -- process p_data
if rising_edge(clk) then -- rising clock edge
if s_state = st_init then
-- initial state is calculated as a function of pipeline depth
-- s_datastate <= st_data_y1;
s_datastate <= st_data_y2;
s_dsp_bus.alu_select <= alu_mul;
s_dsp_bus.acc_mode1 <= acc_store;
s_dsp_bus.acc_mode2 <= acc_store;
else
case s_datastate is
when st_data_y1 =>
s_datastate <= st_data_y2;
when others => -- st_data_y2
s_datastate <= st_data_y1;
s_dsp_bus.alu_select <= alu_cmul_conj;
s_dsp_bus.acc_mode1 <= acc_store;
s_dsp_bus.acc_mode2 <= acc_store;
end case;
end if;
end if;
end process p_data;
-------------------------------------------------------------------------------
-- load data from memory
-------------------------------------------------------------------------------
p_dataload : process (clk)
begin -- process p_dataload
if rising_edge(clk) then -- rising clock edge
case s_datastate is
when st_data_y1 =>
s_data_u1_r <= data_in_m1;
s_data_y1_r <= data_in_m0;
when others => -- st_data_y2
dispsig("sigcmul", to_integer(s_sample_index) + 1, to_integer(signed(s_data_y1_r)));
s_data_y1 <= s_data_y1_r;
s_data_y2 <= data_in_m0;
s_data_u2 <= data_in_m1;
s_data_u1 <= s_data_u1_r;
end case;
end if;
end process p_dataload;
-------------------------------------------------------------------------------
-- store data to memory
-------------------------------------------------------------------------------
p_datastore : process (clk)
begin -- process p_datastore
if rising_edge(clk) then -- rising clock edge
s_datastate_n1 <= s_datastate;
case s_datastate_n1 is
when st_data_y1 =>
-- states y1, y2 inverted for writing because pipe length is odd
s_dsp_bus.data_out_m0 <= s_out_y1;
s_out_y2_r <= s_out_y2;
when others => -- st_data_y1
s_dsp_bus.data_out_m0 <= s_out_y2_r;
s_out_y1 <= result1;
s_out_y2 <= result2;
end case;
end if;
end process p_datastore;
-------------------------------------------------------------------------------
-- Compute address of reading words
-------------------------------------------------------------------------------
p_addr_comput : process (clk)
begin -- process p_addr_comput
if rising_edge(clk) then -- rising clock edge
if s_state = st_init then
s_sample_index <= to_unsigned(0, c_ind_width);
s_imag_part <= '0';
else
-- the real datastate is shifted of 2 stages because of pipeline delay
if (s_datastate = st_data_y2) then
-- y1 being read, compute index of y2
s_imag_part <= '1';
-- else compute index of next sample
-- elsif (s_next_index < s_length) then
else
-- increment index
s_sample_index <= s_next_index((c_ind_width - 1) downto 0);
s_imag_part <= '0';
end if;
end if;
end if;
end process p_addr_comput;
s_next_index <= s_sample_index + 1;
-------------------------------------------------------------------------------
-- address pipe : output is writting address
-------------------------------------------------------------------------------
p_addr_pipe : process (clk)
begin -- process p_addr_pipe
if rising_edge(clk) then -- rising clock edge
s_addr_pipe(0) <= s_addr_r_m0_tmp;
if(s_state = st_performop) then
s_wr_pipe(0) <= '1';
else
s_wr_pipe(0) <= '0';
end if;
for i in 0 to c_addr_pipe_depth - 2 loop
s_addr_pipe(i + 1) <= s_addr_pipe(i);
s_wr_pipe(i + 1) <= s_wr_pipe(i);
end loop;
end if;
end process p_addr_pipe;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
dsp_bus <= s_dsp_bus;
s_dsp_bus.data_out_m2 <= (others => '0');
s_dsp_bus.data_out_m1 <= (others => '0');
s_dsp_bus.c_en_m0 <= '1';
s_dsp_bus.c_en_m1 <= '1';
s_dsp_bus.c_en_m2 <= '1';
s_dsp_bus.gcounter_reset <= '1';
-- alu inputs
s_dsp_bus.mul_in_a1 <= s_data_y1;
s_dsp_bus.mul_in_a2 <= s_data_y2;
s_dsp_bus.mul_in_b1 <= s_data_u1;
s_dsp_bus.mul_in_b2 <= s_data_u2;
-- Writing and reading address of the memory
s_sample_index_rev <= bit_reverse(s_sample_index);
s_addr_r_m0_tmp((cmdreg_width - 1) downto (c_ind_width + 1)) <= (others => '0');
s_addr_r_m1_tmp((cmdreg_width - 1) downto (c_ind_width + 1)) <= (others => '0');
s_addr_r_m1_tmp((c_ind_width) downto 1) <= s_sample_index;
-- index with bit reverse if needed
s_addr_r_m0_tmp((c_ind_width) downto 1) <= s_sample_index when opflag_select(opflagbit_bitrev) = '0' else
s_sample_index((c_ind_width - 1) downto 4) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 4))
when length_kern_reg(4) = '1' else
s_sample_index((c_ind_width - 1) downto 5) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 5))
when length_kern_reg(5) = '1' else
s_sample_index((c_ind_width - 1) downto 6) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 6))
when length_kern_reg(6) = '1' else
s_sample_index((c_ind_width - 1) downto 7) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 7))
when length_kern_reg(7) = '1' else
s_sample_index((c_ind_width - 1) downto 8) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 8))
when length_kern_reg(8) = '1' else
s_sample_index((c_ind_width - 1) downto 9) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 9))
when length_kern_reg(9) = '1' else
s_sample_index((c_ind_width - 1) downto 10) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 10))
when length_kern_reg(10) = '1' else
s_sample_index((c_ind_width - 1) downto 11) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 11))
when length_kern_reg(11) = '1' else
s_sample_index((c_ind_width - 1) downto 12) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 12))
when length_kern_reg(12) = '1' else
s_sample_index((c_ind_width - 1) downto 13) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 13))
when length_kern_reg(13) = '1' else
s_sample_index_rev;
s_addr_r_m0_tmp(0) <= s_imag_part;
s_addr_r_m1_tmp(0) <= s_imag_part;
p_addr_delay : process (clk)
begin -- process p_addr_pipe
if rising_edge(clk) then -- rising clock edge
s_dsp_bus.addr_r_m0 <= s_addr_r_m0_tmp;
s_dsp_bus.addr_m1 <= unsigned(bitbit_and(std_logic_vector(s_addr_r_m1_tmp),
std_logic_vector(s_mask_reg)));
end if;
end process p_addr_delay;
s_dsp_bus.addr_w_m0 <= s_addr_pipe(c_addr_pipe_depth - 1);
s_dsp_bus.wr_en_m0 <= s_wr_pipe(c_addr_pipe_depth - 1);
-- specific index relations
s_length <= unsigned(length_reg);
-- left shift because real length is double (complex values)
s_length_kern <= unsigned(length_kern_reg((cmdreg_data_width - 2) downto 0) & '0');
s_mask_reg <= s_length_kern - 1;
-- s_module <= module(signed(s_data_y1), signed(s_data_y2));
end archi_dotcmul;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
use work.dspalu_pac.all;
use work.Bit_Manipulation.all;
-------------------------------------------------------------------------------
entity dotcmul is
port (
--@inputs
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
length_kern_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
result1 : in std_logic_vector((sig_width - 1) downto 0);
result2 : in std_logic_vector((sig_width - 1) downto 0);
--@outputs;
dsp_bus : out t_dsp_bus
);
end dotcmul;
--=----------------------------------------------------------------------------
architecture archi_dotcmul of dotcmul is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_addr_pipe_depth : integer := 11;
constant c_ind_width : integer := cmdreg_width - 2;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_bus : t_dsp_bus;
type t_dotcmul_state is (st_init, st_startpipe, st_performop, st_copy);
type t_datastate is (st_data_y1, st_data_y2);
signal s_state : t_dotcmul_state;
signal s_length : unsigned((cmdreg_width - 1) downto 0);
signal s_data_y1_r : std_logic_vector((sig_width - 1) downto 0);
signal s_data_y2_r : std_logic_vector((sig_width - 1) downto 0);
signal s_data_u1_r : std_logic_vector((sig_width - 1) downto 0);
signal s_data_y1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_y2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_u1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_u2 : std_logic_vector((sig_width - 1) downto 0);
signal s_out_y2_r : std_logic_vector((sig_width - 1) downto 0);
signal s_out_u1_r : std_logic_vector((sig_width - 1) downto 0);
signal s_out_u2_r : std_logic_vector((sig_width - 1) downto 0);
signal s_out_y1 : std_logic_vector((sig_width - 1) downto 0);
signal s_out_y2 : std_logic_vector((sig_width - 1) downto 0);
signal s_out_u1 : std_logic_vector((sig_width - 1) downto 0);
signal s_out_u2 : std_logic_vector((sig_width - 1) downto 0);
signal s_datastate : t_datastate;
signal s_datastate_n1 : t_datastate;
type t_addr_pipe is array(0 to c_addr_pipe_depth - 1) of unsigned((cmdreg_width - 1) downto 0);
type t_wr_pipe is array(0 to c_addr_pipe_depth - 1) of std_logic;
signal s_addr_pipe : t_addr_pipe;
signal s_wr_pipe : t_wr_pipe;
signal s_next_index : unsigned((c_ind_width - 1) downto 0);
signal s_next_group : unsigned((c_ind_width - 1) downto 0);
signal s_sample_index : unsigned((c_ind_width - 1) downto 0);
signal s_sample_index_rev : unsigned((c_ind_width - 1) downto 0);
signal s_addr_r_m0_tmp : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_r_m1_tmp : unsigned((cmdreg_width - 1) downto 0);
signal s_imag_part : std_logic;
-- signal s_module : integer;
signal s_mask_reg : unsigned((cmdreg_width - 1) downto 0);
signal s_length_kern : unsigned((cmdreg_width - 1) downto 0);
begin -- archs_dotcmul
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_dotcmul : process (clk)
begin -- process p_dotcmul
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_state <= st_init;
--s_dsp_bus <= c_dsp_bus_init;
s_dsp_bus.op_done <= '0';
-- memory 0
-- s_dsp_bus.data_out_m0 <= (others => '0');
-- s_dsp_bus.addr_r_m0 <= (others => '0');
-- s_dsp_bus.addr_w_m0 <= (others => '0');
-- s_dsp_bus.wr_en_m0 <= '0';
--s_dsp_bus.c_en_m0 <= '0';
-- memory 1
-- s_dsp_bus.data_out_m1 <= (others => '0');
s_dsp_bus.wr_en_m1 <= '0';
--s_dsp_bus.c_en_m1 <= '0';
-- memory 2
-- s_dsp_bus.data_out_m2 <= (others => '0');
s_dsp_bus.addr_m2 <= (others => '0');
s_dsp_bus.wr_en_m2 <= '0';
-------------------------------------------------------------------------------
-- operation management
-------------------------------------------------------------------------------
else
case s_state is
when st_init =>
-- s_count <= 0;
if s_dsp_bus.op_done = '0' then
s_state <= st_performop;
end if;
when st_performop =>
-- In this state : reading, complex multiplication and writting
-- are done concurently
if s_sample_index = s_length then
--s_dsp_bus.wr_en_m1 <= '1';
s_state <= st_copy;
end if;
when st_copy =>
-- write last words to memory
-- s_count <= s_count + 1;
-- if(s_count = 10) then
if(s_dsp_bus.wr_en_m0 = '0') then
s_state <= st_init;
s_dsp_bus.op_done <= '1';
end if;
when others => null;
end case;
end if;
end if;
end process p_dotcmul;
-------------------------------------------------------------------------------
-- Data states
-------------------------------------------------------------------------------
p_data : process (clk)
begin -- process p_data
if rising_edge(clk) then -- rising clock edge
if s_state = st_init then
-- initial state is calculated as a function of pipeline depth
-- s_datastate <= st_data_y1;
s_datastate <= st_data_y2;
s_dsp_bus.alu_select <= alu_mul;
s_dsp_bus.acc_mode1 <= acc_store;
s_dsp_bus.acc_mode2 <= acc_store;
else
case s_datastate is
when st_data_y1 =>
s_datastate <= st_data_y2;
when others => -- st_data_y2
s_datastate <= st_data_y1;
s_dsp_bus.alu_select <= alu_cmul_conj;
s_dsp_bus.acc_mode1 <= acc_store;
s_dsp_bus.acc_mode2 <= acc_store;
end case;
end if;
end if;
end process p_data;
-------------------------------------------------------------------------------
-- load data from memory
-------------------------------------------------------------------------------
p_dataload : process (clk)
begin -- process p_dataload
if rising_edge(clk) then -- rising clock edge
case s_datastate is
when st_data_y1 =>
s_data_u1_r <= data_in_m1;
s_data_y1_r <= data_in_m0;
when others => -- st_data_y2
dispsig("sigcmul", to_integer(s_sample_index) + 1, to_integer(signed(s_data_y1_r)));
s_data_y1 <= s_data_y1_r;
s_data_y2 <= data_in_m0;
s_data_u2 <= data_in_m1;
s_data_u1 <= s_data_u1_r;
end case;
end if;
end process p_dataload;
-------------------------------------------------------------------------------
-- store data to memory
-------------------------------------------------------------------------------
p_datastore : process (clk)
begin -- process p_datastore
if rising_edge(clk) then -- rising clock edge
s_datastate_n1 <= s_datastate;
case s_datastate_n1 is
when st_data_y1 =>
-- states y1, y2 inverted for writing because pipe length is odd
s_dsp_bus.data_out_m0 <= s_out_y1;
s_out_y2_r <= s_out_y2;
when others => -- st_data_y1
s_dsp_bus.data_out_m0 <= s_out_y2_r;
s_out_y1 <= result1;
s_out_y2 <= result2;
end case;
end if;
end process p_datastore;
-------------------------------------------------------------------------------
-- Compute address of reading words
-------------------------------------------------------------------------------
p_addr_comput : process (clk)
begin -- process p_addr_comput
if rising_edge(clk) then -- rising clock edge
if s_state = st_init then
s_sample_index <= to_unsigned(0, c_ind_width);
s_imag_part <= '0';
else
-- the real datastate is shifted of 2 stages because of pipeline delay
if (s_datastate = st_data_y2) then
-- y1 being read, compute index of y2
s_imag_part <= '1';
-- else compute index of next sample
-- elsif (s_next_index < s_length) then
else
-- increment index
s_sample_index <= s_next_index((c_ind_width - 1) downto 0);
s_imag_part <= '0';
end if;
end if;
end if;
end process p_addr_comput;
s_next_index <= s_sample_index + 1;
-------------------------------------------------------------------------------
-- address pipe : output is writting address
-------------------------------------------------------------------------------
p_addr_pipe : process (clk)
begin -- process p_addr_pipe
if rising_edge(clk) then -- rising clock edge
s_addr_pipe(0) <= s_addr_r_m0_tmp;
if(s_state = st_performop) then
s_wr_pipe(0) <= '1';
else
s_wr_pipe(0) <= '0';
end if;
for i in 0 to c_addr_pipe_depth - 2 loop
s_addr_pipe(i + 1) <= s_addr_pipe(i);
s_wr_pipe(i + 1) <= s_wr_pipe(i);
end loop;
end if;
end process p_addr_pipe;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
dsp_bus <= s_dsp_bus;
s_dsp_bus.data_out_m2 <= (others => '0');
s_dsp_bus.data_out_m1 <= (others => '0');
s_dsp_bus.c_en_m0 <= '1';
s_dsp_bus.c_en_m1 <= '1';
s_dsp_bus.c_en_m2 <= '1';
s_dsp_bus.gcounter_reset <= '1';
-- alu inputs
s_dsp_bus.mul_in_a1 <= s_data_y1;
s_dsp_bus.mul_in_a2 <= s_data_y2;
s_dsp_bus.mul_in_b1 <= s_data_u1;
s_dsp_bus.mul_in_b2 <= s_data_u2;
-- Writing and reading address of the memory
s_sample_index_rev <= bit_reverse(s_sample_index);
s_addr_r_m0_tmp((cmdreg_width - 1) downto (c_ind_width + 1)) <= (others => '0');
s_addr_r_m1_tmp((cmdreg_width - 1) downto (c_ind_width + 1)) <= (others => '0');
s_addr_r_m1_tmp((c_ind_width) downto 1) <= s_sample_index;
-- index with bit reverse if needed
s_addr_r_m0_tmp((c_ind_width) downto 1) <= s_sample_index when opflag_select(opflagbit_bitrev) = '0' else
s_sample_index((c_ind_width - 1) downto 4) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 4))
when length_kern_reg(4) = '1' else
s_sample_index((c_ind_width - 1) downto 5) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 5))
when length_kern_reg(5) = '1' else
s_sample_index((c_ind_width - 1) downto 6) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 6))
when length_kern_reg(6) = '1' else
s_sample_index((c_ind_width - 1) downto 7) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 7))
when length_kern_reg(7) = '1' else
s_sample_index((c_ind_width - 1) downto 8) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 8))
when length_kern_reg(8) = '1' else
s_sample_index((c_ind_width - 1) downto 9) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 9))
when length_kern_reg(9) = '1' else
s_sample_index((c_ind_width - 1) downto 10) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 10))
when length_kern_reg(10) = '1' else
s_sample_index((c_ind_width - 1) downto 11) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 11))
when length_kern_reg(11) = '1' else
s_sample_index((c_ind_width - 1) downto 12) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 12))
when length_kern_reg(12) = '1' else
s_sample_index((c_ind_width - 1) downto 13) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 13))
when length_kern_reg(13) = '1' else
s_sample_index_rev;
s_addr_r_m0_tmp(0) <= s_imag_part;
s_addr_r_m1_tmp(0) <= s_imag_part;
p_addr_delay : process (clk)
begin -- process p_addr_pipe
if rising_edge(clk) then -- rising clock edge
s_dsp_bus.addr_r_m0 <= s_addr_r_m0_tmp;
s_dsp_bus.addr_m1 <= unsigned(bitbit_and(std_logic_vector(s_addr_r_m1_tmp),
std_logic_vector(s_mask_reg)));
end if;
end process p_addr_delay;
s_dsp_bus.addr_w_m0 <= s_addr_pipe(c_addr_pipe_depth - 1);
s_dsp_bus.wr_en_m0 <= s_wr_pipe(c_addr_pipe_depth - 1);
-- specific index relations
s_length <= unsigned(length_reg);
-- left shift because real length is double (complex values)
s_length_kern <= unsigned(length_kern_reg((cmdreg_data_width - 2) downto 0) & '0');
s_mask_reg <= s_length_kern - 1;
-- s_module <= module(signed(s_data_y1), signed(s_data_y2));
end archi_dotcmul;
|
entity test_ is end;
|
-----LIBRARIES-----
library ieee;
use ieee.std_logic_1164.all;
-----ENTITY-----
entity Binary_7_Segment is
port (bin : in std_logic_vector(3 downto 0);
seg : out std_logic_vector(6 downto 0)
);
end Binary_7_Segment;
architecture binToHex of Binary_7_Segment is
begin
with bin select
seg <= "1000000" when "0000", -- 0
"1111001" when "0001", -- 1
"0100100" when "0010", -- 2
"0110000" when "0011", -- 3
"0011001" when "0100", -- 4
"0010010" when "0101", -- 5
"0000010" when "0110", -- 6
"1111000" when "0111", -- 7
"0000000" when "1000", -- 8
"0011000" when "1001", -- 9
"1111111" when others;
end binToHex; |
-----LIBRARIES-----
library ieee;
use ieee.std_logic_1164.all;
-----ENTITY-----
entity Binary_7_Segment is
port (bin : in std_logic_vector(3 downto 0);
seg : out std_logic_vector(6 downto 0)
);
end Binary_7_Segment;
architecture binToHex of Binary_7_Segment is
begin
with bin select
seg <= "1000000" when "0000", -- 0
"1111001" when "0001", -- 1
"0100100" when "0010", -- 2
"0110000" when "0011", -- 3
"0011001" when "0100", -- 4
"0010010" when "0101", -- 5
"0000010" when "0110", -- 6
"1111000" when "0111", -- 7
"0000000" when "1000", -- 8
"0011000" when "1001", -- 9
"1111111" when others;
end binToHex; |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY Mem IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END Mem;
ARCHITECTURE Mem_arch OF Mem IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Mem_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Mem_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Mem_arch : ARCHITECTURE IS "Mem,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Mem_arch: ARCHITECTURE IS "Mem,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=Mem.mif,C_INIT_FILE=Mem.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=131072,C_READ_DEPTH_A=131072,C_ADDRA_WIDTH=17,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=131072,C_READ_DEPTH_B=131072,C_ADDRB_WIDTH=17,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=32,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.5485 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "Mem.mif",
C_INIT_FILE => "Mem.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 131072,
C_READ_DEPTH_A => 131072,
C_ADDRA_WIDTH => 17,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 131072,
C_READ_DEPTH_B => 131072,
C_ADDRB_WIDTH => 17,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "32",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.5485 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 17)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END Mem_arch;
|
package fifo_pkg is
end package;
library ieee;
package fifo_pkg is
end package;
-- Comment
package fifo_pkg is
end package;
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity receive_frame_buffer_tb is
end receive_frame_buffer_tb;
architecture write_sequence of receive_frame_buffer_tb is
constant CLK_PERIOD : time := 10 ns;
constant UUT_WORD_COUNT_MAX : natural := 11;
constant UUT_WIDTH : natural := 8;
signal clk, clr, store : std_logic;
signal complete, full : std_logic;
signal word : std_logic_vector(UUT_WIDTH -1 downto 0);
signal frame : std_logic_vector(UUT_WORD_COUNT_MAX*UUT_WIDTH -1 downto 0);
procedure clear (signal clr : out std_logic;
signal store : out std_logic
) is
begin
clr <= '1';
store <= '1';
wait for CLK_PERIOD;
end clear;
procedure send_word (constant word_arg : in std_logic_vector(UUT_WIDTH -1 downto 0);
signal word : out std_logic_vector(UUT_WIDTH -1 downto 0);
signal clr : out std_logic;
signal store : out std_logic
) is
begin
clr <= '0';
store <= '1';
word <= word_arg;
wait for CLK_PERIOD;
end send_word;
begin
--**************************************
-- instantiation of unit under test
--**************************************
UUT : entity work.receive_frame_buffer
generic map (
WIDTH => UUT_WIDTH ,
WORD_COUNT_MAX => UUT_WORD_COUNT_MAX
) port map (
clk_i => clk,
clear_i => clr,
store_i => store,
frame_complete_o => complete,
full_o => full,
word_i => word,
frame_o => frame
);
--*****************************
-- clock generator process
--*****************************
CLOCK_GEN_PROC : process is
begin
clk <= '0';
wait for CLK_PERIOD/2;
clk <= '1';
wait for CLK_PERIOD/2;
end process CLOCK_GEN_PROC;
--*******************************
-- stimuli generator process
--*******************************
STIMULI_GEN_PROC : process is
begin
-- hold in reset for 100 ns
clr <= '1';
store <= '0';
word <= x"00";
wait for 100 ns;
--******************
-- send MCU_SEL
--******************
assert false report "will now send MCU_SEL" severity note;
send_word(word_arg => x"8A", word => word, clr => clr, store => store);
send_word(word_arg => x"55", word => word, clr => clr, store => store);
clear(clr => clr, store => store);
--**********************
-- send REGISTER_WR
--**********************
assert false report "will now send REGISTER_WR" severity note;
send_word(word_arg => x"8A", word => word, clr => clr, store => store);
send_word(word_arg => x"66", word => word, clr => clr, store => store);
-- data
send_word(word_arg => x"00", word => word, clr => clr, store => store);
send_word(word_arg => x"11", word => word, clr => clr, store => store);
send_word(word_arg => x"22", word => word, clr => clr, store => store);
send_word(word_arg => x"33", word => word, clr => clr, store => store);
-- address
send_word(word_arg => x"44", word => word, clr => clr, store => store);
send_word(word_arg => x"AA", word => word, clr => clr, store => store);
send_word(word_arg => x"BB", word => word, clr => clr, store => store);
send_word(word_arg => x"CC", word => word, clr => clr, store => store);
-- parity (correct)
send_word(word_arg => x"99", word => word, clr => clr, store => store);
-- clear
clear(clr => clr, store => store);
wait; -- forever
end process STIMULI_GEN_PROC;
end write_sequence;
|
entity tb_var04 is
end tb_var04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var04 is
signal clk : std_logic;
signal mask : std_logic_vector (1 downto 0);
signal val : std_logic_vector (15 downto 0);
signal res : std_logic_vector (15 downto 0);
begin
dut: entity work.var04
port map (
mask => mask,
val => val,
res => res);
process
begin
mask <= "11";
val <= x"aa_bb";
wait for 1 ns;
assert res = x"aa_bb" severity failure;
mask <= "00";
val <= x"12_34";
wait for 1 ns;
assert res = x"00_00" severity failure;
mask <= "10";
val <= x"12_34";
wait for 1 ns;
assert res = x"12_00" severity failure;
wait;
end process;
end behav;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004-2008 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.ml50x.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal bus_error : std_logic_vector (1 downto 0);
signal sram_flash_addr : std_logic_vector(23 downto 0);
signal address : std_logic_vector(24 downto 0);
signal sram_flash_data, data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_oen : std_ulogic;
signal flash_oen : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_cen : std_logic;
signal flash_adv_n : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic_vector(1 downto 0);
signal ddr_clkb : std_logic_vector(1 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqsp : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
signal ddr_dq2 : std_logic_vector (63 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(13 downto 0); -- I/O port
signal led : std_logic_vector(12 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_int : std_ulogic := '1';
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal usb_csn, usb_rstn : std_logic;
signal iic_scl_main, iic_sda_main : std_logic;
signal iic_scl_dvi, iic_sda_dvi : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_logic;
signal tft_lcd_clk_n : std_logic;
signal tft_lcd_hsync : std_logic;
signal tft_lcd_vsync : std_logic;
signal tft_lcd_de : std_logic;
signal tft_lcd_reset_b : std_logic;
signal sace_usb_a : std_logic_vector(6 downto 0);
signal sace_mpce : std_ulogic;
signal sace_usb_d : std_logic_vector(15 downto 0);
signal sace_usb_oen : std_ulogic;
signal sace_usb_wen : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk_200_p : std_ulogic := '0';
signal clk_200_n : std_ulogic := '1';
signal sysace_clk_in : std_ulogic := '0';
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
clk_200_p <= not clk_200_p after 2.5 ns;
clk_200_n <= not clk_200_n after 2.5 ns;
sysace_clk_in <= not sysace_clk_in after 15 ns;
rxd1 <= 'H'; gpio(11) <= 'L';
sram_clk_fb <= sram_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl_main <= 'H'; iic_sda_main <= 'H';
iic_scl_dvi <= 'H'; iic_sda_dvi <= 'H';
sace_usb_d <= (others => 'H'); sysace_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map (sys_rst_in, sys_clk, clk_200_p, clk_200_n, sysace_clk_in,
sram_flash_addr, sram_flash_data, sram_cen, sram_bw, sram_oen,
sram_flash_we_n, flash_cen, flash_oen, flash_adv_n,sram_clk,
sram_clk_fb, sram_mode, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, led, bus_error,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_int,
ps2_keyb_clk, ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data,
usb_csn, usb_rstn,
iic_scl_main, iic_sda_main,
iic_scl_dvi, iic_sda_dvi,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
sace_usb_a, sace_mpce, sace_usb_d, sace_usb_oen, sace_usb_wen,
sysace_mpirq
);
-- ddr2mem : for i in 0 to 3 generate
-- u1 : ddr2
-- PORT MAP(
-- ck => ddr_clk(0), ck_n => ddr_clkb(0), cke => ddr_cke(0), cs_n => ddr_csb(0),
-- ras_n => ddr_rasb, cas_n => ddr_casb, we_n => ddr_web,
-- dm_rdqs => ddr_dm(i*2+1 downto i*2), ba => ddr_ba,
-- addr => ddr_ad(12 downto 0), dq => ddr_dq(i*16+15 downto i*16),
-- dqs => ddr_dqsp(i*2+1 downto i*2), dqs_n => ddr_dqsn(i*2+1 downto i*2),
-- rdqs_n => ddr_rdqs(i*2+1 downto i*2), odt => ddr_odt(0));
-- end generate;
ddr2ranks: for j in 0 to CS_NUM-1 generate
-- ddr2chips: for i in 0 to 3 generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => 3-i, fname => sdramfile, fdelay => 100*CFG_MIG_DDR2)
-- port map (DQ => ddr_dq2(i*16+15 downto i*16), LDQS => ddr_dqsp(i*2),
-- LDQSB => ddr_dqsn(i*2), UDQS => ddr_dqsp(i*2+1),
-- UDQSB => ddr_dqsn(i*2+1), LDM => ddr_dm(i*2),
-- WEB => ddr_web, CASB => ddr_casb, RASB => ddr_rasb, CSB => ddr_csb(j),
-- BA => ddr_ba(1 downto 0), ADDR => ddr_ad(12 downto 0), CKE => ddr_cke(j),
-- CLK => ddr_clk(j), CLKB => ddr_clkb(j), UDM => ddr_dm(i*2+1));
-- end generate;
ddr0 : ddr2ram
generic map(width => 64, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>0, density => 2,
lddelay => 100 us * CFG_MIG_DDR2)
port map (ck => ddr_clk(j), ckn => ddr_clkb(j), cke => ddr_cke(j), csn => ddr_csb(j),
odt => ddr_odt(j), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba(1 downto 0), a => ddr_ad(12 downto 0), dq => ddr_dq2,
dqs => ddr_dqsp, dqsn =>ddr_dqsn);
end generate;
nodqdel : if (CFG_MIG_DDR2 = 1) generate
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 0.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
dqdel : if (CFG_MIG_DDR2 = 0) generate
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 4.5)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
sram01 : for i in 0 to 1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(15-i*8 downto 8-i*8),
sram_cen, sram_bw(i+2), sram_oen);
end generate;
sram23 : for i in 2 to 3 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(47-i*8 downto 40-i*8),
sram_cen, sram_bw(i-2), sram_oen);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(15 downto 0),
gnd, gnd, flash_cen, sram_flash_we_n, flash_oen);
phy0 : if (CFG_GRETH = 1) generate
phy_mii_data <= 'H';
p0: phy
generic map (address => 7)
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
phy_tx_er, phy_mii_clk, phy_gtx_clk);
end generate;
-- p0: phy
-- port map(rst, led_cfg, open, etx_clk, erx_clk, erxd, erx_dv,
-- erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc);
i0: i2c_slave_model
port map (iic_scl_main, iic_sda_main);
iuerr : process
begin
wait for 5000 ns;
if to_x01(bus_error(0)) = '0' then wait on bus_error; end if;
assert (to_x01(bus_error(0)) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= sram_flash_data(15 downto 0) & sram_flash_data(31 downto 16);
address <= sram_flash_addr & '0';
test0 : grtestmod
port map ( sys_rst_in, sys_clk, bus_error(0), sram_flash_addr(20 downto 1), data,
iosn, flash_oen, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
-- ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
data <= buskeep(data), (others => 'H') after 250 ns;
end ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc600.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:40 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:58 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:18 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00600ent IS
END c03s04b01x00p01n01i00600ent;
ARCHITECTURE c03s04b01x00p01n01i00600arch OF c03s04b01x00p01n01i00600ent IS
type time_vector is array (natural range <>) of time;
type time_vector_file is file of time_vector;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : time_vector_file open read_mode is "iofile.27";
variable v : time_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= (1 ns,2 ns,3 ns,4 ns)) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00600"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00600 - File reading operation (time_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00600arch;
|
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