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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc64.vhd,v 1.2 2001-10-26 16:29:58 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p02n01i00064ent IS
END c04s03b01x02p02n01i00064ent;
ARCHITECTURE c04s03b01x02p02n01i00064arch OF c04s03b01x02p02n01i00064ent IS
signal C1 : Boolean := TRUE; -- No_failure_here
signal C2 : bit := '1'; -- No_failure_here
signal C3 : integer := 12345; -- No_failure_here
signal C4 : positive := 54321; -- No_failure_here
signal C5 : natural := 12121; -- No_failure_here
signal C6 : real := 1.345; -- No_failure_here
signal C7 : character := 'N'; -- No_failure_here
signal C8 : time := 100 ns; -- No_failure_here
signal C9 : String (1 to 8) := "AAAAAAAA"; -- No_failure_here
signal C10 : bit_vector(0 to 7) := "11111111"; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( C1 = TRUE and
C2 = '1' and
C3 = 12345 and
C4 = 54321 and
C5 = 12121 and
C6 = 1.345 and
C7 = 'N' and
C8 = 100 ns and
C9 = "AAAAAAAA" and
C10 = "11111111" )
report "***PASSED TEST:c04s03b01x02p02n01i00064"
severity NOTE;
assert ( C1 = TRUE and
C2 = '1' and
C3 = 12345 and
C4 = 54321 and
C5 = 12121 and
C6 = 1.345 and
C7 = 'N' and
C8 = 100 ns and
C9 = "AAAAAAAA" and
C10 = "11111111" )
report "***FAILED TEST: c04s03b01x02p02n01i00064 - Syntactic test for signal assignment failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x02p02n01i00064arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc64.vhd,v 1.2 2001-10-26 16:29:58 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p02n01i00064ent IS
END c04s03b01x02p02n01i00064ent;
ARCHITECTURE c04s03b01x02p02n01i00064arch OF c04s03b01x02p02n01i00064ent IS
signal C1 : Boolean := TRUE; -- No_failure_here
signal C2 : bit := '1'; -- No_failure_here
signal C3 : integer := 12345; -- No_failure_here
signal C4 : positive := 54321; -- No_failure_here
signal C5 : natural := 12121; -- No_failure_here
signal C6 : real := 1.345; -- No_failure_here
signal C7 : character := 'N'; -- No_failure_here
signal C8 : time := 100 ns; -- No_failure_here
signal C9 : String (1 to 8) := "AAAAAAAA"; -- No_failure_here
signal C10 : bit_vector(0 to 7) := "11111111"; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( C1 = TRUE and
C2 = '1' and
C3 = 12345 and
C4 = 54321 and
C5 = 12121 and
C6 = 1.345 and
C7 = 'N' and
C8 = 100 ns and
C9 = "AAAAAAAA" and
C10 = "11111111" )
report "***PASSED TEST:c04s03b01x02p02n01i00064"
severity NOTE;
assert ( C1 = TRUE and
C2 = '1' and
C3 = 12345 and
C4 = 54321 and
C5 = 12121 and
C6 = 1.345 and
C7 = 'N' and
C8 = 100 ns and
C9 = "AAAAAAAA" and
C10 = "11111111" )
report "***FAILED TEST: c04s03b01x02p02n01i00064 - Syntactic test for signal assignment failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x02p02n01i00064arch;
|
-- From OSVVM
--
use std.textio.all ;
package NamePkg is
type NamePType is protected
procedure Set (NameIn : String) ;
impure function Get (DefaultName : string := "") return string ;
impure function GetOpt return string ;
impure function IsSet return boolean ;
procedure Clear ; -- clear name
procedure Deallocate ; -- effectively alias to clear name
end protected NamePType ;
end package NamePkg ;
package body NamePkg is
type NamePType is protected body
variable NamePtr : line ;
------------------------------------------------------------
procedure Set (NameIn : String) is
------------------------------------------------------------
begin
deallocate(NamePtr) ;
NamePtr := new string'(NameIn) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (DefaultName : string := "") return string is
------------------------------------------------------------
begin
if NamePtr = NULL then
return DefaultName ;
else
return NamePtr.all ;
end if ;
end function Get ;
------------------------------------------------------------
impure function GetOpt return string is
------------------------------------------------------------
begin
if NamePtr = NULL then
return NUL & "" ;
else
return NamePtr.all ;
end if ;
end function GetOpt ;
------------------------------------------------------------
impure function IsSet return boolean is
------------------------------------------------------------
begin
return NamePtr /= NULL ;
end function IsSet ;
------------------------------------------------------------
procedure Clear is -- clear name
------------------------------------------------------------
begin
deallocate(NamePtr) ;
end procedure Clear ;
------------------------------------------------------------
procedure Deallocate is -- clear name
------------------------------------------------------------
begin
Clear ;
end procedure Deallocate ;
end protected body NamePType ;
end package body NamePkg ;
-------------------------------------------------------------------------------
use work.namepkg.all;
package other_pkg is
type otherptype is protected
procedure do_clear;
end protected;
end package;
package body other_pkg is
type otherptype is protected body
variable n : nameptype;
procedure do_clear is
begin
n.clear;
end procedure;
end protected body;
end package body;
-------------------------------------------------------------------------------
entity link3 is
end entity;
use work.other_pkg.all;
architecture test of link3 is
shared variable p : otherptype;
begin
p1: process is
begin
p.do_clear;
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cache is
Generic (WIDTH : natural := 13; -- Length of address
DWIDTH : natural := 13; -- Length of one entry
CACHE_SIZE : natural := 4); -- Log2 of number of entries in the cache
Port ( clk, reset : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
din : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
push : in STD_LOGIC;
valid : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR (DWIDTH-1 downto 0));
end cache;
architecture Behavioral of cache is
type cache_type_data is array(0 to 2**CACHE_SIZE-1) of std_logic_vector(DWIDTH-1 downto 0);
type cache_type_tag is array(0 to 2**CACHE_SIZE-1) of std_logic_vector(WIDTH-1 downto CACHE_SIZE);
signal last_used : std_logic_vector(2**CACHE_SIZE-1 downto 0);
signal valid0, valid1 : std_logic_vector(2**CACHE_SIZE-1 downto 0);
signal cache0_d, cache1_d : cache_type_data;
signal cache0_t, cache1_t : cache_type_tag;
begin
process(clk, reset, addr, din, push)
begin
if rising_edge(clk) then
if reset = '1' then
for I in 0 to 2**CACHE_SIZE-1 loop
valid0(to_integer(to_unsigned(I, CACHE_SIZE))) <= '0';
valid1(to_integer(to_unsigned(I, CACHE_SIZE))) <= '0';
end loop;
end if;
-- Write to free location or replace randomly
if push = '1' then
if valid0(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = '0' then
cache0_t(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= addr(WIDTH-1 downto CACHE_SIZE);
cache0_d(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= din;
valid0(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '1';
last_used(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '0';
elsif valid1(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = '0' then
cache1_t(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= addr(WIDTH-1 downto CACHE_SIZE);
cache1_d(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= din;
valid1(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '1';
last_used(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '1';
else
-- Both locations are already occupied so replace the least recently used
if last_used(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = '0' then
cache1_t(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= addr(WIDTH-1 downto CACHE_SIZE);
cache1_d(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= din;
valid1(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '1';
last_used(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '1';
else
cache0_t(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= addr(WIDTH-1 downto CACHE_SIZE);
cache0_d(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= din;
valid0(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '1';
last_used(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '0';
end if;
end if;
end if;
-- Set output if tag matches and entry is valid
if valid0(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = '1'
and cache0_t(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = addr(WIDTH-1 downto CACHE_SIZE) then
valid <= '1';
dout <= cache0_d(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0))));
elsif valid1(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = '1'
and cache1_t(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = addr(WIDTH-1 downto CACHE_SIZE) then
valid <= '1';
dout <= cache1_d(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0))));
else
valid <= '0';
dout <= (others => '-');
end if;
end if;
end process;
end Behavioral;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_7_full_dsp_32_u : component convolve_kernel_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_7_full_dsp_32_u : component convolve_kernel_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_7_full_dsp_32_u : component convolve_kernel_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_7_full_dsp_32_u : component convolve_kernel_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_7_full_dsp_32_u : component convolve_kernel_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:25:50 07/14/2014
-- Design Name:
-- Module Name: key_expansion_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity key_expansion is
port(
clk : in std_logic;
reset : in std_logic;
exp_start : in std_logic;
exp_end : out std_logic;
address_in : in std_logic_vector(3 downto 0);
key_in : in state;
key_out : out state
);
end key_expansion;
architecture Structural of key_expansion is
signal y_1_2, y_3_4 : std_logic_vector (1 downto 0);
signal y_we : std_logic;
signal x_comp : std_logic;
signal count : byte;
signal round_key : state;
signal rcon_in : byte;
begin
rcon_in <= count + 1;
expander : entity work.key_expander port map(clk => clk,
reset => reset,
y => y_1_2,
rcon_in => rcon_in,
key_in => key_in,
key_out => round_key
);
counter : entity work.counter port map (clk => clk,
reset => reset,
y => y_3_4,
x => x_comp,
d_out => count
);
ram : entity work.dp_ram port map(clk => clk,
address_read => address_in,
address_write => count (3 downto 0),
en_write => y_we,
din_write => round_key,
q => key_out
);
control_unit : entity work.key_expansion_cu port map (clk => clk,
reset => reset,
y_1_2 => y_1_2,
y_3_4 => y_3_4,
y_we => y_we,
y_end => exp_end,
x_start => exp_start,
x_comp => x_comp
);
end Structural;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:01:55 11/20/2015
-- Design Name:
-- Module Name: C:/Users/Bailey/Desktop/Nibble_Knowledge_CPU(1)/tb_io_mapping.vhd
-- Project Name: Nibble_Knowledge_CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: io_mapping
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_io_mapping IS
END tb_io_mapping;
ARCHITECTURE behavior OF tb_io_mapping IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT io_mapping
PORT(
address : IN std_logic_vector(15 downto 0);
data_in : IN std_logic_vector(3 downto 0);
data_out : OUT std_logic_vector(3 downto 0);
ram_data : INOUT std_logic_vector(3 downto 0);
bus_chip_select : OUT std_logic_vector(3 downto 0);
store : IN std_logic;
bus_data : INOUT std_logic_vector(3 downto 0);
bus_ready : IN std_logic;
oe : OUT std_logic;
bus_parity : IN std_logic;
clk : IN std_logic;
rst : IN std_logic
);
END COMPONENT;
--Inputs
signal address : std_logic_vector(15 downto 0) := (others => '0');
signal data_in : std_logic_vector(3 downto 0) := (others => '0');
signal store : std_logic := '0';
signal bus_ready : std_logic := '0';
signal bus_parity : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--BiDirs
signal ram_data : std_logic_vector(3 downto 0);
signal bus_data : std_logic_vector(3 downto 0);
--Outputs
signal data_out : std_logic_vector(3 downto 0);
signal bus_chip_select : std_logic_vector(3 downto 0);
signal oe : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: io_mapping PORT MAP (
address => address,
data_in => data_in,
data_out => data_out,
ram_data => ram_data,
bus_chip_select => bus_chip_select,
store => store,
bus_data => bus_data,
bus_ready => bus_ready,
oe => oe,
bus_parity => bus_parity,
clk => clk,
rst => rst
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
rst <= '1';
wait for clk_period*10;
rst <= '0';
-- Test that a store to status only write the lower 2 bits
wait for clk_period*5;
address <= "0000000000000001";
store <= '1';
data_in <= "1101";
-- Test that a read from data reads corretly
wait for clk_period*5;
store <= '0';
address <= "0000000000000010";
data_in <= "0010";
-- Test that a write to the data reg works while CPU is doing other things
wait for clk_period*5;
address <= "0000000100100011";
ram_data <= "0110";
bus_data <= "1011";
wait for clk_period*5;
bus_data <= "0101";
wait for clk_period*5;
bus_data <= "ZZZZ";
wait for clk_period*5;
address <= "0000000000000001";
store <= '1';
data_in <= "0000";
wait for clk_period*5;
store <= '0';
wait;
end process;
END;
|
architecture RTL of FIFO is
SIGNAL sig1 : std_logic;
SIGNAL sig2 : std_logic;
-- Violations below
SIGNAL sig1 : std_logic;
SIGNAL sig2 : std_logic;
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc97.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n02i00097ent IS
END c04s03b02x00p29n02i00097ent;
ARCHITECTURE c04s03b02x00p29n02i00097arch OF c04s03b02x00p29n02i00097ent IS
signal P1 : BIT := '1' ;
signal P2 : BIT;
BEGIN
TESTING: PROCESS
procedure read_write(signal S1 : in BIT; signal S2 : out BIT) is
begin
if (S1 = '1' and not S1'STABLE) then
S2 <= '1' after 10 ns;
end if;
end;
BEGIN
read_write(P1, P2);
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n02i00097 - Attribute STABLE can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n02i00097arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc97.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n02i00097ent IS
END c04s03b02x00p29n02i00097ent;
ARCHITECTURE c04s03b02x00p29n02i00097arch OF c04s03b02x00p29n02i00097ent IS
signal P1 : BIT := '1' ;
signal P2 : BIT;
BEGIN
TESTING: PROCESS
procedure read_write(signal S1 : in BIT; signal S2 : out BIT) is
begin
if (S1 = '1' and not S1'STABLE) then
S2 <= '1' after 10 ns;
end if;
end;
BEGIN
read_write(P1, P2);
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n02i00097 - Attribute STABLE can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n02i00097arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc97.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n02i00097ent IS
END c04s03b02x00p29n02i00097ent;
ARCHITECTURE c04s03b02x00p29n02i00097arch OF c04s03b02x00p29n02i00097ent IS
signal P1 : BIT := '1' ;
signal P2 : BIT;
BEGIN
TESTING: PROCESS
procedure read_write(signal S1 : in BIT; signal S2 : out BIT) is
begin
if (S1 = '1' and not S1'STABLE) then
S2 <= '1' after 10 ns;
end if;
end;
BEGIN
read_write(P1, P2);
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n02i00097 - Attribute STABLE can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n02i00097arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY rs232_tb IS
END rs232_tb;
ARCHITECTURE behavior OF rs232_tb IS
COMPONENT RS232
PORT(
clk : IN std_logic;
Entrada_8bits : IN std_logic_vector(7 downto 0);
Activador_Envio_Mensaje : IN std_logic;
Salida_1bit : OUT std_logic;
Entrada_1bit : IN std_logic;
Mensaje_8bits : OUT std_logic_vector(7 downto 0);
Activador_Entrega_Mensaje : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal Entrada_8bits : std_logic_vector(7 downto 0) := (others => '0');
signal Activador_Envio_Mensaje : std_logic := '0';
signal Entrada_1bit : std_logic := '0';
--Outputs
signal Salida_1bit : std_logic;
signal Mensaje_8bits : std_logic_vector(7 downto 0);
signal Activador_Entrega_Mensaje : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RS232 PORT MAP (
clk => clk,
Entrada_8bits => Entrada_8bits,
Activador_Envio_Mensaje => Activador_Envio_Mensaje,
Salida_1bit => Salida_1bit,
Entrada_1bit => Entrada_1bit,
Mensaje_8bits => Mensaje_8bits,
Activador_Entrega_Mensaje => Activador_Entrega_Mensaje
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-------------------------------------------------------------
-- Recibo un 11111111 con paridad 0
-------------------------------------------------------------
-- IDLE --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Recibo <= '0';
wait for 0.10416 ms;
-- 8 BITS DE INFORMACION --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Recibo <= '0';
wait for 0.10416 ms;
-- BIT DE PARADA --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-------------------------------------------------------------
-- Recibo un 01111110 con paridad 1 MALO!!!!!!
-------------------------------------------------------------
-- IDLE --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Recibo <= '0';
wait for 0.10416 ms;
-- 8 BITS DE INFORMACION --
Recibo <= '0';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE PARADA --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-------------------------------------------------------------
-- Recibo un 10110110 con paridad 1
-------------------------------------------------------------
-- IDLE --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE INICIO --
Recibo <= '0';
wait for 0.10416 ms;
-- 8 BITS DE INFORMACION --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '0';
wait for 0.10416 ms;
-- BIT DE PARIDAD --
Recibo <= '1';
wait for 0.10416 ms;
-- BIT DE PARADA --
Recibo <= '1';
wait for 0.10416 ms;
Recibo <= '1';
wait for 0.10416 ms;
wait;
end process;
END; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc329.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p05n01i00329ent IS
END c03s02b01x00p05n01i00329ent;
ARCHITECTURE c03s02b01x00p05n01i00329arch OF c03s02b01x00p05n01i00329ent IS
type bit_vctor is array ( range <>) of bit; -- Failure_here
type str_vctor is array (natural range <>) of character;
type matrix is array (integer range <>) of real;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p05n01i00329 - The type mark in the unconstrained array definition is missing."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p05n01i00329arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc329.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p05n01i00329ent IS
END c03s02b01x00p05n01i00329ent;
ARCHITECTURE c03s02b01x00p05n01i00329arch OF c03s02b01x00p05n01i00329ent IS
type bit_vctor is array ( range <>) of bit; -- Failure_here
type str_vctor is array (natural range <>) of character;
type matrix is array (integer range <>) of real;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p05n01i00329 - The type mark in the unconstrained array definition is missing."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p05n01i00329arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc329.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p05n01i00329ent IS
END c03s02b01x00p05n01i00329ent;
ARCHITECTURE c03s02b01x00p05n01i00329arch OF c03s02b01x00p05n01i00329ent IS
type bit_vctor is array ( range <>) of bit; -- Failure_here
type str_vctor is array (natural range <>) of character;
type matrix is array (integer range <>) of real;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p05n01i00329 - The type mark in the unconstrained array definition is missing."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p05n01i00329arch;
|
--
-- Serial reset for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
--
-- This module causes a synchronous reset when we receive 0xFF at 300 baud.
-- Hopefully no other speed setting will cause this.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 100
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end entity zpuino_serialreset;
architecture behave of zpuino_serialreset is
constant rstcount_val: integer := ((SYSTEM_CLOCK_MHZ*1000000)/300)*8;
signal rstcount: integer;
signal rstcount_zero_q: std_logic;
begin
rstout<='1' when rstin='1' or rstcount_zero_q='1' else '0';
process(clk)
begin
if rising_edge(clk) then
if rstin='1' then
rstcount <= rstcount_val;
rstcount_zero_q <= '0';
else
if rx='1' then
rstcount <= rstcount_val;
else
if rstcount/=0 then
rstcount <= rstcount - 1;
rstcount_zero_q<='0';
else
rstcount_zero_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
-------------------------------------------------------------------------------
-- $Id$
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision$
-- Date: $Date$
--
-- History:
-- goran 2006-10-27 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library mdm_v3_1;
use mdm_v3_1.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.ipif_pkg.SLV64_ARRAY_TYPE;
use proc_common_v4_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use proc_common_v4_0.ipif_pkg.calc_num_ce;
library axi_lite_ipif_v2_0;
use axi_lite_ipif_v2_0.axi_lite_ipif;
entity MDM is
generic (
C_FAMILY : string := "virtex7";
C_JTAG_CHAIN : integer := 2;
C_USE_BSCAN : integer := 0;
C_USE_CONFIG_RESET : integer := 0;
C_INTERCONNECT : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_FFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"0000_0000";
C_MB_DBG_PORTS : integer := 1;
C_DBG_REG_ACCESS : integer := 0;
C_DBG_MEM_ACCESS : integer := 0;
C_USE_UART : integer := 1;
C_USE_CROSS_TRIGGER : integer := 0;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_THREAD_ID_WIDTH : integer := 1;
C_DATA_SIZE : integer range 32 to 32 := 32
);
port (
-- Global signals
Config_Reset : in std_logic := '0';
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- External cross trigger signals
Trig_In_0 : in std_logic;
Trig_Ack_In_0 : out std_logic;
Trig_Out_0 : out std_logic;
Trig_Ack_Out_0 : in std_logic;
Trig_In_1 : in std_logic;
Trig_Ack_In_1 : out std_logic;
Trig_Out_1 : out std_logic;
Trig_Ack_Out_1 : in std_logic;
Trig_In_2 : in std_logic;
Trig_Ack_In_2 : out std_logic;
Trig_Out_2 : out std_logic;
Trig_Ack_Out_2 : in std_logic;
Trig_In_3 : in std_logic;
Trig_Ack_In_3 : out std_logic;
Trig_Out_3 : out std_logic;
Trig_Ack_Out_3 : in std_logic;
-- AXI slave signals
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Bus master signals
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
LMB_Data_Addr_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_0 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_0 : out std_logic;
LMB_Read_Strobe_0 : out std_logic;
LMB_Write_Strobe_0 : out std_logic;
LMB_Ready_0 : in std_logic;
LMB_Wait_0 : in std_logic;
LMB_CE_0 : in std_logic;
LMB_UE_0 : in std_logic;
LMB_Byte_Enable_0 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_1 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_1 : out std_logic;
LMB_Read_Strobe_1 : out std_logic;
LMB_Write_Strobe_1 : out std_logic;
LMB_Ready_1 : in std_logic;
LMB_Wait_1 : in std_logic;
LMB_CE_1 : in std_logic;
LMB_UE_1 : in std_logic;
LMB_Byte_Enable_1 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_2 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_2 : out std_logic;
LMB_Read_Strobe_2 : out std_logic;
LMB_Write_Strobe_2 : out std_logic;
LMB_Ready_2 : in std_logic;
LMB_Wait_2 : in std_logic;
LMB_CE_2 : in std_logic;
LMB_UE_2 : in std_logic;
LMB_Byte_Enable_2 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_3 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_3 : out std_logic;
LMB_Read_Strobe_3 : out std_logic;
LMB_Write_Strobe_3 : out std_logic;
LMB_Ready_3 : in std_logic;
LMB_Wait_3 : in std_logic;
LMB_CE_3 : in std_logic;
LMB_UE_3 : in std_logic;
LMB_Byte_Enable_3 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_4 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_4 : out std_logic;
LMB_Read_Strobe_4 : out std_logic;
LMB_Write_Strobe_4 : out std_logic;
LMB_Ready_4 : in std_logic;
LMB_Wait_4 : in std_logic;
LMB_CE_4 : in std_logic;
LMB_UE_4 : in std_logic;
LMB_Byte_Enable_4 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_5 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_5 : out std_logic;
LMB_Read_Strobe_5 : out std_logic;
LMB_Write_Strobe_5 : out std_logic;
LMB_Ready_5 : in std_logic;
LMB_Wait_5 : in std_logic;
LMB_CE_5 : in std_logic;
LMB_UE_5 : in std_logic;
LMB_Byte_Enable_5 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_6 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_6 : out std_logic;
LMB_Read_Strobe_6 : out std_logic;
LMB_Write_Strobe_6 : out std_logic;
LMB_Ready_6 : in std_logic;
LMB_Wait_6 : in std_logic;
LMB_CE_6 : in std_logic;
LMB_UE_6 : in std_logic;
LMB_Byte_Enable_6 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_7 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_7 : out std_logic;
LMB_Read_Strobe_7 : out std_logic;
LMB_Write_Strobe_7 : out std_logic;
LMB_Ready_7 : in std_logic;
LMB_Wait_7 : in std_logic;
LMB_CE_7 : in std_logic;
LMB_UE_7 : in std_logic;
LMB_Byte_Enable_7 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_8 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_8 : out std_logic;
LMB_Read_Strobe_8 : out std_logic;
LMB_Write_Strobe_8 : out std_logic;
LMB_Ready_8 : in std_logic;
LMB_Wait_8 : in std_logic;
LMB_CE_8 : in std_logic;
LMB_UE_8 : in std_logic;
LMB_Byte_Enable_8 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_9 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_9 : out std_logic;
LMB_Read_Strobe_9 : out std_logic;
LMB_Write_Strobe_9 : out std_logic;
LMB_Ready_9 : in std_logic;
LMB_Wait_9 : in std_logic;
LMB_CE_9 : in std_logic;
LMB_UE_9 : in std_logic;
LMB_Byte_Enable_9 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_10 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_10 : out std_logic;
LMB_Read_Strobe_10 : out std_logic;
LMB_Write_Strobe_10 : out std_logic;
LMB_Ready_10 : in std_logic;
LMB_Wait_10 : in std_logic;
LMB_CE_10 : in std_logic;
LMB_UE_10 : in std_logic;
LMB_Byte_Enable_10 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_11 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_11 : out std_logic;
LMB_Read_Strobe_11 : out std_logic;
LMB_Write_Strobe_11 : out std_logic;
LMB_Ready_11 : in std_logic;
LMB_Wait_11 : in std_logic;
LMB_CE_11 : in std_logic;
LMB_UE_11 : in std_logic;
LMB_Byte_Enable_11 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_12 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_12 : out std_logic;
LMB_Read_Strobe_12 : out std_logic;
LMB_Write_Strobe_12 : out std_logic;
LMB_Ready_12 : in std_logic;
LMB_Wait_12 : in std_logic;
LMB_CE_12 : in std_logic;
LMB_UE_12 : in std_logic;
LMB_Byte_Enable_12 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_13 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_13 : out std_logic;
LMB_Read_Strobe_13 : out std_logic;
LMB_Write_Strobe_13 : out std_logic;
LMB_Ready_13 : in std_logic;
LMB_Wait_13 : in std_logic;
LMB_CE_13 : in std_logic;
LMB_UE_13 : in std_logic;
LMB_Byte_Enable_13 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_14 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_14 : out std_logic;
LMB_Read_Strobe_14 : out std_logic;
LMB_Write_Strobe_14 : out std_logic;
LMB_Ready_14 : in std_logic;
LMB_Wait_14 : in std_logic;
LMB_CE_14 : in std_logic;
LMB_UE_14 : in std_logic;
LMB_Byte_Enable_14 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_15 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_15 : out std_logic;
LMB_Read_Strobe_15 : out std_logic;
LMB_Write_Strobe_15 : out std_logic;
LMB_Ready_15 : in std_logic;
LMB_Wait_15 : in std_logic;
LMB_CE_15 : in std_logic;
LMB_UE_15 : in std_logic;
LMB_Byte_Enable_15 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_16 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_16 : out std_logic;
LMB_Read_Strobe_16 : out std_logic;
LMB_Write_Strobe_16 : out std_logic;
LMB_Ready_16 : in std_logic;
LMB_Wait_16 : in std_logic;
LMB_CE_16 : in std_logic;
LMB_UE_16 : in std_logic;
LMB_Byte_Enable_16 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_17 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_17 : out std_logic;
LMB_Read_Strobe_17 : out std_logic;
LMB_Write_Strobe_17 : out std_logic;
LMB_Ready_17 : in std_logic;
LMB_Wait_17 : in std_logic;
LMB_CE_17 : in std_logic;
LMB_UE_17 : in std_logic;
LMB_Byte_Enable_17 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_18 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_18 : out std_logic;
LMB_Read_Strobe_18 : out std_logic;
LMB_Write_Strobe_18 : out std_logic;
LMB_Ready_18 : in std_logic;
LMB_Wait_18 : in std_logic;
LMB_CE_18 : in std_logic;
LMB_UE_18 : in std_logic;
LMB_Byte_Enable_18 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_19 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_19 : out std_logic;
LMB_Read_Strobe_19 : out std_logic;
LMB_Write_Strobe_19 : out std_logic;
LMB_Ready_19 : in std_logic;
LMB_Wait_19 : in std_logic;
LMB_CE_19 : in std_logic;
LMB_UE_19 : in std_logic;
LMB_Byte_Enable_19 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_20 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_20 : out std_logic;
LMB_Read_Strobe_20 : out std_logic;
LMB_Write_Strobe_20 : out std_logic;
LMB_Ready_20 : in std_logic;
LMB_Wait_20 : in std_logic;
LMB_CE_20 : in std_logic;
LMB_UE_20 : in std_logic;
LMB_Byte_Enable_20 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_21 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_21 : out std_logic;
LMB_Read_Strobe_21 : out std_logic;
LMB_Write_Strobe_21 : out std_logic;
LMB_Ready_21 : in std_logic;
LMB_Wait_21 : in std_logic;
LMB_CE_21 : in std_logic;
LMB_UE_21 : in std_logic;
LMB_Byte_Enable_21 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_22 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_22 : out std_logic;
LMB_Read_Strobe_22 : out std_logic;
LMB_Write_Strobe_22 : out std_logic;
LMB_Ready_22 : in std_logic;
LMB_Wait_22 : in std_logic;
LMB_CE_22 : in std_logic;
LMB_UE_22 : in std_logic;
LMB_Byte_Enable_22 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_23 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_23 : out std_logic;
LMB_Read_Strobe_23 : out std_logic;
LMB_Write_Strobe_23 : out std_logic;
LMB_Ready_23 : in std_logic;
LMB_Wait_23 : in std_logic;
LMB_CE_23 : in std_logic;
LMB_UE_23 : in std_logic;
LMB_Byte_Enable_23 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_24 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_24 : out std_logic;
LMB_Read_Strobe_24 : out std_logic;
LMB_Write_Strobe_24 : out std_logic;
LMB_Ready_24 : in std_logic;
LMB_Wait_24 : in std_logic;
LMB_CE_24 : in std_logic;
LMB_UE_24 : in std_logic;
LMB_Byte_Enable_24 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_25 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_25 : out std_logic;
LMB_Read_Strobe_25 : out std_logic;
LMB_Write_Strobe_25 : out std_logic;
LMB_Ready_25 : in std_logic;
LMB_Wait_25 : in std_logic;
LMB_CE_25 : in std_logic;
LMB_UE_25 : in std_logic;
LMB_Byte_Enable_25 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_26 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_26 : out std_logic;
LMB_Read_Strobe_26 : out std_logic;
LMB_Write_Strobe_26 : out std_logic;
LMB_Ready_26 : in std_logic;
LMB_Wait_26 : in std_logic;
LMB_CE_26 : in std_logic;
LMB_UE_26 : in std_logic;
LMB_Byte_Enable_26 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_27 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_27 : out std_logic;
LMB_Read_Strobe_27 : out std_logic;
LMB_Write_Strobe_27 : out std_logic;
LMB_Ready_27 : in std_logic;
LMB_Wait_27 : in std_logic;
LMB_CE_27 : in std_logic;
LMB_UE_27 : in std_logic;
LMB_Byte_Enable_27 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_28 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_28 : out std_logic;
LMB_Read_Strobe_28 : out std_logic;
LMB_Write_Strobe_28 : out std_logic;
LMB_Ready_28 : in std_logic;
LMB_Wait_28 : in std_logic;
LMB_CE_28 : in std_logic;
LMB_UE_28 : in std_logic;
LMB_Byte_Enable_28 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_29 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_29 : out std_logic;
LMB_Read_Strobe_29 : out std_logic;
LMB_Write_Strobe_29 : out std_logic;
LMB_Ready_29 : in std_logic;
LMB_Wait_29 : in std_logic;
LMB_CE_29 : in std_logic;
LMB_UE_29 : in std_logic;
LMB_Byte_Enable_29 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_30 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_30 : out std_logic;
LMB_Read_Strobe_30 : out std_logic;
LMB_Write_Strobe_30 : out std_logic;
LMB_Ready_30 : in std_logic;
LMB_Wait_30 : in std_logic;
LMB_CE_30 : in std_logic;
LMB_UE_30 : in std_logic;
LMB_Byte_Enable_30 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_31 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_31 : out std_logic;
LMB_Read_Strobe_31 : out std_logic;
LMB_Write_Strobe_31 : out std_logic;
LMB_Ready_31 : in std_logic;
LMB_Wait_31 : in std_logic;
LMB_CE_31 : in std_logic;
LMB_UE_31 : in std_logic;
LMB_Byte_Enable_31 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
-- External BSCAN inputs
-- These signals are used when C_USE_BSCAN = 2 (EXTERNAL)
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
-- External JTAG ports
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM;
architecture IMP of MDM is
function int2std (val : integer) return std_logic is
begin -- function int2std
if (val = 0) then
return '0';
else
return '1';
end if;
end function int2std;
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0) := X"00000000";
constant C_REG_NUM_CE : integer := 4 + 4 * C_DBG_REG_ACCESS;
constant C_REG_DATA_WIDTH : integer := 8 + 24 * C_DBG_REG_ACCESS;
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) :=
(31 downto 5 => '0', 4 => int2std(C_DBG_REG_ACCESS), 3 downto 0 => '1');
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := (
-- Registers Base Address (not used)
ZEROES & C_BASEADDR,
ZEROES & (C_BASEADDR or C_S_AXI_MIN_SIZE)
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (
0 => C_REG_NUM_CE
);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
--------------------------------------------------------------------------
-- Component declarations
--------------------------------------------------------------------------
component MDM_Core
generic (
C_USE_CONFIG_RESET : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8);
port (
-- Global signals
Config_Reset : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
-- AXI IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
-- External Trace Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component MDM_Core;
component bus_master is
generic (
C_M_AXI_DATA_WIDTH : natural;
C_M_AXI_THREAD_ID_WIDTH : natural;
C_M_AXI_ADDR_WIDTH : natural;
C_DATA_SIZE : natural
);
port (
Rd_Start : in std_logic;
Rd_Addr : in std_logic_vector(31 downto 0);
Rd_Len : in std_logic_vector(4 downto 0);
Rd_Size : in std_logic_vector(1 downto 0);
Rd_Exclusive : in std_logic;
Rd_Idle : out std_logic;
Rd_Response : out std_logic_vector(1 downto 0);
Wr_Start : in std_logic;
Wr_Addr : in std_logic_vector(31 downto 0);
Wr_Len : in std_logic_vector(4 downto 0);
Wr_Size : in std_logic_vector(1 downto 0);
Wr_Exclusive : in std_logic;
Wr_Idle : out std_logic;
Wr_Response : out std_logic_vector(1 downto 0);
Data_Rd : in std_logic;
Data_Out : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Exists : out std_logic;
Data_Wr : in std_logic;
Data_In : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Empty : out std_logic;
LMB_Data_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe : out std_logic;
LMB_Read_Strobe : out std_logic;
LMB_Write_Strobe : out std_logic;
LMB_Ready : in std_logic;
LMB_Wait : in std_logic;
LMB_UE : in std_logic;
LMB_Byte_Enable : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WLAST : out std_logic;
M_AXI_WDATA : out std_logic_vector(31 downto 0);
M_AXI_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end component bus_master;
--------------------------------------------------------------------------
-- Functions
--------------------------------------------------------------------------
--
-- The native_bscan function returns the native BSCAN primitive for the given
-- family. This funtion needs to be revised for every new architecture.
--
function native_bscan (C_FAMILY : string)
return proc_common_v4_0.family_support.primitives_type is
begin
if supported(C_FAMILY, u_BSCANE2) then return u_BSCANE2; -- 7 series
else
assert false
report "Function native_bscan : No BSCAN available for " & C_FAMILY
severity error;
return u_BSCANE2; -- To prevent simulator warnings
end if;
end;
-- Returns at least 1
function MakePos (a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
constant C_EN_WIDTH : integer := MakePos(C_MB_DBG_PORTS);
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal tdi : std_logic;
signal reset : std_logic;
signal update : std_logic;
signal capture : std_logic;
signal shift : std_logic;
signal sel : std_logic;
signal drck : std_logic;
signal tdo : std_logic;
signal drck_i : std_logic;
signal update_i : std_logic;
signal dbgreg_drck : std_logic;
signal dbgreg_update : std_logic;
signal dbgreg_select : std_logic;
signal jtag_busy : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
signal bus2ip_cs : std_logic_vector(((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal mb_debug_enabled : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal master_rd_start : std_logic;
signal master_rd_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_rd_len : std_logic_vector(4 downto 0);
signal master_rd_size : std_logic_vector(1 downto 0);
signal master_rd_excl : std_logic;
signal master_rd_idle : std_logic;
signal master_rd_resp : std_logic_vector(1 downto 0);
signal master_wr_start : std_logic;
signal master_wr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_wr_len : std_logic_vector(4 downto 0);
signal master_wr_size : std_logic_vector(1 downto 0);
signal master_wr_excl : std_logic;
signal master_wr_idle : std_logic;
signal master_wr_resp : std_logic_vector(1 downto 0);
signal master_data_rd : std_logic;
signal master_data_out : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_exists : std_logic;
signal master_data_wr : std_logic;
signal master_data_in : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_empty : std_logic;
signal ext_trig_in : std_logic_vector(0 to 3);
signal ext_trig_Ack_In : std_logic_vector(0 to 3);
signal ext_trig_out : std_logic_vector(0 to 3);
signal ext_trig_Ack_Out : std_logic_vector(0 to 3);
--------------------------------------------------------------------------
-- Attibute declarations
--------------------------------------------------------------------------
attribute period : string;
attribute period of update : signal is "200 ns";
attribute buffer_type : string;
attribute buffer_type of update_i : signal is "none";
attribute buffer_type of MDM_Core_I1 : label is "none";
begin -- architecture IMP
Use_E2 : if native_bscan(C_FAMILY) = u_BSCANE2 and C_USE_BSCAN /= 2 generate
begin
BSCANE2_I : BSCANE2
generic map (
DISABLE_JTAG => "FALSE",
JTAG_CHAIN => C_JTAG_CHAIN)
port map (
CAPTURE => capture, -- [out std_logic]
DRCK => drck_i, -- [out std_logic]
RESET => reset, -- [out std_logic]
RUNTEST => open, -- [out std_logic]
SEL => sel, -- [out std_logic]
SHIFT => shift, -- [out std_logic]
TCK => open, -- [out std_logic]
TDI => tdi, -- [out std_logic]
TMS => open, -- [out std_logic]
UPDATE => update_i, -- [out std_logic]
TDO => tdo); -- [in std_logic]
end generate Use_E2;
Use_External : if C_USE_BSCAN = 2 generate
begin
capture <= bscan_ext_capture;
drck_i <= bscan_ext_drck;
reset <= bscan_ext_reset;
sel <= bscan_ext_sel;
shift <= bscan_ext_shift;
tdi <= bscan_ext_tdi;
update_i <= bscan_ext_update;
bscan_ext_tdo <= tdo;
end generate Use_External;
No_External : if C_USE_BSCAN /= 2 generate
begin
bscan_ext_tdo <= '0';
end generate No_External;
Use_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 1 generate
signal dbgreg_select_n : std_logic;
signal dbgreg_drck_i : std_logic;
signal dbgreg_update_i : std_logic;
signal update_set : std_logic;
signal update_reset : std_logic;
begin
dbgreg_select_n <= not dbgreg_select;
-- drck <= dbgreg_drck when dbgreg_select = '1' else drck_i;
BUFG_DRCK : BUFG
port map (
O => dbgreg_drck_i,
I => dbgreg_drck
);
BUFGCTRL_DRCK : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => drck,
CE0 => '1',
CE1 => '1',
I0 => drck_i,
I1 => dbgreg_drck_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
-- update <= dbgreg_update when dbgreg_select = '1' else update_i;
BUFG_UPDATE : BUFG
port map (
O => dbgreg_update_i,
I => dbgreg_update
);
BUFGCTRL_UPDATE : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => update,
CE0 => '1',
CE1 => '1',
I0 => update_i,
I1 => dbgreg_update_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
JTAG_Busy_Detect : process (drck_i, sel, update_set, Config_Reset)
begin
if sel = '0' or update_set = '1' or Config_Reset = '1' then
jtag_busy <= '0';
update_reset <= '1';
elsif drck_i'event and drck_i = '1' then
if sel = '1' and capture = '1' then
jtag_busy <= '1';
end if;
update_reset <= '0';
end if;
end process JTAG_Busy_Detect;
JTAG_Update_Detect : process (update_i, update_reset, Config_Reset)
begin
if update_reset = '1' or Config_Reset = '1' then
update_set <= '0';
elsif update_i'event and update_i = '1' then
update_set <= '1';
end if;
end process JTAG_Update_Detect;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 0 generate
begin
BUFG_DRCK : BUFG
port map (
O => drck,
I => drck_i
);
update <= update_i;
jtag_busy <= '0';
end generate No_Dbg_Reg_Access;
---------------------------------------------------------------------------
-- MDM core
---------------------------------------------------------------------------
MDM_Core_I1 : MDM_Core
generic map (
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET, -- [integer = 0]
C_BASEADDR => C_BASEADDR, -- [std_logic_vector(0 to 31)]
C_HIGHADDR => C_HIGHADDR, -- [std_logic_vector(0 to 31)]
C_MB_DBG_PORTS => C_MB_DBG_PORTS, -- [integer]
C_EN_WIDTH => C_EN_WIDTH, -- [integer]
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS, -- [integer]
C_REG_NUM_CE => C_REG_NUM_CE, -- [integer]
C_REG_DATA_WIDTH => C_REG_DATA_WIDTH, -- [integer]
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS, -- [integer]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ, -- [integer]
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH, -- [integer]
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH, -- [integer]
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER, -- [integer]
C_USE_UART => C_USE_UART, -- [integer]
C_UART_WIDTH => 8 -- [integer]
)
port map (
-- Global signals
Config_Reset => Config_Reset, -- [in std_logic]
Interrupt => Interrupt, -- [out std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst, -- [out std_logic]
-- Debug Register Access signals
DbgReg_DRCK => dbgreg_drck, -- [out std_logic]
DbgReg_UPDATE => dbgreg_update, -- [out std_logic]
DbgReg_Select => dbgreg_select, -- [out std_logic]
JTAG_Busy => jtag_busy, -- [in std_logic]
-- AXI IPIC signals
bus2ip_clk => bus2ip_clk,
bus2ip_resetn => bus2ip_resetn,
bus2ip_data => bus2ip_data(C_REG_DATA_WIDTH-1 downto 0),
bus2ip_rdce => bus2ip_rdce(C_REG_NUM_CE-1 downto 0),
bus2ip_wrce => bus2ip_wrce(C_REG_NUM_CE-1 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
ip2bus_data => ip2bus_data(C_REG_DATA_WIDTH-1 downto 0),
-- Bus Master signals
MB_Debug_Enabled => mb_debug_enabled,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
Master_rd_start => master_rd_start,
Master_rd_addr => master_rd_addr,
Master_rd_len => master_rd_len,
Master_rd_size => master_rd_size,
Master_rd_excl => master_rd_excl,
Master_rd_idle => master_rd_idle,
Master_rd_resp => master_rd_resp,
Master_wr_start => master_wr_start,
Master_wr_addr => master_wr_addr,
Master_wr_len => master_wr_len,
Master_wr_size => master_wr_size,
Master_wr_excl => master_wr_excl,
Master_wr_idle => master_wr_idle,
Master_wr_resp => master_wr_resp,
Master_data_rd => master_data_rd,
Master_data_out => master_data_out,
Master_data_exists => master_data_exists,
Master_data_wr => master_data_wr,
Master_data_in => master_data_in,
Master_data_empty => master_data_empty,
-- JTAG signals
JTAG_TDI => tdi, -- [in std_logic]
JTAG_RESET => reset, -- [in std_logic]
UPDATE => update, -- [in std_logic]
JTAG_SHIFT => shift, -- [in std_logic]
JTAG_CAPTURE => capture, -- [in std_logic]
SEL => sel, -- [in std_logic]
DRCK => drck, -- [in std_logic]
JTAG_TDO => tdo, -- [out std_logic]
-- MicroBlaze Debug Signals
Dbg_Clk_0 => Dbg_Clk_0, -- [out std_logic]
Dbg_TDI_0 => Dbg_TDI_0, -- [out std_logic]
Dbg_TDO_0 => Dbg_TDO_0, -- [in std_logic]
Dbg_Reg_En_0 => Dbg_Reg_En_0, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_0 => Dbg_Capture_0, -- [out std_logic]
Dbg_Shift_0 => Dbg_Shift_0, -- [out std_logic]
Dbg_Update_0 => Dbg_Update_0, -- [out std_logic]
Dbg_Rst_0 => Dbg_Rst_0, -- [out std_logic]
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_1 => Dbg_Clk_1, -- [out std_logic]
Dbg_TDI_1 => Dbg_TDI_1, -- [out std_logic]
Dbg_TDO_1 => Dbg_TDO_1, -- [in std_logic]
Dbg_Reg_En_1 => Dbg_Reg_En_1, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_1 => Dbg_Capture_1, -- [out std_logic]
Dbg_Shift_1 => Dbg_Shift_1, -- [out std_logic]
Dbg_Update_1 => Dbg_Update_1, -- [out std_logic]
Dbg_Rst_1 => Dbg_Rst_1, -- [out std_logic]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_2 => Dbg_Clk_2, -- [out std_logic]
Dbg_TDI_2 => Dbg_TDI_2, -- [out std_logic]
Dbg_TDO_2 => Dbg_TDO_2, -- [in std_logic]
Dbg_Reg_En_2 => Dbg_Reg_En_2, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_2 => Dbg_Capture_2, -- [out std_logic]
Dbg_Shift_2 => Dbg_Shift_2, -- [out std_logic]
Dbg_Update_2 => Dbg_Update_2, -- [out std_logic]
Dbg_Rst_2 => Dbg_Rst_2, -- [out std_logic]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_3 => Dbg_Clk_3, -- [out std_logic]
Dbg_TDI_3 => Dbg_TDI_3, -- [out std_logic]
Dbg_TDO_3 => Dbg_TDO_3, -- [in std_logic]
Dbg_Reg_En_3 => Dbg_Reg_En_3, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_3 => Dbg_Capture_3, -- [out std_logic]
Dbg_Shift_3 => Dbg_Shift_3, -- [out std_logic]
Dbg_Update_3 => Dbg_Update_3, -- [out std_logic]
Dbg_Rst_3 => Dbg_Rst_3, -- [out std_logic]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_4 => Dbg_Clk_4, -- [out std_logic]
Dbg_TDI_4 => Dbg_TDI_4, -- [out std_logic]
Dbg_TDO_4 => Dbg_TDO_4, -- [in std_logic]
Dbg_Reg_En_4 => Dbg_Reg_En_4, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_4 => Dbg_Capture_4, -- [out std_logic]
Dbg_Shift_4 => Dbg_Shift_4, -- [out std_logic]
Dbg_Update_4 => Dbg_Update_4, -- [out std_logic]
Dbg_Rst_4 => Dbg_Rst_4, -- [out std_logic]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_5 => Dbg_Clk_5, -- [out std_logic]
Dbg_TDI_5 => Dbg_TDI_5, -- [out std_logic]
Dbg_TDO_5 => Dbg_TDO_5, -- [in std_logic]
Dbg_Reg_En_5 => Dbg_Reg_En_5, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_5 => Dbg_Capture_5, -- [out std_logic]
Dbg_Shift_5 => Dbg_Shift_5, -- [out std_logic]
Dbg_Update_5 => Dbg_Update_5, -- [out std_logic]
Dbg_Rst_5 => Dbg_Rst_5, -- [out std_logic]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_6 => Dbg_Clk_6, -- [out std_logic]
Dbg_TDI_6 => Dbg_TDI_6, -- [out std_logic]
Dbg_TDO_6 => Dbg_TDO_6, -- [in std_logic]
Dbg_Reg_En_6 => Dbg_Reg_En_6, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_6 => Dbg_Capture_6, -- [out std_logic]
Dbg_Shift_6 => Dbg_Shift_6, -- [out std_logic]
Dbg_Update_6 => Dbg_Update_6, -- [out std_logic]
Dbg_Rst_6 => Dbg_Rst_6, -- [out std_logic]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_7 => Dbg_Clk_7, -- [out std_logic]
Dbg_TDI_7 => Dbg_TDI_7, -- [out std_logic]
Dbg_TDO_7 => Dbg_TDO_7, -- [in std_logic]
Dbg_Reg_En_7 => Dbg_Reg_En_7, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_7 => Dbg_Capture_7, -- [out std_logic]
Dbg_Shift_7 => Dbg_Shift_7, -- [out std_logic]
Dbg_Update_7 => Dbg_Update_7, -- [out std_logic]
Dbg_Rst_7 => Dbg_Rst_7, -- [out std_logic]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_8 => Dbg_Clk_8, -- [out std_logic]
Dbg_TDI_8 => Dbg_TDI_8, -- [out std_logic]
Dbg_TDO_8 => Dbg_TDO_8, -- [in std_logic]
Dbg_Reg_En_8 => Dbg_Reg_En_8, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_8 => Dbg_Capture_8, -- [out std_logic]
Dbg_Shift_8 => Dbg_Shift_8, -- [out std_logic]
Dbg_Update_8 => Dbg_Update_8, -- [out std_logic]
Dbg_Rst_8 => Dbg_Rst_8, -- [out std_logic]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_9 => Dbg_Clk_9, -- [out std_logic]
Dbg_TDI_9 => Dbg_TDI_9, -- [out std_logic]
Dbg_TDO_9 => Dbg_TDO_9, -- [in std_logic]
Dbg_Reg_En_9 => Dbg_Reg_En_9, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_9 => Dbg_Capture_9, -- [out std_logic]
Dbg_Shift_9 => Dbg_Shift_9, -- [out std_logic]
Dbg_Update_9 => Dbg_Update_9, -- [out std_logic]
Dbg_Rst_9 => Dbg_Rst_9, -- [out std_logic]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_10 => Dbg_Clk_10, -- [out std_logic]
Dbg_TDI_10 => Dbg_TDI_10, -- [out std_logic]
Dbg_TDO_10 => Dbg_TDO_10, -- [in std_logic]
Dbg_Reg_En_10 => Dbg_Reg_En_10, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_10 => Dbg_Capture_10, -- [out std_logic]
Dbg_Shift_10 => Dbg_Shift_10, -- [out std_logic]
Dbg_Update_10 => Dbg_Update_10, -- [out std_logic]
Dbg_Rst_10 => Dbg_Rst_10, -- [out std_logic]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_11 => Dbg_Clk_11, -- [out std_logic]
Dbg_TDI_11 => Dbg_TDI_11, -- [out std_logic]
Dbg_TDO_11 => Dbg_TDO_11, -- [in std_logic]
Dbg_Reg_En_11 => Dbg_Reg_En_11, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_11 => Dbg_Capture_11, -- [out std_logic]
Dbg_Shift_11 => Dbg_Shift_11, -- [out std_logic]
Dbg_Update_11 => Dbg_Update_11, -- [out std_logic]
Dbg_Rst_11 => Dbg_Rst_11, -- [out std_logic]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_12 => Dbg_Clk_12, -- [out std_logic]
Dbg_TDI_12 => Dbg_TDI_12, -- [out std_logic]
Dbg_TDO_12 => Dbg_TDO_12, -- [in std_logic]
Dbg_Reg_En_12 => Dbg_Reg_En_12, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_12 => Dbg_Capture_12, -- [out std_logic]
Dbg_Shift_12 => Dbg_Shift_12, -- [out std_logic]
Dbg_Update_12 => Dbg_Update_12, -- [out std_logic]
Dbg_Rst_12 => Dbg_Rst_12, -- [out std_logic]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_13 => Dbg_Clk_13, -- [out std_logic]
Dbg_TDI_13 => Dbg_TDI_13, -- [out std_logic]
Dbg_TDO_13 => Dbg_TDO_13, -- [in std_logic]
Dbg_Reg_En_13 => Dbg_Reg_En_13, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_13 => Dbg_Capture_13, -- [out std_logic]
Dbg_Shift_13 => Dbg_Shift_13, -- [out std_logic]
Dbg_Update_13 => Dbg_Update_13, -- [out std_logic]
Dbg_Rst_13 => Dbg_Rst_13, -- [out std_logic]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_14 => Dbg_Clk_14, -- [out std_logic]
Dbg_TDI_14 => Dbg_TDI_14, -- [out std_logic]
Dbg_TDO_14 => Dbg_TDO_14, -- [in std_logic]
Dbg_Reg_En_14 => Dbg_Reg_En_14, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_14 => Dbg_Capture_14, -- [out std_logic]
Dbg_Shift_14 => Dbg_Shift_14, -- [out std_logic]
Dbg_Update_14 => Dbg_Update_14, -- [out std_logic]
Dbg_Rst_14 => Dbg_Rst_14, -- [out std_logic]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_15 => Dbg_Clk_15, -- [out std_logic]
Dbg_TDI_15 => Dbg_TDI_15, -- [out std_logic]
Dbg_TDO_15 => Dbg_TDO_15, -- [in std_logic]
Dbg_Reg_En_15 => Dbg_Reg_En_15, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_15 => Dbg_Capture_15, -- [out std_logic]
Dbg_Shift_15 => Dbg_Shift_15, -- [out std_logic]
Dbg_Update_15 => Dbg_Update_15, -- [out std_logic]
Dbg_Rst_15 => Dbg_Rst_15, -- [out std_logic]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_16 => Dbg_Clk_16, -- [out std_logic]
Dbg_TDI_16 => Dbg_TDI_16, -- [out std_logic]
Dbg_TDO_16 => Dbg_TDO_16, -- [in std_logic]
Dbg_Reg_En_16 => Dbg_Reg_En_16, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_16 => Dbg_Capture_16, -- [out std_logic]
Dbg_Shift_16 => Dbg_Shift_16, -- [out std_logic]
Dbg_Update_16 => Dbg_Update_16, -- [out std_logic]
Dbg_Rst_16 => Dbg_Rst_16, -- [out std_logic]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_17 => Dbg_Clk_17, -- [out std_logic]
Dbg_TDI_17 => Dbg_TDI_17, -- [out std_logic]
Dbg_TDO_17 => Dbg_TDO_17, -- [in std_logic]
Dbg_Reg_En_17 => Dbg_Reg_En_17, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_17 => Dbg_Capture_17, -- [out std_logic]
Dbg_Shift_17 => Dbg_Shift_17, -- [out std_logic]
Dbg_Update_17 => Dbg_Update_17, -- [out std_logic]
Dbg_Rst_17 => Dbg_Rst_17, -- [out std_logic]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_18 => Dbg_Clk_18, -- [out std_logic]
Dbg_TDI_18 => Dbg_TDI_18, -- [out std_logic]
Dbg_TDO_18 => Dbg_TDO_18, -- [in std_logic]
Dbg_Reg_En_18 => Dbg_Reg_En_18, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_18 => Dbg_Capture_18, -- [out std_logic]
Dbg_Shift_18 => Dbg_Shift_18, -- [out std_logic]
Dbg_Update_18 => Dbg_Update_18, -- [out std_logic]
Dbg_Rst_18 => Dbg_Rst_18, -- [out std_logic]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_19 => Dbg_Clk_19, -- [out std_logic]
Dbg_TDI_19 => Dbg_TDI_19, -- [out std_logic]
Dbg_TDO_19 => Dbg_TDO_19, -- [in std_logic]
Dbg_Reg_En_19 => Dbg_Reg_En_19, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_19 => Dbg_Capture_19, -- [out std_logic]
Dbg_Shift_19 => Dbg_Shift_19, -- [out std_logic]
Dbg_Update_19 => Dbg_Update_19, -- [out std_logic]
Dbg_Rst_19 => Dbg_Rst_19, -- [out std_logic]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_20 => Dbg_Clk_20, -- [out std_logic]
Dbg_TDI_20 => Dbg_TDI_20, -- [out std_logic]
Dbg_TDO_20 => Dbg_TDO_20, -- [in std_logic]
Dbg_Reg_En_20 => Dbg_Reg_En_20, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_20 => Dbg_Capture_20, -- [out std_logic]
Dbg_Shift_20 => Dbg_Shift_20, -- [out std_logic]
Dbg_Update_20 => Dbg_Update_20, -- [out std_logic]
Dbg_Rst_20 => Dbg_Rst_20, -- [out std_logic]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_21 => Dbg_Clk_21, -- [out std_logic]
Dbg_TDI_21 => Dbg_TDI_21, -- [out std_logic]
Dbg_TDO_21 => Dbg_TDO_21, -- [in std_logic]
Dbg_Reg_En_21 => Dbg_Reg_En_21, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_21 => Dbg_Capture_21, -- [out std_logic]
Dbg_Shift_21 => Dbg_Shift_21, -- [out std_logic]
Dbg_Update_21 => Dbg_Update_21, -- [out std_logic]
Dbg_Rst_21 => Dbg_Rst_21, -- [out std_logic]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_22 => Dbg_Clk_22, -- [out std_logic]
Dbg_TDI_22 => Dbg_TDI_22, -- [out std_logic]
Dbg_TDO_22 => Dbg_TDO_22, -- [in std_logic]
Dbg_Reg_En_22 => Dbg_Reg_En_22, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_22 => Dbg_Capture_22, -- [out std_logic]
Dbg_Shift_22 => Dbg_Shift_22, -- [out std_logic]
Dbg_Update_22 => Dbg_Update_22, -- [out std_logic]
Dbg_Rst_22 => Dbg_Rst_22, -- [out std_logic]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_23 => Dbg_Clk_23, -- [out std_logic]
Dbg_TDI_23 => Dbg_TDI_23, -- [out std_logic]
Dbg_TDO_23 => Dbg_TDO_23, -- [in std_logic]
Dbg_Reg_En_23 => Dbg_Reg_En_23, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_23 => Dbg_Capture_23, -- [out std_logic]
Dbg_Shift_23 => Dbg_Shift_23, -- [out std_logic]
Dbg_Update_23 => Dbg_Update_23, -- [out std_logic]
Dbg_Rst_23 => Dbg_Rst_23, -- [out std_logic]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_24 => Dbg_Clk_24, -- [out std_logic]
Dbg_TDI_24 => Dbg_TDI_24, -- [out std_logic]
Dbg_TDO_24 => Dbg_TDO_24, -- [in std_logic]
Dbg_Reg_En_24 => Dbg_Reg_En_24, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_24 => Dbg_Capture_24, -- [out std_logic]
Dbg_Shift_24 => Dbg_Shift_24, -- [out std_logic]
Dbg_Update_24 => Dbg_Update_24, -- [out std_logic]
Dbg_Rst_24 => Dbg_Rst_24, -- [out std_logic]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_25 => Dbg_Clk_25, -- [out std_logic]
Dbg_TDI_25 => Dbg_TDI_25, -- [out std_logic]
Dbg_TDO_25 => Dbg_TDO_25, -- [in std_logic]
Dbg_Reg_En_25 => Dbg_Reg_En_25, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_25 => Dbg_Capture_25, -- [out std_logic]
Dbg_Shift_25 => Dbg_Shift_25, -- [out std_logic]
Dbg_Update_25 => Dbg_Update_25, -- [out std_logic]
Dbg_Rst_25 => Dbg_Rst_25, -- [out std_logic]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_26 => Dbg_Clk_26, -- [out std_logic]
Dbg_TDI_26 => Dbg_TDI_26, -- [out std_logic]
Dbg_TDO_26 => Dbg_TDO_26, -- [in std_logic]
Dbg_Reg_En_26 => Dbg_Reg_En_26, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_26 => Dbg_Capture_26, -- [out std_logic]
Dbg_Shift_26 => Dbg_Shift_26, -- [out std_logic]
Dbg_Update_26 => Dbg_Update_26, -- [out std_logic]
Dbg_Rst_26 => Dbg_Rst_26, -- [out std_logic]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_27 => Dbg_Clk_27, -- [out std_logic]
Dbg_TDI_27 => Dbg_TDI_27, -- [out std_logic]
Dbg_TDO_27 => Dbg_TDO_27, -- [in std_logic]
Dbg_Reg_En_27 => Dbg_Reg_En_27, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_27 => Dbg_Capture_27, -- [out std_logic]
Dbg_Shift_27 => Dbg_Shift_27, -- [out std_logic]
Dbg_Update_27 => Dbg_Update_27, -- [out std_logic]
Dbg_Rst_27 => Dbg_Rst_27, -- [out std_logic]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_28 => Dbg_Clk_28, -- [out std_logic]
Dbg_TDI_28 => Dbg_TDI_28, -- [out std_logic]
Dbg_TDO_28 => Dbg_TDO_28, -- [in std_logic]
Dbg_Reg_En_28 => Dbg_Reg_En_28, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_28 => Dbg_Capture_28, -- [out std_logic]
Dbg_Shift_28 => Dbg_Shift_28, -- [out std_logic]
Dbg_Update_28 => Dbg_Update_28, -- [out std_logic]
Dbg_Rst_28 => Dbg_Rst_28, -- [out std_logic]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_29 => Dbg_Clk_29, -- [out std_logic]
Dbg_TDI_29 => Dbg_TDI_29, -- [out std_logic]
Dbg_TDO_29 => Dbg_TDO_29, -- [in std_logic]
Dbg_Reg_En_29 => Dbg_Reg_En_29, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_29 => Dbg_Capture_29, -- [out std_logic]
Dbg_Shift_29 => Dbg_Shift_29, -- [out std_logic]
Dbg_Update_29 => Dbg_Update_29, -- [out std_logic]
Dbg_Rst_29 => Dbg_Rst_29, -- [out std_logic]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_30 => Dbg_Clk_30, -- [out std_logic]
Dbg_TDI_30 => Dbg_TDI_30, -- [out std_logic]
Dbg_TDO_30 => Dbg_TDO_30, -- [in std_logic]
Dbg_Reg_En_30 => Dbg_Reg_En_30, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_30 => Dbg_Capture_30, -- [out std_logic]
Dbg_Shift_30 => Dbg_Shift_30, -- [out std_logic]
Dbg_Update_30 => Dbg_Update_30, -- [out std_logic]
Dbg_Rst_30 => Dbg_Rst_30, -- [out std_logic]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_Clk_31 => Dbg_Clk_31, -- [out std_logic]
Dbg_TDI_31 => Dbg_TDI_31, -- [out std_logic]
Dbg_TDO_31 => Dbg_TDO_31, -- [in std_logic]
Dbg_Reg_En_31 => Dbg_Reg_En_31, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_31 => Dbg_Capture_31, -- [out std_logic]
Dbg_Shift_31 => Dbg_Shift_31, -- [out std_logic]
Dbg_Update_31 => Dbg_Update_31, -- [out std_logic]
Dbg_Rst_31 => Dbg_Rst_31, -- [out std_logic]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Ext_Trig_In => ext_trig_in, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => ext_trig_ack_in, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => ext_trig_out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => ext_trig_ack_out, -- [in std_logic_vector(0 to 3)]
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
ext_trig_in <= Trig_In_0 & Trig_In_1 & Trig_In_2 & Trig_In_3;
ext_trig_ack_out <= Trig_Ack_Out_0 & Trig_Ack_Out_1 & Trig_Ack_Out_2 & Trig_Ack_Out_3;
Trig_Ack_In_0 <= ext_trig_ack_in(0);
Trig_Ack_In_1 <= ext_trig_ack_in(1);
Trig_Ack_In_2 <= ext_trig_ack_in(2);
Trig_Ack_In_3 <= ext_trig_ack_in(3);
Trig_Out_0 <= ext_trig_out(0);
Trig_Out_1 <= ext_trig_out(1);
Trig_Out_2 <= ext_trig_out(2);
Trig_Out_3 <= ext_trig_out(3);
-- Bus Master port
Use_Bus_MASTER : if (C_DBG_MEM_ACCESS = 1) generate
type LMB_vec_type is array (natural range <>) of std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_addr : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_write : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_addr_strobe : std_logic;
signal lmb_read_strobe : std_logic;
signal lmb_write_strobe : std_logic;
signal lmb_ready : std_logic;
signal lmb_wait : std_logic;
signal lmb_ue : std_logic;
signal lmb_byte_enable : std_logic_vector(0 to C_DATA_SIZE / 8 - 1);
signal lmb_addr_strobe_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec : LMB_vec_type(0 to 31);
signal lmb_ready_vec : std_logic_vector(0 to 31);
signal lmb_wait_vec : std_logic_vector(0 to 31);
signal lmb_ue_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec_q : LMB_vec_type(0 to C_EN_WIDTH - 1);
signal lmb_ready_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_wait_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_ue_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
LMB_Data_Addr => lmb_data_addr,
LMB_Data_Read => lmb_data_read,
LMB_Data_Write => lmb_data_write,
LMB_Addr_Strobe => lmb_addr_strobe,
LMB_Read_Strobe => lmb_read_strobe,
LMB_Write_Strobe => lmb_write_strobe,
LMB_Ready => lmb_ready,
LMB_Wait => lmb_wait,
LMB_UE => lmb_ue,
LMB_Byte_Enable => lmb_byte_enable,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
Generate_LMB_Outputs : process (mb_debug_enabled, lmb_addr_strobe)
begin -- process Generate_LMB_Outputs
lmb_addr_strobe_vec <= (others => '0');
for I in 0 to C_EN_WIDTH - 1 loop
lmb_addr_strobe_vec(I) <= lmb_addr_strobe and mb_debug_enabled(I);
end loop;
end process Generate_LMB_Outputs;
LMB_Addr_Strobe_0 <= lmb_addr_strobe_vec(0);
LMB_Addr_Strobe_1 <= lmb_addr_strobe_vec(1);
LMB_Addr_Strobe_2 <= lmb_addr_strobe_vec(2);
LMB_Addr_Strobe_3 <= lmb_addr_strobe_vec(3);
LMB_Addr_Strobe_4 <= lmb_addr_strobe_vec(4);
LMB_Addr_Strobe_5 <= lmb_addr_strobe_vec(5);
LMB_Addr_Strobe_6 <= lmb_addr_strobe_vec(6);
LMB_Addr_Strobe_7 <= lmb_addr_strobe_vec(7);
LMB_Addr_Strobe_8 <= lmb_addr_strobe_vec(8);
LMB_Addr_Strobe_9 <= lmb_addr_strobe_vec(9);
LMB_Addr_Strobe_10 <= lmb_addr_strobe_vec(10);
LMB_Addr_Strobe_11 <= lmb_addr_strobe_vec(11);
LMB_Addr_Strobe_12 <= lmb_addr_strobe_vec(12);
LMB_Addr_Strobe_13 <= lmb_addr_strobe_vec(13);
LMB_Addr_Strobe_14 <= lmb_addr_strobe_vec(14);
LMB_Addr_Strobe_15 <= lmb_addr_strobe_vec(15);
LMB_Addr_Strobe_16 <= lmb_addr_strobe_vec(16);
LMB_Addr_Strobe_17 <= lmb_addr_strobe_vec(17);
LMB_Addr_Strobe_18 <= lmb_addr_strobe_vec(18);
LMB_Addr_Strobe_19 <= lmb_addr_strobe_vec(19);
LMB_Addr_Strobe_20 <= lmb_addr_strobe_vec(20);
LMB_Addr_Strobe_21 <= lmb_addr_strobe_vec(21);
LMB_Addr_Strobe_22 <= lmb_addr_strobe_vec(22);
LMB_Addr_Strobe_23 <= lmb_addr_strobe_vec(23);
LMB_Addr_Strobe_24 <= lmb_addr_strobe_vec(24);
LMB_Addr_Strobe_25 <= lmb_addr_strobe_vec(25);
LMB_Addr_Strobe_26 <= lmb_addr_strobe_vec(26);
LMB_Addr_Strobe_27 <= lmb_addr_strobe_vec(27);
LMB_Addr_Strobe_28 <= lmb_addr_strobe_vec(28);
LMB_Addr_Strobe_29 <= lmb_addr_strobe_vec(29);
LMB_Addr_Strobe_30 <= lmb_addr_strobe_vec(30);
LMB_Addr_Strobe_31 <= lmb_addr_strobe_vec(31);
LMB_Data_Addr_0 <= lmb_data_addr;
LMB_Data_Addr_1 <= lmb_data_addr;
LMB_Data_Addr_2 <= lmb_data_addr;
LMB_Data_Addr_3 <= lmb_data_addr;
LMB_Data_Addr_4 <= lmb_data_addr;
LMB_Data_Addr_5 <= lmb_data_addr;
LMB_Data_Addr_6 <= lmb_data_addr;
LMB_Data_Addr_7 <= lmb_data_addr;
LMB_Data_Addr_8 <= lmb_data_addr;
LMB_Data_Addr_9 <= lmb_data_addr;
LMB_Data_Addr_10 <= lmb_data_addr;
LMB_Data_Addr_11 <= lmb_data_addr;
LMB_Data_Addr_12 <= lmb_data_addr;
LMB_Data_Addr_13 <= lmb_data_addr;
LMB_Data_Addr_14 <= lmb_data_addr;
LMB_Data_Addr_15 <= lmb_data_addr;
LMB_Data_Addr_16 <= lmb_data_addr;
LMB_Data_Addr_17 <= lmb_data_addr;
LMB_Data_Addr_18 <= lmb_data_addr;
LMB_Data_Addr_19 <= lmb_data_addr;
LMB_Data_Addr_20 <= lmb_data_addr;
LMB_Data_Addr_21 <= lmb_data_addr;
LMB_Data_Addr_22 <= lmb_data_addr;
LMB_Data_Addr_23 <= lmb_data_addr;
LMB_Data_Addr_24 <= lmb_data_addr;
LMB_Data_Addr_25 <= lmb_data_addr;
LMB_Data_Addr_26 <= lmb_data_addr;
LMB_Data_Addr_27 <= lmb_data_addr;
LMB_Data_Addr_28 <= lmb_data_addr;
LMB_Data_Addr_29 <= lmb_data_addr;
LMB_Data_Addr_30 <= lmb_data_addr;
LMB_Data_Addr_31 <= lmb_data_addr;
LMB_Data_write_0 <= lmb_data_write;
LMB_Data_write_1 <= lmb_data_write;
LMB_Data_write_2 <= lmb_data_write;
LMB_Data_write_3 <= lmb_data_write;
LMB_Data_write_4 <= lmb_data_write;
LMB_Data_write_5 <= lmb_data_write;
LMB_Data_write_6 <= lmb_data_write;
LMB_Data_write_7 <= lmb_data_write;
LMB_Data_write_8 <= lmb_data_write;
LMB_Data_write_9 <= lmb_data_write;
LMB_Data_write_10 <= lmb_data_write;
LMB_Data_write_11 <= lmb_data_write;
LMB_Data_write_12 <= lmb_data_write;
LMB_Data_write_13 <= lmb_data_write;
LMB_Data_write_14 <= lmb_data_write;
LMB_Data_write_15 <= lmb_data_write;
LMB_Data_write_16 <= lmb_data_write;
LMB_Data_write_17 <= lmb_data_write;
LMB_Data_write_18 <= lmb_data_write;
LMB_Data_write_19 <= lmb_data_write;
LMB_Data_write_20 <= lmb_data_write;
LMB_Data_write_21 <= lmb_data_write;
LMB_Data_write_22 <= lmb_data_write;
LMB_Data_write_23 <= lmb_data_write;
LMB_Data_write_24 <= lmb_data_write;
LMB_Data_write_25 <= lmb_data_write;
LMB_Data_write_26 <= lmb_data_write;
LMB_Data_write_27 <= lmb_data_write;
LMB_Data_write_28 <= lmb_data_write;
LMB_Data_write_29 <= lmb_data_write;
LMB_Data_write_30 <= lmb_data_write;
LMB_Data_write_31 <= lmb_data_write;
LMB_Read_strobe_0 <= lmb_read_strobe;
LMB_Read_strobe_1 <= lmb_read_strobe;
LMB_Read_strobe_2 <= lmb_read_strobe;
LMB_Read_strobe_3 <= lmb_read_strobe;
LMB_Read_strobe_4 <= lmb_read_strobe;
LMB_Read_strobe_5 <= lmb_read_strobe;
LMB_Read_strobe_6 <= lmb_read_strobe;
LMB_Read_strobe_7 <= lmb_read_strobe;
LMB_Read_strobe_8 <= lmb_read_strobe;
LMB_Read_strobe_9 <= lmb_read_strobe;
LMB_Read_strobe_10 <= lmb_read_strobe;
LMB_Read_strobe_11 <= lmb_read_strobe;
LMB_Read_strobe_12 <= lmb_read_strobe;
LMB_Read_strobe_13 <= lmb_read_strobe;
LMB_Read_strobe_14 <= lmb_read_strobe;
LMB_Read_strobe_15 <= lmb_read_strobe;
LMB_Read_strobe_16 <= lmb_read_strobe;
LMB_Read_strobe_17 <= lmb_read_strobe;
LMB_Read_strobe_18 <= lmb_read_strobe;
LMB_Read_strobe_19 <= lmb_read_strobe;
LMB_Read_strobe_20 <= lmb_read_strobe;
LMB_Read_strobe_21 <= lmb_read_strobe;
LMB_Read_strobe_22 <= lmb_read_strobe;
LMB_Read_strobe_23 <= lmb_read_strobe;
LMB_Read_strobe_24 <= lmb_read_strobe;
LMB_Read_strobe_25 <= lmb_read_strobe;
LMB_Read_strobe_26 <= lmb_read_strobe;
LMB_Read_strobe_27 <= lmb_read_strobe;
LMB_Read_strobe_28 <= lmb_read_strobe;
LMB_Read_strobe_29 <= lmb_read_strobe;
LMB_Read_strobe_30 <= lmb_read_strobe;
LMB_Read_strobe_31 <= lmb_read_strobe;
LMB_Write_strobe_0 <= lmb_write_strobe;
LMB_Write_strobe_1 <= lmb_write_strobe;
LMB_Write_strobe_2 <= lmb_write_strobe;
LMB_Write_strobe_3 <= lmb_write_strobe;
LMB_Write_strobe_4 <= lmb_write_strobe;
LMB_Write_strobe_5 <= lmb_write_strobe;
LMB_Write_strobe_6 <= lmb_write_strobe;
LMB_Write_strobe_7 <= lmb_write_strobe;
LMB_Write_strobe_8 <= lmb_write_strobe;
LMB_Write_strobe_9 <= lmb_write_strobe;
LMB_Write_strobe_10 <= lmb_write_strobe;
LMB_Write_strobe_11 <= lmb_write_strobe;
LMB_Write_strobe_12 <= lmb_write_strobe;
LMB_Write_strobe_13 <= lmb_write_strobe;
LMB_Write_strobe_14 <= lmb_write_strobe;
LMB_Write_strobe_15 <= lmb_write_strobe;
LMB_Write_strobe_16 <= lmb_write_strobe;
LMB_Write_strobe_17 <= lmb_write_strobe;
LMB_Write_strobe_18 <= lmb_write_strobe;
LMB_Write_strobe_19 <= lmb_write_strobe;
LMB_Write_strobe_20 <= lmb_write_strobe;
LMB_Write_strobe_21 <= lmb_write_strobe;
LMB_Write_strobe_22 <= lmb_write_strobe;
LMB_Write_strobe_23 <= lmb_write_strobe;
LMB_Write_strobe_24 <= lmb_write_strobe;
LMB_Write_strobe_25 <= lmb_write_strobe;
LMB_Write_strobe_26 <= lmb_write_strobe;
LMB_Write_strobe_27 <= lmb_write_strobe;
LMB_Write_strobe_28 <= lmb_write_strobe;
LMB_Write_strobe_29 <= lmb_write_strobe;
LMB_Write_strobe_30 <= lmb_write_strobe;
LMB_Write_strobe_31 <= lmb_write_strobe;
LMB_Byte_enable_0 <= lmb_byte_enable;
LMB_Byte_enable_1 <= lmb_byte_enable;
LMB_Byte_enable_2 <= lmb_byte_enable;
LMB_Byte_enable_3 <= lmb_byte_enable;
LMB_Byte_enable_4 <= lmb_byte_enable;
LMB_Byte_enable_5 <= lmb_byte_enable;
LMB_Byte_enable_6 <= lmb_byte_enable;
LMB_Byte_enable_7 <= lmb_byte_enable;
LMB_Byte_enable_8 <= lmb_byte_enable;
LMB_Byte_enable_9 <= lmb_byte_enable;
LMB_Byte_enable_10 <= lmb_byte_enable;
LMB_Byte_enable_11 <= lmb_byte_enable;
LMB_Byte_enable_12 <= lmb_byte_enable;
LMB_Byte_enable_13 <= lmb_byte_enable;
LMB_Byte_enable_14 <= lmb_byte_enable;
LMB_Byte_enable_15 <= lmb_byte_enable;
LMB_Byte_enable_16 <= lmb_byte_enable;
LMB_Byte_enable_17 <= lmb_byte_enable;
LMB_Byte_enable_18 <= lmb_byte_enable;
LMB_Byte_enable_19 <= lmb_byte_enable;
LMB_Byte_enable_20 <= lmb_byte_enable;
LMB_Byte_enable_21 <= lmb_byte_enable;
LMB_Byte_enable_22 <= lmb_byte_enable;
LMB_Byte_enable_23 <= lmb_byte_enable;
LMB_Byte_enable_24 <= lmb_byte_enable;
LMB_Byte_enable_25 <= lmb_byte_enable;
LMB_Byte_enable_26 <= lmb_byte_enable;
LMB_Byte_enable_27 <= lmb_byte_enable;
LMB_Byte_enable_28 <= lmb_byte_enable;
LMB_Byte_enable_29 <= lmb_byte_enable;
LMB_Byte_enable_30 <= lmb_byte_enable;
LMB_Byte_enable_31 <= lmb_byte_enable;
Generate_LMB_Inputs : process (mb_debug_enabled, lmb_data_read_vec_q, lmb_ready_vec_q, lmb_wait_vec_q, lmb_ue_vec_q)
variable data_mask : std_logic_vector(0 to C_DATA_SIZE - 1);
variable data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
variable ready : std_logic;
variable wait_i : std_logic;
variable ue : std_logic;
begin -- process Generate_LMB_Inputs
data_read := (others => '0');
ready := '0';
wait_i := '0';
ue := '0';
for I in 0 to C_EN_WIDTH - 1 loop
data_mask := (0 to C_DATA_SIZE - 1 => mb_debug_enabled(I));
data_read := data_read or (lmb_data_read_vec_q(I) and data_mask);
ready := ready or (lmb_ready_vec_q(I) and mb_debug_enabled(I));
wait_i := wait_i or (lmb_wait_vec_q(I) and mb_debug_enabled(I));
ue := ue or (lmb_ue_vec_q(I) and mb_debug_enabled(I));
end loop;
lmb_data_read <= data_read;
lmb_ready <= ready;
lmb_wait <= wait_i;
lmb_ue <= ue;
end process Generate_LMB_Inputs;
Clock_LMB_Inputs : process (M_AXI_ACLK)
begin
if M_AXI_ACLK'event and M_AXI_ACLK = '1' then -- rising clock edge
for I in 0 to C_EN_WIDTH - 1 loop
lmb_data_read_vec_q(I) <= lmb_data_read_vec(I);
lmb_ready_vec_q(I) <= lmb_ready_vec(I);
lmb_wait_vec_q(I) <= lmb_wait_vec(I);
lmb_ue_vec_q(I) <= lmb_ue_vec(I);
end loop;
end if;
end process Clock_LMB_Inputs;
lmb_data_read_vec(0) <= LMB_Data_Read_0;
lmb_data_read_vec(1) <= LMB_Data_Read_1;
lmb_data_read_vec(2) <= LMB_Data_Read_2;
lmb_data_read_vec(3) <= LMB_Data_Read_3;
lmb_data_read_vec(4) <= LMB_Data_Read_4;
lmb_data_read_vec(5) <= LMB_Data_Read_5;
lmb_data_read_vec(6) <= LMB_Data_Read_6;
lmb_data_read_vec(7) <= LMB_Data_Read_7;
lmb_data_read_vec(8) <= LMB_Data_Read_8;
lmb_data_read_vec(9) <= LMB_Data_Read_9;
lmb_data_read_vec(10) <= LMB_Data_Read_10;
lmb_data_read_vec(11) <= LMB_Data_Read_11;
lmb_data_read_vec(12) <= LMB_Data_Read_12;
lmb_data_read_vec(13) <= LMB_Data_Read_13;
lmb_data_read_vec(14) <= LMB_Data_Read_14;
lmb_data_read_vec(15) <= LMB_Data_Read_15;
lmb_data_read_vec(16) <= LMB_Data_Read_16;
lmb_data_read_vec(17) <= LMB_Data_Read_17;
lmb_data_read_vec(18) <= LMB_Data_Read_18;
lmb_data_read_vec(19) <= LMB_Data_Read_19;
lmb_data_read_vec(20) <= LMB_Data_Read_20;
lmb_data_read_vec(21) <= LMB_Data_Read_21;
lmb_data_read_vec(22) <= LMB_Data_Read_22;
lmb_data_read_vec(23) <= LMB_Data_Read_23;
lmb_data_read_vec(24) <= LMB_Data_Read_24;
lmb_data_read_vec(25) <= LMB_Data_Read_25;
lmb_data_read_vec(26) <= LMB_Data_Read_26;
lmb_data_read_vec(27) <= LMB_Data_Read_27;
lmb_data_read_vec(28) <= LMB_Data_Read_28;
lmb_data_read_vec(29) <= LMB_Data_Read_29;
lmb_data_read_vec(30) <= LMB_Data_Read_30;
lmb_data_read_vec(31) <= LMB_Data_Read_31;
lmb_ready_vec(0) <= LMB_Ready_0;
lmb_ready_vec(1) <= LMB_Ready_1;
lmb_ready_vec(2) <= LMB_Ready_2;
lmb_ready_vec(3) <= LMB_Ready_3;
lmb_ready_vec(4) <= LMB_Ready_4;
lmb_ready_vec(5) <= LMB_Ready_5;
lmb_ready_vec(6) <= LMB_Ready_6;
lmb_ready_vec(7) <= LMB_Ready_7;
lmb_ready_vec(8) <= LMB_Ready_8;
lmb_ready_vec(9) <= LMB_Ready_9;
lmb_ready_vec(10) <= LMB_Ready_10;
lmb_ready_vec(11) <= LMB_Ready_11;
lmb_ready_vec(12) <= LMB_Ready_12;
lmb_ready_vec(13) <= LMB_Ready_13;
lmb_ready_vec(14) <= LMB_Ready_14;
lmb_ready_vec(15) <= LMB_Ready_15;
lmb_ready_vec(16) <= LMB_Ready_16;
lmb_ready_vec(17) <= LMB_Ready_17;
lmb_ready_vec(18) <= LMB_Ready_18;
lmb_ready_vec(19) <= LMB_Ready_19;
lmb_ready_vec(20) <= LMB_Ready_20;
lmb_ready_vec(21) <= LMB_Ready_21;
lmb_ready_vec(22) <= LMB_Ready_22;
lmb_ready_vec(23) <= LMB_Ready_23;
lmb_ready_vec(24) <= LMB_Ready_24;
lmb_ready_vec(25) <= LMB_Ready_25;
lmb_ready_vec(26) <= LMB_Ready_26;
lmb_ready_vec(27) <= LMB_Ready_27;
lmb_ready_vec(28) <= LMB_Ready_28;
lmb_ready_vec(29) <= LMB_Ready_29;
lmb_ready_vec(30) <= LMB_Ready_30;
lmb_ready_vec(31) <= LMB_Ready_31;
lmb_wait_vec(0) <= LMB_Wait_0;
lmb_wait_vec(1) <= LMB_Wait_1;
lmb_wait_vec(2) <= LMB_Wait_2;
lmb_wait_vec(3) <= LMB_Wait_3;
lmb_wait_vec(4) <= LMB_Wait_4;
lmb_wait_vec(5) <= LMB_Wait_5;
lmb_wait_vec(6) <= LMB_Wait_6;
lmb_wait_vec(7) <= LMB_Wait_7;
lmb_wait_vec(8) <= LMB_Wait_8;
lmb_wait_vec(9) <= LMB_Wait_9;
lmb_wait_vec(10) <= LMB_Wait_10;
lmb_wait_vec(11) <= LMB_Wait_11;
lmb_wait_vec(12) <= LMB_Wait_12;
lmb_wait_vec(13) <= LMB_Wait_13;
lmb_wait_vec(14) <= LMB_Wait_14;
lmb_wait_vec(15) <= LMB_Wait_15;
lmb_wait_vec(16) <= LMB_Wait_16;
lmb_wait_vec(17) <= LMB_Wait_17;
lmb_wait_vec(18) <= LMB_Wait_18;
lmb_wait_vec(19) <= LMB_Wait_19;
lmb_wait_vec(20) <= LMB_Wait_20;
lmb_wait_vec(21) <= LMB_Wait_21;
lmb_wait_vec(22) <= LMB_Wait_22;
lmb_wait_vec(23) <= LMB_Wait_23;
lmb_wait_vec(24) <= LMB_Wait_24;
lmb_wait_vec(25) <= LMB_Wait_25;
lmb_wait_vec(26) <= LMB_Wait_26;
lmb_wait_vec(27) <= LMB_Wait_27;
lmb_wait_vec(28) <= LMB_Wait_28;
lmb_wait_vec(29) <= LMB_Wait_29;
lmb_wait_vec(30) <= LMB_Wait_30;
lmb_wait_vec(31) <= LMB_Wait_31;
lmb_ue_vec(0) <= LMB_UE_0;
lmb_ue_vec(1) <= LMB_UE_1;
lmb_ue_vec(2) <= LMB_UE_2;
lmb_ue_vec(3) <= LMB_UE_3;
lmb_ue_vec(4) <= LMB_UE_4;
lmb_ue_vec(5) <= LMB_UE_5;
lmb_ue_vec(6) <= LMB_UE_6;
lmb_ue_vec(7) <= LMB_UE_7;
lmb_ue_vec(8) <= LMB_UE_8;
lmb_ue_vec(9) <= LMB_UE_9;
lmb_ue_vec(10) <= LMB_UE_10;
lmb_ue_vec(11) <= LMB_UE_11;
lmb_ue_vec(12) <= LMB_UE_12;
lmb_ue_vec(13) <= LMB_UE_13;
lmb_ue_vec(14) <= LMB_UE_14;
lmb_ue_vec(15) <= LMB_UE_15;
lmb_ue_vec(16) <= LMB_UE_16;
lmb_ue_vec(17) <= LMB_UE_17;
lmb_ue_vec(18) <= LMB_UE_18;
lmb_ue_vec(19) <= LMB_UE_19;
lmb_ue_vec(20) <= LMB_UE_20;
lmb_ue_vec(21) <= LMB_UE_21;
lmb_ue_vec(22) <= LMB_UE_22;
lmb_ue_vec(23) <= LMB_UE_23;
lmb_ue_vec(24) <= LMB_UE_24;
lmb_ue_vec(25) <= LMB_UE_25;
lmb_ue_vec(26) <= LMB_UE_26;
lmb_ue_vec(27) <= LMB_UE_27;
lmb_ue_vec(28) <= LMB_UE_28;
lmb_ue_vec(29) <= LMB_UE_29;
lmb_ue_vec(30) <= LMB_UE_30;
lmb_ue_vec(31) <= LMB_UE_31;
end generate Use_Bus_MASTER;
No_Bus_MASTER : if (C_DBG_MEM_ACCESS = 0) generate
begin
master_rd_idle <= '1';
master_rd_resp <= "00";
master_wr_idle <= '1';
master_wr_resp <= "00";
master_data_out <= (others => '0');
master_data_exists <= '0';
master_data_empty <= '1';
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= (others => '0');
M_AXI_AWLEN <= (others => '0');
M_AXI_AWSIZE <= (others => '0');
M_AXI_AWBURST <= (others => '0');
M_AXI_AWLOCK <= '0';
M_AXI_AWCACHE <= (others => '0');
M_AXI_AWPROT <= (others => '0');
M_AXI_AWQOS <= (others => '0');
M_AXI_AWVALID <= '0';
M_AXI_WDATA <= (others => '0');
M_AXI_WSTRB <= (others => '0');
M_AXI_WLAST <= '0';
M_AXI_WVALID <= '0';
M_AXI_BREADY <= '0';
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= (others => '0');
M_AXI_ARBURST <= (others => '0');
M_AXI_ARLOCK <= '0';
M_AXI_ARCACHE <= (others => '0');
M_AXI_ARPROT <= (others => '0');
M_AXI_ARQOS <= (others => '0');
M_AXI_ARVALID <= '0';
M_AXI_RREADY <= '0';
LMB_Data_Addr_0 <= (others => '0');
LMB_Data_Write_0 <= (others => '0');
LMB_Addr_Strobe_0 <= '0';
LMB_Read_Strobe_0 <= '0';
LMB_Write_Strobe_0 <= '0';
LMB_Byte_Enable_0 <= (others => '0');
LMB_Data_Addr_1 <= (others => '0');
LMB_Data_Write_1 <= (others => '0');
LMB_Addr_Strobe_1 <= '0';
LMB_Read_Strobe_1 <= '0';
LMB_Write_Strobe_1 <= '0';
LMB_Byte_Enable_1 <= (others => '0');
LMB_Data_Addr_2 <= (others => '0');
LMB_Data_Write_2 <= (others => '0');
LMB_Addr_Strobe_2 <= '0';
LMB_Read_Strobe_2 <= '0';
LMB_Write_Strobe_2 <= '0';
LMB_Byte_Enable_2 <= (others => '0');
LMB_Data_Addr_3 <= (others => '0');
LMB_Data_Write_3 <= (others => '0');
LMB_Addr_Strobe_3 <= '0';
LMB_Read_Strobe_3 <= '0';
LMB_Write_Strobe_3 <= '0';
LMB_Byte_Enable_3 <= (others => '0');
LMB_Data_Addr_4 <= (others => '0');
LMB_Data_Write_4 <= (others => '0');
LMB_Addr_Strobe_4 <= '0';
LMB_Read_Strobe_4 <= '0';
LMB_Write_Strobe_4 <= '0';
LMB_Byte_Enable_4 <= (others => '0');
LMB_Data_Addr_5 <= (others => '0');
LMB_Data_Write_5 <= (others => '0');
LMB_Addr_Strobe_5 <= '0';
LMB_Read_Strobe_5 <= '0';
LMB_Write_Strobe_5 <= '0';
LMB_Byte_Enable_5 <= (others => '0');
LMB_Data_Addr_6 <= (others => '0');
LMB_Data_Write_6 <= (others => '0');
LMB_Addr_Strobe_6 <= '0';
LMB_Read_Strobe_6 <= '0';
LMB_Write_Strobe_6 <= '0';
LMB_Byte_Enable_6 <= (others => '0');
LMB_Data_Addr_7 <= (others => '0');
LMB_Data_Write_7 <= (others => '0');
LMB_Addr_Strobe_7 <= '0';
LMB_Read_Strobe_7 <= '0';
LMB_Write_Strobe_7 <= '0';
LMB_Byte_Enable_7 <= (others => '0');
LMB_Data_Addr_8 <= (others => '0');
LMB_Data_Write_8 <= (others => '0');
LMB_Addr_Strobe_8 <= '0';
LMB_Read_Strobe_8 <= '0';
LMB_Write_Strobe_8 <= '0';
LMB_Byte_Enable_8 <= (others => '0');
LMB_Data_Addr_9 <= (others => '0');
LMB_Data_Write_9 <= (others => '0');
LMB_Addr_Strobe_9 <= '0';
LMB_Read_Strobe_9 <= '0';
LMB_Write_Strobe_9 <= '0';
LMB_Byte_Enable_9 <= (others => '0');
LMB_Data_Addr_10 <= (others => '0');
LMB_Data_Write_10 <= (others => '0');
LMB_Addr_Strobe_10 <= '0';
LMB_Read_Strobe_10 <= '0';
LMB_Write_Strobe_10 <= '0';
LMB_Byte_Enable_10 <= (others => '0');
LMB_Data_Addr_11 <= (others => '0');
LMB_Data_Write_11 <= (others => '0');
LMB_Addr_Strobe_11 <= '0';
LMB_Read_Strobe_11 <= '0';
LMB_Write_Strobe_11 <= '0';
LMB_Byte_Enable_11 <= (others => '0');
LMB_Data_Addr_12 <= (others => '0');
LMB_Data_Write_12 <= (others => '0');
LMB_Addr_Strobe_12 <= '0';
LMB_Read_Strobe_12 <= '0';
LMB_Write_Strobe_12 <= '0';
LMB_Byte_Enable_12 <= (others => '0');
LMB_Data_Addr_13 <= (others => '0');
LMB_Data_Write_13 <= (others => '0');
LMB_Addr_Strobe_13 <= '0';
LMB_Read_Strobe_13 <= '0';
LMB_Write_Strobe_13 <= '0';
LMB_Byte_Enable_13 <= (others => '0');
LMB_Data_Addr_14 <= (others => '0');
LMB_Data_Write_14 <= (others => '0');
LMB_Addr_Strobe_14 <= '0';
LMB_Read_Strobe_14 <= '0';
LMB_Write_Strobe_14 <= '0';
LMB_Byte_Enable_14 <= (others => '0');
LMB_Data_Addr_15 <= (others => '0');
LMB_Data_Write_15 <= (others => '0');
LMB_Addr_Strobe_15 <= '0';
LMB_Read_Strobe_15 <= '0';
LMB_Write_Strobe_15 <= '0';
LMB_Byte_Enable_15 <= (others => '0');
LMB_Data_Addr_16 <= (others => '0');
LMB_Data_Write_16 <= (others => '0');
LMB_Addr_Strobe_16 <= '0';
LMB_Read_Strobe_16 <= '0';
LMB_Write_Strobe_16 <= '0';
LMB_Byte_Enable_16 <= (others => '0');
LMB_Data_Addr_17 <= (others => '0');
LMB_Data_Write_17 <= (others => '0');
LMB_Addr_Strobe_17 <= '0';
LMB_Read_Strobe_17 <= '0';
LMB_Write_Strobe_17 <= '0';
LMB_Byte_Enable_17 <= (others => '0');
LMB_Data_Addr_18 <= (others => '0');
LMB_Data_Write_18 <= (others => '0');
LMB_Addr_Strobe_18 <= '0';
LMB_Read_Strobe_18 <= '0';
LMB_Write_Strobe_18 <= '0';
LMB_Byte_Enable_18 <= (others => '0');
LMB_Data_Addr_19 <= (others => '0');
LMB_Data_Write_19 <= (others => '0');
LMB_Addr_Strobe_19 <= '0';
LMB_Read_Strobe_19 <= '0';
LMB_Write_Strobe_19 <= '0';
LMB_Byte_Enable_19 <= (others => '0');
LMB_Data_Addr_20 <= (others => '0');
LMB_Data_Write_20 <= (others => '0');
LMB_Addr_Strobe_20 <= '0';
LMB_Read_Strobe_20 <= '0';
LMB_Write_Strobe_20 <= '0';
LMB_Byte_Enable_20 <= (others => '0');
LMB_Data_Addr_21 <= (others => '0');
LMB_Data_Write_21 <= (others => '0');
LMB_Addr_Strobe_21 <= '0';
LMB_Read_Strobe_21 <= '0';
LMB_Write_Strobe_21 <= '0';
LMB_Byte_Enable_21 <= (others => '0');
LMB_Data_Addr_22 <= (others => '0');
LMB_Data_Write_22 <= (others => '0');
LMB_Addr_Strobe_22 <= '0';
LMB_Read_Strobe_22 <= '0';
LMB_Write_Strobe_22 <= '0';
LMB_Byte_Enable_22 <= (others => '0');
LMB_Data_Addr_23 <= (others => '0');
LMB_Data_Write_23 <= (others => '0');
LMB_Addr_Strobe_23 <= '0';
LMB_Read_Strobe_23 <= '0';
LMB_Write_Strobe_23 <= '0';
LMB_Byte_Enable_23 <= (others => '0');
LMB_Data_Addr_24 <= (others => '0');
LMB_Data_Write_24 <= (others => '0');
LMB_Addr_Strobe_24 <= '0';
LMB_Read_Strobe_24 <= '0';
LMB_Write_Strobe_24 <= '0';
LMB_Byte_Enable_24 <= (others => '0');
LMB_Data_Addr_25 <= (others => '0');
LMB_Data_Write_25 <= (others => '0');
LMB_Addr_Strobe_25 <= '0';
LMB_Read_Strobe_25 <= '0';
LMB_Write_Strobe_25 <= '0';
LMB_Byte_Enable_25 <= (others => '0');
LMB_Data_Addr_26 <= (others => '0');
LMB_Data_Write_26 <= (others => '0');
LMB_Addr_Strobe_26 <= '0';
LMB_Read_Strobe_26 <= '0';
LMB_Write_Strobe_26 <= '0';
LMB_Byte_Enable_26 <= (others => '0');
LMB_Data_Addr_27 <= (others => '0');
LMB_Data_Write_27 <= (others => '0');
LMB_Addr_Strobe_27 <= '0';
LMB_Read_Strobe_27 <= '0';
LMB_Write_Strobe_27 <= '0';
LMB_Byte_Enable_27 <= (others => '0');
LMB_Data_Addr_28 <= (others => '0');
LMB_Data_Write_28 <= (others => '0');
LMB_Addr_Strobe_28 <= '0';
LMB_Read_Strobe_28 <= '0';
LMB_Write_Strobe_28 <= '0';
LMB_Byte_Enable_28 <= (others => '0');
LMB_Data_Addr_29 <= (others => '0');
LMB_Data_Write_29 <= (others => '0');
LMB_Addr_Strobe_29 <= '0';
LMB_Read_Strobe_29 <= '0';
LMB_Write_Strobe_29 <= '0';
LMB_Byte_Enable_29 <= (others => '0');
LMB_Data_Addr_30 <= (others => '0');
LMB_Data_Write_30 <= (others => '0');
LMB_Addr_Strobe_30 <= '0';
LMB_Read_Strobe_30 <= '0';
LMB_Write_Strobe_30 <= '0';
LMB_Byte_Enable_30 <= (others => '0');
LMB_Data_Addr_31 <= (others => '0');
LMB_Data_Write_31 <= (others => '0');
LMB_Addr_Strobe_31 <= '0';
LMB_Read_Strobe_31 <= '0';
LMB_Write_Strobe_31 <= '0';
LMB_Byte_Enable_31 <= (others => '0');
end generate No_Bus_MASTER;
Use_AXI_IPIF : if (C_USE_UART = 1) or (C_DBG_REG_ACCESS = 1) generate
begin
-- ip2bus_data assignment - as core may use less than 32 bits
ip2bus_data(C_S_AXI_DATA_WIDTH-1 downto C_REG_DATA_WIDTH) <= (others => '0');
---------------------------------------------------------------------------
-- AXI lite IPIF
---------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v2_0.axi_lite_ipif
generic map (
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end generate Use_AXI_IPIF;
No_AXI_IPIF : if (C_USE_UART = 0) and (C_DBG_REG_ACCESS = 0) generate
begin
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
S_AXI_BRESP <= (others => '0');
S_AXI_BVALID <= '0';
S_AXI_ARREADY <= '0';
S_AXI_RDATA <= (others => '0');
S_AXI_RRESP <= (others => '0');
S_AXI_RVALID <= '0';
bus2ip_clk <= '0';
bus2ip_resetn <= '0';
bus2ip_data <= (others => '0');
bus2ip_rdce <= (others => '0');
bus2ip_wrce <= (others => '0');
bus2ip_cs <= (others => '0');
end generate No_AXI_IPIF;
end architecture IMP;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity uart_bridge is
port (
-- UART Interface
uart_clock : in std_logic ;
uart_reset : in std_logic ;
uart_enable : in std_logic ;
uart_rxd : out std_logic ;
uart_txd : out std_logic ;
-- SPI Interface
spi_clock : in std_logic ;
spi_reset : in std_logic ;
spi_sclk : out std_logic ;
spi_miso : in std_logic ;
spi_mosi : out std_logic ;
spi_csn : out std_logic
) ;
end entity ; -- uart_bridge
architecture arch of uart_bridge is
-- UART to SPI FIFO signals
signal u2s_write : std_logic ;
signal u2s_full : std_logic ;
signal u2s_data : std_logic_vector(7 downto 0) ;
-- SPI to UART FIFO signals
signal s2u_read : std_logic ;
signal s2u_empty : std_logic ;
signal s2u_data : std_logic_vector(7 downto 0) ;
begin
-- UART interface
U_uart : entity work.uart
port map (
-- Control signals
clock => uart_clock,
reset => uart_reset,
enable => uart_enable,
-- External UART signals
rs232_rxd => uart_rxd,
rs232_txd => uart_txd,
-- FIFO signals for UART to FIFO from external interface
txd_we => u2s_write,
txd_full => u2s_full,
txd_wdata => u2s_data,
-- FIFO signals for FIFO to UART to be transmitted back
rxd_re => s2u_read,
rxd_empty => s2u_empty,
rxd_rdata => s2u_data
) ;
-- Dual clock FIFO for UART -> SPI comms
U_u2s_fifo : entity work.async_fifo
port map (
-- Write side: UART
w_clock => uart_clock,
w_enable => u2s_write,
w_data => u2s_data,
w_empty => open,
w_full => u2s_full,
-- Read side: SPI
r_clock => spi_clock,
r_enable => spi_read,
r_data => spi_data,
r_empty => spi_empty,
r_full => open
) ;
-- Dual clock FIFO for SPI -> UART comms
U_s2u_fifo : entity work.async_fifo
port map (
-- Write side: SPI
w_clock => spi_clock,
w_enable => spi_readback_wen,
w_data => spi_readback_data,
w_empty => open,
w_full => s2u_full,
-- Read side: UART
r_clock => uart_clock,
r_enable => s2u_read,
r_data => s2u_data,
r_empty => s2u_empty,
r_full => open
) ;
-- LMS SPI interface
U_lms_spi : entity lms_spi
port map (
-- Control signals
clock => spi_clock,
reset => spi_reset,
-- SPI data stream
spi_data => spi_data,
spi_read => spi_read,
spi_empty => spi_empty,
-- SPI readback data stream
readback_data => spi_readback_data,
readback_enable => spi_readback_wen
) ;
end architecture ; -- arch
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_ds_buf:2.1
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_ds_buf_v2_01_a;
USE util_ds_buf_v2_01_a.util_ds_buf;
ENTITY system_util_ds_buf_0_0 IS
PORT (
BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_util_ds_buf_0_0;
ARCHITECTURE system_util_ds_buf_0_0_arch OF system_util_ds_buf_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_ds_buf_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_ds_buf IS
GENERIC (
C_BUF_TYPE : STRING;
C_SIZE : INTEGER
);
PORT (
IBUF_DS_P : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_DS_N : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_OUT : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_DS_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_IN : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_DS_P : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_DS_N : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_DS_P : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_DS_N : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_T : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFH_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFH_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CEMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CLR : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CLRMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_DIV : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
BUFG_GT_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_ds_buf;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_util_ds_buf_0_0_arch: ARCHITECTURE IS "util_ds_buf,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_util_ds_buf_0_0_arch : ARCHITECTURE IS "system_util_ds_buf_0_0,util_ds_buf,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_util_ds_buf_0_0_arch: ARCHITECTURE IS "system_util_ds_buf_0_0,util_ds_buf,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_ds_buf,x_ipVersion=2.1,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_BUF_TYPE=BUFG,C_SIZE=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF BUFG_I: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_I CLK";
ATTRIBUTE X_INTERFACE_INFO OF BUFG_O: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_O CLK";
BEGIN
U0 : util_ds_buf
GENERIC MAP (
C_BUF_TYPE => "BUFG",
C_SIZE => 1
)
PORT MAP (
IBUF_DS_P => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IBUF_DS_N => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
OBUF_IN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IOBUF_IO_T => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IOBUF_IO_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_I => BUFG_I,
BUFG_O => BUFG_O,
BUFGCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFGCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFH_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFHCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFHCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CEMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CLR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CLRMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_DIV => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3))
);
END system_util_ds_buf_0_0_arch;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE work.flink_definitions.ALL;
--USE work.UART_pkg.ALL;
entity uartDevice_S00_AXI is
generic (
-- Users to add parameters here
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
number_of_uarts: INTEGER RANGE 0 TO 16 := 1;--number of uarts which will be generated
base_clk: INTEGER RANGE 0 TO 2147483647 := 100000000;--clock frequency which is used on the clock input signal of this block
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of ID for for write address, write data, read address and read data
C_S_AXI_ID_WIDTH : integer := 1;
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 12
);
port (
-- Users to add ports here
islv_rx : IN STD_LOGIC_VECTOR(number_of_uarts-1 DOWNTO 0);
oslv_tx : OUT STD_LOGIC_VECTOR(number_of_uarts-1 DOWNTO 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write Address ID
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write address
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid write address and
-- control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_AWREADY : out std_logic;
-- Write Data
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte
-- lanes hold valid data. There is one write strobe
-- bit for each eight bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write last. This signal indicates the last transfer
-- in a write burst.
S_AXI_WLAST : in std_logic;
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Response ID tag. This signal is the ID tag of the
-- write response.
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the
-- channel is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address ID. This signal is the identification
-- tag for the read address group of signals.
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read address. This signal indicates the initial
-- address of a read burst transaction.
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Quality of Service, QoS identifier sent for each
-- read transaction.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_ARREADY : out std_logic;
-- Read ID tag. This signal is the identification tag
-- for the read data group of signals generated by the slave.
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read Data
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of
-- the read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read last. This signal indicates the last transfer
-- in a read burst.
S_AXI_RLAST : out std_logic;
-- Read valid. This signal indicates that the channel
-- is signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end uartDevice_S00_AXI;
architecture arch_imp of uartDevice_S00_AXI is
-- AXI4FULL signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rlast : std_logic;
signal axi_rvalid : std_logic;
-- aw_wrap_en determines wrap boundary and enables wrapping
signal aw_wrap_en : std_logic;
-- ar_wrap_en determines wrap boundary and enables wrapping
signal ar_wrap_en : std_logic;
-- aw_wrap_size is the size of the write transfer, the
-- write address wraps to a lower address if upper address
-- limit is reached
signal aw_wrap_size : integer;
-- ar_wrap_size is the size of the read transfer, the
-- read address wraps to a lower address if upper address
-- limit is reached
signal ar_wrap_size : integer;
-- The axi_awv_awr_flag flag marks the presence of write address valid
signal axi_awv_awr_flag : std_logic;
--The axi_arv_arr_flag flag marks the presence of read address valid
signal axi_arv_arr_flag : std_logic;
-- The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
signal axi_awlen_cntr : std_logic_vector(7 downto 0);
--The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
signal axi_arlen_cntr : std_logic_vector(7 downto 0);
signal axi_arburst : std_logic_vector(2-1 downto 0);
signal axi_awburst : std_logic_vector(2-1 downto 0);
signal axi_arlen : std_logic_vector(8-1 downto 0);
signal axi_awlen : std_logic_vector(8-1 downto 0);
--local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
--ADDR_LSB is used for addressing 32/64 bit registers/memories
--ADDR_LSB = 2 for 32 bits (n downto 2)
--ADDR_LSB = 3 for 42 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
constant USER_NUM_MEM: integer := 1;
constant low : std_logic_vector (C_S_AXI_ADDR_WIDTH - 1 downto 0) := (OTHERS => '0');
CONSTANT c_usig_typdef_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_mem_size_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_number_of_channels_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_unique_id_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_status_reg_address: STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_status_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_configuration_reg_address: STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_configuration_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_base_clk_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_std_registers*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_divider_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_base_clk_address) + 4);
CONSTANT c_usig_tx_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_divider_address) + number_of_uarts*4);
CONSTANT c_usig_rx_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_tx_address) + number_of_uarts*4);
CONSTANT c_usig_stat_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_rx_address) + number_of_uarts*4);
CONSTANT c_usig_max_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_stat_address) + number_of_uarts*4);
CONSTANT id : STD_LOGIC_VECTOR(15 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_uart_id,16));
CONSTANT subtype_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'0');
CONSTANT interface_version : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'0');
TYPE t_uart_reg IS RECORD
divider : STD_LOGIC_VECTOR(31 DOWNTO 0);
tx : STD_LOGIC_VECTOR(7 DOWNTO 0);
rx : STD_LOGIC_VECTOR(7 DOWNTO 0);
uart_reset : STD_LOGIC;
sl_read_strobe : STD_LOGIC;
sl_read_strobe_d1 : STD_LOGIC;
sl_rx_read_data : STD_LOGIC;
sl_write_strobe : STD_LOGIC;
sl_write_strobe_d1 : STD_LOGIC;
sl_tx_write_data : STD_LOGIC;
END RECORD;
Type t_uart_regs IS ARRAY(number_of_uarts-1 DOWNTO 0) OF t_uart_reg;
TYPE t_internal_register IS RECORD
conf_reg : STD_LOGIC_VECTOR(0 DOWNTO 0);
uart : t_uart_regs;
END RECORD;
CONSTANT INTERNAL_REG_RESET : t_internal_register := (
conf_reg=> (OTHERS=>'0'),
uart => (OTHERS => (divider => x"0000A2C0",
tx => (OTHERS => '0'),
rx => (OTHERS => '0'),
uart_reset => '0',
sl_read_strobe => '0',
sl_read_strobe_d1 => '0',
sl_rx_read_data => '0',
sl_write_strobe => '0',
sl_write_strobe_d1 => '0',
sl_tx_write_data => '0'))
);
SIGNAL ri,ri_next : t_internal_register := INTERNAL_REG_RESET;
TYPE sig_array IS ARRAY (number_of_uarts-1 DOWNTO 0) of STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL slv8_uart_rx_data : sig_array;
TYPE sig_count_array IS ARRAY (number_of_uarts-1 DOWNTO 0) of STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL slv10_uart_rx_count : sig_count_array;
SIGNAL slv_rx_fifo_empty : STD_LOGIC_VECTOR(number_of_uarts-1 DOWNTO 0);
SIGNAL slv_rx_fifo_half : STD_LOGIC_VECTOR(number_of_uarts-1 DOWNTO 0);
SIGNAL slv_rx_fifo_full : STD_LOGIC_VECTOR(number_of_uarts-1 DOWNTO 0);
SIGNAL slv_tx_fifo_empty : STD_LOGIC_VECTOR(number_of_uarts-1 DOWNTO 0);
SIGNAL slv_tx_fifo_half : STD_LOGIC_VECTOR(number_of_uarts-1 DOWNTO 0);
SIGNAL slv_tx_fifo_full : STD_LOGIC_VECTOR(number_of_uarts-1 DOWNTO 0);
------------------------------------------------
---- Signals for user logic memory space example
--------------------------------------------------
signal mem_address : std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
signal mem_select : std_logic_vector(USER_NUM_MEM-1 downto 0);
type word_array is array (0 to USER_NUM_MEM-1) of std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal mem_data_out : word_array;
signal i : integer;
signal j : integer;
signal mem_byte_index : integer;
type BYTE_RAM_TYPE is array (0 to 15) of std_logic_vector(7 downto 0);
-- UART Component
COMPONENT UART IS
PORT (
-- System Signals
isl_clk_100mhz : IN STD_LOGIC;
isl_reset : IN STD_LOGIC;
-- Serial Signals
osl_txd : OUT STD_LOGIC;
isl_rxd : IN STD_LOGIC;
-- Data Signals
isl_write_tx_data : IN STD_LOGIC;
islv8_tx_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
isl_read_rx_data : IN STD_LOGIC;
oslv8_rx_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oslv10_rx_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
islv32_div_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- FIFO Signals
osl_tx_fifo_full : OUT STD_LOGIC;
osl_tx_fifo_half : OUT STD_LOGIC;
osl_tx_fifo_empty : OUT STD_LOGIC;
osl_rx_fifo_full : OUT STD_LOGIC;
osl_rx_fifo_half : OUT STD_LOGIC;
osl_rx_fifo_empty : OUT STD_LOGIC;
-- Interrupt Signals
isl_irq_enable : IN STD_LOGIC;
osl_rx_irq : OUT STD_LOGIC
);
END COMPONENT UART;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= (OTHERS => '0');
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= (OTHERS => '0');
S_AXI_RLAST <= axi_rlast;
S_AXI_RVALID <= axi_rvalid;
S_AXI_BID <= S_AXI_AWID;
S_AXI_RID <= S_AXI_ARID;
aw_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_awlen)));
ar_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_arlen)));
aw_wrap_en <= '1' when (((axi_awaddr AND std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
ar_wrap_en <= '1' when (((axi_araddr AND std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
axi_awv_awr_flag <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
-- slave is ready to accept an address and
-- associated control signals
axi_awv_awr_flag <= '1'; -- used for generation of bresp() and bvalid
axi_awready <= '1';
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
-- preparing to accept next address after current write burst tx completion
axi_awv_awr_flag <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
axi_awburst <= (others => '0');
axi_awlen <= (others => '0');
axi_awlen_cntr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0') then
-- address latching
axi_awaddr <= S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_awlen_cntr <= (others => '0');
axi_awburst <= S_AXI_AWBURST;
axi_awlen <= S_AXI_AWLEN;
elsif((axi_awlen_cntr <= axi_awlen) and axi_wready = '1' and S_AXI_WVALID = '1') then
axi_awlen_cntr <= std_logic_vector (unsigned(axi_awlen_cntr) + 1);
case (axi_awburst) is
when "00" => -- fixed burst
-- The write address for all the beats in the transaction are fixed
axi_awaddr <= axi_awaddr; ----for awsize = 4 bytes (010)
when "01" => --incremental burst
-- The write address for all the beats in the transaction are increments by awsize
IF(S_AXI_AWSIZE = "000") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 1);
ELSIF(S_AXI_AWSIZE = "001") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 2);
ELSIF(S_AXI_AWSIZE = "010") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 4);
ELSIF(S_AXI_AWSIZE = "011") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 8);
ELSIF(S_AXI_AWSIZE = "100") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 16);
ELSE
axi_awaddr <= axi_awaddr;
END IF;
when "10" => --Wrapping burst
-- The write address wraps when the address reaches wrap boundary
if (aw_wrap_en = '1') then
axi_awaddr <= std_logic_vector (unsigned(axi_awaddr) - (to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for awsize = 4 bytes (010)
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and axi_awv_awr_flag = '1') then
axi_wready <= '1';
-- elsif (axi_awv_awr_flag = '0') then
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
else
if (axi_awv_awr_flag = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' and S_AXI_WLAST = '1' ) then
axi_bvalid <= '1';
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
--check if bready is asserted while bvalid is high)
axi_bvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_arv_arr_flag <= '0';
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
axi_arready <= '1';
axi_arv_arr_flag <= '1';
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1' and (axi_arlen_cntr = axi_arlen)) then
-- preparing to accept next address after current read completion
axi_arv_arr_flag <= '0';
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_araddr latching
--This process is used to latch the address when both
--S_AXI_ARVALID and S_AXI_RVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_araddr <= (others => '0');
axi_arburst <= (others => '0');
axi_arlen <= (others => '0');
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_arv_arr_flag = '0') then
-- address latching
axi_araddr <= S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
axi_arburst <= S_AXI_ARBURST;
axi_arlen <= S_AXI_ARLEN;
elsif((axi_arlen_cntr <= axi_arlen) and axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_arlen_cntr <= std_logic_vector (unsigned(axi_arlen_cntr) + 1);
axi_rlast <= '0';
case (axi_arburst) is
when "00" => -- fixed burst
-- The read address for all the beats in the transaction are fixed
axi_araddr <= axi_araddr; ----for arsize = 4 bytes (010)
when "01" => --incremental burst
-- The read address for all the beats in the transaction are increments by awsize
IF(S_AXI_ARSIZE = "000") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 1);
ELSIF(S_AXI_ARSIZE = "001") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 2);
ELSIF(S_AXI_ARSIZE = "010") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 4);
ELSIF(S_AXI_ARSIZE = "011") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 8);
ELSIF(S_AXI_ARSIZE = "100") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 16);
ELSE
axi_araddr <= axi_araddr;
END IF;
when "10" => --Wrapping burst
-- The read address wraps when the address reaches wrap boundary
if (ar_wrap_en = '1') then
axi_araddr <= std_logic_vector (unsigned(axi_araddr) - (to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for arsize = 4 bytes (010)
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
elsif((axi_arlen_cntr = axi_arlen) and axi_rlast = '0' and axi_arv_arr_flag = '1') then
axi_rlast <= '1';
elsif (S_AXI_RREADY = '1') then
axi_rlast <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
else
if (axi_arv_arr_flag = '1' and axi_rvalid = '0') then
axi_rvalid <= '1';
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- read and write data
PROCESS (axi_rvalid,axi_araddr,axi_wready,S_AXI_WVALID,S_AXI_WDATA,axi_awaddr,S_AXI_WSTRB,ri,S_AXI_ARESETN) is
VARIABLE reg_number: INTEGER := 0;
VARIABLE vi: t_internal_register := INTERNAL_REG_RESET;
BEGIN
vi := ri;
FOR i IN 0 TO number_of_uarts-1 LOOP -- Single cycle signal
vi.uart(i).sl_write_strobe_d1 := vi.uart(i).sl_write_strobe;
vi.uart(i).sl_write_strobe := '0';
vi.uart(i).sl_read_strobe_d1 := vi.uart(i).sl_read_strobe;
vi.uart(i).sl_read_strobe := '0';
END LOOP;
IF (axi_rvalid = '1') THEN
IF (axi_araddr = c_usig_typdef_address) THEN
axi_rdata(31 DOWNTO 16) <= id;
axi_rdata(15 DOWNTO 8) <= subtype_id;
axi_rdata(7 DOWNTO 0) <= interface_version;
ELSIF (axi_araddr = c_usig_mem_size_address)THEN
axi_rdata <= (others => '0');
axi_rdata(C_S_AXI_ADDR_WIDTH) <= '1';
ELSIF (axi_araddr = c_number_of_channels_address)THEN
axi_rdata <= STD_LOGIC_VECTOR(to_unsigned(number_of_uarts, axi_rdata'length));
ELSIF (axi_araddr = c_usig_unique_id_address) THEN
axi_rdata <= unique_id;
ELSIF (axi_araddr = c_status_reg_address) THEN
axi_rdata <= (others => '0');
ELSIF (axi_araddr = c_configuration_reg_address) THEN
axi_rdata <= (others => '0');
axi_rdata(c_fLink_reset_bit_num) <= ri.conf_reg(c_fLink_reset_bit_num);
ELSIF (axi_araddr = c_usig_base_clk_address) THEN
axi_rdata <= STD_LOGIC_VECTOR(to_unsigned(base_clk, C_S_AXI_DATA_WIDTH));
ELSIF (axi_araddr >= c_usig_divider_address AND axi_araddr < c_usig_tx_address) THEN
axi_rdata <= STD_LOGIC_VECTOR(ri.uart(to_integer(unsigned(axi_araddr) - unsigned(c_usig_divider_address))/4).divider);
ELSIF (axi_araddr >= c_usig_tx_address AND axi_araddr < c_usig_rx_address) THEN
axi_rdata <= (OTHERS=>'0');
axi_rdata(7 DOWNTO 0) <= STD_LOGIC_VECTOR(ri.uart(to_integer(unsigned(axi_araddr) - unsigned(c_usig_tx_address))/4).tx);
ELSIF (axi_araddr >= c_usig_rx_address AND axi_araddr < c_usig_stat_address) THEN
axi_rdata <= (OTHERS=>'0');
axi_rdata(7 DOWNTO 0) <= STD_LOGIC_VECTOR(ri.uart(to_integer(unsigned(axi_araddr) - unsigned(c_usig_rx_address))/4).rx);
reg_number := (to_integer(unsigned(axi_araddr)) - to_integer(UNSIGNED(c_usig_rx_address)))/4;
vi.uart(reg_number).sl_read_strobe := '1';
ELSIF (axi_araddr >= c_usig_stat_address AND axi_araddr < c_usig_max_address) THEN
axi_rdata <= (OTHERS=>'0');
axi_rdata(0) <= slv_rx_fifo_empty(to_integer(unsigned(axi_araddr) - unsigned(c_usig_stat_address))/4);
axi_rdata(1) <= slv_rx_fifo_half(to_integer(unsigned(axi_araddr) - unsigned(c_usig_stat_address))/4);
axi_rdata(2) <= slv_rx_fifo_full(to_integer(unsigned(axi_araddr) - unsigned(c_usig_stat_address))/4);
axi_rdata(4) <= slv_tx_fifo_empty(to_integer(unsigned(axi_araddr) - unsigned(c_usig_stat_address))/4);
axi_rdata(5) <= slv_tx_fifo_half(to_integer(unsigned(axi_araddr) - unsigned(c_usig_stat_address))/4);
axi_rdata(6) <= slv_tx_fifo_full(to_integer(unsigned(axi_araddr) - unsigned(c_usig_stat_address))/4);
axi_rdata(25 DOWNTO 16) <= slv10_uart_rx_count(to_integer(unsigned(axi_araddr) - unsigned(c_usig_stat_address))/4);
ELSE
axi_rdata <= (others => '0');
END IF;
ELSE
axi_rdata <= (others => '0');
END IF;
-- Generate signal to advance RX FIFO
FOR i IN 0 TO number_of_uarts-1 LOOP
IF vi.uart(i).sl_read_strobe = '0' AND vi.uart(i).sl_read_strobe_d1 = '1' THEN
vi.uart(i).sl_rx_read_data := '1';
ELSE
vi.uart(i).sl_rx_read_data := '0';
END IF;
END LOOP;
FOR i IN 0 TO number_of_uarts-1 LOOP
vi.uart(i).rx := slv8_uart_rx_data(i);
END LOOP;
IF (axi_wready = '1') THEN
IF (axi_awaddr = c_configuration_reg_address) THEN
vi.conf_reg(c_fLink_reset_bit_num) := S_AXI_WDATA(c_fLink_reset_bit_num);
ELSIF (axi_awaddr >= c_usig_divider_address AND axi_awaddr < c_usig_tx_address) THEN
reg_number := (to_integer(unsigned(axi_awaddr)) - to_integer(UNSIGNED(c_usig_divider_address)))/4;
IF (S_AXI_WSTRB(0) = '1')THEN
vi.uart(reg_number).divider(7 DOWNTO 0) := S_AXI_WDATA(7 DOWNTO 0);
END IF;
IF (S_AXI_WSTRB(1) = '1')THEN
vi.uart(reg_number).divider(15 DOWNTO 8) := S_AXI_WDATA(15 DOWNTO 8);
END IF;
IF (S_AXI_WSTRB(2) = '1')THEN
vi.uart(reg_number).divider(23 DOWNTO 16) := S_AXI_WDATA(23 DOWNTO 16);
END IF;
IF (S_AXI_WSTRB(3) = '1')THEN
vi.uart(reg_number).divider(31 DOWNTO 24) := S_AXI_WDATA(31 DOWNTO 24);
END IF;
ELSIF (axi_awaddr >= c_usig_tx_address AND axi_awaddr < c_usig_rx_address) THEN
reg_number := (to_integer(unsigned(axi_awaddr)) - to_integer(UNSIGNED(c_usig_tx_address)))/4;
IF (S_AXI_WSTRB(0) = '1')THEN
vi.uart(reg_number).tx := S_AXI_WDATA(7 DOWNTO 0);
vi.uart(reg_number).sl_write_strobe := '1';
END IF;
END IF;
END IF;
-- Generate signal to advance TX FIFO
FOR i IN 0 TO number_of_uarts-1 LOOP
IF vi.uart(i).sl_write_strobe = '1' AND vi.uart(i).sl_write_strobe_d1 = '0' THEN
vi.uart(i).sl_tx_write_data := '1';
ELSE
vi.uart(i).sl_tx_write_data := '0';
END IF;
END LOOP;
FOR i IN 0 TO number_of_uarts-1 LOOP
IF(S_AXI_ARESETN = '0' OR vi.conf_reg(c_fLink_reset_bit_num) = '1' )THEN
vi := INTERNAL_REG_RESET;
vi.uart(i).uart_reset := '1';
ELSE
vi.uart(i).uart_reset := '0';
END IF;
END LOOP;
ri_next <= vi;
END PROCESS;
-- Add user logic here
--create component
gen_uart: FOR i IN 0 TO number_of_uarts-1 GENERATE
my_uart : uart PORT MAP (
isl_clk_100mhz => S_AXI_ACLK,
isl_reset => ri.uart(i).uart_reset,
osl_txd => oslv_tx(i),
isl_rxd => islv_rx(i),
isl_write_tx_data => ri.uart(i).sl_tx_write_data,
islv8_tx_data => ri.uart(i).tx,
isl_read_rx_data => ri.uart(i).sl_rx_read_data,
oslv8_rx_data => slv8_uart_rx_data(i),
oslv10_rx_count => slv10_uart_rx_count(i),
islv32_div_data => ri.uart(i).divider,
osl_tx_fifo_full => slv_tx_fifo_full(i),
osl_tx_fifo_half => slv_tx_fifo_half(i),
osl_tx_fifo_empty => slv_tx_fifo_empty(i),
osl_rx_fifo_full => slv_rx_fifo_full(i),
osl_rx_fifo_half => slv_rx_fifo_half(i),
osl_rx_fifo_empty => slv_rx_fifo_empty(i),
isl_irq_enable => '0',
osl_rx_irq => open
);
END GENERATE gen_uart;
reg_proc : PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
-- User logic ends
-- oslv_tx(0) <= ri.uart(0).sl_tx_write_data;
-- oslv_tx(1) <= ri.uart(1).sl_tx_write_data;
end arch_imp;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity uart_rx is
generic (
log2_oversampling : integer := 4);
port (
RST : in std_logic;
RDCLK : in std_logic;
CLKOSX : in std_logic;
RXD : in std_logic;
RDADDR : in std_logic_vector(8 downto 0);
RDDATA : out std_logic_vector(47 downto 0);
FRAMESEL : out std_logic);
end uart_rx;
architecture rtl of uart_rx is
type STATE_TYPE is (st0_idle, st1_read_start_bit, st2_read_data_bits, st3_read_stop_bit);
signal STATE, NEXT_STATE : STATE_TYPE;
signal WREN : std_logic;
signal WRRST : std_logic;
signal WRDATA : std_logic_vector(7 downto 0);
--signal WRCOUNT : std_logic_vector(10 downto 0);
--signal RDCOUNT : std_logic_vector(10 downto 0);
signal DIVCTR : std_logic_vector(log2_oversampling-1 downto 0);
signal DIVCTREN : std_logic;
signal BYTECTR : std_logic_vector(2 downto 0);
signal BYTECTRINC : std_logic;
signal RXDATA : std_logic;
signal NEXT_WRDATA : std_logic_vector(7 downto 0);
signal we_red : std_logic_vector(1 downto 0);
signal we_green : std_logic_vector(1 downto 0);
signal we_blue : std_logic_vector(1 downto 0);
signal rdaddr_ext : std_logic_vector(9 downto 0);
signal rd_msb : std_logic;
signal rgb_ctr : std_logic_vector(1 downto 0);
signal wr_addr : std_logic_vector(10 downto 0);
signal wr_addr_short : std_logic_vector(9 downto 0);
signal wr_inc : std_logic;
begin
i_gen : for i in 1 downto 0 generate
-- RAM for red color
ram_red : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_red(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+7 downto i*24));
-- RAM for green color
ram_green : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_green(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+15 downto i*24+8));
-- RAM for blue color
ram_blue : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_blue(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+23 downto i*24+16));
end generate i_gen;
-- Register for FSM
sync_proc : process (CLKOSX, RST)
begin
if RST = '1' then
STATE <= st0_idle;
WRDATA <= (others => '0');
RXDATA <= '1';
elsif rising_edge(CLKOSX) then
STATE <= NEXT_STATE;
WRDATA <= NEXT_WRDATA;
RXDATA <= RXD;
end if;
end process sync_proc;
-- Finite state machine (FSM)
fsm_proc : process (STATE, RXDATA, WRDATA, DIVCTR, BYTECTR)
begin
-- Default values
NEXT_STATE <= STATE; --default is to stay in current state
NEXT_WRDATA <= WRDATA;
DIVCTREN <= '1';
BYTECTRINC <= '0';
WREN <= '0';
WRRST <= '0';
case STATE is
when st0_idle =>
if (RXDATA = '0') then
NEXT_STATE <= st1_read_start_bit;
else
DIVCTREN <= '0';
end if;
when st1_read_start_bit =>
if DIVCTR(log2_oversampling-1) = '1' then
NEXT_STATE <= st2_read_data_bits;
BYTECTRINC <= '1';
DIVCTREN <= '0';
end if;
when st2_read_data_bits =>
if (DIVCTR = 2**log2_oversampling-1) then
NEXT_WRDATA(conv_integer(BYTECTR)) <= RXDATA;
if (BYTECTR = "111") then
NEXT_STATE <= st3_read_stop_bit;
else
BYTECTRINC <= '1';
end if;
end if;
when st3_read_stop_bit =>
if (DIVCTR = 2**log2_oversampling-1) then
NEXT_STATE <= st0_idle;
if WRDATA = 1 then
WREN <= '0';
WRRST <= RXDATA;
else
WREN <= RXDATA;
WRRST <= '0';
end if;
end if;
end case;
end process fsm_proc;
-- Clock divide counter
div_proc : process (CLKOSX)
begin
if rising_edge(CLKOSX) then
if DIVCTREN = '1' then
DIVCTR <= DIVCTR + 1;
else
DIVCTR <= (others => '0');
end if;
end if;
end process div_proc;
-- Byte counter
byte_proc : process (CLKOSX, RST)
begin
if RST = '1' then
BYTECTR <= (others => '1');
elsif rising_edge(CLKOSX) then
if BYTECTRINC = '1' then
BYTECTR <= BYTECTR + 1;
end if;
end if;
end process byte_proc;
-- RGB color select
we_red(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "00")) else '0';
we_green(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "01")) else '0';
we_blue(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "10")) else '0';
we_red(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "00")) else '0';
we_green(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "01")) else '0';
we_blue(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "10")) else '0';
-- RAM control signals
rgb_proc : process (CLKOSX, RST)
begin
if RST = '1' then
rgb_ctr <= (others => '0');
wr_addr <= (others => '0');
elsif rising_edge(CLKOSX) then
if WRRST = '1' then
rgb_ctr <= (others => '0');
wr_addr(9 downto 0) <= (others => '0');
elsif WREN = '1' then
if rgb_ctr = "10" then
rgb_ctr <= (others => '0');
wr_addr <= wr_addr + 1;
else
rgb_ctr <= rgb_ctr + 1;
end if;
end if;
end if;
end process rgb_proc;
-- Clock domain crossing
rd_proc : process (RDCLK)
begin
if rising_edge(RDCLK) then
rd_msb <= not wr_addr(10);
FRAMESEL <= rd_msb;
end if;
end process rd_proc;
rdaddr_ext <= rd_msb & RDADDR;
wr_addr_short <= wr_addr(10) & wr_addr(8 downto 0);
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity uart_rx is
generic (
log2_oversampling : integer := 4);
port (
RST : in std_logic;
RDCLK : in std_logic;
CLKOSX : in std_logic;
RXD : in std_logic;
RDADDR : in std_logic_vector(8 downto 0);
RDDATA : out std_logic_vector(47 downto 0);
FRAMESEL : out std_logic);
end uart_rx;
architecture rtl of uart_rx is
type STATE_TYPE is (st0_idle, st1_read_start_bit, st2_read_data_bits, st3_read_stop_bit);
signal STATE, NEXT_STATE : STATE_TYPE;
signal WREN : std_logic;
signal WRRST : std_logic;
signal WRDATA : std_logic_vector(7 downto 0);
--signal WRCOUNT : std_logic_vector(10 downto 0);
--signal RDCOUNT : std_logic_vector(10 downto 0);
signal DIVCTR : std_logic_vector(log2_oversampling-1 downto 0);
signal DIVCTREN : std_logic;
signal BYTECTR : std_logic_vector(2 downto 0);
signal BYTECTRINC : std_logic;
signal RXDATA : std_logic;
signal NEXT_WRDATA : std_logic_vector(7 downto 0);
signal we_red : std_logic_vector(1 downto 0);
signal we_green : std_logic_vector(1 downto 0);
signal we_blue : std_logic_vector(1 downto 0);
signal rdaddr_ext : std_logic_vector(9 downto 0);
signal rd_msb : std_logic;
signal rgb_ctr : std_logic_vector(1 downto 0);
signal wr_addr : std_logic_vector(10 downto 0);
signal wr_addr_short : std_logic_vector(9 downto 0);
signal wr_inc : std_logic;
begin
i_gen : for i in 1 downto 0 generate
-- RAM for red color
ram_red : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_red(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+7 downto i*24));
-- RAM for green color
ram_green : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_green(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+15 downto i*24+8));
-- RAM for blue color
ram_blue : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_blue(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+23 downto i*24+16));
end generate i_gen;
-- Register for FSM
sync_proc : process (CLKOSX, RST)
begin
if RST = '1' then
STATE <= st0_idle;
WRDATA <= (others => '0');
RXDATA <= '1';
elsif rising_edge(CLKOSX) then
STATE <= NEXT_STATE;
WRDATA <= NEXT_WRDATA;
RXDATA <= RXD;
end if;
end process sync_proc;
-- Finite state machine (FSM)
fsm_proc : process (STATE, RXDATA, WRDATA, DIVCTR, BYTECTR)
begin
-- Default values
NEXT_STATE <= STATE; --default is to stay in current state
NEXT_WRDATA <= WRDATA;
DIVCTREN <= '1';
BYTECTRINC <= '0';
WREN <= '0';
WRRST <= '0';
case STATE is
when st0_idle =>
if (RXDATA = '0') then
NEXT_STATE <= st1_read_start_bit;
else
DIVCTREN <= '0';
end if;
when st1_read_start_bit =>
if DIVCTR(log2_oversampling-1) = '1' then
NEXT_STATE <= st2_read_data_bits;
BYTECTRINC <= '1';
DIVCTREN <= '0';
end if;
when st2_read_data_bits =>
if (DIVCTR = 2**log2_oversampling-1) then
NEXT_WRDATA(conv_integer(BYTECTR)) <= RXDATA;
if (BYTECTR = "111") then
NEXT_STATE <= st3_read_stop_bit;
else
BYTECTRINC <= '1';
end if;
end if;
when st3_read_stop_bit =>
if (DIVCTR = 2**log2_oversampling-1) then
NEXT_STATE <= st0_idle;
if WRDATA = 1 then
WREN <= '0';
WRRST <= RXDATA;
else
WREN <= RXDATA;
WRRST <= '0';
end if;
end if;
end case;
end process fsm_proc;
-- Clock divide counter
div_proc : process (CLKOSX)
begin
if rising_edge(CLKOSX) then
if DIVCTREN = '1' then
DIVCTR <= DIVCTR + 1;
else
DIVCTR <= (others => '0');
end if;
end if;
end process div_proc;
-- Byte counter
byte_proc : process (CLKOSX, RST)
begin
if RST = '1' then
BYTECTR <= (others => '1');
elsif rising_edge(CLKOSX) then
if BYTECTRINC = '1' then
BYTECTR <= BYTECTR + 1;
end if;
end if;
end process byte_proc;
-- RGB color select
we_red(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "00")) else '0';
we_green(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "01")) else '0';
we_blue(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "10")) else '0';
we_red(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "00")) else '0';
we_green(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "01")) else '0';
we_blue(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "10")) else '0';
-- RAM control signals
rgb_proc : process (CLKOSX, RST)
begin
if RST = '1' then
rgb_ctr <= (others => '0');
wr_addr <= (others => '0');
elsif rising_edge(CLKOSX) then
if WRRST = '1' then
rgb_ctr <= (others => '0');
wr_addr(9 downto 0) <= (others => '0');
elsif WREN = '1' then
if rgb_ctr = "10" then
rgb_ctr <= (others => '0');
wr_addr <= wr_addr + 1;
else
rgb_ctr <= rgb_ctr + 1;
end if;
end if;
end if;
end process rgb_proc;
-- Clock domain crossing
rd_proc : process (RDCLK)
begin
if rising_edge(RDCLK) then
rd_msb <= not wr_addr(10);
FRAMESEL <= rd_msb;
end if;
end process rd_proc;
rdaddr_ext <= rd_msb & RDADDR;
wr_addr_short <= wr_addr(10) & wr_addr(8 downto 0);
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity uart_rx is
generic (
log2_oversampling : integer := 4);
port (
RST : in std_logic;
RDCLK : in std_logic;
CLKOSX : in std_logic;
RXD : in std_logic;
RDADDR : in std_logic_vector(8 downto 0);
RDDATA : out std_logic_vector(47 downto 0);
FRAMESEL : out std_logic);
end uart_rx;
architecture rtl of uart_rx is
type STATE_TYPE is (st0_idle, st1_read_start_bit, st2_read_data_bits, st3_read_stop_bit);
signal STATE, NEXT_STATE : STATE_TYPE;
signal WREN : std_logic;
signal WRRST : std_logic;
signal WRDATA : std_logic_vector(7 downto 0);
--signal WRCOUNT : std_logic_vector(10 downto 0);
--signal RDCOUNT : std_logic_vector(10 downto 0);
signal DIVCTR : std_logic_vector(log2_oversampling-1 downto 0);
signal DIVCTREN : std_logic;
signal BYTECTR : std_logic_vector(2 downto 0);
signal BYTECTRINC : std_logic;
signal RXDATA : std_logic;
signal NEXT_WRDATA : std_logic_vector(7 downto 0);
signal we_red : std_logic_vector(1 downto 0);
signal we_green : std_logic_vector(1 downto 0);
signal we_blue : std_logic_vector(1 downto 0);
signal rdaddr_ext : std_logic_vector(9 downto 0);
signal rd_msb : std_logic;
signal rgb_ctr : std_logic_vector(1 downto 0);
signal wr_addr : std_logic_vector(10 downto 0);
signal wr_addr_short : std_logic_vector(9 downto 0);
signal wr_inc : std_logic;
begin
i_gen : for i in 1 downto 0 generate
-- RAM for red color
ram_red : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_red(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+7 downto i*24));
-- RAM for green color
ram_green : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_green(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+15 downto i*24+8));
-- RAM for blue color
ram_blue : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_blue(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+23 downto i*24+16));
end generate i_gen;
-- Register for FSM
sync_proc : process (CLKOSX, RST)
begin
if RST = '1' then
STATE <= st0_idle;
WRDATA <= (others => '0');
RXDATA <= '1';
elsif rising_edge(CLKOSX) then
STATE <= NEXT_STATE;
WRDATA <= NEXT_WRDATA;
RXDATA <= RXD;
end if;
end process sync_proc;
-- Finite state machine (FSM)
fsm_proc : process (STATE, RXDATA, WRDATA, DIVCTR, BYTECTR)
begin
-- Default values
NEXT_STATE <= STATE; --default is to stay in current state
NEXT_WRDATA <= WRDATA;
DIVCTREN <= '1';
BYTECTRINC <= '0';
WREN <= '0';
WRRST <= '0';
case STATE is
when st0_idle =>
if (RXDATA = '0') then
NEXT_STATE <= st1_read_start_bit;
else
DIVCTREN <= '0';
end if;
when st1_read_start_bit =>
if DIVCTR(log2_oversampling-1) = '1' then
NEXT_STATE <= st2_read_data_bits;
BYTECTRINC <= '1';
DIVCTREN <= '0';
end if;
when st2_read_data_bits =>
if (DIVCTR = 2**log2_oversampling-1) then
NEXT_WRDATA(conv_integer(BYTECTR)) <= RXDATA;
if (BYTECTR = "111") then
NEXT_STATE <= st3_read_stop_bit;
else
BYTECTRINC <= '1';
end if;
end if;
when st3_read_stop_bit =>
if (DIVCTR = 2**log2_oversampling-1) then
NEXT_STATE <= st0_idle;
if WRDATA = 1 then
WREN <= '0';
WRRST <= RXDATA;
else
WREN <= RXDATA;
WRRST <= '0';
end if;
end if;
end case;
end process fsm_proc;
-- Clock divide counter
div_proc : process (CLKOSX)
begin
if rising_edge(CLKOSX) then
if DIVCTREN = '1' then
DIVCTR <= DIVCTR + 1;
else
DIVCTR <= (others => '0');
end if;
end if;
end process div_proc;
-- Byte counter
byte_proc : process (CLKOSX, RST)
begin
if RST = '1' then
BYTECTR <= (others => '1');
elsif rising_edge(CLKOSX) then
if BYTECTRINC = '1' then
BYTECTR <= BYTECTR + 1;
end if;
end if;
end process byte_proc;
-- RGB color select
we_red(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "00")) else '0';
we_green(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "01")) else '0';
we_blue(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "10")) else '0';
we_red(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "00")) else '0';
we_green(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "01")) else '0';
we_blue(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "10")) else '0';
-- RAM control signals
rgb_proc : process (CLKOSX, RST)
begin
if RST = '1' then
rgb_ctr <= (others => '0');
wr_addr <= (others => '0');
elsif rising_edge(CLKOSX) then
if WRRST = '1' then
rgb_ctr <= (others => '0');
wr_addr(9 downto 0) <= (others => '0');
elsif WREN = '1' then
if rgb_ctr = "10" then
rgb_ctr <= (others => '0');
wr_addr <= wr_addr + 1;
else
rgb_ctr <= rgb_ctr + 1;
end if;
end if;
end if;
end process rgb_proc;
-- Clock domain crossing
rd_proc : process (RDCLK)
begin
if rising_edge(RDCLK) then
rd_msb <= not wr_addr(10);
FRAMESEL <= rd_msb;
end if;
end process rd_proc;
rdaddr_ext <= rd_msb & RDADDR;
wr_addr_short <= wr_addr(10) & wr_addr(8 downto 0);
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity uart_rx is
generic (
log2_oversampling : integer := 4);
port (
RST : in std_logic;
RDCLK : in std_logic;
CLKOSX : in std_logic;
RXD : in std_logic;
RDADDR : in std_logic_vector(8 downto 0);
RDDATA : out std_logic_vector(47 downto 0);
FRAMESEL : out std_logic);
end uart_rx;
architecture rtl of uart_rx is
type STATE_TYPE is (st0_idle, st1_read_start_bit, st2_read_data_bits, st3_read_stop_bit);
signal STATE, NEXT_STATE : STATE_TYPE;
signal WREN : std_logic;
signal WRRST : std_logic;
signal WRDATA : std_logic_vector(7 downto 0);
--signal WRCOUNT : std_logic_vector(10 downto 0);
--signal RDCOUNT : std_logic_vector(10 downto 0);
signal DIVCTR : std_logic_vector(log2_oversampling-1 downto 0);
signal DIVCTREN : std_logic;
signal BYTECTR : std_logic_vector(2 downto 0);
signal BYTECTRINC : std_logic;
signal RXDATA : std_logic;
signal NEXT_WRDATA : std_logic_vector(7 downto 0);
signal we_red : std_logic_vector(1 downto 0);
signal we_green : std_logic_vector(1 downto 0);
signal we_blue : std_logic_vector(1 downto 0);
signal rdaddr_ext : std_logic_vector(9 downto 0);
signal rd_msb : std_logic;
signal rgb_ctr : std_logic_vector(1 downto 0);
signal wr_addr : std_logic_vector(10 downto 0);
signal wr_addr_short : std_logic_vector(9 downto 0);
signal wr_inc : std_logic;
begin
i_gen : for i in 1 downto 0 generate
-- RAM for red color
ram_red : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_red(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+7 downto i*24));
-- RAM for green color
ram_green : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_green(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+15 downto i*24+8));
-- RAM for blue color
ram_blue : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_blue(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+23 downto i*24+16));
end generate i_gen;
-- Register for FSM
sync_proc : process (CLKOSX, RST)
begin
if RST = '1' then
STATE <= st0_idle;
WRDATA <= (others => '0');
RXDATA <= '1';
elsif rising_edge(CLKOSX) then
STATE <= NEXT_STATE;
WRDATA <= NEXT_WRDATA;
RXDATA <= RXD;
end if;
end process sync_proc;
-- Finite state machine (FSM)
fsm_proc : process (STATE, RXDATA, WRDATA, DIVCTR, BYTECTR)
begin
-- Default values
NEXT_STATE <= STATE; --default is to stay in current state
NEXT_WRDATA <= WRDATA;
DIVCTREN <= '1';
BYTECTRINC <= '0';
WREN <= '0';
WRRST <= '0';
case STATE is
when st0_idle =>
if (RXDATA = '0') then
NEXT_STATE <= st1_read_start_bit;
else
DIVCTREN <= '0';
end if;
when st1_read_start_bit =>
if DIVCTR(log2_oversampling-1) = '1' then
NEXT_STATE <= st2_read_data_bits;
BYTECTRINC <= '1';
DIVCTREN <= '0';
end if;
when st2_read_data_bits =>
if (DIVCTR = 2**log2_oversampling-1) then
NEXT_WRDATA(conv_integer(BYTECTR)) <= RXDATA;
if (BYTECTR = "111") then
NEXT_STATE <= st3_read_stop_bit;
else
BYTECTRINC <= '1';
end if;
end if;
when st3_read_stop_bit =>
if (DIVCTR = 2**log2_oversampling-1) then
NEXT_STATE <= st0_idle;
if WRDATA = 1 then
WREN <= '0';
WRRST <= RXDATA;
else
WREN <= RXDATA;
WRRST <= '0';
end if;
end if;
end case;
end process fsm_proc;
-- Clock divide counter
div_proc : process (CLKOSX)
begin
if rising_edge(CLKOSX) then
if DIVCTREN = '1' then
DIVCTR <= DIVCTR + 1;
else
DIVCTR <= (others => '0');
end if;
end if;
end process div_proc;
-- Byte counter
byte_proc : process (CLKOSX, RST)
begin
if RST = '1' then
BYTECTR <= (others => '1');
elsif rising_edge(CLKOSX) then
if BYTECTRINC = '1' then
BYTECTR <= BYTECTR + 1;
end if;
end if;
end process byte_proc;
-- RGB color select
we_red(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "00")) else '0';
we_green(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "01")) else '0';
we_blue(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "10")) else '0';
we_red(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "00")) else '0';
we_green(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "01")) else '0';
we_blue(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "10")) else '0';
-- RAM control signals
rgb_proc : process (CLKOSX, RST)
begin
if RST = '1' then
rgb_ctr <= (others => '0');
wr_addr <= (others => '0');
elsif rising_edge(CLKOSX) then
if WRRST = '1' then
rgb_ctr <= (others => '0');
wr_addr(9 downto 0) <= (others => '0');
elsif WREN = '1' then
if rgb_ctr = "10" then
rgb_ctr <= (others => '0');
wr_addr <= wr_addr + 1;
else
rgb_ctr <= rgb_ctr + 1;
end if;
end if;
end if;
end process rgb_proc;
-- Clock domain crossing
rd_proc : process (RDCLK)
begin
if rising_edge(RDCLK) then
rd_msb <= not wr_addr(10);
FRAMESEL <= rd_msb;
end if;
end process rd_proc;
rdaddr_ext <= rd_msb & RDADDR;
wr_addr_short <= wr_addr(10) & wr_addr(8 downto 0);
end rtl;
|
------------------------------------------------------------------------------
--
-- Design : Branch Predicton Buffer
-- Project : Tomasulo Processor
-- Entity : bpb
-- Author : kapil
-- Company : University of Southern California
-- Last Updated : June 24, 2010
-- Last Updated by : Waleed Dweik
-- Modification : 1. Modify the branch prediction to use the most well-known state machine of the 2-bit saturating counter
-- 2. Update old comments
-------------------------------------------------------------------------------
--
-- Description : 2 - bit wide / 8 deep
-- each 2 bit locn is a state machine
-- 2 bit saturating counter
-- 00 strongly nottaken
-- 01 mildly nottaken
-- 10 mildly taken
-- 11 strongly taken
--
-------------------------------------------------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------------------------------------
entity bpb is
port (
Clk : in std_logic;
Resetb : in std_logic;
---- Interaction with Cdb -------------------
Dis_CdbUpdBranch : in std_logic; -- indicates that a branch appears on Cdb(wen to bpb)
Dis_CdbUpdBranchAddr : in std_logic_vector(2 downto 0);-- indiactes the last 3 bit addr of the branch on the Cdb
Dis_CdbBranchOutcome : in std_logic; -- indiacates the outocome of the branch to the bpb: 0 means nottaken and 1 means taken
---- Interaction with dispatch --------------
Bpb_BranchPrediction : out std_logic; --This bit tells the dispatch what the prediction actually based on bpb state-mc
Dis_BpbBranchPCBits : in std_logic_vector(2 downto 0) ;--indiaces the 3 least sig bits of the current instr being dispatched
Dis_BpbBranch : in std_logic -- indiactes that there is a branch instr in the dispatch (ren to the bpb)
);
end bpb;
architecture behv of bpb is
subtype sat_counters is std_logic_vector(1 downto 0);
type bpb_array is array (0 to 7) of sat_counters ;
signal bpb_array_r: bpb_array ; -- An array of 8 2-bit saturating counters represents 8 location bpb.
signal Bpb_read_status,Bpb_write_status : std_logic_vector(1 downto 0);
begin
---------------------------------------------------------------------------
-- Task1: Complete the following 2 concurrent statements for Bpb read and write status:
-- Hint: You may want to use CONV_INTEGER function to convert from std_logic_vector to an integer
-- Bpb_read_status represets the 2-bit counter value in the Bpb entry addressed by the branch instruction in dispatch.
-- Bpb_read_status tells whether branch should predicted Taken (11,10) or not Taken (00,01)
Bpb_read_status <= --
-- Bpb_write_status represents the 2-bit counter value in the Bpb entry addressed by the branch instruction on the Cdb.
-- Bpb_write_status is used along with the actual outcome of the branch on Cdb to update the corresponding Bpb entry.
Bpb_write_status <= --
---------------------------------------------------------------------------
-- Update Process
-- This prcoess is used to update the Bpb entry indexed by the PC[4:2] of the branch instruction which appears on Cdb.
-- The update process is based on the State machine for a 2-bit saturating counter which is given in the slide set.
bpb_write: process (Clk,Resetb)
variable write_data_bpb: std_logic_vector(1 downto 0);
variable bpb_waddr_mask ,bpb_index_addr,raw_bpb_addr: std_logic_vector(7 downto 0);
begin
if (Resetb = '0') then
-------------------------------Initialize register file contents(!! weakly taken, weakly not taken alternatvely!!) here----------------------------------
bpb_array_r <= (
"01", -- $0
"10", -- $1
"01", -- $2
"10", -- $3
"01", -- $4
"10", -- $5
"01", -- $6
"10" -- $7
);
elsif(Clk'event and Clk='1') then
if (Dis_CdbUpdBranch = '1')then
bpb_waddr_mask := X"FF";
else
bpb_waddr_mask := X"00";
end if ;
case Dis_CdbUpdBranchAddr is
when "000" => raw_bpb_addr := ("00000001");
when "001" => raw_bpb_addr := ("00000010");
when "010" => raw_bpb_addr := ("00000100");
when "011" => raw_bpb_addr := ("00001000");
when "100" => raw_bpb_addr := ("00010000");
when "101" => raw_bpb_addr := ("00100000");
when "110" => raw_bpb_addr := ("01000000");
when others => raw_bpb_addr := ("10000000");
end case ;
bpb_index_addr := raw_bpb_addr and bpb_waddr_mask ;
---------------------------------------------------------------------------
-- Task2: Add the Code inside the for loop to modify Bpb entries:
-- Hint: According to the current counter value of the corresponding entry and the actual outcome of the branch on Cdb you can
-- decide what is the new prediction value should be based on the state machine given in the slides.
---------------------------------------------------------------------------
for i in 0 to 7 loop
-- Add your Code here
end loop;
end if;
end process bpb_write;
-- Prediction Process
-- This prcoess generates Bpb_BranchPrediction signal which indicates the prediction for branch instruction
-- The signal is always set to '0' except when there is a branch instruction in dispatch and the prediction is either Strongly Taken or Taken.
bpb_predict : process(Bpb_read_status ,Dis_BpbBranch)
begin
Bpb_BranchPrediction<= '0';
if (Bpb_read_status(1) = '0' ) then
Bpb_BranchPrediction<= '0';
else
Bpb_BranchPrediction<= '1' and Dis_BpbBranch;
end if ;
end process;
end behv;
|
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
epcs_flash_dclk : out std_logic; -- dclk
epcs_flash_sce : out std_logic; -- sce
epcs_flash_sdo : out std_logic; -- sdo
epcs_flash_data0 : in std_logic := 'X'; -- data0
ip_pwm_dir : out std_logic_vector(1 downto 0); -- dir
ip_pwm_out : out std_logic_vector(1 downto 0); -- out
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_rxd : in std_logic := 'X'; -- rxd
uart_0_txd : out std_logic -- txd
);
end component niosii;
u0 : component niosii
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
epcs_flash_dclk => CONNECTED_TO_epcs_flash_dclk, -- epcs_flash.dclk
epcs_flash_sce => CONNECTED_TO_epcs_flash_sce, -- .sce
epcs_flash_sdo => CONNECTED_TO_epcs_flash_sdo, -- .sdo
epcs_flash_data0 => CONNECTED_TO_epcs_flash_data0, -- .data0
ip_pwm_dir => CONNECTED_TO_ip_pwm_dir, -- ip_pwm.dir
ip_pwm_out => CONNECTED_TO_ip_pwm_out, -- .out
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export, -- pio_0_external_connection.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
uart_0_rxd => CONNECTED_TO_uart_0_rxd, -- uart_0.rxd
uart_0_txd => CONNECTED_TO_uart_0_txd -- .txd
);
|
library ieee;
use ieee.std_logic_1164.all;
use work.rec10_pkg.all;
entity rec10 is
port (inp : std_logic;
o : out myrec);
end rec10;
architecture behav of rec10 is
begin
o.b (1) <= not inp;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- PL330 DMA interface
dclk : in std_logic;
dresetn : in std_logic;
davalid : in std_logic;
daready : out std_logic;
datype : in std_logic_vector(1 downto 0);
drvalid : out std_logic;
drready : in std_logic;
drtype : out std_logic_vector(1 downto 0);
drlast : out std_logic;
DBG : out std_logic_vector(7 downto 0)
);
end;
architecture imp of pl330_dma_fifo is
signal request_data : Boolean;
type state_type is (IDLE, REQUEST, WAITING, FLUSH);
signal state : state_type;
signal i_in_ack : std_logic;
signal i_out_stb : std_logic;
begin
in_ack <= i_in_ack;
out_stb <= i_out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => i_in_ack,
in_data => in_data,
out_stb => i_out_stb,
out_ack => out_ack,
out_data => out_data
);
request_data <= i_in_ack = '1' when FIFO_DIRECTION = 0 else i_out_stb = '1';
drlast <= '0';
daready <= '1';
drvalid <= '1' when (state = REQUEST) or (state = FLUSH) else '0';
drtype <= "00" when state = REQUEST else "10";
DBG(0) <= davalid;
DBG(2 downto 1) <= datype;
DBG(3) <= '1' when request_data else '0';
process (state)
begin
case state is
when IDLE => DBG(5 downto 4) <= "00";
when REQUEST => DBG(5 downto 4) <= "01";
when WAITING => DBG(5 downto 4) <= "10";
when FLUSH => DBG(5 downto 4) <= "11";
end case;
end process;
pl330_req_fsm: process (dclk) is
begin
if rising_edge(dclk) then
if dresetn = '0' then
state <= IDLE;
else
-- The controller may send a FLUSH request at any time and it won't
-- respond to any of our requests until we've ack the FLUSH request.
-- The FLUSH request is also supposed to reset our state machine, so
-- go back to idle after having acked the FLUSH.
if davalid = '1' and datype = "10" then
state <= FLUSH;
else
case state is
-- Nothing to do, wait for the fifo to run empty
when IDLE =>
if request_data and enable then
state <= REQUEST;
end if;
-- Send out a request to the PL330
when REQUEST =>
if drready = '1' then
state <= WAITING;
end if;
-- Wait for a ACK from the PL330 that it did transfer the data
when WAITING =>
if fifo_reset = '1' then
state <= IDLE;
elsif davalid = '1' then
if datype = "00" then
state <= IDLE;
end if;
end if;
-- Send out an ACK for the flush
when FLUSH =>
if drready = '1' then
state <= IDLE;
end if;
end case;
end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- PL330 DMA interface
dclk : in std_logic;
dresetn : in std_logic;
davalid : in std_logic;
daready : out std_logic;
datype : in std_logic_vector(1 downto 0);
drvalid : out std_logic;
drready : in std_logic;
drtype : out std_logic_vector(1 downto 0);
drlast : out std_logic;
DBG : out std_logic_vector(7 downto 0)
);
end;
architecture imp of pl330_dma_fifo is
signal request_data : Boolean;
type state_type is (IDLE, REQUEST, WAITING, FLUSH);
signal state : state_type;
signal i_in_ack : std_logic;
signal i_out_stb : std_logic;
begin
in_ack <= i_in_ack;
out_stb <= i_out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => i_in_ack,
in_data => in_data,
out_stb => i_out_stb,
out_ack => out_ack,
out_data => out_data
);
request_data <= i_in_ack = '1' when FIFO_DIRECTION = 0 else i_out_stb = '1';
drlast <= '0';
daready <= '1';
drvalid <= '1' when (state = REQUEST) or (state = FLUSH) else '0';
drtype <= "00" when state = REQUEST else "10";
DBG(0) <= davalid;
DBG(2 downto 1) <= datype;
DBG(3) <= '1' when request_data else '0';
process (state)
begin
case state is
when IDLE => DBG(5 downto 4) <= "00";
when REQUEST => DBG(5 downto 4) <= "01";
when WAITING => DBG(5 downto 4) <= "10";
when FLUSH => DBG(5 downto 4) <= "11";
end case;
end process;
pl330_req_fsm: process (dclk) is
begin
if rising_edge(dclk) then
if dresetn = '0' then
state <= IDLE;
else
-- The controller may send a FLUSH request at any time and it won't
-- respond to any of our requests until we've ack the FLUSH request.
-- The FLUSH request is also supposed to reset our state machine, so
-- go back to idle after having acked the FLUSH.
if davalid = '1' and datype = "10" then
state <= FLUSH;
else
case state is
-- Nothing to do, wait for the fifo to run empty
when IDLE =>
if request_data and enable then
state <= REQUEST;
end if;
-- Send out a request to the PL330
when REQUEST =>
if drready = '1' then
state <= WAITING;
end if;
-- Wait for a ACK from the PL330 that it did transfer the data
when WAITING =>
if fifo_reset = '1' then
state <= IDLE;
elsif davalid = '1' then
if datype = "00" then
state <= IDLE;
end if;
end if;
-- Send out an ACK for the flush
when FLUSH =>
if drready = '1' then
state <= IDLE;
end if;
end case;
end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- PL330 DMA interface
dclk : in std_logic;
dresetn : in std_logic;
davalid : in std_logic;
daready : out std_logic;
datype : in std_logic_vector(1 downto 0);
drvalid : out std_logic;
drready : in std_logic;
drtype : out std_logic_vector(1 downto 0);
drlast : out std_logic;
DBG : out std_logic_vector(7 downto 0)
);
end;
architecture imp of pl330_dma_fifo is
signal request_data : Boolean;
type state_type is (IDLE, REQUEST, WAITING, FLUSH);
signal state : state_type;
signal i_in_ack : std_logic;
signal i_out_stb : std_logic;
begin
in_ack <= i_in_ack;
out_stb <= i_out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => i_in_ack,
in_data => in_data,
out_stb => i_out_stb,
out_ack => out_ack,
out_data => out_data
);
request_data <= i_in_ack = '1' when FIFO_DIRECTION = 0 else i_out_stb = '1';
drlast <= '0';
daready <= '1';
drvalid <= '1' when (state = REQUEST) or (state = FLUSH) else '0';
drtype <= "00" when state = REQUEST else "10";
DBG(0) <= davalid;
DBG(2 downto 1) <= datype;
DBG(3) <= '1' when request_data else '0';
process (state)
begin
case state is
when IDLE => DBG(5 downto 4) <= "00";
when REQUEST => DBG(5 downto 4) <= "01";
when WAITING => DBG(5 downto 4) <= "10";
when FLUSH => DBG(5 downto 4) <= "11";
end case;
end process;
pl330_req_fsm: process (dclk) is
begin
if rising_edge(dclk) then
if dresetn = '0' then
state <= IDLE;
else
-- The controller may send a FLUSH request at any time and it won't
-- respond to any of our requests until we've ack the FLUSH request.
-- The FLUSH request is also supposed to reset our state machine, so
-- go back to idle after having acked the FLUSH.
if davalid = '1' and datype = "10" then
state <= FLUSH;
else
case state is
-- Nothing to do, wait for the fifo to run empty
when IDLE =>
if request_data and enable then
state <= REQUEST;
end if;
-- Send out a request to the PL330
when REQUEST =>
if drready = '1' then
state <= WAITING;
end if;
-- Wait for a ACK from the PL330 that it did transfer the data
when WAITING =>
if fifo_reset = '1' then
state <= IDLE;
elsif davalid = '1' then
if datype = "00" then
state <= IDLE;
end if;
end if;
-- Send out an ACK for the flush
when FLUSH =>
if drready = '1' then
state <= IDLE;
end if;
end case;
end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- PL330 DMA interface
dclk : in std_logic;
dresetn : in std_logic;
davalid : in std_logic;
daready : out std_logic;
datype : in std_logic_vector(1 downto 0);
drvalid : out std_logic;
drready : in std_logic;
drtype : out std_logic_vector(1 downto 0);
drlast : out std_logic;
DBG : out std_logic_vector(7 downto 0)
);
end;
architecture imp of pl330_dma_fifo is
signal request_data : Boolean;
type state_type is (IDLE, REQUEST, WAITING, FLUSH);
signal state : state_type;
signal i_in_ack : std_logic;
signal i_out_stb : std_logic;
begin
in_ack <= i_in_ack;
out_stb <= i_out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => i_in_ack,
in_data => in_data,
out_stb => i_out_stb,
out_ack => out_ack,
out_data => out_data
);
request_data <= i_in_ack = '1' when FIFO_DIRECTION = 0 else i_out_stb = '1';
drlast <= '0';
daready <= '1';
drvalid <= '1' when (state = REQUEST) or (state = FLUSH) else '0';
drtype <= "00" when state = REQUEST else "10";
DBG(0) <= davalid;
DBG(2 downto 1) <= datype;
DBG(3) <= '1' when request_data else '0';
process (state)
begin
case state is
when IDLE => DBG(5 downto 4) <= "00";
when REQUEST => DBG(5 downto 4) <= "01";
when WAITING => DBG(5 downto 4) <= "10";
when FLUSH => DBG(5 downto 4) <= "11";
end case;
end process;
pl330_req_fsm: process (dclk) is
begin
if rising_edge(dclk) then
if dresetn = '0' then
state <= IDLE;
else
-- The controller may send a FLUSH request at any time and it won't
-- respond to any of our requests until we've ack the FLUSH request.
-- The FLUSH request is also supposed to reset our state machine, so
-- go back to idle after having acked the FLUSH.
if davalid = '1' and datype = "10" then
state <= FLUSH;
else
case state is
-- Nothing to do, wait for the fifo to run empty
when IDLE =>
if request_data and enable then
state <= REQUEST;
end if;
-- Send out a request to the PL330
when REQUEST =>
if drready = '1' then
state <= WAITING;
end if;
-- Wait for a ACK from the PL330 that it did transfer the data
when WAITING =>
if fifo_reset = '1' then
state <= IDLE;
elsif davalid = '1' then
if datype = "00" then
state <= IDLE;
end if;
end if;
-- Send out an ACK for the flush
when FLUSH =>
if drready = '1' then
state <= IDLE;
end if;
end case;
end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- PL330 DMA interface
dclk : in std_logic;
dresetn : in std_logic;
davalid : in std_logic;
daready : out std_logic;
datype : in std_logic_vector(1 downto 0);
drvalid : out std_logic;
drready : in std_logic;
drtype : out std_logic_vector(1 downto 0);
drlast : out std_logic;
DBG : out std_logic_vector(7 downto 0)
);
end;
architecture imp of pl330_dma_fifo is
signal request_data : Boolean;
type state_type is (IDLE, REQUEST, WAITING, FLUSH);
signal state : state_type;
signal i_in_ack : std_logic;
signal i_out_stb : std_logic;
begin
in_ack <= i_in_ack;
out_stb <= i_out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => i_in_ack,
in_data => in_data,
out_stb => i_out_stb,
out_ack => out_ack,
out_data => out_data
);
request_data <= i_in_ack = '1' when FIFO_DIRECTION = 0 else i_out_stb = '1';
drlast <= '0';
daready <= '1';
drvalid <= '1' when (state = REQUEST) or (state = FLUSH) else '0';
drtype <= "00" when state = REQUEST else "10";
DBG(0) <= davalid;
DBG(2 downto 1) <= datype;
DBG(3) <= '1' when request_data else '0';
process (state)
begin
case state is
when IDLE => DBG(5 downto 4) <= "00";
when REQUEST => DBG(5 downto 4) <= "01";
when WAITING => DBG(5 downto 4) <= "10";
when FLUSH => DBG(5 downto 4) <= "11";
end case;
end process;
pl330_req_fsm: process (dclk) is
begin
if rising_edge(dclk) then
if dresetn = '0' then
state <= IDLE;
else
-- The controller may send a FLUSH request at any time and it won't
-- respond to any of our requests until we've ack the FLUSH request.
-- The FLUSH request is also supposed to reset our state machine, so
-- go back to idle after having acked the FLUSH.
if davalid = '1' and datype = "10" then
state <= FLUSH;
else
case state is
-- Nothing to do, wait for the fifo to run empty
when IDLE =>
if request_data and enable then
state <= REQUEST;
end if;
-- Send out a request to the PL330
when REQUEST =>
if drready = '1' then
state <= WAITING;
end if;
-- Wait for a ACK from the PL330 that it did transfer the data
when WAITING =>
if fifo_reset = '1' then
state <= IDLE;
elsif davalid = '1' then
if datype = "00" then
state <= IDLE;
end if;
end if;
-- Send out an ACK for the flush
when FLUSH =>
if drready = '1' then
state <= IDLE;
end if;
end case;
end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- PL330 DMA interface
dclk : in std_logic;
dresetn : in std_logic;
davalid : in std_logic;
daready : out std_logic;
datype : in std_logic_vector(1 downto 0);
drvalid : out std_logic;
drready : in std_logic;
drtype : out std_logic_vector(1 downto 0);
drlast : out std_logic;
DBG : out std_logic_vector(7 downto 0)
);
end;
architecture imp of pl330_dma_fifo is
signal request_data : Boolean;
type state_type is (IDLE, REQUEST, WAITING, FLUSH);
signal state : state_type;
signal i_in_ack : std_logic;
signal i_out_stb : std_logic;
begin
in_ack <= i_in_ack;
out_stb <= i_out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => i_in_ack,
in_data => in_data,
out_stb => i_out_stb,
out_ack => out_ack,
out_data => out_data
);
request_data <= i_in_ack = '1' when FIFO_DIRECTION = 0 else i_out_stb = '1';
drlast <= '0';
daready <= '1';
drvalid <= '1' when (state = REQUEST) or (state = FLUSH) else '0';
drtype <= "00" when state = REQUEST else "10";
DBG(0) <= davalid;
DBG(2 downto 1) <= datype;
DBG(3) <= '1' when request_data else '0';
process (state)
begin
case state is
when IDLE => DBG(5 downto 4) <= "00";
when REQUEST => DBG(5 downto 4) <= "01";
when WAITING => DBG(5 downto 4) <= "10";
when FLUSH => DBG(5 downto 4) <= "11";
end case;
end process;
pl330_req_fsm: process (dclk) is
begin
if rising_edge(dclk) then
if dresetn = '0' then
state <= IDLE;
else
-- The controller may send a FLUSH request at any time and it won't
-- respond to any of our requests until we've ack the FLUSH request.
-- The FLUSH request is also supposed to reset our state machine, so
-- go back to idle after having acked the FLUSH.
if davalid = '1' and datype = "10" then
state <= FLUSH;
else
case state is
-- Nothing to do, wait for the fifo to run empty
when IDLE =>
if request_data and enable then
state <= REQUEST;
end if;
-- Send out a request to the PL330
when REQUEST =>
if drready = '1' then
state <= WAITING;
end if;
-- Wait for a ACK from the PL330 that it did transfer the data
when WAITING =>
if fifo_reset = '1' then
state <= IDLE;
elsif davalid = '1' then
if datype = "00" then
state <= IDLE;
end if;
end if;
-- Send out an ACK for the flush
when FLUSH =>
if drready = '1' then
state <= IDLE;
end if;
end case;
end if;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- PL330 DMA interface
dclk : in std_logic;
dresetn : in std_logic;
davalid : in std_logic;
daready : out std_logic;
datype : in std_logic_vector(1 downto 0);
drvalid : out std_logic;
drready : in std_logic;
drtype : out std_logic_vector(1 downto 0);
drlast : out std_logic;
DBG : out std_logic_vector(7 downto 0)
);
end;
architecture imp of pl330_dma_fifo is
signal request_data : Boolean;
type state_type is (IDLE, REQUEST, WAITING, FLUSH);
signal state : state_type;
signal i_in_ack : std_logic;
signal i_out_stb : std_logic;
begin
in_ack <= i_in_ack;
out_stb <= i_out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => i_in_ack,
in_data => in_data,
out_stb => i_out_stb,
out_ack => out_ack,
out_data => out_data
);
request_data <= i_in_ack = '1' when FIFO_DIRECTION = 0 else i_out_stb = '1';
drlast <= '0';
daready <= '1';
drvalid <= '1' when (state = REQUEST) or (state = FLUSH) else '0';
drtype <= "00" when state = REQUEST else "10";
DBG(0) <= davalid;
DBG(2 downto 1) <= datype;
DBG(3) <= '1' when request_data else '0';
process (state)
begin
case state is
when IDLE => DBG(5 downto 4) <= "00";
when REQUEST => DBG(5 downto 4) <= "01";
when WAITING => DBG(5 downto 4) <= "10";
when FLUSH => DBG(5 downto 4) <= "11";
end case;
end process;
pl330_req_fsm: process (dclk) is
begin
if rising_edge(dclk) then
if dresetn = '0' then
state <= IDLE;
else
-- The controller may send a FLUSH request at any time and it won't
-- respond to any of our requests until we've ack the FLUSH request.
-- The FLUSH request is also supposed to reset our state machine, so
-- go back to idle after having acked the FLUSH.
if davalid = '1' and datype = "10" then
state <= FLUSH;
else
case state is
-- Nothing to do, wait for the fifo to run empty
when IDLE =>
if request_data and enable then
state <= REQUEST;
end if;
-- Send out a request to the PL330
when REQUEST =>
if drready = '1' then
state <= WAITING;
end if;
-- Wait for a ACK from the PL330 that it did transfer the data
when WAITING =>
if fifo_reset = '1' then
state <= IDLE;
elsif davalid = '1' then
if datype = "00" then
state <= IDLE;
end if;
end if;
-- Send out an ACK for the flush
when FLUSH =>
if drready = '1' then
state <= IDLE;
end if;
end case;
end if;
end if;
end if;
end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity ddr3if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
burstlen: integer := 8
);
port (
pll_ref_clk: in std_ulogic;
global_reset_n: in std_ulogic;
mem_a: out std_logic_vector(14 downto 0);
mem_ba: out std_logic_vector(2 downto 0);
mem_ck: out std_ulogic;
mem_ck_n: out std_ulogic;
mem_cke: out std_ulogic;
mem_reset_n: out std_ulogic;
mem_cs_n: out std_ulogic;
mem_dm: out std_logic_vector(3 downto 0);
mem_ras_n: out std_ulogic;
mem_cas_n: out std_ulogic;
mem_we_n: out std_ulogic;
mem_dq: inout std_logic_vector(31 downto 0);
mem_dqs: inout std_logic_vector(3 downto 0);
mem_dqs_n: inout std_logic_vector(3 downto 0);
mem_odt: out std_ulogic;
oct_rzqin: in std_logic;
ahb_clk: in std_ulogic;
ahb_rst: in std_ulogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type
);
end;
architecture rtl of ddr3if is
component ddr3controller_0002 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(14 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_reset_n : out std_logic; -- mem_reset_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(127 downto 0); -- readdata
avl_wdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_locked : out std_logic; -- pll_locked
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
-- pll_dr_clk : out std_logic; -- pll_dr_clk
-- pll_dr_clk_pre_phy_clk : out std_logic; -- pll_dr_clk_pre_phy_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component ddr3controller_0002;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal rasn_arr, casn_arr, wen_arr, odt_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
begin
vcc <= '1';
mem_ck <= ck_p_arr(0);
mem_ck_n <= ck_n_arr(0);
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
mem_ras_n <= rasn_arr(0);
mem_cas_n <= casn_arr(0);
mem_we_n <= wen_arr(0);
mem_odt <= odt_arr(0);
ctrl0: ddr3controller_0002
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_a => mem_a,
mem_ba => mem_ba,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_ras_n => rasn_arr,
mem_cas_n => casn_arr,
mem_we_n => wen_arr,
mem_reset_n => mem_reset_n,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
mem_odt => odt_arr,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(25 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => avlso.rdata(127 downto 0),
avl_wdata => avlsi.wdata(127 downto 0),
avl_be => avlsi.be(15 downto 0),
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size(3 downto 0),
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rzqin => oct_rzqin,
pll_mem_clk => open,
pll_write_clk => open,
pll_locked => open,
pll_write_clk_pre_phy_clk => open,
pll_addr_cmd_clk => open,
pll_avl_clk => open,
pll_config_clk => open,
-- pll_dr_clk => open,
-- pll_dr_clk_pre_phy_clk => open,
pll_mem_phy_clk => open,
afi_phy_clk => open,
pll_avl_phy_clk => open
);
avlso.rdata(avlso.rdata'high downto 128) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
avldbits => 128,
avlabits => 26
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3
-- C_XDEVICEFAMILY : spartan3
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 10
-- C_READ_WIDTH_A : 10
-- C_WRITE_DEPTH_A : 43000
-- C_READ_DEPTH_A : 43000
-- C_ADDRA_WIDTH : 16
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 10
-- C_READ_WIDTH_B : 10
-- C_WRITE_DEPTH_B : 43000
-- C_READ_DEPTH_B : 43000
-- C_ADDRB_WIDTH : 16
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use ieee.std_logic_misc.all;
package RWCACHE_PKG is
constant RWCACHE_WAYS : natural := 2;
constant RWCACHE_NUMSETS : natural := 4; --Depth of ICache
constant RWCACHE_WORDS : natural := 2;
constant DATA_SIZE : natural := 32;
constant RWCACHE_SETINDEXSIZE : natural := 2;
constant RWCACHE_NUMLINES : natural := RWCACHE_WAYS;
constant RWCACHE_INDEXSIZE : natural := 1;
constant RWCACHE_TAGSIZE : natural := DATA_SIZE - RWCACHE_INDEXSIZE - RWCACHE_SETINDEXSIZE;
constant RWCACHE_TAGOFFSET : natural := DATA_SIZE - RWCACHE_TAGSIZE;
constant RWCACHE_SETOFFSET : natural := RWCACHE_TAGOFFSET - RWCACHE_SETINDEXSIZE;
constant RWCACHE_INDEXOFFSET : natural := RWCACHE_INDEXSIZE;
constant RWCACHE_COUNTERSIZE : natural := 8;
subtype RWCACHE_LINES is natural range 0 to RWCACHE_NUMLINES - 1;
subtype RWCACHE_SETS is natural range 0 to 2**RWCACHE_SETINDEXSIZE - 1;
subtype RWCACHE_INDEX is natural range 0 to 2**RWCACHE_INDEXSIZE - 1;
type DATA_WORDS is array (RWCACHE_INDEX) of std_logic_vector(DATA_SIZE - 1 downto 0);
type RWCACHE_RECORD is
record
tag : std_logic_vector(RWCACHE_TAGSIZE-1 downto 0);
words : DATA_WORDS;
counter : integer range 0 to 2**RWCACHE_COUNTERSIZE;
valid : std_logic;
end record;
type RWCACHE_LINE is array (RWCACHE_LINES) of RWCACHE_RECORD;
type RWCACHE_TYPE is array (RWCACHE_SETS) of RWCACHE_LINE;
subtype state_type is std_logic_vector(2 downto 0);
constant STATE_FLUSH_MEM : state_type := "000";
constant STATE_MISS : state_type := "001";
constant STATE_COMPARE_TAGS : state_type := "010";
constant STATE_WRITE_MISS : state_type := "011";
constant STATE_IDLE : state_type := "100";
function COMPARE_TAGS(
x : std_logic_vector(RWCACHE_TAGSIZE - 1 downto 0 );
y : std_logic_vector(RWCACHE_TAGSIZE - 1 downto 0 )
) return std_logic;
function GET_SET(
x : std_logic_vector(DATA_SIZE - 1 downto 0)
) return integer;
function GET_REPLACEMENT_LINE(
pc : std_logic_vector(DATA_SIZE - 1 downto 0);
cache: RWCACHE_TYPE
) return natural;
end RWCACHE_PKG;
package body RWCACHE_PKG is
function COMPARE_TAGS(
x : std_logic_vector(RWCACHE_TAGSIZE-1 downto 0);
y : std_logic_vector(RWCACHE_TAGSIZE-1 downto 0)
) return std_logic is
begin
return and_reduce(x xnor y);
end COMPARE_TAGS;
function GET_SET (
x : std_logic_vector(DATA_SIZE - 1 downto 0)
) return integer is
variable ret : integer :=0;
variable y : std_logic_vector(RWCACHE_TAGOFFSET-1 downto RWCACHE_SETOFFSET);
begin
y := x(RWCACHE_TAGOFFSET-1 downto RWCACHE_SETOFFSET);
ret := conv_integer(unsigned (y));
return ret;
end GET_SET;
function GET_REPLACEMENT_LINE (
pc : std_logic_vector(DATA_SIZE - 1 downto 0);
cache: RWCACHE_TYPE
) return natural is
variable count : natural range 0 to 2**RWCACHE_COUNTERSIZE;
variable min_found : std_logic;
variable i : natural := 0;
variable to_evict : natural range 0 to 2**RWCACHE_COUNTERSIZE;
variable countValid : std_logic;
begin
-- count := cache( GET_SET(pc) )(i).counter;
to_evict := i;
countValid := '0';
count:=0;
-- Iterate
-- while i < (RWCACHE_NUMLINES - 2) loop
-- Check counter value
-- if(cache( GET_SET(pc) )(i+1).valid = '0') then
-- to_evict := i + 1;
-- exit;
-- elsif(cache( GET_SET(pc) )(i+1).counter < count) then
-- -- New least frequently used -> save its index and counter value
-- count := cache( GET_SET(pc) )(i+1).counter;
-- to_evict := i + 1;
-- end if;
-- i := i + 1 ;
-- end loop;
-- Iterate
for i in 0 to RWCACHE_NUMLINES - 1 loop
-- If not valid -> USE IT
if(cache( GET_SET(pc) )(i).valid = '0') then
to_evict := i;
exit;
-- Line is busy, but counter not initialized
elsif(countValid = '0') then
count := cache(GET_SET(pc))(i).counter;
countValid := '1';
to_evict := i;
-- Line is busy, and counter initialized: check if lower
elsif(cache( GET_SET(pc) )(i).counter < count) then
-- New least frequently used -> save its index and counter value
count := cache( GET_SET(pc) )(i).counter;
to_evict := i;
end if;
end loop;
return to_evict;
end GET_REPLACEMENT_LINE;
end package body;
|
------------------------------------------------------------------------------
---- ----
---- Single Port RAM that maps to a Xilinx/Lattice BRAM ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- This is a program memory for the AVR. It maps to a Xilinx/Lattice ----
---- BRAM. ----
---- This version can be modified by the CPU (i. e. SPM instruction) ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: SinglePortPM(Xilinx) (Entity and architecture) ----
---- File name: pm_s_rw.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- iCE40 (iCE40HX4K) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- iCEcube2.2016.02 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lattuino_1_blPM_2 is
generic(
WORD_SIZE : integer:=16; -- Word Size
FALL_EDGE : std_logic:='0'; -- Ram clock falling edge
ADDR_W : integer:=13); -- Address Width
port(
clk_i : in std_logic;
addr_i : in std_logic_vector(ADDR_W-1 downto 0);
data_o : out std_logic_vector(WORD_SIZE-1 downto 0);
we_i : in std_logic;
data_i : in std_logic_vector(WORD_SIZE-1 downto 0));
end entity lattuino_1_blPM_2;
architecture Xilinx of lattuino_1_blPM_2 is
constant ROM_SIZE : natural:=2**ADDR_W;
type rom_t is array(natural range 0 to ROM_SIZE-1) of std_logic_vector(WORD_SIZE-1 downto 0);
signal addr_r : std_logic_vector(ADDR_W-1 downto 0);
signal rom : rom_t :=
(
696 => x"c00e",
697 => x"c01b",
698 => x"c01a",
699 => x"c019",
700 => x"c018",
701 => x"c017",
702 => x"c016",
703 => x"c015",
704 => x"c014",
705 => x"c013",
706 => x"c012",
707 => x"c011",
708 => x"c010",
709 => x"c00f",
710 => x"c00e",
711 => x"2411",
712 => x"be1f",
713 => x"edcf",
714 => x"bfcd",
715 => x"e020",
716 => x"e6a0",
717 => x"e0b0",
718 => x"c001",
719 => x"921d",
720 => x"36a5",
721 => x"07b2",
722 => x"f7e1",
723 => x"d036",
724 => x"c125",
725 => x"cfe2",
726 => x"e081",
727 => x"bb8f",
728 => x"e681",
729 => x"ee93",
730 => x"e1a6",
731 => x"e0b0",
732 => x"99f1",
733 => x"c00a",
734 => x"9701",
735 => x"09a1",
736 => x"09b1",
737 => x"9700",
738 => x"05a1",
739 => x"05b1",
740 => x"f7b9",
741 => x"e0e0",
742 => x"e0f0",
743 => x"9509",
744 => x"ba1f",
745 => x"b38e",
746 => x"9508",
747 => x"e091",
748 => x"bb9f",
749 => x"9bf0",
750 => x"cffe",
751 => x"ba1f",
752 => x"bb8e",
753 => x"e080",
754 => x"e090",
755 => x"9508",
756 => x"dfe1",
757 => x"3280",
758 => x"f421",
759 => x"e184",
760 => x"dff2",
761 => x"e180",
762 => x"cff0",
763 => x"9508",
764 => x"93cf",
765 => x"2fc8",
766 => x"dfd7",
767 => x"3280",
768 => x"f439",
769 => x"e184",
770 => x"dfe8",
771 => x"2f8c",
772 => x"dfe6",
773 => x"e180",
774 => x"91cf",
775 => x"cfe3",
776 => x"91cf",
777 => x"9508",
778 => x"9abe",
779 => x"e044",
780 => x"e450",
781 => x"e020",
782 => x"e030",
783 => x"b388",
784 => x"2785",
785 => x"bb88",
786 => x"01c9",
787 => x"9701",
788 => x"f7f1",
789 => x"5041",
790 => x"f7c1",
791 => x"e011",
792 => x"dfbd",
793 => x"3380",
794 => x"f0c9",
795 => x"3381",
796 => x"f499",
797 => x"dfb8",
798 => x"3280",
799 => x"f7c1",
800 => x"e184",
801 => x"dfc9",
802 => x"e481",
803 => x"dfc7",
804 => x"e586",
805 => x"dfc5",
806 => x"e582",
807 => x"dfc3",
808 => x"e280",
809 => x"dfc1",
810 => x"e489",
811 => x"dfbf",
812 => x"e583",
813 => x"dfbd",
814 => x"e580",
815 => x"c0c2",
816 => x"3480",
817 => x"f421",
818 => x"dfa3",
819 => x"dfa2",
820 => x"dfbf",
821 => x"cfe2",
822 => x"3481",
823 => x"f469",
824 => x"df9d",
825 => x"3880",
826 => x"f411",
827 => x"e082",
828 => x"c029",
829 => x"3881",
830 => x"f411",
831 => x"e081",
832 => x"c025",
833 => x"3882",
834 => x"f511",
835 => x"e182",
836 => x"c021",
837 => x"3482",
838 => x"f429",
839 => x"e1c4",
840 => x"df8d",
841 => x"50c1",
842 => x"f7e9",
843 => x"cfe8",
844 => x"3485",
845 => x"f421",
846 => x"df87",
847 => x"df86",
848 => x"df85",
849 => x"cfe0",
850 => x"eb90",
851 => x"0f98",
852 => x"3093",
853 => x"f2f0",
854 => x"3585",
855 => x"f439",
856 => x"df7d",
857 => x"9380",
858 => x"0063",
859 => x"df7a",
860 => x"9380",
861 => x"0064",
862 => x"cfd5",
863 => x"3586",
864 => x"f439",
865 => x"df74",
866 => x"df73",
867 => x"df72",
868 => x"df71",
869 => x"e080",
870 => x"df95",
871 => x"cfb0",
872 => x"3684",
873 => x"f009",
874 => x"c039",
875 => x"df6a",
876 => x"9380",
877 => x"0062",
878 => x"df67",
879 => x"9380",
880 => x"0061",
881 => x"9210",
882 => x"0060",
883 => x"df62",
884 => x"3485",
885 => x"f419",
886 => x"9310",
887 => x"0060",
888 => x"c00a",
889 => x"9180",
890 => x"0063",
891 => x"9190",
892 => x"0064",
893 => x"0f88",
894 => x"1f99",
895 => x"9390",
896 => x"0064",
897 => x"9380",
898 => x"0063",
899 => x"e0c0",
900 => x"e0d0",
901 => x"9180",
902 => x"0061",
903 => x"9190",
904 => x"0062",
905 => x"17c8",
906 => x"07d9",
907 => x"f008",
908 => x"cfa7",
909 => x"df48",
910 => x"2f08",
911 => x"df46",
912 => x"9190",
913 => x"0060",
914 => x"91e0",
915 => x"0063",
916 => x"91f0",
917 => x"0064",
918 => x"1191",
919 => x"c005",
920 => x"921f",
921 => x"2e00",
922 => x"2e18",
923 => x"95e8",
924 => x"901f",
925 => x"9632",
926 => x"93f0",
927 => x"0064",
928 => x"93e0",
929 => x"0063",
930 => x"9622",
931 => x"cfe1",
932 => x"3784",
933 => x"f009",
934 => x"c03e",
935 => x"df2e",
936 => x"9380",
937 => x"0062",
938 => x"df2b",
939 => x"9380",
940 => x"0061",
941 => x"9210",
942 => x"0060",
943 => x"df26",
944 => x"3485",
945 => x"f419",
946 => x"9310",
947 => x"0060",
948 => x"c00a",
949 => x"9180",
950 => x"0063",
951 => x"9190",
952 => x"0064",
953 => x"0f88",
954 => x"1f99",
955 => x"9390",
956 => x"0064",
957 => x"9380",
958 => x"0063",
959 => x"df16",
960 => x"3280",
961 => x"f009",
962 => x"cf55",
963 => x"e184",
964 => x"df26",
965 => x"e0c0",
966 => x"e0d0",
967 => x"9180",
968 => x"0061",
969 => x"9190",
970 => x"0062",
971 => x"17c8",
972 => x"07d9",
973 => x"f528",
974 => x"9180",
975 => x"0060",
976 => x"2388",
977 => x"f011",
978 => x"e080",
979 => x"c005",
980 => x"91e0",
981 => x"0063",
982 => x"91f0",
983 => x"0064",
984 => x"9184",
985 => x"df11",
986 => x"9180",
987 => x"0063",
988 => x"9190",
989 => x"0064",
990 => x"9601",
991 => x"9390",
992 => x"0064",
993 => x"9380",
994 => x"0063",
995 => x"9621",
996 => x"cfe2",
997 => x"3785",
998 => x"f479",
999 => x"deee",
1000 => x"3280",
1001 => x"f009",
1002 => x"cf2d",
1003 => x"e184",
1004 => x"defe",
1005 => x"e18e",
1006 => x"defc",
1007 => x"e981",
1008 => x"defa",
1009 => x"e088",
1010 => x"def8",
1011 => x"e180",
1012 => x"def6",
1013 => x"cf22",
1014 => x"3786",
1015 => x"f009",
1016 => x"cf1f",
1017 => x"cf6b",
1018 => x"94f8",
1019 => x"cfff",
others => x"0000"
);
begin
use_rising_edge:
if FALL_EDGE='0' generate
do_rom:
process (clk_i)
begin
if rising_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_rising_edge;
use_falling_edge:
if FALL_EDGE='1' generate
do_rom:
process (clk_i)
begin
if falling_edge(clk_i)then
addr_r <= addr_i;
if we_i='1' then
rom(to_integer(unsigned(addr_i))) <= data_i;
end if;
end if;
end process do_rom;
end generate use_falling_edge;
data_o <= rom(to_integer(unsigned(addr_r)));
end architecture Xilinx; -- Entity: lattuino_1_blPM_2
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0_12;
USE dds_compiler_v6_0_12.dds_compiler_v6_0_12;
ENTITY design_1_dds_compiler_0_1 IS
PORT (
aclk : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_dds_compiler_0_1;
ARCHITECTURE design_1_dds_compiler_0_1_arch OF design_1_dds_compiler_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dds_compiler_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0_12 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0_12;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_dds_compiler_0_1_arch: ARCHITECTURE IS "dds_compiler_v6_0_12,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dds_compiler_0_1_arch : ARCHITECTURE IS "design_1_dds_compiler_0_1,dds_compiler_v6_0_12,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_dds_compiler_0_1_arch: ARCHITECTURE IS "design_1_dds_compiler_0_1,dds_compiler_v6_0_12,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=29,C_CHANNELS=1,C_HAS_PHASE_OUT=1,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=3,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=8,C_PHASE_ANGL" &
"E_WIDTH=8,C_PHASE_INCREMENT=2,C_PHASE_INCREMENT_VALUE=10100111110001011_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=0,C_S_PHASE_TDATA_WIDTH=1,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=16,C_M_DATA" &
"_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=1,C_M_PHASE_TDATA_WIDTH=32,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TDATA";
BEGIN
U0 : dds_compiler_v6_0_12
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 29,
C_CHANNELS => 1,
C_HAS_PHASE_OUT => 1,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 3,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 2,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 8,
C_PHASE_ANGLE_WIDTH => 8,
C_PHASE_INCREMENT => 2,
C_PHASE_INCREMENT_VALUE => "10100111110001011,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 0,
C_S_PHASE_TDATA_WIDTH => 1,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 16,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 1,
C_M_PHASE_TDATA_WIDTH => 32,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tvalid => m_axis_phase_tvalid,
m_axis_phase_tready => '0',
m_axis_phase_tdata => m_axis_phase_tdata
);
END design_1_dds_compiler_0_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0_12;
USE dds_compiler_v6_0_12.dds_compiler_v6_0_12;
ENTITY design_1_dds_compiler_0_1 IS
PORT (
aclk : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_dds_compiler_0_1;
ARCHITECTURE design_1_dds_compiler_0_1_arch OF design_1_dds_compiler_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dds_compiler_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0_12 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0_12;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_dds_compiler_0_1_arch: ARCHITECTURE IS "dds_compiler_v6_0_12,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dds_compiler_0_1_arch : ARCHITECTURE IS "design_1_dds_compiler_0_1,dds_compiler_v6_0_12,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_dds_compiler_0_1_arch: ARCHITECTURE IS "design_1_dds_compiler_0_1,dds_compiler_v6_0_12,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=29,C_CHANNELS=1,C_HAS_PHASE_OUT=1,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=3,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=8,C_PHASE_ANGL" &
"E_WIDTH=8,C_PHASE_INCREMENT=2,C_PHASE_INCREMENT_VALUE=10100111110001011_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=0,C_S_PHASE_TDATA_WIDTH=1,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=16,C_M_DATA" &
"_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=1,C_M_PHASE_TDATA_WIDTH=32,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TDATA";
BEGIN
U0 : dds_compiler_v6_0_12
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 29,
C_CHANNELS => 1,
C_HAS_PHASE_OUT => 1,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 3,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 2,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 8,
C_PHASE_ANGLE_WIDTH => 8,
C_PHASE_INCREMENT => 2,
C_PHASE_INCREMENT_VALUE => "10100111110001011,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 0,
C_S_PHASE_TDATA_WIDTH => 1,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 16,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 1,
C_M_PHASE_TDATA_WIDTH => 32,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tvalid => m_axis_phase_tvalid,
m_axis_phase_tready => '0',
m_axis_phase_tdata => m_axis_phase_tdata
);
END design_1_dds_compiler_0_1_arch;
|
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_comparator is
generic
(
width : integer := 16
);
port
(
input1 : in std_logic_vector((width - 1) downto 0);
input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector(2 downto 0)
);
end c_comparator;
architecture behavior of c_comparator is
function twocomp_bits_to_int (input : std_logic_vector)return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if (i < input'HIGH) then
if (input(input'HIGH) = '0') then
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
else
if input(i) = '0' then
ret_val := 2 ** i + ret_val;
end if;
end if;
end if;
end loop;
if (input(input'HIGH) = '1') then
ret_val := ret_val + 1;
ret_val := 0 - ret_val;
end if; return ret_val;
end twocomp_bits_to_int;
begin
P0 : process (input1, input2)
variable result : std_logic_vector(2 downto 0);
variable inp1, inp2 : integer;
begin
result := "000";
inp1 := twocomp_bits_to_int(input1);
inp2 := twocomp_bits_to_int(input2);
if (inp1 = inp2) then
result(0) := '1';
end if;
if (inp1 > inp2) then
result(1) := '1';
end if;
if (inp1 < inp2) then
result(2) := '1';
end if;
output <= result;
end process P0;
end behavior; |
-- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: add_flt_stratix5_speed.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix V" DIRECTION="ADD" OPTIMIZE="SPEED" PIPELINE=14 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 clk_en clock dataa datab result
--VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_altfp_add_sub 2013:10:23:18:05:48:SJ cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_compare 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ VERSION_END
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources = reg 27
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altbarrel_shift_nud IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END add_flt_stratix5_speed_altbarrel_shift_nud;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altbarrel_shift_nud IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w702w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w698w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w724w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w720w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w768w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w764w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range665w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range687w701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range708w723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range730w745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range752w767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w716w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w738w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w760w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w684w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w705w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w727w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w749w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w771w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w676w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w679w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w697w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w700w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w719w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w722w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w741w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w744w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w763w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w766w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range728w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range750w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range663w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range686w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range706w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range759w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop0 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) AND wire_lbarrel_shift_w679w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) AND wire_lbarrel_shift_w676w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) AND wire_lbarrel_shift_w700w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) AND wire_lbarrel_shift_w697w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) AND wire_lbarrel_shift_w722w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) AND wire_lbarrel_shift_w719w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) AND wire_lbarrel_shift_w744w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) AND wire_lbarrel_shift_w741w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) AND wire_lbarrel_shift_w766w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) AND wire_lbarrel_shift_w763w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) AND wire_lbarrel_shift_w_sbit_w_range663w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) AND wire_lbarrel_shift_w_sbit_w_range686w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) AND wire_lbarrel_shift_w_sbit_w_range706w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) AND wire_lbarrel_shift_w_sbit_w_range728w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) AND wire_lbarrel_shift_w_sbit_w_range750w(i);
END GENERATE loop14;
wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0) <= NOT wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0) <= NOT wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0) <= NOT wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0) <= NOT wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0) <= NOT wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) <= NOT wire_lbarrel_shift_w_sel_w_range668w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) <= NOT wire_lbarrel_shift_w_sel_w_range689w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) <= NOT wire_lbarrel_shift_w_sel_w_range711w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) <= NOT wire_lbarrel_shift_w_sel_w_range733w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) <= NOT wire_lbarrel_shift_w_sel_w_range755w(0);
loop15 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i);
END GENERATE loop17;
loop18 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i);
END GENERATE loop18;
loop19 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w684w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w705w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w727w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i);
END GENERATE loop22;
loop23 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w749w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i);
END GENERATE loop23;
loop24 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w771w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i);
END GENERATE loop24;
dir_w <= ( dir_pipe(0) & dir_w(3 DOWNTO 0) & direction_w);
direction_w <= '0';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( sbit_piper1d & smux_w(103 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_lbarrel_shift_w771w & wire_lbarrel_shift_w749w & wire_lbarrel_shift_w727w & wire_lbarrel_shift_w705w & wire_lbarrel_shift_w684w);
wire_lbarrel_shift_w676w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_lbarrel_shift_w679w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_lbarrel_shift_w697w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_lbarrel_shift_w700w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_lbarrel_shift_w719w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_lbarrel_shift_w722w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_lbarrel_shift_w741w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_lbarrel_shift_w744w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_lbarrel_shift_w763w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_lbarrel_shift_w766w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_lbarrel_shift_w_dir_w_range665w(0) <= dir_w(0);
wire_lbarrel_shift_w_dir_w_range687w(0) <= dir_w(1);
wire_lbarrel_shift_w_dir_w_range708w(0) <= dir_w(2);
wire_lbarrel_shift_w_dir_w_range730w(0) <= dir_w(3);
wire_lbarrel_shift_w_dir_w_range752w(0) <= dir_w(4);
wire_lbarrel_shift_w_sbit_w_range728w <= sbit_w(103 DOWNTO 78);
wire_lbarrel_shift_w_sbit_w_range750w <= sbit_w(129 DOWNTO 104);
wire_lbarrel_shift_w_sbit_w_range663w <= sbit_w(25 DOWNTO 0);
wire_lbarrel_shift_w_sbit_w_range686w <= sbit_w(51 DOWNTO 26);
wire_lbarrel_shift_w_sbit_w_range706w <= sbit_w(77 DOWNTO 52);
wire_lbarrel_shift_w_sel_w_range668w(0) <= sel_w(0);
wire_lbarrel_shift_w_sel_w_range689w(0) <= sel_w(1);
wire_lbarrel_shift_w_sel_w_range711w(0) <= sel_w(2);
wire_lbarrel_shift_w_sel_w_range733w(0) <= sel_w(3);
wire_lbarrel_shift_w_sel_w_range755w(0) <= sel_w(4);
wire_lbarrel_shift_w_smux_w_range759w <= smux_w(129 DOWNTO 104);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(4));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_lbarrel_shift_w_smux_w_range759w;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_speed_altbarrel_shift_nud
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=2 REGISTER_OUTPUT="NO" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources = reg 58
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altbarrel_shift_u1g IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END add_flt_stratix5_speed_altbarrel_shift_u1g;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altbarrel_shift_u1g IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper2d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sel_pipec2r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec3r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec4r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec4r2d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w839w840w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w835w836w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w858w859w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w854w855w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w879w880w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w875w876w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w831w832w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w850w851w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w871w872w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w796w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w792w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w817w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w813w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range827w839w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range827w835w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range846w858w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range846w854w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range867w879w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range867w875w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range780w795w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range802w816w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range825w838w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range844w857w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range865w878w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w788w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w809w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range827w831w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range846w850w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range867w871w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range827w839w840w841w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range846w858w859w860w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range867w879w880w881w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w799w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w820w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w842w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w861w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w882w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w791w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w794w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w812w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w815w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w834w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w837w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w853w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w856w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w874w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w877w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range780w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range802w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range825w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range844w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range865w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range843w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range862w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range778w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range801w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range821w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range783w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range804w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range827w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range846w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range867w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_smux_w_range849w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_smux_w_range808w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop25 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w796w(0) AND wire_rbarrel_shift_w794w(i);
END GENERATE loop25;
loop26 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w792w(0) AND wire_rbarrel_shift_w791w(i);
END GENERATE loop26;
loop27 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w817w(0) AND wire_rbarrel_shift_w815w(i);
END GENERATE loop27;
loop28 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w813w(0) AND wire_rbarrel_shift_w812w(i);
END GENERATE loop28;
loop29 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w839w840w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range827w839w(0) AND wire_rbarrel_shift_w837w(i);
END GENERATE loop29;
loop30 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w835w836w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range827w835w(0) AND wire_rbarrel_shift_w834w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w858w859w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range846w858w(0) AND wire_rbarrel_shift_w856w(i);
END GENERATE loop31;
loop32 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w854w855w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range846w854w(0) AND wire_rbarrel_shift_w853w(i);
END GENERATE loop32;
loop33 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w879w880w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range867w879w(0) AND wire_rbarrel_shift_w877w(i);
END GENERATE loop33;
loop34 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w875w876w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range867w875w(0) AND wire_rbarrel_shift_w874w(i);
END GENERATE loop34;
loop35 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w788w(0) AND wire_rbarrel_shift_w_sbit_w_range778w(i);
END GENERATE loop35;
loop36 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w809w(0) AND wire_rbarrel_shift_w_sbit_w_range801w(i);
END GENERATE loop36;
loop37 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w831w832w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range827w831w(0) AND wire_rbarrel_shift_w_sbit_w_range821w(i);
END GENERATE loop37;
loop38 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w850w851w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range846w850w(0) AND wire_rbarrel_shift_w_sbit_w_range843w(i);
END GENERATE loop38;
loop39 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w871w872w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range867w871w(0) AND wire_rbarrel_shift_w_sbit_w_range862w(i);
END GENERATE loop39;
wire_rbarrel_shift_w_lg_w_sel_w_range783w796w(0) <= wire_rbarrel_shift_w_sel_w_range783w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range780w795w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range783w792w(0) <= wire_rbarrel_shift_w_sel_w_range783w(0) AND wire_rbarrel_shift_w_dir_w_range780w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w817w(0) <= wire_rbarrel_shift_w_sel_w_range804w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range802w816w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w813w(0) <= wire_rbarrel_shift_w_sel_w_range804w(0) AND wire_rbarrel_shift_w_dir_w_range802w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range827w839w(0) <= wire_rbarrel_shift_w_sel_w_range827w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range825w838w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range827w835w(0) <= wire_rbarrel_shift_w_sel_w_range827w(0) AND wire_rbarrel_shift_w_dir_w_range825w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range846w858w(0) <= wire_rbarrel_shift_w_sel_w_range846w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range844w857w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range846w854w(0) <= wire_rbarrel_shift_w_sel_w_range846w(0) AND wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range867w879w(0) <= wire_rbarrel_shift_w_sel_w_range867w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range865w878w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range867w875w(0) <= wire_rbarrel_shift_w_sel_w_range867w(0) AND wire_rbarrel_shift_w_dir_w_range865w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range780w795w(0) <= NOT wire_rbarrel_shift_w_dir_w_range780w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range802w816w(0) <= NOT wire_rbarrel_shift_w_dir_w_range802w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range825w838w(0) <= NOT wire_rbarrel_shift_w_dir_w_range825w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range844w857w(0) <= NOT wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range865w878w(0) <= NOT wire_rbarrel_shift_w_dir_w_range865w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range783w788w(0) <= NOT wire_rbarrel_shift_w_sel_w_range783w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w809w(0) <= NOT wire_rbarrel_shift_w_sel_w_range804w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range827w831w(0) <= NOT wire_rbarrel_shift_w_sel_w_range827w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range846w850w(0) <= NOT wire_rbarrel_shift_w_sel_w_range846w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range867w871w(0) <= NOT wire_rbarrel_shift_w_sel_w_range867w(0);
loop40 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w(i);
END GENERATE loop40;
loop41 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w(i);
END GENERATE loop41;
loop42 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range827w839w840w841w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w839w840w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w835w836w(i);
END GENERATE loop42;
loop43 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range846w858w859w860w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w858w859w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w854w855w(i);
END GENERATE loop43;
loop44 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range867w879w880w881w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w879w880w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w875w876w(i);
END GENERATE loop44;
loop45 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w799w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w(i);
END GENERATE loop45;
loop46 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w820w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w(i);
END GENERATE loop46;
loop47 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w842w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range827w839w840w841w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range827w831w832w(i);
END GENERATE loop47;
loop48 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w861w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range846w858w859w860w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range846w850w851w(i);
END GENERATE loop48;
loop49 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w882w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range867w879w880w881w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range867w871w872w(i);
END GENERATE loop49;
dir_w <= ( dir_w(4) & dir_pipe(1) & dir_w(2) & dir_pipe(0) & dir_w(0) & direction_w);
direction_w <= '1';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( smux_w(129 DOWNTO 104) & sbit_piper2d & smux_w(77 DOWNTO 52) & sbit_piper1d & smux_w(25 DOWNTO 0) & data);
sel_w <= ( sel_pipec4r2d & sel_pipec3r1d & sel_pipec2r1d & distance(1 DOWNTO 0));
smux_w <= ( wire_rbarrel_shift_w882w & wire_rbarrel_shift_w861w & wire_rbarrel_shift_w842w & wire_rbarrel_shift_w820w & wire_rbarrel_shift_w799w);
wire_rbarrel_shift_w791w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_rbarrel_shift_w794w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_rbarrel_shift_w812w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_rbarrel_shift_w815w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_rbarrel_shift_w834w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_rbarrel_shift_w837w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_rbarrel_shift_w853w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_rbarrel_shift_w856w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_rbarrel_shift_w874w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_rbarrel_shift_w877w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_rbarrel_shift_w_dir_w_range780w(0) <= dir_w(0);
wire_rbarrel_shift_w_dir_w_range802w(0) <= dir_w(1);
wire_rbarrel_shift_w_dir_w_range825w(0) <= dir_w(2);
wire_rbarrel_shift_w_dir_w_range844w(0) <= dir_w(3);
wire_rbarrel_shift_w_dir_w_range865w(0) <= dir_w(4);
wire_rbarrel_shift_w_sbit_w_range843w <= sbit_w(103 DOWNTO 78);
wire_rbarrel_shift_w_sbit_w_range862w <= sbit_w(129 DOWNTO 104);
wire_rbarrel_shift_w_sbit_w_range778w <= sbit_w(25 DOWNTO 0);
wire_rbarrel_shift_w_sbit_w_range801w <= sbit_w(51 DOWNTO 26);
wire_rbarrel_shift_w_sbit_w_range821w <= sbit_w(77 DOWNTO 52);
wire_rbarrel_shift_w_sel_w_range783w(0) <= sel_w(0);
wire_rbarrel_shift_w_sel_w_range804w(0) <= sel_w(1);
wire_rbarrel_shift_w_sel_w_range827w(0) <= sel_w(2);
wire_rbarrel_shift_w_sel_w_range846w(0) <= sel_w(3);
wire_rbarrel_shift_w_sel_w_range867w(0) <= sel_w(4);
wire_rbarrel_shift_w_smux_w_range849w <= smux_w(103 DOWNTO 78);
wire_rbarrel_shift_w_smux_w_range808w <= smux_w(51 DOWNTO 26);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe <= ( dir_w(3) & dir_w(1));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_rbarrel_shift_w_smux_w_range808w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper2d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper2d <= wire_rbarrel_shift_w_smux_w_range849w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec2r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec2r1d <= distance(2);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec3r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec3r1d <= distance(3);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec4r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec4r1d <= distance(4);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec4r2d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec4r2d <= sel_pipec4r1d;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_speed_altbarrel_shift_u1g
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" PIPELINE=1 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_3e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_3e8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_3e8 IS
BEGIN
q(0) <= ( data(1));
zero <= (NOT (data(0) OR data(1)));
END RTL; --add_flt_stratix5_speed_altpriority_encoder_3e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_6e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_6e8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_6e8 IS
SIGNAL wire_altpriority_encoder13_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero916w917w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero918w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero916w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero918w919w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder14_w_lg_zero916w & wire_altpriority_encoder14_w_lg_w_lg_zero918w919w);
zero <= (wire_altpriority_encoder13_zero AND wire_altpriority_encoder14_zero);
altpriority_encoder13 : add_flt_stratix5_speed_altpriority_encoder_3e8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder13_q,
zero => wire_altpriority_encoder13_zero
);
wire_altpriority_encoder14_w_lg_w_lg_zero916w917w(0) <= wire_altpriority_encoder14_w_lg_zero916w(0) AND wire_altpriority_encoder14_q(0);
wire_altpriority_encoder14_w_lg_zero918w(0) <= wire_altpriority_encoder14_zero AND wire_altpriority_encoder13_q(0);
wire_altpriority_encoder14_w_lg_zero916w(0) <= NOT wire_altpriority_encoder14_zero;
wire_altpriority_encoder14_w_lg_w_lg_zero918w919w(0) <= wire_altpriority_encoder14_w_lg_zero918w(0) OR wire_altpriority_encoder14_w_lg_w_lg_zero916w917w(0);
altpriority_encoder14 : add_flt_stratix5_speed_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder14_q,
zero => wire_altpriority_encoder14_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_6e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_be8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_be8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_be8 IS
SIGNAL wire_altpriority_encoder11_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero906w907w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero908w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero906w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero908w909w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder12_w_lg_zero906w & wire_altpriority_encoder12_w_lg_w_lg_zero908w909w);
zero <= (wire_altpriority_encoder11_zero AND wire_altpriority_encoder12_zero);
altpriority_encoder11 : add_flt_stratix5_speed_altpriority_encoder_6e8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder11_q,
zero => wire_altpriority_encoder11_zero
);
loop50 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero906w907w(i) <= wire_altpriority_encoder12_w_lg_zero906w(0) AND wire_altpriority_encoder12_q(i);
END GENERATE loop50;
loop51 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_zero908w(i) <= wire_altpriority_encoder12_zero AND wire_altpriority_encoder11_q(i);
END GENERATE loop51;
wire_altpriority_encoder12_w_lg_zero906w(0) <= NOT wire_altpriority_encoder12_zero;
loop52 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero908w909w(i) <= wire_altpriority_encoder12_w_lg_zero908w(i) OR wire_altpriority_encoder12_w_lg_w_lg_zero906w907w(i);
END GENERATE loop52;
altpriority_encoder12 : add_flt_stratix5_speed_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder12_q,
zero => wire_altpriority_encoder12_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_be8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_3v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_3v7;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_3v7 IS
BEGIN
q(0) <= ( data(1));
END RTL; --add_flt_stratix5_speed_altpriority_encoder_3v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_6v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_6v7;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_6v7 IS
SIGNAL wire_altpriority_encoder17_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero941w942w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero943w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero941w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero943w944w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_3v7
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder18_w_lg_zero941w & wire_altpriority_encoder18_w_lg_w_lg_zero943w944w);
altpriority_encoder17 : add_flt_stratix5_speed_altpriority_encoder_3v7
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder17_q
);
wire_altpriority_encoder18_w_lg_w_lg_zero941w942w(0) <= wire_altpriority_encoder18_w_lg_zero941w(0) AND wire_altpriority_encoder18_q(0);
wire_altpriority_encoder18_w_lg_zero943w(0) <= wire_altpriority_encoder18_zero AND wire_altpriority_encoder17_q(0);
wire_altpriority_encoder18_w_lg_zero941w(0) <= NOT wire_altpriority_encoder18_zero;
wire_altpriority_encoder18_w_lg_w_lg_zero943w944w(0) <= wire_altpriority_encoder18_w_lg_zero943w(0) OR wire_altpriority_encoder18_w_lg_w_lg_zero941w942w(0);
altpriority_encoder18 : add_flt_stratix5_speed_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder18_q,
zero => wire_altpriority_encoder18_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_6v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_bv7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_bv7;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_bv7 IS
SIGNAL wire_altpriority_encoder15_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero932w933w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero934w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero932w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero934w935w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_6v7
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder16_w_lg_zero932w & wire_altpriority_encoder16_w_lg_w_lg_zero934w935w);
altpriority_encoder15 : add_flt_stratix5_speed_altpriority_encoder_6v7
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder15_q
);
loop53 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero932w933w(i) <= wire_altpriority_encoder16_w_lg_zero932w(0) AND wire_altpriority_encoder16_q(i);
END GENERATE loop53;
loop54 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_zero934w(i) <= wire_altpriority_encoder16_zero AND wire_altpriority_encoder15_q(i);
END GENERATE loop54;
wire_altpriority_encoder16_w_lg_zero932w(0) <= NOT wire_altpriority_encoder16_zero;
loop55 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero934w935w(i) <= wire_altpriority_encoder16_w_lg_zero934w(i) OR wire_altpriority_encoder16_w_lg_w_lg_zero932w933w(i);
END GENERATE loop55;
altpriority_encoder16 : add_flt_stratix5_speed_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder16_q,
zero => wire_altpriority_encoder16_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_bv7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_uv8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_uv8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_uv8 IS
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero897w898w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero899w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero897w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero899w900w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder9_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_bv7
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder10_w_lg_zero897w & wire_altpriority_encoder10_w_lg_w_lg_zero899w900w);
loop56 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero897w898w(i) <= wire_altpriority_encoder10_w_lg_zero897w(0) AND wire_altpriority_encoder10_q(i);
END GENERATE loop56;
loop57 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_zero899w(i) <= wire_altpriority_encoder10_zero AND wire_altpriority_encoder9_q(i);
END GENERATE loop57;
wire_altpriority_encoder10_w_lg_zero897w(0) <= NOT wire_altpriority_encoder10_zero;
loop58 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero899w900w(i) <= wire_altpriority_encoder10_w_lg_zero899w(i) OR wire_altpriority_encoder10_w_lg_w_lg_zero897w898w(i);
END GENERATE loop58;
altpriority_encoder10 : add_flt_stratix5_speed_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder10_q,
zero => wire_altpriority_encoder10_zero
);
altpriority_encoder9 : add_flt_stratix5_speed_altpriority_encoder_bv7
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder9_q
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_uv8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_ue9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_ue9;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_ue9 IS
SIGNAL wire_altpriority_encoder19_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero953w954w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero955w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero953w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero955w956w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder20_w_lg_zero953w & wire_altpriority_encoder20_w_lg_w_lg_zero955w956w);
zero <= (wire_altpriority_encoder19_zero AND wire_altpriority_encoder20_zero);
altpriority_encoder19 : add_flt_stratix5_speed_altpriority_encoder_be8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder19_q,
zero => wire_altpriority_encoder19_zero
);
loop59 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero953w954w(i) <= wire_altpriority_encoder20_w_lg_zero953w(0) AND wire_altpriority_encoder20_q(i);
END GENERATE loop59;
loop60 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_zero955w(i) <= wire_altpriority_encoder20_zero AND wire_altpriority_encoder19_q(i);
END GENERATE loop60;
wire_altpriority_encoder20_w_lg_zero953w(0) <= NOT wire_altpriority_encoder20_zero;
loop61 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero955w956w(i) <= wire_altpriority_encoder20_w_lg_zero955w(i) OR wire_altpriority_encoder20_w_lg_w_lg_zero953w954w(i);
END GENERATE loop61;
altpriority_encoder20 : add_flt_stratix5_speed_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder20_q,
zero => wire_altpriority_encoder20_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_ue9
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_ou8 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_ou8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_ou8 IS
SIGNAL wire_altpriority_encoder7_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero887w888w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero889w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero887w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero889w890w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_zero : STD_LOGIC;
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altpriority_encoder_uv8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_ue9
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= pipeline_q_dffe;
tmp_q_wire <= ( wire_altpriority_encoder8_w_lg_zero887w & wire_altpriority_encoder8_w_lg_w_lg_zero889w890w);
altpriority_encoder7 : add_flt_stratix5_speed_altpriority_encoder_uv8
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder7_q
);
loop62 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero887w888w(i) <= wire_altpriority_encoder8_w_lg_zero887w(0) AND wire_altpriority_encoder8_q(i);
END GENERATE loop62;
loop63 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_zero889w(i) <= wire_altpriority_encoder8_zero AND wire_altpriority_encoder7_q(i);
END GENERATE loop63;
wire_altpriority_encoder8_w_lg_zero887w(0) <= NOT wire_altpriority_encoder8_zero;
loop64 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero889w890w(i) <= wire_altpriority_encoder8_w_lg_zero889w(i) OR wire_altpriority_encoder8_w_lg_w_lg_zero887w888w(i);
END GENERATE loop64;
altpriority_encoder8 : add_flt_stratix5_speed_altpriority_encoder_ue9
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder8_q,
zero => wire_altpriority_encoder8_zero
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= tmp_q_wire;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_speed_altpriority_encoder_ou8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=2 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=1 WIDTH=16 WIDTHAD=4 aclr clk_en clock data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_nh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_nh8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_nh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_data_range1008w1010w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_data_range1008w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder27_w_lg_w_data_range1008w1010w(0) <= NOT wire_altpriority_encoder27_w_data_range1008w(0);
q <= ( wire_altpriority_encoder27_w_lg_w_data_range1008w1010w);
zero <= (NOT (data(0) OR data(1)));
wire_altpriority_encoder27_w_data_range1008w(0) <= data(0);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_nh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_qh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_qh8;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_qh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero1002w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero1000w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero1002w1003w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder28_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder27_zero & wire_altpriority_encoder27_w_lg_w_lg_zero1002w1003w);
zero <= (wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_zero);
wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w(0) <= wire_altpriority_encoder27_w_lg_zero1000w(0) AND wire_altpriority_encoder27_q(0);
wire_altpriority_encoder27_w_lg_zero1002w(0) <= wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_q(0);
wire_altpriority_encoder27_w_lg_zero1000w(0) <= NOT wire_altpriority_encoder27_zero;
wire_altpriority_encoder27_w_lg_w_lg_zero1002w1003w(0) <= wire_altpriority_encoder27_w_lg_zero1002w(0) OR wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w(0);
altpriority_encoder27 : add_flt_stratix5_speed_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder27_q,
zero => wire_altpriority_encoder27_zero
);
altpriority_encoder28 : add_flt_stratix5_speed_altpriority_encoder_nh8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder28_q,
zero => wire_altpriority_encoder28_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_qh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_2h9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_2h9;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_2h9 IS
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero990w991w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero992w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero990w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero992w993w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder26_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_zero : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder25_zero & wire_altpriority_encoder25_w_lg_w_lg_zero992w993w);
zero <= (wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_zero);
loop65 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero990w991w(i) <= wire_altpriority_encoder25_w_lg_zero990w(0) AND wire_altpriority_encoder25_q(i);
END GENERATE loop65;
loop66 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_zero992w(i) <= wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_q(i);
END GENERATE loop66;
wire_altpriority_encoder25_w_lg_zero990w(0) <= NOT wire_altpriority_encoder25_zero;
loop67 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero992w993w(i) <= wire_altpriority_encoder25_w_lg_zero992w(i) OR wire_altpriority_encoder25_w_lg_w_lg_zero990w991w(i);
END GENERATE loop67;
altpriority_encoder25 : add_flt_stratix5_speed_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder25_q,
zero => wire_altpriority_encoder25_zero
);
altpriority_encoder26 : add_flt_stratix5_speed_altpriority_encoder_qh8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder26_q,
zero => wire_altpriority_encoder26_zero
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_2h9
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_d6b IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END add_flt_stratix5_speed_altpriority_encoder_d6b;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_d6b IS
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero975w976w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero977w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero975w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero977w978w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder24_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_zero : STD_LOGIC;
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(3 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL pipeline_zero_n_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_pipeline_zero_n_dffe_w_lg_q987w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_tmp_q_wire984w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_tmp_zero_wire985w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tmp_zero_wire : STD_LOGIC;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_2h9
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
loop68 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_tmp_q_wire984w(i) <= NOT tmp_q_wire(i);
END GENERATE loop68;
wire_altpriority_encoder21_w_lg_tmp_zero_wire985w(0) <= NOT tmp_zero_wire;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder23_zero & wire_altpriority_encoder23_w_lg_w_lg_zero977w978w);
tmp_zero_wire <= (wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_zero);
zero <= wire_pipeline_zero_n_dffe_w_lg_q987w(0);
loop69 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero975w976w(i) <= wire_altpriority_encoder23_w_lg_zero975w(0) AND wire_altpriority_encoder23_q(i);
END GENERATE loop69;
loop70 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_zero977w(i) <= wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_q(i);
END GENERATE loop70;
wire_altpriority_encoder23_w_lg_zero975w(0) <= NOT wire_altpriority_encoder23_zero;
loop71 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero977w978w(i) <= wire_altpriority_encoder23_w_lg_zero977w(i) OR wire_altpriority_encoder23_w_lg_w_lg_zero975w976w(i);
END GENERATE loop71;
altpriority_encoder23 : add_flt_stratix5_speed_altpriority_encoder_2h9
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder23_q,
zero => wire_altpriority_encoder23_zero
);
altpriority_encoder24 : add_flt_stratix5_speed_altpriority_encoder_2h9
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder24_q,
zero => wire_altpriority_encoder24_zero
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_altpriority_encoder21_w_lg_tmp_q_wire984w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_zero_n_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_zero_n_dffe <= wire_altpriority_encoder21_w_lg_tmp_zero_wire985w(0);
END IF;
END IF;
END PROCESS;
wire_pipeline_zero_n_dffe_w_lg_q987w(0) <= NOT pipeline_zero_n_dffe;
END RTL; --add_flt_stratix5_speed_altpriority_encoder_d6b
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=1 WIDTH=16 WIDTHAD=4 aclr clk_en clock data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_n28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_n28;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_n28 IS
SIGNAL wire_altpriority_encoder34_w_lg_w_data_range1045w1047w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_data_range1045w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder34_w_lg_w_data_range1045w1047w(0) <= NOT wire_altpriority_encoder34_w_data_range1045w(0);
q <= ( wire_altpriority_encoder34_w_lg_w_data_range1045w1047w);
wire_altpriority_encoder34_w_data_range1045w(0) <= data(0);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_n28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_q28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_q28;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_q28 IS
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1038w1039w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1040w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1038w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1040w1041w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder34_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_n28
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder33_zero & wire_altpriority_encoder33_w_lg_w_lg_zero1040w1041w);
wire_altpriority_encoder33_w_lg_w_lg_zero1038w1039w(0) <= wire_altpriority_encoder33_w_lg_zero1038w(0) AND wire_altpriority_encoder33_q(0);
wire_altpriority_encoder33_w_lg_zero1040w(0) <= wire_altpriority_encoder33_zero AND wire_altpriority_encoder34_q(0);
wire_altpriority_encoder33_w_lg_zero1038w(0) <= NOT wire_altpriority_encoder33_zero;
wire_altpriority_encoder33_w_lg_w_lg_zero1040w1041w(0) <= wire_altpriority_encoder33_w_lg_zero1040w(0) OR wire_altpriority_encoder33_w_lg_w_lg_zero1038w1039w(0);
altpriority_encoder33 : add_flt_stratix5_speed_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder33_q,
zero => wire_altpriority_encoder33_zero
);
altpriority_encoder34 : add_flt_stratix5_speed_altpriority_encoder_n28
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder34_q
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_q28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_229 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_229;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_229 IS
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1029w1030w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1031w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1029w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1031w1032w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder32_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_q28
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder31_zero & wire_altpriority_encoder31_w_lg_w_lg_zero1031w1032w);
loop72 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1029w1030w(i) <= wire_altpriority_encoder31_w_lg_zero1029w(0) AND wire_altpriority_encoder31_q(i);
END GENERATE loop72;
loop73 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_zero1031w(i) <= wire_altpriority_encoder31_zero AND wire_altpriority_encoder32_q(i);
END GENERATE loop73;
wire_altpriority_encoder31_w_lg_zero1029w(0) <= NOT wire_altpriority_encoder31_zero;
loop74 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1031w1032w(i) <= wire_altpriority_encoder31_w_lg_zero1031w(i) OR wire_altpriority_encoder31_w_lg_w_lg_zero1029w1030w(i);
END GENERATE loop74;
altpriority_encoder31 : add_flt_stratix5_speed_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder31_q,
zero => wire_altpriority_encoder31_zero
);
altpriority_encoder32 : add_flt_stratix5_speed_altpriority_encoder_q28
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder32_q
);
END RTL; --add_flt_stratix5_speed_altpriority_encoder_229
--synthesis_resources = reg 4
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_ena IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_ena;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_ena IS
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1019w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1017w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1019w1020w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder30_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(3 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_altpriority_encoder22_w_lg_tmp_q_wire1025w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altpriority_encoder_2h9
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_229
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
loop75 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder22_w_lg_tmp_q_wire1025w(i) <= NOT tmp_q_wire(i);
END GENERATE loop75;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder29_zero & wire_altpriority_encoder29_w_lg_w_lg_zero1019w1020w);
loop76 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w(i) <= wire_altpriority_encoder29_w_lg_zero1017w(0) AND wire_altpriority_encoder29_q(i);
END GENERATE loop76;
loop77 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_zero1019w(i) <= wire_altpriority_encoder29_zero AND wire_altpriority_encoder30_q(i);
END GENERATE loop77;
wire_altpriority_encoder29_w_lg_zero1017w(0) <= NOT wire_altpriority_encoder29_zero;
loop78 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1019w1020w(i) <= wire_altpriority_encoder29_w_lg_zero1019w(i) OR wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w(i);
END GENERATE loop78;
altpriority_encoder29 : add_flt_stratix5_speed_altpriority_encoder_2h9
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder29_q,
zero => wire_altpriority_encoder29_zero
);
altpriority_encoder30 : add_flt_stratix5_speed_altpriority_encoder_229
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder30_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_altpriority_encoder22_w_lg_tmp_q_wire1025w;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_speed_altpriority_encoder_ena
--synthesis_resources = reg 14
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altpriority_encoder_dna IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END add_flt_stratix5_speed_altpriority_encoder_dna;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altpriority_encoder_dna IS
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero963w964w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero965w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero963w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero965w966w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder22_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_trailing_zeros_cnt_w_lg_tmp_q_wire971w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altpriority_encoder_d6b
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_ena
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
loop79 : FOR i IN 0 TO 4 GENERATE
wire_trailing_zeros_cnt_w_lg_tmp_q_wire971w(i) <= NOT tmp_q_wire(i);
END GENERATE loop79;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder21_zero & wire_altpriority_encoder21_w_lg_w_lg_zero965w966w);
loop80 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero963w964w(i) <= wire_altpriority_encoder21_w_lg_zero963w(0) AND wire_altpriority_encoder21_q(i);
END GENERATE loop80;
loop81 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_zero965w(i) <= wire_altpriority_encoder21_zero AND wire_altpriority_encoder22_q(i);
END GENERATE loop81;
wire_altpriority_encoder21_w_lg_zero963w(0) <= NOT wire_altpriority_encoder21_zero;
loop82 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero965w966w(i) <= wire_altpriority_encoder21_w_lg_zero965w(i) OR wire_altpriority_encoder21_w_lg_w_lg_zero963w964w(i);
END GENERATE loop82;
altpriority_encoder21 : add_flt_stratix5_speed_altpriority_encoder_d6b
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder21_q,
zero => wire_altpriority_encoder21_zero
);
altpriority_encoder22 : add_flt_stratix5_speed_altpriority_encoder_ena
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder22_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_trailing_zeros_cnt_w_lg_tmp_q_wire971w;
END IF;
END IF;
END PROCESS;
END RTL; --add_flt_stratix5_speed_altpriority_encoder_dna
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 816
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed_altfp_add_sub_jkj IS
PORT
(
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END add_flt_stratix5_speed_altfp_add_sub_jkj;
ARCHITECTURE RTL OF add_flt_stratix5_speed_altfp_add_sub_jkj IS
SIGNAL wire_lbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_data : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe15 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe15 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe15 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe15 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL both_inputs_are_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL data_exp_dffe1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL datab_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_adj_dffe21 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_adj_dffe23 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_intermediate_res_dffe41 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_out_dffe5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe21 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe23 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe27 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe21 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe23 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe27 : STD_LOGIC_VECTOR(27 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_dffe31 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_leading_zeros_dffe31 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_out_dffe5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_dffe4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_not_zero_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_rounding_add_sub_result_reg : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_smaller_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL need_complement_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rounded_res_infinity_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe13 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe14 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe15 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_out_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_sub1_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub2_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub3_result : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_add_sub4_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout366w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_cout : STD_LOGIC;
SIGNAL wire_man_2comp_res_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_cout354w355w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout353w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_add_sub_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout579w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_res_rounding_add_sub_lower_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_upper1_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_trailing_zeros_limit_comparator_agb : STD_LOGIC;
SIGNAL wire_w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w397w407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_denormal_result_w558w559w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w279w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w277w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w639w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w648w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w642w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w651w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w293w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w383w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w412w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w587w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w637w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w646w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo330w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo323w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo314w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w280w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w274w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w640w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w649w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w643w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w652w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_a_all_one_w_range84w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_b_all_one_w_range86w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range540w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range543w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range545w546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range547w548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range553w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range555w561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range601w604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range605w607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range608w610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range611w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range614w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range617w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range620w622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w379w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_dffe25_wo491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_w2342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_denormal_result_w558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_denormal_dffe11_wo233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_infinite_dffe11_wo246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_dffe11_wo245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_denormal_dffe11_wo252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe11_wo265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_dffe11_wo264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_is_not_zero_dffe4_wo627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_not_zero_dffe26_wo503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe1_wo343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_w_range215w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_w_range218w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w640w641w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w649w650w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe27_wo402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range516w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range520w522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range523w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range526w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range529w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range532w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range535w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range417w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range448w450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range451w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range460w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range463w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range466w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range469w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range472w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range475w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range478w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range481w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range484w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range487w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range427w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range430w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range436w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range439w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range442w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range445w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aclr : STD_LOGIC;
SIGNAL add_sub_dffe25_wi : STD_LOGIC;
SIGNAL add_sub_dffe25_wo : STD_LOGIC;
SIGNAL add_sub_w2 : STD_LOGIC;
SIGNAL adder_upper_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_datab_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL borrow_w : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wo : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wo : STD_LOGIC;
SIGNAL data_exp_dffe1_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_exp_dffe1_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wo : STD_LOGIC;
SIGNAL datab_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL denormal_flag_w : STD_LOGIC;
SIGNAL denormal_res_dffe32_wi : STD_LOGIC;
SIGNAL denormal_res_dffe32_wo : STD_LOGIC;
SIGNAL denormal_res_dffe33_wi : STD_LOGIC;
SIGNAL denormal_res_dffe33_wo : STD_LOGIC;
SIGNAL denormal_res_dffe3_wi : STD_LOGIC;
SIGNAL denormal_res_dffe3_wo : STD_LOGIC;
SIGNAL denormal_res_dffe41_wi : STD_LOGIC;
SIGNAL denormal_res_dffe41_wo : STD_LOGIC;
SIGNAL denormal_res_dffe42_wi : STD_LOGIC;
SIGNAL denormal_res_dffe42_wo : STD_LOGIC;
SIGNAL denormal_res_dffe4_wi : STD_LOGIC;
SIGNAL denormal_res_dffe4_wo : STD_LOGIC;
SIGNAL denormal_result_w : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_adj_0pads : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL exp_adj_dffe21_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe21_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_all_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_amb_mux_dffe13_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe13_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wo : STD_LOGIC;
SIGNAL exp_amb_mux_w : STD_LOGIC;
SIGNAL exp_amb_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bma_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_diff_abs_exceed_max_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_diff_abs_max_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL exp_diff_abs_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_not_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_rounded_res_infinity_w : STD_LOGIC;
SIGNAL exp_rounded_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounded_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounding_adjustment_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL force_infinity_w : STD_LOGIC;
SIGNAL force_nan_w : STD_LOGIC;
SIGNAL force_zero_w : STD_LOGIC;
SIGNAL guard_bit_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wo : STD_LOGIC;
SIGNAL infinite_res_dff32_wi : STD_LOGIC;
SIGNAL infinite_res_dff32_wo : STD_LOGIC;
SIGNAL infinite_res_dff33_wi : STD_LOGIC;
SIGNAL infinite_res_dff33_wo : STD_LOGIC;
SIGNAL infinite_res_dffe3_wi : STD_LOGIC;
SIGNAL infinite_res_dffe3_wo : STD_LOGIC;
SIGNAL infinite_res_dffe41_wi : STD_LOGIC;
SIGNAL infinite_res_dffe41_wo : STD_LOGIC;
SIGNAL infinite_res_dffe42_wi : STD_LOGIC;
SIGNAL infinite_res_dffe42_wo : STD_LOGIC;
SIGNAL infinite_res_dffe4_wi : STD_LOGIC;
SIGNAL infinite_res_dffe4_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_w : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_denormal_w : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_datab_infinite_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wo : STD_LOGIC;
SIGNAL man_2comp_res_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_add_sub_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wi : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wo : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_w2 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_sign_dffe21_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_w2 : STD_LOGIC;
SIGNAL man_add_sub_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_all_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_dffe31_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_intermediate_res_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_leading_zeros_cnt_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_is_not_zero_dffe31_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe31_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wo : STD_LOGIC;
SIGNAL man_res_mag_w2 : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_not_zero_dffe23_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe23_wo : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wo : STD_LOGIC;
SIGNAL man_res_not_zero_w2 : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_w3 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_rounded_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_rounding_add_value_w : STD_LOGIC;
SIGNAL man_smaller_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL need_complement_dffe22_wi : STD_LOGIC;
SIGNAL need_complement_dffe22_wo : STD_LOGIC;
SIGNAL need_complement_dffe2_wi : STD_LOGIC;
SIGNAL need_complement_dffe2_wo : STD_LOGIC;
SIGNAL pos_sign_bit_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL priority_encoder_1pads_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL round_bit_dffe21_wi : STD_LOGIC;
SIGNAL round_bit_dffe21_wo : STD_LOGIC;
SIGNAL round_bit_dffe23_wi : STD_LOGIC;
SIGNAL round_bit_dffe23_wo : STD_LOGIC;
SIGNAL round_bit_dffe26_wi : STD_LOGIC;
SIGNAL round_bit_dffe26_wo : STD_LOGIC;
SIGNAL round_bit_dffe31_wi : STD_LOGIC;
SIGNAL round_bit_dffe31_wo : STD_LOGIC;
SIGNAL round_bit_dffe32_wi : STD_LOGIC;
SIGNAL round_bit_dffe32_wo : STD_LOGIC;
SIGNAL round_bit_dffe33_wi : STD_LOGIC;
SIGNAL round_bit_dffe33_wo : STD_LOGIC;
SIGNAL round_bit_dffe3_wi : STD_LOGIC;
SIGNAL round_bit_dffe3_wo : STD_LOGIC;
SIGNAL round_bit_w : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wi : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wo : STD_LOGIC;
SIGNAL rshift_distance_dffe13_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe13_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sign_dffe31_wi : STD_LOGIC;
SIGNAL sign_dffe31_wo : STD_LOGIC;
SIGNAL sign_dffe32_wi : STD_LOGIC;
SIGNAL sign_dffe32_wo : STD_LOGIC;
SIGNAL sign_dffe33_wi : STD_LOGIC;
SIGNAL sign_dffe33_wo : STD_LOGIC;
SIGNAL sign_out_dffe5_wi : STD_LOGIC;
SIGNAL sign_out_dffe5_wo : STD_LOGIC;
SIGNAL sign_res_dffe3_wi : STD_LOGIC;
SIGNAL sign_res_dffe3_wo : STD_LOGIC;
SIGNAL sign_res_dffe41_wi : STD_LOGIC;
SIGNAL sign_res_dffe41_wo : STD_LOGIC;
SIGNAL sign_res_dffe42_wi : STD_LOGIC;
SIGNAL sign_res_dffe42_wo : STD_LOGIC;
SIGNAL sign_res_dffe4_wi : STD_LOGIC;
SIGNAL sign_res_dffe4_wo : STD_LOGIC;
SIGNAL sticky_bit_cnt_dataa_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_datab_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_res_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_dffe1_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe1_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wo : STD_LOGIC;
SIGNAL sticky_bit_w : STD_LOGIC;
SIGNAL trailing_zeros_limit_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL zero_man_sign_dffe21_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe21_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wo : STD_LOGIC;
SIGNAL wire_w_aligned_dataa_exp_dffe15_wo_range315w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_aligned_datab_exp_dffe15_wo_range313w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range242w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range232w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range261w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range251w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_amb_w_range275w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_bma_w_range273w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range291w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range411w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range413w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_w_range372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range584w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range588w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altbarrel_shift_nud
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altbarrel_shift_u1g
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_ou8
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT add_flt_stratix5_speed_altpriority_encoder_dna
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w248w(0) <= wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) AND wire_w_lg_input_dataa_zero_dffe11_wo245w(0);
wire_w267w(0) <= wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) AND wire_w_lg_input_datab_zero_dffe11_wo264w(0);
wire_w_lg_w397w407w(0) <= wire_w397w(0) AND sticky_bit_dffe27_wo;
loop83 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND exp_res_dffe4_wo(i);
END GENERATE loop83;
loop84 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND man_res_dffe4_wo(i);
END GENERATE loop84;
loop85 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_denormal_result_w558w559w(i) <= wire_w_lg_denormal_result_w558w(0) AND wire_w_exp_adjustment2_add_sub_w_range557w(i);
END GENERATE loop85;
loop86 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND aligned_dataa_man_dffe15_w(i);
END GENERATE loop86;
loop87 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_rbarrel_shift_result(i);
END GENERATE loop87;
loop88 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_w_aligned_dataa_exp_dffe15_wo_range315w(i);
END GENERATE loop88;
loop89 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w279w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND aligned_datab_man_dffe12_wo(i);
END GENERATE loop89;
loop90 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w277w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND wire_w_exp_amb_w_range275w(i);
END GENERATE loop90;
loop91 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w629w639w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i);
END GENERATE loop91;
loop92 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w629w648w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i);
END GENERATE loop92;
wire_w_lg_w_lg_force_infinity_w629w654w(0) <= wire_w_lg_force_infinity_w629w(0) AND sign_res_dffe4_wo;
loop93 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_nan_w630w642w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w640w641w(i);
END GENERATE loop93;
loop94 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_nan_w630w651w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w649w650w(i);
END GENERATE loop94;
loop95 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range242w(i);
END GENERATE loop95;
loop96 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range232w(i);
END GENERATE loop96;
wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) <= wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) AND wire_w_lg_input_dataa_denormal_dffe11_wo233w(0);
loop97 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range261w(i);
END GENERATE loop97;
loop98 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range251w(i);
END GENERATE loop98;
wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) <= wire_w_lg_input_datab_infinite_dffe11_wo265w(0) AND wire_w_lg_input_datab_denormal_dffe11_wo252w(0);
wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) <= wire_w_lg_input_datab_infinite_dffe15_wo337w(0) AND aligned_dataa_sign_dffe15_wo;
wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0) <= wire_w_lg_man_res_not_zero_dffe26_wo503w(0) AND zero_man_sign_dffe26_wo;
loop99 : FOR i IN 0 TO 4 GENERATE
wire_w293w(i) <= wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) AND wire_w_exp_diff_abs_w_range291w(i);
END GENERATE loop99;
wire_w397w(0) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop100 : FOR i IN 0 TO 1 GENERATE
wire_w383w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND exp_adjust_by_add1(i);
END GENERATE loop100;
loop101 : FOR i IN 0 TO 25 GENERATE
wire_w412w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range411w(i);
END GENERATE loop101;
loop102 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w(i) <= wire_w_lg_w_man_add_sub_w_range372w375w(0) AND man_add_sub_w(i);
END GENERATE loop102;
loop103 : FOR i IN 0 TO 22 GENERATE
wire_w587w(i) <= wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) AND wire_w_man_res_rounding_add_sub_w_range584w(i);
END GENERATE loop103;
loop104 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_zero_w634w637w(i) <= wire_w_lg_force_zero_w634w(0) AND exp_all_zeros_w(i);
END GENERATE loop104;
loop105 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_zero_w634w646w(i) <= wire_w_lg_force_zero_w634w(0) AND man_all_zeros_w(i);
END GENERATE loop105;
loop106 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo330w(i) <= exp_amb_mux_dffe15_wo AND aligned_datab_man_dffe15_w(i);
END GENERATE loop106;
loop107 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo323w(i) <= exp_amb_mux_dffe15_wo AND wire_rbarrel_shift_result(i);
END GENERATE loop107;
loop108 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo314w(i) <= exp_amb_mux_dffe15_wo AND wire_w_aligned_datab_exp_dffe15_wo_range313w(i);
END GENERATE loop108;
loop109 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_exp_amb_mux_w280w(i) <= exp_amb_mux_w AND aligned_dataa_man_dffe12_wo(i);
END GENERATE loop109;
loop110 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_w274w(i) <= exp_amb_mux_w AND wire_w_exp_bma_w_range273w(i);
END GENERATE loop110;
loop111 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_infinity_w640w(i) <= force_infinity_w AND exp_all_ones_w(i);
END GENERATE loop111;
loop112 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_infinity_w649w(i) <= force_infinity_w AND man_all_zeros_w(i);
END GENERATE loop112;
loop113 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_nan_w643w(i) <= force_nan_w AND exp_all_ones_w(i);
END GENERATE loop113;
loop114 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_nan_w652w(i) <= force_nan_w AND man_nan_w(i);
END GENERATE loop114;
wire_w_lg_need_complement_dffe22_wo376w(0) <= need_complement_dffe22_wo AND wire_w_lg_w_man_add_sub_w_range372w375w(0);
wire_w_lg_w_dataa_range17w23w(0) <= wire_w_dataa_range17w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range27w33w(0) <= wire_w_dataa_range27w(0) AND wire_w_exp_a_all_one_w_range24w(0);
wire_w_lg_w_dataa_range37w43w(0) <= wire_w_dataa_range37w(0) AND wire_w_exp_a_all_one_w_range34w(0);
wire_w_lg_w_dataa_range47w53w(0) <= wire_w_dataa_range47w(0) AND wire_w_exp_a_all_one_w_range44w(0);
wire_w_lg_w_dataa_range57w63w(0) <= wire_w_dataa_range57w(0) AND wire_w_exp_a_all_one_w_range54w(0);
wire_w_lg_w_dataa_range67w73w(0) <= wire_w_dataa_range67w(0) AND wire_w_exp_a_all_one_w_range64w(0);
wire_w_lg_w_dataa_range77w83w(0) <= wire_w_dataa_range77w(0) AND wire_w_exp_a_all_one_w_range74w(0);
wire_w_lg_w_datab_range20w25w(0) <= wire_w_datab_range20w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range30w35w(0) <= wire_w_datab_range30w(0) AND wire_w_exp_b_all_one_w_range26w(0);
wire_w_lg_w_datab_range40w45w(0) <= wire_w_datab_range40w(0) AND wire_w_exp_b_all_one_w_range36w(0);
wire_w_lg_w_datab_range50w55w(0) <= wire_w_datab_range50w(0) AND wire_w_exp_b_all_one_w_range46w(0);
wire_w_lg_w_datab_range60w65w(0) <= wire_w_datab_range60w(0) AND wire_w_exp_b_all_one_w_range56w(0);
wire_w_lg_w_datab_range70w75w(0) <= wire_w_datab_range70w(0) AND wire_w_exp_b_all_one_w_range66w(0);
wire_w_lg_w_datab_range80w85w(0) <= wire_w_datab_range80w(0) AND wire_w_exp_b_all_one_w_range76w(0);
wire_w_lg_w_exp_a_all_one_w_range84w220w(0) <= wire_w_exp_a_all_one_w_range84w(0) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0);
wire_w_lg_w_exp_b_all_one_w_range86w226w(0) <= wire_w_exp_b_all_one_w_range86w(0) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0);
loop115 : FOR i IN 0 TO 4 GENERATE
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w(i) <= wire_w_exp_diff_abs_exceed_max_w_range290w(0) AND exp_diff_abs_max_w(i);
END GENERATE loop115;
wire_w_lg_w_exp_res_max_w_range540w542w(0) <= wire_w_exp_res_max_w_range540w(0) AND wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_max_w_range543w544w(0) <= wire_w_exp_res_max_w_range543w(0) AND wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_max_w_range545w546w(0) <= wire_w_exp_res_max_w_range545w(0) AND wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_max_w_range547w548w(0) <= wire_w_exp_res_max_w_range547w(0) AND wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_max_w_range549w550w(0) <= wire_w_exp_res_max_w_range549w(0) AND wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_max_w_range551w552w(0) <= wire_w_exp_res_max_w_range551w(0) AND wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_max_w_range553w554w(0) <= wire_w_exp_res_max_w_range553w(0) AND wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_max_w_range555w561w(0) <= wire_w_exp_res_max_w_range555w(0) AND wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0);
wire_w_lg_w_exp_rounded_res_max_w_range601w604w(0) <= wire_w_exp_rounded_res_max_w_range601w(0) AND wire_w_exp_rounded_res_w_range603w(0);
wire_w_lg_w_exp_rounded_res_max_w_range605w607w(0) <= wire_w_exp_rounded_res_max_w_range605w(0) AND wire_w_exp_rounded_res_w_range606w(0);
wire_w_lg_w_exp_rounded_res_max_w_range608w610w(0) <= wire_w_exp_rounded_res_max_w_range608w(0) AND wire_w_exp_rounded_res_w_range609w(0);
wire_w_lg_w_exp_rounded_res_max_w_range611w613w(0) <= wire_w_exp_rounded_res_max_w_range611w(0) AND wire_w_exp_rounded_res_w_range612w(0);
wire_w_lg_w_exp_rounded_res_max_w_range614w616w(0) <= wire_w_exp_rounded_res_max_w_range614w(0) AND wire_w_exp_rounded_res_w_range615w(0);
wire_w_lg_w_exp_rounded_res_max_w_range617w619w(0) <= wire_w_exp_rounded_res_max_w_range617w(0) AND wire_w_exp_rounded_res_w_range618w(0);
wire_w_lg_w_exp_rounded_res_max_w_range620w622w(0) <= wire_w_exp_rounded_res_max_w_range620w(0) AND wire_w_exp_rounded_res_w_range621w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop116 : FOR i IN 0 TO 1 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND exp_adjust_by_add2(i);
END GENERATE loop116;
loop117 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range413w(i);
END GENERATE loop117;
loop118 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_man_add_sub_w_range372w379w(i) <= wire_w_man_add_sub_w_range372w(0) AND man_2comp_res_w(i);
END GENERATE loop118;
loop119 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w(i) <= wire_w_man_res_rounding_add_sub_w_range585w(0) AND wire_w_man_res_rounding_add_sub_w_range588w(i);
END GENERATE loop119;
wire_w_lg_w_lg_force_zero_w634w635w(0) <= NOT wire_w_lg_force_zero_w634w(0);
wire_w_lg_add_sub_dffe25_wo491w(0) <= NOT add_sub_dffe25_wo;
wire_w_lg_add_sub_w2342w(0) <= NOT add_sub_w2;
wire_w_lg_denormal_result_w558w(0) <= NOT denormal_result_w;
wire_w_lg_exp_amb_mux_dffe15_wo316w(0) <= NOT exp_amb_mux_dffe15_wo;
wire_w_lg_exp_amb_mux_w276w(0) <= NOT exp_amb_mux_w;
wire_w_lg_force_infinity_w629w(0) <= NOT force_infinity_w;
wire_w_lg_force_nan_w630w(0) <= NOT force_nan_w;
wire_w_lg_force_zero_w628w(0) <= NOT force_zero_w;
wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) <= NOT input_dataa_denormal_dffe11_wo;
wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) <= NOT input_dataa_infinite_dffe11_wo;
wire_w_lg_input_dataa_zero_dffe11_wo245w(0) <= NOT input_dataa_zero_dffe11_wo;
wire_w_lg_input_datab_denormal_dffe11_wo252w(0) <= NOT input_datab_denormal_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe11_wo265w(0) <= NOT input_datab_infinite_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe15_wo337w(0) <= NOT input_datab_infinite_dffe15_wo;
wire_w_lg_input_datab_zero_dffe11_wo264w(0) <= NOT input_datab_zero_dffe11_wo;
wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0) <= NOT man_res_is_not_zero_dffe4_wo;
wire_w_lg_man_res_not_zero_dffe26_wo503w(0) <= NOT man_res_not_zero_dffe26_wo;
wire_w_lg_need_complement_dffe22_wo373w(0) <= NOT need_complement_dffe22_wo;
wire_w_lg_sticky_bit_dffe1_wo343w(0) <= NOT sticky_bit_dffe1_wo;
wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0) <= NOT wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) <= NOT wire_w_exp_diff_abs_exceed_max_w_range290w(0);
wire_w_lg_w_man_a_not_zero_w_range215w219w(0) <= NOT wire_w_man_a_not_zero_w_range215w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0);
wire_w_lg_w_man_add_sub_w_range372w375w(0) <= NOT wire_w_man_add_sub_w_range372w(0);
wire_w_lg_w_man_b_not_zero_w_range218w225w(0) <= NOT wire_w_man_b_not_zero_w_range218w(0);
wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) <= NOT wire_w_man_res_rounding_add_sub_w_range585w(0);
loop120 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i) <= wire_w_lg_w_lg_force_zero_w634w637w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i);
END GENERATE loop120;
loop121 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i) <= wire_w_lg_w_lg_force_zero_w634w646w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i);
END GENERATE loop121;
loop122 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w640w641w(i) <= wire_w_lg_force_infinity_w640w(i) OR wire_w_lg_w_lg_force_infinity_w629w639w(i);
END GENERATE loop122;
loop123 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w649w650w(i) <= wire_w_lg_force_infinity_w649w(i) OR wire_w_lg_w_lg_force_infinity_w629w648w(i);
END GENERATE loop123;
wire_w_lg_force_zero_w634w(0) <= force_zero_w OR denormal_flag_w;
wire_w_lg_sticky_bit_dffe27_wo402w(0) <= sticky_bit_dffe27_wo OR wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range153w154w(0) <= wire_w_dataa_range153w(0) OR wire_w_man_a_not_zero_w_range149w(0);
wire_w_lg_w_dataa_range159w160w(0) <= wire_w_dataa_range159w(0) OR wire_w_man_a_not_zero_w_range155w(0);
wire_w_lg_w_dataa_range165w166w(0) <= wire_w_dataa_range165w(0) OR wire_w_man_a_not_zero_w_range161w(0);
wire_w_lg_w_dataa_range171w172w(0) <= wire_w_dataa_range171w(0) OR wire_w_man_a_not_zero_w_range167w(0);
wire_w_lg_w_dataa_range177w178w(0) <= wire_w_dataa_range177w(0) OR wire_w_man_a_not_zero_w_range173w(0);
wire_w_lg_w_dataa_range183w184w(0) <= wire_w_dataa_range183w(0) OR wire_w_man_a_not_zero_w_range179w(0);
wire_w_lg_w_dataa_range189w190w(0) <= wire_w_dataa_range189w(0) OR wire_w_man_a_not_zero_w_range185w(0);
wire_w_lg_w_dataa_range195w196w(0) <= wire_w_dataa_range195w(0) OR wire_w_man_a_not_zero_w_range191w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range12w(0);
wire_w_lg_w_dataa_range201w202w(0) <= wire_w_dataa_range201w(0) OR wire_w_man_a_not_zero_w_range197w(0);
wire_w_lg_w_dataa_range207w208w(0) <= wire_w_dataa_range207w(0) OR wire_w_man_a_not_zero_w_range203w(0);
wire_w_lg_w_dataa_range213w214w(0) <= wire_w_dataa_range213w(0) OR wire_w_man_a_not_zero_w_range209w(0);
wire_w_lg_w_dataa_range17w18w(0) <= wire_w_dataa_range17w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range27w28w(0) <= wire_w_dataa_range27w(0) OR wire_w_exp_a_not_zero_w_range19w(0);
wire_w_lg_w_dataa_range37w38w(0) <= wire_w_dataa_range37w(0) OR wire_w_exp_a_not_zero_w_range29w(0);
wire_w_lg_w_dataa_range47w48w(0) <= wire_w_dataa_range47w(0) OR wire_w_exp_a_not_zero_w_range39w(0);
wire_w_lg_w_dataa_range57w58w(0) <= wire_w_dataa_range57w(0) OR wire_w_exp_a_not_zero_w_range49w(0);
wire_w_lg_w_dataa_range67w68w(0) <= wire_w_dataa_range67w(0) OR wire_w_exp_a_not_zero_w_range59w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range77w78w(0) <= wire_w_dataa_range77w(0) OR wire_w_exp_a_not_zero_w_range69w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range156w157w(0) <= wire_w_datab_range156w(0) OR wire_w_man_b_not_zero_w_range152w(0);
wire_w_lg_w_datab_range162w163w(0) <= wire_w_datab_range162w(0) OR wire_w_man_b_not_zero_w_range158w(0);
wire_w_lg_w_datab_range168w169w(0) <= wire_w_datab_range168w(0) OR wire_w_man_b_not_zero_w_range164w(0);
wire_w_lg_w_datab_range174w175w(0) <= wire_w_datab_range174w(0) OR wire_w_man_b_not_zero_w_range170w(0);
wire_w_lg_w_datab_range180w181w(0) <= wire_w_datab_range180w(0) OR wire_w_man_b_not_zero_w_range176w(0);
wire_w_lg_w_datab_range186w187w(0) <= wire_w_datab_range186w(0) OR wire_w_man_b_not_zero_w_range182w(0);
wire_w_lg_w_datab_range192w193w(0) <= wire_w_datab_range192w(0) OR wire_w_man_b_not_zero_w_range188w(0);
wire_w_lg_w_datab_range198w199w(0) <= wire_w_datab_range198w(0) OR wire_w_man_b_not_zero_w_range194w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range15w(0);
wire_w_lg_w_datab_range204w205w(0) <= wire_w_datab_range204w(0) OR wire_w_man_b_not_zero_w_range200w(0);
wire_w_lg_w_datab_range210w211w(0) <= wire_w_datab_range210w(0) OR wire_w_man_b_not_zero_w_range206w(0);
wire_w_lg_w_datab_range216w217w(0) <= wire_w_datab_range216w(0) OR wire_w_man_b_not_zero_w_range212w(0);
wire_w_lg_w_datab_range20w21w(0) <= wire_w_datab_range20w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range30w31w(0) <= wire_w_datab_range30w(0) OR wire_w_exp_b_not_zero_w_range22w(0);
wire_w_lg_w_datab_range40w41w(0) <= wire_w_datab_range40w(0) OR wire_w_exp_b_not_zero_w_range32w(0);
wire_w_lg_w_datab_range50w51w(0) <= wire_w_datab_range50w(0) OR wire_w_exp_b_not_zero_w_range42w(0);
wire_w_lg_w_datab_range60w61w(0) <= wire_w_datab_range60w(0) OR wire_w_exp_b_not_zero_w_range52w(0);
wire_w_lg_w_datab_range70w71w(0) <= wire_w_datab_range70w(0) OR wire_w_exp_b_not_zero_w_range62w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range80w81w(0) <= wire_w_datab_range80w(0) OR wire_w_exp_b_not_zero_w_range72w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w(0) <= wire_w_exp_diff_abs_exceed_max_w_range283w(0) OR wire_w_exp_diff_abs_w_range285w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w(0) <= wire_w_exp_diff_abs_exceed_max_w_range287w(0) OR wire_w_exp_diff_abs_w_range288w(0);
wire_w_lg_w_exp_res_not_zero_w_range516w519w(0) <= wire_w_exp_res_not_zero_w_range516w(0) OR wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_not_zero_w_range520w522w(0) <= wire_w_exp_res_not_zero_w_range520w(0) OR wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_not_zero_w_range523w525w(0) <= wire_w_exp_res_not_zero_w_range523w(0) OR wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_not_zero_w_range526w528w(0) <= wire_w_exp_res_not_zero_w_range526w(0) OR wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_not_zero_w_range529w531w(0) <= wire_w_exp_res_not_zero_w_range529w(0) OR wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_not_zero_w_range532w534w(0) <= wire_w_exp_res_not_zero_w_range532w(0) OR wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_not_zero_w_range535w537w(0) <= wire_w_exp_res_not_zero_w_range535w(0) OR wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_not_zero_w_range538w539w(0) <= wire_w_exp_res_not_zero_w_range538w(0) OR wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_man_res_not_zero_w2_range417w420w(0) <= wire_w_man_res_not_zero_w2_range417w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0);
wire_w_lg_w_man_res_not_zero_w2_range448w450w(0) <= wire_w_man_res_not_zero_w2_range448w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0);
wire_w_lg_w_man_res_not_zero_w2_range451w453w(0) <= wire_w_man_res_not_zero_w2_range451w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0);
wire_w_lg_w_man_res_not_zero_w2_range454w456w(0) <= wire_w_man_res_not_zero_w2_range454w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0);
wire_w_lg_w_man_res_not_zero_w2_range457w459w(0) <= wire_w_man_res_not_zero_w2_range457w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0);
wire_w_lg_w_man_res_not_zero_w2_range460w462w(0) <= wire_w_man_res_not_zero_w2_range460w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0);
wire_w_lg_w_man_res_not_zero_w2_range463w465w(0) <= wire_w_man_res_not_zero_w2_range463w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0);
wire_w_lg_w_man_res_not_zero_w2_range466w468w(0) <= wire_w_man_res_not_zero_w2_range466w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0);
wire_w_lg_w_man_res_not_zero_w2_range469w471w(0) <= wire_w_man_res_not_zero_w2_range469w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0);
wire_w_lg_w_man_res_not_zero_w2_range472w474w(0) <= wire_w_man_res_not_zero_w2_range472w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0);
wire_w_lg_w_man_res_not_zero_w2_range475w477w(0) <= wire_w_man_res_not_zero_w2_range475w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0);
wire_w_lg_w_man_res_not_zero_w2_range421w423w(0) <= wire_w_man_res_not_zero_w2_range421w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0);
wire_w_lg_w_man_res_not_zero_w2_range478w480w(0) <= wire_w_man_res_not_zero_w2_range478w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0);
wire_w_lg_w_man_res_not_zero_w2_range481w483w(0) <= wire_w_man_res_not_zero_w2_range481w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0);
wire_w_lg_w_man_res_not_zero_w2_range484w486w(0) <= wire_w_man_res_not_zero_w2_range484w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0);
wire_w_lg_w_man_res_not_zero_w2_range487w489w(0) <= wire_w_man_res_not_zero_w2_range487w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0);
wire_w_lg_w_man_res_not_zero_w2_range424w426w(0) <= wire_w_man_res_not_zero_w2_range424w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0);
wire_w_lg_w_man_res_not_zero_w2_range427w429w(0) <= wire_w_man_res_not_zero_w2_range427w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0);
wire_w_lg_w_man_res_not_zero_w2_range430w432w(0) <= wire_w_man_res_not_zero_w2_range430w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0);
wire_w_lg_w_man_res_not_zero_w2_range433w435w(0) <= wire_w_man_res_not_zero_w2_range433w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0);
wire_w_lg_w_man_res_not_zero_w2_range436w438w(0) <= wire_w_man_res_not_zero_w2_range436w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0);
wire_w_lg_w_man_res_not_zero_w2_range439w441w(0) <= wire_w_man_res_not_zero_w2_range439w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0);
wire_w_lg_w_man_res_not_zero_w2_range442w444w(0) <= wire_w_man_res_not_zero_w2_range442w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0);
wire_w_lg_w_man_res_not_zero_w2_range445w447w(0) <= wire_w_man_res_not_zero_w2_range445w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0);
aclr <= '0';
add_sub_dffe25_wi <= add_sub_w2;
add_sub_dffe25_wo <= add_sub_dffe25_wi;
add_sub_w2 <= (NOT (dataa_sign_dffe1_wo XOR datab_sign_dffe1_wo));
adder_upper_w <= man_intermediate_res_w(25 DOWNTO 13);
aligned_dataa_exp_dffe12_wi <= aligned_dataa_exp_w;
aligned_dataa_exp_dffe12_wo <= aligned_dataa_exp_dffe12;
aligned_dataa_exp_dffe13_wi <= aligned_dataa_exp_dffe12_wo;
aligned_dataa_exp_dffe13_wo <= aligned_dataa_exp_dffe13;
aligned_dataa_exp_dffe14_wi <= aligned_dataa_exp_dffe13_wo;
aligned_dataa_exp_dffe14_wo <= aligned_dataa_exp_dffe14;
aligned_dataa_exp_dffe15_wi <= aligned_dataa_exp_dffe14_wo;
aligned_dataa_exp_dffe15_wo <= aligned_dataa_exp_dffe15;
aligned_dataa_exp_w <= ( "0" & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w);
aligned_dataa_man_dffe12_wi <= aligned_dataa_man_w(25 DOWNTO 2);
aligned_dataa_man_dffe12_wo <= aligned_dataa_man_dffe12;
aligned_dataa_man_dffe13_wi <= aligned_dataa_man_dffe12_wo;
aligned_dataa_man_dffe13_wo <= aligned_dataa_man_dffe13;
aligned_dataa_man_dffe14_wi <= aligned_dataa_man_dffe13_wo;
aligned_dataa_man_dffe14_wo <= aligned_dataa_man_dffe14;
aligned_dataa_man_dffe15_w <= ( aligned_dataa_man_dffe15_wo & "00");
aligned_dataa_man_dffe15_wi <= aligned_dataa_man_dffe14_wo;
aligned_dataa_man_dffe15_wo <= aligned_dataa_man_dffe15;
aligned_dataa_man_w <= ( wire_w248w & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w & "00");
aligned_dataa_sign_dffe12_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe12_wo <= aligned_dataa_sign_dffe12;
aligned_dataa_sign_dffe13_wi <= aligned_dataa_sign_dffe12_wo;
aligned_dataa_sign_dffe13_wo <= aligned_dataa_sign_dffe13;
aligned_dataa_sign_dffe14_wi <= aligned_dataa_sign_dffe13_wo;
aligned_dataa_sign_dffe14_wo <= aligned_dataa_sign_dffe14;
aligned_dataa_sign_dffe15_wi <= aligned_dataa_sign_dffe14_wo;
aligned_dataa_sign_dffe15_wo <= aligned_dataa_sign_dffe15;
aligned_dataa_sign_w <= dataa_dffe11_wo(31);
aligned_datab_exp_dffe12_wi <= aligned_datab_exp_w;
aligned_datab_exp_dffe12_wo <= aligned_datab_exp_dffe12;
aligned_datab_exp_dffe13_wi <= aligned_datab_exp_dffe12_wo;
aligned_datab_exp_dffe13_wo <= aligned_datab_exp_dffe13;
aligned_datab_exp_dffe14_wi <= aligned_datab_exp_dffe13_wo;
aligned_datab_exp_dffe14_wo <= aligned_datab_exp_dffe14;
aligned_datab_exp_dffe15_wi <= aligned_datab_exp_dffe14_wo;
aligned_datab_exp_dffe15_wo <= aligned_datab_exp_dffe15;
aligned_datab_exp_w <= ( "0" & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w);
aligned_datab_man_dffe12_wi <= aligned_datab_man_w(25 DOWNTO 2);
aligned_datab_man_dffe12_wo <= aligned_datab_man_dffe12;
aligned_datab_man_dffe13_wi <= aligned_datab_man_dffe12_wo;
aligned_datab_man_dffe13_wo <= aligned_datab_man_dffe13;
aligned_datab_man_dffe14_wi <= aligned_datab_man_dffe13_wo;
aligned_datab_man_dffe14_wo <= aligned_datab_man_dffe14;
aligned_datab_man_dffe15_w <= ( aligned_datab_man_dffe15_wo & "00");
aligned_datab_man_dffe15_wi <= aligned_datab_man_dffe14_wo;
aligned_datab_man_dffe15_wo <= aligned_datab_man_dffe15;
aligned_datab_man_w <= ( wire_w267w & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w & "00");
aligned_datab_sign_dffe12_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe12_wo <= aligned_datab_sign_dffe12;
aligned_datab_sign_dffe13_wi <= aligned_datab_sign_dffe12_wo;
aligned_datab_sign_dffe13_wo <= aligned_datab_sign_dffe13;
aligned_datab_sign_dffe14_wi <= aligned_datab_sign_dffe13_wo;
aligned_datab_sign_dffe14_wo <= aligned_datab_sign_dffe14;
aligned_datab_sign_dffe15_wi <= aligned_datab_sign_dffe14_wo;
aligned_datab_sign_dffe15_wo <= aligned_datab_sign_dffe15;
aligned_datab_sign_w <= datab_dffe11_wo(31);
borrow_w <= (wire_w_lg_sticky_bit_dffe1_wo343w(0) AND wire_w_lg_add_sub_w2342w(0));
both_inputs_are_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo AND input_datab_infinite_dffe15_wo);
both_inputs_are_infinite_dffe1_wo <= both_inputs_are_infinite_dffe1;
both_inputs_are_infinite_dffe25_wi <= both_inputs_are_infinite_dffe1_wo;
both_inputs_are_infinite_dffe25_wo <= both_inputs_are_infinite_dffe25_wi;
data_exp_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w OR wire_w_lg_exp_amb_mux_dffe15_wo314w);
data_exp_dffe1_wo <= data_exp_dffe1;
dataa_dffe11_wi <= dataa;
dataa_dffe11_wo <= dataa_dffe11_wi;
dataa_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w OR wire_w_lg_exp_amb_mux_dffe15_wo323w);
dataa_man_dffe1_wo <= dataa_man_dffe1;
dataa_sign_dffe1_wi <= aligned_dataa_sign_dffe15_wo;
dataa_sign_dffe1_wo <= dataa_sign_dffe1;
dataa_sign_dffe25_wi <= dataa_sign_dffe1_wo;
dataa_sign_dffe25_wo <= dataa_sign_dffe25_wi;
datab_dffe11_wi <= datab;
datab_dffe11_wo <= datab_dffe11_wi;
datab_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w OR wire_w_lg_exp_amb_mux_dffe15_wo330w);
datab_man_dffe1_wo <= datab_man_dffe1;
datab_sign_dffe1_wi <= aligned_datab_sign_dffe15_wo;
datab_sign_dffe1_wo <= datab_sign_dffe1;
denormal_flag_w <= (((wire_w_lg_force_nan_w630w(0) AND wire_w_lg_force_infinity_w629w(0)) AND wire_w_lg_force_zero_w628w(0)) AND denormal_res_dffe4_wo);
denormal_res_dffe32_wi <= denormal_result_w;
denormal_res_dffe32_wo <= denormal_res_dffe32_wi;
denormal_res_dffe33_wi <= denormal_res_dffe32_wo;
denormal_res_dffe33_wo <= denormal_res_dffe33_wi;
denormal_res_dffe3_wi <= denormal_res_dffe33_wo;
denormal_res_dffe3_wo <= denormal_res_dffe3;
denormal_res_dffe41_wi <= denormal_res_dffe42_wo;
denormal_res_dffe41_wo <= denormal_res_dffe41;
denormal_res_dffe42_wi <= denormal_res_dffe3_wo;
denormal_res_dffe42_wo <= denormal_res_dffe42_wi;
denormal_res_dffe4_wi <= denormal_res_dffe41_wo;
denormal_res_dffe4_wo <= denormal_res_dffe4;
denormal_result_w <= ((NOT exp_res_not_zero_w(8)) OR exp_adjustment2_add_sub_w(8));
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range77w83w & wire_w_lg_w_dataa_range67w73w & wire_w_lg_w_dataa_range57w63w & wire_w_lg_w_dataa_range47w53w & wire_w_lg_w_dataa_range37w43w & wire_w_lg_w_dataa_range27w33w & wire_w_lg_w_dataa_range17w23w & dataa(23));
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range77w78w & wire_w_lg_w_dataa_range67w68w & wire_w_lg_w_dataa_range57w58w & wire_w_lg_w_dataa_range47w48w & wire_w_lg_w_dataa_range37w38w & wire_w_lg_w_dataa_range27w28w & wire_w_lg_w_dataa_range17w18w & dataa(23));
exp_adj_0pads <= (OTHERS => '0');
exp_adj_dffe21_wi <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w OR wire_w383w);
exp_adj_dffe21_wo <= exp_adj_dffe21;
exp_adj_dffe23_wi <= exp_adj_dffe21_wo;
exp_adj_dffe23_wo <= exp_adj_dffe23;
exp_adj_dffe26_wi <= exp_adj_dffe23_wo;
exp_adj_dffe26_wo <= exp_adj_dffe26_wi;
exp_adjust_by_add1 <= "01";
exp_adjust_by_add2 <= "10";
exp_adjustment2_add_sub_dataa_w <= exp_value;
exp_adjustment2_add_sub_datab_w <= exp_adjustment_add_sub_w;
exp_adjustment2_add_sub_w <= wire_add_sub5_result;
exp_adjustment_add_sub_dataa_w <= ( priority_encoder_1pads_w & wire_leading_zeroes_cnt_q);
exp_adjustment_add_sub_datab_w <= ( exp_adj_0pads & exp_adj_dffe26_wo);
exp_adjustment_add_sub_w <= wire_add_sub4_result;
exp_all_ones_w <= (OTHERS => '1');
exp_all_zeros_w <= (OTHERS => '0');
exp_amb_mux_dffe13_wi <= exp_amb_mux_w;
exp_amb_mux_dffe13_wo <= exp_amb_mux_dffe13;
exp_amb_mux_dffe14_wi <= exp_amb_mux_dffe13_wo;
exp_amb_mux_dffe14_wo <= exp_amb_mux_dffe14;
exp_amb_mux_dffe15_wi <= exp_amb_mux_dffe14_wo;
exp_amb_mux_dffe15_wo <= exp_amb_mux_dffe15;
exp_amb_mux_w <= exp_amb_w(8);
exp_amb_w <= wire_add_sub1_result;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range80w85w & wire_w_lg_w_datab_range70w75w & wire_w_lg_w_datab_range60w65w & wire_w_lg_w_datab_range50w55w & wire_w_lg_w_datab_range40w45w & wire_w_lg_w_datab_range30w35w & wire_w_lg_w_datab_range20w25w & datab(23));
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range80w81w & wire_w_lg_w_datab_range70w71w & wire_w_lg_w_datab_range60w61w & wire_w_lg_w_datab_range50w51w & wire_w_lg_w_datab_range40w41w & wire_w_lg_w_datab_range30w31w & wire_w_lg_w_datab_range20w21w & datab(23));
exp_bma_w <= wire_add_sub2_result;
exp_diff_abs_exceed_max_w <= ( wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w & wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w & exp_diff_abs_w(5));
exp_diff_abs_max_w <= (OTHERS => '1');
exp_diff_abs_w <= (wire_w_lg_w_lg_exp_amb_mux_w276w277w OR wire_w_lg_exp_amb_mux_w274w);
exp_intermediate_res_dffe41_wi <= exp_intermediate_res_dffe42_wo;
exp_intermediate_res_dffe41_wo <= exp_intermediate_res_dffe41;
exp_intermediate_res_dffe42_wi <= exp_intermediate_res_w;
exp_intermediate_res_dffe42_wo <= exp_intermediate_res_dffe42_wi;
exp_intermediate_res_w <= exp_res_dffe3_wo;
exp_out_dffe5_wi <= (wire_w_lg_force_nan_w643w OR wire_w_lg_w_lg_force_nan_w630w642w);
exp_out_dffe5_wo <= exp_out_dffe5;
exp_res_dffe21_wi <= exp_res_dffe27_wo;
exp_res_dffe21_wo <= exp_res_dffe21;
exp_res_dffe22_wi <= exp_res_dffe2_wo;
exp_res_dffe22_wo <= exp_res_dffe22_wi;
exp_res_dffe23_wi <= exp_res_dffe21_wo;
exp_res_dffe23_wo <= exp_res_dffe23;
exp_res_dffe25_wi <= data_exp_dffe1_wo;
exp_res_dffe25_wo <= exp_res_dffe25_wi;
exp_res_dffe26_wi <= exp_res_dffe23_wo;
exp_res_dffe26_wo <= exp_res_dffe26_wi;
exp_res_dffe27_wi <= exp_res_dffe22_wo;
exp_res_dffe27_wo <= exp_res_dffe27;
exp_res_dffe2_wi <= exp_res_dffe25_wo;
exp_res_dffe2_wo <= exp_res_dffe2;
exp_res_dffe32_wi <= wire_w_lg_w_lg_denormal_result_w558w559w;
exp_res_dffe32_wo <= exp_res_dffe32_wi;
exp_res_dffe33_wi <= exp_res_dffe32_wo;
exp_res_dffe33_wo <= exp_res_dffe33_wi;
exp_res_dffe3_wi <= exp_res_dffe33_wo;
exp_res_dffe3_wo <= exp_res_dffe3;
exp_res_dffe4_wi <= exp_rounded_res_w;
exp_res_dffe4_wo <= exp_res_dffe4;
exp_res_max_w <= ( wire_w_lg_w_exp_res_max_w_range553w554w & wire_w_lg_w_exp_res_max_w_range551w552w & wire_w_lg_w_exp_res_max_w_range549w550w & wire_w_lg_w_exp_res_max_w_range547w548w & wire_w_lg_w_exp_res_max_w_range545w546w & wire_w_lg_w_exp_res_max_w_range543w544w & wire_w_lg_w_exp_res_max_w_range540w542w & exp_adjustment2_add_sub_w(0));
exp_res_not_zero_w <= ( wire_w_lg_w_exp_res_not_zero_w_range538w539w & wire_w_lg_w_exp_res_not_zero_w_range535w537w & wire_w_lg_w_exp_res_not_zero_w_range532w534w & wire_w_lg_w_exp_res_not_zero_w_range529w531w & wire_w_lg_w_exp_res_not_zero_w_range526w528w & wire_w_lg_w_exp_res_not_zero_w_range523w525w & wire_w_lg_w_exp_res_not_zero_w_range520w522w & wire_w_lg_w_exp_res_not_zero_w_range516w519w & exp_adjustment2_add_sub_w(0));
exp_res_rounding_adder_dataa_w <= ( "0" & exp_intermediate_res_dffe41_wo);
exp_res_rounding_adder_w <= wire_add_sub6_result;
exp_rounded_res_infinity_w <= exp_rounded_res_max_w(7);
exp_rounded_res_max_w <= ( wire_w_lg_w_exp_rounded_res_max_w_range620w622w & wire_w_lg_w_exp_rounded_res_max_w_range617w619w & wire_w_lg_w_exp_rounded_res_max_w_range614w616w & wire_w_lg_w_exp_rounded_res_max_w_range611w613w & wire_w_lg_w_exp_rounded_res_max_w_range608w610w & wire_w_lg_w_exp_rounded_res_max_w_range605w607w & wire_w_lg_w_exp_rounded_res_max_w_range601w604w & exp_rounded_res_w(0));
exp_rounded_res_w <= exp_res_rounding_adder_w(7 DOWNTO 0);
exp_rounding_adjustment_w <= ( "00000000" & man_res_rounding_add_sub_w(24));
exp_value <= ( "0" & exp_res_dffe26_wo);
force_infinity_w <= ((input_is_infinite_dffe4_wo OR rounded_res_infinity_dffe4_wo) OR infinite_res_dffe4_wo);
force_nan_w <= (infinity_magnitude_sub_dffe4_wo OR input_is_nan_dffe4_wo);
force_zero_w <= wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0);
guard_bit_dffe3_wo <= man_res_w3(0);
infinite_output_sign_dffe1_wi <= (wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) OR (input_datab_infinite_dffe15_wo AND aligned_datab_sign_dffe15_wo));
infinite_output_sign_dffe1_wo <= infinite_output_sign_dffe1;
infinite_output_sign_dffe21_wi <= infinite_output_sign_dffe27_wo;
infinite_output_sign_dffe21_wo <= infinite_output_sign_dffe21;
infinite_output_sign_dffe22_wi <= infinite_output_sign_dffe2_wo;
infinite_output_sign_dffe22_wo <= infinite_output_sign_dffe22_wi;
infinite_output_sign_dffe23_wi <= infinite_output_sign_dffe21_wo;
infinite_output_sign_dffe23_wo <= infinite_output_sign_dffe23;
infinite_output_sign_dffe25_wi <= infinite_output_sign_dffe1_wo;
infinite_output_sign_dffe25_wo <= infinite_output_sign_dffe25_wi;
infinite_output_sign_dffe26_wi <= infinite_output_sign_dffe23_wo;
infinite_output_sign_dffe26_wo <= infinite_output_sign_dffe26_wi;
infinite_output_sign_dffe27_wi <= infinite_output_sign_dffe22_wo;
infinite_output_sign_dffe27_wo <= infinite_output_sign_dffe27;
infinite_output_sign_dffe2_wi <= infinite_output_sign_dffe25_wo;
infinite_output_sign_dffe2_wo <= infinite_output_sign_dffe2;
infinite_output_sign_dffe31_wi <= infinite_output_sign_dffe26_wo;
infinite_output_sign_dffe31_wo <= infinite_output_sign_dffe31;
infinite_output_sign_dffe32_wi <= infinite_output_sign_dffe31_wo;
infinite_output_sign_dffe32_wo <= infinite_output_sign_dffe32_wi;
infinite_output_sign_dffe33_wi <= infinite_output_sign_dffe32_wo;
infinite_output_sign_dffe33_wo <= infinite_output_sign_dffe33_wi;
infinite_output_sign_dffe3_wi <= infinite_output_sign_dffe33_wo;
infinite_output_sign_dffe3_wo <= infinite_output_sign_dffe3;
infinite_output_sign_dffe41_wi <= infinite_output_sign_dffe42_wo;
infinite_output_sign_dffe41_wo <= infinite_output_sign_dffe41;
infinite_output_sign_dffe42_wi <= infinite_output_sign_dffe3_wo;
infinite_output_sign_dffe42_wo <= infinite_output_sign_dffe42_wi;
infinite_output_sign_dffe4_wi <= infinite_output_sign_dffe41_wo;
infinite_output_sign_dffe4_wo <= infinite_output_sign_dffe4;
infinite_res_dff32_wi <= wire_w_lg_w_exp_res_max_w_range555w561w(0);
infinite_res_dff32_wo <= infinite_res_dff32_wi;
infinite_res_dff33_wi <= infinite_res_dff32_wo;
infinite_res_dff33_wo <= infinite_res_dff33_wi;
infinite_res_dffe3_wi <= infinite_res_dff33_wo;
infinite_res_dffe3_wo <= infinite_res_dffe3;
infinite_res_dffe41_wi <= infinite_res_dffe42_wo;
infinite_res_dffe41_wo <= infinite_res_dffe41;
infinite_res_dffe42_wi <= infinite_res_dffe3_wo;
infinite_res_dffe42_wo <= infinite_res_dffe42_wi;
infinite_res_dffe4_wi <= infinite_res_dffe41_wo;
infinite_res_dffe4_wo <= infinite_res_dffe4;
infinity_magnitude_sub_dffe21_wi <= infinity_magnitude_sub_dffe27_wo;
infinity_magnitude_sub_dffe21_wo <= infinity_magnitude_sub_dffe21;
infinity_magnitude_sub_dffe22_wi <= infinity_magnitude_sub_dffe2_wo;
infinity_magnitude_sub_dffe22_wo <= infinity_magnitude_sub_dffe22_wi;
infinity_magnitude_sub_dffe23_wi <= infinity_magnitude_sub_dffe21_wo;
infinity_magnitude_sub_dffe23_wo <= infinity_magnitude_sub_dffe23;
infinity_magnitude_sub_dffe26_wi <= infinity_magnitude_sub_dffe23_wo;
infinity_magnitude_sub_dffe26_wo <= infinity_magnitude_sub_dffe26_wi;
infinity_magnitude_sub_dffe27_wi <= infinity_magnitude_sub_dffe22_wo;
infinity_magnitude_sub_dffe27_wo <= infinity_magnitude_sub_dffe27;
infinity_magnitude_sub_dffe2_wi <= (wire_w_lg_add_sub_dffe25_wo491w(0) AND both_inputs_are_infinite_dffe25_wo);
infinity_magnitude_sub_dffe2_wo <= infinity_magnitude_sub_dffe2;
infinity_magnitude_sub_dffe31_wi <= infinity_magnitude_sub_dffe26_wo;
infinity_magnitude_sub_dffe31_wo <= infinity_magnitude_sub_dffe31;
infinity_magnitude_sub_dffe32_wi <= infinity_magnitude_sub_dffe31_wo;
infinity_magnitude_sub_dffe32_wo <= infinity_magnitude_sub_dffe32_wi;
infinity_magnitude_sub_dffe33_wi <= infinity_magnitude_sub_dffe32_wo;
infinity_magnitude_sub_dffe33_wo <= infinity_magnitude_sub_dffe33_wi;
infinity_magnitude_sub_dffe3_wi <= infinity_magnitude_sub_dffe33_wo;
infinity_magnitude_sub_dffe3_wo <= infinity_magnitude_sub_dffe3;
infinity_magnitude_sub_dffe41_wi <= infinity_magnitude_sub_dffe42_wo;
infinity_magnitude_sub_dffe41_wo <= infinity_magnitude_sub_dffe41;
infinity_magnitude_sub_dffe42_wi <= infinity_magnitude_sub_dffe3_wo;
infinity_magnitude_sub_dffe42_wo <= infinity_magnitude_sub_dffe42_wi;
infinity_magnitude_sub_dffe4_wi <= infinity_magnitude_sub_dffe41_wo;
infinity_magnitude_sub_dffe4_wo <= infinity_magnitude_sub_dffe4;
input_dataa_denormal_dffe11_wi <= input_dataa_denormal_w;
input_dataa_denormal_dffe11_wo <= input_dataa_denormal_dffe11_wi;
input_dataa_denormal_w <= ((NOT exp_a_not_zero_w(7)) AND man_a_not_zero_w(22));
input_dataa_infinite_dffe11_wi <= input_dataa_infinite_w;
input_dataa_infinite_dffe11_wo <= input_dataa_infinite_dffe11_wi;
input_dataa_infinite_dffe12_wi <= input_dataa_infinite_dffe11_wo;
input_dataa_infinite_dffe12_wo <= input_dataa_infinite_dffe12;
input_dataa_infinite_dffe13_wi <= input_dataa_infinite_dffe12_wo;
input_dataa_infinite_dffe13_wo <= input_dataa_infinite_dffe13;
input_dataa_infinite_dffe14_wi <= input_dataa_infinite_dffe13_wo;
input_dataa_infinite_dffe14_wo <= input_dataa_infinite_dffe14;
input_dataa_infinite_dffe15_wi <= input_dataa_infinite_dffe14_wo;
input_dataa_infinite_dffe15_wo <= input_dataa_infinite_dffe15;
input_dataa_infinite_w <= wire_w_lg_w_exp_a_all_one_w_range84w220w(0);
input_dataa_nan_dffe11_wi <= input_dataa_nan_w;
input_dataa_nan_dffe11_wo <= input_dataa_nan_dffe11_wi;
input_dataa_nan_dffe12_wi <= input_dataa_nan_dffe11_wo;
input_dataa_nan_dffe12_wo <= input_dataa_nan_dffe12;
input_dataa_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
input_dataa_zero_dffe11_wi <= input_dataa_zero_w;
input_dataa_zero_dffe11_wo <= input_dataa_zero_dffe11_wi;
input_dataa_zero_w <= ((NOT exp_a_not_zero_w(7)) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0));
input_datab_denormal_dffe11_wi <= input_datab_denormal_w;
input_datab_denormal_dffe11_wo <= input_datab_denormal_dffe11_wi;
input_datab_denormal_w <= ((NOT exp_b_not_zero_w(7)) AND man_b_not_zero_w(22));
input_datab_infinite_dffe11_wi <= input_datab_infinite_w;
input_datab_infinite_dffe11_wo <= input_datab_infinite_dffe11_wi;
input_datab_infinite_dffe12_wi <= input_datab_infinite_dffe11_wo;
input_datab_infinite_dffe12_wo <= input_datab_infinite_dffe12;
input_datab_infinite_dffe13_wi <= input_datab_infinite_dffe12_wo;
input_datab_infinite_dffe13_wo <= input_datab_infinite_dffe13;
input_datab_infinite_dffe14_wi <= input_datab_infinite_dffe13_wo;
input_datab_infinite_dffe14_wo <= input_datab_infinite_dffe14;
input_datab_infinite_dffe15_wi <= input_datab_infinite_dffe14_wo;
input_datab_infinite_dffe15_wo <= input_datab_infinite_dffe15;
input_datab_infinite_w <= wire_w_lg_w_exp_b_all_one_w_range86w226w(0);
input_datab_nan_dffe11_wi <= input_datab_nan_w;
input_datab_nan_dffe11_wo <= input_datab_nan_dffe11_wi;
input_datab_nan_dffe12_wi <= input_datab_nan_dffe11_wo;
input_datab_nan_dffe12_wo <= input_datab_nan_dffe12;
input_datab_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
input_datab_zero_dffe11_wi <= input_datab_zero_w;
input_datab_zero_dffe11_wo <= input_datab_zero_dffe11_wi;
input_datab_zero_w <= ((NOT exp_b_not_zero_w(7)) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0));
input_is_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo OR input_datab_infinite_dffe15_wo);
input_is_infinite_dffe1_wo <= input_is_infinite_dffe1;
input_is_infinite_dffe21_wi <= input_is_infinite_dffe27_wo;
input_is_infinite_dffe21_wo <= input_is_infinite_dffe21;
input_is_infinite_dffe22_wi <= input_is_infinite_dffe2_wo;
input_is_infinite_dffe22_wo <= input_is_infinite_dffe22_wi;
input_is_infinite_dffe23_wi <= input_is_infinite_dffe21_wo;
input_is_infinite_dffe23_wo <= input_is_infinite_dffe23;
input_is_infinite_dffe25_wi <= input_is_infinite_dffe1_wo;
input_is_infinite_dffe25_wo <= input_is_infinite_dffe25_wi;
input_is_infinite_dffe26_wi <= input_is_infinite_dffe23_wo;
input_is_infinite_dffe26_wo <= input_is_infinite_dffe26_wi;
input_is_infinite_dffe27_wi <= input_is_infinite_dffe22_wo;
input_is_infinite_dffe27_wo <= input_is_infinite_dffe27;
input_is_infinite_dffe2_wi <= input_is_infinite_dffe25_wo;
input_is_infinite_dffe2_wo <= input_is_infinite_dffe2;
input_is_infinite_dffe31_wi <= input_is_infinite_dffe26_wo;
input_is_infinite_dffe31_wo <= input_is_infinite_dffe31;
input_is_infinite_dffe32_wi <= input_is_infinite_dffe31_wo;
input_is_infinite_dffe32_wo <= input_is_infinite_dffe32_wi;
input_is_infinite_dffe33_wi <= input_is_infinite_dffe32_wo;
input_is_infinite_dffe33_wo <= input_is_infinite_dffe33_wi;
input_is_infinite_dffe3_wi <= input_is_infinite_dffe33_wo;
input_is_infinite_dffe3_wo <= input_is_infinite_dffe3;
input_is_infinite_dffe41_wi <= input_is_infinite_dffe42_wo;
input_is_infinite_dffe41_wo <= input_is_infinite_dffe41;
input_is_infinite_dffe42_wi <= input_is_infinite_dffe3_wo;
input_is_infinite_dffe42_wo <= input_is_infinite_dffe42_wi;
input_is_infinite_dffe4_wi <= input_is_infinite_dffe41_wo;
input_is_infinite_dffe4_wo <= input_is_infinite_dffe4;
input_is_nan_dffe13_wi <= (input_dataa_nan_dffe12_wo OR input_datab_nan_dffe12_wo);
input_is_nan_dffe13_wo <= input_is_nan_dffe13;
input_is_nan_dffe14_wi <= input_is_nan_dffe13_wo;
input_is_nan_dffe14_wo <= input_is_nan_dffe14;
input_is_nan_dffe15_wi <= input_is_nan_dffe14_wo;
input_is_nan_dffe15_wo <= input_is_nan_dffe15;
input_is_nan_dffe1_wi <= input_is_nan_dffe15_wo;
input_is_nan_dffe1_wo <= input_is_nan_dffe1;
input_is_nan_dffe21_wi <= input_is_nan_dffe27_wo;
input_is_nan_dffe21_wo <= input_is_nan_dffe21;
input_is_nan_dffe22_wi <= input_is_nan_dffe2_wo;
input_is_nan_dffe22_wo <= input_is_nan_dffe22_wi;
input_is_nan_dffe23_wi <= input_is_nan_dffe21_wo;
input_is_nan_dffe23_wo <= input_is_nan_dffe23;
input_is_nan_dffe25_wi <= input_is_nan_dffe1_wo;
input_is_nan_dffe25_wo <= input_is_nan_dffe25_wi;
input_is_nan_dffe26_wi <= input_is_nan_dffe23_wo;
input_is_nan_dffe26_wo <= input_is_nan_dffe26_wi;
input_is_nan_dffe27_wi <= input_is_nan_dffe22_wo;
input_is_nan_dffe27_wo <= input_is_nan_dffe27;
input_is_nan_dffe2_wi <= input_is_nan_dffe25_wo;
input_is_nan_dffe2_wo <= input_is_nan_dffe2;
input_is_nan_dffe31_wi <= input_is_nan_dffe26_wo;
input_is_nan_dffe31_wo <= input_is_nan_dffe31;
input_is_nan_dffe32_wi <= input_is_nan_dffe31_wo;
input_is_nan_dffe32_wo <= input_is_nan_dffe32_wi;
input_is_nan_dffe33_wi <= input_is_nan_dffe32_wo;
input_is_nan_dffe33_wo <= input_is_nan_dffe33_wi;
input_is_nan_dffe3_wi <= input_is_nan_dffe33_wo;
input_is_nan_dffe3_wo <= input_is_nan_dffe3;
input_is_nan_dffe41_wi <= input_is_nan_dffe42_wo;
input_is_nan_dffe41_wo <= input_is_nan_dffe41;
input_is_nan_dffe42_wi <= input_is_nan_dffe3_wo;
input_is_nan_dffe42_wo <= input_is_nan_dffe42_wi;
input_is_nan_dffe4_wi <= input_is_nan_dffe41_wo;
input_is_nan_dffe4_wo <= input_is_nan_dffe4;
man_2comp_res_dataa_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_2comp_res_datab_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_2comp_res_w <= ( wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w & wire_man_2comp_res_lower_result);
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range213w214w & wire_w_lg_w_dataa_range207w208w & wire_w_lg_w_dataa_range201w202w & wire_w_lg_w_dataa_range195w196w & wire_w_lg_w_dataa_range189w190w & wire_w_lg_w_dataa_range183w184w & wire_w_lg_w_dataa_range177w178w & wire_w_lg_w_dataa_range171w172w & wire_w_lg_w_dataa_range165w166w & wire_w_lg_w_dataa_range159w160w & wire_w_lg_w_dataa_range153w154w & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_add_sub_dataa_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_add_sub_datab_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_add_sub_res_mag_dffe21_wi <= man_res_mag_w2;
man_add_sub_res_mag_dffe21_wo <= man_add_sub_res_mag_dffe21;
man_add_sub_res_mag_dffe23_wi <= man_add_sub_res_mag_dffe21_wo;
man_add_sub_res_mag_dffe23_wo <= man_add_sub_res_mag_dffe23;
man_add_sub_res_mag_dffe26_wi <= man_add_sub_res_mag_dffe23_wo;
man_add_sub_res_mag_dffe26_wo <= man_add_sub_res_mag_dffe26_wi;
man_add_sub_res_mag_dffe27_wi <= man_add_sub_res_mag_w2;
man_add_sub_res_mag_dffe27_wo <= man_add_sub_res_mag_dffe27;
man_add_sub_res_mag_w2 <= (wire_w_lg_w_man_add_sub_w_range372w379w OR wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w);
man_add_sub_res_sign_dffe21_wo <= man_add_sub_res_sign_dffe21;
man_add_sub_res_sign_dffe23_wi <= man_add_sub_res_sign_dffe21_wo;
man_add_sub_res_sign_dffe23_wo <= man_add_sub_res_sign_dffe23;
man_add_sub_res_sign_dffe26_wi <= man_add_sub_res_sign_dffe23_wo;
man_add_sub_res_sign_dffe26_wo <= man_add_sub_res_sign_dffe26_wi;
man_add_sub_res_sign_dffe27_wi <= man_add_sub_res_sign_w2;
man_add_sub_res_sign_dffe27_wo <= man_add_sub_res_sign_dffe27;
man_add_sub_res_sign_w2 <= (wire_w_lg_need_complement_dffe22_wo376w(0) OR (wire_w_lg_need_complement_dffe22_wo373w(0) AND man_add_sub_w(27)));
man_add_sub_w <= ( wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w & wire_man_add_sub_lower_result);
man_all_zeros_w <= (OTHERS => '0');
man_b_not_zero_w <= ( wire_w_lg_w_datab_range216w217w & wire_w_lg_w_datab_range210w211w & wire_w_lg_w_datab_range204w205w & wire_w_lg_w_datab_range198w199w & wire_w_lg_w_datab_range192w193w & wire_w_lg_w_datab_range186w187w & wire_w_lg_w_datab_range180w181w & wire_w_lg_w_datab_range174w175w & wire_w_lg_w_datab_range168w169w & wire_w_lg_w_datab_range162w163w & wire_w_lg_w_datab_range156w157w & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
man_dffe31_wo <= man_dffe31;
man_intermediate_res_w <= ( "00" & man_res_w3);
man_leading_zeros_cnt_w <= man_leading_zeros_dffe31_wo;
man_leading_zeros_dffe31_wi <= (NOT wire_leading_zeroes_cnt_q);
man_leading_zeros_dffe31_wo <= man_leading_zeros_dffe31;
man_nan_w <= "10000000000000000000000";
man_out_dffe5_wi <= (wire_w_lg_force_nan_w652w OR wire_w_lg_w_lg_force_nan_w630w651w);
man_out_dffe5_wo <= man_out_dffe5;
man_res_dffe4_wi <= man_rounded_res_w;
man_res_dffe4_wo <= man_res_dffe4;
man_res_is_not_zero_dffe31_wi <= man_res_not_zero_dffe26_wo;
man_res_is_not_zero_dffe31_wo <= man_res_is_not_zero_dffe31;
man_res_is_not_zero_dffe32_wi <= man_res_is_not_zero_dffe31_wo;
man_res_is_not_zero_dffe32_wo <= man_res_is_not_zero_dffe32_wi;
man_res_is_not_zero_dffe33_wi <= man_res_is_not_zero_dffe32_wo;
man_res_is_not_zero_dffe33_wo <= man_res_is_not_zero_dffe33_wi;
man_res_is_not_zero_dffe3_wi <= man_res_is_not_zero_dffe33_wo;
man_res_is_not_zero_dffe3_wo <= man_res_is_not_zero_dffe3;
man_res_is_not_zero_dffe41_wi <= man_res_is_not_zero_dffe42_wo;
man_res_is_not_zero_dffe41_wo <= man_res_is_not_zero_dffe41;
man_res_is_not_zero_dffe42_wi <= man_res_is_not_zero_dffe3_wo;
man_res_is_not_zero_dffe42_wo <= man_res_is_not_zero_dffe42_wi;
man_res_is_not_zero_dffe4_wi <= man_res_is_not_zero_dffe41_wo;
man_res_is_not_zero_dffe4_wo <= man_res_is_not_zero_dffe4;
man_res_mag_w2 <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w OR wire_w412w);
man_res_not_zero_dffe23_wi <= man_res_not_zero_w2(24);
man_res_not_zero_dffe23_wo <= man_res_not_zero_dffe23;
man_res_not_zero_dffe26_wi <= man_res_not_zero_dffe23_wo;
man_res_not_zero_dffe26_wo <= man_res_not_zero_dffe26_wi;
man_res_not_zero_w2 <= ( wire_w_lg_w_man_res_not_zero_w2_range487w489w & wire_w_lg_w_man_res_not_zero_w2_range484w486w & wire_w_lg_w_man_res_not_zero_w2_range481w483w & wire_w_lg_w_man_res_not_zero_w2_range478w480w & wire_w_lg_w_man_res_not_zero_w2_range475w477w & wire_w_lg_w_man_res_not_zero_w2_range472w474w & wire_w_lg_w_man_res_not_zero_w2_range469w471w & wire_w_lg_w_man_res_not_zero_w2_range466w468w & wire_w_lg_w_man_res_not_zero_w2_range463w465w & wire_w_lg_w_man_res_not_zero_w2_range460w462w & wire_w_lg_w_man_res_not_zero_w2_range457w459w & wire_w_lg_w_man_res_not_zero_w2_range454w456w & wire_w_lg_w_man_res_not_zero_w2_range451w453w & wire_w_lg_w_man_res_not_zero_w2_range448w450w & wire_w_lg_w_man_res_not_zero_w2_range445w447w & wire_w_lg_w_man_res_not_zero_w2_range442w444w & wire_w_lg_w_man_res_not_zero_w2_range439w441w & wire_w_lg_w_man_res_not_zero_w2_range436w438w & wire_w_lg_w_man_res_not_zero_w2_range433w435w & wire_w_lg_w_man_res_not_zero_w2_range430w432w & wire_w_lg_w_man_res_not_zero_w2_range427w429w & wire_w_lg_w_man_res_not_zero_w2_range424w426w & wire_w_lg_w_man_res_not_zero_w2_range421w423w & wire_w_lg_w_man_res_not_zero_w2_range417w420w & man_add_sub_res_mag_dffe21_wo(1));
man_res_rounding_add_sub_datab_w <= ( "0000000000000000000000000" & man_rounding_add_value_w);
man_res_rounding_add_sub_w <= man_res_rounding_add_sub_result_reg;
man_res_w3 <= wire_lbarrel_shift_result(25 DOWNTO 2);
man_rounded_res_w <= (wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w OR wire_w587w);
man_rounding_add_value_w <= (round_bit_dffe3_wo AND (sticky_bit_dffe3_wo OR guard_bit_dffe3_wo));
man_smaller_dffe13_wi <= man_smaller_w;
man_smaller_dffe13_wo <= man_smaller_dffe13;
man_smaller_w <= (wire_w_lg_exp_amb_mux_w280w OR wire_w_lg_w_lg_exp_amb_mux_w276w279w);
need_complement_dffe22_wi <= need_complement_dffe2_wo;
need_complement_dffe22_wo <= need_complement_dffe22_wi;
need_complement_dffe2_wi <= dataa_sign_dffe25_wo;
need_complement_dffe2_wo <= need_complement_dffe2;
pos_sign_bit_ext <= (OTHERS => '0');
priority_encoder_1pads_w <= (OTHERS => '1');
result <= ( sign_out_dffe5_wo & exp_out_dffe5_wo & man_out_dffe5_wo);
round_bit_dffe21_wi <= round_bit_w;
round_bit_dffe21_wo <= round_bit_dffe21;
round_bit_dffe23_wi <= round_bit_dffe21_wo;
round_bit_dffe23_wo <= round_bit_dffe23;
round_bit_dffe26_wi <= round_bit_dffe23_wo;
round_bit_dffe26_wo <= round_bit_dffe26_wi;
round_bit_dffe31_wi <= round_bit_dffe26_wo;
round_bit_dffe31_wo <= round_bit_dffe31;
round_bit_dffe32_wi <= round_bit_dffe31_wo;
round_bit_dffe32_wo <= round_bit_dffe32_wi;
round_bit_dffe33_wi <= round_bit_dffe32_wo;
round_bit_dffe33_wo <= round_bit_dffe33_wi;
round_bit_dffe3_wi <= round_bit_dffe33_wo;
round_bit_dffe3_wo <= round_bit_dffe3;
round_bit_w <= ((((wire_w397w(0) AND man_add_sub_res_mag_dffe27_wo(0)) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(1))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND man_add_sub_res_mag_dffe27_wo(2))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(2)));
rounded_res_infinity_dffe4_wi <= exp_rounded_res_infinity_w;
rounded_res_infinity_dffe4_wo <= rounded_res_infinity_dffe4;
rshift_distance_dffe13_wi <= rshift_distance_w;
rshift_distance_dffe13_wo <= rshift_distance_dffe13;
rshift_distance_dffe14_wi <= rshift_distance_dffe13_wo;
rshift_distance_dffe14_wo <= rshift_distance_dffe14;
rshift_distance_dffe15_wi <= rshift_distance_dffe14_wo;
rshift_distance_dffe15_wo <= rshift_distance_dffe15;
rshift_distance_w <= (wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w OR wire_w293w);
sign_dffe31_wi <= ((man_res_not_zero_dffe26_wo AND man_add_sub_res_sign_dffe26_wo) OR wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0));
sign_dffe31_wo <= sign_dffe31;
sign_dffe32_wi <= sign_dffe31_wo;
sign_dffe32_wo <= sign_dffe32_wi;
sign_dffe33_wi <= sign_dffe32_wo;
sign_dffe33_wo <= sign_dffe33_wi;
sign_out_dffe5_wi <= (wire_w_lg_force_nan_w630w(0) AND ((force_infinity_w AND infinite_output_sign_dffe4_wo) OR wire_w_lg_w_lg_force_infinity_w629w654w(0)));
sign_out_dffe5_wo <= sign_out_dffe5;
sign_res_dffe3_wi <= sign_dffe33_wo;
sign_res_dffe3_wo <= sign_res_dffe3;
sign_res_dffe41_wi <= sign_res_dffe42_wo;
sign_res_dffe41_wo <= sign_res_dffe41;
sign_res_dffe42_wi <= sign_res_dffe3_wo;
sign_res_dffe42_wo <= sign_res_dffe42_wi;
sign_res_dffe4_wi <= sign_res_dffe41_wo;
sign_res_dffe4_wo <= sign_res_dffe4;
sticky_bit_cnt_dataa_w <= ( "0" & rshift_distance_dffe15_wo);
sticky_bit_cnt_datab_w <= ( "0" & wire_trailing_zeros_cnt_q);
sticky_bit_cnt_res_w <= wire_add_sub3_result;
sticky_bit_dffe1_wi <= wire_trailing_zeros_limit_comparator_agb;
sticky_bit_dffe1_wo <= sticky_bit_dffe1;
sticky_bit_dffe21_wi <= sticky_bit_w;
sticky_bit_dffe21_wo <= sticky_bit_dffe21;
sticky_bit_dffe22_wi <= sticky_bit_dffe2_wo;
sticky_bit_dffe22_wo <= sticky_bit_dffe22_wi;
sticky_bit_dffe23_wi <= sticky_bit_dffe21_wo;
sticky_bit_dffe23_wo <= sticky_bit_dffe23;
sticky_bit_dffe25_wi <= sticky_bit_dffe1_wo;
sticky_bit_dffe25_wo <= sticky_bit_dffe25_wi;
sticky_bit_dffe26_wi <= sticky_bit_dffe23_wo;
sticky_bit_dffe26_wo <= sticky_bit_dffe26_wi;
sticky_bit_dffe27_wi <= sticky_bit_dffe22_wo;
sticky_bit_dffe27_wo <= sticky_bit_dffe27;
sticky_bit_dffe2_wi <= sticky_bit_dffe25_wo;
sticky_bit_dffe2_wo <= sticky_bit_dffe2;
sticky_bit_dffe31_wi <= sticky_bit_dffe26_wo;
sticky_bit_dffe31_wo <= sticky_bit_dffe31;
sticky_bit_dffe32_wi <= sticky_bit_dffe31_wo;
sticky_bit_dffe32_wo <= sticky_bit_dffe32_wi;
sticky_bit_dffe33_wi <= sticky_bit_dffe32_wo;
sticky_bit_dffe33_wo <= sticky_bit_dffe33_wi;
sticky_bit_dffe3_wi <= sticky_bit_dffe33_wo;
sticky_bit_dffe3_wo <= sticky_bit_dffe3;
sticky_bit_w <= (((wire_w_lg_w397w407w(0) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND wire_w_lg_sticky_bit_dffe27_wo402w(0))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1)))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1))));
trailing_zeros_limit_w <= "000010";
zero_man_sign_dffe21_wi <= zero_man_sign_dffe27_wo;
zero_man_sign_dffe21_wo <= zero_man_sign_dffe21;
zero_man_sign_dffe22_wi <= zero_man_sign_dffe2_wo;
zero_man_sign_dffe22_wo <= zero_man_sign_dffe22_wi;
zero_man_sign_dffe23_wi <= zero_man_sign_dffe21_wo;
zero_man_sign_dffe23_wo <= zero_man_sign_dffe23;
zero_man_sign_dffe26_wi <= zero_man_sign_dffe23_wo;
zero_man_sign_dffe26_wo <= zero_man_sign_dffe26_wi;
zero_man_sign_dffe27_wi <= zero_man_sign_dffe22_wo;
zero_man_sign_dffe27_wo <= zero_man_sign_dffe27;
zero_man_sign_dffe2_wi <= (dataa_sign_dffe25_wo AND add_sub_dffe25_wo);
zero_man_sign_dffe2_wo <= zero_man_sign_dffe2;
wire_w_aligned_dataa_exp_dffe15_wo_range315w <= aligned_dataa_exp_dffe15_wo(7 DOWNTO 0);
wire_w_aligned_datab_exp_dffe15_wo_range313w <= aligned_datab_exp_dffe15_wo(7 DOWNTO 0);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range153w(0) <= dataa(12);
wire_w_dataa_range159w(0) <= dataa(13);
wire_w_dataa_range165w(0) <= dataa(14);
wire_w_dataa_range171w(0) <= dataa(15);
wire_w_dataa_range177w(0) <= dataa(16);
wire_w_dataa_range183w(0) <= dataa(17);
wire_w_dataa_range189w(0) <= dataa(18);
wire_w_dataa_range195w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range201w(0) <= dataa(20);
wire_w_dataa_range207w(0) <= dataa(21);
wire_w_dataa_range213w(0) <= dataa(22);
wire_w_dataa_range17w(0) <= dataa(24);
wire_w_dataa_range27w(0) <= dataa(25);
wire_w_dataa_range37w(0) <= dataa(26);
wire_w_dataa_range47w(0) <= dataa(27);
wire_w_dataa_range57w(0) <= dataa(28);
wire_w_dataa_range67w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range77w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_dataa_dffe11_wo_range242w <= dataa_dffe11_wo(22 DOWNTO 0);
wire_w_dataa_dffe11_wo_range232w <= dataa_dffe11_wo(30 DOWNTO 23);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range156w(0) <= datab(12);
wire_w_datab_range162w(0) <= datab(13);
wire_w_datab_range168w(0) <= datab(14);
wire_w_datab_range174w(0) <= datab(15);
wire_w_datab_range180w(0) <= datab(16);
wire_w_datab_range186w(0) <= datab(17);
wire_w_datab_range192w(0) <= datab(18);
wire_w_datab_range198w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range204w(0) <= datab(20);
wire_w_datab_range210w(0) <= datab(21);
wire_w_datab_range216w(0) <= datab(22);
wire_w_datab_range20w(0) <= datab(24);
wire_w_datab_range30w(0) <= datab(25);
wire_w_datab_range40w(0) <= datab(26);
wire_w_datab_range50w(0) <= datab(27);
wire_w_datab_range60w(0) <= datab(28);
wire_w_datab_range70w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range80w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_datab_dffe11_wo_range261w <= datab_dffe11_wo(22 DOWNTO 0);
wire_w_datab_dffe11_wo_range251w <= datab_dffe11_wo(30 DOWNTO 23);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range24w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range34w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range44w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range54w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range64w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range74w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_all_one_w_range84w(0) <= exp_a_all_one_w(7);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range19w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range29w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range39w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range49w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range59w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range69w(0) <= exp_a_not_zero_w(6);
wire_w_exp_adjustment2_add_sub_w_range518w(0) <= exp_adjustment2_add_sub_w(1);
wire_w_exp_adjustment2_add_sub_w_range521w(0) <= exp_adjustment2_add_sub_w(2);
wire_w_exp_adjustment2_add_sub_w_range524w(0) <= exp_adjustment2_add_sub_w(3);
wire_w_exp_adjustment2_add_sub_w_range527w(0) <= exp_adjustment2_add_sub_w(4);
wire_w_exp_adjustment2_add_sub_w_range530w(0) <= exp_adjustment2_add_sub_w(5);
wire_w_exp_adjustment2_add_sub_w_range533w(0) <= exp_adjustment2_add_sub_w(6);
wire_w_exp_adjustment2_add_sub_w_range557w <= exp_adjustment2_add_sub_w(7 DOWNTO 0);
wire_w_exp_adjustment2_add_sub_w_range536w(0) <= exp_adjustment2_add_sub_w(7);
wire_w_exp_adjustment2_add_sub_w_range511w(0) <= exp_adjustment2_add_sub_w(8);
wire_w_exp_amb_w_range275w <= exp_amb_w(7 DOWNTO 0);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range26w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range36w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range46w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range56w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range66w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range76w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_all_one_w_range86w(0) <= exp_b_all_one_w(7);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range22w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range32w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range42w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range52w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range62w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range72w(0) <= exp_b_not_zero_w(6);
wire_w_exp_bma_w_range273w <= exp_bma_w(7 DOWNTO 0);
wire_w_exp_diff_abs_exceed_max_w_range283w(0) <= exp_diff_abs_exceed_max_w(0);
wire_w_exp_diff_abs_exceed_max_w_range287w(0) <= exp_diff_abs_exceed_max_w(1);
wire_w_exp_diff_abs_exceed_max_w_range290w(0) <= exp_diff_abs_exceed_max_w(2);
wire_w_exp_diff_abs_w_range291w <= exp_diff_abs_w(4 DOWNTO 0);
wire_w_exp_diff_abs_w_range285w(0) <= exp_diff_abs_w(6);
wire_w_exp_diff_abs_w_range288w(0) <= exp_diff_abs_w(7);
wire_w_exp_res_max_w_range540w(0) <= exp_res_max_w(0);
wire_w_exp_res_max_w_range543w(0) <= exp_res_max_w(1);
wire_w_exp_res_max_w_range545w(0) <= exp_res_max_w(2);
wire_w_exp_res_max_w_range547w(0) <= exp_res_max_w(3);
wire_w_exp_res_max_w_range549w(0) <= exp_res_max_w(4);
wire_w_exp_res_max_w_range551w(0) <= exp_res_max_w(5);
wire_w_exp_res_max_w_range553w(0) <= exp_res_max_w(6);
wire_w_exp_res_max_w_range555w(0) <= exp_res_max_w(7);
wire_w_exp_res_not_zero_w_range516w(0) <= exp_res_not_zero_w(0);
wire_w_exp_res_not_zero_w_range520w(0) <= exp_res_not_zero_w(1);
wire_w_exp_res_not_zero_w_range523w(0) <= exp_res_not_zero_w(2);
wire_w_exp_res_not_zero_w_range526w(0) <= exp_res_not_zero_w(3);
wire_w_exp_res_not_zero_w_range529w(0) <= exp_res_not_zero_w(4);
wire_w_exp_res_not_zero_w_range532w(0) <= exp_res_not_zero_w(5);
wire_w_exp_res_not_zero_w_range535w(0) <= exp_res_not_zero_w(6);
wire_w_exp_res_not_zero_w_range538w(0) <= exp_res_not_zero_w(7);
wire_w_exp_rounded_res_max_w_range601w(0) <= exp_rounded_res_max_w(0);
wire_w_exp_rounded_res_max_w_range605w(0) <= exp_rounded_res_max_w(1);
wire_w_exp_rounded_res_max_w_range608w(0) <= exp_rounded_res_max_w(2);
wire_w_exp_rounded_res_max_w_range611w(0) <= exp_rounded_res_max_w(3);
wire_w_exp_rounded_res_max_w_range614w(0) <= exp_rounded_res_max_w(4);
wire_w_exp_rounded_res_max_w_range617w(0) <= exp_rounded_res_max_w(5);
wire_w_exp_rounded_res_max_w_range620w(0) <= exp_rounded_res_max_w(6);
wire_w_exp_rounded_res_w_range603w(0) <= exp_rounded_res_w(1);
wire_w_exp_rounded_res_w_range606w(0) <= exp_rounded_res_w(2);
wire_w_exp_rounded_res_w_range609w(0) <= exp_rounded_res_w(3);
wire_w_exp_rounded_res_w_range612w(0) <= exp_rounded_res_w(4);
wire_w_exp_rounded_res_w_range615w(0) <= exp_rounded_res_w(5);
wire_w_exp_rounded_res_w_range618w(0) <= exp_rounded_res_w(6);
wire_w_exp_rounded_res_w_range621w(0) <= exp_rounded_res_w(7);
wire_w_man_a_not_zero_w_range12w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0) <= man_add_sub_res_mag_dffe21_wo(10);
wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0) <= man_add_sub_res_mag_dffe21_wo(11);
wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0) <= man_add_sub_res_mag_dffe21_wo(12);
wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0) <= man_add_sub_res_mag_dffe21_wo(13);
wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0) <= man_add_sub_res_mag_dffe21_wo(14);
wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0) <= man_add_sub_res_mag_dffe21_wo(15);
wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0) <= man_add_sub_res_mag_dffe21_wo(16);
wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0) <= man_add_sub_res_mag_dffe21_wo(17);
wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0) <= man_add_sub_res_mag_dffe21_wo(18);
wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0) <= man_add_sub_res_mag_dffe21_wo(19);
wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0) <= man_add_sub_res_mag_dffe21_wo(20);
wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0) <= man_add_sub_res_mag_dffe21_wo(21);
wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0) <= man_add_sub_res_mag_dffe21_wo(22);
wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0) <= man_add_sub_res_mag_dffe21_wo(23);
wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0) <= man_add_sub_res_mag_dffe21_wo(24);
wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0) <= man_add_sub_res_mag_dffe21_wo(25);
wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0) <= man_add_sub_res_mag_dffe21_wo(2);
wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0) <= man_add_sub_res_mag_dffe21_wo(3);
wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0) <= man_add_sub_res_mag_dffe21_wo(4);
wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0) <= man_add_sub_res_mag_dffe21_wo(5);
wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0) <= man_add_sub_res_mag_dffe21_wo(6);
wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0) <= man_add_sub_res_mag_dffe21_wo(7);
wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0) <= man_add_sub_res_mag_dffe21_wo(8);
wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0) <= man_add_sub_res_mag_dffe21_wo(9);
wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0) <= man_add_sub_res_mag_dffe27_wo(0);
wire_w_man_add_sub_res_mag_dffe27_wo_range411w <= man_add_sub_res_mag_dffe27_wo(25 DOWNTO 0);
wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0) <= man_add_sub_res_mag_dffe27_wo(25);
wire_w_man_add_sub_res_mag_dffe27_wo_range413w <= man_add_sub_res_mag_dffe27_wo(26 DOWNTO 1);
wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) <= man_add_sub_res_mag_dffe27_wo(26);
wire_w_man_add_sub_w_range372w(0) <= man_add_sub_w(27);
wire_w_man_b_not_zero_w_range15w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_w_man_res_not_zero_w2_range417w(0) <= man_res_not_zero_w2(0);
wire_w_man_res_not_zero_w2_range448w(0) <= man_res_not_zero_w2(10);
wire_w_man_res_not_zero_w2_range451w(0) <= man_res_not_zero_w2(11);
wire_w_man_res_not_zero_w2_range454w(0) <= man_res_not_zero_w2(12);
wire_w_man_res_not_zero_w2_range457w(0) <= man_res_not_zero_w2(13);
wire_w_man_res_not_zero_w2_range460w(0) <= man_res_not_zero_w2(14);
wire_w_man_res_not_zero_w2_range463w(0) <= man_res_not_zero_w2(15);
wire_w_man_res_not_zero_w2_range466w(0) <= man_res_not_zero_w2(16);
wire_w_man_res_not_zero_w2_range469w(0) <= man_res_not_zero_w2(17);
wire_w_man_res_not_zero_w2_range472w(0) <= man_res_not_zero_w2(18);
wire_w_man_res_not_zero_w2_range475w(0) <= man_res_not_zero_w2(19);
wire_w_man_res_not_zero_w2_range421w(0) <= man_res_not_zero_w2(1);
wire_w_man_res_not_zero_w2_range478w(0) <= man_res_not_zero_w2(20);
wire_w_man_res_not_zero_w2_range481w(0) <= man_res_not_zero_w2(21);
wire_w_man_res_not_zero_w2_range484w(0) <= man_res_not_zero_w2(22);
wire_w_man_res_not_zero_w2_range487w(0) <= man_res_not_zero_w2(23);
wire_w_man_res_not_zero_w2_range424w(0) <= man_res_not_zero_w2(2);
wire_w_man_res_not_zero_w2_range427w(0) <= man_res_not_zero_w2(3);
wire_w_man_res_not_zero_w2_range430w(0) <= man_res_not_zero_w2(4);
wire_w_man_res_not_zero_w2_range433w(0) <= man_res_not_zero_w2(5);
wire_w_man_res_not_zero_w2_range436w(0) <= man_res_not_zero_w2(6);
wire_w_man_res_not_zero_w2_range439w(0) <= man_res_not_zero_w2(7);
wire_w_man_res_not_zero_w2_range442w(0) <= man_res_not_zero_w2(8);
wire_w_man_res_not_zero_w2_range445w(0) <= man_res_not_zero_w2(9);
wire_w_man_res_rounding_add_sub_w_range584w <= man_res_rounding_add_sub_w(22 DOWNTO 0);
wire_w_man_res_rounding_add_sub_w_range588w <= man_res_rounding_add_sub_w(23 DOWNTO 1);
wire_w_man_res_rounding_add_sub_w_range585w(0) <= man_res_rounding_add_sub_w(24);
lbarrel_shift : add_flt_stratix5_speed_altbarrel_shift_nud
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => man_dffe31_wo,
distance => man_leading_zeros_cnt_w,
result => wire_lbarrel_shift_result
);
wire_rbarrel_shift_data <= ( man_smaller_dffe13_wo & "00");
rbarrel_shift : add_flt_stratix5_speed_altbarrel_shift_u1g
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_rbarrel_shift_data,
distance => rshift_distance_dffe13_wo,
result => wire_rbarrel_shift_result
);
wire_leading_zeroes_cnt_data <= ( man_add_sub_res_mag_dffe21_wo(25 DOWNTO 1) & "1" & "000000");
leading_zeroes_cnt : add_flt_stratix5_speed_altpriority_encoder_ou8
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_leading_zeroes_cnt_data,
q => wire_leading_zeroes_cnt_q
);
wire_trailing_zeros_cnt_data <= ( "111111111" & man_smaller_dffe13_wo(22 DOWNTO 0));
trailing_zeros_cnt : add_flt_stratix5_speed_altpriority_encoder_dna
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_trailing_zeros_cnt_data,
q => wire_trailing_zeros_cnt_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe12 <= aligned_dataa_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe13 <= aligned_dataa_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe14 <= aligned_dataa_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe15 <= aligned_dataa_exp_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe12 <= aligned_dataa_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe13 <= aligned_dataa_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe14 <= aligned_dataa_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe15 <= aligned_dataa_man_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe12 <= aligned_dataa_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe13 <= aligned_dataa_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe14 <= aligned_dataa_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe15 <= aligned_dataa_sign_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe12 <= aligned_datab_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe13 <= aligned_datab_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe14 <= aligned_datab_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe15 <= aligned_datab_exp_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe12 <= aligned_datab_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe13 <= aligned_datab_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe14 <= aligned_datab_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe15 <= aligned_datab_man_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe12 <= aligned_datab_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe13 <= aligned_datab_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe14 <= aligned_datab_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe15 <= aligned_datab_sign_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN data_exp_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN data_exp_dffe1 <= data_exp_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_dffe1 <= dataa_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_dffe1 <= datab_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_sign_dffe1 <= datab_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe3 <= denormal_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe4 <= denormal_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe41 <= denormal_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe21 <= exp_adj_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe23 <= exp_adj_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe13 <= exp_amb_mux_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe14 <= exp_amb_mux_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe15 <= exp_amb_mux_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_intermediate_res_dffe41 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_intermediate_res_dffe41 <= exp_intermediate_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_out_dffe5 <= exp_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe2 <= exp_res_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe21 <= exp_res_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe23 <= exp_res_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe27 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe27 <= exp_res_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe3 <= exp_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe4 <= exp_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe23 <= infinite_output_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe27 <= infinite_output_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe41 <= infinite_output_sign_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe3 <= infinite_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe4 <= infinite_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe41 <= infinite_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe23 <= infinity_magnitude_sub_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe27 <= infinity_magnitude_sub_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe41 <= infinity_magnitude_sub_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe12 <= input_dataa_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe13 <= input_dataa_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe14 <= input_dataa_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe15 <= input_dataa_infinite_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_nan_dffe12 <= input_dataa_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe12 <= input_datab_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe13 <= input_datab_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe14 <= input_datab_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe15 <= input_datab_infinite_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_nan_dffe12 <= input_datab_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe23 <= input_is_infinite_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe27 <= input_is_infinite_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe41 <= input_is_infinite_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe13 <= input_is_nan_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe14 <= input_is_nan_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe15 <= input_is_nan_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe23 <= input_is_nan_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe27 <= input_is_nan_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe41 <= input_is_nan_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe23 <= man_add_sub_res_mag_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe27 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe27 <= man_add_sub_res_mag_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe23 <= man_add_sub_res_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe27 <= man_add_sub_res_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_leading_zeros_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_out_dffe5 <= man_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_dffe4 <= man_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe41 <= man_res_is_not_zero_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_not_zero_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_not_zero_dffe23 <= man_res_not_zero_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_rounding_add_sub_result_reg <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_rounding_add_sub_result_reg <= ( wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w & wire_man_res_rounding_add_sub_lower_result);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_smaller_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_smaller_dffe13 <= man_smaller_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN need_complement_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN need_complement_dffe2 <= need_complement_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe21 <= round_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe23 <= round_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe3 <= round_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe31 <= round_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rounded_res_infinity_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe13 <= rshift_distance_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe14 <= rshift_distance_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe15 <= rshift_distance_dffe15_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe31 <= sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_out_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_out_dffe5 <= sign_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe3 <= sign_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe4 <= sign_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe41 <= sign_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe23 <= sticky_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe27 <= sticky_bit_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe23 <= zero_man_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe27 <= zero_man_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
add_sub1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_dataa_exp_w,
datab => aligned_datab_exp_w,
result => wire_add_sub1_result
);
add_sub2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_datab_exp_w,
datab => aligned_dataa_exp_w,
result => wire_add_sub2_result
);
add_sub3 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
dataa => sticky_bit_cnt_dataa_w,
datab => sticky_bit_cnt_datab_w,
result => wire_add_sub3_result
);
add_sub4 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_adjustment_add_sub_dataa_w,
datab => exp_adjustment_add_sub_datab_w,
result => wire_add_sub4_result
);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_adjustment2_add_sub_dataa_w,
datab => exp_adjustment2_add_sub_datab_w,
result => wire_add_sub5_result
);
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_res_rounding_adder_dataa_w,
datab => exp_rounding_adjustment_w,
result => wire_add_sub6_result
);
loop124 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) <= wire_man_2comp_res_lower_w_lg_cout367w(0) AND wire_man_2comp_res_upper0_result(i);
END GENERATE loop124;
loop125 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_cout366w(i) <= wire_man_2comp_res_lower_cout AND wire_man_2comp_res_upper1_result(i);
END GENERATE loop125;
wire_man_2comp_res_lower_w_lg_cout367w(0) <= NOT wire_man_2comp_res_lower_cout;
loop126 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w(i) <= wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) OR wire_man_2comp_res_lower_w_lg_cout366w(i);
END GENERATE loop126;
man_2comp_res_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_2comp_res_lower_cout,
dataa => man_2comp_res_dataa_w(13 DOWNTO 0),
datab => man_2comp_res_datab_w(13 DOWNTO 0),
result => wire_man_2comp_res_lower_result
);
man_2comp_res_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper0_result
);
man_2comp_res_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper1_result
);
loop127 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) <= wire_man_add_sub_lower_w_lg_cout354w(0) AND wire_man_add_sub_upper0_result(i);
END GENERATE loop127;
loop128 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_cout353w(i) <= wire_man_add_sub_lower_cout AND wire_man_add_sub_upper1_result(i);
END GENERATE loop128;
wire_man_add_sub_lower_w_lg_cout354w(0) <= NOT wire_man_add_sub_lower_cout;
loop129 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w(i) <= wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) OR wire_man_add_sub_lower_w_lg_cout353w(i);
END GENERATE loop129;
man_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_add_sub_lower_cout,
dataa => man_add_sub_dataa_w(13 DOWNTO 0),
datab => man_add_sub_datab_w(13 DOWNTO 0),
result => wire_man_add_sub_lower_result
);
man_add_sub_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper0_result
);
man_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper1_result
);
loop130 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) AND adder_upper_w(i);
END GENERATE loop130;
loop131 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i) <= wire_man_res_rounding_add_sub_lower_cout AND wire_man_res_rounding_add_sub_upper1_result(i);
END GENERATE loop131;
wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) <= NOT wire_man_res_rounding_add_sub_lower_cout;
loop132 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) OR wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i);
END GENERATE loop132;
man_res_rounding_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cout => wire_man_res_rounding_add_sub_lower_cout,
dataa => man_intermediate_res_w(12 DOWNTO 0),
datab => man_res_rounding_add_sub_datab_w(12 DOWNTO 0),
result => wire_man_res_rounding_add_sub_lower_result
);
man_res_rounding_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cin => wire_vcc,
dataa => man_intermediate_res_w(25 DOWNTO 13),
datab => man_res_rounding_add_sub_datab_w(25 DOWNTO 13),
result => wire_man_res_rounding_add_sub_upper1_result
);
trailing_zeros_limit_comparator : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
agb => wire_trailing_zeros_limit_comparator_agb,
dataa => sticky_bit_cnt_res_w,
datab => trailing_zeros_limit_w
);
END RTL; --add_flt_stratix5_speed_altfp_add_sub_jkj
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY add_flt_stratix5_speed IS
PORT
(
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END add_flt_stratix5_speed;
ARCHITECTURE RTL OF add_flt_stratix5_speed IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT add_flt_stratix5_speed_altfp_add_sub_jkj
PORT (
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
add_flt_stratix5_speed_altfp_add_sub_jkj_component : add_flt_stratix5_speed_altfp_add_sub_jkj
PORT MAP (
clk_en => clk_en,
clock => clock,
datab => datab,
dataa => dataa,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "14"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_speed.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_speed.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_speed.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_speed.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_flt_stratix5_speed_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ftl;
use ftl.ftlbase.all;
package myutils is
subtype dfu_opcode_t is std_logic_vector(4 downto 0);
subtype dfu_veclen_t is std_logic_vector(9 downto 0);
subtype raw_dfu_config_t is std_logic_vector(14 downto 0);
type dfu_config_t is record
opcode : dfu_opcode_t; --! DFU command operation code
veclen : dfu_veclen_t; --! vector length
end record;
type dfu_ctrlreg_t is record
cfg : dfu_config_t;
idx : dfu_veclen_t;
p_idx : dfu_veclen_t;
end record;
constant ZERO_dfu_config_t : dfu_config_t := (
opcode => (others => '0'),
veclen => (others => '0')
);
constant ZERO_dfu_ctrlreg_t : dfu_ctrlreg_t := (
cfg => ZERO_dfu_config_t,
idx => (others => '0'), p_idx => (others => '0')
);
constant UNDEF_dfu_ctrlreg_t : dfu_ctrlreg_t := ZERO_dfu_ctrlreg_t;
--
-- counter
function minus(D: std_logic_vector; P: std_ulogic) return std_logic_vector;
function minus(D: std_logic_vector) return std_logic_vector;
function is_nonzero(D: std_logic_vector(7 downto 0)) return std_ulogic;
-- folder
function concat(D1: std_logic_vector; D2: std_logic_vector; P: std_ulogic) return std_logic_vector;
function take_first(D1: std_logic_vector; D2: std_logic_vector; P: std_ulogic) return std_logic_vector;
function adder_stage(DI: std_logic_vector; P: std_ulogic) return std_logic_vector;
function nop1(DI: std_logic_vector; P: std_ulogic) return std_logic_vector;
function nop2(DI: std_logic_vector; P: std_ulogic) return std_logic_vector;
function extend_inp_null(DI: std_logic_vector(31 downto 0); P: std_ulogic) return std_logic_vector;
function give_neutral(ctc: dfu_ctrlreg_t) return std_logic_vector;
function extend_inp_ctr(DA: std_logic_vector(31 downto 0); ctr: dfu_ctrlreg_t; P: std_ulogic) return std_logic_vector;
function init_ctr(DI: raw_dfu_config_t; P: std_ulogic) return dfu_ctrlreg_t;
function update_ctr(DI: dfu_ctrlreg_t; P: std_ulogic) return dfu_ctrlreg_t;
function is_reduction(DI: dfu_ctrlreg_t) return std_ulogic;
function is_continuing(DI: dfu_ctrlreg_t) return std_ulogic;
end;
package body myutils is
function minus(D: std_logic_vector; P: std_ulogic) return std_logic_vector is
constant len : integer := D'length;
variable res : std_logic_vector(len downto 0); -- wider
begin
res := std_logic_vector( to_signed(to_integer(signed(D)) - 1, len+1) );
return res(len-1 downto 0);
end function minus;
function minus(D: std_logic_vector) return std_logic_vector is
constant len : integer := D'length;
variable res : std_logic_vector(len downto 0); -- wider
begin
res := std_logic_vector( to_signed(to_integer(signed(D)) - 1, len+1) );
return res(len-1 downto 0);
end function minus;
function is_nonzero(D: std_logic_vector(7 downto 0)) return std_ulogic is
begin
if D /= zero_std_logic_vector(7, 0) then
return '1';
else
return '0';
end if;
end function is_nonzero;
function concat(D1: std_logic_vector; D2: std_logic_vector; P: std_ulogic) return std_logic_vector is
variable D : std_logic_vector((D1'length + D2'length - 1) downto 0);
begin
D := D1 & D2;
return D;
end function concat;
function take_first(D1: std_logic_vector; D2: std_logic_vector; P: std_ulogic) return std_logic_vector is
begin
return D1;
end function;
function adder_stage(DI: std_logic_vector; P: std_ulogic) return std_logic_vector is
variable DO : std_logic_vector((DI'length/2 -1) downto 0);
variable a, b : integer;
begin
a := to_integer(signed(DI(DI'length-1 downto DI'length/2)));
b := to_integer(signed(DI(DI'length/2-1 downto 0)));
DO := std_logic_vector(to_signed(a + b, DI'length/2));
return DO;
end function adder_stage;
function nop1(DI: std_logic_vector; P: std_ulogic) return std_logic_vector is
begin
return DI;
end function;
function nop2(DI: std_logic_vector; P: std_ulogic) return std_logic_vector is
begin
return DI;
end function;
function extend_inp_null(DI: std_logic_vector(31 downto 0); P: std_ulogic) return std_logic_vector is
variable v : std_logic_vector(41 downto 0);
begin
v := (others => '0');
v(31 downto 0) := DI;
return v;
end function;
function give_neutral(ctc: dfu_ctrlreg_t) return std_logic_vector is
variable v : std_logic_vector(41 downto 0);
begin
-- ctc.cfg.opcode(4 downto 0)
-- RIMmS neutral
-- "00000" add -> 0
-- "00001" sub -> 0
-- "10000" sum -> 0
-- "10011" min -> +inf
-- "10101" max -> -inf
-- "11011" idxmin -> +inf
-- "11101" idxmax -> -inf
v := (others => '0');
if ctc.cfg.opcode(2 downto 1) = "01" then
-- +inf
-- v(31 downto 0) := x"7FFFffff";
v(31 downto 0) := x"7FFF0000";
elsif ctc.cfg.opcode(2 downto 1) = "10" then
-- -inf
-- v(31 downto 0) := x"80000000";
v(31 downto 0) := x"8000ffff";
end if;
-- TODO
--v(31 downto 0) := DI;
return v;
end function;
function extend_inp_ctr(DA: std_logic_vector(31 downto 0); ctr: dfu_ctrlreg_t; P: std_ulogic) return std_logic_vector is
variable v : std_logic_vector(41 downto 0);
begin
v := (others => '0');
v(31 downto 0) := DA;
v(41 downto 32) := ctr.p_idx;
return v;
end function;
function init_ctr(DI: raw_dfu_config_t; P: std_ulogic) return dfu_ctrlreg_t is
variable v : dfu_ctrlreg_t;
begin
v := ZERO_dfu_ctrlreg_t;
v.cfg.opcode := DI(14 downto 10);
v.cfg.veclen := DI(9 downto 0);
return v;
end function;
function update_ctr(DI: dfu_ctrlreg_t; P: std_ulogic) return dfu_ctrlreg_t is
variable v : dfu_ctrlreg_t;
begin
v := DI;
v.p_idx := v.idx;
v.idx := std_logic_vector(to_unsigned( to_integer(unsigned(v.idx)) + 1, dfu_veclen_t'length));
return v;
end function;
function is_reduction(DI: dfu_ctrlreg_t) return std_ulogic is
begin
return DI.cfg.opcode(4);
end function;
function is_continuing(DI: dfu_ctrlreg_t) return std_ulogic is
begin
if DI.cfg.veclen /= DI.idx then
return '1';
else
return '0';
end if;
end function;
end;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00662
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (19)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00662(ARCH00662)
-- ENT00662_Test_Bench(ARCH00662_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all;
entity ENT00662 is
port ( Pt1 : buffer Bit_Vector ;
Pt2 : buffer Integer ) ;
end ENT00662 ;
--
architecture ARCH00662 of ENT00662 is
function To_Real ( P : Integer ) return Real is
begin
if P = -1 then
return -1.0 ;
else
return -2.0 ;
end if ;
end To_Real ;
function To_Integer ( P : Real ) return Integer is
begin
if P = -1.0 then
return -1 ;
else
return -2 ;
end if ;
end To_Integer ;
begin
P2 :
process -- Check formal port on entity (no signal attributes)
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00662" ,
"The predefined attributes of an interface "&
"object (port) of mode 'buffer' for an entity may be read" ,
(Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
) ;
wait ;
end process P2 ;
P3 :
process ( Pt2 ) -- Check formal port on entity (signal attributes)
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
test_report ( "ARCH00662" ,
"The predefined signal attributes of an interface "&
"object (port) of mode 'buffer' for an entity may "&
"be read" ,
(Pt2'DELAYED(10 ns) = -2) and
(Not Pt2'STABLE(10 ns)) and
(Not Pt2'QUIET(10 ns)) and
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = -2)
) ;
end if ;
end process P3 ;
L1 : -- Check block ports/generics
block
port ( Pt1 : buffer Bit_Vector ;
Pt2 : buffer Real ) ;
port map ( Pt1 => Pt1, To_Integer(Pt2) => To_Real(Pt2) ) ;
begin
BP2 :
process -- Check formal port on block (no signal attributes)
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00662" ,
"The predefined attributes of an interface "&
"object (port) of mode 'buffer' for a block may be read" ,
(Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
) ;
wait ;
end process BP2 ;
BP3 :
process ( Pt2 ) -- Check formal port on a block (signal attributes)
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
Pt2 <= transport -1.0 after 10 ns ;
else
test_report ( "ARCH00662" ,
"The predefined signal attributes of an interface "&
"object (port) of mode 'buffer' for a block may be read" ,
(Pt2'DELAYED(10 ns) = real'left) and
(Not Pt2'STABLE(10 ns)) and
(Not Pt2'QUIET(10 ns)) and
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = real'left)
) ;
end if ;
end process BP3 ;
end block L1 ;
end ARCH00662 ;
--
entity ENT00662_Test_Bench is
end ENT00662_Test_Bench ;
architecture ARCH00662_Test_Bench of ENT00662_Test_Bench is
begin
L1:
block
component UUT
end component ;
subtype ST is Bit_Vector ( 10 to 20 ) ;
constant C : ST := B"10101010101" ;
signal S1 : ST := C ;
signal S2 : Integer := -2 ;
for CIS1 : UUT use entity WORK.ENT00662 ( ARCH00662 )
port map ( S1, S2 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00662_Test_Bench ;
--
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( clk_raw : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (7 downto 0);
leds : out STD_LOGIC_VECTOR (7 downto 0);
VGA_DATA : out STD_LOGIC_VECTOR (11 downto 0);
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC
);
end top;
architecture Behavioral of top is
constant horz : integer := 5;
signal clk_100MHz: std_logic;
signal clk_193MHz: std_logic;
signal clk_250MHz: std_logic;
signal sw_buffer: std_logic_vector(7 downto 0);
signal hscnt: std_logic_vector(11 downto 0);
signal vscnt: std_logic_vector(11 downto 0);
signal data: std_logic_vector(11 downto 0):= (others=>'0');
signal addra: std_logic_vector(10 downto 0);
signal addrb: std_logic_vector(10 downto 0);
signal dina: std_logic_vector(15 downto 0);
signal doutb: std_logic_vector(15 downto 0);
alias sine:std_logic_vector(7 downto 0) is doutb(7 downto 0);
signal s_axis_config_tdata: std_logic_vector(7 downto 0);
signal phase: std_logic_vector(31 downto 0);
signal m_axis_data_tdata: std_logic_vector(7 downto 0);
signal m_last: std_logic_vector(7 downto 0);
signal valid: std_logic;
signal write: std_logic;
signal fpulse: std_logic;
signal vga_fpulse: std_logic;
signal saved: std_logic;
signal timer : std_logic_vector(5 downto 0);
signal sine_signed : signed (7 downto 0);
signal last: signed (7 downto 0);
signal y: signed (11 downto 0);
component clk_base is
port (
clk_raw : in STD_LOGIC;
clk_250MHz : out STD_LOGIC;
clk_100MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
component clk_video is
port (
clk_100MHz : in STD_LOGIC;
clk_193MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
COMPONENT bram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- COMPONENT dds
-- PORT (
-- aclk : IN STD_LOGIC;
-- s_axis_phase_tvalid : IN STD_LOGIC;
-- s_axis_phase_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- m_axis_data_tvalid : OUT STD_LOGIC;
-- m_axis_data_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-- );
-- END COMPONENT;
COMPONENT dds
PORT (
aclk : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
begin
clk_base1: clk_base port map(clk_raw, clk_250MHz, clk_100MHz, open);
clk_video1: clk_video port map(clk_100MHz, clk_193MHz, open);
vga1: vga generic map(
Hsync=> 112,
Hact=> 1280,
Hfp=>48,
Hbp=>248,
Vsync=>3,
Vact=> 1024,
Vfp=> 1,
Vbp=> 38
) port map( clk_193MHz, hscnt,vscnt,VGA_HSYNC, VGA_VSYNC,vga_fpulse);
bram_disp: bram
PORT MAP (
clka => clk_250MHz,
wea(0) => '1',
addra => addra,
dina => dina,
clkb => clk_193MHz,
addrb => addrb,
doutb => doutb
);
-- sig_gen: dds
-- PORT MAP (
-- aclk => clk_250MHz,
-- s_axis_phase_tvalid => '1',
-- s_axis_phase_tdata => addra(7 downto 0),
-- m_axis_data_tvalid => valid,
-- m_axis_data_tdata => m_axis_data_tdata
-- );
sig_gen: dds
PORT MAP (
aclk => clk_250MHz,
m_axis_data_tvalid => valid,
m_axis_data_tdata => m_axis_data_tdata
);
--sine_gen: dds
--PORT MAP (
-- aclk => clk_250MHz,
-- s_axis_config_tvalid => '1',
-- s_axis_config_tdata => s_axis_config_tdata,
-- m_axis_data_tvalid => valid,
-- m_axis_data_tdata => m_axis_data_tdata,
-- m_axis_phase_tvalid => open,
-- m_axis_phase_tdata => phase
--);
y <= 511-signed(vscnt);
sine_signed <= signed(sine);
--s_axis_config_tdata(31 downto 1) <= (others=>'0');
--s_axis_config_tdata(0) <= '1';
--addrb <= (others=>'0');
--dina(15 downto 0) <= (others=>'0');
--dina(7 downto 0) <= m_axis_data_tdata;
--s_axis_config_tdata <= "000000000000000000000000"&sw;
--dina <= y ;
addrb <= hscnt(10 downto 0);
dina(15 downto 8) <= (others=>'0');
--std_logic_vector(to_signed(10,11));
process(clk_250MHz) begin
if(clk_250MHz'event and clk_250MHz='1')then
sw_buffer <= sw;
leds <= sw_buffer;
s_axis_config_tdata <= sw_buffer;
end if;
end process;
process(clk_250MHz) begin
if(clk_250MHz'event and clk_250MHz='1')then
--if(valid = '1' and timer > sw_buffer)then
--timer <= (others=>'0');
-- write <= '1';
if(sw_buffer(0) = '1')then
m_last <= dina(7 downto 0);
dina(7 downto 0) <= m_axis_data_tdata;
if(addra < 1024)then
addra <= addra+1;
--else
-- addra <= (others=>'0');
end if;
end if;
-- end if;
-- timer <= timer + 1;
--if(write = '1')then
-- write <= '0';
-- end if;
if(addra >= 1024 and signed(dina(7 downto 0)) >= 0 and signed(m_last) <= 0 )then
addra <= (others=>'0');
end if;
end if;
end process;
process(clk_193MHz) begin
if(clk_193MHz'event and clk_193MHz='1')then
if( hscnt < 1280 and vscnt < 1024)then
VGA_DATA <= data;
else
VGA_DATA <= (others=>'0');
end if;
if (vscnt = 512 or hscnt = 0)then
data <= X"07F";
elsif( (hscnt = 128) or (hscnt = 256) or (hscnt = 384) or (hscnt = 512) or (hscnt = 640) or (hscnt = 768) or (hscnt = 896) or (hscnt = 1024) or (hscnt = 1152) or (hscnt = 1280-1)) then
data <= X"0F0";
elsif((vscnt = 0) or (vscnt = 128) or (vscnt = 256) or (vscnt = 384) or (vscnt = 640) or (vscnt = 768) or (vscnt = 896) or (vscnt = 1024-1)) then
data <= X"0F0";
elsif((sine_signed > last and y > last and y < sine_signed) or sine_signed = y or (sine_signed < last and y < last and y > sine_signed) )then --or (doutb < last and vscnt < last and vscnt > doutb)
data <= X"FFF";
elsif(y = sine_signed)then
data <= X"FFF";
else
data <= X"000";
end if;
last <= sine_signed;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 25.04.2017 17:45:32
-- Design Name: VMM Driver
-- Module Name: vmm_driver - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484
-- Tool Versions: Vivado 2016.4
-- Description: This module drives the data from the vmm_readout component
-- to the FIFO2UDP component.
--
-- Dependencies: packet_formation.vhd
--
-- Changelog:
-- 06.06.2017 Simplified the module as the continuous readout mode now uses a buffer
-- as well. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity vmm_driver is
port(
------------------------------------
------ General/PF Interface --------
clk : in std_logic;
drv_enable : in std_logic;
drv_done : out std_logic;
pack_len_drv : out std_logic_vector(11 downto 0);
------------------------------------
----- VMM_RO/FIFO2UDP Interface ----
wr_en_fifo2udp : out std_logic;
rd_en_buff : out std_logic;
vmmWordReady : in std_logic
);
end vmm_driver;
architecture RTL of vmm_driver is
signal wait_cnt : integer range 0 to 15 := 0;
signal packLen_i : unsigned(11 downto 0) := (others => '0');
constant timeout : integer := 15;
type stateType_l0 is (ST_IDLE, ST_WAIT, ST_CHECK_FIFO, ST_RD_LOW, ST_WR_LOW, ST_DONE);
signal state_l0 : stateType_l0 := ST_IDLE;
begin
l0_FSM_drv: process(clk)
begin
if(rising_edge(clk))then
if(drv_enable = '0')then
drv_done <= '0';
wait_cnt <= 0;
rd_en_buff <= '0';
wr_en_fifo2udp <= '0';
packLen_i <= (others => '0');
state_l0 <= ST_IDLE;
else
case state_l0 is
-- reset the counter and begin the process
when ST_IDLE =>
packLen_i <= (others => '0');
state_l0 <= ST_WAIT;
-- stay here for "timeout" cycles for data bus stabilization
when ST_WAIT =>
if(wait_cnt < timeout)then
wait_cnt <= wait_cnt + 1;
state_l0 <= ST_WAIT;
else
wait_cnt <= 0;
state_l0 <= ST_CHECK_FIFO;
end if;
-- read the vmm buffer if there is still data
when ST_CHECK_FIFO =>
if(vmmWordReady = '1')then
rd_en_buff <= '1';
state_l0 <= ST_RD_LOW;
else
rd_en_buff <= '0';
state_l0 <= ST_DONE;
end if;
-- stay here for "timeout" cycles for data bus stabilization
when ST_RD_LOW =>
rd_en_buff <= '0';
if(wait_cnt < timeout)then
wait_cnt <= wait_cnt + 1;
wr_en_fifo2udp <= '0';
state_l0 <= ST_RD_LOW;
else
wait_cnt <= 0;
wr_en_fifo2udp <= '1';
state_l0 <= ST_WR_LOW;
end if;
-- increment the packLen counter
when ST_WR_LOW =>
wr_en_fifo2udp <= '0';
packLen_i <= packLen_i + 1;
state_l0 <= ST_WAIT;
-- stay here until reset by pf
when ST_DONE =>
drv_done <= '1';
when others =>
drv_done <= '0';
wait_cnt <= 0;
rd_en_buff <= '0';
wr_en_fifo2udp <= '0';
packLen_i <= (others => '0');
state_l0 <= ST_IDLE;
end case;
end if;
end if;
end process;
pack_len_drv <= std_logic_vector(packLen_i);
end RTL; |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF transmitter component package. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/07/14 17:58:49 gedra
-- Added new components.
--
-- Revision 1.1 2004/07/13 18:30:25 gedra
-- Transmitter component declarations.
--
--
--
library ieee;
use ieee.std_logic_1164.all;
package tx_package is
component tx_encoder
generic
(
DATA_WIDTH: integer range 16 to 32 := 32
);
port
(
up_clk: in std_logic; -- clock
data_clk : in std_logic; -- data clock
resetn : in std_logic; -- resetn
conf_mode: in std_logic_vector(3 downto 0); -- sample format
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
conf_txdata: in std_logic; -- sample data enable
conf_txen: in std_logic; -- spdif signal enable
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
chstat_gstat: in std_logic; -- generation status
chstat_preem: in std_logic; -- preemphasis status
chstat_copy: in std_logic; -- copyright bit
chstat_audio: in std_logic; -- data format
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
sample_data_ack : out std_logic; -- sample buffer read
channel: out std_logic;
spdif_tx_o: out std_logic
);
end component;
end tx_package;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF transmitter component package. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/07/14 17:58:49 gedra
-- Added new components.
--
-- Revision 1.1 2004/07/13 18:30:25 gedra
-- Transmitter component declarations.
--
--
--
library ieee;
use ieee.std_logic_1164.all;
package tx_package is
component tx_encoder
generic
(
DATA_WIDTH: integer range 16 to 32 := 32
);
port
(
up_clk: in std_logic; -- clock
data_clk : in std_logic; -- data clock
resetn : in std_logic; -- resetn
conf_mode: in std_logic_vector(3 downto 0); -- sample format
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
conf_txdata: in std_logic; -- sample data enable
conf_txen: in std_logic; -- spdif signal enable
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
chstat_gstat: in std_logic; -- generation status
chstat_preem: in std_logic; -- preemphasis status
chstat_copy: in std_logic; -- copyright bit
chstat_audio: in std_logic; -- data format
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
sample_data_ack : out std_logic; -- sample buffer read
channel: out std_logic;
spdif_tx_o: out std_logic
);
end component;
end tx_package;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF transmitter component package. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/07/14 17:58:49 gedra
-- Added new components.
--
-- Revision 1.1 2004/07/13 18:30:25 gedra
-- Transmitter component declarations.
--
--
--
library ieee;
use ieee.std_logic_1164.all;
package tx_package is
component tx_encoder
generic
(
DATA_WIDTH: integer range 16 to 32 := 32
);
port
(
up_clk: in std_logic; -- clock
data_clk : in std_logic; -- data clock
resetn : in std_logic; -- resetn
conf_mode: in std_logic_vector(3 downto 0); -- sample format
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
conf_txdata: in std_logic; -- sample data enable
conf_txen: in std_logic; -- spdif signal enable
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
chstat_gstat: in std_logic; -- generation status
chstat_preem: in std_logic; -- preemphasis status
chstat_copy: in std_logic; -- copyright bit
chstat_audio: in std_logic; -- data format
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
sample_data_ack : out std_logic; -- sample buffer read
channel: out std_logic;
spdif_tx_o: out std_logic
);
end component;
end tx_package;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF transmitter component package. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/07/14 17:58:49 gedra
-- Added new components.
--
-- Revision 1.1 2004/07/13 18:30:25 gedra
-- Transmitter component declarations.
--
--
--
library ieee;
use ieee.std_logic_1164.all;
package tx_package is
component tx_encoder
generic
(
DATA_WIDTH: integer range 16 to 32 := 32
);
port
(
up_clk: in std_logic; -- clock
data_clk : in std_logic; -- data clock
resetn : in std_logic; -- resetn
conf_mode: in std_logic_vector(3 downto 0); -- sample format
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
conf_txdata: in std_logic; -- sample data enable
conf_txen: in std_logic; -- spdif signal enable
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
chstat_gstat: in std_logic; -- generation status
chstat_preem: in std_logic; -- preemphasis status
chstat_copy: in std_logic; -- copyright bit
chstat_audio: in std_logic; -- data format
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
sample_data_ack : out std_logic; -- sample buffer read
channel: out std_logic;
spdif_tx_o: out std_logic
);
end component;
end tx_package;
|
library IEEE;
use ieee.std_logic_1164.all;
-- ENTITY
entity FSMctrl is
port(
CLK, RST, ENTER: in std_logic;
Operacao: in std_logic_vector(1 downto 0);
Selecao: out std_logic_vector(1 downto 0);
Enable_1, Enable_2: out std_logic
);
end FSMctrl;
--ARCHITECTURE
architecture FSM_beh of FSMctrl is
type states is(S0,S1,S2,S3,S4,S5,S6,S7);
signal EA, PE: states;
signal clock: std_logic;
signal reset: std_logic;
begin
clock <= CLK;
P1: process(clock, reset)
begin
if reset = '0' then
EA <= S0;
elsif clock'event and clock = '1' then
EA <= PE;
end if;
end process;
P2: process(EA, ENTER, Operacao)
begin
case EA is
when S0 =>
if Enter = '1' then
PE <= S0;
else
PE <= S1;
end if;
Enable_1 <= '0';
Enable_2 <= '0';
when S1 =>
if Enter = '0' then
PE <= S1;
else
PE <= S2;
end if;
Enable_1 <= '1';
Enable_2 <= '0';
when S2 =>
Enable_1 <= '0';
Enable_2 <= '0';
if Operacao = "00" then
PE <= S3;
elsif Operacao = "01" then
PE <= S4;
elsif Operacao = "10" then
PE <= S5;
elsif Operacao = "11" then
PE <= S6;
end if;
when S3 =>
Selecao <= "00";
if Enter = '1' then
PE <= S3;
else
PE <= S7;
end if;
when S4 =>
Selecao <= "01";
if Enter = '1' then
PE <= S4;
else
PE <= S7;
end if;
when S5 =>
Selecao <= "10";
if Enter = '1' then
PE <= S5;
else
PE <= S7;
end if;
when S6 =>
Enable_1 <= '0';
Enable_2 <= '1';
Selecao <= "11";
PE <= S0;
when S7 =>
Enable_1 <= '0';
Enable_2 <= '1';
PE <= S0;
end case;
end process;
end FSM_beh;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
library work;
use work.i2c_arb_pkg.all;
ENTITY testbench_i2c_arbiter IS
END testbench_i2c_arbiter;
ARCHITECTURE behavior OF testbench_i2c_arbiter IS
signal clk : std_logic := '0';
signal reset : std_logic := '1'; -- low-level active
constant clk_period : time := 16 ns; -- 62.5 MHz
constant c_num_i2c_inputs : integer := 2;
signal input_sda_i : std_logic_vector(c_num_i2c_inputs-1 downto 0);
signal input_sda_o : std_logic_vector(c_num_i2c_inputs-1 downto 0);
signal input_scl_i : std_logic_vector(c_num_i2c_inputs-1 downto 0);
signal input_scl_o : std_logic_vector(c_num_i2c_inputs-1 downto 0);
--signal output_sda_i : std_logic;
signal output_sda_o : std_logic;
--signal output_scl_i : std_logic;
signal output_scl_o : std_logic;
BEGIN
uut: wb_i2c_arbiter
generic map(
g_num_inputs => c_num_i2c_inputs
)
port map (
clk_i => clk,
rst_n_i => reset,
input_sda_i => input_sda_i,
input_sda_o => input_sda_o,
input_scl_i => input_scl_i,
input_scl_o => input_scl_o,
output_sda_i => output_sda_o,
output_sda_o => output_sda_o,
output_scl_i => output_scl_o,
output_scl_o => output_scl_o,
wb_adr_i => (others => '0'),
wb_dat_i => (others => '0'),
wb_dat_o => open,
wb_cyc_i => '0',
wb_sel_i => (others => '0'),
wb_stb_i => '0',
wb_we_i => '0',
wb_ack_o => open,
wb_stall_o => open
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <='0'; -- reset!
wait for 3 ns;
reset <='1';
input_sda_i(0) <= '1';
input_scl_i(0) <= '1';
input_sda_i(1) <= '1';
input_scl_i(1) <= '1';
wait for 250 ns;
input_sda_i(0) <= '0';
wait for 250ns;
input_scl_i(0) <= '0';
wait for 250 ns;
input_scl_i(0) <= '1';
wait for 250 ns;
input_scl_i(0) <= '0';
wait for 250 ns;
input_scl_i(0) <= '1';
wait for 250 ns;
input_scl_i(0) <= '0';
wait for 250 ns;
input_scl_i(0) <= '1';
wait for 250 ns;
input_sda_i(0) <= '1';
wait;
end process;
END;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
dpra : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
spo : out std_logic_vector(NBIT-1 downto 0 );
dpo : out std_logic_vector(NBIT-1 downto 0 )
);
end dpram_NxN;
architecture behavioral of dpram_NxN is
type ram_type is array (0 to (SIZE - 1)) of std_logic_vector(NBIT-1 downto 0 );
signal RAM : ram_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(a)) <= di;
end if;
spo <= RAM(conv_integer(a));
dpo <= RAM(conv_integer(dpra));
end if;
end process;
end behavioral ; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
dpra : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
spo : out std_logic_vector(NBIT-1 downto 0 );
dpo : out std_logic_vector(NBIT-1 downto 0 )
);
end dpram_NxN;
architecture behavioral of dpram_NxN is
type ram_type is array (0 to (SIZE - 1)) of std_logic_vector(NBIT-1 downto 0 );
signal RAM : ram_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(a)) <= di;
end if;
spo <= RAM(conv_integer(a));
dpo <= RAM(conv_integer(dpra));
end if;
end process;
end behavioral ; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity threshold is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end threshold;
architecture rtl of threshold is
component threshold_process
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
threshold_reg : in std_logic_vector(31 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component threshold_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
threshold_reg : out std_logic_vector(31 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal threshold_reg : std_logic_vector (31 downto 0);
begin
threshold_process_inst : threshold_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
threshold_reg => threshold_reg,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
threshold_slave_inst : threshold_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
threshold_reg => threshold_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
port(
clk: in std_logic;
resend: in std_logic;
config_finished : out std_logic;
sioc: out std_logic;
siod: inout std_logic;
reset: out std_logic;
pwdn: out std_logic;
xclk: out std_logic
);
end ov7670_controller;
architecture Structural of ov7670_controller is
component ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end component;
component i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end component;
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender port map(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
Inst_ov7670_registers: ov7670_registers port map(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
end Structural; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
port(
clk: in std_logic;
resend: in std_logic;
config_finished : out std_logic;
sioc: out std_logic;
siod: inout std_logic;
reset: out std_logic;
pwdn: out std_logic;
xclk: out std_logic
);
end ov7670_controller;
architecture Structural of ov7670_controller is
component ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end component;
component i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end component;
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender port map(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
Inst_ov7670_registers: ov7670_registers port map(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
end Structural; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
port(
clk: in std_logic;
resend: in std_logic;
config_finished : out std_logic;
sioc: out std_logic;
siod: inout std_logic;
reset: out std_logic;
pwdn: out std_logic;
xclk: out std_logic
);
end ov7670_controller;
architecture Structural of ov7670_controller is
component ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end component;
component i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end component;
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender port map(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
Inst_ov7670_registers: ov7670_registers port map(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
end Structural; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
port(
clk: in std_logic;
resend: in std_logic;
config_finished : out std_logic;
sioc: out std_logic;
siod: inout std_logic;
reset: out std_logic;
pwdn: out std_logic;
xclk: out std_logic
);
end ov7670_controller;
architecture Structural of ov7670_controller is
component ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end component;
component i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end component;
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender port map(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
Inst_ov7670_registers: ov7670_registers port map(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
end Structural; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
port(
clk: in std_logic;
resend: in std_logic;
config_finished : out std_logic;
sioc: out std_logic;
siod: inout std_logic;
reset: out std_logic;
pwdn: out std_logic;
xclk: out std_logic
);
end ov7670_controller;
architecture Structural of ov7670_controller is
component ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end component;
component i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end component;
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender port map(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
Inst_ov7670_registers: ov7670_registers port map(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
end Structural; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
port(
clk: in std_logic;
resend: in std_logic;
config_finished : out std_logic;
sioc: out std_logic;
siod: inout std_logic;
reset: out std_logic;
pwdn: out std_logic;
xclk: out std_logic
);
end ov7670_controller;
architecture Structural of ov7670_controller is
component ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end component;
component i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end component;
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender port map(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
Inst_ov7670_registers: ov7670_registers port map(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
end Structural; |
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
reset_o1 : out std_ulogic;
reset_o2 : out std_ulogic;
clk27 : in std_ulogic;
clk200_p : in std_ulogic;
clk200_n : in std_ulogic;
errorn : out std_ulogic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(7 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(23 downto 0);
-- pragma translate_on
-- DDR2 memory
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_we : out std_ulogic; -- write enable
ddr_ras : out std_ulogic; -- ras
ddr_cas : out std_ulogic; -- cas
ddr_dm : out std_logic_vector(1 downto 0); -- dm
ddr_dqs : inout std_logic_vector(1 downto 0); -- dqs
ddr_dqsn : inout std_logic_vector(1 downto 0); -- dqsn
ddr_ad : out std_logic_vector(12 downto 0); -- address
ddr_ba : out std_logic_vector(2 downto 0); -- bank address
ddr_dq : inout std_logic_vector(15 downto 0); -- data
ddr_odt : out std_logic;
ddr_rzq : inout std_logic;
ddr_zio : inout std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
-- SPI flash
-- spi_sel_n : inout std_ulogic;
-- spi_clk : out std_ulogic;
-- spi_mosi : out std_ulogic;
-- Output signals to LEDs
led : out std_logic_vector(2 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal ddr_clk_fb_out : std_logic;
signal ddr_clk_fb : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 27000; -- CLK input frequency in KHz
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
-- Glitch free reset that can be used for the Eth Phy and flash memory
reset_o1 <= rstn;
reset_o2 <= rstn;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk27_pad : clkpad generic map (tech => padtech) port map (clk27, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8, devid => XILINX_SP601)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "00";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 24)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : iopadv generic map (tech => padtech, width => 24)
port map (testdata(23 downto 0), memo.data(23 downto 0),
memo.bdrive(1), memi.data(23 downto 0));
-- pragma translate_on
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2sp0 : if (CFG_DDR2SP /= 0) generate
clk200_pad : inpad_ds generic map (tech => padtech, voltage => x25v)
port map (clk200_p, clk200_n, lclk200);
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR2_FREQ/1000, clkmul => 5, clkdiv => 8,
TRFC => CFG_DDR2SP_TRFC,
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
ddrbits => 16, eightbanks => 1, odten => 0)
port map ( cgo.clklock, rstn, lclk200, clkm, vcc, lock, clkml, clkml, ahbsi, ahbso(4),
core_ddr_clk, core_ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, core_ddr_cke,
core_ddr_csb, ddr_we, ddr_ras, ddr_cas, ddr_dm, ddr_dqs, ddr_dqsn,
core_ddr_ad, ddr_ba, ddr_dq, core_ddr_odt);
ddr_clk <= core_ddr_clk(0);
ddr_clkb <= core_ddr_clkb(0);
ddr_cke <= core_ddr_cke(0);
ddr_ad <= core_ddr_ad(12 downto 0);
ddr_odt <= core_ddr_odt(0);
end generate;
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_sp601 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => clk200_n,
clk_mem_p => clk200_p,
test_error => open
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
-- spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
-- spimctrl0 : spimctrl -- SPI Memory Controller
-- generic map (hindex => 7, hirq => 11, faddr => 16#e00#, fmask => 16#ff8#,
-- ioaddr => 16#002#, iomask => 16#fff#,
-- spliten => CFG_SPLIT, oepol => 0,
-- sdcard => CFG_SPIMCTRL_SDCARD,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
-- scaler => CFG_SPIMCTRL_SCALER,
-- altscaler => CFG_SPIMCTRL_ASCALER,
-- pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
-- port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
--
-- -- MISO is shared with Flash data 0
-- spmi.miso <= memi.data(24);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, spmo.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spmo.sck);
-- slvsel0_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, spmo.csn);
-- end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
-- spi1 : spictrl
-- generic map (pindex => 7, paddr => 7, pmask => 16#fff#, pirq => 11,
-- fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
-- slvselsz => CFG_SPICTRL_SLVS, odmode => 0)
-- port map (rstn, clkm, apbi, apbo(7), spii, spio, slvsel);
-- spii.spisel <= '1'; -- Master only
-- -- MISO is shared with Flash data 0
-- spii.miso <= memi.data(24);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, spio.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spio.sck);
-- slvsel_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, slvsel(0));
-- end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, gnd);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, gnd);
-- slvsel_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, vcc);
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Spartan6 SP601 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
-------------------------------------------------------------------------------
--
-- Title : master_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\master_handler.vhd
-- Generated : Wed Aug 3 14:09:02 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-11-08 V0.02 zelenkaj Added transfer qualifiers
-- 2011-11-30 V0.03 zelenkaj Removed unnecessary ports
-- 2011-12-23 V0.04 zelenkaj Fix write hanging
-- 2012-04-17 V0.05 zelenkaj Added forwarding of DMA read length
-- 2012-04-23 V0.06 zelenkaj Fix read length alignment
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity master_handler is
generic(
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
tx_fifo_word_size_log2_g : natural := 5;
gen_rx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_burst_wr_const_g : boolean := true;
fifo_data_width_g : integer := 16
);
port(
m_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_aclr : out std_logic;
tx_wr_req : out std_logic;
rx_rd_req : out std_logic;
m_waitrequest : in std_logic;
m_readdatavalid : in std_logic;
m_write : out std_logic;
m_read : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_wr : in std_logic;
dma_new_addr_rd : in std_logic;
dma_new_len_rd : in std_logic
);
end master_handler;
architecture master_handler of master_handler is
--clock signal
signal clk : std_logic;
--constants
constant tx_burst_size_c : integer := m_tx_burst_size_g; --(2**(m_burstcount_width_g-1));
constant rx_burst_size_c : integer := m_rx_burst_size_g; --(2**(m_burstcount_width_g-1));
---used to trigger rx/tx data transfers depending on fill level and burst size
constant tx_fifo_limit_c : integer := 2**tx_fifo_word_size_log2_g - tx_burst_size_c - 1; --fifo_size - burst size - 1
constant rx_fifo_limit_c : integer := rx_burst_size_c + 1; --burst size
--fsm
type transfer_t is (idle, run, finish);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--transfer signals
signal m_burstcount_s, m_burstcount_latch : std_logic_vector(m_burstcount'range);
signal m_address_latch : std_logic_vector(m_address'range);
signal m_write_s, m_read_s : std_logic;
signal rx_first_read_done, rx_rd_done : std_logic;
--fifo signals
signal arst : std_logic;
signal tx_fifo_limit, rx_fifo_limit : std_logic;
signal tx_wr_req_s, rx_rd_req_s, rx_first_rd_req : std_logic;
--generate addresses
signal tx_cnt, tx_cnt_next : std_logic_vector(m_address'range);
signal rx_cnt, rx_cnt_next : std_logic_vector(m_address'range);
--handle tx read transfer
signal tx_rd_cnt, tx_rd_cnt_next : std_logic_vector(dma_len_rd'range);
signal dma_len_rd_s : std_logic_vector(dma_len_rd'range);
begin
--m_clk, rx_rd_clk and tx_wr_clk are the same!
clk <= m_clk; --to ease typing
tx_aclr <= rst or arst;
--fifo limit is set to '1' if the fill level is equal/above the limit
tx_fifo_limit <= '1' when tx_wr_usedw >= conv_std_logic_vector(tx_fifo_limit_c, tx_wr_usedw'length) else '0';
rx_fifo_limit <= '1' when rx_rd_usedw >= conv_std_logic_vector(rx_fifo_limit_c, rx_rd_usedw'length) else '0';
process(clk, rst)
begin
if rst = '1' then
if gen_rx_fifo_g then
rx_fsm <= idle;
end if;
if gen_tx_fifo_g then
tx_fsm <= idle;
end if;
elsif clk = '1' and clk'event then
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
end if;
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
end if;
end if;
end process;
tx_fsm_next <= run when tx_fsm = idle and dma_new_addr_rd = '1' else
finish when tx_fsm = run and mac_tx_off = '1' else
idle when tx_fsm = finish and tx_wr_empty = '1' else --stay finish as long as tx fifo is filled
tx_fsm;
rx_fsm_next <= run when rx_fsm = idle and dma_new_addr_wr = '1' else
finish when rx_fsm = run and mac_rx_off = '1' else
idle when rx_fsm = finish and rx_rd_done = '1' else --stay finish as long the transfer process is not done
rx_fsm;
m_burstcount <= m_burstcount_latch when m_write_s = '1' and m_burst_wr_const_g else m_burstcount_s;
m_burstcounter <= m_burstcount_s; --output current burst counter value
m_write <= m_write_s;
m_read <= m_read_s;
--generate address
m_address <= m_address_latch when m_write_s = '1' and m_burst_wr_const_g else
rx_cnt when m_write_s = '1' and not m_burst_wr_const_g else
tx_cnt;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_cnt <= (others => '0');
tx_rd_cnt <= (others => '0');
end if;
if gen_rx_fifo_g then
rx_cnt <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_cnt <= tx_cnt_next;
tx_rd_cnt <= tx_rd_cnt_next;
end if;
if gen_rx_fifo_g then
rx_cnt <= rx_cnt_next;
end if;
end if;
end process;
dma_len_rd_s <= dma_len_rd + 1 when fifo_data_width_g = 16 else
dma_len_rd + 3 when fifo_data_width_g = 32 else
dma_len_rd;
tx_rd_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
'0' & dma_len_rd_s(dma_len_rd_s'left downto 1) when dma_new_len_rd = '1' and fifo_data_width_g = 16 else
"00" & dma_len_rd_s(dma_len_rd_s'left downto 2) when dma_new_len_rd = '1' and fifo_data_width_g = 32 else
tx_rd_cnt - 1 when tx_wr_req_s = '1' and tx_rd_cnt /= 0 else
tx_rd_cnt;
tx_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
tx_cnt + fifo_data_width_g/8 when tx_wr_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_rd = '1' else
tx_cnt;
rx_cnt_next <= (others => '0') when gen_rx_fifo_g = false else
rx_cnt + fifo_data_width_g/8 when rx_rd_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_wr = '1' else
rx_cnt;
m_byteenable <= (others => '1');
tx_wr_req_s <= m_readdatavalid;
tx_wr_req <= tx_wr_req_s;
rx_rd_req_s <= m_write_s and not m_waitrequest;
rx_rd_req <= rx_rd_req_s or rx_first_rd_req;
process(clk, rst)
--arbitration of rx and tx requests is done by process variable (tx overrules rx)
variable tx_is_the_owner_v : std_logic;
begin
if rst = '1' then
tx_is_the_owner_v := '0';
if gen_tx_fifo_g then
arst <= '0';
m_read_s <= '0';
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
m_write_s <= '0';
rx_first_read_done <= '0';
rx_rd_done <= '0';
end if;
m_burstcount_s <= (others => '0');
if m_burst_wr_const_g then
m_burstcount_latch <= (others => '0');
m_address_latch <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
arst <= '0';
if m_readdatavalid = '1' then
--read was successful -> write to tx fifo
m_burstcount_s <= m_burstcount_s - 1;
end if;
case tx_fsm is
when idle =>
--no transfer in progress
when run =>
--read transfer base address is ready
if tx_fifo_limit = '0' and m_read_s = '0' and m_write_s = '0' and m_burstcount_s = 0 and tx_rd_cnt /= 0 then
--tx fifo is below defined limit -> there is place for at least one burst!
m_read_s <= '1';
if tx_rd_cnt > conv_std_logic_vector(tx_burst_size_c, tx_rd_cnt'length) then
m_burstcount_s <= conv_std_logic_vector(tx_burst_size_c, m_burstcount_s'length);
else
m_burstcount_s <= conv_std_logic_vector(conv_integer(tx_rd_cnt), m_burstcount_s'length);
end if;
--a tx transfer is necessary and overrules necessary rx transfers...
tx_is_the_owner_v := '1';
elsif m_read_s = '1' and m_waitrequest = '0' then
--request is confirmed -> deassert request
m_read_s <= '0';
--so, we are done with tx requesting
tx_is_the_owner_v := '0';
end if;
when finish =>
--transfer done, MAC has its data...
---is there still a request?
if m_read_s = '1' and m_waitrequest = '0' then
--last request confirmed -> deassert request
m_read_s <= '0'; tx_is_the_owner_v := '0';
---is the burst transfer done?
elsif m_read_s = '0' and m_burstcount_s = 0 then
--burst transfer done, clear fifo
arst <= '1';
end if;
end case;
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
rx_rd_done <= '0';
if m_write_s = '1' and m_waitrequest = '0' then
--write was successful
m_burstcount_s <= m_burstcount_s - 1;
end if;
case rx_fsm is
when idle =>
--no transfer in progress
rx_first_read_done <= '0';
when run =>
--a not empty fifo has to be read once, to get the very first pattern
if rx_first_read_done = '0' and rx_rd_empty = '0' then
rx_first_read_done <= '1';
rx_first_rd_req <= '1';
end if;
--write transfer base address is ready
if rx_fifo_limit = '1' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 and rx_first_read_done = '1' then
--rx fifo is filled with enough data -> build burst transfer
m_write_s <= '1';
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--last transfer is done -> deassert write qualifiers
m_write_s <= '0';
end if;
when finish =>
--MAC is finished with RX, transfer rest of fifo
---note: The last word (part of crc32) is not transferred!
if rx_rd_empty = '0' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 then
--rx fifo has some data left
m_write_s <= '1';
--verify how many patterns are left in the fifo
if conv_integer(rx_rd_usedw) < rx_burst_size_c then
--start the smaller burst write transfer
m_burstcount_s <= conv_std_logic_vector(conv_integer(rx_rd_usedw), m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(conv_integer(rx_rd_usedw), m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
--workaround: fifo is not empty but word level is zero => set to one
if conv_integer(rx_rd_usedw) = 0 then
m_burstcount_s <= conv_std_logic_vector(1, m_burstcount_s'length);
m_burstcount_latch <= conv_std_logic_vector(1, m_burstcount_latch'length);
end if;
else
--start the maximum burst write transfer
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--transfer is done -> deassert write qualifiers
m_write_s <= '0';
--completely done?!
if rx_rd_empty = '1' then
--yes!
rx_rd_done <= '1';
end if;
elsif rx_rd_empty = '1' and m_write_s = '0' then
--nothing left in the fifo and we don't try to do anything -> done!
rx_rd_done <= '1';
end if;
end case;
end if;
end if;
end process;
end master_handler;
|
-------------------------------------------------------------------------------
--
-- Title : master_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\master_handler.vhd
-- Generated : Wed Aug 3 14:09:02 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-11-08 V0.02 zelenkaj Added transfer qualifiers
-- 2011-11-30 V0.03 zelenkaj Removed unnecessary ports
-- 2011-12-23 V0.04 zelenkaj Fix write hanging
-- 2012-04-17 V0.05 zelenkaj Added forwarding of DMA read length
-- 2012-04-23 V0.06 zelenkaj Fix read length alignment
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity master_handler is
generic(
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
tx_fifo_word_size_log2_g : natural := 5;
gen_rx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_burst_wr_const_g : boolean := true;
fifo_data_width_g : integer := 16
);
port(
m_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_aclr : out std_logic;
tx_wr_req : out std_logic;
rx_rd_req : out std_logic;
m_waitrequest : in std_logic;
m_readdatavalid : in std_logic;
m_write : out std_logic;
m_read : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_wr : in std_logic;
dma_new_addr_rd : in std_logic;
dma_new_len_rd : in std_logic
);
end master_handler;
architecture master_handler of master_handler is
--clock signal
signal clk : std_logic;
--constants
constant tx_burst_size_c : integer := m_tx_burst_size_g; --(2**(m_burstcount_width_g-1));
constant rx_burst_size_c : integer := m_rx_burst_size_g; --(2**(m_burstcount_width_g-1));
---used to trigger rx/tx data transfers depending on fill level and burst size
constant tx_fifo_limit_c : integer := 2**tx_fifo_word_size_log2_g - tx_burst_size_c - 1; --fifo_size - burst size - 1
constant rx_fifo_limit_c : integer := rx_burst_size_c + 1; --burst size
--fsm
type transfer_t is (idle, run, finish);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--transfer signals
signal m_burstcount_s, m_burstcount_latch : std_logic_vector(m_burstcount'range);
signal m_address_latch : std_logic_vector(m_address'range);
signal m_write_s, m_read_s : std_logic;
signal rx_first_read_done, rx_rd_done : std_logic;
--fifo signals
signal arst : std_logic;
signal tx_fifo_limit, rx_fifo_limit : std_logic;
signal tx_wr_req_s, rx_rd_req_s, rx_first_rd_req : std_logic;
--generate addresses
signal tx_cnt, tx_cnt_next : std_logic_vector(m_address'range);
signal rx_cnt, rx_cnt_next : std_logic_vector(m_address'range);
--handle tx read transfer
signal tx_rd_cnt, tx_rd_cnt_next : std_logic_vector(dma_len_rd'range);
signal dma_len_rd_s : std_logic_vector(dma_len_rd'range);
begin
--m_clk, rx_rd_clk and tx_wr_clk are the same!
clk <= m_clk; --to ease typing
tx_aclr <= rst or arst;
--fifo limit is set to '1' if the fill level is equal/above the limit
tx_fifo_limit <= '1' when tx_wr_usedw >= conv_std_logic_vector(tx_fifo_limit_c, tx_wr_usedw'length) else '0';
rx_fifo_limit <= '1' when rx_rd_usedw >= conv_std_logic_vector(rx_fifo_limit_c, rx_rd_usedw'length) else '0';
process(clk, rst)
begin
if rst = '1' then
if gen_rx_fifo_g then
rx_fsm <= idle;
end if;
if gen_tx_fifo_g then
tx_fsm <= idle;
end if;
elsif clk = '1' and clk'event then
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
end if;
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
end if;
end if;
end process;
tx_fsm_next <= run when tx_fsm = idle and dma_new_addr_rd = '1' else
finish when tx_fsm = run and mac_tx_off = '1' else
idle when tx_fsm = finish and tx_wr_empty = '1' else --stay finish as long as tx fifo is filled
tx_fsm;
rx_fsm_next <= run when rx_fsm = idle and dma_new_addr_wr = '1' else
finish when rx_fsm = run and mac_rx_off = '1' else
idle when rx_fsm = finish and rx_rd_done = '1' else --stay finish as long the transfer process is not done
rx_fsm;
m_burstcount <= m_burstcount_latch when m_write_s = '1' and m_burst_wr_const_g else m_burstcount_s;
m_burstcounter <= m_burstcount_s; --output current burst counter value
m_write <= m_write_s;
m_read <= m_read_s;
--generate address
m_address <= m_address_latch when m_write_s = '1' and m_burst_wr_const_g else
rx_cnt when m_write_s = '1' and not m_burst_wr_const_g else
tx_cnt;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_cnt <= (others => '0');
tx_rd_cnt <= (others => '0');
end if;
if gen_rx_fifo_g then
rx_cnt <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_cnt <= tx_cnt_next;
tx_rd_cnt <= tx_rd_cnt_next;
end if;
if gen_rx_fifo_g then
rx_cnt <= rx_cnt_next;
end if;
end if;
end process;
dma_len_rd_s <= dma_len_rd + 1 when fifo_data_width_g = 16 else
dma_len_rd + 3 when fifo_data_width_g = 32 else
dma_len_rd;
tx_rd_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
'0' & dma_len_rd_s(dma_len_rd_s'left downto 1) when dma_new_len_rd = '1' and fifo_data_width_g = 16 else
"00" & dma_len_rd_s(dma_len_rd_s'left downto 2) when dma_new_len_rd = '1' and fifo_data_width_g = 32 else
tx_rd_cnt - 1 when tx_wr_req_s = '1' and tx_rd_cnt /= 0 else
tx_rd_cnt;
tx_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
tx_cnt + fifo_data_width_g/8 when tx_wr_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_rd = '1' else
tx_cnt;
rx_cnt_next <= (others => '0') when gen_rx_fifo_g = false else
rx_cnt + fifo_data_width_g/8 when rx_rd_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_wr = '1' else
rx_cnt;
m_byteenable <= (others => '1');
tx_wr_req_s <= m_readdatavalid;
tx_wr_req <= tx_wr_req_s;
rx_rd_req_s <= m_write_s and not m_waitrequest;
rx_rd_req <= rx_rd_req_s or rx_first_rd_req;
process(clk, rst)
--arbitration of rx and tx requests is done by process variable (tx overrules rx)
variable tx_is_the_owner_v : std_logic;
begin
if rst = '1' then
tx_is_the_owner_v := '0';
if gen_tx_fifo_g then
arst <= '0';
m_read_s <= '0';
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
m_write_s <= '0';
rx_first_read_done <= '0';
rx_rd_done <= '0';
end if;
m_burstcount_s <= (others => '0');
if m_burst_wr_const_g then
m_burstcount_latch <= (others => '0');
m_address_latch <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
arst <= '0';
if m_readdatavalid = '1' then
--read was successful -> write to tx fifo
m_burstcount_s <= m_burstcount_s - 1;
end if;
case tx_fsm is
when idle =>
--no transfer in progress
when run =>
--read transfer base address is ready
if tx_fifo_limit = '0' and m_read_s = '0' and m_write_s = '0' and m_burstcount_s = 0 and tx_rd_cnt /= 0 then
--tx fifo is below defined limit -> there is place for at least one burst!
m_read_s <= '1';
if tx_rd_cnt > conv_std_logic_vector(tx_burst_size_c, tx_rd_cnt'length) then
m_burstcount_s <= conv_std_logic_vector(tx_burst_size_c, m_burstcount_s'length);
else
m_burstcount_s <= conv_std_logic_vector(conv_integer(tx_rd_cnt), m_burstcount_s'length);
end if;
--a tx transfer is necessary and overrules necessary rx transfers...
tx_is_the_owner_v := '1';
elsif m_read_s = '1' and m_waitrequest = '0' then
--request is confirmed -> deassert request
m_read_s <= '0';
--so, we are done with tx requesting
tx_is_the_owner_v := '0';
end if;
when finish =>
--transfer done, MAC has its data...
---is there still a request?
if m_read_s = '1' and m_waitrequest = '0' then
--last request confirmed -> deassert request
m_read_s <= '0'; tx_is_the_owner_v := '0';
---is the burst transfer done?
elsif m_read_s = '0' and m_burstcount_s = 0 then
--burst transfer done, clear fifo
arst <= '1';
end if;
end case;
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
rx_rd_done <= '0';
if m_write_s = '1' and m_waitrequest = '0' then
--write was successful
m_burstcount_s <= m_burstcount_s - 1;
end if;
case rx_fsm is
when idle =>
--no transfer in progress
rx_first_read_done <= '0';
when run =>
--a not empty fifo has to be read once, to get the very first pattern
if rx_first_read_done = '0' and rx_rd_empty = '0' then
rx_first_read_done <= '1';
rx_first_rd_req <= '1';
end if;
--write transfer base address is ready
if rx_fifo_limit = '1' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 and rx_first_read_done = '1' then
--rx fifo is filled with enough data -> build burst transfer
m_write_s <= '1';
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--last transfer is done -> deassert write qualifiers
m_write_s <= '0';
end if;
when finish =>
--MAC is finished with RX, transfer rest of fifo
---note: The last word (part of crc32) is not transferred!
if rx_rd_empty = '0' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 then
--rx fifo has some data left
m_write_s <= '1';
--verify how many patterns are left in the fifo
if conv_integer(rx_rd_usedw) < rx_burst_size_c then
--start the smaller burst write transfer
m_burstcount_s <= conv_std_logic_vector(conv_integer(rx_rd_usedw), m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(conv_integer(rx_rd_usedw), m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
--workaround: fifo is not empty but word level is zero => set to one
if conv_integer(rx_rd_usedw) = 0 then
m_burstcount_s <= conv_std_logic_vector(1, m_burstcount_s'length);
m_burstcount_latch <= conv_std_logic_vector(1, m_burstcount_latch'length);
end if;
else
--start the maximum burst write transfer
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--transfer is done -> deassert write qualifiers
m_write_s <= '0';
--completely done?!
if rx_rd_empty = '1' then
--yes!
rx_rd_done <= '1';
end if;
elsif rx_rd_empty = '1' and m_write_s = '0' then
--nothing left in the fifo and we don't try to do anything -> done!
rx_rd_done <= '1';
end if;
end case;
end if;
end if;
end process;
end master_handler;
|
-------------------------------------------------------------------------------
--
-- Title : master_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\master_handler.vhd
-- Generated : Wed Aug 3 14:09:02 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-11-08 V0.02 zelenkaj Added transfer qualifiers
-- 2011-11-30 V0.03 zelenkaj Removed unnecessary ports
-- 2011-12-23 V0.04 zelenkaj Fix write hanging
-- 2012-04-17 V0.05 zelenkaj Added forwarding of DMA read length
-- 2012-04-23 V0.06 zelenkaj Fix read length alignment
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity master_handler is
generic(
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
tx_fifo_word_size_log2_g : natural := 5;
gen_rx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_burst_wr_const_g : boolean := true;
fifo_data_width_g : integer := 16
);
port(
m_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_aclr : out std_logic;
tx_wr_req : out std_logic;
rx_rd_req : out std_logic;
m_waitrequest : in std_logic;
m_readdatavalid : in std_logic;
m_write : out std_logic;
m_read : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_wr : in std_logic;
dma_new_addr_rd : in std_logic;
dma_new_len_rd : in std_logic
);
end master_handler;
architecture master_handler of master_handler is
--clock signal
signal clk : std_logic;
--constants
constant tx_burst_size_c : integer := m_tx_burst_size_g; --(2**(m_burstcount_width_g-1));
constant rx_burst_size_c : integer := m_rx_burst_size_g; --(2**(m_burstcount_width_g-1));
---used to trigger rx/tx data transfers depending on fill level and burst size
constant tx_fifo_limit_c : integer := 2**tx_fifo_word_size_log2_g - tx_burst_size_c - 1; --fifo_size - burst size - 1
constant rx_fifo_limit_c : integer := rx_burst_size_c + 1; --burst size
--fsm
type transfer_t is (idle, run, finish);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--transfer signals
signal m_burstcount_s, m_burstcount_latch : std_logic_vector(m_burstcount'range);
signal m_address_latch : std_logic_vector(m_address'range);
signal m_write_s, m_read_s : std_logic;
signal rx_first_read_done, rx_rd_done : std_logic;
--fifo signals
signal arst : std_logic;
signal tx_fifo_limit, rx_fifo_limit : std_logic;
signal tx_wr_req_s, rx_rd_req_s, rx_first_rd_req : std_logic;
--generate addresses
signal tx_cnt, tx_cnt_next : std_logic_vector(m_address'range);
signal rx_cnt, rx_cnt_next : std_logic_vector(m_address'range);
--handle tx read transfer
signal tx_rd_cnt, tx_rd_cnt_next : std_logic_vector(dma_len_rd'range);
signal dma_len_rd_s : std_logic_vector(dma_len_rd'range);
begin
--m_clk, rx_rd_clk and tx_wr_clk are the same!
clk <= m_clk; --to ease typing
tx_aclr <= rst or arst;
--fifo limit is set to '1' if the fill level is equal/above the limit
tx_fifo_limit <= '1' when tx_wr_usedw >= conv_std_logic_vector(tx_fifo_limit_c, tx_wr_usedw'length) else '0';
rx_fifo_limit <= '1' when rx_rd_usedw >= conv_std_logic_vector(rx_fifo_limit_c, rx_rd_usedw'length) else '0';
process(clk, rst)
begin
if rst = '1' then
if gen_rx_fifo_g then
rx_fsm <= idle;
end if;
if gen_tx_fifo_g then
tx_fsm <= idle;
end if;
elsif clk = '1' and clk'event then
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
end if;
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
end if;
end if;
end process;
tx_fsm_next <= run when tx_fsm = idle and dma_new_addr_rd = '1' else
finish when tx_fsm = run and mac_tx_off = '1' else
idle when tx_fsm = finish and tx_wr_empty = '1' else --stay finish as long as tx fifo is filled
tx_fsm;
rx_fsm_next <= run when rx_fsm = idle and dma_new_addr_wr = '1' else
finish when rx_fsm = run and mac_rx_off = '1' else
idle when rx_fsm = finish and rx_rd_done = '1' else --stay finish as long the transfer process is not done
rx_fsm;
m_burstcount <= m_burstcount_latch when m_write_s = '1' and m_burst_wr_const_g else m_burstcount_s;
m_burstcounter <= m_burstcount_s; --output current burst counter value
m_write <= m_write_s;
m_read <= m_read_s;
--generate address
m_address <= m_address_latch when m_write_s = '1' and m_burst_wr_const_g else
rx_cnt when m_write_s = '1' and not m_burst_wr_const_g else
tx_cnt;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_cnt <= (others => '0');
tx_rd_cnt <= (others => '0');
end if;
if gen_rx_fifo_g then
rx_cnt <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_cnt <= tx_cnt_next;
tx_rd_cnt <= tx_rd_cnt_next;
end if;
if gen_rx_fifo_g then
rx_cnt <= rx_cnt_next;
end if;
end if;
end process;
dma_len_rd_s <= dma_len_rd + 1 when fifo_data_width_g = 16 else
dma_len_rd + 3 when fifo_data_width_g = 32 else
dma_len_rd;
tx_rd_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
'0' & dma_len_rd_s(dma_len_rd_s'left downto 1) when dma_new_len_rd = '1' and fifo_data_width_g = 16 else
"00" & dma_len_rd_s(dma_len_rd_s'left downto 2) when dma_new_len_rd = '1' and fifo_data_width_g = 32 else
tx_rd_cnt - 1 when tx_wr_req_s = '1' and tx_rd_cnt /= 0 else
tx_rd_cnt;
tx_cnt_next <= (others => '0') when gen_tx_fifo_g = false else
tx_cnt + fifo_data_width_g/8 when tx_wr_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_rd = '1' else
tx_cnt;
rx_cnt_next <= (others => '0') when gen_rx_fifo_g = false else
rx_cnt + fifo_data_width_g/8 when rx_rd_req_s = '1' else
dma_addr_in & '0' when dma_new_addr_wr = '1' else
rx_cnt;
m_byteenable <= (others => '1');
tx_wr_req_s <= m_readdatavalid;
tx_wr_req <= tx_wr_req_s;
rx_rd_req_s <= m_write_s and not m_waitrequest;
rx_rd_req <= rx_rd_req_s or rx_first_rd_req;
process(clk, rst)
--arbitration of rx and tx requests is done by process variable (tx overrules rx)
variable tx_is_the_owner_v : std_logic;
begin
if rst = '1' then
tx_is_the_owner_v := '0';
if gen_tx_fifo_g then
arst <= '0';
m_read_s <= '0';
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
m_write_s <= '0';
rx_first_read_done <= '0';
rx_rd_done <= '0';
end if;
m_burstcount_s <= (others => '0');
if m_burst_wr_const_g then
m_burstcount_latch <= (others => '0');
m_address_latch <= (others => '0');
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
arst <= '0';
if m_readdatavalid = '1' then
--read was successful -> write to tx fifo
m_burstcount_s <= m_burstcount_s - 1;
end if;
case tx_fsm is
when idle =>
--no transfer in progress
when run =>
--read transfer base address is ready
if tx_fifo_limit = '0' and m_read_s = '0' and m_write_s = '0' and m_burstcount_s = 0 and tx_rd_cnt /= 0 then
--tx fifo is below defined limit -> there is place for at least one burst!
m_read_s <= '1';
if tx_rd_cnt > conv_std_logic_vector(tx_burst_size_c, tx_rd_cnt'length) then
m_burstcount_s <= conv_std_logic_vector(tx_burst_size_c, m_burstcount_s'length);
else
m_burstcount_s <= conv_std_logic_vector(conv_integer(tx_rd_cnt), m_burstcount_s'length);
end if;
--a tx transfer is necessary and overrules necessary rx transfers...
tx_is_the_owner_v := '1';
elsif m_read_s = '1' and m_waitrequest = '0' then
--request is confirmed -> deassert request
m_read_s <= '0';
--so, we are done with tx requesting
tx_is_the_owner_v := '0';
end if;
when finish =>
--transfer done, MAC has its data...
---is there still a request?
if m_read_s = '1' and m_waitrequest = '0' then
--last request confirmed -> deassert request
m_read_s <= '0'; tx_is_the_owner_v := '0';
---is the burst transfer done?
elsif m_read_s = '0' and m_burstcount_s = 0 then
--burst transfer done, clear fifo
arst <= '1';
end if;
end case;
end if;
if gen_rx_fifo_g then
rx_first_rd_req <= '0';
rx_rd_done <= '0';
if m_write_s = '1' and m_waitrequest = '0' then
--write was successful
m_burstcount_s <= m_burstcount_s - 1;
end if;
case rx_fsm is
when idle =>
--no transfer in progress
rx_first_read_done <= '0';
when run =>
--a not empty fifo has to be read once, to get the very first pattern
if rx_first_read_done = '0' and rx_rd_empty = '0' then
rx_first_read_done <= '1';
rx_first_rd_req <= '1';
end if;
--write transfer base address is ready
if rx_fifo_limit = '1' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 and rx_first_read_done = '1' then
--rx fifo is filled with enough data -> build burst transfer
m_write_s <= '1';
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--last transfer is done -> deassert write qualifiers
m_write_s <= '0';
end if;
when finish =>
--MAC is finished with RX, transfer rest of fifo
---note: The last word (part of crc32) is not transferred!
if rx_rd_empty = '0' and m_read_s = '0' and m_write_s = '0' and tx_is_the_owner_v = '0' and m_burstcount_s = 0 then
--rx fifo has some data left
m_write_s <= '1';
--verify how many patterns are left in the fifo
if conv_integer(rx_rd_usedw) < rx_burst_size_c then
--start the smaller burst write transfer
m_burstcount_s <= conv_std_logic_vector(conv_integer(rx_rd_usedw), m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(conv_integer(rx_rd_usedw), m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
--workaround: fifo is not empty but word level is zero => set to one
if conv_integer(rx_rd_usedw) = 0 then
m_burstcount_s <= conv_std_logic_vector(1, m_burstcount_s'length);
m_burstcount_latch <= conv_std_logic_vector(1, m_burstcount_latch'length);
end if;
else
--start the maximum burst write transfer
m_burstcount_s <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_s'length);
if m_burst_wr_const_g then
m_burstcount_latch <= conv_std_logic_vector(rx_burst_size_c, m_burstcount_latch'length);
m_address_latch <= rx_cnt;
end if;
end if;
elsif m_write_s = '1' and m_waitrequest = '0' and m_burstcount_s = 1 then
--transfer is done -> deassert write qualifiers
m_write_s <= '0';
--completely done?!
if rx_rd_empty = '1' then
--yes!
rx_rd_done <= '1';
end if;
elsif rx_rd_empty = '1' and m_write_s = '0' then
--nothing left in the fifo and we don't try to do anything -> done!
rx_rd_done <= '1';
end if;
end case;
end if;
end if;
end process;
end master_handler;
|
--------------------------------------------------------------------------------------------------
-- Sparse FIR Filter
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package sparse_fir_filter_pkg is
--FIR filter component declaration
component sparse_fir_filter is
generic( h : coefficient_array);
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.sparse_fir_tap_pkg.all;
use work.fir_tap_pkg.all;
entity sparse_fir_filter is
generic( h : coefficient_array);
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end sparse_fir_filter;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of sparse_fir_filter is
signal x_chain : sig_array(h'range) := (others => (others => '0'));
signal running_sum : fir_sig_array(h'range) := (others => (others => '0'));
begin
filter_loop : for tap in h'low to h'high generate
begin
if_sparse_tap_gen : if h(tap) = ZERO_COEF generate
sparse_head_tap_gen : if tap = h'low generate
sparse_head_tap : sparse_fir_tap
port map(clk => clk,
rst => rst,
sig_in => x,
sig_out => x_chain(tap),
sum_in => (others => '0'),
sum_out => running_sum(tap));
end generate; --if head tap
sparse_tail_taps_gen : if tap /= h'low generate
sparse_tail_tap : sparse_fir_tap
port map(clk => clk,
rst => rst,
sig_in => x_chain(tap-1),
sig_out => x_chain(tap),
sum_in => running_sum(tap-1),
sum_out => running_sum(tap));
end generate; --if tail taps
end generate;
if_normal_tap_gen : if h(tap) /= ZERO_COEF generate
head_tap_gen : if tap = h'low generate
head_tap : fir_tap
port map(clk => clk,
rst => rst,
coef => h(tap),
sig_in => x,
sig_out => x_chain(tap),
sum_in => (others => '0'),
sum_out => running_sum(tap));
end generate; --if head tap
tail_taps_gen : if tap /= h'low generate
tail_tap : fir_tap
port map(clk => clk,
rst => rst,
coef => h(tap),
sig_in => x_chain(tap-1),
sig_out => x_chain(tap),
sum_in => running_sum(tap-1),
sum_out => running_sum(tap));
end generate; --if tail taps
end generate;
end generate;
--output end of the running sum
y <= running_sum(h'high);
end behave;
|
----------------------------------------------------------------------------
-- debouncer.vhd -- Signal Debouncer
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component is used to debounce signals. It is designed to
-- independently debounce a variable number of signals, the number of which
-- are set using the PORT_WIDTH generic. Debouncing is done by only
-- registering a change in a button state if it remains constant for
-- the number of clocks determined by the DEBNC_CLOCKS generic.
--
-- Generic Descriptions:
--
-- PORT_WIDTH - The number of signals to debounce. determines the width
-- of the SIGNAL_I and SIGNAL_O std_logic_vectors
-- DEBNC_CLOCKS - The number of clocks (CLK_I) to wait before registering
-- a change.
--
-- Port Descriptions:
--
-- SIGNAL_I - The input signals. A vector of width equal to PORT_WIDTH
-- CLK_I - Input clock
-- SIGNAL_O - The debounced signals. A vector of width equal to PORT_WIDTH
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
-- 08/29/2013(SamB): Improved reuseability by using generics
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE IEEE.NUMERIC_STD.ALL;
use IEEE.math_real.all;
entity debouncer is
Generic ( DEBNC_CLOCKS : INTEGER range 2 to (INTEGER'high) := 2**16;
PORT_WIDTH : INTEGER range 1 to (INTEGER'high) := 5);
Port ( SIGNAL_I : in STD_LOGIC_VECTOR ((PORT_WIDTH - 1) downto 0);
CLK_I : in STD_LOGIC;
SIGNAL_O : out STD_LOGIC_VECTOR ((PORT_WIDTH - 1) downto 0));
end debouncer;
architecture Behavioral of debouncer is
constant CNTR_WIDTH : integer := natural(ceil(LOG2(real(DEBNC_CLOCKS))));
constant CNTR_MAX : std_logic_vector((CNTR_WIDTH - 1) downto 0) := std_logic_vector(to_unsigned((DEBNC_CLOCKS - 1), CNTR_WIDTH));
type VECTOR_ARRAY_TYPE is array (integer range <>) of std_logic_vector((CNTR_WIDTH - 1) downto 0);
signal sig_cntrs_ary : VECTOR_ARRAY_TYPE (0 to (PORT_WIDTH - 1)) := (others=>(others=>'0'));
signal sig_out_reg : std_logic_vector((PORT_WIDTH - 1) downto 0) := (others => '0');
begin
debounce_process : process (CLK_I)
begin
if (rising_edge(CLK_I)) then
for index in 0 to (PORT_WIDTH - 1) loop
if (sig_cntrs_ary(index) = CNTR_MAX) then
sig_out_reg(index) <= not(sig_out_reg(index));
end if;
end loop;
end if;
end process;
counter_process : process (CLK_I)
begin
if (rising_edge(CLK_I)) then
for index in 0 to (PORT_WIDTH - 1) loop
if ((sig_out_reg(index) = '1') xor (SIGNAL_I(index) = '1')) then
if (sig_cntrs_ary(index) = CNTR_MAX) then
sig_cntrs_ary(index) <= (others => '0');
else
sig_cntrs_ary(index) <= sig_cntrs_ary(index) + 1;
end if;
else
sig_cntrs_ary(index) <= (others => '0');
end if;
end loop;
end if;
end process;
SIGNAL_O <= sig_out_reg;
end Behavioral;
|
entity test is
end entity test;
architecture test of test is
-- next line should fail to compile because it's not legal to assign a default value to a signal parameter
procedure proc(signal a : integer := 1) is
begin
end procedure proc;
begin
end architecture test;
architecture test2 of test is
procedure proc(signal a : integer) is
begin
end procedure proc;
begin
-- next line should also fail to compile because it's not legal to have no actual or an OPEN actual
proc(a => open);
end architecture test2;
architecture test3 of test is
procedure proc(
variable a : in integer := 1;
variable b : out integer := 1 -- Error
) is
begin
end procedure proc;
begin
end architecture test3;
architecture test4 of test is
procedure proc(
variable a : in integer := 1;
variable b : inout integer := 1 -- Error
) is
begin
end procedure proc;
begin
end architecture test4;
entity test2 is
port (
a : linkage boolean := false -- error
);
end entity test2;
|
-- Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.26.17:32:01
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par is
port (
vertex_col : out std_logic_vector(15 downto 0); -- vertex_col.wire
vertex_row : out std_logic_vector(15 downto 0); -- vertex_row.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
width : out std_logic_vector(15 downto 0); -- width.wire
data : in std_logic_vector(23 downto 0) := (others => '0'); -- data.wire
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire
write : in std_logic := '0'; -- write.wire
height : out std_logic_vector(15 downto 0); -- height.wire
addr : in std_logic_vector(2 downto 0) := (others => '0'); -- addr.wire
sop : in std_logic := '0' -- sop.wire
);
end entity Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par;
architecture rtl of Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNNZHXLS76 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNNZHXLS76;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_port_GNS2GDLO5E is
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_port_GNS2GDLO5E;
component alt_dspbuilder_port_GNBO6OMO5Y is
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_port_GNBO6OMO5Y;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_decoder_GNBHXAVAPH is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNBHXAVAPH;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_delay_GNKM23YKPN is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNKM23YKPN;
component alt_dspbuilder_delay_GNC4JNSRBA is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNC4JNSRBA;
component alt_dspbuilder_delay_GNH6PQLQQ2 is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNH6PQLQQ2;
component alt_dspbuilder_decoder_GNQPHUITBS is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNQPHUITBS;
component alt_dspbuilder_decoder_GN7W55JURN is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GN7W55JURN;
component alt_dspbuilder_decoder_GNBT6YIKS3 is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNBT6YIKS3;
signal decoder2sclrgnd_output_wire : std_logic; -- Decoder2sclrGND:output -> Decoder2:sclr
signal decoder2enavcc_output_wire : std_logic; -- Decoder2enaVCC:output -> Decoder2:ena
signal decoder3sclrgnd_output_wire : std_logic; -- Decoder3sclrGND:output -> Decoder3:sclr
signal decoder3enavcc_output_wire : std_logic; -- Decoder3enaVCC:output -> Decoder3:ena
signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr
signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena
signal delay6sclrgnd_output_wire : std_logic; -- Delay6sclrGND:output -> Delay6:sclr
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr
signal delay9sclrgnd_output_wire : std_logic; -- Delay9sclrGND:output -> Delay9:sclr
signal delay8sclrgnd_output_wire : std_logic; -- Delay8sclrGND:output -> Delay8:sclr
signal delay7sclrgnd_output_wire : std_logic; -- Delay7sclrGND:output -> Delay7:sclr
signal decoder7sclrgnd_output_wire : std_logic; -- Decoder7sclrGND:output -> Decoder7:sclr
signal decoder7enavcc_output_wire : std_logic; -- Decoder7enaVCC:output -> Decoder7:ena
signal delay10sclrgnd_output_wire : std_logic; -- Delay10sclrGND:output -> Delay10:sclr
signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr
signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena
signal decoder6sclrgnd_output_wire : std_logic; -- Decoder6sclrGND:output -> Decoder6:sclr
signal decoder6enavcc_output_wire : std_logic; -- Decoder6enaVCC:output -> Decoder6:ena
signal delay11sclrgnd_output_wire : std_logic; -- Delay11sclrGND:output -> Delay11:sclr
signal decoder5sclrgnd_output_wire : std_logic; -- Decoder5sclrGND:output -> Decoder5:sclr
signal decoder5enavcc_output_wire : std_logic; -- Decoder5enaVCC:output -> Decoder5:ena
signal decoder4sclrgnd_output_wire : std_logic; -- Decoder4sclrGND:output -> Decoder4:sclr
signal decoder4enavcc_output_wire : std_logic; -- Decoder4enaVCC:output -> Decoder4:ena
signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> [Bus_Conversion1:input, Bus_Conversion2:input, Bus_Conversion3:input, Bus_Conversion8:input]
signal addr_0_output_wire : std_logic_vector(2 downto 0); -- addr_0:output -> [Decoder2:data, Decoder4:data, Decoder6:data, Decoder:data]
signal bus_conversion8_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion8:output -> Delay10:input
signal delay10_output_wire : std_logic_vector(15 downto 0); -- Delay10:output -> Delay11:input
signal bus_conversion1_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion1:output -> Delay4:input
signal delay4_output_wire : std_logic_vector(15 downto 0); -- Delay4:output -> Delay5:input
signal bus_conversion2_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion2:output -> Delay6:input
signal delay6_output_wire : std_logic_vector(15 downto 0); -- Delay6:output -> Delay7:input
signal bus_conversion3_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion3:output -> Delay8:input
signal delay8_output_wire : std_logic_vector(15 downto 0); -- Delay8:output -> Delay9:input
signal data_0_output_wire : std_logic_vector(23 downto 0); -- data_0:output -> [Decoder1:data, Decoder3:data, Decoder5:data, Decoder7:data]
signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator1:data0
signal write_0_output_wire : std_logic; -- write_0:output -> [Logical_Bit_Operator1:data1, Logical_Bit_Operator4:data1, Logical_Bit_Operator6:data1, Logical_Bit_Operator8:data1]
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Delay4:ena
signal sop_0_output_wire : std_logic; -- sop_0:output -> [Logical_Bit_Operator3:data0, Logical_Bit_Operator5:data0, Logical_Bit_Operator7:data0, Logical_Bit_Operator9:data0]
signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator3:data1
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Delay5:ena
signal decoder2_dec_wire : std_logic; -- Decoder2:dec -> Logical_Bit_Operator4:data0
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Delay6:ena
signal decoder3_dec_wire : std_logic; -- Decoder3:dec -> Logical_Bit_Operator5:data1
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> Delay7:ena
signal decoder4_dec_wire : std_logic; -- Decoder4:dec -> Logical_Bit_Operator6:data0
signal logical_bit_operator6_result_wire : std_logic; -- Logical_Bit_Operator6:result -> Delay8:ena
signal decoder5_dec_wire : std_logic; -- Decoder5:dec -> Logical_Bit_Operator7:data1
signal logical_bit_operator7_result_wire : std_logic; -- Logical_Bit_Operator7:result -> Delay9:ena
signal decoder6_dec_wire : std_logic; -- Decoder6:dec -> Logical_Bit_Operator8:data0
signal logical_bit_operator8_result_wire : std_logic; -- Logical_Bit_Operator8:result -> Delay10:ena
signal decoder7_dec_wire : std_logic; -- Decoder7:dec -> Logical_Bit_Operator9:data1
signal logical_bit_operator9_result_wire : std_logic; -- Logical_Bit_Operator9:result -> Delay11:ena
signal delay5_output_wire : std_logic_vector(15 downto 0); -- Delay5:output -> vertex_col_0:input
signal delay7_output_wire : std_logic_vector(15 downto 0); -- Delay7:output -> vertex_row_0:input
signal delay9_output_wire : std_logic_vector(15 downto 0); -- Delay9:output -> width_0:input
signal delay11_output_wire : std_logic_vector(15 downto 0); -- Delay11:output -> height_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Decoder1:aclr, Decoder2:aclr, Decoder3:aclr, Decoder4:aclr, Decoder5:aclr, Decoder6:aclr, Decoder7:aclr, Decoder:aclr, Delay10:aclr, Delay11:aclr, Delay4:aclr, Delay5:aclr, Delay6:aclr, Delay7:aclr, Delay8:aclr, Delay9:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Decoder1:clock, Decoder2:clock, Decoder3:clock, Decoder4:clock, Decoder5:clock, Decoder6:clock, Decoder7:clock, Decoder:clock, Delay10:clock, Delay11:clock, Delay4:clock, Delay5:clock, Delay6:clock, Delay7:clock, Delay8:clock, Delay9:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
bus_conversion2 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => writedata, -- input.wire
output => writedata_0_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data, -- input.wire
output => data_0_output_wire -- output.wire
);
addr_0 : component alt_dspbuilder_port_GNS2GDLO5E
port map (
input => addr, -- input.wire
output => addr_0_output_wire -- output.wire
);
vertex_row_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay7_output_wire, -- input.wire
output => vertex_row -- output.wire
);
logical_bit_operator7 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator7_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder5_dec_wire -- data1.wire
);
logical_bit_operator6 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator6_result_wire, -- result.wire
data0 => decoder4_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
vertex_col_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay5_output_wire, -- input.wire
output => vertex_col -- output.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder3_dec_wire -- data1.wire
);
height_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay11_output_wire, -- input.wire
output => height -- output.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => decoder2_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
logical_bit_operator9 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator9_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder7_dec_wire -- data1.wire
);
logical_bit_operator8 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator8_result_wire, -- result.wire
data0 => decoder6_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => write, -- input.wire
output => write_0_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder1_dec_wire -- data1.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => decoder_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
decoder2 : component alt_dspbuilder_decoder_GNBHXAVAPH
generic map (
decode => "010",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder2_dec_wire, -- dec.wire
sclr => decoder2sclrgnd_output_wire, -- sclr.wire
ena => decoder2enavcc_output_wire -- ena.wire
);
decoder2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder2sclrgnd_output_wire -- output.wire
);
decoder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder2enavcc_output_wire -- output.wire
);
decoder3 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder3_dec_wire, -- dec.wire
sclr => decoder3sclrgnd_output_wire, -- sclr.wire
ena => decoder3enavcc_output_wire -- ena.wire
);
decoder3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder3sclrgnd_output_wire -- output.wire
);
decoder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder3enavcc_output_wire -- output.wire
);
decoder1 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder1_dec_wire, -- dec.wire
sclr => decoder1sclrgnd_output_wire, -- sclr.wire
ena => decoder1enavcc_output_wire -- ena.wire
);
decoder1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder1sclrgnd_output_wire -- output.wire
);
decoder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder1enavcc_output_wire -- output.wire
);
width_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay9_output_wire, -- input.wire
output => width -- output.wire
);
delay6 : component alt_dspbuilder_delay_GNKM23YKPN
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000001100100",
width => 16
)
port map (
input => bus_conversion2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay6_output_wire, -- output.wire
sclr => delay6sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator4_result_wire -- ena.wire
);
delay6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay6sclrgnd_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNC4JNSRBA
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000100101100",
width => 16
)
port map (
input => delay4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator3_result_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay4 : component alt_dspbuilder_delay_GNC4JNSRBA
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000100101100",
width => 16
)
port map (
input => bus_conversion1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay4_output_wire, -- output.wire
sclr => delay4sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator1_result_wire -- ena.wire
);
delay4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay4sclrgnd_output_wire -- output.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
delay9 : component alt_dspbuilder_delay_GNH6PQLQQ2
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000110010",
width => 16
)
port map (
input => delay8_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay9_output_wire, -- output.wire
sclr => delay9sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator7_result_wire -- ena.wire
);
delay9sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay9sclrgnd_output_wire -- output.wire
);
delay8 : component alt_dspbuilder_delay_GNH6PQLQQ2
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000110010",
width => 16
)
port map (
input => bus_conversion3_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay8_output_wire, -- output.wire
sclr => delay8sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator6_result_wire -- ena.wire
);
delay8sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay8sclrgnd_output_wire -- output.wire
);
delay7 : component alt_dspbuilder_delay_GNKM23YKPN
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000001100100",
width => 16
)
port map (
input => delay6_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay7_output_wire, -- output.wire
sclr => delay7sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator5_result_wire -- ena.wire
);
delay7sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay7sclrgnd_output_wire -- output.wire
);
bus_conversion8 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion8_output_wire -- output.wire
);
decoder7 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder7_dec_wire, -- dec.wire
sclr => decoder7sclrgnd_output_wire, -- sclr.wire
ena => decoder7enavcc_output_wire -- ena.wire
);
decoder7sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder7sclrgnd_output_wire -- output.wire
);
decoder7enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder7enavcc_output_wire -- output.wire
);
delay10 : component alt_dspbuilder_delay_GNC4JNSRBA
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000100101100",
width => 16
)
port map (
input => bus_conversion8_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay10_output_wire, -- output.wire
sclr => delay10sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator8_result_wire -- ena.wire
);
delay10sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay10sclrgnd_output_wire -- output.wire
);
decoder : component alt_dspbuilder_decoder_GNQPHUITBS
generic map (
decode => "001",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder_dec_wire, -- dec.wire
sclr => decodersclrgnd_output_wire, -- sclr.wire
ena => decoderenavcc_output_wire -- ena.wire
);
decodersclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decodersclrgnd_output_wire -- output.wire
);
decoderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoderenavcc_output_wire -- output.wire
);
decoder6 : component alt_dspbuilder_decoder_GN7W55JURN
generic map (
decode => "100",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder6_dec_wire, -- dec.wire
sclr => decoder6sclrgnd_output_wire, -- sclr.wire
ena => decoder6enavcc_output_wire -- ena.wire
);
decoder6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder6sclrgnd_output_wire -- output.wire
);
decoder6enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder6enavcc_output_wire -- output.wire
);
delay11 : component alt_dspbuilder_delay_GNC4JNSRBA
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000100101100",
width => 16
)
port map (
input => delay10_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay11_output_wire, -- output.wire
sclr => delay11sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator9_result_wire -- ena.wire
);
delay11sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay11sclrgnd_output_wire -- output.wire
);
decoder5 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder5_dec_wire, -- dec.wire
sclr => decoder5sclrgnd_output_wire, -- sclr.wire
ena => decoder5enavcc_output_wire -- ena.wire
);
decoder5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder5sclrgnd_output_wire -- output.wire
);
decoder5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder5enavcc_output_wire -- output.wire
);
decoder4 : component alt_dspbuilder_decoder_GNBT6YIKS3
generic map (
decode => "011",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder4_dec_wire, -- dec.wire
sclr => decoder4sclrgnd_output_wire, -- sclr.wire
ena => decoder4enavcc_output_wire -- ena.wire
);
decoder4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder4sclrgnd_output_wire -- output.wire
);
decoder4enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder4enavcc_output_wire -- output.wire
);
end architecture rtl; -- of Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par
|
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
-- the ready signal to limit the CPU.
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Write_Data_r : std_logic_vector(2 downto 0);
signal Set_Addr_To_r : std_logic_vector(1 downto 0);
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal B_o : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(2 downto 0);
signal Set_Addr_To : std_logic_vector(1 downto 0);
signal Write_Data : std_logic_vector(2 downto 0);
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal really_rdy : std_logic;
signal R_W_n_i : std_logic;
begin
-- ehenciak : gate Rdy with read/write to make an "OK, it's
-- really OK to stop the processor now if Rdy is
-- deasserted" signal
really_rdy <= Rdy or not(R_W_n_i);
-- ehenciak : Drive R_W_n_i off chip.
R_W_n <= R_W_n_i;
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write
);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= "1100";
Write_Data_r <= "000";
Set_Addr_To_r <= "00";
R_W_n_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
R_W_n_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= "00";
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0), 9) + resize(unsigned(DL(7) & DL), 9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Clk)
begin
if Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
P <= P_Out;
end if;
end if;
if SaveP = '1' then
P <= P_Out;
end if;
if LDP = '1' then
P <= ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>
P(Flag_C) <= '0';
when "001" =>
P(Flag_C) <= '1';
when "010" =>
P(Flag_I) <= '0';
when "011" =>
P(Flag_I) <= '1';
when "101" =>
P(Flag_V) <= '0';
when "110" =>
P(Flag_D) <= '0';
when "111" =>
P(Flag_D) <= '1';
when others =>
end case;
end if;
--if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
-- P(Flag_B) <= '1';
--end if;
--if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
-- P(Flag_I) <= '1';
-- P(Flag_B) <= B_o;
--end if;
-- B=1 always on the 6502
P(Flag_B) <= '1';
if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
if MCycle = "011" then
-- B=0 in *copy* of P pushed onto the stack
P(Flag_B) <= '0';
elsif MCycle = "100" then
P(Flag_I) <= '1';
end if;
end if;
if SO_n_o = '1' and SO_n = '0' then
P(Flag_V) <= '1';
end if;
if RstCycle = '1' and Mode_r /= "00" then
P(Flag_1) <= '1';
P(Flag_D) <= '0';
P(Flag_I) <= '1';
end if;
P(Flag_1) <= '1';
B_o <= P(Flag_B);
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
NMI_n_o <= NMI_n;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (Rdy = '1') then
BusA_r <= BusA;
BusB <= DI;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)), 9) + resize(unsigned(BusA), 9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- ehenciak : modified to use Y register as well (bugfix)
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = "11" then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <= DI when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
(others => '-') when others;
with Set_Addr_To_r select
A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
DBR & "00000000" & AD when "10",
"00000000" & BAH & BAL(7 downto 0) when "11",
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
with Write_Data_r select
DO <= DL when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
std_logic_vector(PC(7 downto 0)) when "110",
std_logic_vector(PC(15 downto 8)) when others;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
if NMI_n_o = '1' and NMI_n = '0' then
NMIAct <= '1';
end if;
end if;
end if;
end if;
end process;
end;
|
--
-- VHDL Architecture lab8_new_lib.Decoder.Structure
--
-- Created:
-- by - Hong.UNKNOWN (HSM)
-- at - 12:10:03 03/28/2014
--
-- using Mentor Graphics HDL Designer(TM) 2013.1 (Build 6)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Decode_stage IS
GENERIC( n: POSITIVE := 24; -- control output length
n_toExecute: POSITIVE := 16 -- control output length, sent to the execute stage
);
PORT( inst, pcval: IN std_logic_vector(15 downto 0); -- from Fetch Stage
A0, A1: OUT std_logic_vector(3 downto 0); -- To Register File
RD0, RD1: IN std_logic_vector(15 downto 0); -- From Register File
L, R: OUT std_logic_vector(15 downto 0); -- To Execute Stage
Control: OUT std_logic_vector(n_toExecute-1 downto 0);
Dest: OUT std_logic_vector(3 downto 0);
Extra: OUT std_logic_vector(15 downto 0);
decode_pcval_out: OUT std_logic_vector(15 downto 0);
dependsOn_op1: OUT std_logic; -- whether the decoded instruction depends on the Register corresponding to operand 1
dependsOn_op2: OUT std_logic; -- whether the decoded instruction depends on the Register corresponding to operand 2
RegWrite_current: OUT std_logic; -- Register WriteBack enable value for the current instruction decoded
clock: IN std_logic;
stall: IN std_logic;
jump: IN std_logic;
can_move_on: IN std_logic
);
END ENTITY Decode_stage;
--
ARCHITECTURE Structure OF Decode_stage IS
-- IR (Instruction Register)
SIGNAL IR_Out: std_logic_vector(15 downto 0);
-- pcval (program counter Register)
SIGNAL pcval_Out: std_logic_vector(15 downto 0);
-- ALU ROM
SIGNAL ALU_ROM_Out: std_logic_vector(n-1 downto 0);
-- Decode ROM
SIGNAL Decode_ROM_Out: std_logic_vector(n-1 downto 0);
-- Choose_ROM_MUX
SIGNAL Choose_ROM_MUX_Out: std_logic_vector(n-1 downto 0);
SIGNAL Intermediate_Control: std_logic_vector(n-1 downto 0);
-- A0 MUX
SIGNAL A0_MUX_Control: std_logic; -- 1 bit MUX control
SIGNAL A0_MUX_Out: std_logic_vector(3 downto 0); -- 4 bit out
-- L MUX
SIGNAL L_MUX_Control: std_logic_vector(1 downto 0); -- 2 bit MUX control
SIGNAL L_MUX_In_0: std_logic_vector(15 downto 0);
SIGNAL L_MUX_In_1: std_logic_vector(15 downto 0);
SIGNAL L_MUX_In_2: std_logic_vector(15 downto 0);
SIGNAL L_MUX_In_3: std_logic_vector(15 downto 0);
-- R MUX
SIGNAL R_MUX_Control: std_logic_vector(1 downto 0); -- 2 bit MUX control
SIGNAL R_MUX_In_0: std_logic_vector(15 downto 0);
SIGNAL R_MUX_In_1: std_logic_vector(15 downto 0);
SIGNAL R_MUX_In_2: std_logic_vector(15 downto 0);
SIGNAL R_MUX_In_3: std_logic_vector(15 downto 0);
-- Dest MUX
SIGNAL fourteen_signal: std_logic_vector(3 downto 0) := "1110";
SIGNAL Dest_MUX_Out: std_logic_vector(3 downto 0);
-- **************** MISC ***********************
SIGNAL IS_ALUShiftOp: std_logic;
SIGNAL IS_SUB_Control: std_logic;
SIGNAL load_enable: std_logic;
BEGIN
load_enable <= ( not( stall ) ) and can_move_on;
-- IR (Instruction Register)
IR_Register: ENTITY work.Reg(Behavior)
GENERIC MAP(size=> 16)
PORT MAP(d=>inst, q=>IR_Out, clock=> clock, e=> load_enable );
-- pcval (program counter Register)
pcval_Register: ENTITY work.Reg(Behavior)
GENERIC MAP(size=> 16)
PORT MAP(d=>pcval, q=>pcval_Out, clock=>clock, e=> load_enable);
-- ALU Decode ROM
ALU_ROM1: ENTITY work.ALU_ROM(Behavior)
GENERIC MAP(output_length=> n)
PORT MAP(inst => IR_Out, ALU_ROM_Out => ALU_ROM_Out );
-- Decode ROM (opcode)
Decode_ROM1: ENTITY work.Decode_ROM(Behavior)
GENERIC MAP(output_length=> n)
PORT MAP(inst=> IR_Out, Decode_ROM_Out=> Decode_ROM_Out);
-- ********* Decide whether to use ALU_ROM or Decode_ROM
IS_ALUShiftOp <= '1' when IR_Out(15 downto 13) = "101"
else '0';
Choose_ROM_MUX: ENTITY work.SimpleMux2(Behavior)
GENERIC MAP(width=> n)
PORT MAP(Data_In_0 => Decode_ROM_Out, Data_In_1 => ALU_ROM_Out, mux_control => Is_ALUShiftOp,
Data_Out => Choose_ROM_MUX_Out);
-- ********** CONTROL OUTPUT COMING OUT !!!!!!!!
Intermediate_Control <= (others => '0') when (stall = '1' or jump = '1') -- send a 'nop' if stall or jump is detected
else Choose_ROM_MUX_Out;
-- A0 MUX
A0_MUX_Control <= Intermediate_Control(4); -- **************************************************************************
A0_MUX: ENTITY work.SimpleMux2(Behavior)
GENERIC MAP(width=>4) -- 4 bit
PORT MAP(Data_In_0 => IR_Out(8 downto 5), Data_In_1 => IR_Out(12 downto 9), mux_control => A0_MUX_Control,
Data_Out => A0);
-- A1
A1 <= IR_Out(12 downto 9);
-- L MUX
L_MUX_In_0 <= RD0;
L_MUX_In_1 <= ( 7 downto 0 => IR_Out(7) ) & IR_Out(7 downto 0);
L_MUX_In_2 <= IR_Out(7 downto 0) & RD1(7 downto 0) ;
L_MUX_In_3 <= RD1;
L_MUX_Control <= Intermediate_Control(3 downto 2); -- *********************************************************************
L_MUX: ENTITY work.SimpleMux4(Behavior)
GENERIC MAP(width=>16) -- 16 bit
PORT MAP(Data_In_0 => L_MUX_In_0, Data_In_1 => L_MUX_In_1, Data_In_2 => L_MUX_In_2, Data_In_3 => L_MUX_In_3, mux_control => L_MUX_Control,
Data_Out => L);
-- R MUX
R_MUX_In_0 <= (10 downto 0 => '0') & IR_Out(4 downto 0);
R_In_1_MUX: ENTITY work.SimpleMux2(Behavior)
GENERIC MAP(width=> 16) -- 16 bit
PORT MAP(Data_In_0 => RD1, Data_In_1 => RD0, mux_control => Intermediate_Control(23), -- IS_SUB_Control
Data_Out => R_MUX_In_1);
R_MUX_In_2 <= ( 7 downto 0 => IR_Out(7) ) & IR_Out(7 downto 0);
R_MUX_In_3 <= pcval_out;
R_MUX_Control <= Intermediate_Control(1 downto 0); -- **********************************************************************
R_MUX: ENTITY work.SimpleMux4(Behavior)
GENERIC MAP(width=>16) -- 16 bit
PORT MAP(Data_In_0 => R_MUX_In_0 , Data_In_1 => R_MUX_In_1, Data_In_2 => R_MUX_In_2, Data_In_3 => R_MUX_In_3, mux_control => R_MUX_Control,
Data_Out => R);
-- Dest MUX
Dest_MUX: ENTITY work.SimpleMux2(Behavior)
GENERIC MAP(width=> 4) -- 4 bit
PORT MAP(Data_In_0 => IR_Out(12 downto 9), Data_In_1 => fourteen_signal, mux_control => Intermediate_Control(16), -- ***** IS_JAL
Data_Out => Dest_MUX_Out);
Dest <= Dest_MUX_Out;
-- Extra
Extra <= RD1;
-- pcval_out
decode_pcval_out <= pcval_out;
-- Outputs to Register Tracker
dependsOn_op1 <= Intermediate_Control(22);
dependsOn_op2 <= Intermediate_Control(21);
RegWrite_current <= Intermediate_Control(20);
-- Control
Control <= Intermediate_Control(20 downto 5); -- **********************************************************************
END ARCHITECTURE Structure;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: VGA_BUFFER_RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY VGA_BUFFER_RAM_tb IS
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_tb_ARCH OF VGA_BUFFER_RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
VGA_BUFFER_RAM_synth_inst:ENTITY work.VGA_BUFFER_RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: VGA_BUFFER_RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY VGA_BUFFER_RAM_tb IS
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_tb_ARCH OF VGA_BUFFER_RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
VGA_BUFFER_RAM_synth_inst:ENTITY work.VGA_BUFFER_RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: VGA_BUFFER_RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY VGA_BUFFER_RAM_tb IS
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_tb_ARCH OF VGA_BUFFER_RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
VGA_BUFFER_RAM_synth_inst:ENTITY work.VGA_BUFFER_RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: VGA_BUFFER_RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY VGA_BUFFER_RAM_tb IS
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_tb_ARCH OF VGA_BUFFER_RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
VGA_BUFFER_RAM_synth_inst:ENTITY work.VGA_BUFFER_RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: VGA_BUFFER_RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY VGA_BUFFER_RAM_tb IS
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_tb_ARCH OF VGA_BUFFER_RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
VGA_BUFFER_RAM_synth_inst:ENTITY work.VGA_BUFFER_RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: VGA_BUFFER_RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY VGA_BUFFER_RAM_tb IS
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_tb_ARCH OF VGA_BUFFER_RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
VGA_BUFFER_RAM_synth_inst:ENTITY work.VGA_BUFFER_RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: VGA_BUFFER_RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY VGA_BUFFER_RAM_tb IS
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_tb_ARCH OF VGA_BUFFER_RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
VGA_BUFFER_RAM_synth_inst:ENTITY work.VGA_BUFFER_RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: VGA_BUFFER_RAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY VGA_BUFFER_RAM_tb IS
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_tb_ARCH OF VGA_BUFFER_RAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
VGA_BUFFER_RAM_synth_inst:ENTITY work.VGA_BUFFER_RAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
--
-- The testbench for t8048.
--
-- $Id: tb_t8048.vhd,v 1.8 2008-04-28 22:10:13 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_t8048 is
end tb_t8048;
use work.t48_core_comp_pack.generic_ram_ena;
use work.t48_system_comp_pack.t8048;
use work.t48_tb_pack.all;
architecture behav of tb_t8048 is
-- clock period, 11 MHz
constant period_c : time := 90 ns;
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_ROM";
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_FILE : string;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_HINT : string := "UNUSED"
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
inclock : in std_logic;
outclock : in std_logic;
memenab : in std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);
end component;
signal xtal_s : std_logic;
signal res_n_s : std_logic;
signal int_n_s : std_logic;
signal ale_s : std_logic;
signal psen_n_s : std_logic;
signal prog_n_s : std_logic;
signal t0_b : std_logic;
signal p1_b : std_logic_vector( 7 downto 0);
signal p2_b : std_logic_vector( 7 downto 0);
signal db_b : std_logic_vector( 7 downto 0);
signal ext_mem_addr_s : std_logic_vector(11 downto 0);
signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
signal ext_ram_we_s : std_logic;
signal ext_rom_data_s : std_logic_vector( 7 downto 0);
signal rd_n_s : std_logic;
signal wr_n_s : std_logic;
signal zero_s : std_logic;
signal one_s : std_logic;
begin
zero_s <= '0';
one_s <= '1';
p2_b <= (others => 'H');
p1_b <= (others => 'H');
-----------------------------------------------------------------------------
-- External ROM, 3k bytes
-- Initialized by file t48_ext_rom.hex.
-----------------------------------------------------------------------------
ext_rom_b : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 12,
LPM_NUMWORDS => 3 * (2 ** 10),
LPM_FILE => "rom_t48_ext.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => ext_mem_addr_s,
inclock => xtal_s,
outclock => zero_s, -- unused
memenab => one_s,
q => ext_rom_data_s
);
ext_ram_b : generic_ram_ena
generic map (
addr_width_g => 8,
data_width_g => 8
)
port map (
clk_i => xtal_s,
a_i => ext_mem_addr_s(7 downto 0),
we_i => ext_ram_we_s,
ena_i => one_s,
d_i => db_b,
d_o => ext_ram_data_from_s
);
t8048_b : t8048
port map (
xtal_i => xtal_s,
reset_n_i => res_n_s,
t0_b => t0_b,
int_n_i => int_n_s,
ea_i => zero_s,
rd_n_o => rd_n_s,
psen_n_o => psen_n_s,
wr_n_o => wr_n_s,
ale_o => ale_s,
db_b => db_b,
t1_i => p1_b(1),
p2_b => p2_b,
p1_b => p1_b,
prog_n_o => prog_n_s
);
-----------------------------------------------------------------------------
-- Read from external memory
--
db_b <= ext_rom_data_s
when psen_n_s = '0' else
(others => 'Z');
db_b <= ext_ram_data_from_s
when rd_n_s = '0' else
(others => 'Z');
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- External RAM access signals
--
ext_ram: process (wr_n_s,
ale_s,
p2_b,
db_b)
begin
-- lowest 1k of external ROM is not used
ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0));
if ale_s'event and ale_s = '0' then
if not is_X(db_b) then
ext_mem_addr_s(7 downto 0) <= db_b;
else
ext_mem_addr_s(7 downto 0) <= (others => '0');
end if;
end if;
if wr_n_s'event and wr_n_s = '1' then
ext_ram_we_s <= '0';
end if;
if wr_n_s'event and wr_n_s = '0' then
ext_ram_we_s <= '1';
end if;
end process ext_ram;
--
-----------------------------------------------------------------------------
t0_b <= p1_b(0);
-----------------------------------------------------------------------------
-- The clock generator
--
clk_gen: process
begin
xtal_s <= '0';
wait for period_c/2;
xtal_s <= '1';
wait for period_c/2;
end process clk_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The reset generator
--
res_gen: process
begin
res_n_s <= '0';
wait for 5 * period_c;
res_n_s <= '1';
wait;
end process res_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The interrupt generator
--
int_gen: process
begin
int_n_s <= '1';
wait for 750 * period_c;
int_n_s <= '0';
wait for 45 * period_c;
end process int_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- End of simulation detection
--
eos: process
begin
outer: loop
wait on tb_accu_s;
if tb_accu_s = "10101010" then
wait on tb_accu_s;
if tb_accu_s = "01010101" then
wait on tb_accu_s;
if tb_accu_s = "00000001" then
-- wait for instruction strobe of this move
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
-- wait for next strobe
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
assert false
report "Simulation Result: PASS."
severity note;
else
assert false
report "Simulation Result: FAIL."
severity note;
end if;
assert false
report "End of simulation reached."
severity failure;
end if;
end if;
end loop;
end process eos;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.7 2006/06/24 00:51:50 arniml
-- comment added about lower 1k of external ROM
--
-- Revision 1.6 2006/06/22 00:21:28 arniml
-- added external ROM
--
-- Revision 1.5 2006/06/21 01:04:05 arniml
-- replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom
--
-- Revision 1.4 2004/04/18 19:00:58 arniml
-- connect T0 and T1 to P1
--
-- Revision 1.3 2004/04/14 20:57:44 arniml
-- wait for instruction strobe after final end-of-simulation detection
-- this ensures that the last mov instruction is part of the dump and
-- enables 100% matching with i8039 simulator
--
-- Revision 1.2 2004/03/26 22:39:28 arniml
-- enhance simulation result string
--
-- Revision 1.1 2004/03/24 21:42:10 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-- fft16_tb.vhd
--
-- Created on: 15 Jul 2017
-- Author: Fabian Meyer
--
-- This testbench simulates a 16-Point FFT for manual testing. Pipelining
-- and synchronisation can be tested.
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fft_helpers.all;
entity fft16_tb is
end entity;
architecture behavioral of fft16_tb is
-- Component Declaration for the Unit Under Test (UUT)
component fft16
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
swrst: in std_logic; -- software reset, RSTDEF active
en: in std_logic; -- enable, high active
start: in std_logic; -- start FFT, high active
set: in std_logic; -- load FFT with values, high active
get: in std_logic; -- read FFT results, high active
din: in complex; -- datain for loading FFT
done: out std_logic; -- FFT is done, active high
dout: out complex); -- data out for reading results
end component;
-- Clock period definitions
constant clk_period: time := 10 ns;
constant test_data: complex_arr(0 to 15) := (
to_complex(0.0,0.0),
to_complex(1.0,0.0),
to_complex(2.0,0.0),
to_complex(3.0,0.0),
to_complex(4.0,0.0),
to_complex(5.0,0.0),
to_complex(6.0,0.0),
to_complex(7.0,0.0),
to_complex(8.0,0.0),
to_complex(9.0,0.0),
to_complex(10.0,0.0),
to_complex(11.0,0.0),
to_complex(12.0,0.0),
to_complex(13.0,0.0),
to_complex(14.0,0.0),
to_complex(15.0,0.0)
);
-- Generics
constant RSTDEF: std_logic := '0';
-- Inputs
signal rst: std_logic := '0';
signal clk: std_logic := '0';
signal swrst: std_logic := '0';
signal en: std_logic := '0';
signal start: std_logic := '0';
signal set: std_logic := '0';
signal get: std_logic := '0';
signal din: complex := COMPZERO;
-- Outputs
signal done: std_logic := '0';
signal dout: complex := COMPZERO;
begin
-- Instantiate the Unit Under Test (UUT)
uut: fft16
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
swrst => swrst,
en => en,
start => start,
set => set,
get => get,
din => din,
done => done,
dout => dout);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
rst <= '1';
swrst <= '1';
en <= '1';
-- load data into FFT
-- send set signal
set <= '1';
din <= test_data(0);
wait for clk_period;
set <= '0';
for i in 1 to 15 loop
din <= test_data(i);
wait for clk_period;
end loop;
-- wait one extra cycle until data is stored to memory
wait for clk_period;
-- compute FFT
start <= '1';
wait for clk_period;
start <= '0';
wait for 50*clk_period;
-- get results
get <= '1';
wait for clk_period;
get <= '0';
wait for 15*clk_period;
wait;
end process;
end;
|
architecture RTL of ENTITY1 is
type memory is array (DEPTH - 1 downto 0) of STD_LOGIC_VECTOR(WIDTH-1 downto 0);
type memory is array (DEPTH - 1 downto 0) of
STD_LOGIC_VECTOR(WIDTH-1 downto 0);
begin
end architecture RTL;
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY tb_mux_2x1_busInput IS END tb_mux_2x1_busInput;
ARCHITECTURE test OF tb_mux_2x1_busInput IS
CONSTANT size: INTEGER:=4;
COMPONENT mux_2x1_busInput IS
GENERIC(size: INTEGER);
PORT(a, b: IN STD_LOGIC_VECTOR(size-1 downto 0);
ctrl: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(size-1 downto 0));
END COMPONENT;
SIGNAL i1: STD_LOGIC_VECTOR(size-1 DOWNTO 0):="0000";
SIGNAL i2: STD_LOGIC_VECTOR(size-1 DOWNTO 0):="1111";
SIGNAL result: STD_LOGIC_VECTOR(size-1 DOWNTO 0);
SIGNAL address: STD_LOGIC;
BEGIN
T1: mux_2x1_busInput GENERIC MAP(size) PORT MAP(a=>i1, b=>i2, ctrl=>address, q=>result);
address<='0',
'1' AFTER 20 ns;
i1<="1010" AFTER 30 ns;
i2<="0111" AFTER 30 ns;
END test; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 15:55:33 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_clk_wiz_1_0 -prefix
-- system_clk_wiz_1_0_ system_clk_wiz_1_0_sim_netlist.vhdl
-- Design : system_clk_wiz_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz is
signal clk_in1_system_clk_wiz_1_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_1_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_1_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_1_0 : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_1_0,
O => clkfbout_buf_system_clk_wiz_1_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_1_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_1_0,
O => clk_out1
);
plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => 10,
CLKFBOUT_PHASE => 0.000000,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE => 5,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
STARTUP_WAIT => "FALSE"
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_1_0,
CLKFBOUT => clkfbout_system_clk_wiz_1_0,
CLKIN1 => clk_in1_system_clk_wiz_1_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKOUT0 => clk_out1_system_clk_wiz_1_0,
CLKOUT1 => NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_plle2_adv_inst_LOCKED_UNCONNECTED,
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_1_0 is
port (
clk_out1 : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_1_0 : entity is true;
end system_clk_wiz_1_0;
architecture STRUCTURE of system_clk_wiz_1_0 is
begin
inst: entity work.system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1
);
end STRUCTURE;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- flash/ethernet bus
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(31 downto 0);
romsn : out std_ulogic;
oen : out std_logic;
writen : out std_logic;
byten : out std_logic;
wpn : out std_logic;
-- SSRAM
ssram_ce1n : out std_logic;
ssram_ce2 : out std_logic;
ssram_ce3n : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (0 to 3);
ssram_oen : out std_ulogic;
ssaddr : out std_logic_vector(20 downto 2);
ssdata : inout std_logic_vector(31 downto 0);
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
ssram_adsp_n : out std_ulogic;
ssram_adv_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
ddr_clkin : in std_logic;
ddr_clk : out std_logic;
ddr_clkn : out std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console/debug UART
rxd1 : in std_logic;
txd1 : out std_logic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal ssd, prd : std_logic_vector(31 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector;
signal clkm, rstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal dsubre : std_ulogic;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
freq => freq)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => ssram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
sden => 0, ram8 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
end generate;
wpn <= '1'; byten <= '0';
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if CFG_MCTRL_LEON2 = 1 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
ssram_adv_n_pad : outpad generic map (tech => padtech)
port map (ssram_adv_n, vcc(0));
ssram_adsp_n_pad : outpad generic map (tech => padtech)
port map (ssram_adsp_n, gnd(0));
ssaddr_pad : outpadv generic map (width => 19, tech => padtech)
port map (ssaddr, memo.address(20 downto 2));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, vcc(0));
ssram_ce1n_pad : outpad generic map (tech => padtech)
port map (ssram_ce1n, gnd(0));
ssram_ce2_pad : outpad generic map (tech => padtech)
port map (ssram_ce2, vcc(0));
ssrams_pad : outpad generic map ( tech => padtech)
port map (ssram_ce3n, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.oen);
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.wrn);
ssram_wri_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.writen);
ssram_data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (ssdata, memo.data, memo.vbdrive, ssd);
memi.data(31 downto 0) <= ssd when memo.ramsn(0) = '0' else prd;
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, prd);
end generate;
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16)
port map (
resetn, rstn, ddr_clkin, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, open, gnd(0),
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
ddrsp1 : if (CFG_DDRSP = 0) generate
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
upads : if CFG_AHB_UART = 0 generate
u1i.rxd <= rxd1; txd1 <= u1o.txd;
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2C60 SSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: fmd2030_udc2.vhd
-- Creation Date:
-- Description:
-- Second section of the 360/30, corresponding to Unit Data & Control Diagram 2
-- in the MDM.
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
-- Revision 1.1 2012-04-07
-- Add Mpx and 1050 buses, and Storage interface
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY work;
USE work.Gates_package.all;
USE work.Buses_package.all;
USE work.all;
entity UDC2 is
port(
-- Buses
SALS : IN SALS_Bus;
CTRL : IN CTRL_REG;
Z_BUS : OUT STD_LOGIC_VECTOR(0 to 8);
A_BUS1 : IN STD_LOGIC_VECTOR(0 to 8);
B_BUS : IN STD_LOGIC_VECTOR(0 to 8);
M_ASSM_BUS,N_ASSM_BUS : IN STD_LOGIC_VECTOR(0 to 8);
R : OUT STD_LOGIC_VECTOR(0 to 8);
S : OUT STD_LOGIC_VECTOR(0 to 7);
MN : OUT STD_LOGIC_VECTOR(0 to 15);
-- M_P, N_P : OUT STD_LOGIC;
E_BUS : IN E_SW_BUS_Type;
-- External MPX connections:
MPX_BUS_O : OUT STD_LOGIC_VECTOR(0 to 8);
MPX_BUS_I : IN STD_LOGIC_VECTOR(0 to 8);
MPX_TAGS_O : OUT MPX_TAGS_OUT;
MPX_TAGS_I : IN MPX_TAGS_IN;
-- Switches
LAMP_TEST : IN STD_LOGIC;
CHK_SW_PROC_SW : IN STD_LOGIC; -- 04A
CHK_SW_DISABLE : IN STD_LOGIC; -- 04A
Sw_Slow : IN STD_LOGIC;
-- Indicators
IND_OPNL_IN : OUT STD_LOGIC;
IND_ADDR_IN : OUT STD_LOGIC;
IND_STATUS_IN : OUT STD_LOGIC;
IND_SERV_IN : OUT STD_LOGIC;
IND_SEL_OUT : OUT STD_LOGIC;
IND_ADDR_OUT : OUT STD_LOGIC;
IND_CMMD_OUT : OUT STD_LOGIC;
IND_SERV_OUT : OUT STD_LOGIC;
IND_SUPPR_OUT : OUT STD_LOGIC;
IND_FO : OUT STD_LOGIC_VECTOR(0 to 7);
IND_FO_P : OUT STD_LOGIC;
IND_A : OUT STD_LOGIC_VECTOR(0 to 8);
IND_B : OUT STD_LOGIC_VECTOR(0 to 8);
IND_ALU : OUT STD_LOGIC_VECTOR(0 to 8);
IND_M, IND_N : OUT STD_LOGIC_VECTOR(0 to 8);
IND_MAIN_STG, IND_LOC_STG, IND_COMP_MODE : OUT STD_LOGIC;
IND_CHK_A_REG, IND_CHK_B_REG, IND_CHK_STOR_ADDR, IND_CHK_CTRL_REG,
IND_CHK_ROS_SALS, IND_CHK_ROS_ADDR, IND_CHK_STOR_DATA, IND_CHK_ALU : OUT STD_LOGIC;
-- Hardware interface
StorageIn : IN STORAGE_IN_INTERFACE;
StorageOut : OUT STORAGE_OUT_INTERFACE;
-- Controls
CLOCK_START : IN STD_LOGIC;
MACH_RST_3,MACH_RST_6 : IN STD_LOGIC;
CLOCK_ON : OUT STD_LOGIC;
CLOCK_OFF : OUT STD_LOGIC;
MANUAL_STORE : IN STD_LOGIC;
RECYCLE_RST : IN STD_LOGIC;
MAN_STOR_OR_DSPLY : IN STD_LOGIC;
MAN_STOR_PWR : IN STD_LOGIC;
STORE_S_REG_RST : IN STD_LOGIC;
E_SW_SEL_S : IN STD_LOGIC;
MACH_RST_SET_LCH : IN STD_LOGIC;
DIAG_SW : IN STD_LOGIC;
-- S_REG_RST : OUT STD_LOGIC;
CTRL_REG_RST : IN STD_LOGIC;
ROS_SCAN : IN STD_LOGIC;
GT_SWS_TO_WX_PWR : IN STD_LOGIC;
RST_LOAD : IN STD_LOGIC;
SYSTEM_RST_PRIORITY_LCH : IN STD_LOGIC;
A_REG_PC : OUT STD_LOGIC;
-- B_REG_PC : OUT STD_LOGIC;
CARRY_1_LCHD : OUT STD_LOGIC;
CARRY_0_LATCHED : OUT STD_LOGIC;
ALU_CHK : OUT STD_LOGIC;
NTRUE,COMPLEMENT : OUT STD_LOGIC;
P_CONNECT,P_CTRL_N,N_CTRL_N,N_CTRL_LM : OUT STD_LOGIC;
ALU_CHK_LCH : OUT STD_LOGIC;
CPU_RD_PWR : IN STD_LOGIC; -- 04B
GT_MAN_SET_MN : IN STD_LOGIC; -- 03B
CHNL_RD_CALL : IN STD_LOGIC; -- 04D
XH, XL, XXH : OUT STD_LOGIC; -- 08C
MN_PC : OUT STD_LOGIC; -- 07AD3
SET_IND_ROSAR : IN STD_LOGIC;
N_STACK_MEMORY_SELECT, STACK_RD_WR_CONTROL : IN STD_LOGIC;
H_REG_5_PWR : IN STD_LOGIC;
FORCE_M_REG_123 : IN STD_LOGIC;
GT_LOCAL_STORAGE : IN STD_LOGIC;
GT_T_REG_TO_MN : IN STD_LOGIC;
GT_CK_TO_MN : IN STD_LOGIC;
MAIN_STG_CP_1 : IN STD_LOGIC;
N_STACK_MEM_SELECT : IN STD_LOGIC;
SEL_CPU_BUMP : OUT STD_LOGIC; -- 04D
WX_CHK : IN STD_LOGIC; -- 01A
EARLY_M0 : OUT STD_LOGIC; -- 07B to 05D
MEM_WRAP : IN STD_LOGIC;
SUPPR_A_REG_CHK : OUT STD_LOGIC;
ODD : OUT STD_LOGIC;
STATUS_IN_LCHD : OUT STD_LOGIC;
SALS_PC : IN STD_LOGIC;
R_REG_PC : IN STD_LOGIC;
STORE_R : IN STD_LOGIC;
N2ND_ERROR_STOP : IN STD_LOGIC;
DECIMAL : OUT STD_LOGIC;
-- Inputs from UDC1
USE_R : IN STD_LOGIC;
USE_MAIN_MEM, USE_LOC_MAIN_MEM : IN STD_LOGIC;
USE_BASIC_CA_DECO : IN STD_LOGIC; -- 02A
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
SUPPR_MACH_CHK_TRAP : IN STD_LOGIC; -- 03A
SEL_DATA_READY : IN STD_LOGIC; -- 03B
N1401_MODE : IN STD_LOGIC; -- 05A
STG_MEM_SELECT : IN STD_LOGIC; -- 03D
MEM_PROT_REQUEST : IN STD_LOGIC; -- 03A
MANUAL_DISPLAY : IN STD_LOGIC; -- 03D
MAIN_STG : IN STD_LOGIC; -- 04D
MACH_RST_SW : IN STD_LOGIC; -- 03D
MACH_RST_SET_LCH_DLY : IN STD_LOGIC; -- 04B
MACH_CHK_RST : IN STD_LOGIC; -- 04A
MACH_CHK_PULSE : IN STD_LOGIC; -- 03A
LOCAL_STG : IN STD_LOGIC; -- 04D
GT_D_REG_TO_A_BUS : IN STD_LOGIC; -- 05C
GT_CA_TO_W_REG : IN STD_LOGIC; -- 02B
DATA_READY : IN STD_LOGIC; -- 03A
CTRL_REG_CHK : IN STD_LOGIC; -- 01A
CPU_WR_IN_R_REG : IN STD_LOGIC; -- 04D
CPU_SET_ALLOW_WR_LCH : IN STD_LOGIC; -- 03D
ANY_PRIORITY_LCH : IN STD_LOGIC; -- 03A
ALLOW_WRITE_DLYD, ALLOW_WRITE : IN STD_LOGIC; -- 03D
USE_MANUAL_DECODER : IN STD_LOGIC;
GATED_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05C
MPX_ROS_LCH : IN STD_LOGIC; -- 02A
SET_FW : IN STD_LOGIC; -- 01B
LOAD_IND : IN STD_LOGIC; -- 03C
CLOCK_OUT : IN STD_LOGIC; -- 04A
METERING_OUT : IN STD_LOGIC; -- 04A
READ_ECHO_1,READ_ECHO_2,WRITE_ECHO_1,WRITE_ECHO_2 : IN STD_LOGIC;
-- Outputs to UDC1
FIRST_MACH_CHK_REQ : OUT STD_LOGIC; -- 03A
FIRST_MACH_CHK : OUT STD_LOGIC; -- 03C
ANY_MACH_CHK : OUT STD_LOGIC; -- 01A, 03C, 04A
ALLOW_PROTECT : OUT STD_LOGIC; -- 03A
ALLOW_PC_SALS : OUT STD_LOGIC; -- 01B
P_8F_DETECTED : OUT STD_LOGIC; -- 03A
M_REG_0 : OUT STD_LOGIC; -- 05D
Z0_BUS_0 : OUT STD_LOGIC;
Z_0 : OUT STD_LOGIC;
EXT_TRAP_MASK_ON : OUT STD_LOGIC; -- 08C to 04C
MACH_RST_PROT : OUT STD_LOGIC; -- 07B to 04C
CS_DECODE_X001 : OUT STD_LOGIC; -- 07B to 03C
BASIC_CS0 : OUT STD_LOGIC; -- 07B to 03C
MACH_RST_2A : OUT STD_LOGIC;
MACH_RST_2B : OUT STD_LOGIC;
CARRY_0 : OUT STD_LOGIC;
INTRODUCE_ALU_CHK : OUT STD_LOGIC;
FT0, FT2, FT3, FT5, FT6, FT7 : OUT STD_LOGIC; -- 08C,D to 05C
MPX_INTERRUPT : OUT STD_LOGIC;
MACH_RST_MPX : OUT STD_LOGIC;
MPX_SHARE_REQ : OUT STD_LOGIC;
MPX_METERING_IN : OUT STD_LOGIC;
ADDR_IN_LCHD : OUT STD_LOGIC;
OPNL_IN_LCHD : OUT STD_LOGIC;
SERV_IN_LCHD : OUT STD_LOGIC;
-- Inputs from UDC3
T_REQUEST : IN STD_LOGIC; -- 10B
STORE_HR, STORE_GR : IN STD_LOGIC; -- 14D, 12D
SEL_SHARE_CYCLE : IN STD_LOGIC; -- 12D
SEL_R_W_CTRL : IN STD_LOGIC; -- 12C
SEL_CHNL_CHK : IN STD_LOGIC; -- 11A
HR_REG_0_7, GR_REG_0_7 : IN STD_LOGIC_VECTOR(0 TO 7); -- 13C, 11C
HR_REG_P_BIT, GR_REG_P_BIT : IN STD_LOGIC; -- 13A, 11A
GT_HSMPX_INTO_R_REG : IN STD_LOGIC; -- ???
DR_CORR_P_BIT : IN STD_LOGIC; -- ??? (HSMPX)
GT_DETECTORS_TO_HR, GT_DETECTORS_TO_GR : IN STD_LOGIC; -- 12D, 14D
EVEN_HR_0_7_BITS, EVEN_GR_0_7_BITS : IN STD_LOGIC; -- 13A, 11A
-- Outputs to UDC3
STORE_BITS : OUT STD_LOGIC_VECTOR(0 TO 8); -- 11C
-- Selector & Mpx channels
SX1_RD_CYCLE,SX2_RD_CYCLE,SX1_WR_CYCLE,SX2_WR_CYCLE : IN STD_LOGIC;
SX1_SHARE_CYCLE, SX2_SHARE_CYCLE : IN STD_LOGIC;
N_SEL_SHARE_HOLD : IN STD_LOGIC;
GK,HK : IN STD_LOGIC_VECTOR(0 to 3);
PROTECT_LOC_CPU_OR_MPX, PROTECT_LOC_SEL_CHNL : OUT STD_LOGIC;
FO, FI : OUT STD_LOGIC_VECTOR(0 to 8);
MPX_OPN_LT_GATE : OUT STD_LOGIC;
ADDR_OUT : OUT STD_LOGIC;
MPX_BUS_IN_TO_CPU : OUT STD_LOGIC_VECTOR(0 to 8);
n1050_SEL_IN : OUT STD_LOGIC;
n1050_INSTALLED : IN STD_LOGIC;
n1050_REQ_IN : IN STD_LOGIC;
n1050_OP_IN : IN STD_LOGIC;
n1050_CE_MODE : IN STD_LOGIC;
n1050_SEL_O : IN STD_LOGIC;
P_1050_SEL_OUT : OUT STD_LOGIC;
P_1050_SEL_IN : OUT STD_LOGIC;
-- Debug
DEBUG : INOUT DEBUG_BUS;
-- Clocks
CLOCK_IN : IN STD_LOGIC;
T1,T2,T3,T4 : OUT STD_LOGIC;
P1,P2,P3,P4 : OUT STD_LOGIC;
SEL_T1, SEL_T3 : IN STD_LOGIC;
M_CONV_OSC,P_CONV_OSC,M_CONV_OSC_2 : OUT STD_LOGIC;
Clk : IN STD_LOGIC
);
end entity UDC2;
architecture FMD of UDC2 is
signal sFO : STD_LOGIC_VECTOR(0 to 7);
signal sFO_P : STD_LOGIC;
signal OPNL_IN : STD_LOGIC;
signal ADDR_IN : STD_LOGIC;
signal STATUS_IN : STD_LOGIC;
signal SERVICE_IN : STD_LOGIC;
signal SELECT_OUT : STD_LOGIC;
signal sADDR_OUT : STD_LOGIC;
signal COMMAND_OUT : STD_LOGIC;
signal SERVICE_OUT : STD_LOGIC;
signal SUPPRESS_OUT : STD_LOGIC;
signal Z_HI_0,Z_LO_0,sZ_0 : STD_LOGIC;
signal sCARRY_0, CARRY_4 : STD_LOGIC;
signal GT_CARRY_TO_S3 : STD_LOGIC;
signal sMACH_RST_2A,sMACH_RST_2B,MACH_RST_2C : STD_LOGIC;
signal MN_REG_CHK_SMPLD : STD_LOGIC;
signal A_BUS, A_BUS2, Q_REG_BUS : STD_LOGIC_VECTOR(0 TO 8);
signal R_0 : STD_LOGIC;
signal READ_1,READ_2,WRITE_1,WRITE_2 : STD_LOGIC;
-- signal PHASE_RD_1, PHASE_RD_2, PHASE_WR_1, PHASE_WR_2 : STD_LOGIC;
signal SA : STD_LOGIC_VECTOR(0 to 7);
signal MPX_CP : STD_LOGIC;
signal OSC_T_LINE : STD_LOGIC;
signal FB_K_T2_PULSE : STD_LOGIC;
signal GT_Q_REG_TO_A_BUS : STD_LOGIC;
signal STACK_PC : STD_LOGIC;
signal MC : STD_LOGIC_VECTOR(0 to 7);
signal MAIN_STORAGE_CP : STD_LOGIC;
signal GATE_Z_BUS_TO_S_REG : STD_LOGIC;
signal GT_DDC_TO_A_BUS : STD_LOGIC;
-- signal A_BUS_2,A_BUS_3 : STD_LOGIC_VECTOR(0 to 8);
-- IO
signal SERV_IN_SIG : STD_LOGIC := '0';
signal STAT_IN_SIG : STD_LOGIC := '0';
signal sT1,sT2,sT3,sT4 : STD_LOGIC;
signal sP1,sP2,sP3,sP4 : STD_LOGIC;
signal sCLOCK_ON, sCLOCK_OFF : STD_LOGIC;
signal sM_CONV_OSC, sP_CONV_OSC, sM_CONV_OSC_2 : STD_LOGIC;
signal sA_REG_PC, sB_REG_PC : STD_LOGIC;
signal sALU_CHK : STD_LOGIC;
signal sMN : STD_LOGIC_VECTOR(0 to 15);
signal sM_P, sN_P : STD_LOGIC;
signal sS : STD_LOGIC_VECTOR(0 to 7);
signal sZ_BUS,sN_Z_BUS,sR : STD_LOGIC_VECTOR(0 to 8);
signal sS_REG_RST : STD_LOGIC;
signal sNTRUE, sCOMPLEMENT : STD_LOGIC;
signal sP_CONNECT, sP_CTRL_N, sN_CTRL_N, sN_CTRL_LM : STD_LOGIC;
signal sALU_CHK_LCH : STD_LOGIC;
signal sZ_BUS_LO_DIGIT_PARITY : STD_LOGIC;
signal sMN_PC : STD_LOGIC;
signal sPROTECT_LOC_CPU_OR_MPX : STD_LOGIC;
signal sXL,sXH,sXXH : STD_LOGIC;
signal SUPPR_CTRL_LCH,OP_OUT_SIG,SX1_MASK,SX2_MASK,FAK,SET_BUS_O_CTRL_LCH : STD_LOGIC;
-- signal sMPX_BUS_O_REG : STD_LOGIC_VECTOR(0 to 8);
signal sFT2, sFT7 : STD_LOGIC;
begin
-- Clock
clock_sect: entity Clock (FMD) port map (
CLOCK_IN => CLOCK_IN,
T1 => sT1,
T2 => sT2,
T3 => sT3,
T4 => sT4,
P1 => sP1,
P2 => sP2,
P3 => sP3,
P4 => sP4,
CLOCK_START => CLOCK_START,
CLOCK_ON => sCLOCK_ON,
CLOCK_OFF => sCLOCK_OFF,
MACH_RST_3 => MACH_RST_3,
M_CONV_OSC => sM_CONV_OSC,
P_CONV_OSC => sP_CONV_OSC,
M_CONV_OSC_2 => sM_CONV_OSC_2,
OSC_T_LINE => OSC_T_LINE,
Sw_Slow => Sw_Slow
);
T1 <= sT1;
T2 <= sT2;
T3 <= sT3;
T4 <= sT4;
P1 <= sP1;
P2 <= sP2;
P3 <= sP3;
P4 <= sP4;
M_CONV_OSC <= sM_CONV_OSC;
P_CONV_OSC <= sP_CONV_OSC;
M_CONV_OSC_2 <= sM_CONV_OSC_2;
CLOCK_ON <= sCLOCK_ON;
CLOCK_OFF <= sCLOCK_OFF;
MpxInd_sect: entity MpxInd (FMD) port map (
FO => sFO,
FO_P => sFO_P,
OPNL_IN => OPNL_IN,
ADDR_IN => ADDR_IN,
STATUS_IN => STATUS_IN,
SERVICE_IN => SERVICE_IN,
SELECT_OUT => SELECT_OUT,
ADDR_OUT => sADDR_OUT,
COMMAND_OUT => COMMAND_OUT,
SERVICE_OUT => SERVICE_OUT,
SUPPRESS_OUT => SUPPRESS_OUT,
IND_OPNL_IN => IND_OPNL_IN,
IND_ADDR_IN => IND_ADDR_IN,
IND_STATUS_IN => IND_STATUS_IN,
IND_SERV_IN => IND_SERV_IN,
IND_SEL_OUT => IND_SEL_OUT,
IND_ADDR_OUT => IND_ADDR_OUT,
IND_CMMD_OUT => IND_CMMD_OUT,
IND_SERV_OUT => IND_SERV_OUT,
IND_SUPPR_OUT => IND_SUPPR_OUT,
IND_FO => IND_FO,
IND_FO_P => IND_FO_P,
TEST_LAMP => LAMP_TEST
);
A_BUS <= A_BUS1 and A_BUS2; -- Combine buses - input buses are 11111111 when inactive, values are inverted
ALU: entity ABALU port map(
-- Inputs
LAMP_TEST => LAMP_TEST,
SALS => SALS,
MANUAL_STORE => MANUAL_STORE,
RECYCLE_RST => RECYCLE_RST,
S_REG_3 => sS(3),
SERV_IN_SIG => SERV_IN_SIG,
STAT_IN_SIG => STAT_IN_SIG,
OPNL_IN => OPNL_IN,
ADDR_IN => ADDR_IN,
T_REQUEST => T_REQUEST,
A_BUS => A_BUS,
B_BUS => B_BUS,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
MACH_RST_SET_LCH => MACH_RST_SET_LCH,
S_REG_0 => sS(0),
CTRL => CTRL,
DIAG_SW => DIAG_SW,
S_REG_RST => sS_REG_RST,
GT_Z_BUS_TO_S_REG => GATE_Z_BUS_TO_S_REG,
ROS_SCAN => ROS_SCAN,
GT_SWS_TO_WX_PWR => GT_SWS_TO_WX_PWR,
RST_LOAD => RST_LOAD,
SYSTEM_RST_PRIORITY_LCH => SYSTEM_RST_PRIORITY_LCH,
-- Outputs
IND_A => IND_A,
IND_B => IND_B,
IND_ALU => IND_ALU,
A_REG_PC => sA_REG_PC,
B_REG_PC => sB_REG_PC,
OPNL_IN_LCHD => OPNL_IN_LCHD,
STATUS_IN_LCHD => STATUS_IN_LCHD,
Z0_BUS_0 => Z0_BUS_0,
SERV_IN_LCHD => SERV_IN_LCHD,
ADDR_IN_LCHD => ADDR_IN_LCHD,
CARRY_0 => sCARRY_0,
CARRY_1_LCHD => CARRY_1_LCHD,
CARRY_0_LATCHED => CARRY_0_LATCHED,
ALU_CHK => sALU_CHK,
NTRUE => sNTRUE,
COMPLEMENT => sCOMPLEMENT,
P_CONNECT => sP_CONNECT,
P_CTRL_N => sP_CTRL_N,
N_CTRL_N => sN_CTRL_N,
N_CTRL_LM => sN_CTRL_LM,
P_Z_BUS => sZ_BUS,
N_Z_BUS => sN_Z_BUS,
Z_HI_0 => Z_HI_0,
Z_LO_0 => Z_LO_0,
Z_0 => sZ_0,
Z_BUS_LO_DIGIT_PARITY => sZ_BUS_LO_DIGIT_PARITY,
MACH_RST_2A => sMACH_RST_2A,
MACH_RST_2B => sMACH_RST_2B,
MACH_RST_2C => MACH_RST_2C,
ALU_CHK_LCH => sALU_CHK_LCH,
ODD => ODD,
GT_CARRY_TO_S3 => GT_CARRY_TO_S3,
DECIMAL => DECIMAL,
INTRODUCE_ALU_CHK => INTRODUCE_ALU_CHK,
-- Debug
-- DEBUG => DEBUG,
-- Clocks
T1 => sT1,
T2 => sT2,
T3 => sT3,
T4 => sT4,
P1 => sP1,
Clk => Clk
);
A_REG_PC <= sA_REG_PC;
-- B_REG_PC <= sB_REG_PC;
ALU_CHK <= sALU_CHK;
Z_BUS <= sZ_BUS;
-- S_REG_RST <= sS_REG_RST;
NTRUE <= sNTRUE;
COMPLEMENT <= sCOMPLEMENT;
P_CONNECT <= sP_CONNECT;
P_CTRL_N <= sP_CTRL_N;
N_CTRL_N <= sN_CTRL_N;
N_CTRL_LM <= sN_CTRL_LM;
ALU_CHK_LCH <= sALU_CHK_LCH;
MACH_RST_2A <= sMACH_RST_2A;
MACH_RST_2B <= sMACH_RST_2B;
CARRY_0 <= sCARRY_0;
Z_0 <= sZ_0;
r_reg: entity RREG_STG port map (
-- Inputs
SALS => SALS,
CTRL => CTRL,
SX2_RD_CYCLE => SX2_RD_CYCLE,
SEL_T3 => SEL_T3,
GT_DETECTORS_TO_HR => GT_DETECTORS_TO_HR,
SEL_DATA_READY => SEL_DATA_READY,
SEL_R_W_CTRL => SEL_R_W_CTRL,
SX2_WR_CYCLE => SX2_WR_CYCLE,
SX1_RD_CYCLE => SX1_RD_CYCLE,
SX1_WR_CYCLE => SX1_WR_CYCLE,
GT_DETECTORS_TO_GR => GT_DETECTORS_TO_GR,
EVEN_HR_0_7_BITS => EVEN_HR_0_7_BITS,
EVEN_GR_0_7_BITS => EVEN_GR_0_7_BITS,
HR_REG_0_7 => HR_REG_0_7,
GR_REG_0_7 => GR_REG_0_7,
DR_CORR_P_BIT => DR_CORR_P_BIT,
HR_REG_P_BIT => HR_REG_P_BIT,
GR_REG_P_BIT => GR_REG_P_BIT,
STORE_HR => STORE_HR,
STORE_GR => STORE_GR,
STORE_R => STORE_R,
MEM_SELECT => STG_MEM_SELECT,
MAN_STORE_PWR => MANUAL_STORE,
E_SW_SEL_R => E_BUS.R_SEL,
GT_HSMPX_INTO_R_REG => GT_HSMPX_INTO_R_REG,
COMPUTE_CY_LCH => CTRL.COMPUTE_CY_LCH,
CLOCK_OFF => sCLOCK_OFF,
ALLOW_WRITE_1 => ALLOW_WRITE_DLYD,
PROT_LOC_CPU_OR_MPX => sPROTECT_LOC_CPU_OR_MPX,
USE_R => USE_R,
MANUAL_DISPLAY => MANUAL_DISPLAY,
MAN_STORE => MANUAL_STORE,
DATA_READY => DATA_READY,
MACH_RST_2A => sMACH_RST_2A,
MACH_RST_SET_LCH_DLY => MACH_RST_SET_LCH_DLY,
SEL_SHARE_CYCLE => SEL_SHARE_CYCLE,
MN_REG_CHK_SMPLD => MN_REG_CHK_SMPLD,
MEM_WRAP => MEM_WRAP,
MAIN_STG => MAIN_STG,
MACH_RST_6 => MACH_RST_6,
ALLOW_WRITE => ALLOW_WRITE,
ALLOW_PROTECT => ALLOW_PROTECT,
CPU_SET_ALLOW_WR_LCH => CPU_SET_ALLOW_WR_LCH,
N1401_MODE => N1401_MODE,
MACH_RST_SW => MACH_RST_SW,
MN => sMN,
N_Z_BUS => sN_Z_BUS,
USE_MAIN_MEM => USE_MAIN_MEM,
USE_LOC_MAIN_MEM => USE_LOC_MAIN_MEM,
PHASE_RD_1 => READ_ECHO_1,
PHASE_RD_2 => READ_ECHO_2,
PHASE_WR_1 => WRITE_ECHO_1,
PHASE_WR_2 => WRITE_ECHO_2,
-- Outputs
STORE_BITS => STORE_BITS,
R_0 => R_0,
R_REG_BUS => sR,
P_8F_DETECTED => P_8F_DETECTED,
StorageIn => StorageIn,
StorageOut => StorageOut,
-- Clocks
T1 => sT1,
T2 => sT2,
T3 => sT3, -- not really needed
T4 => sT4,
clk => clk
);
R <= sR;
SAR_SA : entity SARSA port map (
M_ASSM_BUS => M_ASSM_BUS,
N_ASSM_BUS => N_ASSM_BUS,
MACH_RST_SW => MACH_RST_SW,
MACH_RESET_SET_LCH_DLY => MACH_RST_SET_LCH_DLY ,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
CPU_RD_PWR => CPU_RD_PWR,
SEL_RDWR_CTRL => SEL_R_W_CTRL,
GT_MAN_SET_MN => GT_MAN_SET_MN,
CHNL_RD_CALL => CHNL_RD_CALL,
XH => sXH,
XL => sXL,
XXH => sXXH,
MAIN_STORAGE_CP => MAIN_STORAGE_CP,
MPX_CP => MPX_CP,
MN => sMN,
M_P => sM_P,
N_P => sN_P,
MACH_RST_PROTECT => MACH_RST_PROT,
EARLY_M0 => EARLY_M0,
M_REG_0 => M_REG_0,
SA_REG => SA,
SEL_T1 => SEL_T1,
T1 => sT1
);
S_Reg : entity SReg port map (
CS => CTRL.CTRL_CS,
SA => SALS.SALS_SA,
CD => CTRL.CTRL_CD,
N_Z_BUS => sN_Z_BUS(0 to 7),
Z_BUS0 => sZ_0,
CARRY_0 => sCARRY_0,
Z_BUS_HI_0 => Z_HI_0,
Z_BUS_LO_0 => Z_LO_0,
GT_CARRY_TO_S3 => GT_CARRY_TO_S3,
CTRL_REG_RST => CTRL_REG_RST,
MAN_STOR_PWR => MAN_STOR_PWR,
STORE_S_REG_RST => STORE_S_REG_RST,
E_SW_SEL_S => E_SW_SEL_S,
MACH_RST_2C => MACH_RST_2C,
T_REQUEST => T_REQUEST,
GT_Z_BUS_TO_S => GATE_Z_BUS_TO_S_REG,
S_REG_RST => sS_REG_RST,
FB_K_T2_PULSE => FB_K_T2_PULSE,
CS_DECODE_X001 => CS_DECODE_X001,
BASIC_CS_0 => BASIC_CS0,
P1 => sP1,
T1 => sT1,
T2 => sT2,
T3 => sT3,
T4 => sT4,
S => sS,
clk => clk
);
S <= sS;
MN_Ind : entity MNInd port map (
-- Inputs
MN => sMN,
M_P => sM_P,
N_P => sN_P,
LAMP_TEST => LAMP_TEST,
MAIN_STG => MAIN_STG,
LOCAL_STG => LOCAL_STG,
N1401_MODE => N1401_MODE,
-- Outputs
IND_M => IND_M,
IND_N => IND_N,
IND_MAIN_STG => IND_MAIN_STG,
IND_LOC_STG => IND_LOC_STG,
IND_COMP_MODE => IND_COMP_MODE,
MN_PC => sMN_PC
);
MN <= sMN;
-- M_P <= sM_P;
-- N_P <= sN_P;
MN_PC <= sMN_PC;
ChkReg_Ind : entity ChkRegInd port map (
-- Inputs
LAMP_TEST => LAMP_TEST,
GT_CA_TO_W_REG => GT_CA_TO_W_REG,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
CA_SALS => SALS.SALS_CA,
ROS_SCAN => ROS_SCAN,
MACH_CHK_PULSE => MACH_CHK_PULSE,
GT_D_REG_TO_A_BUS => GT_D_REG_TO_A_BUS,
MACH_RST_SW => MACH_RST_SW,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
SET_IND_ROSAR => SET_IND_ROSAR,
MACH_RST_6 => MACH_RST_6,
WX_CHK => WX_CHK,
A_REG_PC => sA_REG_PC,
B_REG_PC => sB_REG_PC,
N2ND_ERROR_STOP => N2ND_ERROR_STOP,
ALLOW_WRITE => ALLOW_WRITE,
CTRL_REG_CHK => CTRL_REG_CHK,
SALS_PC => SALS_PC,
R_REG_PC => R_REG_PC,
ALU_CHK => sALU_CHK,
CHK_SW_PROC_SW => CHK_SW_PROC_SW,
SUPPR_MACH_CHK_TRAP => SUPPR_MACH_CHK_TRAP,
CPU_WR_IN_R_REG => CPU_WR_IN_R_REG,
GT_Q_REG_TO_A_BUS => GT_Q_REG_TO_A_BUS,
STACK_PC => STACK_PC,
MEM_PROT_REQUEST => MEM_PROT_REQUEST,
SEL_CHNL_CHK => SEL_CHNL_CHK,
MACH_CHK_RST => MACH_CHK_RST,
AK_SAL_BIT => SALS.SALS_AK,
CK_SALS => SALS.SALS_CK,
MN_PC => sMN_PC,
N1401_MODE => N1401_MODE,
-- Outputs
SUPPR_A_REG_CHK => SUPPR_A_REG_CHK,
ALLOW_PC_SALS => ALLOW_PC_SALS,
MN_REG_CHK_SMPLD => MN_REG_CHK_SMPLD,
FIRST_MACH_CHK => FIRST_MACH_CHK,
FIRST_MACH_CHK_REQ => FIRST_MACH_CHK_REQ,
ANY_MACH_CHK => ANY_MACH_CHK,
IND_MC_A_REG => IND_CHK_A_REG,
IND_MC_B_REG => IND_CHK_B_REG,
IND_MC_STOR_ADDR => IND_CHK_STOR_ADDR,
IND_MC_CTRL_REG => IND_CHK_CTRL_REG,
IND_MC_ROS_SALS => IND_CHK_ROS_SALS,
IND_MC_ROS_ADDR => IND_CHK_ROS_ADDR,
IND_MC_STOR_DATA => IND_CHK_STOR_DATA,
IND_MC_ALU => IND_CHK_ALU,
MC => MC,
-- Clocks
T1 => sT1,
T2 => sT2,
T3 => sT3,
T4 => sT4,
P1 => sP1,
clk => clk
);
STP : entity QReg_STP port map (
-- Inputs
SA_REG => SA,
Z_BUS => sZ_BUS,
SX1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX2_SHARE_CYCLE => SX2_SHARE_CYCLE,
MAIN_STG => MAIN_STG,
H_REG_5_PWR => H_REG_5_PWR,
FORCE_M_REG_123 => FORCE_M_REG_123,
GT_LOCAL_STORAGE => GT_LOCAL_STORAGE,
GT_T_REG_TO_MN => GT_T_REG_TO_MN,
GT_CK_TO_MN => GT_CK_TO_MN,
MAIN_STG_CP_1 => MAIN_STG_CP_1,
N_STACK_MEMORY_SELECT => N_STACK_MEMORY_SELECT,
STACK_RD_WR_CONTROL => STACK_RD_WR_CONTROL,
E_SW_SEL_Q => E_BUS.Q_SEL,
MAN_STORE_PWR => MANUAL_STORE,
T4 => sT4,
MACH_RST_2B => sMACH_RST_2B,
Z_BUS_LO_DIG_PARITY => sZ_BUS_LO_DIGIT_PARITY,
CD_REG => CTRL.CTRL_CD,
CLOCK_OFF => sCLOCK_OFF,
N_SEL_SHARE_HOLD => N_SEL_SHARE_HOLD,
N_MEM_SELECT => N_STACK_MEM_SELECT,
GK => GK,
HK => HK,
CLK => CLOCK_IN,
-- Outputs
Q_REG_BUS => Q_REG_BUS,
SEL_CPU_BUMP => SEL_CPU_BUMP,
STACK_PC => STACK_PC,
MPX_CP => MPX_CP,
MAIN_STG_CP => MAIN_STORAGE_CP,
PROTECT_LOC_CPU_OR_MPX => sPROTECT_LOC_CPU_OR_MPX,
PROTECT_LOC_SEL_CHNL => PROTECT_LOC_SEL_CHNL
);
PROTECT_LOC_CPU_OR_MPX <= sPROTECT_LOC_CPU_OR_MPX;
ARegA : entity ARegAssm port map (
-- Inputs
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
E_SEL_SW_BUS => E_BUS,
GTD_CA_BITS => GATED_CA_BITS,
CHK_SW_DISABLE => CHK_SW_DISABLE,
S => sS,
MC_CTRL_REG => MC,
Q_REG => Q_REG_BUS,
-- Outputs
A_BUS => A_BUS2,
GT_Q_REG_TO_A_BUS => GT_Q_REG_TO_A_BUS
);
MpxReg1 : entity MpxFOFB port map (
-- Inputs
MPX_ROS_LCH => MPX_ROS_LCH, -- 02A
S_REG_0 => sS(0), -- 07B
SET_FW => SET_FW, -- 01B
S_REG_1 => sS(1), -- 07B
S_REG_2 => sS(2), -- 07B
T3 => sT3,
CK_SALS => SALS.SALS_CK,
PK_SALS => SALS.SALS_PK,
FBK_T2 => FB_K_T2_PULSE, -- 07B
MACH_RST_SET_LCH => MACH_RST_SET_LCH, -- 04B
SALS_CS => SALS.SALS_CS,
SALS_SA => SALS.SALS_SA,
CK_0_PWR => SALS.SALS_CK(0), -- 01C
R_REG => sR, -- 06C
T1 => sT1,
T2 => sT2,
-- Outputs
XXH => sXXH, -- 05B 07B
XH => sXH, -- 05B 07B
XL => sXL, -- 05B 07B
FT_7_BIT_MPX_CHNL_INTRP => sFT7, -- 05C 08D
FT_2_BIT_MPX_OPN_LCH => FT2, -- 04A 05C
SUPPR_CTRL_LCH => SUPPR_CTRL_LCH, -- 08D
OP_OUT_SIG => OP_OUT_SIG, -- 08D
MPX_OPN_LT_GATE => MPX_OPN_LT_GATE, -- 10B
MACH_RST_MPX => MACH_RST_MPX, -- 01C
MPX_INTRPT => MPX_INTERRUPT, -- 02A
SX1_MASK => SX1_MASK, -- 12D
EXT_TRAP_MASK_ON => EXT_TRAP_MASK_ON, -- 04C
SX2_MASK => SX2_MASK, -- 14D
FAK => FAK, -- 08D
SET_BUS_O_CTRL_LCH => SET_BUS_O_CTRL_LCH, -- 08D
MPX_BUS_O_REG(0 to 7) => sFO,-- 08A 08D 05C 11D 13D
MPX_BUS_O_REG(8) => sFO_P,
clk => clk
);
XL <= sXL;
XH <= sXH;
XXH <= sXXH;
FO <= sFO & sFO_P;
FT7 <= sFT7;
MpxChnlCtrls: entity MpxFA port map ( -- 5-08D
BUS_O_REG(0 to 7) => sFO,
BUS_O_REG(8) => sFO_P,
DIAG_SW => DIAG_SW,
-- MPX physical I/O
MPX_BUS_OUT_BITS => MPX_BUS_O,
MPX_BUS_IN_BITS => MPX_BUS_I,
TAGS_OUT => MPX_TAGS_O,
TAGS_IN => MPX_TAGS_I,
FI => FI,
FAK => FAK,
RECYCLE_RST => RECYCLE_RST,
CK_P_BIT => SALS.SALS_PK,
ALU_CHK_LCH => sALU_CHK_LCH,
CHK_SW_PROC_SW => CHK_SW_PROC_SW,
ROS_SCAN => ROS_SCAN,
FBK_T2 => FB_K_T2_PULSE,
FT5_BIT_SEL_IN => FT5,
SERV_IN_SIGNAL => SERV_IN_SIG,
STATUS_IN_SIGNAL => STAT_IN_SIG,
FT3_BIT_MPX_SHARE_REQ => FT3,
MPX_SHARE_REQ => MPX_SHARE_REQ,
T1 => sT1,
T2 => sT2,
T3 => sT3,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
CK_SALS_PWR => SALS.SALS_CK,
SET_BUS_O_CTRL_LCH => SET_BUS_O_CTRL_LCH,
N1401_MODE => N1401_MODE,
-- 1050 attachment
N1050_INSTALLED => n1050_INSTALLED,
N1050_REQ_IN => n1050_REQ_IN,
N1050_OP_IN => n1050_OP_IN,
N1050_CE_MODE => n1050_CE_MODE,
N1050_SEL_IN => n1050_SEL_IN,
N1050_SEL_O => n1050_SEL_O,
P_1050_SEL_OUT => P_1050_SEL_OUT,
P_1050_SEL_IN => P_1050_SEL_IN,
MPX_METERING_IN => MPX_METERING_IN,
FT7_MPX_CHNL_IN => sFT7,
LOAD_IND => LOAD_IND,
SUPPR_CTRL_LCH => SUPPR_CTRL_LCH,
OP_OUT_SIGNAL => OP_OUT_SIG,
-- RECYCLE_RESET => RECYCLE_RST,
OP_OUT_SIG => OP_OUT_SIG,
SEL_O_FT6 => FT6,
-- N1050_SEL_OUT => N1050_SEL_OUT,
SUPPR_O => FT0 ,
-- SUPPR_O_FT0 => FT0,
-- OP_OUT => OP_OUT,
METERING_OUT => METERING_OUT,
CLOCK_OUT => CLOCK_OUT,
CLK => CLK,
DEBUG => DEBUG,
-- Mpx Indicators
OPNL_IN => OPNL_IN,
ADDR_IN => ADDR_IN,
STATUS_IN => STATUS_IN,
SERVICE_IN => SERVICE_IN,
SELECT_OUT => SELECT_OUT,
ADDR_OUT => sADDR_OUT,
COMMAND_OUT => COMMAND_OUT,
SERVICE_OUT => SERVICE_OUT,
SUPPRESS_OUT => SUPPRESS_OUT
);
ADDR_OUT <= sADDR_OUT;
end FMD;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port(
clk, res_as, up : in std_logic;
count : out std_logic_vector (3 downto 0)
);
end entity;
architecture behav of counter is
signal Q : std_logic_vector (3 downto 0) := "0000";
signal N : std_logic_vector (3 downto 0) := "1001";
signal t : std_logic;
begin
process (clk, res_as)
begin
if res_as = '1' or (Q(2)='1' and Q(0)='1') then
Q<=(others=>'0');
elsif rising_edge(clk) then
if up='1' then
Q<=Q+1;
elsif up='0' then
Q<=Q-1;
end if;
end if;
end process;
count <= Q;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity gpio is
port( clk : in std_logic;
rst : in std_logic;
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
wr : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(7 downto 0);
HEX0, HEX1, HEX2, HEX3: out std_logic_vector(6 downto 0)
);
end;
architecture gpio of gpio is
signal outport : std_logic_vector(31 downto 0);
signal disp : std_logic_vector(15 downto 0);
begin
display3: entity work.sevenseg port map (disp(15 downto 12), hex3);
display2: entity work.sevenseg port map (disp(11 downto 8), hex2);
display1: entity work.sevenseg port map (disp(7 downto 4), hex1);
display0: entity work.sevenseg port map (disp(3 downto 0), hex0);
disp <= outport(15 downto 0) when key(3)='1' else outport(31 downto 16);
process(clk, rst) is
begin
if(rst = '1') then
outport <= (others => '0');
elsif(clk'event and clk = '1') then
if(wr='1') then
outport <= gpio_in;
end if;
gpio_out <= X"000000" & SW;
end if;
end process;
end gpio;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 07.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_OUT : out std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; --Chip Enable
UB1 : out std_logic; --Upper Byte Enable
LB1 : out std_logic; --Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT)
begin
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
ADR_DAT_OUT_PROC: process (n_COUNT_ADR, n_COUNT_DAT) --Ausgabe Adresse und Daten
begin
--Adressen
COUNT_ADR_OUT(0) <= n_COUNT_ADR(0);
COUNT_ADR_OUT(1) <= n_COUNT_ADR(1);
COUNT_ADR_OUT(2) <= n_COUNT_ADR(2);
COUNT_ADR_OUT(3) <= n_COUNT_ADR(3);
COUNT_ADR_OUT(4) <= n_COUNT_ADR(4);
COUNT_ADR_OUT(5) <= n_COUNT_ADR(5);
COUNT_ADR_OUT(6) <= n_COUNT_ADR(6);
COUNT_ADR_OUT(7) <= n_COUNT_ADR(7);
COUNT_ADR_OUT(8) <= n_COUNT_ADR(8);
COUNT_ADR_OUT(9) <= n_COUNT_ADR(9);
COUNT_ADR_OUT(10) <= n_COUNT_ADR(10);
COUNT_ADR_OUT(11) <= n_COUNT_ADR(11);
COUNT_ADR_OUT(12) <= n_COUNT_ADR(12);
COUNT_ADR_OUT(13) <= n_COUNT_ADR(13);
COUNT_ADR_OUT(14) <= n_COUNT_ADR(14);
COUNT_ADR_OUT(15) <= n_COUNT_ADR(15);
COUNT_ADR_OUT(16) <= n_COUNT_ADR(16);
COUNT_ADR_OUT(17) <= n_COUNT_ADR(17);
COUNT_ADR_OUT(18) <= n_COUNT_ADR(18);
--Daten
COUNT_DAT_OUT(0) <= n_COUNT_DAT(0);
COUNT_DAT_OUT(1) <= n_COUNT_DAT(1);
COUNT_DAT_OUT(2) <= n_COUNT_DAT(2);
COUNT_DAT_OUT(3) <= n_COUNT_DAT(3);
COUNT_DAT_OUT(4) <= n_COUNT_DAT(4);
COUNT_DAT_OUT(5) <= n_COUNT_DAT(5);
COUNT_DAT_OUT(6) <= n_COUNT_DAT(6);
COUNT_DAT_OUT(7) <= n_COUNT_DAT(7);
COUNT_DAT_OUT(8) <= n_COUNT_DAT(8);
COUNT_DAT_OUT(9) <= n_COUNT_DAT(9);
COUNT_DAT_OUT(10) <= n_COUNT_DAT(10);
COUNT_DAT_OUT(11) <= n_COUNT_DAT(11);
COUNT_DAT_OUT(12) <= n_COUNT_DAT(12);
COUNT_DAT_OUT(13) <= n_COUNT_DAT(13);
COUNT_DAT_OUT(14) <= n_COUNT_DAT(14);
COUNT_DAT_OUT(15) <= n_COUNT_DAT(15);
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
end process;
end Behavioral;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 07.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_OUT : out std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; --Chip Enable
UB1 : out std_logic; --Upper Byte Enable
LB1 : out std_logic; --Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT)
begin
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
ADR_DAT_OUT_PROC: process (n_COUNT_ADR, n_COUNT_DAT) --Ausgabe Adresse und Daten
begin
--Adressen
COUNT_ADR_OUT(0) <= n_COUNT_ADR(0);
COUNT_ADR_OUT(1) <= n_COUNT_ADR(1);
COUNT_ADR_OUT(2) <= n_COUNT_ADR(2);
COUNT_ADR_OUT(3) <= n_COUNT_ADR(3);
COUNT_ADR_OUT(4) <= n_COUNT_ADR(4);
COUNT_ADR_OUT(5) <= n_COUNT_ADR(5);
COUNT_ADR_OUT(6) <= n_COUNT_ADR(6);
COUNT_ADR_OUT(7) <= n_COUNT_ADR(7);
COUNT_ADR_OUT(8) <= n_COUNT_ADR(8);
COUNT_ADR_OUT(9) <= n_COUNT_ADR(9);
COUNT_ADR_OUT(10) <= n_COUNT_ADR(10);
COUNT_ADR_OUT(11) <= n_COUNT_ADR(11);
COUNT_ADR_OUT(12) <= n_COUNT_ADR(12);
COUNT_ADR_OUT(13) <= n_COUNT_ADR(13);
COUNT_ADR_OUT(14) <= n_COUNT_ADR(14);
COUNT_ADR_OUT(15) <= n_COUNT_ADR(15);
COUNT_ADR_OUT(16) <= n_COUNT_ADR(16);
COUNT_ADR_OUT(17) <= n_COUNT_ADR(17);
COUNT_ADR_OUT(18) <= n_COUNT_ADR(18);
--Daten
COUNT_DAT_OUT(0) <= n_COUNT_DAT(0);
COUNT_DAT_OUT(1) <= n_COUNT_DAT(1);
COUNT_DAT_OUT(2) <= n_COUNT_DAT(2);
COUNT_DAT_OUT(3) <= n_COUNT_DAT(3);
COUNT_DAT_OUT(4) <= n_COUNT_DAT(4);
COUNT_DAT_OUT(5) <= n_COUNT_DAT(5);
COUNT_DAT_OUT(6) <= n_COUNT_DAT(6);
COUNT_DAT_OUT(7) <= n_COUNT_DAT(7);
COUNT_DAT_OUT(8) <= n_COUNT_DAT(8);
COUNT_DAT_OUT(9) <= n_COUNT_DAT(9);
COUNT_DAT_OUT(10) <= n_COUNT_DAT(10);
COUNT_DAT_OUT(11) <= n_COUNT_DAT(11);
COUNT_DAT_OUT(12) <= n_COUNT_DAT(12);
COUNT_DAT_OUT(13) <= n_COUNT_DAT(13);
COUNT_DAT_OUT(14) <= n_COUNT_DAT(14);
COUNT_DAT_OUT(15) <= n_COUNT_DAT(15);
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
end process;
end Behavioral;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 07.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_OUT : out std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; --Chip Enable
UB1 : out std_logic; --Upper Byte Enable
LB1 : out std_logic; --Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT)
begin
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
ADR_DAT_OUT_PROC: process (n_COUNT_ADR, n_COUNT_DAT) --Ausgabe Adresse und Daten
begin
--Adressen
COUNT_ADR_OUT(0) <= n_COUNT_ADR(0);
COUNT_ADR_OUT(1) <= n_COUNT_ADR(1);
COUNT_ADR_OUT(2) <= n_COUNT_ADR(2);
COUNT_ADR_OUT(3) <= n_COUNT_ADR(3);
COUNT_ADR_OUT(4) <= n_COUNT_ADR(4);
COUNT_ADR_OUT(5) <= n_COUNT_ADR(5);
COUNT_ADR_OUT(6) <= n_COUNT_ADR(6);
COUNT_ADR_OUT(7) <= n_COUNT_ADR(7);
COUNT_ADR_OUT(8) <= n_COUNT_ADR(8);
COUNT_ADR_OUT(9) <= n_COUNT_ADR(9);
COUNT_ADR_OUT(10) <= n_COUNT_ADR(10);
COUNT_ADR_OUT(11) <= n_COUNT_ADR(11);
COUNT_ADR_OUT(12) <= n_COUNT_ADR(12);
COUNT_ADR_OUT(13) <= n_COUNT_ADR(13);
COUNT_ADR_OUT(14) <= n_COUNT_ADR(14);
COUNT_ADR_OUT(15) <= n_COUNT_ADR(15);
COUNT_ADR_OUT(16) <= n_COUNT_ADR(16);
COUNT_ADR_OUT(17) <= n_COUNT_ADR(17);
COUNT_ADR_OUT(18) <= n_COUNT_ADR(18);
--Daten
COUNT_DAT_OUT(0) <= n_COUNT_DAT(0);
COUNT_DAT_OUT(1) <= n_COUNT_DAT(1);
COUNT_DAT_OUT(2) <= n_COUNT_DAT(2);
COUNT_DAT_OUT(3) <= n_COUNT_DAT(3);
COUNT_DAT_OUT(4) <= n_COUNT_DAT(4);
COUNT_DAT_OUT(5) <= n_COUNT_DAT(5);
COUNT_DAT_OUT(6) <= n_COUNT_DAT(6);
COUNT_DAT_OUT(7) <= n_COUNT_DAT(7);
COUNT_DAT_OUT(8) <= n_COUNT_DAT(8);
COUNT_DAT_OUT(9) <= n_COUNT_DAT(9);
COUNT_DAT_OUT(10) <= n_COUNT_DAT(10);
COUNT_DAT_OUT(11) <= n_COUNT_DAT(11);
COUNT_DAT_OUT(12) <= n_COUNT_DAT(12);
COUNT_DAT_OUT(13) <= n_COUNT_DAT(13);
COUNT_DAT_OUT(14) <= n_COUNT_DAT(14);
COUNT_DAT_OUT(15) <= n_COUNT_DAT(15);
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
end process;
end Behavioral;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 07.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_OUT : out std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; --Chip Enable
UB1 : out std_logic; --Upper Byte Enable
LB1 : out std_logic; --Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT)
begin
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
ADR_DAT_OUT_PROC: process (n_COUNT_ADR, n_COUNT_DAT) --Ausgabe Adresse und Daten
begin
--Adressen
COUNT_ADR_OUT(0) <= n_COUNT_ADR(0);
COUNT_ADR_OUT(1) <= n_COUNT_ADR(1);
COUNT_ADR_OUT(2) <= n_COUNT_ADR(2);
COUNT_ADR_OUT(3) <= n_COUNT_ADR(3);
COUNT_ADR_OUT(4) <= n_COUNT_ADR(4);
COUNT_ADR_OUT(5) <= n_COUNT_ADR(5);
COUNT_ADR_OUT(6) <= n_COUNT_ADR(6);
COUNT_ADR_OUT(7) <= n_COUNT_ADR(7);
COUNT_ADR_OUT(8) <= n_COUNT_ADR(8);
COUNT_ADR_OUT(9) <= n_COUNT_ADR(9);
COUNT_ADR_OUT(10) <= n_COUNT_ADR(10);
COUNT_ADR_OUT(11) <= n_COUNT_ADR(11);
COUNT_ADR_OUT(12) <= n_COUNT_ADR(12);
COUNT_ADR_OUT(13) <= n_COUNT_ADR(13);
COUNT_ADR_OUT(14) <= n_COUNT_ADR(14);
COUNT_ADR_OUT(15) <= n_COUNT_ADR(15);
COUNT_ADR_OUT(16) <= n_COUNT_ADR(16);
COUNT_ADR_OUT(17) <= n_COUNT_ADR(17);
COUNT_ADR_OUT(18) <= n_COUNT_ADR(18);
--Daten
COUNT_DAT_OUT(0) <= n_COUNT_DAT(0);
COUNT_DAT_OUT(1) <= n_COUNT_DAT(1);
COUNT_DAT_OUT(2) <= n_COUNT_DAT(2);
COUNT_DAT_OUT(3) <= n_COUNT_DAT(3);
COUNT_DAT_OUT(4) <= n_COUNT_DAT(4);
COUNT_DAT_OUT(5) <= n_COUNT_DAT(5);
COUNT_DAT_OUT(6) <= n_COUNT_DAT(6);
COUNT_DAT_OUT(7) <= n_COUNT_DAT(7);
COUNT_DAT_OUT(8) <= n_COUNT_DAT(8);
COUNT_DAT_OUT(9) <= n_COUNT_DAT(9);
COUNT_DAT_OUT(10) <= n_COUNT_DAT(10);
COUNT_DAT_OUT(11) <= n_COUNT_DAT(11);
COUNT_DAT_OUT(12) <= n_COUNT_DAT(12);
COUNT_DAT_OUT(13) <= n_COUNT_DAT(13);
COUNT_DAT_OUT(14) <= n_COUNT_DAT(14);
COUNT_DAT_OUT(15) <= n_COUNT_DAT(15);
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
end process;
end Behavioral;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity C1 is
port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
F: out std_logic
);
end C1;
architecture c1_estr of C1 is
begin
F <= A or B or C;
end c1_estr; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
entity cronometro is
port (
-- Entradas
startStop: in std_logic;
puestaCero: in std_logic;
clk: in std_logic;
rst: in std_logic;
-- Salidas
rightSegs: out std_logic_vector(7 downto 0);
leftSegs: out std_logic_vector(7 downto 0);
puntoDec: out std_logic
);
end cronometro;
architecture Behavioral of cronometro is
signal ssDebounced,ssDebFallEdge,ssDebRiseEdge: std_logic;
signal pODebounced,pODebFallEdge,pODebRiseEdge: std_logic;
signal t: std_logic;
signal salidaCont5kk: std_logic_vector(22 downto 0);
signal salidaContDecimas, salidaContUnidades,salidaContDecenas: std_logic_vector(3 downto 0);
signal cuentaDecimas, cuentaUnidades, cuentaDecenas: std_logic;
signal cs1 : std_logic_vector( 22 downto 0 );
signal cs2,cs3,cs4 : std_logic_vector( 3 downto 0 );
signal lit1,lit2,lit3: std_logic;
component debouncer
port(rst: in std_logic;
clk: in std_logic;
x: in std_logic;
xDeb: out std_logic;
xDebFallingEdge: out std_logic;
xDebRisingEdge: out std_logic);
end component;
component binToSeg is
port (
bin: in std_logic_vector(3 downto 0);
displaySeg: out std_logic_vector(7 downto 0) -- 7 = A / 6 = B / ... / 0 = H
);
end component;
begin
-- ELIMINACION DE REBOTES EN LOS PUSHBUTTONS
debouncerStartStop: debouncer port map (rst,clk,startStop,ssDebounced,ssDebFallEdge,ssDebRiseEdge);
debouncerPuestaCero: debouncer port map (rst,clk,puestaCero,pODebounced,pODebFallEdge,pODebRiseEdge);
-- CONTADORES
contMod5kk:
process( clk, cs1, rst, pODebFallEdge, ssDebFallEdge )
begin
salidaCont5kk <= cs1;
if rst = '0' then
cs1 <= conv_std_logic_vector( 0 , 23 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs1 <= conv_std_logic_vector( 0 , 23 );
elsif t = '1' then
if cs1 = conv_std_logic_vector( 4999999 , 23 ) then
cs1 <= conv_std_logic_vector( 0 , 23 );
else
cs1 <= cs1 + 1;
end if;
end if;
end if;
end process;
-- contDecimas cuenta cuando se tenga 4.999.999 = 10011000100101100111111 en cont5Millones
cuentaDecimas <= salidaCont5kk(22) and salidaCont5kk(19) and salidaCont5kk(18) and salidaCont5kk(14) and salidaCont5kk(11) and
salidaCont5kk(9) and salidaCont5kk(8) and salidaCont5kk(5) and salidaCont5kk(4) and salidaCont5kk(3) and
salidaCont5kk(2) and salidaCont5kk(1) and salidaCont5kk(0);
contDecimas:
process( clk, cs2, rst, pODebFallEdge, cuentaDecimas )
begin
salidaContDecimas <= cs2;
if rst = '0' then
cs2 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs2 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaDecimas = '1' then
if cs2 = conv_std_logic_vector( 9 , 4 ) then
cs2 <= conv_std_logic_vector( 0 , 4 );
else
cs2 <= cs2 + 1;
end if;
end if;
end if;
end process;
-- contUnidades cuenta cuando se tenga 9 = 1001 en contDecimas
cuentaUnidades <= (salidaContDecimas(3) and salidaContDecimas(0)) and cuentaDecimas;
contUnidades:
process( clk, cs3, rst, pODebFallEdge, cuentaUnidades )
begin
salidaContUnidades <= cs3;
if rst = '0' then
cs3 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs3 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaUnidades = '1' then
if cs3 = conv_std_logic_vector( 9 , 4 ) then
cs3 <= conv_std_logic_vector( 0 , 4 );
else
cs3 <= cs3 + 1;
end if;
end if;
end if;
end process;
cuentaDecenas <= (salidaContUnidades(3) and salidaContUnidades(0)) and (cuentaDecimas and cuentaUnidades);
contDecenas:
process( clk, cs4, rst, pODebFallEdge, cuentaDecenas )
begin
salidaContDecenas <= cs4;
if rst = '0' then
cs4 <= conv_std_logic_vector( 0 , 4 );
elsif clk'event and clk = '1' then
if pODebFallEdge = '1' then
cs4 <= conv_std_logic_vector( 0 , 4 );
elsif cuentaDecenas = '1' then
if cs4 = conv_std_logic_vector( 5 , 4 ) then
cs4 <= conv_std_logic_vector( 0 , 4 );
else
cs4 <= cs4 + 1;
end if;
end if;
end if;
end process;
-- BIESTABLE T
-- Usamos el flanco de bajada (fall) porque la placa tiene logica negativa
biestableT:
process(clk)
begin
if (rst = '0') then
t <= '0';
elsif (clk'event and clk='1') then
if (ssDebFallEdge = '1') then
t <= not (t);
end if;
end if;
end process;
parpadeoPuntoDecimal:
process(salidaContDecimas)
begin
lit1 <= not salidaContDecimas(3) and not salidaContDecimas(2);
lit2 <= not salidaContDecimas(3) and not salidaContDecimas(1) and not salidaContDecimas(0);
lit3 <= lit1 or lit2;
if (lit3 = '1') then
puntoDec <= '1';
else
puntoDec <= '0';
end if;
end process;
-- DISPLAYS 8 SEGMENTOS
decenasSeg: binToSeg port map (salidaContDecenas,leftSegs);
unidadesSeg: binToSeg port map (salidaContUnidades,rightSegs);
end Behavioral;
-- x3 x2 x1 x0 z
--------------------
--0 0 0 0 0 1
--1 0 0 0 1 1
--2 0 0 1 0 1
--3 0 0 1 1 1
--4 0 1 0 0 1
--5 0 1 0 1 0
--6 0 1 1 0 0
--7 0 1 1 1 0
--8 1 0 0 0 0
--9 1 0 0 1 0
-- Mapa de Karnaugh ==> FLASH = (¬ x3)(¬ x2) + (¬ x3)(¬ x1)(¬ x0)
|
-- Copyright (c) 2002-2009 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.numeric_std.all;
use work.ffaccel_globals.all;
use work.ffaccel_gcu_opcodes.all;
use work.ffaccel_imem_mau.all;
use work.tce_util.all;
entity ffaccel_ifetch is
generic (
no_glock_loopback_g : std_logic := '0';
bypass_fetchblock_register : boolean := false;
bypass_pc_register : boolean := false;
bypass_decoder_registers : boolean := false;
extra_fetch_cycles : integer := 0;
sync_reset_g : boolean := false;
debug_logic_g : boolean := false;
enable_loop_buffer_g : boolean := false;
enable_infloop_buffer_g : boolean := false;
enable_irf_g : boolean := false;
irf_size_g : integer := 0;
pc_init_g : std_logic_vector(IMEMADDRWIDTH-1 downto 0) := (others => '0'));
port (
-- program counter in
pc_in : in std_logic_vector (IMEMADDRWIDTH-1 downto 0);
--return address out
ra_out : out std_logic_vector (IMEMADDRWIDTH-1 downto 0);
-- return address in
ra_in : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);
-- ifetch control signals
pc_load : in std_logic;
ra_load : in std_logic;
pc_opcode : in std_logic_vector(0 downto 0);
--instruction memory interface
imem_data : in std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
imem_addr : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
imem_en_x : out std_logic;
fetchblock : out std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
busy : in std_logic;
-- global lock
glock : out std_logic;
-- external control interface
fetch_en : in std_logic; --fetch_enable
-- debugger signals
db_lockreq : in std_logic;
db_rstx : in std_logic;
db_pc : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
db_cyclecnt : out std_logic_vector(64-1 downto 0);
db_lockcnt : out std_logic_vector(64-1 downto 0);
clk : in std_logic;
rstx : in std_logic);
end ffaccel_ifetch;
architecture rtl_andor of ffaccel_ifetch is
-- signals for program counter.
signal pc_reg : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal pc_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal pc_prev_reg : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal next_pc : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal increased_pc : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal return_addr_reg : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
-- internal signals for initializing and locking execution.
signal lock : std_logic;
signal mem_en_lock_r : std_logic;
-- Delay/latency from retrieving instruction block from instruction memory.
constant IFETCH_DELAY : integer := 1 + extra_fetch_cycles;
-- Delay/latency from pc register to dispatching instruction.
constant PC_TO_DISPATCH_DELAY : integer :=
to_int(not bypass_fetchblock_register) +
IFETCH_DELAY;
-- Delay/latency from control flow operation to dispatching instruction.
constant NEXT_TO_DISPATCH_DELAY : integer :=
PC_TO_DISPATCH_DELAY + to_int(not bypass_pc_register);
signal reset_cntr : integer range 0 to IFETCH_DELAY;
signal reset_lock : std_logic;
-- Loopbuffer signals, or placeholders if lb is not enabled
-- Placeholder signals for loop buffer ports/constants
constant LBUFMAXITER : integer := 1;
constant LBUFMAXDEPTH : integer := 1;
constant IFE_LBUFS : integer := 1;
constant IFE_INFLOOP : integer := 1;
signal o1data : std_logic_vector(LBUFMAXITER-1 downto 0);
signal o1load : std_logic;
signal loop_start_out : std_logic;
signal loop_len_out : std_logic_vector(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
signal loop_iter_out : std_logic_vector(LBUFMAXITER-1 downto 0);
signal iteration_count : std_logic_vector(LBUFMAXITER-1 downto 0);
signal pc_after_loop : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal lockcnt_r, cyclecnt_r : unsigned(64 - 1 downto 0);
signal db_pc_next : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
constant db_pc_start : std_logic_vector(IMEMADDRWIDTH-1 downto 0)
:= (others => '0');
begin
-- enable instruction memory.
imem_en_x <= '0' when (fetch_en = '1' and mem_en_lock_r = '0') else '1';
-- do not fetch new instruction when processor is locked.
imem_addr <= pc_wire;
-- propagate lock to global lock
glock <= busy or reset_lock or (not (fetch_en or no_glock_loopback_g));
ra_out <= return_addr_reg;
lock <= not fetch_en or busy or mem_en_lock_r;
pc_update_generate_0 : if not enable_irf_g generate
pc_update_proc : process (clk)
begin
if not sync_reset_g and rstx = '0' then
pc_reg <= pc_init_g;
pc_prev_reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge.
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
pc_reg <= db_pc_start;
pc_prev_reg <= (others => '0');
elsif lock = '0' then
pc_reg <= next_pc;
if bypass_pc_register and bypass_fetchblock_register
and bypass_decoder_registers and pc_load = '1' then
pc_prev_reg <= pc_in;
else
pc_prev_reg <= pc_reg;
end if;
end if;
end if;
end process pc_update_proc;
end generate pc_update_generate_0;
-----------------------------------------------------------------------------
ra_block : block
signal ra_source : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
begin -- block ra_block
-- Default choice generate
ra_source_select_generate_0 : if not enable_irf_g and not bypass_pc_register generate
ra_source <= increased_pc;
end generate ra_source_select_generate_0;
-- Choice enabled by generic
ra_source_select_generate_1 : if not enable_irf_g and bypass_pc_register generate
ra_source <= pc_reg;
end generate ra_source_select_generate_1;
-- When using IRF
ra_source_select_generate_2 : if enable_irf_g generate
ra_source <= pc_prev_reg;
end generate ra_source_select_generate_2;
ra_update_proc : process (clk)
begin -- process ra_update_proc
if not sync_reset_g and rstx = '0' then -- asynchronous reset (active low)
return_addr_reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
return_addr_reg <= (others => '0');
elsif lock = '0' then
-- return address
if (ra_load = '1') then
return_addr_reg <= ra_in;
elsif (pc_load = '1' and unsigned(pc_opcode) = IFE_CALL) then
-- return address transformed to same form as all others addresses
-- provided as input
return_addr_reg <= ra_source;
end if;
end if;
end if;
end process ra_update_proc;
end block ra_block;
-----------------------------------------------------------------------------
-- Keeps memory enable inactive during reset
imem_lock_proc : process (clk)
begin
if not sync_reset_g and rstx = '0' then
mem_en_lock_r <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
mem_en_lock_r <= '1';
else
mem_en_lock_r <= '0';
end if;
end if;
end process imem_lock_proc;
-----------------------------------------------------------------------------
-- Default fetch implementation
fetch_block_registered_generate : if
not bypass_fetchblock_register generate
fetch_block : block
signal instruction_reg : std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH*
(extra_fetch_cycles+1)-1 downto 0);
begin -- block fetch_block
fetch_block_proc : process (clk)
begin -- process fetch_block_proc
if not sync_reset_g and rstx = '0' then -- asynchronous reset (active low)
instruction_reg <= (others => '0');
reset_cntr <= 0;
reset_lock <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
instruction_reg <= (others => '0');
reset_cntr <= 0;
reset_lock <= '1';
elsif lock = '0' then
if reset_cntr < IFETCH_DELAY then
reset_cntr <= reset_cntr + 1;
else
reset_lock <= '0';
end if;
if (extra_fetch_cycles > 0) then
instruction_reg(instruction_reg'length-fetchblock'length-1 downto 0)
<= instruction_reg(instruction_reg'length-1 downto fetchblock'length);
end if;
instruction_reg(instruction_reg'length-1
downto instruction_reg'length - fetchblock'length)
<= imem_data;
end if;
end if;
end process fetch_block_proc;
fetchblock <= instruction_reg(fetchblock'length-1 downto 0);
end block fetch_block;
end generate fetch_block_registered_generate;
-- Fetch implementation without fetch register.
fetch_block_bypassed_generate : if
not (not bypass_fetchblock_register) generate
fetch_block : block
begin -- block fetch_block
fetch_block_proc : process (clk)
begin -- process fetch_block_proc
if not sync_reset_g and rstx = '0' then -- asynchronous reset (active low)
reset_lock <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
reset_lock <= '1';
elsif lock = '0' then
reset_lock <= '0';
end if;
end if;
end process fetch_block_proc;
fetchblock <= imem_data;
end block fetch_block;
end generate fetch_block_bypassed_generate;
-----------------------------------------------------------------------------
loopbuf_logic : if enable_loop_buffer_g generate
-- Loop buffer signals --
signal start_looping : std_logic;
signal start_looping_r : std_logic_vector(NEXT_TO_DISPATCH_DELAY-1
downto 0);
signal loop_length, loop_length_reg
: std_logic_vector(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
signal loop_iter_reg : std_logic_vector(LBUFMAXITER-1 downto 0);
signal loop_iter_temp_reg : std_logic_vector(LBUFMAXITER-1 downto 0);
begin
assert not enable_irf_g
report "IRF is not supported with loop buffer!"
severity failure;
-- Loop buffer setup operation logic --
start_looping <= '1' when (pc_load = '1' and
unsigned(pc_opcode) = IFE_LBUFS) else
'0';
iteration_count <= o1data(LBUFMAXITER-1 downto 0)
when o1load = '1' else
loop_iter_temp_reg;
loop_length <= pc_in(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
process (clk)
begin
if not sync_reset_g and rstx = '0' then
start_looping_r <= (others => '0');
loop_length_reg <= (others => '0');
loop_iter_reg <= (others => '0');
loop_iter_temp_reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
-- Loop buffer control --
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
start_looping_r <= (others => '0');
loop_length_reg <= (others => '0');
loop_iter_reg <= (others => '0');
loop_iter_temp_reg <= (others => '0');
elsif lock = '0' then
if (start_looping = '1' and
unsigned(iteration_count) /= 0) then
loop_length_reg <= loop_length;
loop_iter_reg <= iteration_count;
start_looping_r(0) <= '1';
else
start_looping_r(0) <= '0';
end if;
if o1load = '1' then
loop_iter_temp_reg <= o1data(LBUFMAXITER-1 downto 0);
end if;
-- Delay slots for lbufs are introduced to avoid need of pipeline
-- flushing in case the loop is skipped with iteration count of zero.
start_looping_r(start_looping_r'left downto 1) <=
start_looping_r(start_looping_r'left-1 downto 0);
end if;
end if;
end process;
loop_start_out <= start_looping_r(start_looping_r'left);
loop_iter_out <= loop_iter_reg;
loop_len_out <= loop_length_reg;
pc_after_loop <= std_logic_vector(
unsigned(increased_pc) + unsigned(loop_length));
end generate;
infloop_logic : if enable_infloop_buffer_g generate
signal start_looping : std_logic;
signal start_looping_r
: std_logic_vector(NEXT_TO_DISPATCH_DELAY-1 downto 0);
signal loop_length, loop_length_reg
: std_logic_vector(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
begin
-- infinity loop operation control logic --
start_looping <= '1' when (pc_load = '1' and
unsigned(pc_opcode) = IFE_INFLOOP) else
'0';
loop_length <= pc_in(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
process (clk)
begin
if not sync_reset_g and rstx = '0' then
start_looping_r <= (others => '0');
loop_length_reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
-- Loop buffer control --
if sync_reset_g and rstx = '0' then
start_looping_r <= (others => '0');
loop_length_reg <= (others => '0');
elsif lock = '0' then
if (start_looping = '1' and to_uint(loop_length) /= 0) then
assert to_uint(loop_length) <= LBUFMAXDEPTH
report "The loop body size exceeds loop buffer capacity!"
severity failure;
loop_length_reg <= loop_length;
start_looping_r(0) <= '1';
else
start_looping_r(0) <= '0';
end if;
-- Delay slots for lbufs are introduced to avoid need of pipeline
-- flushing in case the loop is skipped with iteration count of
-- zero.
start_looping_r(start_looping_r'left downto 1) <=
start_looping_r(start_looping_r'left-1 downto 0);
end if;
end if;
end process;
loop_start_out <= start_looping_r(start_looping_r'left);
loop_len_out <= loop_length_reg;
end generate infloop_logic;
--------------------------------------------------------------------------------
default_pc_generate: if not bypass_pc_register generate
pc_wire <= pc_reg when (lock = '0') else pc_prev_reg;
-- increase program counter
increased_pc <= std_logic_vector(unsigned(pc_wire) + IMEMWIDTHINMAUS);
sel_next_pc : process (pc_load, pc_in, increased_pc, pc_opcode)
begin
if pc_load = '1' and (unsigned(pc_opcode) = IFE_CALL or unsigned(pc_opcode) = IFE_JUMP) then
next_pc <= pc_in;
else -- no branch
next_pc <= increased_pc;
end if;
end process sel_next_pc;
end generate default_pc_generate;
bypass_pc_register_generate: if bypass_pc_register generate
-- increase program counter
increased_pc <= std_logic_vector(unsigned(pc_wire) + IMEMWIDTHINMAUS);
sel_next_pc : process (pc_in, pc_reg, increased_pc ,
pc_load, pc_opcode)
begin
if pc_load = '1' and (unsigned(pc_opcode) = IFE_CALL or unsigned(pc_opcode) = IFE_JUMP) then
pc_wire <= pc_in;
next_pc <= increased_pc;
else -- no branch
pc_wire <= pc_reg;
next_pc <= increased_pc;
end if;
end process sel_next_pc;
end generate bypass_pc_register_generate;
-----------------------------------------------------------------------------
debug_counters : if debug_logic_g generate
-----------------------------------------------------------------------------
-- Debugger processes and signal assignments
-----------------------------------------------------------------------------
db_counters : process(clk)
begin
if not sync_reset_g and rstx = '0' then -- async reset (active low)
lockcnt_r <= (others => '0');
cyclecnt_r <= (others => '0');
elsif rising_edge(clk) then
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
lockcnt_r <= (others => '0');
cyclecnt_r <= (others => '0');
elsif db_lockreq = '0' then
if lock = '1' then
lockcnt_r <= lockcnt_r + 1;
else
cyclecnt_r <= cyclecnt_r + 1;
end if;
end if;
end if;
end process;
db_cyclecnt <= std_logic_vector(cyclecnt_r);
db_lockcnt <= std_logic_vector(lockcnt_r);
db_pc <= pc_reg;
db_pc_next <= next_pc;
end generate debug_counters;
end rtl_andor;
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