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-- Copyright (c) 2002-2009 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.numeric_std.all;
use work.ffaccel_globals.all;
use work.ffaccel_gcu_opcodes.all;
use work.ffaccel_imem_mau.all;
use work.tce_util.all;
entity ffaccel_ifetch is
generic (
no_glock_loopback_g : std_logic := '0';
bypass_fetchblock_register : boolean := false;
bypass_pc_register : boolean := false;
bypass_decoder_registers : boolean := false;
extra_fetch_cycles : integer := 0;
sync_reset_g : boolean := false;
debug_logic_g : boolean := false;
enable_loop_buffer_g : boolean := false;
enable_infloop_buffer_g : boolean := false;
enable_irf_g : boolean := false;
irf_size_g : integer := 0;
pc_init_g : std_logic_vector(IMEMADDRWIDTH-1 downto 0) := (others => '0'));
port (
-- program counter in
pc_in : in std_logic_vector (IMEMADDRWIDTH-1 downto 0);
--return address out
ra_out : out std_logic_vector (IMEMADDRWIDTH-1 downto 0);
-- return address in
ra_in : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);
-- ifetch control signals
pc_load : in std_logic;
ra_load : in std_logic;
pc_opcode : in std_logic_vector(0 downto 0);
--instruction memory interface
imem_data : in std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
imem_addr : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
imem_en_x : out std_logic;
fetchblock : out std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH-1 downto 0);
busy : in std_logic;
-- global lock
glock : out std_logic;
-- external control interface
fetch_en : in std_logic; --fetch_enable
-- debugger signals
db_lockreq : in std_logic;
db_rstx : in std_logic;
db_pc : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
db_cyclecnt : out std_logic_vector(64-1 downto 0);
db_lockcnt : out std_logic_vector(64-1 downto 0);
clk : in std_logic;
rstx : in std_logic);
end ffaccel_ifetch;
architecture rtl_andor of ffaccel_ifetch is
-- signals for program counter.
signal pc_reg : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal pc_wire : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal pc_prev_reg : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal next_pc : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal increased_pc : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal return_addr_reg : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
-- internal signals for initializing and locking execution.
signal lock : std_logic;
signal mem_en_lock_r : std_logic;
-- Delay/latency from retrieving instruction block from instruction memory.
constant IFETCH_DELAY : integer := 1 + extra_fetch_cycles;
-- Delay/latency from pc register to dispatching instruction.
constant PC_TO_DISPATCH_DELAY : integer :=
to_int(not bypass_fetchblock_register) +
IFETCH_DELAY;
-- Delay/latency from control flow operation to dispatching instruction.
constant NEXT_TO_DISPATCH_DELAY : integer :=
PC_TO_DISPATCH_DELAY + to_int(not bypass_pc_register);
signal reset_cntr : integer range 0 to IFETCH_DELAY;
signal reset_lock : std_logic;
-- Loopbuffer signals, or placeholders if lb is not enabled
-- Placeholder signals for loop buffer ports/constants
constant LBUFMAXITER : integer := 1;
constant LBUFMAXDEPTH : integer := 1;
constant IFE_LBUFS : integer := 1;
constant IFE_INFLOOP : integer := 1;
signal o1data : std_logic_vector(LBUFMAXITER-1 downto 0);
signal o1load : std_logic;
signal loop_start_out : std_logic;
signal loop_len_out : std_logic_vector(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
signal loop_iter_out : std_logic_vector(LBUFMAXITER-1 downto 0);
signal iteration_count : std_logic_vector(LBUFMAXITER-1 downto 0);
signal pc_after_loop : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
signal lockcnt_r, cyclecnt_r : unsigned(64 - 1 downto 0);
signal db_pc_next : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
constant db_pc_start : std_logic_vector(IMEMADDRWIDTH-1 downto 0)
:= (others => '0');
begin
-- enable instruction memory.
imem_en_x <= '0' when (fetch_en = '1' and mem_en_lock_r = '0') else '1';
-- do not fetch new instruction when processor is locked.
imem_addr <= pc_wire;
-- propagate lock to global lock
glock <= busy or reset_lock or (not (fetch_en or no_glock_loopback_g));
ra_out <= return_addr_reg;
lock <= not fetch_en or busy or mem_en_lock_r;
pc_update_generate_0 : if not enable_irf_g generate
pc_update_proc : process (clk)
begin
if not sync_reset_g and rstx = '0' then
pc_reg <= pc_init_g;
pc_prev_reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge.
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
pc_reg <= db_pc_start;
pc_prev_reg <= (others => '0');
elsif lock = '0' then
pc_reg <= next_pc;
if bypass_pc_register and bypass_fetchblock_register
and bypass_decoder_registers and pc_load = '1' then
pc_prev_reg <= pc_in;
else
pc_prev_reg <= pc_reg;
end if;
end if;
end if;
end process pc_update_proc;
end generate pc_update_generate_0;
-----------------------------------------------------------------------------
ra_block : block
signal ra_source : std_logic_vector(IMEMADDRWIDTH-1 downto 0);
begin -- block ra_block
-- Default choice generate
ra_source_select_generate_0 : if not enable_irf_g and not bypass_pc_register generate
ra_source <= increased_pc;
end generate ra_source_select_generate_0;
-- Choice enabled by generic
ra_source_select_generate_1 : if not enable_irf_g and bypass_pc_register generate
ra_source <= pc_reg;
end generate ra_source_select_generate_1;
-- When using IRF
ra_source_select_generate_2 : if enable_irf_g generate
ra_source <= pc_prev_reg;
end generate ra_source_select_generate_2;
ra_update_proc : process (clk)
begin -- process ra_update_proc
if not sync_reset_g and rstx = '0' then -- asynchronous reset (active low)
return_addr_reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
return_addr_reg <= (others => '0');
elsif lock = '0' then
-- return address
if (ra_load = '1') then
return_addr_reg <= ra_in;
elsif (pc_load = '1' and unsigned(pc_opcode) = IFE_CALL) then
-- return address transformed to same form as all others addresses
-- provided as input
return_addr_reg <= ra_source;
end if;
end if;
end if;
end process ra_update_proc;
end block ra_block;
-----------------------------------------------------------------------------
-- Keeps memory enable inactive during reset
imem_lock_proc : process (clk)
begin
if not sync_reset_g and rstx = '0' then
mem_en_lock_r <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
mem_en_lock_r <= '1';
else
mem_en_lock_r <= '0';
end if;
end if;
end process imem_lock_proc;
-----------------------------------------------------------------------------
-- Default fetch implementation
fetch_block_registered_generate : if
not bypass_fetchblock_register generate
fetch_block : block
signal instruction_reg : std_logic_vector(IMEMWIDTHINMAUS*IMEMMAUWIDTH*
(extra_fetch_cycles+1)-1 downto 0);
begin -- block fetch_block
fetch_block_proc : process (clk)
begin -- process fetch_block_proc
if not sync_reset_g and rstx = '0' then -- asynchronous reset (active low)
instruction_reg <= (others => '0');
reset_cntr <= 0;
reset_lock <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
instruction_reg <= (others => '0');
reset_cntr <= 0;
reset_lock <= '1';
elsif lock = '0' then
if reset_cntr < IFETCH_DELAY then
reset_cntr <= reset_cntr + 1;
else
reset_lock <= '0';
end if;
if (extra_fetch_cycles > 0) then
instruction_reg(instruction_reg'length-fetchblock'length-1 downto 0)
<= instruction_reg(instruction_reg'length-1 downto fetchblock'length);
end if;
instruction_reg(instruction_reg'length-1
downto instruction_reg'length - fetchblock'length)
<= imem_data;
end if;
end if;
end process fetch_block_proc;
fetchblock <= instruction_reg(fetchblock'length-1 downto 0);
end block fetch_block;
end generate fetch_block_registered_generate;
-- Fetch implementation without fetch register.
fetch_block_bypassed_generate : if
not (not bypass_fetchblock_register) generate
fetch_block : block
begin -- block fetch_block
fetch_block_proc : process (clk)
begin -- process fetch_block_proc
if not sync_reset_g and rstx = '0' then -- asynchronous reset (active low)
reset_lock <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
reset_lock <= '1';
elsif lock = '0' then
reset_lock <= '0';
end if;
end if;
end process fetch_block_proc;
fetchblock <= imem_data;
end block fetch_block;
end generate fetch_block_bypassed_generate;
-----------------------------------------------------------------------------
loopbuf_logic : if enable_loop_buffer_g generate
-- Loop buffer signals --
signal start_looping : std_logic;
signal start_looping_r : std_logic_vector(NEXT_TO_DISPATCH_DELAY-1
downto 0);
signal loop_length, loop_length_reg
: std_logic_vector(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
signal loop_iter_reg : std_logic_vector(LBUFMAXITER-1 downto 0);
signal loop_iter_temp_reg : std_logic_vector(LBUFMAXITER-1 downto 0);
begin
assert not enable_irf_g
report "IRF is not supported with loop buffer!"
severity failure;
-- Loop buffer setup operation logic --
start_looping <= '1' when (pc_load = '1' and
unsigned(pc_opcode) = IFE_LBUFS) else
'0';
iteration_count <= o1data(LBUFMAXITER-1 downto 0)
when o1load = '1' else
loop_iter_temp_reg;
loop_length <= pc_in(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
process (clk)
begin
if not sync_reset_g and rstx = '0' then
start_looping_r <= (others => '0');
loop_length_reg <= (others => '0');
loop_iter_reg <= (others => '0');
loop_iter_temp_reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
-- Loop buffer control --
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
start_looping_r <= (others => '0');
loop_length_reg <= (others => '0');
loop_iter_reg <= (others => '0');
loop_iter_temp_reg <= (others => '0');
elsif lock = '0' then
if (start_looping = '1' and
unsigned(iteration_count) /= 0) then
loop_length_reg <= loop_length;
loop_iter_reg <= iteration_count;
start_looping_r(0) <= '1';
else
start_looping_r(0) <= '0';
end if;
if o1load = '1' then
loop_iter_temp_reg <= o1data(LBUFMAXITER-1 downto 0);
end if;
-- Delay slots for lbufs are introduced to avoid need of pipeline
-- flushing in case the loop is skipped with iteration count of zero.
start_looping_r(start_looping_r'left downto 1) <=
start_looping_r(start_looping_r'left-1 downto 0);
end if;
end if;
end process;
loop_start_out <= start_looping_r(start_looping_r'left);
loop_iter_out <= loop_iter_reg;
loop_len_out <= loop_length_reg;
pc_after_loop <= std_logic_vector(
unsigned(increased_pc) + unsigned(loop_length));
end generate;
infloop_logic : if enable_infloop_buffer_g generate
signal start_looping : std_logic;
signal start_looping_r
: std_logic_vector(NEXT_TO_DISPATCH_DELAY-1 downto 0);
signal loop_length, loop_length_reg
: std_logic_vector(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
begin
-- infinity loop operation control logic --
start_looping <= '1' when (pc_load = '1' and
unsigned(pc_opcode) = IFE_INFLOOP) else
'0';
loop_length <= pc_in(bit_width(LBUFMAXDEPTH+1)-1 downto 0);
process (clk)
begin
if not sync_reset_g and rstx = '0' then
start_looping_r <= (others => '0');
loop_length_reg <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
-- Loop buffer control --
if sync_reset_g and rstx = '0' then
start_looping_r <= (others => '0');
loop_length_reg <= (others => '0');
elsif lock = '0' then
if (start_looping = '1' and to_uint(loop_length) /= 0) then
assert to_uint(loop_length) <= LBUFMAXDEPTH
report "The loop body size exceeds loop buffer capacity!"
severity failure;
loop_length_reg <= loop_length;
start_looping_r(0) <= '1';
else
start_looping_r(0) <= '0';
end if;
-- Delay slots for lbufs are introduced to avoid need of pipeline
-- flushing in case the loop is skipped with iteration count of
-- zero.
start_looping_r(start_looping_r'left downto 1) <=
start_looping_r(start_looping_r'left-1 downto 0);
end if;
end if;
end process;
loop_start_out <= start_looping_r(start_looping_r'left);
loop_len_out <= loop_length_reg;
end generate infloop_logic;
--------------------------------------------------------------------------------
default_pc_generate: if not bypass_pc_register generate
pc_wire <= pc_reg when (lock = '0') else pc_prev_reg;
-- increase program counter
increased_pc <= std_logic_vector(unsigned(pc_wire) + IMEMWIDTHINMAUS);
sel_next_pc : process (pc_load, pc_in, increased_pc, pc_opcode)
begin
if pc_load = '1' and (unsigned(pc_opcode) = IFE_CALL or unsigned(pc_opcode) = IFE_JUMP) then
next_pc <= pc_in;
else -- no branch
next_pc <= increased_pc;
end if;
end process sel_next_pc;
end generate default_pc_generate;
bypass_pc_register_generate: if bypass_pc_register generate
-- increase program counter
increased_pc <= std_logic_vector(unsigned(pc_wire) + IMEMWIDTHINMAUS);
sel_next_pc : process (pc_in, pc_reg, increased_pc ,
pc_load, pc_opcode)
begin
if pc_load = '1' and (unsigned(pc_opcode) = IFE_CALL or unsigned(pc_opcode) = IFE_JUMP) then
pc_wire <= pc_in;
next_pc <= increased_pc;
else -- no branch
pc_wire <= pc_reg;
next_pc <= increased_pc;
end if;
end process sel_next_pc;
end generate bypass_pc_register_generate;
-----------------------------------------------------------------------------
debug_counters : if debug_logic_g generate
-----------------------------------------------------------------------------
-- Debugger processes and signal assignments
-----------------------------------------------------------------------------
db_counters : process(clk)
begin
if not sync_reset_g and rstx = '0' then -- async reset (active low)
lockcnt_r <= (others => '0');
cyclecnt_r <= (others => '0');
elsif rising_edge(clk) then
if (sync_reset_g and rstx = '0') or db_rstx = '0' then
lockcnt_r <= (others => '0');
cyclecnt_r <= (others => '0');
elsif db_lockreq = '0' then
if lock = '1' then
lockcnt_r <= lockcnt_r + 1;
else
cyclecnt_r <= cyclecnt_r + 1;
end if;
end if;
end if;
end process;
db_cyclecnt <= std_logic_vector(cyclecnt_r);
db_lockcnt <= std_logic_vector(lockcnt_r);
db_pc <= pc_reg;
db_pc_next <= next_pc;
end generate debug_counters;
end rtl_andor;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity or00 is
port(
clko: in std_logic ;
codopo: in std_logic_vector ( 3 downto 0 );
portAo: in std_logic_vector ( 7 downto 0 );
portBo: in std_logic_vector ( 7 downto 0 );
inFlago: in std_logic ;
outo: out std_logic_vector ( 7 downto 0 );
outFlago: out std_logic );
end;
architecture or0 of or00 is
begin
por: process(codopo, portAo, portBo)
begin
if(codopo = "0010") then
outo <= portAo or portBo;
outFlago <= '1';
else
outo <= (others => 'Z');
outFlago <= 'Z';
end if;
end process por;
-- por: process(clko, codopo, inFlago)
-- --variable auxo: bit:='0';
-- begin
-- if (clko = '1') then
----clko'event and
-- if (codopo = "0010") then
-- if (inFlago = '1') then
-- --if (auxo = '0') then
-- --auxo:= '1';
-- outo <= portAo or portBo;
-- outFlago <= '1';
-- --end if;
-- else
-- outFlago <= '0';
-- end if;
-- else
-- outo <= (others => 'Z');
-- outFlago <= 'Z';
-- --auxo:='0';
-- end if;
-- end if;
-- end process por;
end or0;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:51:15 09/10/2011
-- Design Name:
-- Module Name: MULTIPLEXOR3BITS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MULTIPLEXOR3BITS is
Port ( DIS1 : in STD_LOGIC_VECTOR (0 downto 2);
DIS2 : in STD_LOGIC_VECTOR (0 downto 2);
DIS3 : in STD_LOGIC_VECTOR (0 downto 2);
SW1 : in STD_LOGIC_VECTOR (0 downto 2);
SW2 : in STD_LOGIC_VECTOR (0 downto 2);
SW3 : in STD_LOGIC_VECTOR (0 downto 2));
end MULTIPLEXOR3BITS;
architecture Behavioral of MULTIPLEXOR3BITS is
begin
end Behavioral;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0_3.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0_3.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0_3.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0_3.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0_3.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0_3.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0_3.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0_3.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
t-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.08:58:01)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END hal_alap_entity;
ARCHITECTURE hal_alap_description OF hal_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register3 := input3 * 3;
register1 := register2 * register1;
WHEN "00000011" =>
register2 := input4 * 4;
register3 := register3 * 6;
register1 := register1 - 8;
register4 := input5 + 9;
WHEN "00000100" =>
output1 <= register2 + 10;
output2 <= register1 - register3;
IF (register4 < 12) THEN
output3 <= register4;
ELSE
output3 <= "0000000000000000000000000001100";
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_alap_description; |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 10:32:44 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.2 2005/07/15 16:20:08 wig Exp $
-- $Date: 2005/07/15 16:20:08 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.2 2005/07/15 16:20:08 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_a_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
s_open_i : in std_ulogic;
s_open_o : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal s_open_i : std_ulogic;
-- __I_OUT_OPEN signal s_open_o : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
s_open_i => s_open_i, -- open input
s_open_o => open -- open output -- __I_OUT_OPEN
);
-- End of Generated Instance Port Map for inst_a
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_19a is
end entity inline_19a;
architecture test of inline_19a is
signal reset, trigger_n : std_ulogic;
terminal rc_ext : electrical;
quantity v_rc_ext across rc_ext;
constant half_vdd : voltage := 2.5;
begin
block_1 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
-- ...
if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
q <= '0'; q_n <= '1';
break;
elsif trigger_n = '0' or trigger_n = 'L' then
q <= '1'; q_n <= '0';
break;
end if;
-- ...
-- end code from book
wait;
end process;
end block block_1;
block_2 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
q_n <= '1' after 20 ns;
break;
-- end code from book
wait;
end process;
end block block_2;
block_3 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
q_n <= '1';
break;
-- end code from book
wait;
end process;
end block block_3;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_19a is
end entity inline_19a;
architecture test of inline_19a is
signal reset, trigger_n : std_ulogic;
terminal rc_ext : electrical;
quantity v_rc_ext across rc_ext;
constant half_vdd : voltage := 2.5;
begin
block_1 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
-- ...
if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
q <= '0'; q_n <= '1';
break;
elsif trigger_n = '0' or trigger_n = 'L' then
q <= '1'; q_n <= '0';
break;
end if;
-- ...
-- end code from book
wait;
end process;
end block block_1;
block_2 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
q_n <= '1' after 20 ns;
break;
-- end code from book
wait;
end process;
end block block_2;
block_3 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
q_n <= '1';
break;
-- end code from book
wait;
end process;
end block block_3;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_19a is
end entity inline_19a;
architecture test of inline_19a is
signal reset, trigger_n : std_ulogic;
terminal rc_ext : electrical;
quantity v_rc_ext across rc_ext;
constant half_vdd : voltage := 2.5;
begin
block_1 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
-- ...
if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
q <= '0'; q_n <= '1';
break;
elsif trigger_n = '0' or trigger_n = 'L' then
q <= '1'; q_n <= '0';
break;
end if;
-- ...
-- end code from book
wait;
end process;
end block block_1;
block_2 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
q_n <= '1' after 20 ns;
break;
-- end code from book
wait;
end process;
end block block_2;
block_3 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
q_n <= '1';
break;
-- end code from book
wait;
end process;
end block block_3;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nand00 is
port(
clknd: in std_logic ;
codopnd: in std_logic_vector ( 3 downto 0 );
portAnd: in std_logic_vector ( 7 downto 0 );
portBnd: in std_logic_vector ( 7 downto 0 );
inFlagnd: in std_logic;
outnd: out std_logic_vector ( 7 downto 0 );
outFlagnd: out std_logic );
end;
architecture nand0 of nand00 is
begin
pnand: process(codopnd, portAnd, portBnd)
begin
if(codopnd = "0100") then
outnd <= portAnd nand portBnd;
outFlagnd <= '1';
else
outnd <= (others => 'Z');
outFlagnd <= 'Z';
end if;
end process pnand;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end nand0;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split4 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split4;
architecture augh of output_split4 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split4 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split4;
architecture augh of output_split4 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_accr-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of accumulator_reg is
begin
behavior : process (clk) is
constant Tpd_clk_out : time := 3 ns;
begin
if rising_edge(clk) then
if To_X01(clr) = '1' then
q <= (others => '0') after Tpd_clk_out;
else
q <= d after Tpd_clk_out;
end if;
end if;
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_accr-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of accumulator_reg is
begin
behavior : process (clk) is
constant Tpd_clk_out : time := 3 ns;
begin
if rising_edge(clk) then
if To_X01(clr) = '1' then
q <= (others => '0') after Tpd_clk_out;
else
q <= d after Tpd_clk_out;
end if;
end if;
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_accr-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of accumulator_reg is
begin
behavior : process (clk) is
constant Tpd_clk_out : time := 3 ns;
begin
if rising_edge(clk) then
if To_X01(clr) = '1' then
q <= (others => '0') after Tpd_clk_out;
else
q <= d after Tpd_clk_out;
end if;
end if;
end process behavior;
end architecture behavioral;
|
package pkg_6502_opcodes is
type t_opcode_array is array(0 to 255) of string(1 to 13);
constant opcode_array : t_opcode_array := (
"BRK ", "ORA ($nn,X) ", "HLT* ", "ASO*($nn,X) ",
"NOP*$nn ", "ORA $nn ", "ASL $nn ", "ASO*$nn ",
"PHP ", "ORA # ", "ASL A ", "ANC*# ",
"NOP*$nnnn ", "ORA $nnnn ", "ASL $nnnn ", "ASO*$nnnn ",
"BPL rel ", "ORA ($nn),Y ", "HLT* ", "ASO*($nn),Y ",
"NOP*$nn,X ", "ORA $nn,X ", "ASL $nn,X ", "ASO*$nn,X ",
"CLC ", "ORA $nnnn,Y ", "NOP* ", "ASO*$nnnn,Y ",
"NOP*$nnnn,X ", "ORA $nnnn,X ", "ASL $nnnn,X ", "ASO*$nnnn,X ",
"JSR $nnnn ", "AND ($nn,X) ", "HLT* ", "RLA*($nn,X) ",
"BIT $nn ", "AND $nn ", "ROL $nn ", "RLA*$nn ",
"PLP ", "AND # ", "ROL A ", "ANC*# ",
"BIT $nnnn ", "AND $nnnn ", "ROL $nnnn ", "RLA*$nnnn ",
"BMI rel ", "AND ($nn),Y ", "HLT* ", "RLA*($nn),Y ",
"NOP*$nn,X ", "AND $nn,X ", "ROL $nn,X ", "RLA*$nn,X ",
"SEC ", "AND $nnnn,Y ", "NOP* ", "RLA*$nnnn,Y ",
"NOP*$nnnn,X ", "AND $nnnn,X ", "ROL $nnnn,X ", "RLA*$nnnn,X ",
"RTI ", "EOR ($nn,X) ", "HLT* ", "LSE*($nn,X) ",
"NOP*$nn ", "EOR $nn ", "LSR $nn ", "LSE*$nn ",
"PHA ", "EOR # ", "LSR A ", "ALR*# ",
"JMP $nnnn ", "EOR $nnnn ", "LSR $nnnn ", "LSE*$nnnn ",
"BVC rel ", "EOR ($nn),Y ", "HLT* ", "LSE*($nn),Y ",
"NOP $nn,x ", "EOR $nn,X ", "LSR $nn,X ", "LSE*$nn,X ",
"CLI ", "EOR $nnnn,Y ", "NOP* ", "LSE*$nnnn,Y ",
"JMP*$nnnn $$", "EOR $nnnn,X ", "LSR $nnnn,X ", "LSE*$nnnn,X ",
"RTS ", "ADC ($nn,X) ", "HLT* ", "RRA*($nn,X) ",
"NOP*$nn ", "ADC $nn ", "ROR $nn ", "RRA*$nn ",
"PLA ", "ADC # ", "ROR A ", "ARR*# ",
"JMP ($nnnn) ", "ADC $nnnn ", "ROR $nnnn ", "RRA*$nnnn ",
"BVS rel ", "ADC ($nn),Y ", "HLT* ", "RRA*($nn),Y ",
"NOP $nn,x ", "ADC $nn,X ", "ROR $nn,X ", "RRA*$nn,X ",
"SEI ", "ADC $nnnn,Y ", "NOP* ", "RRA*$nnnn,Y ",
"JMP*(ABS,X)$$", "ADC $nnnn,X ", "ROR $nnnn,X ", "RRA*$nnnn,X ",
"NOP*# ", "STA ($nn,X) ", "NOP*# ", "SAX*($nn,X) ",
"STY $nn ", "STA $nn ", "STX $nn ", "SAX*$nn ",
"DEY ", "NOP # ", "TXA ", "XAA* ",
"STY $nnnn ", "STA $nnnn ", "STX $nnnn ", "SAX*$nnnn ",
"BCC ", "STA ($nn),Y ", "HLT* ", "AHX*($nn),Y ",
"STY $nn,X ", "STA $nn,X ", "STX $nn,Y ", "SAX*$nn,Y ",
"TYA ", "STA $nnnn,Y ", "TXS ", "TAS*$nnnn,Y ",
"SHY*$nnnn,X ", "STA $nnnn,X ", "SHX*$nnnn,Y ", "AHX*$nnnn,Y ",
"LDY # ", "LDA ($nn,X) ", "LDX # ", "LAX*($nn,X) ",
"LDY $nn ", "LDA $nn ", "LDX $nn ", "LAX*$nn ",
"TAY ", "LDA # ", "TAX ", "LAX*# ",
"LDY $nnnn ", "LDA $nnnn ", "LDX $nnnn ", "LAX*$nnnn ",
"BCS ", "LDA ($nn),Y ", "HLT* ", "LAX*($nn),Y ",
"LDY $nn,X ", "LDA $nn,X ", "LDX $nn,Y ", "LAX*$nn,Y ",
"CLV ", "LDA $nnnn,Y ", "TSX ", "LAS*$nnnn,Y ",
"LDY $nnnn,X ", "LDA $nnnn,X ", "LDX $nnnn,Y ", "LAX*$nnnn,Y ",
"CPY # ", "CMP ($nn,X) ", "NOP*# ", "DCM*($nn,X) ",
"CPY $nn ", "CMP $nn ", "DEC $nn ", "DCM*$nn ",
"INY ", "CMP # ", "DEX ", "AXS*# (used!)",
"CPY $nnnn ", "CMP $nnnn ", "DEC $nnnn ", "DCM*$nnnn ",
"BNE ", "CMP ($nn),Y ", "HLT* ", "DCM*($nn),Y ",
"NOP*$nn,X ", "CMP $nn,X ", "DEC $nn,X ", "DCM*$nn,X ",
"CLD ", "CMP $nnnn,Y ", "NOP* ", "DCM*$nnnn,Y ",
"NOP*$nnnn,X ", "CMP $nnnn,X ", "DEC $nnnn,X ", "DCM*$nnnn,X ",
"CPX # ", "SBC ($nn,X) ", "NOP*# ", "INS*($nn,X) ",
"CPX $nn ", "SBC $nn ", "INC $nn ", "INS*$nn ",
"INX ", "SBC # ", "NOP ", "SBC*# ",
"CPX $nnnn ", "SBC $nnnn ", "INC $nnnn ", "INS*$nnnn ",
"BEQ ", "SBC ($nn),Y ", "HLT* ", "INS*($nn),Y ",
"NOP*$nn,S ", "SBC $nn,X ", "INC $nn,X ", "INS*$nn,X ",
"SED ", "SBC $nnnn,Y ", "NOP* ", "INS*$nnnn,Y ",
"NOP*$nnnn,X ", "SBC $nnnn,X ", "INC $nnnn,X ", "INS*$nnnn,X " );
end;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: controller_synthesis.vhd
-- /___/ /\ Timestamp: Sat Jul 04 18:44:17 2015
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -tm controller -w -dir netgen/synthesis -ofmt vhdl -sim controller.ngc controller_synthesis.vhd
-- Device : xc7a100t-1-csg324
-- Input file : controller.ngc
-- Output file : C:\Users\saidwivedi\OneDrive\Project\NIT\ANN_proto_final\netgen\synthesis\controller_synthesis.vhd
-- # of Entities : 1
-- Design Name : controller
-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity controller is
port (
clk : in STD_LOGIC := 'X';
reset : in STD_LOGIC := 'X'
);
end controller;
architecture Structure of controller is
component test_image
port (
clka : in STD_LOGIC := 'X';
wea : in STD_LOGIC_VECTOR ( 0 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component;
component weight_hid
port (
clka : in STD_LOGIC := 'X';
wea : in STD_LOGIC_VECTOR ( 0 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
dina : in STD_LOGIC_VECTOR ( 23 downto 0 );
douta : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component;
component weight_out
port (
clka : in STD_LOGIC := 'X';
wea : in STD_LOGIC_VECTOR ( 0 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
dina : in STD_LOGIC_VECTOR ( 23 downto 0 );
douta : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component;
component mul_hid
port (
clk : in STD_LOGIC := 'X';
ce : in STD_LOGIC := 'X';
sclr : in STD_LOGIC := 'X';
bypass : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 7 downto 0 );
b : in STD_LOGIC_VECTOR ( 7 downto 0 );
s : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component;
component acticv_mul
port (
clk : in STD_LOGIC := 'X';
ce : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 15 downto 0 );
b : in STD_LOGIC_VECTOR ( 15 downto 0 );
d : in STD_LOGIC_VECTOR ( 15 downto 0 );
p : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component;
signal clk_BUFGP_0 : STD_LOGIC;
signal reset_IBUF_1 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shift_over_flag_34 : STD_LOGIC;
signal curr_state_FSM_FFd1_150 : STD_LOGIC;
signal \Q_n0319_3)\ : STD_LOGIC;
signal \Q_n0319_1)\ : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_7_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_6_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_5_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_4_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_3_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_2_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_1_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_0_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_31_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_30_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_29_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_28_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_27_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_26_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_25_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_24_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_23_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_22_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_21_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_20_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_19_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_18_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_17_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_16_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_15_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_14_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_13_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_12_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_11_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_10_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_9_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_8_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_7_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_6_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_5_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_4_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_3_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_2_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_1_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_0_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_31_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_30_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_29_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_28_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_27_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_26_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_25_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_24_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_23_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_22_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_21_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_20_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_19_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_18_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_17_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_16_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_15_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_14_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_13_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_12_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_11_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_10_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_9_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_8_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_7_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_6_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_5_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_4_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_3_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_2_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_1_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_0_Q : STD_LOGIC;
signal N0 : STD_LOGIC;
signal Q_n0240_inv : STD_LOGIC;
signal curr_state_FSM_FFd3_In : STD_LOGIC;
signal curr_state_FSM_FFd2_In : STD_LOGIC;
signal curr_state_FSM_FFd1_In : STD_LOGIC;
signal curr_state_FSM_FFd3_266 : STD_LOGIC;
signal curr_state_FSM_FFd2_267 : STD_LOGIC;
signal Mcount_addra_image : STD_LOGIC;
signal Mcount_addra_image1 : STD_LOGIC;
signal Mcount_addra_image2 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_lut_0_Q : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_0_Q_275 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_Q_276 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_Q_277 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_Q_278 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_Q_279 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_Q_280 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_Q_281 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_Q_282 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_Q_283 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_Q_284 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_Q_285 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_Q_286 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_Q_287 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_Q_288 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_Q_289 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_Q_290 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_Q_291 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_Q_292 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_Q_293 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_Q_294 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_Q_295 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_Q_296 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_Q_297 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_Q_298 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_Q_299 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_Q_300 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_Q_301 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_Q_302 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_Q_303 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_Q_304 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_Q_305 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi_306 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_0_Q_307 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_0_Q_308 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi1_309 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_1_Q_310 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_1_Q_311 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi2_312 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_2_Q_313 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_2_Q_314 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi3_315 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_3_Q_316 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_3_Q_317 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi4_318 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_4_Q_319 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_4_Q_320 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi5_321 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_5_Q_322 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323 : STD_LOGIC;
signal Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324 : STD_LOGIC;
signal layer_map_count_en_inv : STD_LOGIC;
signal layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv : STD_LOGIC;
signal layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o : STD_LOGIC;
signal layer_map_ce : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_401 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_402 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_403 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_404 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_405 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_406 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_407 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_408 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_409 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_410 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_411 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_412 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_413 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_414 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_415 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_416 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_417 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_418 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_419 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_420 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_421 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_422 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_423 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_424 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_425 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_426 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_427 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_428 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_429 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_430 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_431 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_lut_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_433 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_434 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_435 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_436 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_437 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_438 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_439 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_440 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_441 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_442 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_443 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_444 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_445 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_447 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_448 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_449 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_450 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_451 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_452 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_453 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_454 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_455 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_456 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_457 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_458 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_459 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_460 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_31_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_30_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_29_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_28_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_27_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_26_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_25_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_24_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_23_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_22_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_21_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_20_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_19_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_18_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_17_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_16_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_15_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_14_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_13_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_12_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_11_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_10_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_9_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_8_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_7_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_6_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_5_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_4_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_3_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_2_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_1_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_n0056_inv : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_enable_inv : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_GND_14_o_MUX_60_o : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_INV_16_o : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_1_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_2_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_3_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_4_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_5_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_6_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_7_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_8_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_9_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_10_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_11_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_12_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_13_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_14_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_15_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_5_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_6_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_7_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_8_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_9_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_10_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_11_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_12_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_13_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_14_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_15_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_16_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_17_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_18_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_19_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_20_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_21_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_22_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_23_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_24_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_25_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_26_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_27_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_28_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_29_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_30_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_1_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_2_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_3_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_4_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_5_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_6_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_7_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_8_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_9_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_10_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_11_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_12_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_13_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_14_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_acticv_mul_en_562 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_1_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_2_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_3_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_4_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_5_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_6_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_7_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_8_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_9_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_10_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_11_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_12_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_13_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_14_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_15_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_595 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_596 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_597 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_598 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_599 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_600 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_601 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_602 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_603 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_604 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_605 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_606 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_607 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_608 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_609 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_610 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_611 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_612 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_613 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_614 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_615 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_616 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_617 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_618 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_619 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_620 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_621 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_622 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_623 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_624 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_625 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_lut_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_627 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_628 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_629 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_630 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_631 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_632 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_633 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_634 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_635 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_636 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_637 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_638 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_639 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_641 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_642 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_643 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_644 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_645 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_646 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_647 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_648 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_649 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_650 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_651 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_652 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_653 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_654 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_31_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_30_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_29_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_28_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_27_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_26_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_25_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_24_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_23_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_22_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_21_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_20_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_19_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_18_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_17_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_16_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_15_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_14_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_13_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_12_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_11_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_10_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_9_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_8_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_7_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_6_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_5_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_4_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_3_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_2_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_1_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_n0056_inv : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_GND_14_o_MUX_60_o : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_INV_16_o : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_1_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_2_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_3_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_4_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_5_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_6_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_7_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_8_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_9_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_10_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_11_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_12_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_13_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_14_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_15_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_5_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_6_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_7_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_8_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_9_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_10_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_11_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_12_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_13_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_14_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_15_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_16_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_17_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_18_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_19_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_20_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_21_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_22_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_23_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_24_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_25_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_26_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_27_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_28_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_29_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_30_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_1_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_2_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_3_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_4_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_5_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_6_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_7_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_8_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_9_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_10_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_11_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_12_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_13_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_14_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_acticv_mul_en_755 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_1_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_2_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_3_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_4_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_5_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_6_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_7_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_8_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_9_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_10_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_11_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_12_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_13_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_14_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_15_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_788 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_789 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_790 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_791 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_792 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_793 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_794 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_795 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_796 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_797 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_798 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_799 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_800 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_801 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_802 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_803 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_804 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_805 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_806 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_807 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_808 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_809 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_810 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_811 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_812 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_813 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_814 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_815 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_816 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_817 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_818 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_lut_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_820 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_821 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_822 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_823 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_824 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_825 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_826 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_827 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_828 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_829 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_830 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_831 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_832 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_834 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_835 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_836 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_837 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_838 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_839 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_840 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_841 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_842 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_843 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_844 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_845 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_846 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_847 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_31_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_30_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_29_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_28_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_27_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_26_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_25_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_24_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_23_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_22_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_21_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_20_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_19_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_18_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_17_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_16_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_15_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_14_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_13_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_12_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_11_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_10_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_9_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_8_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_7_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_6_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_5_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_4_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_3_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_2_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_1_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_n0056_inv : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_GND_14_o_MUX_60_o : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_INV_16_o : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_1_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_2_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_3_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_4_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_5_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_6_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_7_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_8_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_9_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_10_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_11_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_12_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_13_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_14_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_15_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_5_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_6_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_7_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_8_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_9_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_10_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_11_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_12_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_13_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_14_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_15_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_16_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_17_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_18_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_19_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_20_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_21_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_22_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_23_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_24_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_25_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_26_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_27_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_28_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_29_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_30_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_1_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_2_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_3_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_4_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_5_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_6_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_7_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_8_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_9_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_10_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_11_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_12_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_13_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_14_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_acticv_mul_en_948 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_1_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_2_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_3_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_4_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_5_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_6_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_7_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_8_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_9_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_10_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_11_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_12_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_13_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_14_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_15_Q : STD_LOGIC;
signal N01 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_983 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_984 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_985 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_986 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_987 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_989 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_990 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_991 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_992 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_993 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_995 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_996 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_997 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_998 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_999 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_rt_1002 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_rt_1003 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_rt_1004 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_rt_1005 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_rt_1006 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_rt_1007 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_rt_1008 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_rt_1009 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_rt_1010 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_rt_1011 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_rt_1012 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_rt_1013 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_rt_1014 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_rt_1015 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_rt_1016 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_rt_1017 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_rt_1018 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_rt_1019 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_rt_1020 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_rt_1021 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_rt_1022 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_rt_1023 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_rt_1024 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_rt_1025 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_rt_1026 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_rt_1027 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_rt_1028 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_rt_1029 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_rt_1030 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_rt_1031 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_cy_6_rt_1032 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_cy_5_rt_1033 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_cy_4_rt_1034 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_cy_3_rt_1035 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_cy_2_rt_1036 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_cy_1_rt_1037 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1038 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1039 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1040 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1041 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1042 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1043 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1044 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1045 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1046 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1047 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1048 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1049 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1050 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1051 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1052 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1053 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1054 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1055 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1056 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1057 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1058 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1059 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1060 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1061 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1062 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1063 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1064 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1065 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1066 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1067 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1068 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1069 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1070 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1071 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1072 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1073 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1074 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1075 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1076 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1077 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1078 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1079 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1080 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1081 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1082 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1083 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1084 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1085 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1086 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1087 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1088 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1089 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1090 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1091 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1092 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1093 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1094 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1095 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1096 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1097 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1098 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1099 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1100 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1101 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1102 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1103 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1104 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1105 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1106 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1107 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1108 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1109 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1110 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1111 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1112 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1113 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1114 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1115 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1116 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1117 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1118 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1119 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1120 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1121 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1122 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1123 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1124 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1125 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1126 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1127 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_xor_31_rt_1128 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_xor_7_rt_1129 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1130 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1131 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1132 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shift_over_flag_rstpot_1133 : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_31_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_30_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_29_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_28_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_27_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_26_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_17_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_16_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_15_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_14_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_13_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_12_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_11_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_10_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_9_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_8_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_7_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_6_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_5_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_4_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_3_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_2_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_1_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_0_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_31_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_30_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_29_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_28_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_27_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_26_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_17_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_16_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_15_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_14_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_13_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_12_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_11_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_10_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_9_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_8_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_7_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_6_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_5_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_4_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_3_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_2_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_1_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_0_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_31_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_30_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_29_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_28_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_27_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_26_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_17_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_16_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_15_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_14_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_13_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_12_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_11_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_10_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_9_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_8_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_7_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_6_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_5_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_4_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_3_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_2_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_1_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_0_UNCONNECTED : STD_LOGIC;
signal image : STD_LOGIC_VECTOR ( 7 downto 0 );
signal output_hid : STD_LOGIC_VECTOR2 ( 2 downto 0 , 7 downto 0 );
signal out_weight_hid : STD_LOGIC_VECTOR ( 23 downto 0 );
signal out_weight_out : STD_LOGIC_VECTOR ( 23 downto 0 );
signal addra_image : STD_LOGIC_VECTOR ( 2 downto 0 );
signal output_3 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal output_2 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal output_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal output_temp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal transition_num : STD_LOGIC_VECTOR ( 31 downto 0 );
signal GND_7_o_GND_7_o_mux_14_OUT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal input : STD_LOGIC_VECTOR ( 7 downto 0 );
signal weight : STD_LOGIC_VECTOR2 ( 2 downto 0 , 7 downto 0 );
signal dina_image : STD_LOGIC_VECTOR ( 0 downto 0 );
signal addr_weight_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal layer_map_activation_hid_count_map_Mcount_count_cy : STD_LOGIC_VECTOR ( 6 downto 0 );
signal layer_map_activation_hid_count_map_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal layer_map_Result : STD_LOGIC_VECTOR ( 7 downto 0 );
signal layer_map_activation_hid_count_map_count : STD_LOGIC_VECTOR ( 7 downto 0 );
signal layer_map_weighted_sum : STD_LOGIC_VECTOR2 ( 2 downto 0 , 15 downto 0 );
begin
XST_VCC : VCC
port map (
P => N0
);
XST_GND : GND
port map (
G => dina_image(0)
);
output_3_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 0),
Q => output_3(0)
);
output_3_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 1),
Q => output_3(1)
);
output_3_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 2),
Q => output_3(2)
);
output_3_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 3),
Q => output_3(3)
);
output_3_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 4),
Q => output_3(4)
);
output_3_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 5),
Q => output_3(5)
);
output_3_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 6),
Q => output_3(6)
);
output_3_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 7),
Q => output_3(7)
);
output_2_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 0),
Q => output_2(0)
);
output_2_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 1),
Q => output_2(1)
);
output_2_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 2),
Q => output_2(2)
);
output_2_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 3),
Q => output_2(3)
);
output_2_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 4),
Q => output_2(4)
);
output_2_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 5),
Q => output_2(5)
);
output_2_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 6),
Q => output_2(6)
);
output_2_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 7),
Q => output_2(7)
);
output_1_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 0),
Q => output_1(0)
);
output_1_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 1),
Q => output_1(1)
);
output_1_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 2),
Q => output_1(2)
);
output_1_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 3),
Q => output_1(3)
);
output_1_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 4),
Q => output_1(4)
);
output_1_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 5),
Q => output_1(5)
);
output_1_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 6),
Q => output_1(6)
);
output_1_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 7),
Q => output_1(7)
);
transition_num_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_0_Q,
Q => transition_num(0)
);
transition_num_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_1_Q,
Q => transition_num(1)
);
transition_num_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_2_Q,
Q => transition_num(2)
);
transition_num_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_3_Q,
Q => transition_num(3)
);
transition_num_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_4_Q,
Q => transition_num(4)
);
transition_num_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_5_Q,
Q => transition_num(5)
);
transition_num_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_6_Q,
Q => transition_num(6)
);
transition_num_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_7_Q,
Q => transition_num(7)
);
transition_num_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_8_Q,
Q => transition_num(8)
);
transition_num_9 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_9_Q,
Q => transition_num(9)
);
transition_num_10 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_10_Q,
Q => transition_num(10)
);
transition_num_11 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_11_Q,
Q => transition_num(11)
);
transition_num_12 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_12_Q,
Q => transition_num(12)
);
transition_num_13 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_13_Q,
Q => transition_num(13)
);
transition_num_14 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_14_Q,
Q => transition_num(14)
);
transition_num_15 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_15_Q,
Q => transition_num(15)
);
transition_num_16 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_16_Q,
Q => transition_num(16)
);
transition_num_17 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_17_Q,
Q => transition_num(17)
);
transition_num_18 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_18_Q,
Q => transition_num(18)
);
transition_num_19 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_19_Q,
Q => transition_num(19)
);
transition_num_20 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_20_Q,
Q => transition_num(20)
);
transition_num_21 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_21_Q,
Q => transition_num(21)
);
transition_num_22 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_22_Q,
Q => transition_num(22)
);
transition_num_23 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_23_Q,
Q => transition_num(23)
);
transition_num_24 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_24_Q,
Q => transition_num(24)
);
transition_num_25 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_25_Q,
Q => transition_num(25)
);
transition_num_26 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_26_Q,
Q => transition_num(26)
);
transition_num_27 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_27_Q,
Q => transition_num(27)
);
transition_num_28 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_28_Q,
Q => transition_num(28)
);
transition_num_29 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_29_Q,
Q => transition_num(29)
);
transition_num_30 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_30_Q,
Q => transition_num(30)
);
transition_num_31 : FDCE
generic map(
INIT => '1'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_31_Q,
Q => transition_num(31)
);
addr_weight_out_0 : FDC
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => GND_7_o_GND_7_o_mux_14_OUT(0),
Q => addr_weight_out(0)
);
addr_weight_out_1 : FDC
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => GND_7_o_GND_7_o_mux_14_OUT(1),
Q => addr_weight_out(1)
);
addr_weight_out_2 : FDC
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => GND_7_o_GND_7_o_mux_14_OUT(2),
Q => addr_weight_out(2)
);
output_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_0_Q,
Q => output_temp(0)
);
output_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_1_Q,
Q => output_temp(1)
);
output_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_2_Q,
Q => output_temp(2)
);
output_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_3_Q,
Q => output_temp(3)
);
output_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_4_Q,
Q => output_temp(4)
);
output_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_5_Q,
Q => output_temp(5)
);
output_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_6_Q,
Q => output_temp(6)
);
output_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_7_Q,
Q => output_temp(7)
);
curr_state_FSM_FFd3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => curr_state_FSM_FFd3_In,
Q => curr_state_FSM_FFd3_266
);
curr_state_FSM_FFd2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => curr_state_FSM_FFd2_In,
Q => curr_state_FSM_FFd2_267
);
curr_state_FSM_FFd1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => curr_state_FSM_FFd1_In,
Q => curr_state_FSM_FFd1_150
);
addra_image_0 : FDC
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => Mcount_addra_image,
Q => addra_image(0)
);
addra_image_1 : FDC
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => Mcount_addra_image1,
Q => addra_image(1)
);
addra_image_2 : FDC
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => Mcount_addra_image2,
Q => addra_image(2)
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_0_Q : MUXCY
port map (
CI => dina_image(0),
DI => N0,
S => Madd_transition_num_31_GND_7_o_add_6_OUT_lut_0_Q,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_0_Q_275
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_0_Q : XORCY
port map (
CI => dina_image(0),
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_lut_0_Q,
O => transition_num_31_GND_7_o_add_6_OUT_0_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_0_Q_275,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_rt_1002,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_Q_276
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_1_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_0_Q_275,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_rt_1002,
O => transition_num_31_GND_7_o_add_6_OUT_1_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_Q_276,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_rt_1003,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_Q_277
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_2_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_Q_276,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_rt_1003,
O => transition_num_31_GND_7_o_add_6_OUT_2_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_Q_277,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_rt_1004,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_Q_278
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_3_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_Q_277,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_rt_1004,
O => transition_num_31_GND_7_o_add_6_OUT_3_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_Q_278,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_rt_1005,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_Q_279
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_4_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_Q_278,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_rt_1005,
O => transition_num_31_GND_7_o_add_6_OUT_4_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_Q_279,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_rt_1006,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_Q_280
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_5_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_Q_279,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_rt_1006,
O => transition_num_31_GND_7_o_add_6_OUT_5_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_Q_280,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_rt_1007,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_Q_281
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_6_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_Q_280,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_rt_1007,
O => transition_num_31_GND_7_o_add_6_OUT_6_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_Q_281,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_rt_1008,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_Q_282
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_7_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_Q_281,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_rt_1008,
O => transition_num_31_GND_7_o_add_6_OUT_7_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_Q_282,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_rt_1009,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_Q_283
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_8_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_Q_282,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_rt_1009,
O => transition_num_31_GND_7_o_add_6_OUT_8_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_Q_283,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_rt_1010,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_Q_284
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_9_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_Q_283,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_rt_1010,
O => transition_num_31_GND_7_o_add_6_OUT_9_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_Q_284,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_rt_1011,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_Q_285
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_10_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_Q_284,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_rt_1011,
O => transition_num_31_GND_7_o_add_6_OUT_10_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_Q_285,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_rt_1012,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_Q_286
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_11_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_Q_285,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_rt_1012,
O => transition_num_31_GND_7_o_add_6_OUT_11_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_Q_286,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_rt_1013,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_Q_287
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_12_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_Q_286,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_rt_1013,
O => transition_num_31_GND_7_o_add_6_OUT_12_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_Q_287,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_rt_1014,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_Q_288
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_13_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_Q_287,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_rt_1014,
O => transition_num_31_GND_7_o_add_6_OUT_13_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_Q_288,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_rt_1015,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_Q_289
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_14_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_Q_288,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_rt_1015,
O => transition_num_31_GND_7_o_add_6_OUT_14_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_Q_289,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_rt_1016,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_Q_290
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_15_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_Q_289,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_rt_1016,
O => transition_num_31_GND_7_o_add_6_OUT_15_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_Q_290,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_rt_1017,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_Q_291
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_16_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_Q_290,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_rt_1017,
O => transition_num_31_GND_7_o_add_6_OUT_16_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_Q_291,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_rt_1018,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_Q_292
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_17_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_Q_291,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_rt_1018,
O => transition_num_31_GND_7_o_add_6_OUT_17_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_Q_292,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_rt_1019,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_Q_293
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_18_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_Q_292,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_rt_1019,
O => transition_num_31_GND_7_o_add_6_OUT_18_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_Q_293,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_rt_1020,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_Q_294
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_19_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_Q_293,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_rt_1020,
O => transition_num_31_GND_7_o_add_6_OUT_19_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_Q_294,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_rt_1021,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_Q_295
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_20_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_Q_294,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_rt_1021,
O => transition_num_31_GND_7_o_add_6_OUT_20_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_Q_295,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_rt_1022,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_Q_296
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_21_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_Q_295,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_rt_1022,
O => transition_num_31_GND_7_o_add_6_OUT_21_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_Q_296,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_rt_1023,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_Q_297
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_22_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_Q_296,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_rt_1023,
O => transition_num_31_GND_7_o_add_6_OUT_22_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_Q_297,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_rt_1024,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_Q_298
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_23_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_Q_297,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_rt_1024,
O => transition_num_31_GND_7_o_add_6_OUT_23_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_Q_298,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_rt_1025,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_Q_299
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_24_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_Q_298,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_rt_1025,
O => transition_num_31_GND_7_o_add_6_OUT_24_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_Q_299,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_rt_1026,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_Q_300
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_25_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_Q_299,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_rt_1026,
O => transition_num_31_GND_7_o_add_6_OUT_25_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_Q_300,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_rt_1027,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_Q_301
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_26_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_Q_300,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_rt_1027,
O => transition_num_31_GND_7_o_add_6_OUT_26_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_Q_301,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_rt_1028,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_Q_302
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_27_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_Q_301,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_rt_1028,
O => transition_num_31_GND_7_o_add_6_OUT_27_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_Q_302,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_rt_1029,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_Q_303
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_28_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_Q_302,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_rt_1029,
O => transition_num_31_GND_7_o_add_6_OUT_28_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_Q_303,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_rt_1030,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_Q_304
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_29_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_Q_303,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_rt_1030,
O => transition_num_31_GND_7_o_add_6_OUT_29_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_Q_304,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_rt_1031,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_Q_305
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_30_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_Q_304,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_rt_1031,
O => transition_num_31_GND_7_o_add_6_OUT_30_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_31_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_Q_305,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_xor_31_rt_1128,
O => transition_num_31_GND_7_o_add_6_OUT_31_Q
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => transition_num(4),
I1 => transition_num(3),
I2 => transition_num(2),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi_306
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_0_Q : LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => transition_num(2),
I1 => transition_num(3),
I2 => transition_num(4),
I3 => transition_num(1),
I4 => transition_num(0),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_0_Q_307
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi_306,
S => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_0_Q_307,
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_0_Q_308
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi1 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => transition_num(9),
I1 => transition_num(8),
I2 => transition_num(7),
I3 => transition_num(6),
I4 => transition_num(5),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi1_309
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => transition_num(5),
I1 => transition_num(6),
I2 => transition_num(7),
I3 => transition_num(8),
I4 => transition_num(9),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_1_Q_310
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_1_Q : MUXCY
port map (
CI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_0_Q_308,
DI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi1_309,
S => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_1_Q_310,
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_1_Q_311
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi2 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => transition_num(14),
I1 => transition_num(13),
I2 => transition_num(12),
I3 => transition_num(11),
I4 => transition_num(10),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi2_312
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => transition_num(10),
I1 => transition_num(11),
I2 => transition_num(12),
I3 => transition_num(13),
I4 => transition_num(14),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_2_Q_313
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_2_Q : MUXCY
port map (
CI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_1_Q_311,
DI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi2_312,
S => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_2_Q_313,
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_2_Q_314
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi3 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => transition_num(19),
I1 => transition_num(18),
I2 => transition_num(17),
I3 => transition_num(16),
I4 => transition_num(15),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi3_315
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => transition_num(15),
I1 => transition_num(16),
I2 => transition_num(17),
I3 => transition_num(18),
I4 => transition_num(19),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_3_Q_316
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_3_Q : MUXCY
port map (
CI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_2_Q_314,
DI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi3_315,
S => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_3_Q_316,
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_3_Q_317
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi4 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => transition_num(24),
I1 => transition_num(23),
I2 => transition_num(22),
I3 => transition_num(21),
I4 => transition_num(20),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi4_318
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => transition_num(20),
I1 => transition_num(21),
I2 => transition_num(22),
I3 => transition_num(23),
I4 => transition_num(24),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_4_Q_319
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_4_Q : MUXCY
port map (
CI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_3_Q_317,
DI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi4_318,
S => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_4_Q_319,
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_4_Q_320
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi5 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => transition_num(29),
I1 => transition_num(28),
I2 => transition_num(27),
I3 => transition_num(26),
I4 => transition_num(25),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi5_321
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => transition_num(25),
I1 => transition_num(26),
I2 => transition_num(27),
I3 => transition_num(28),
I4 => transition_num(29),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_5_Q_322
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q : MUXCY
port map (
CI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_4_Q_320,
DI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi5_321,
S => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_5_Q_322,
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323
);
layer_map_activation_hid_count_map_Mcount_count_xor_7_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(6),
LI => layer_map_activation_hid_count_map_Mcount_count_xor_7_rt_1129,
O => layer_map_Result(7)
);
layer_map_activation_hid_count_map_Mcount_count_xor_6_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(5),
LI => layer_map_activation_hid_count_map_Mcount_count_cy_6_rt_1032,
O => layer_map_Result(6)
);
layer_map_activation_hid_count_map_Mcount_count_cy_6_Q : MUXCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(5),
DI => dina_image(0),
S => layer_map_activation_hid_count_map_Mcount_count_cy_6_rt_1032,
O => layer_map_activation_hid_count_map_Mcount_count_cy(6)
);
layer_map_activation_hid_count_map_Mcount_count_xor_5_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(4),
LI => layer_map_activation_hid_count_map_Mcount_count_cy_5_rt_1033,
O => layer_map_Result(5)
);
layer_map_activation_hid_count_map_Mcount_count_cy_5_Q : MUXCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(4),
DI => dina_image(0),
S => layer_map_activation_hid_count_map_Mcount_count_cy_5_rt_1033,
O => layer_map_activation_hid_count_map_Mcount_count_cy(5)
);
layer_map_activation_hid_count_map_Mcount_count_xor_4_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(3),
LI => layer_map_activation_hid_count_map_Mcount_count_cy_4_rt_1034,
O => layer_map_Result(4)
);
layer_map_activation_hid_count_map_Mcount_count_cy_4_Q : MUXCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(3),
DI => dina_image(0),
S => layer_map_activation_hid_count_map_Mcount_count_cy_4_rt_1034,
O => layer_map_activation_hid_count_map_Mcount_count_cy(4)
);
layer_map_activation_hid_count_map_Mcount_count_xor_3_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(2),
LI => layer_map_activation_hid_count_map_Mcount_count_cy_3_rt_1035,
O => layer_map_Result(3)
);
layer_map_activation_hid_count_map_Mcount_count_cy_3_Q : MUXCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(2),
DI => dina_image(0),
S => layer_map_activation_hid_count_map_Mcount_count_cy_3_rt_1035,
O => layer_map_activation_hid_count_map_Mcount_count_cy(3)
);
layer_map_activation_hid_count_map_Mcount_count_xor_2_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(1),
LI => layer_map_activation_hid_count_map_Mcount_count_cy_2_rt_1036,
O => layer_map_Result(2)
);
layer_map_activation_hid_count_map_Mcount_count_cy_2_Q : MUXCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(1),
DI => dina_image(0),
S => layer_map_activation_hid_count_map_Mcount_count_cy_2_rt_1036,
O => layer_map_activation_hid_count_map_Mcount_count_cy(2)
);
layer_map_activation_hid_count_map_Mcount_count_xor_1_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(0),
LI => layer_map_activation_hid_count_map_Mcount_count_cy_1_rt_1037,
O => layer_map_Result(1)
);
layer_map_activation_hid_count_map_Mcount_count_cy_1_Q : MUXCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(0),
DI => dina_image(0),
S => layer_map_activation_hid_count_map_Mcount_count_cy_1_rt_1037,
O => layer_map_activation_hid_count_map_Mcount_count_cy(1)
);
layer_map_activation_hid_count_map_Mcount_count_xor_0_Q : XORCY
port map (
CI => dina_image(0),
LI => layer_map_activation_hid_count_map_Mcount_count_lut(0),
O => layer_map_Result(0)
);
layer_map_activation_hid_count_map_Mcount_count_cy_0_Q : MUXCY
port map (
CI => dina_image(0),
DI => N0,
S => layer_map_activation_hid_count_map_Mcount_count_lut(0),
O => layer_map_activation_hid_count_map_Mcount_count_cy(0)
);
layer_map_activation_hid_count_map_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(7),
Q => layer_map_activation_hid_count_map_count(7)
);
layer_map_activation_hid_count_map_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(6),
Q => layer_map_activation_hid_count_map_count(6)
);
layer_map_activation_hid_count_map_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(5),
Q => layer_map_activation_hid_count_map_count(5)
);
layer_map_activation_hid_count_map_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(4),
Q => layer_map_activation_hid_count_map_count(4)
);
layer_map_activation_hid_count_map_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(3),
Q => layer_map_activation_hid_count_map_count(3)
);
layer_map_activation_hid_count_map_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(2),
Q => layer_map_activation_hid_count_map_count(2)
);
layer_map_activation_hid_count_map_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(1),
Q => layer_map_activation_hid_count_map_count(1)
);
layer_map_activation_hid_count_map_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(0),
Q => layer_map_activation_hid_count_map_count(0)
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_31_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_401,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1130,
O => layer_map_shift_map_0_shifter_map_Result_31_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_30_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_402,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1038,
O => layer_map_shift_map_0_shifter_map_Result_30_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_402,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1038,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_401
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_29_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_403,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1039,
O => layer_map_shift_map_0_shifter_map_Result_29_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_403,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1039,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_402
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_28_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_404,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1040,
O => layer_map_shift_map_0_shifter_map_Result_28_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_404,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1040,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_403
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_27_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_405,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1041,
O => layer_map_shift_map_0_shifter_map_Result_27_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_405,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1041,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_404
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_26_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_406,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1042,
O => layer_map_shift_map_0_shifter_map_Result_26_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_406,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1042,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_405
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_25_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_407,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1043,
O => layer_map_shift_map_0_shifter_map_Result_25_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_407,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1043,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_406
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_24_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_408,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1044,
O => layer_map_shift_map_0_shifter_map_Result_24_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_408,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1044,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_407
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_23_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_409,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1045,
O => layer_map_shift_map_0_shifter_map_Result_23_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_409,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1045,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_408
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_22_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_410,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1046,
O => layer_map_shift_map_0_shifter_map_Result_22_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_410,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1046,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_409
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_21_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_411,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1047,
O => layer_map_shift_map_0_shifter_map_Result_21_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_411,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1047,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_410
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_20_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_412,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1048,
O => layer_map_shift_map_0_shifter_map_Result_20_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_412,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1048,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_411
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_19_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_413,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1049,
O => layer_map_shift_map_0_shifter_map_Result_19_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_413,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1049,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_412
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_18_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_414,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1050,
O => layer_map_shift_map_0_shifter_map_Result_18_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_414,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1050,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_413
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_17_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_415,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1051,
O => layer_map_shift_map_0_shifter_map_Result_17_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_415,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1051,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_414
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_16_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_416,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1052,
O => layer_map_shift_map_0_shifter_map_Result_16_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_416,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1052,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_415
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_15_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_417,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1053,
O => layer_map_shift_map_0_shifter_map_Result_15_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_417,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1053,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_416
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_14_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_418,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1054,
O => layer_map_shift_map_0_shifter_map_Result_14_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_418,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1054,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_417
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_13_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_419,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1055,
O => layer_map_shift_map_0_shifter_map_Result_13_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_419,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1055,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_418
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_12_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_420,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1056,
O => layer_map_shift_map_0_shifter_map_Result_12_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_420,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1056,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_419
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_11_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_421,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1057,
O => layer_map_shift_map_0_shifter_map_Result_11_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_421,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1057,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_420
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_10_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_422,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1058,
O => layer_map_shift_map_0_shifter_map_Result_10_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_422,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1058,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_421
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_9_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_423,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1059,
O => layer_map_shift_map_0_shifter_map_Result_9_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_423,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1059,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_422
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_8_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_424,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1060,
O => layer_map_shift_map_0_shifter_map_Result_8_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_424,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1060,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_423
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_7_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_425,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1061,
O => layer_map_shift_map_0_shifter_map_Result_7_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_425,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1061,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_424
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_6_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_426,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1062,
O => layer_map_shift_map_0_shifter_map_Result_6_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_426,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1062,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_425
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_5_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_427,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1063,
O => layer_map_shift_map_0_shifter_map_Result_5_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_427,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1063,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_426
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_4_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_428,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1064,
O => layer_map_shift_map_0_shifter_map_Result_4_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_428,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1064,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_427
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_3_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_429,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1065,
O => layer_map_shift_map_0_shifter_map_Result_3_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_429,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1065,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_428
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_2_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_430,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1066,
O => layer_map_shift_map_0_shifter_map_Result_2_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_430,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1066,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_429
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_1_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_431,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1067,
O => layer_map_shift_map_0_shifter_map_Result_1_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_431,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1067,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_430
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_0_Q : XORCY
port map (
CI => dina_image(0),
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_lut_0_Q,
O => layer_map_shift_map_0_shifter_map_Result_0_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_0_Q : MUXCY
port map (
CI => dina_image(0),
DI => N0,
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_lut_0_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_431
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_433,
DI => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q,
S => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_987,
O => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_INV_16_o
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_6_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_30_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_987
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_435,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_434,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_433
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_26_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_27_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_28_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_434
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_437,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_436,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_435
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_20_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_21_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_22_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_23_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_436
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_439,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_438,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_437
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_15_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_16_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_17_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_18_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_438
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_441,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_440,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_439
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_10_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_11_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_12_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_13_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_440
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_443,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_442,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_441
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_5_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_7_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_8_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_442
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_445,
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_444,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_443
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q : LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_0_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_444
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_445
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_448,
DI => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q,
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_447,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_30_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_447
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_450,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_449,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_448
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_26_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_27_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_28_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_449
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_452,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_451,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_450
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_20_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_21_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_22_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_23_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_451
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_454,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_453,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_452
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_15_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_16_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_17_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_18_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_453
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_456,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_455,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_454
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_10_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_11_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_12_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_13_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_455
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_458,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_457,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_456
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_5_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_7_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_8_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_457
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_460,
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_459,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_458
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q : LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_0_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_459
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_460
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_31 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_31_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_30 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_30_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_30_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_29 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_29_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_29_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_28 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_28_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_28_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_27 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_27_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_27_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_26 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_26_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_26_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_25 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_25_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_25_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_24 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_24_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_24_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_23 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_23_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_23_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_22 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_22_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_22_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_21 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_21_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_21_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_20 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_20_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_20_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_19 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_19_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_19_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_18 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_18_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_18_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_17 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_17_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_17_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_16 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_16_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_16_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_15 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_15_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_15_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_14 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_14_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_14_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_13 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_13_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_13_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_12 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_12_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_12_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_11 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_11_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_11_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_10_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_10_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_9_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_9_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_8_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_8_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_7_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_7_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_6_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_6_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_5_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_5_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_4_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_3_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_2_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_1_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_0_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_0_Q
);
layer_map_shift_map_0_shifter_map_acticv_mul_en : FDC
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_GND_14_o_GND_14_o_MUX_60_o,
Q => layer_map_shift_map_0_shifter_map_acticv_mul_en_562
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_15 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_15_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_14 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_14_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_14_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_13 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_13_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_13_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_12 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_12_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_12_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_11 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_11_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_11_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_10 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_10_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_10_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_9 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_9_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_9_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_8 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_8_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_8_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_7_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_7_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_6_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_6_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_5_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_5_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_4_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_4_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_3_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_3_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_2_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_2_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_1_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_1_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_0_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_0_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_15 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_14 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_14_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_13 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_13_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_12 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_12_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_11 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_11_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_10_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_9_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_8_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_7_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_6_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_5_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_4_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_3_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_2_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_1_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_0_Q
);
layer_map_shift_map_0_shifter_map_input_temp_15 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 15),
Q => layer_map_shift_map_0_shifter_map_input_temp_15_Q
);
layer_map_shift_map_0_shifter_map_input_temp_14 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 14),
Q => layer_map_shift_map_0_shifter_map_input_temp_14_Q
);
layer_map_shift_map_0_shifter_map_input_temp_13 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 13),
Q => layer_map_shift_map_0_shifter_map_input_temp_13_Q
);
layer_map_shift_map_0_shifter_map_input_temp_12 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 12),
Q => layer_map_shift_map_0_shifter_map_input_temp_12_Q
);
layer_map_shift_map_0_shifter_map_input_temp_11 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 11),
Q => layer_map_shift_map_0_shifter_map_input_temp_11_Q
);
layer_map_shift_map_0_shifter_map_input_temp_10 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 10),
Q => layer_map_shift_map_0_shifter_map_input_temp_10_Q
);
layer_map_shift_map_0_shifter_map_input_temp_9 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 9),
Q => layer_map_shift_map_0_shifter_map_input_temp_9_Q
);
layer_map_shift_map_0_shifter_map_input_temp_8 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 8),
Q => layer_map_shift_map_0_shifter_map_input_temp_8_Q
);
layer_map_shift_map_0_shifter_map_input_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 7),
Q => layer_map_shift_map_0_shifter_map_input_temp_7_Q
);
layer_map_shift_map_0_shifter_map_input_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 6),
Q => layer_map_shift_map_0_shifter_map_input_temp_6_Q
);
layer_map_shift_map_0_shifter_map_input_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 5),
Q => layer_map_shift_map_0_shifter_map_input_temp_5_Q
);
layer_map_shift_map_0_shifter_map_input_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 4),
Q => layer_map_shift_map_0_shifter_map_input_temp_4_Q
);
layer_map_shift_map_0_shifter_map_input_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 3),
Q => layer_map_shift_map_0_shifter_map_input_temp_3_Q
);
layer_map_shift_map_0_shifter_map_input_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 2),
Q => layer_map_shift_map_0_shifter_map_input_temp_2_Q
);
layer_map_shift_map_0_shifter_map_input_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 1),
Q => layer_map_shift_map_0_shifter_map_input_temp_1_Q
);
layer_map_shift_map_0_shifter_map_input_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 0),
Q => layer_map_shift_map_0_shifter_map_input_temp_0_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_31_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_595,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1131,
O => layer_map_shift_map_1_shifter_map_Result_31_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_30_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_596,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1068,
O => layer_map_shift_map_1_shifter_map_Result_30_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_596,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1068,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_595
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_29_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_597,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1069,
O => layer_map_shift_map_1_shifter_map_Result_29_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_597,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1069,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_596
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_28_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_598,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1070,
O => layer_map_shift_map_1_shifter_map_Result_28_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_598,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1070,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_597
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_27_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_599,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1071,
O => layer_map_shift_map_1_shifter_map_Result_27_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_599,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1071,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_598
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_26_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_600,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1072,
O => layer_map_shift_map_1_shifter_map_Result_26_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_600,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1072,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_599
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_25_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_601,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1073,
O => layer_map_shift_map_1_shifter_map_Result_25_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_601,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1073,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_600
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_24_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_602,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1074,
O => layer_map_shift_map_1_shifter_map_Result_24_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_602,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1074,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_601
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_23_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_603,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1075,
O => layer_map_shift_map_1_shifter_map_Result_23_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_603,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1075,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_602
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_22_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_604,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1076,
O => layer_map_shift_map_1_shifter_map_Result_22_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_604,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1076,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_603
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_21_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_605,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1077,
O => layer_map_shift_map_1_shifter_map_Result_21_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_605,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1077,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_604
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_20_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_606,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1078,
O => layer_map_shift_map_1_shifter_map_Result_20_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_606,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1078,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_605
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_19_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_607,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1079,
O => layer_map_shift_map_1_shifter_map_Result_19_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_607,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1079,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_606
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_18_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_608,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1080,
O => layer_map_shift_map_1_shifter_map_Result_18_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_608,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1080,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_607
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_17_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_609,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1081,
O => layer_map_shift_map_1_shifter_map_Result_17_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_609,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1081,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_608
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_16_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_610,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1082,
O => layer_map_shift_map_1_shifter_map_Result_16_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_610,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1082,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_609
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_15_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_611,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1083,
O => layer_map_shift_map_1_shifter_map_Result_15_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_611,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1083,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_610
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_14_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_612,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1084,
O => layer_map_shift_map_1_shifter_map_Result_14_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_612,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1084,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_611
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_13_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_613,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1085,
O => layer_map_shift_map_1_shifter_map_Result_13_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_613,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1085,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_612
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_12_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_614,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1086,
O => layer_map_shift_map_1_shifter_map_Result_12_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_614,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1086,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_613
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_11_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_615,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1087,
O => layer_map_shift_map_1_shifter_map_Result_11_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_615,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1087,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_614
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_10_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_616,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1088,
O => layer_map_shift_map_1_shifter_map_Result_10_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_616,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1088,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_615
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_9_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_617,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1089,
O => layer_map_shift_map_1_shifter_map_Result_9_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_617,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1089,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_616
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_8_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_618,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1090,
O => layer_map_shift_map_1_shifter_map_Result_8_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_618,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1090,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_617
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_7_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_619,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1091,
O => layer_map_shift_map_1_shifter_map_Result_7_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_619,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1091,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_618
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_6_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_620,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1092,
O => layer_map_shift_map_1_shifter_map_Result_6_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_620,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1092,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_619
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_5_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_621,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1093,
O => layer_map_shift_map_1_shifter_map_Result_5_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_621,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1093,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_620
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_4_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_622,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1094,
O => layer_map_shift_map_1_shifter_map_Result_4_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_622,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1094,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_621
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_3_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_623,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1095,
O => layer_map_shift_map_1_shifter_map_Result_3_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_623,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1095,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_622
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_2_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_624,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1096,
O => layer_map_shift_map_1_shifter_map_Result_2_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_624,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1096,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_623
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_1_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_625,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1097,
O => layer_map_shift_map_1_shifter_map_Result_1_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_625,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1097,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_624
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_0_Q : XORCY
port map (
CI => dina_image(0),
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_lut_0_Q,
O => layer_map_shift_map_1_shifter_map_Result_0_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_0_Q : MUXCY
port map (
CI => dina_image(0),
DI => N0,
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_lut_0_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_625
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_627,
DI => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q,
S => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_993,
O => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_INV_16_o
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_6_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_30_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_993
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_629,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_628,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_627
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_26_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_27_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_28_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_628
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_631,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_630,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_629
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_20_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_21_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_22_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_23_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_630
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_633,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_632,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_631
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_15_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_16_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_17_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_18_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_632
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_635,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_634,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_633
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_10_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_11_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_12_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_13_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_634
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_637,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_636,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_635
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_5_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_7_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_8_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_636
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_639,
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_638,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_637
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q : LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_0_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_638
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_639
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_642,
DI => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q,
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_641,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_30_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_641
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_644,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_643,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_642
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_26_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_27_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_28_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_643
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_646,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_645,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_644
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_20_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_21_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_22_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_23_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_645
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_648,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_647,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_646
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_15_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_16_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_17_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_18_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_647
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_650,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_649,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_648
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_10_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_11_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_12_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_13_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_649
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_652,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_651,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_650
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_5_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_7_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_8_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_651
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_654,
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_653,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_652
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q : LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_0_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_653
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_654
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_31 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_31_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_30 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_30_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_30_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_29 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_29_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_29_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_28 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_28_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_28_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_27 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_27_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_27_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_26 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_26_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_26_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_25 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_25_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_25_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_24 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_24_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_24_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_23 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_23_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_23_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_22 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_22_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_22_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_21 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_21_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_21_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_20 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_20_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_20_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_19 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_19_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_19_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_18 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_18_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_18_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_17 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_17_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_17_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_16 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_16_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_16_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_15 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_15_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_15_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_14 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_14_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_14_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_13 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_13_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_13_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_12 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_12_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_12_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_11 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_11_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_11_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_10_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_10_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_9_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_9_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_8_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_8_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_7_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_7_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_6_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_6_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_5_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_5_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_4_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_3_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_2_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_1_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_0_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_0_Q
);
layer_map_shift_map_1_shifter_map_acticv_mul_en : FDC
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_GND_14_o_GND_14_o_MUX_60_o,
Q => layer_map_shift_map_1_shifter_map_acticv_mul_en_755
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_15 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_15_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_14 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_14_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_14_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_13 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_13_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_13_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_12 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_12_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_12_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_11 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_11_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_11_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_10 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_10_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_10_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_9 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_9_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_9_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_8 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_8_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_8_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_7_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_7_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_6_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_6_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_5_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_5_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_4_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_4_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_3_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_3_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_2_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_2_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_1_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_1_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_0_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_0_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_15 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_14 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_14_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_13 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_13_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_12 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_12_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_11 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_11_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_10_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_9_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_8_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_7_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_6_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_5_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_4_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_3_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_2_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_1_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_0_Q
);
layer_map_shift_map_1_shifter_map_input_temp_15 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 15),
Q => layer_map_shift_map_1_shifter_map_input_temp_15_Q
);
layer_map_shift_map_1_shifter_map_input_temp_14 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 14),
Q => layer_map_shift_map_1_shifter_map_input_temp_14_Q
);
layer_map_shift_map_1_shifter_map_input_temp_13 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 13),
Q => layer_map_shift_map_1_shifter_map_input_temp_13_Q
);
layer_map_shift_map_1_shifter_map_input_temp_12 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 12),
Q => layer_map_shift_map_1_shifter_map_input_temp_12_Q
);
layer_map_shift_map_1_shifter_map_input_temp_11 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 11),
Q => layer_map_shift_map_1_shifter_map_input_temp_11_Q
);
layer_map_shift_map_1_shifter_map_input_temp_10 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 10),
Q => layer_map_shift_map_1_shifter_map_input_temp_10_Q
);
layer_map_shift_map_1_shifter_map_input_temp_9 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 9),
Q => layer_map_shift_map_1_shifter_map_input_temp_9_Q
);
layer_map_shift_map_1_shifter_map_input_temp_8 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 8),
Q => layer_map_shift_map_1_shifter_map_input_temp_8_Q
);
layer_map_shift_map_1_shifter_map_input_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 7),
Q => layer_map_shift_map_1_shifter_map_input_temp_7_Q
);
layer_map_shift_map_1_shifter_map_input_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 6),
Q => layer_map_shift_map_1_shifter_map_input_temp_6_Q
);
layer_map_shift_map_1_shifter_map_input_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 5),
Q => layer_map_shift_map_1_shifter_map_input_temp_5_Q
);
layer_map_shift_map_1_shifter_map_input_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 4),
Q => layer_map_shift_map_1_shifter_map_input_temp_4_Q
);
layer_map_shift_map_1_shifter_map_input_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 3),
Q => layer_map_shift_map_1_shifter_map_input_temp_3_Q
);
layer_map_shift_map_1_shifter_map_input_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 2),
Q => layer_map_shift_map_1_shifter_map_input_temp_2_Q
);
layer_map_shift_map_1_shifter_map_input_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 1),
Q => layer_map_shift_map_1_shifter_map_input_temp_1_Q
);
layer_map_shift_map_1_shifter_map_input_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 0),
Q => layer_map_shift_map_1_shifter_map_input_temp_0_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_31_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_788,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1132,
O => layer_map_shift_map_2_shifter_map_Result_31_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_30_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_789,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1098,
O => layer_map_shift_map_2_shifter_map_Result_30_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_789,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1098,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_788
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_29_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_790,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1099,
O => layer_map_shift_map_2_shifter_map_Result_29_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_790,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1099,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_789
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_28_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_791,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1100,
O => layer_map_shift_map_2_shifter_map_Result_28_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_791,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1100,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_790
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_27_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_792,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1101,
O => layer_map_shift_map_2_shifter_map_Result_27_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_792,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1101,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_791
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_26_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_793,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1102,
O => layer_map_shift_map_2_shifter_map_Result_26_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_793,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1102,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_792
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_25_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_794,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1103,
O => layer_map_shift_map_2_shifter_map_Result_25_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_794,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1103,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_793
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_24_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_795,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1104,
O => layer_map_shift_map_2_shifter_map_Result_24_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_795,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1104,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_794
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_23_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_796,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1105,
O => layer_map_shift_map_2_shifter_map_Result_23_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_796,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1105,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_795
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_22_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_797,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1106,
O => layer_map_shift_map_2_shifter_map_Result_22_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_797,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1106,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_796
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_21_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_798,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1107,
O => layer_map_shift_map_2_shifter_map_Result_21_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_798,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1107,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_797
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_20_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_799,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1108,
O => layer_map_shift_map_2_shifter_map_Result_20_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_799,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1108,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_798
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_19_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_800,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1109,
O => layer_map_shift_map_2_shifter_map_Result_19_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_800,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1109,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_799
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_18_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_801,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1110,
O => layer_map_shift_map_2_shifter_map_Result_18_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_801,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1110,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_800
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_17_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_802,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1111,
O => layer_map_shift_map_2_shifter_map_Result_17_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_802,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1111,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_801
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_16_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_803,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1112,
O => layer_map_shift_map_2_shifter_map_Result_16_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_803,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1112,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_802
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_15_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_804,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1113,
O => layer_map_shift_map_2_shifter_map_Result_15_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_804,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1113,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_803
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_14_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_805,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1114,
O => layer_map_shift_map_2_shifter_map_Result_14_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_805,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1114,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_804
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_13_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_806,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1115,
O => layer_map_shift_map_2_shifter_map_Result_13_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_806,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1115,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_805
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_12_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_807,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1116,
O => layer_map_shift_map_2_shifter_map_Result_12_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_807,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1116,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_806
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_11_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_808,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1117,
O => layer_map_shift_map_2_shifter_map_Result_11_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_808,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1117,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_807
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_10_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_809,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1118,
O => layer_map_shift_map_2_shifter_map_Result_10_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_809,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1118,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_808
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_9_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_810,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1119,
O => layer_map_shift_map_2_shifter_map_Result_9_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_810,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1119,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_809
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_8_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_811,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1120,
O => layer_map_shift_map_2_shifter_map_Result_8_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_811,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1120,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_810
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_7_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_812,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1121,
O => layer_map_shift_map_2_shifter_map_Result_7_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_812,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1121,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_811
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_6_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_813,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1122,
O => layer_map_shift_map_2_shifter_map_Result_6_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_813,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1122,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_812
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_5_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_814,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1123,
O => layer_map_shift_map_2_shifter_map_Result_5_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_814,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1123,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_813
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_4_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_815,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1124,
O => layer_map_shift_map_2_shifter_map_Result_4_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_815,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1124,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_814
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_3_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_816,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1125,
O => layer_map_shift_map_2_shifter_map_Result_3_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_816,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1125,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_815
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_2_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_817,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1126,
O => layer_map_shift_map_2_shifter_map_Result_2_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_817,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1126,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_816
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_1_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_818,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1127,
O => layer_map_shift_map_2_shifter_map_Result_1_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_818,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1127,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_817
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_0_Q : XORCY
port map (
CI => dina_image(0),
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_lut_0_Q,
O => layer_map_shift_map_2_shifter_map_Result_0_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_0_Q : MUXCY
port map (
CI => dina_image(0),
DI => N0,
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_lut_0_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_818
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_820,
DI => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q,
S => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_999,
O => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_INV_16_o
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_6_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_30_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_999
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_822,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_821,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_820
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_26_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_27_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_28_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_821
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_824,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_823,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_822
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_20_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_21_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_22_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_23_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_823
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_826,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_825,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_824
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_15_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_16_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_17_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_18_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_825
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_828,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_827,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_826
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_10_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_11_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_12_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_13_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_827
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_830,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_829,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_828
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_5_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_7_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_8_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_829
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_832,
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_831,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_830
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q : LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_0_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_831
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_832
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_835,
DI => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q,
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_834,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_30_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_834
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_837,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_836,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_835
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_26_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_27_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_28_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_836
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_839,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_838,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_837
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_20_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_21_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_22_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_23_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_838
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_841,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_840,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_839
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_15_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_16_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_17_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_18_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_840
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_843,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_842,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_841
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_10_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_11_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_12_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_13_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_842
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_845,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_844,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_843
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_5_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_7_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_8_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_844
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_847,
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_846,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_845
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q : LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_0_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_846
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_847
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_31 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_31_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_30 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_30_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_30_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_29 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_29_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_29_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_28 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_28_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_28_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_27 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_27_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_27_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_26 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_26_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_26_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_25 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_25_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_25_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_24 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_24_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_24_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_23 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_23_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_23_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_22 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_22_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_22_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_21 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_21_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_21_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_20 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_20_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_20_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_19 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_19_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_19_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_18 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_18_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_18_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_17 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_17_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_17_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_16 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_16_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_16_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_15 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_15_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_15_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_14 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_14_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_14_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_13 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_13_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_13_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_12 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_12_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_12_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_11 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_11_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_11_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_10_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_10_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_9_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_9_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_8_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_8_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_7_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_7_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_6_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_6_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_5_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_5_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_4_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_3_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_2_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_1_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_0_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_0_Q
);
layer_map_shift_map_2_shifter_map_acticv_mul_en : FDC
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_GND_14_o_GND_14_o_MUX_60_o,
Q => layer_map_shift_map_2_shifter_map_acticv_mul_en_948
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_15 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_15_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_14 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_14_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_14_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_13 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_13_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_13_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_12 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_12_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_12_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_11 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_11_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_11_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_10 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_10_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_10_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_9 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_9_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_9_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_8 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_8_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_8_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_7_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_7_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_6_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_6_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_5_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_5_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_4_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_4_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_3_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_3_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_2_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_2_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_1_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_1_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_0_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_0_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_15 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_14 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_14_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_13 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_13_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_12 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_12_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_11 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_11_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_10_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_9_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_8_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_7_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_6_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_5_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_4_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_3_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_2_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_1_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_0_Q
);
layer_map_shift_map_2_shifter_map_input_temp_15 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 15),
Q => layer_map_shift_map_2_shifter_map_input_temp_15_Q
);
layer_map_shift_map_2_shifter_map_input_temp_14 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 14),
Q => layer_map_shift_map_2_shifter_map_input_temp_14_Q
);
layer_map_shift_map_2_shifter_map_input_temp_13 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 13),
Q => layer_map_shift_map_2_shifter_map_input_temp_13_Q
);
layer_map_shift_map_2_shifter_map_input_temp_12 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 12),
Q => layer_map_shift_map_2_shifter_map_input_temp_12_Q
);
layer_map_shift_map_2_shifter_map_input_temp_11 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 11),
Q => layer_map_shift_map_2_shifter_map_input_temp_11_Q
);
layer_map_shift_map_2_shifter_map_input_temp_10 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 10),
Q => layer_map_shift_map_2_shifter_map_input_temp_10_Q
);
layer_map_shift_map_2_shifter_map_input_temp_9 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 9),
Q => layer_map_shift_map_2_shifter_map_input_temp_9_Q
);
layer_map_shift_map_2_shifter_map_input_temp_8 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 8),
Q => layer_map_shift_map_2_shifter_map_input_temp_8_Q
);
layer_map_shift_map_2_shifter_map_input_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 7),
Q => layer_map_shift_map_2_shifter_map_input_temp_7_Q
);
layer_map_shift_map_2_shifter_map_input_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 6),
Q => layer_map_shift_map_2_shifter_map_input_temp_6_Q
);
layer_map_shift_map_2_shifter_map_input_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 5),
Q => layer_map_shift_map_2_shifter_map_input_temp_5_Q
);
layer_map_shift_map_2_shifter_map_input_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 4),
Q => layer_map_shift_map_2_shifter_map_input_temp_4_Q
);
layer_map_shift_map_2_shifter_map_input_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 3),
Q => layer_map_shift_map_2_shifter_map_input_temp_3_Q
);
layer_map_shift_map_2_shifter_map_input_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 2),
Q => layer_map_shift_map_2_shifter_map_input_temp_2_Q
);
layer_map_shift_map_2_shifter_map_input_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 1),
Q => layer_map_shift_map_2_shifter_map_input_temp_1_Q
);
layer_map_shift_map_2_shifter_map_input_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 0),
Q => layer_map_shift_map_2_shifter_map_input_temp_0_Q
);
Q_n0319_3_1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
O => \Q_n0319_3)\
);
Mmux_GND_7_o_GND_7_o_mux_14_OUT211 : LUT3
generic map(
INIT => X"10"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
O => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT81 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(7),
I3 => output_3(7),
I4 => output_2(7),
O => transition_num_1_output_3_7_wide_mux_4_OUT_7_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT71 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(6),
I3 => output_3(6),
I4 => output_2(6),
O => transition_num_1_output_3_7_wide_mux_4_OUT_6_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT61 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(5),
I3 => output_3(5),
I4 => output_2(5),
O => transition_num_1_output_3_7_wide_mux_4_OUT_5_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT51 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(4),
I3 => output_3(4),
I4 => output_2(4),
O => transition_num_1_output_3_7_wide_mux_4_OUT_4_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT41 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(3),
I3 => output_3(3),
I4 => output_2(3),
O => transition_num_1_output_3_7_wide_mux_4_OUT_3_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT31 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(2),
I3 => output_3(2),
I4 => output_2(2),
O => transition_num_1_output_3_7_wide_mux_4_OUT_2_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT21 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(1),
I3 => output_3(1),
I4 => output_2(1),
O => transition_num_1_output_3_7_wide_mux_4_OUT_1_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT11 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(0),
I3 => output_3(0),
I4 => output_2(0),
O => transition_num_1_output_3_7_wide_mux_4_OUT_0_Q
);
Q_n0240_inv1 : LUT3
generic map(
INIT => X"28"
)
port map (
I0 => curr_state_FSM_FFd2_267,
I1 => curr_state_FSM_FFd1_150,
I2 => curr_state_FSM_FFd3_266,
O => Q_n0240_inv
);
Q_n0319_1_1 : LUT3
generic map(
INIT => X"54"
)
port map (
I0 => curr_state_FSM_FFd3_266,
I1 => curr_state_FSM_FFd1_150,
I2 => curr_state_FSM_FFd2_267,
O => \Q_n0319_1)\
);
input_7_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(7),
I4 => image(7),
O => input(7)
);
input_6_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(6),
I4 => image(6),
O => input(6)
);
input_5_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(5),
I4 => image(5),
O => input(5)
);
input_4_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(4),
I4 => image(4),
O => input(4)
);
input_3_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(3),
I4 => image(3),
O => input(3)
);
input_2_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(2),
I4 => image(2),
O => input(2)
);
input_1_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(1),
I4 => image(1),
O => input(1)
);
input_0_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(0),
I4 => image(0),
O => input(0)
);
weight_2_7_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(23),
I4 => out_weight_hid(23),
O => weight(2, 7)
);
weight_2_6_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(22),
I4 => out_weight_hid(22),
O => weight(2, 6)
);
weight_2_5_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(21),
I4 => out_weight_hid(21),
O => weight(2, 5)
);
weight_2_4_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(20),
I4 => out_weight_hid(20),
O => weight(2, 4)
);
weight_2_3_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(19),
I4 => out_weight_hid(19),
O => weight(2, 3)
);
weight_2_2_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(18),
I4 => out_weight_hid(18),
O => weight(2, 2)
);
weight_2_1_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(17),
I4 => out_weight_hid(17),
O => weight(2, 1)
);
weight_2_0_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(16),
I4 => out_weight_hid(16),
O => weight(2, 0)
);
weight_1_7_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(15),
I4 => out_weight_hid(15),
O => weight(1, 7)
);
weight_1_6_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(14),
I4 => out_weight_hid(14),
O => weight(1, 6)
);
weight_1_5_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(13),
I4 => out_weight_hid(13),
O => weight(1, 5)
);
weight_1_4_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(12),
I4 => out_weight_hid(12),
O => weight(1, 4)
);
weight_1_3_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(11),
I4 => out_weight_hid(11),
O => weight(1, 3)
);
weight_1_2_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(10),
I4 => out_weight_hid(10),
O => weight(1, 2)
);
weight_1_1_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(9),
I4 => out_weight_hid(9),
O => weight(1, 1)
);
weight_1_0_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(8),
I4 => out_weight_hid(8),
O => weight(1, 0)
);
weight_0_7_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(7),
I4 => out_weight_hid(7),
O => weight(0, 7)
);
weight_0_6_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(6),
I4 => out_weight_hid(6),
O => weight(0, 6)
);
weight_0_5_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(5),
I4 => out_weight_hid(5),
O => weight(0, 5)
);
weight_0_4_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(4),
I4 => out_weight_hid(4),
O => weight(0, 4)
);
weight_0_3_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(3),
I4 => out_weight_hid(3),
O => weight(0, 3)
);
weight_0_2_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(2),
I4 => out_weight_hid(2),
O => weight(0, 2)
);
weight_0_1_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(1),
I4 => out_weight_hid(1),
O => weight(0, 1)
);
weight_0_0_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(0),
I4 => out_weight_hid(0),
O => weight(0, 0)
);
Mcount_addra_image_xor_0_11 : LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => addra_image(0),
I1 => curr_state_FSM_FFd1_150,
I2 => curr_state_FSM_FFd3_266,
I3 => curr_state_FSM_FFd2_267,
O => Mcount_addra_image
);
Mcount_addra_image_xor_1_11 : LUT5
generic map(
INIT => X"00101000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd2_267,
I2 => curr_state_FSM_FFd3_266,
I3 => addra_image(0),
I4 => addra_image(1),
O => Mcount_addra_image1
);
Mcount_addra_image_xor_2_11 : LUT6
generic map(
INIT => X"0010100010001000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd2_267,
I2 => curr_state_FSM_FFd3_266,
I3 => addra_image(2),
I4 => addra_image(0),
I5 => addra_image(1),
O => Mcount_addra_image2
);
layer_map_shift_map_0_shifter_map_Mmux_GND_14_o_GND_14_o_MUX_60_o11 : LUT3
generic map(
INIT => X"10"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_INV_16_o,
O => layer_map_shift_map_0_shifter_map_GND_14_o_GND_14_o_MUX_60_o
);
layer_map_shift_map_0_shifter_map_n0056_inv1 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
O => layer_map_shift_map_0_shifter_map_n0056_inv
);
layer_map_shift_map_1_shifter_map_Mmux_GND_14_o_GND_14_o_MUX_60_o11 : LUT3
generic map(
INIT => X"10"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_INV_16_o,
O => layer_map_shift_map_1_shifter_map_GND_14_o_GND_14_o_MUX_60_o
);
layer_map_shift_map_1_shifter_map_n0056_inv1 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
O => layer_map_shift_map_1_shifter_map_n0056_inv
);
layer_map_shift_map_2_shifter_map_Mmux_GND_14_o_GND_14_o_MUX_60_o11 : LUT3
generic map(
INIT => X"10"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_INV_16_o,
O => layer_map_shift_map_2_shifter_map_GND_14_o_GND_14_o_MUX_60_o
);
layer_map_shift_map_2_shifter_map_n0056_inv1 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
O => layer_map_shift_map_2_shifter_map_n0056_inv
);
layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o8_SW0 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => layer_map_activation_hid_count_map_count(7),
I1 => layer_map_activation_hid_count_map_count(6),
I2 => layer_map_activation_hid_count_map_count(5),
I3 => layer_map_activation_hid_count_map_count(4),
I4 => layer_map_activation_hid_count_map_count(3),
O => N01
);
layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o8 : LUT6
generic map(
INIT => X"4001000000004001"
)
port map (
I0 => N01,
I1 => layer_map_activation_hid_count_map_count(1),
I2 => layer_map_activation_hid_count_map_count(0),
I3 => \Q_n0319_1)\,
I4 => \Q_n0319_3)\,
I5 => layer_map_activation_hid_count_map_count(2),
O => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o
);
layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_13_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_12_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_14_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_15_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_16_Q,
I5 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_17_Q,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q
);
layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_19_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_18_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_20_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_21_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_22_Q,
I5 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_23_Q,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_983
);
layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_0_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q,
I5 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_5_Q,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_984
);
layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_7_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_8_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_9_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_10_Q,
I5 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_11_Q,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_985
);
layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_24_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_26_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_27_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_28_Q,
I5 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_986
);
layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_7 : LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q,
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_983,
I2 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_984,
I3 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_985,
I4 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_986,
I5 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_987,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o
);
layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_13_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_12_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_14_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_15_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_16_Q,
I5 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_17_Q,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q
);
layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_19_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_18_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_20_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_21_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_22_Q,
I5 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_23_Q,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_989
);
layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_0_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q,
I5 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_5_Q,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_990
);
layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_7_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_8_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_9_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_10_Q,
I5 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_11_Q,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_991
);
layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_24_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_26_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_27_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_28_Q,
I5 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_992
);
layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_7 : LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q,
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_989,
I2 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_990,
I3 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_991,
I4 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_992,
I5 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_993,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o
);
layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_13_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_12_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_14_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_15_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_16_Q,
I5 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_17_Q,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q
);
layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_19_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_18_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_20_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_21_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_22_Q,
I5 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_23_Q,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_995
);
layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_0_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q,
I5 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_5_Q,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_996
);
layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_7_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_8_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_9_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_10_Q,
I5 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_11_Q,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_997
);
layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_24_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_26_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_27_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_28_Q,
I5 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_998
);
layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_7 : LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q,
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_995,
I2 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_996,
I3 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_997,
I4 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_998,
I5 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_999,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o
);
reset_IBUF : IBUF
port map (
I => reset,
O => reset_IBUF_1
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(1),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_rt_1002
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(2),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_rt_1003
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(3),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_rt_1004
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(4),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_rt_1005
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(5),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_rt_1006
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(6),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_rt_1007
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(7),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_rt_1008
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(8),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_rt_1009
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(9),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_rt_1010
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(10),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_rt_1011
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(11),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_rt_1012
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(12),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_rt_1013
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(13),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_rt_1014
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(14),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_rt_1015
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(15),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_rt_1016
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(16),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_rt_1017
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(17),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_rt_1018
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(18),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_rt_1019
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(19),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_rt_1020
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(20),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_rt_1021
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(21),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_rt_1022
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(22),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_rt_1023
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(23),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_rt_1024
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(24),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_rt_1025
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(25),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_rt_1026
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(26),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_rt_1027
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(27),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_rt_1028
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(28),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_rt_1029
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(29),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_rt_1030
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(30),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_rt_1031
);
layer_map_activation_hid_count_map_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(6),
O => layer_map_activation_hid_count_map_Mcount_count_cy_6_rt_1032
);
layer_map_activation_hid_count_map_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(5),
O => layer_map_activation_hid_count_map_Mcount_count_cy_5_rt_1033
);
layer_map_activation_hid_count_map_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(4),
O => layer_map_activation_hid_count_map_Mcount_count_cy_4_rt_1034
);
layer_map_activation_hid_count_map_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(3),
O => layer_map_activation_hid_count_map_Mcount_count_cy_3_rt_1035
);
layer_map_activation_hid_count_map_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(2),
O => layer_map_activation_hid_count_map_Mcount_count_cy_2_rt_1036
);
layer_map_activation_hid_count_map_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(1),
O => layer_map_activation_hid_count_map_Mcount_count_cy_1_rt_1037
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_30_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1038
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1039
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_28_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1040
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_27_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1041
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_26_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1042
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_25_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1043
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1044
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_23_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1045
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_22_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1046
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_21_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1047
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_20_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1048
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1049
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_18_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1050
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_17_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1051
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_16_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1052
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_15_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1053
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1054
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_13_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1055
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_12_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1056
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_11_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1057
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_10_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1058
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1059
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_8_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1060
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_7_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1061
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_6_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1062
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_5_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1063
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1064
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1065
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1066
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1067
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_30_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1068
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1069
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_28_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1070
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_27_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1071
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_26_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1072
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_25_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1073
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1074
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_23_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1075
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_22_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1076
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_21_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1077
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_20_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1078
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1079
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_18_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1080
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_17_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1081
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_16_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1082
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_15_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1083
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1084
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_13_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1085
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_12_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1086
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_11_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1087
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_10_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1088
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1089
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_8_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1090
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_7_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1091
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_6_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1092
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_5_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1093
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1094
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1095
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1096
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1097
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_30_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1098
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1099
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_28_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1100
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_27_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1101
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_26_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1102
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_25_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1103
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1104
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_23_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1105
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_22_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1106
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_21_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1107
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_20_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1108
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1109
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_18_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1110
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_17_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1111
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_16_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1112
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_15_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1113
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1114
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_13_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1115
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_12_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1116
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_11_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1117
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_10_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1118
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1119
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_8_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1120
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_7_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1121
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_6_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1122
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_5_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1123
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1124
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1125
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1126
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1127
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(31),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_xor_31_rt_1128
);
layer_map_activation_hid_count_map_Mcount_count_xor_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(7),
O => layer_map_activation_hid_count_map_Mcount_count_xor_7_rt_1129
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1130
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1131
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1132
);
layer_map_shift_map_0_shifter_map_shift_over_flag : FDC
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shift_over_flag_rstpot_1133,
Q => layer_map_shift_map_0_shifter_map_shift_over_flag_34
);
layer_map_shift_map_0_shifter_map_shift_over_flag_rstpot : LUT4
generic map(
INIT => X"FF01"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_INV_16_o,
I3 => layer_map_shift_map_0_shifter_map_shift_over_flag_34,
O => layer_map_shift_map_0_shifter_map_shift_over_flag_rstpot_1133
);
layer_map_count_en_inv1 : LUT3
generic map(
INIT => X"EB"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
O => layer_map_count_en_inv
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT18 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 0),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_1_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT21 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 10),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_11_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT31 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 11),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_12_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT41 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 12),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_13_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT51 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 13),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_14_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT71 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 15),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT81 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 1),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_2_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT91 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 2),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_3_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT101 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 3),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_4_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT111 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 4),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_5_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT121 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 5),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_6_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT131 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 6),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_7_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT141 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 7),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_8_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT151 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 8),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_9_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT161 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 9),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_10_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT18 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 0),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_1_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT21 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 10),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_11_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT31 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 11),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_12_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT41 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 12),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_13_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT51 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 13),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_14_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT71 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 15),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT81 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 1),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_2_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT91 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 2),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_3_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT101 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 3),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_4_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT111 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 4),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_5_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT121 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 5),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_6_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT131 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 6),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_7_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT141 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 7),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_8_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT151 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 8),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_9_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT161 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 9),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_10_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT18 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 0),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_1_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT21 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 10),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_11_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT31 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 11),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_12_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT41 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 12),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_13_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT51 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 13),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_14_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT71 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 15),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT81 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 1),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_2_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT91 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 2),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_3_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT101 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 3),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_4_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT111 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 4),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_5_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT121 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 5),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_6_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT131 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 6),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_7_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT141 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 7),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_8_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT151 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 8),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_9_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT161 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 9),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_10_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT61 : LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => layer_map_weighted_sum(0, 14),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT61 : LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => layer_map_weighted_sum(1, 14),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT61 : LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => layer_map_weighted_sum(2, 14),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q
);
layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv1 : LUT6
generic map(
INIT => X"FFFFFFFF7FF7EFFE"
)
port map (
I0 => layer_map_activation_hid_count_map_count(1),
I1 => layer_map_activation_hid_count_map_count(0),
I2 => \Q_n0319_3)\,
I3 => layer_map_activation_hid_count_map_count(2),
I4 => \Q_n0319_1)\,
I5 => N01,
O => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv
);
layer_map_ce1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => curr_state_FSM_FFd3_266,
I1 => curr_state_FSM_FFd2_267,
I2 => curr_state_FSM_FFd1_150,
O => layer_map_ce
);
Mmux_GND_7_o_GND_7_o_mux_14_OUT11 : LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => addr_weight_out(0),
I1 => curr_state_FSM_FFd1_150,
I2 => curr_state_FSM_FFd2_267,
I3 => curr_state_FSM_FFd3_266,
O => GND_7_o_GND_7_o_mux_14_OUT(0)
);
Mmux_GND_7_o_GND_7_o_mux_14_OUT31 : LUT6
generic map(
INIT => X"0010100010001000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => addr_weight_out(2),
I4 => addr_weight_out(0),
I5 => addr_weight_out(1),
O => GND_7_o_GND_7_o_mux_14_OUT(2)
);
Mmux_GND_7_o_GND_7_o_mux_14_OUT21 : LUT5
generic map(
INIT => X"00101000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => addr_weight_out(0),
I4 => addr_weight_out(1),
O => GND_7_o_GND_7_o_mux_14_OUT(1)
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT321 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_9_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_9_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT311 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_8_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_8_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT301 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_7_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_7_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT291 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_6_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_6_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT281 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_5_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_5_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT271 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_4_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_4_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT261 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_3_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_3_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT231 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_2_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_2_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT121 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_1_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_1_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT11 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_0_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_0_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT21 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_10_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_10_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT31 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_11_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_11_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT41 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_12_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_12_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT51 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_13_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_13_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT61 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_14_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_14_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT71 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_15_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_15_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT81 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_16_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_16_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT91 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_17_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_17_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT101 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_18_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_18_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT111 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_19_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_19_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT131 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_20_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_20_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT251 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_31_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_31_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT241 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_30_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_30_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT221 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_29_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_29_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT211 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_28_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_28_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT201 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_27_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_27_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT191 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_26_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_26_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT181 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_25_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_25_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT171 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_24_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_24_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT161 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_23_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_23_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT151 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_22_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_22_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT141 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_21_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_21_Q
);
curr_state_FSM_FFd3_In1 : LUT4
generic map(
INIT => X"7D75"
)
port map (
I0 => curr_state_FSM_FFd2_267,
I1 => curr_state_FSM_FFd1_150,
I2 => curr_state_FSM_FFd3_266,
I3 => layer_map_shift_map_0_shifter_map_shift_over_flag_34,
O => curr_state_FSM_FFd3_In
);
layer_map_shift_map_0_shifter_map_enable_inv1 : LUT4
generic map(
INIT => X"F137"
)
port map (
I0 => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o,
I1 => curr_state_FSM_FFd2_267,
I2 => curr_state_FSM_FFd1_150,
I3 => curr_state_FSM_FFd3_266,
O => layer_map_shift_map_0_shifter_map_enable_inv
);
curr_state_FSM_FFd2_In1 : LUT5
generic map(
INIT => X"B2BEA2AE"
)
port map (
I0 => curr_state_FSM_FFd2_267,
I1 => curr_state_FSM_FFd1_150,
I2 => curr_state_FSM_FFd3_266,
I3 => layer_map_shift_map_0_shifter_map_shift_over_flag_34,
I4 => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o,
O => curr_state_FSM_FFd2_In
);
curr_state_FSM_FFd1_In1 : LUT5
generic map(
INIT => X"7A6A3A2A"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o,
I4 => layer_map_shift_map_0_shifter_map_shift_over_flag_34,
O => curr_state_FSM_FFd1_In
);
clk_BUFGP : BUFGP
port map (
I => clk,
O => clk_BUFGP_0
);
Madd_transition_num_31_GND_7_o_add_6_OUT_lut_0_INV_0 : INV
port map (
I => transition_num(0),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_lut_0_Q
);
layer_map_activation_hid_count_map_Mcount_count_lut_0_INV_0 : INV
port map (
I => layer_map_activation_hid_count_map_count(0),
O => layer_map_activation_hid_count_map_Mcount_count_lut(0)
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_lut_0_INV_0 : INV
port map (
I => layer_map_shift_map_0_shifter_map_shifter_shift_counter_0_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_lut_0_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_lut_0_INV_0 : INV
port map (
I => layer_map_shift_map_1_shifter_map_shifter_shift_counter_0_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_lut_0_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_lut_0_INV_0 : INV
port map (
I => layer_map_shift_map_2_shifter_map_shifter_shift_counter_0_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_lut_0_Q
);
test_image_map : test_image
port map (
clka => clk_BUFGP_0,
wea(0) => dina_image(0),
addra(2) => addra_image(2),
addra(1) => addra_image(1),
addra(0) => addra_image(0),
dina(7) => dina_image(0),
dina(6) => dina_image(0),
dina(5) => dina_image(0),
dina(4) => dina_image(0),
dina(3) => dina_image(0),
dina(2) => dina_image(0),
dina(1) => dina_image(0),
dina(0) => dina_image(0),
douta(7) => image(7),
douta(6) => image(6),
douta(5) => image(5),
douta(4) => image(4),
douta(3) => image(3),
douta(2) => image(2),
douta(1) => image(1),
douta(0) => image(0)
);
weight_hid_map : weight_hid
port map (
clka => clk_BUFGP_0,
wea(0) => dina_image(0),
addra(2) => addra_image(2),
addra(1) => addra_image(1),
addra(0) => addra_image(0),
dina(23) => dina_image(0),
dina(22) => dina_image(0),
dina(21) => dina_image(0),
dina(20) => dina_image(0),
dina(19) => dina_image(0),
dina(18) => dina_image(0),
dina(17) => dina_image(0),
dina(16) => dina_image(0),
dina(15) => dina_image(0),
dina(14) => dina_image(0),
dina(13) => dina_image(0),
dina(12) => dina_image(0),
dina(11) => dina_image(0),
dina(10) => dina_image(0),
dina(9) => dina_image(0),
dina(8) => dina_image(0),
dina(7) => dina_image(0),
dina(6) => dina_image(0),
dina(5) => dina_image(0),
dina(4) => dina_image(0),
dina(3) => dina_image(0),
dina(2) => dina_image(0),
dina(1) => dina_image(0),
dina(0) => dina_image(0),
douta(23) => out_weight_hid(23),
douta(22) => out_weight_hid(22),
douta(21) => out_weight_hid(21),
douta(20) => out_weight_hid(20),
douta(19) => out_weight_hid(19),
douta(18) => out_weight_hid(18),
douta(17) => out_weight_hid(17),
douta(16) => out_weight_hid(16),
douta(15) => out_weight_hid(15),
douta(14) => out_weight_hid(14),
douta(13) => out_weight_hid(13),
douta(12) => out_weight_hid(12),
douta(11) => out_weight_hid(11),
douta(10) => out_weight_hid(10),
douta(9) => out_weight_hid(9),
douta(8) => out_weight_hid(8),
douta(7) => out_weight_hid(7),
douta(6) => out_weight_hid(6),
douta(5) => out_weight_hid(5),
douta(4) => out_weight_hid(4),
douta(3) => out_weight_hid(3),
douta(2) => out_weight_hid(2),
douta(1) => out_weight_hid(1),
douta(0) => out_weight_hid(0)
);
weight_out_map : weight_out
port map (
clka => clk_BUFGP_0,
wea(0) => dina_image(0),
addra(2) => addr_weight_out(2),
addra(1) => addr_weight_out(1),
addra(0) => addr_weight_out(0),
dina(23) => dina_image(0),
dina(22) => dina_image(0),
dina(21) => dina_image(0),
dina(20) => dina_image(0),
dina(19) => dina_image(0),
dina(18) => dina_image(0),
dina(17) => dina_image(0),
dina(16) => dina_image(0),
dina(15) => dina_image(0),
dina(14) => dina_image(0),
dina(13) => dina_image(0),
dina(12) => dina_image(0),
dina(11) => dina_image(0),
dina(10) => dina_image(0),
dina(9) => dina_image(0),
dina(8) => dina_image(0),
dina(7) => dina_image(0),
dina(6) => dina_image(0),
dina(5) => dina_image(0),
dina(4) => dina_image(0),
dina(3) => dina_image(0),
dina(2) => dina_image(0),
dina(1) => dina_image(0),
dina(0) => dina_image(0),
douta(23) => out_weight_out(23),
douta(22) => out_weight_out(22),
douta(21) => out_weight_out(21),
douta(20) => out_weight_out(20),
douta(19) => out_weight_out(19),
douta(18) => out_weight_out(18),
douta(17) => out_weight_out(17),
douta(16) => out_weight_out(16),
douta(15) => out_weight_out(15),
douta(14) => out_weight_out(14),
douta(13) => out_weight_out(13),
douta(12) => out_weight_out(12),
douta(11) => out_weight_out(11),
douta(10) => out_weight_out(10),
douta(9) => out_weight_out(9),
douta(8) => out_weight_out(8),
douta(7) => out_weight_out(7),
douta(6) => out_weight_out(6),
douta(5) => out_weight_out(5),
douta(4) => out_weight_out(4),
douta(3) => out_weight_out(3),
douta(2) => out_weight_out(2),
douta(1) => out_weight_out(1),
douta(0) => out_weight_out(0)
);
layer_map_neuron_map_2_neurons_mul_hid_map : mul_hid
port map (
clk => clk_BUFGP_0,
ce => layer_map_ce,
sclr => dina_image(0),
bypass => dina_image(0),
a(7) => input(7),
a(6) => input(6),
a(5) => input(5),
a(4) => input(4),
a(3) => input(3),
a(2) => input(2),
a(1) => input(1),
a(0) => input(0),
b(7) => weight(2, 7),
b(6) => weight(2, 6),
b(5) => weight(2, 5),
b(4) => weight(2, 4),
b(3) => weight(2, 3),
b(2) => weight(2, 2),
b(1) => weight(2, 1),
b(0) => weight(2, 0),
s(15) => layer_map_weighted_sum(2, 15),
s(14) => layer_map_weighted_sum(2, 14),
s(13) => layer_map_weighted_sum(2, 13),
s(12) => layer_map_weighted_sum(2, 12),
s(11) => layer_map_weighted_sum(2, 11),
s(10) => layer_map_weighted_sum(2, 10),
s(9) => layer_map_weighted_sum(2, 9),
s(8) => layer_map_weighted_sum(2, 8),
s(7) => layer_map_weighted_sum(2, 7),
s(6) => layer_map_weighted_sum(2, 6),
s(5) => layer_map_weighted_sum(2, 5),
s(4) => layer_map_weighted_sum(2, 4),
s(3) => layer_map_weighted_sum(2, 3),
s(2) => layer_map_weighted_sum(2, 2),
s(1) => layer_map_weighted_sum(2, 1),
s(0) => layer_map_weighted_sum(2, 0)
);
layer_map_neuron_map_1_neurons_mul_hid_map : mul_hid
port map (
clk => clk_BUFGP_0,
ce => layer_map_ce,
sclr => dina_image(0),
bypass => dina_image(0),
a(7) => input(7),
a(6) => input(6),
a(5) => input(5),
a(4) => input(4),
a(3) => input(3),
a(2) => input(2),
a(1) => input(1),
a(0) => input(0),
b(7) => weight(1, 7),
b(6) => weight(1, 6),
b(5) => weight(1, 5),
b(4) => weight(1, 4),
b(3) => weight(1, 3),
b(2) => weight(1, 2),
b(1) => weight(1, 1),
b(0) => weight(1, 0),
s(15) => layer_map_weighted_sum(1, 15),
s(14) => layer_map_weighted_sum(1, 14),
s(13) => layer_map_weighted_sum(1, 13),
s(12) => layer_map_weighted_sum(1, 12),
s(11) => layer_map_weighted_sum(1, 11),
s(10) => layer_map_weighted_sum(1, 10),
s(9) => layer_map_weighted_sum(1, 9),
s(8) => layer_map_weighted_sum(1, 8),
s(7) => layer_map_weighted_sum(1, 7),
s(6) => layer_map_weighted_sum(1, 6),
s(5) => layer_map_weighted_sum(1, 5),
s(4) => layer_map_weighted_sum(1, 4),
s(3) => layer_map_weighted_sum(1, 3),
s(2) => layer_map_weighted_sum(1, 2),
s(1) => layer_map_weighted_sum(1, 1),
s(0) => layer_map_weighted_sum(1, 0)
);
layer_map_neuron_map_0_neurons_mul_hid_map : mul_hid
port map (
clk => clk_BUFGP_0,
ce => layer_map_ce,
sclr => dina_image(0),
bypass => dina_image(0),
a(7) => input(7),
a(6) => input(6),
a(5) => input(5),
a(4) => input(4),
a(3) => input(3),
a(2) => input(2),
a(1) => input(1),
a(0) => input(0),
b(7) => weight(0, 7),
b(6) => weight(0, 6),
b(5) => weight(0, 5),
b(4) => weight(0, 4),
b(3) => weight(0, 3),
b(2) => weight(0, 2),
b(1) => weight(0, 1),
b(0) => weight(0, 0),
s(15) => layer_map_weighted_sum(0, 15),
s(14) => layer_map_weighted_sum(0, 14),
s(13) => layer_map_weighted_sum(0, 13),
s(12) => layer_map_weighted_sum(0, 12),
s(11) => layer_map_weighted_sum(0, 11),
s(10) => layer_map_weighted_sum(0, 10),
s(9) => layer_map_weighted_sum(0, 9),
s(8) => layer_map_weighted_sum(0, 8),
s(7) => layer_map_weighted_sum(0, 7),
s(6) => layer_map_weighted_sum(0, 6),
s(5) => layer_map_weighted_sum(0, 5),
s(4) => layer_map_weighted_sum(0, 4),
s(3) => layer_map_weighted_sum(0, 3),
s(2) => layer_map_weighted_sum(0, 2),
s(1) => layer_map_weighted_sum(0, 1),
s(0) => layer_map_weighted_sum(0, 0)
);
layer_map_shift_map_2_shifter_map_acticv_mul_map : acticv_mul
port map (
clk => clk_BUFGP_0,
ce => layer_map_shift_map_2_shifter_map_acticv_mul_en_948,
a(15) => layer_map_shift_map_2_shifter_map_shifted_output_temp_15_Q,
a(14) => layer_map_shift_map_2_shifter_map_shifted_output_temp_14_Q,
a(13) => layer_map_shift_map_2_shifter_map_shifted_output_temp_13_Q,
a(12) => layer_map_shift_map_2_shifter_map_shifted_output_temp_12_Q,
a(11) => layer_map_shift_map_2_shifter_map_shifted_output_temp_11_Q,
a(10) => layer_map_shift_map_2_shifter_map_shifted_output_temp_10_Q,
a(9) => layer_map_shift_map_2_shifter_map_shifted_output_temp_9_Q,
a(8) => layer_map_shift_map_2_shifter_map_shifted_output_temp_8_Q,
a(7) => layer_map_shift_map_2_shifter_map_shifted_output_temp_7_Q,
a(6) => layer_map_shift_map_2_shifter_map_shifted_output_temp_6_Q,
a(5) => layer_map_shift_map_2_shifter_map_shifted_output_temp_5_Q,
a(4) => layer_map_shift_map_2_shifter_map_shifted_output_temp_4_Q,
a(3) => layer_map_shift_map_2_shifter_map_shifted_output_temp_3_Q,
a(2) => layer_map_shift_map_2_shifter_map_shifted_output_temp_2_Q,
a(1) => layer_map_shift_map_2_shifter_map_shifted_output_temp_1_Q,
a(0) => layer_map_shift_map_2_shifter_map_shifted_output_temp_0_Q,
b(15) => layer_map_shift_map_2_shifter_map_input_temp_15_Q,
b(14) => layer_map_shift_map_2_shifter_map_input_temp_14_Q,
b(13) => layer_map_shift_map_2_shifter_map_input_temp_13_Q,
b(12) => layer_map_shift_map_2_shifter_map_input_temp_12_Q,
b(11) => layer_map_shift_map_2_shifter_map_input_temp_11_Q,
b(10) => layer_map_shift_map_2_shifter_map_input_temp_10_Q,
b(9) => layer_map_shift_map_2_shifter_map_input_temp_9_Q,
b(8) => layer_map_shift_map_2_shifter_map_input_temp_8_Q,
b(7) => layer_map_shift_map_2_shifter_map_input_temp_7_Q,
b(6) => layer_map_shift_map_2_shifter_map_input_temp_6_Q,
b(5) => layer_map_shift_map_2_shifter_map_input_temp_5_Q,
b(4) => layer_map_shift_map_2_shifter_map_input_temp_4_Q,
b(3) => layer_map_shift_map_2_shifter_map_input_temp_3_Q,
b(2) => layer_map_shift_map_2_shifter_map_input_temp_2_Q,
b(1) => layer_map_shift_map_2_shifter_map_input_temp_1_Q,
b(0) => layer_map_shift_map_2_shifter_map_input_temp_0_Q,
d(15) => dina_image(0),
d(14) => dina_image(0),
d(13) => dina_image(0),
d(12) => N0,
d(11) => dina_image(0),
d(10) => dina_image(0),
d(9) => dina_image(0),
d(8) => dina_image(0),
d(7) => dina_image(0),
d(6) => dina_image(0),
d(5) => dina_image(0),
d(4) => dina_image(0),
d(3) => dina_image(0),
d(2) => dina_image(0),
d(1) => dina_image(0),
d(0) => dina_image(0),
p(31) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_31_UNCONNECTED,
p(30) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_30_UNCONNECTED,
p(29) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_29_UNCONNECTED,
p(28) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_28_UNCONNECTED,
p(27) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_27_UNCONNECTED,
p(26) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_26_UNCONNECTED,
p(25) => output_hid(2, 7),
p(24) => output_hid(2, 6),
p(23) => output_hid(2, 5),
p(22) => output_hid(2, 4),
p(21) => output_hid(2, 3),
p(20) => output_hid(2, 2),
p(19) => output_hid(2, 1),
p(18) => output_hid(2, 0),
p(17) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_17_UNCONNECTED,
p(16) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_16_UNCONNECTED,
p(15) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_15_UNCONNECTED,
p(14) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_14_UNCONNECTED,
p(13) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_13_UNCONNECTED,
p(12) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_12_UNCONNECTED,
p(11) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_11_UNCONNECTED,
p(10) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_10_UNCONNECTED,
p(9) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_9_UNCONNECTED,
p(8) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_8_UNCONNECTED,
p(7) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_7_UNCONNECTED,
p(6) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_6_UNCONNECTED,
p(5) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_5_UNCONNECTED,
p(4) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_4_UNCONNECTED,
p(3) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_3_UNCONNECTED,
p(2) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_2_UNCONNECTED,
p(1) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_1_UNCONNECTED,
p(0) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_0_UNCONNECTED
);
layer_map_shift_map_1_shifter_map_acticv_mul_map : acticv_mul
port map (
clk => clk_BUFGP_0,
ce => layer_map_shift_map_1_shifter_map_acticv_mul_en_755,
a(15) => layer_map_shift_map_1_shifter_map_shifted_output_temp_15_Q,
a(14) => layer_map_shift_map_1_shifter_map_shifted_output_temp_14_Q,
a(13) => layer_map_shift_map_1_shifter_map_shifted_output_temp_13_Q,
a(12) => layer_map_shift_map_1_shifter_map_shifted_output_temp_12_Q,
a(11) => layer_map_shift_map_1_shifter_map_shifted_output_temp_11_Q,
a(10) => layer_map_shift_map_1_shifter_map_shifted_output_temp_10_Q,
a(9) => layer_map_shift_map_1_shifter_map_shifted_output_temp_9_Q,
a(8) => layer_map_shift_map_1_shifter_map_shifted_output_temp_8_Q,
a(7) => layer_map_shift_map_1_shifter_map_shifted_output_temp_7_Q,
a(6) => layer_map_shift_map_1_shifter_map_shifted_output_temp_6_Q,
a(5) => layer_map_shift_map_1_shifter_map_shifted_output_temp_5_Q,
a(4) => layer_map_shift_map_1_shifter_map_shifted_output_temp_4_Q,
a(3) => layer_map_shift_map_1_shifter_map_shifted_output_temp_3_Q,
a(2) => layer_map_shift_map_1_shifter_map_shifted_output_temp_2_Q,
a(1) => layer_map_shift_map_1_shifter_map_shifted_output_temp_1_Q,
a(0) => layer_map_shift_map_1_shifter_map_shifted_output_temp_0_Q,
b(15) => layer_map_shift_map_1_shifter_map_input_temp_15_Q,
b(14) => layer_map_shift_map_1_shifter_map_input_temp_14_Q,
b(13) => layer_map_shift_map_1_shifter_map_input_temp_13_Q,
b(12) => layer_map_shift_map_1_shifter_map_input_temp_12_Q,
b(11) => layer_map_shift_map_1_shifter_map_input_temp_11_Q,
b(10) => layer_map_shift_map_1_shifter_map_input_temp_10_Q,
b(9) => layer_map_shift_map_1_shifter_map_input_temp_9_Q,
b(8) => layer_map_shift_map_1_shifter_map_input_temp_8_Q,
b(7) => layer_map_shift_map_1_shifter_map_input_temp_7_Q,
b(6) => layer_map_shift_map_1_shifter_map_input_temp_6_Q,
b(5) => layer_map_shift_map_1_shifter_map_input_temp_5_Q,
b(4) => layer_map_shift_map_1_shifter_map_input_temp_4_Q,
b(3) => layer_map_shift_map_1_shifter_map_input_temp_3_Q,
b(2) => layer_map_shift_map_1_shifter_map_input_temp_2_Q,
b(1) => layer_map_shift_map_1_shifter_map_input_temp_1_Q,
b(0) => layer_map_shift_map_1_shifter_map_input_temp_0_Q,
d(15) => dina_image(0),
d(14) => dina_image(0),
d(13) => dina_image(0),
d(12) => N0,
d(11) => dina_image(0),
d(10) => dina_image(0),
d(9) => dina_image(0),
d(8) => dina_image(0),
d(7) => dina_image(0),
d(6) => dina_image(0),
d(5) => dina_image(0),
d(4) => dina_image(0),
d(3) => dina_image(0),
d(2) => dina_image(0),
d(1) => dina_image(0),
d(0) => dina_image(0),
p(31) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_31_UNCONNECTED,
p(30) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_30_UNCONNECTED,
p(29) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_29_UNCONNECTED,
p(28) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_28_UNCONNECTED,
p(27) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_27_UNCONNECTED,
p(26) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_26_UNCONNECTED,
p(25) => output_hid(1, 7),
p(24) => output_hid(1, 6),
p(23) => output_hid(1, 5),
p(22) => output_hid(1, 4),
p(21) => output_hid(1, 3),
p(20) => output_hid(1, 2),
p(19) => output_hid(1, 1),
p(18) => output_hid(1, 0),
p(17) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_17_UNCONNECTED,
p(16) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_16_UNCONNECTED,
p(15) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_15_UNCONNECTED,
p(14) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_14_UNCONNECTED,
p(13) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_13_UNCONNECTED,
p(12) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_12_UNCONNECTED,
p(11) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_11_UNCONNECTED,
p(10) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_10_UNCONNECTED,
p(9) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_9_UNCONNECTED,
p(8) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_8_UNCONNECTED,
p(7) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_7_UNCONNECTED,
p(6) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_6_UNCONNECTED,
p(5) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_5_UNCONNECTED,
p(4) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_4_UNCONNECTED,
p(3) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_3_UNCONNECTED,
p(2) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_2_UNCONNECTED,
p(1) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_1_UNCONNECTED,
p(0) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_0_UNCONNECTED
);
layer_map_shift_map_0_shifter_map_acticv_mul_map : acticv_mul
port map (
clk => clk_BUFGP_0,
ce => layer_map_shift_map_0_shifter_map_acticv_mul_en_562,
a(15) => layer_map_shift_map_0_shifter_map_shifted_output_temp_15_Q,
a(14) => layer_map_shift_map_0_shifter_map_shifted_output_temp_14_Q,
a(13) => layer_map_shift_map_0_shifter_map_shifted_output_temp_13_Q,
a(12) => layer_map_shift_map_0_shifter_map_shifted_output_temp_12_Q,
a(11) => layer_map_shift_map_0_shifter_map_shifted_output_temp_11_Q,
a(10) => layer_map_shift_map_0_shifter_map_shifted_output_temp_10_Q,
a(9) => layer_map_shift_map_0_shifter_map_shifted_output_temp_9_Q,
a(8) => layer_map_shift_map_0_shifter_map_shifted_output_temp_8_Q,
a(7) => layer_map_shift_map_0_shifter_map_shifted_output_temp_7_Q,
a(6) => layer_map_shift_map_0_shifter_map_shifted_output_temp_6_Q,
a(5) => layer_map_shift_map_0_shifter_map_shifted_output_temp_5_Q,
a(4) => layer_map_shift_map_0_shifter_map_shifted_output_temp_4_Q,
a(3) => layer_map_shift_map_0_shifter_map_shifted_output_temp_3_Q,
a(2) => layer_map_shift_map_0_shifter_map_shifted_output_temp_2_Q,
a(1) => layer_map_shift_map_0_shifter_map_shifted_output_temp_1_Q,
a(0) => layer_map_shift_map_0_shifter_map_shifted_output_temp_0_Q,
b(15) => layer_map_shift_map_0_shifter_map_input_temp_15_Q,
b(14) => layer_map_shift_map_0_shifter_map_input_temp_14_Q,
b(13) => layer_map_shift_map_0_shifter_map_input_temp_13_Q,
b(12) => layer_map_shift_map_0_shifter_map_input_temp_12_Q,
b(11) => layer_map_shift_map_0_shifter_map_input_temp_11_Q,
b(10) => layer_map_shift_map_0_shifter_map_input_temp_10_Q,
b(9) => layer_map_shift_map_0_shifter_map_input_temp_9_Q,
b(8) => layer_map_shift_map_0_shifter_map_input_temp_8_Q,
b(7) => layer_map_shift_map_0_shifter_map_input_temp_7_Q,
b(6) => layer_map_shift_map_0_shifter_map_input_temp_6_Q,
b(5) => layer_map_shift_map_0_shifter_map_input_temp_5_Q,
b(4) => layer_map_shift_map_0_shifter_map_input_temp_4_Q,
b(3) => layer_map_shift_map_0_shifter_map_input_temp_3_Q,
b(2) => layer_map_shift_map_0_shifter_map_input_temp_2_Q,
b(1) => layer_map_shift_map_0_shifter_map_input_temp_1_Q,
b(0) => layer_map_shift_map_0_shifter_map_input_temp_0_Q,
d(15) => dina_image(0),
d(14) => dina_image(0),
d(13) => dina_image(0),
d(12) => N0,
d(11) => dina_image(0),
d(10) => dina_image(0),
d(9) => dina_image(0),
d(8) => dina_image(0),
d(7) => dina_image(0),
d(6) => dina_image(0),
d(5) => dina_image(0),
d(4) => dina_image(0),
d(3) => dina_image(0),
d(2) => dina_image(0),
d(1) => dina_image(0),
d(0) => dina_image(0),
p(31) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_31_UNCONNECTED,
p(30) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_30_UNCONNECTED,
p(29) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_29_UNCONNECTED,
p(28) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_28_UNCONNECTED,
p(27) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_27_UNCONNECTED,
p(26) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_26_UNCONNECTED,
p(25) => output_hid(0, 7),
p(24) => output_hid(0, 6),
p(23) => output_hid(0, 5),
p(22) => output_hid(0, 4),
p(21) => output_hid(0, 3),
p(20) => output_hid(0, 2),
p(19) => output_hid(0, 1),
p(18) => output_hid(0, 0),
p(17) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_17_UNCONNECTED,
p(16) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_16_UNCONNECTED,
p(15) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_15_UNCONNECTED,
p(14) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_14_UNCONNECTED,
p(13) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_13_UNCONNECTED,
p(12) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_12_UNCONNECTED,
p(11) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_11_UNCONNECTED,
p(10) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_10_UNCONNECTED,
p(9) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_9_UNCONNECTED,
p(8) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_8_UNCONNECTED,
p(7) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_7_UNCONNECTED,
p(6) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_6_UNCONNECTED,
p(5) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_5_UNCONNECTED,
p(4) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_4_UNCONNECTED,
p(3) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_3_UNCONNECTED,
p(2) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_2_UNCONNECTED,
p(1) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_1_UNCONNECTED,
p(0) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_0_UNCONNECTED
);
end Structure;
-- synthesis translate_on
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_processor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--TODO - make PC and address signals use std_logic_vector
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED;
entity befunge_processor is
generic
(
word_size : integer := 8;
instruction_size : integer := 16;
stack_size : integer := 2048;
grid_width : integer := 8;
grid_height : integer := 8
);
port
(
clk,reset : in std_logic;
data_in : in std_logic_vector(word_size-1 downto 0);
data_out : out std_logic_vector(word_size-1 downto 0)
);
end befunge_processor;
architecture processor_v1 of befunge_processor is
component befunge_pc is
generic(
grid_width : integer;
grid_height : integer
);
port(
clk : in std_logic;
reset : in std_logic;
address_x : out integer range 0 to grid_width-1;
address_y : out integer range 0 to grid_height-1;
dir : in std_logic_vector (1 downto 0);
skip : in std_logic;
en : in std_logic
);
end component;
constant LEFT_INSTRUCTION : integer range 0 to 255 := 62;
type stack_declaration is array(stack_size-1 downto 0) of std_logic_vector(word_size-1 downto 0);
signal stack : stack_declaration;
type grid_nibble is array (grid_height-1 downto 0) of std_logic_vector(word_size-1 downto 0);
type grid_stuff is array (grid_width-1 downto 0) of grid_nibble;
-- an array "array of array" type
variable grid : grid_stuff :=
(
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)))
);
type fde_cycle_states is (idle,fetch,decode,execute);
signal fde_cycle : fde_cycle_states := idle;
type befunge_instruction_set is (move_left,move_right,move_up,move_down);
signal instruction : befunge_instruction_set;
signal grid_data_in : std_logic_vector(word_size-1 downto 0);
signal grid_data_out : std_logic_vector(word_size-1 downto 0);
signal grid_address : integer range 0 to (grid_width*grid_height)-1;
--signal grid_address_y : integer range 0 to grid_height-1;
signal grid_load : std_logic;
signal grid_store : std_logic;
signal dir : std_logic_vector(1 downto 0);
signal pc_address_x : integer range 0 to grid_width-1;
signal pc_address_y : integer range 0 to grid_height-1;
signal pc_skip : std_logic;
signal pc_enable : std_logic;
signal stack_ptr : integer range 0 to stack_size-1;
signal stack_s0 : std_logic_vector(word_size-1 downto 0); --Top of stack
signal stack_s1 : std_logic_vector(word_size-1 downto 0); --Stack -1
begin
data_out <= grid_data_out;
--this will kick up shit if we want to do read/write from the stack any other time
--maybe best to keep a copy of these whenever pushes or pops occur?
stack_s0 <= stack(stack_ptr);
--stack_s1 <= stack(stack_ptr-1);
program_counter : befunge_pc
generic map
(
grid_width => grid_width,
grid_height => grid_height
)
port map
(
clk => clk,
reset => reset,
address_x => pc_address_x,
address_y => pc_address_y,
dir => dir,
skip => pc_skip,
en => pc_enable
);
--TODO : this shit needs casted
grid_address <= to_integer(signed(stack_s0));
--grid_address_y <= stack_s1;
--The grid must handle a write from a store instruction
--the grid must handle a read from the pc address
--the grid must handle a read from a load instruction
grid_process : process(reset,clk, grid_store,instruction)
begin
if(reset = '1') then
fde_cycle <= idle;
else
if rising_edge(clk) then
--set all signals inside this and we're laughing
--fetch execute cycle that we can use to synchronise read/write signals
case fde_cycle is
when idle =>
grid_load <= '0';
when fetch =>
grid_load <= '1';
fde_cycle <= decode;
when decode =>
grid_load <= '0';
fde_cycle <= execute;
when execute =>
grid_load <= '0';
case instruction is
when move_left =>
dir <= "10";
fde_cycle <= fetch;
when move_right =>
dir <= "00";
fde_cycle <= fetch;
when move_up =>
dir <= "01";
fde_cycle <= fetch;
when move_down =>
dir <= "11";
fde_cycle <= fetch;
when others =>
fde_cycle <= idle;
end case;
--fed_cycle <= idle;
end case;
--only write the grid when the grid_store flag is enabled
if (grid_store = '1') then
grid(grid_address_x,grid_address_y) <= grid_data_in;
end if;
if (grid_load = '1') then
grid_data_out <= grid(grid_address);
else
grid_data_out <= grid(pc_address);
end if;
end if;
end if;
end process;
process(reset,clk,instruction,grid_data_out)
begin
if(reset = '1') then
instruction <= move_right;
else
if rising_edge(clk) then
case grid_data_out(7 downto 0) is
when X"3E" => --move right!!
instruction <= move_right;
when X"3C" => --move left!!
instruction <= move_left;
when X"5E" => --move up!!
instruction <= move_up;
when X"76" => --move down!!
instruction <= move_down;
when others =>
instruction <= move_right;
end case;
end if;
end if;
end process;
end processor_v1;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library device_lib;
configuration identical_devices of led_bar_display is
for device_level
for device_array
for limiting_resistor : resistor
use entity device_lib.resistor(ideal);
end for;
for segment_led : led
use entity device_lib.led(ideal);
end for;
end for;
end for;
end configuration identical_devices;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library device_lib;
configuration identical_devices of led_bar_display is
for device_level
for device_array
for limiting_resistor : resistor
use entity device_lib.resistor(ideal);
end for;
for segment_led : led
use entity device_lib.led(ideal);
end for;
end for;
end for;
end configuration identical_devices;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library device_lib;
configuration identical_devices of led_bar_display is
for device_level
for device_array
for limiting_resistor : resistor
use entity device_lib.resistor(ideal);
end for;
for segment_led : led
use entity device_lib.led(ideal);
end for;
end for;
end for;
end configuration identical_devices;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM64K36 is
-- pragma translate_off
generic (MEMORYFILE:string := "");
-- pragma translate_on
port(
DEPTH3, DEPTH2, DEPTH1, DEPTH0,
WRAD15, WRAD14, WRAD13, WRAD12, WRAD11, WRAD10, WRAD9 ,
WRAD8 , WRAD7 , WRAD6 , WRAD5 , WRAD4 , WRAD3 , WRAD2 ,
WRAD1 , WRAD0 , WD35 , WD34 , WD33 , WD32 , WD31 ,
WD30 , WD29 , WD28 , WD27 , WD26 , WD25 , WD24 ,
WD23 , WD22 , WD21 , WD20 , WD19 , WD18 , WD17 ,
WD16 , WD15 , WD14 , WD13 , WD12 , WD11 , WD10 ,
WD9 , WD8 , WD7 , WD6 , WD5 , WD4 , WD3 ,
WD2 , WD1 , WD0 , WW2 , WW1 , WW0 , WEN ,
WCLK , RDAD15, RDAD14, RDAD13, RDAD12, RDAD11, RDAD10,
RDAD9 , RDAD8 , RDAD7 , RDAD6 , RDAD5 , RDAD4 , RDAD3 ,
RDAD2 , RDAD1 , RDAD0 , RW2 , RW1 , RW0 , REN ,
RCLK : in std_ulogic ;
RD35 , RD34 , RD33 , RD32 , RD31 , RD30 , RD29 ,
RD28 , RD27 , RD26 , RD25 , RD24 , RD23 , RD22 ,
RD21 , RD20 , RD19 , RD18 , RD17 , RD16 , RD15 ,
RD14 , RD13 , RD12 , RD11 , RD10 , RD9 , RD8 ,
RD7 , RD6 , RD5 , RD4 , RD3 , RD2 , RD1 ,
RD0 : out std_ulogic);
end;
architecture rtl of RAM64K36 is
signal re : std_ulogic;
begin
rp : process(RCLK, WCLK)
constant words : integer := 2**16;
subtype word is std_logic_vector(35 downto 0);
type dregtype is array (0 to words - 1) of word;
variable rfd : dregtype;
variable wa, ra : std_logic_vector(15 downto 0);
variable q : std_logic_vector(35 downto 0);
begin
if rising_edge(RCLK) then
ra := RDAD15 & RDAD14 & RDAD13 & RDAD12 & RDAD11 & RDAD10 & RDAD9 &
RDAD8 & RDAD7 & RDAD6 & RDAD5 & RDAD4 & RDAD3 & RDAD2 & RDAD1 & RDAD0;
if not (is_x (ra)) and REN = '1' then
q := rfd(to_integer(unsigned(ra)) mod words);
else q := (others => 'X'); end if;
end if;
if rising_edge(WCLK) and (wen = '1') then
wa := WRAD15 & WRAD14 & WRAD13 & WRAD12 & WRAD11 & WRAD10 & WRAD9 &
WRAD8 & WRAD7 & WRAD6 & WRAD5 & WRAD4 & WRAD3 & WRAD2 & WRAD1 & WRAD0;
if not is_x (wa) then
rfd(to_integer(unsigned(wa)) mod words) :=
WD35 & WD34 & WD33 & WD32 & WD31 & WD30 & WD29 & WD28 & WD27 &
WD26 & WD25 & WD24 & WD23 & WD22 & WD21 & WD20 & WD19 & WD18 &
WD17 & WD16 & WD15 & WD14 & WD13 & WD12 & WD11 & WD10 & WD9 &
WD8 & WD7 & WD6 & WD5 & WD4 & WD3 & WD2 & WD1 & WD0;
end if;
if ra = wa then q := (others => 'X'); end if; -- no write-through
end if;
RD35 <= q(35); RD34 <= q(34); RD33 <= q(33); RD32 <= q(32); RD31 <= q(31);
RD30 <= q(30); RD29 <= q(29); RD28 <= q(28); RD27 <= q(27); RD26 <= q(26);
RD25 <= q(25); RD24 <= q(24); RD23 <= q(23); RD22 <= q(22); RD21 <= q(21);
RD20 <= q(20); RD19 <= q(19); RD18 <= q(18); RD17 <= q(17); RD16 <= q(16);
RD15 <= q(15); RD14 <= q(14); RD13 <= q(13); RD12 <= q(12); RD11 <= q(11);
RD10 <= q(10); RD9 <= q(9); RD8 <= q(8); RD7 <= q(7); RD6 <= q(6);
RD5 <= q(5); RD4 <= q(4); RD3 <= q(3); RD2 <= q(2); RD1 <= q(1);
RD0 <= q(0);
end process;
end;
-- PCI PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf_pci is begin y <= to_X01(pad) after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf_pci is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf_pci is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff_pci is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff_pci is begin
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_pci is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_pci is begin pad <= d after 5 ns; end;
-- STANDARD PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_in is port( pad : in std_logic; y : out std_logic); end;
architecture struct of iopad_in is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_in_u is port( pad : in std_logic; y : out std_logic); end;
architecture struct of iopad_in_u is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_in_u is port( pad : in std_logic; y : out std_logic); end;
architecture struct of iopad_in_u is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_bi is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of iopad_bi is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_tri is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopad_tri is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_tri_u is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopad_tri_u is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadp_tri is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopadp_tri is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadp_in is port (n2pin, pad : in std_logic; y : out std_logic ); end;
architecture struct of iopadp_in is begin
y <= pad after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadn_in is port ( pad : in std_logic; n2pout : out std_logic ); end;
architecture struct of iopadn_in is begin
n2pout <= pad after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadn_tri is port (db, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopadn_tri is begin
pad <= not db after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_8 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_8 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_12 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_12 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_16 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_16 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_24 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_24 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_lvds is port( y : out std_logic; padp, padn : in std_logic); end;
architecture struct of inbuf_lvds is
signal yn : std_ulogic := '0';
begin
yn <= to_X01(padp) after 1 ns when to_x01(padp xor padn) = '1' else yn after 1 ns;
y <= yn;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_lvds is port (d : in std_logic; padp, padn : out std_logic ); end;
architecture struct of outbuf_lvds is begin
padp <= d after 1 ns;
padn <= not d after 1 ns;
end;
-- clock buffers ----------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of hclkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of clkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity IOFIFO_BIBUF is
port( AIN : in std_logic;
AOUT : in std_logic;
YIN : out std_logic;
YOUT : out std_logic
);
end ;
architecture struct of IOFIFO_BIBUF is begin
YIN <= to_X01(AIN);
YOUT <= to_X01(AOUT);
end;
library ieee;
use ieee.std_logic_1164.all;
entity add1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end add1;
architecture beh of add1 is
signal un1_fco : std_logic;
signal un2_fco : std_logic;
signal un3_fco : std_logic;
begin
s <= a xor b xor fci;
un1_fco <= a and b;
un2_fco <= a and fci;
un3_fco <= b and fci;
fco <= un1_fco or un2_fco or un3_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2;
architecture beh of and2 is
begin
y <= b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2a;
architecture beh of and2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2b;
architecture beh of and2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3;
architecture beh of and3 is
begin
y <= c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3a;
architecture beh of and3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3b;
architecture beh of and3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3c;
architecture beh of and3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4;
architecture beh of and4 is
begin
y <= d and c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4a;
architecture beh of and4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d and c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4b;
architecture beh of and4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d and c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4c;
architecture beh of and4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d and ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity buff is
port(
a : in std_logic;
y : out std_logic);
end buff;
architecture beh of buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ioi_buff is
port(
a : in std_logic;
y : out std_logic);
end ioi_buff;
architecture beh of ioi_buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iooe_buff is
port(
a : in std_logic;
y : out std_logic);
end iooe_buff;
architecture beh of iooe_buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iofifo_outbuf is
port(
a : in std_logic;
y : out std_logic);
end iofifo_outbuf;
architecture beh of iofifo_outbuf is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8buff is
port(
a : in std_logic;
y : out std_logic);
end cm8buff;
architecture beh of cm8buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity hclkmux is
port(
a : in std_logic;
y : out std_logic);
end hclkmux;
architecture beh of hclkmux is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity rclkmux is
port(
a : in std_logic;
y : out std_logic);
end rclkmux;
architecture beh of rclkmux is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity IOFIFO_INBUF is
port(
a : in std_logic;
y : out std_logic);
end IOFIFO_INBUF;
architecture beh of IOFIFO_INBUF is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity CLKINT_W is
port(
a : in std_logic;
y : out std_logic);
end CLKINT_W;
architecture beh of CLKINT_W is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity fcend_buff is
port(
fci : in std_logic;
co : out std_logic);
end fcend_buff;
architecture beh of fcend_buff is
begin
co <= fci;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity fcinit_buff is
port(
a : in std_logic;
fco : out std_logic);
end fcinit_buff;
architecture beh of fcinit_buff is
begin
fco <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8 is
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
s00 : in std_logic;
s01 : in std_logic;
s10 : in std_logic;
s11 : in std_logic;
y : out std_logic);
end cm8;
architecture beh of cm8 is
signal s0 : std_logic;
signal s1 : std_logic;
signal m0 : std_logic;
signal m1 : std_logic;
begin
s0 <= s01 and s00;
s1 <= s11 or s10;
m0 <= d0 when s0 = '0' else d1;
m1 <= d2 when s0 = '0' else d3;
y <= m0 when s1 = '0' else m1;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8inv is
port(
a : in std_logic;
y : out std_logic);
end cm8inv;
architecture beh of cm8inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity df1 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end df1;
architecture beh of df1 is
begin
ff : process (clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity df1b is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end df1b;
architecture beh of df1b is
begin
ff : process (clk)
begin
if falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1b is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1b;
architecture beh of dfc1b is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1c is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1c;
architecture beh of dfc1c is
begin
ff : process (clk, clr)
begin
if clr = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= not d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1d is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1d;
architecture beh of dfc1d is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe1b is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end dfe1b;
architecture beh of dfe1b is
signal q_int_1 : std_logic;
signal nq : std_logic;
begin
nq <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk)
begin
if rising_edge(clk) then
q_int_1 <= nq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe3c is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfe3c;
architecture beh of dfe3c is
signal q_int_0 : std_logic;
signal md : std_logic;
begin
md <= d when e = '0' else q_int_0;
q <= q_int_0;
ff : process (clk, clr)
begin
if clr = '0' then
q_int_0 <= '0';
elsif rising_edge(clk) then
q_int_0 <= md;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe4f is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfe4f;
architecture beh of dfe4f is
signal q_int_1 : std_logic;
signal un1 : std_logic;
begin
un1 <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk, pre)
begin
if pre = '0' then
q_int_1 <= '1';
elsif rising_edge(clk) then
q_int_1 <= un1;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1 is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1;
architecture beh of dfp1 is
begin
ff : process (clk, pre)
begin
if pre = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1b is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1b;
architecture beh of dfp1b is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1d is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1d;
architecture beh of dfp1d is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfeh is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic);
end dfeh;
architecture beh of dfeh is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif falling_edge(clk) and (e = '0') then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iooe_dfeh is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic;
yout : out std_logic);
end iooe_dfeh;
architecture beh of iooe_dfeh is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
yout <= '0';
elsif pre = '0' then
q <= '1';
yout <= '1';
elsif falling_edge(clk) and (e = '0') then
q <= d;
yout <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfeg is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic);
end dfeg;
architecture beh of dfeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif rising_edge(clk) and (e = '0') then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfmeg is
port(
a : in std_logic;
b : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
s : in std_logic;
q : out std_logic);
end dfmeg;
architecture beh of dfmeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif rising_edge(clk) and (e = '0') then
if s = '0' then q <= a; else q <= b; end if;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ioi_dfeg is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic);
end ioi_dfeg;
architecture beh of ioi_dfeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif rising_edge(clk) and (e = '0') then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iooe_dfeg is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic;
yout : out std_logic);
end iooe_dfeg;
architecture beh of iooe_dfeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
yout <= '0';
elsif pre = '0' then
q <= '1';
yout <= '1';
elsif rising_edge(clk) and (e = '0') then
q <= d;
yout <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity gnd is
port(
y : out std_logic);
end gnd;
architecture beh of gnd is
begin
y <= '0';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfm is
port(
clk : in std_logic;
s : in std_logic;
a : in std_logic;
b : in std_logic;
q : out std_logic);
end dfm;
architecture beh of dfm is
begin
ff : process (clk)
begin
if rising_edge(clk) then
if s = '0' then q <= a;
else q <= b; end if;
end if;
end process ff;
end beh;
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity hclkbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end hclkbuf;
--architecture beh of hclkbuf is
--begin
-- y <= pad;
--end beh;
--
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity inbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end inbuf;
--architecture beh of inbuf is
--begin
-- y <= pad;
--end beh;
library ieee;
use ieee.std_logic_1164.all;
entity inv is
port(
a : in std_logic;
y : out std_logic);
end inv;
architecture beh of inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity nand2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end nand2;
architecture beh of nand2 is
signal yx : std_logic;
begin
yx <= b and a;
y <= not yx;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity nand4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end nand4;
architecture beh of nand4 is
signal yx : std_logic;
begin
yx <= d and c and b and a;
y <= not yx;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2;
architecture beh of or2 is
begin
y <= b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2a;
architecture beh of or2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2b;
architecture beh of or2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3;
architecture beh of or3 is
begin
y <= c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3a;
architecture beh of or3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3b;
architecture beh of or3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3c;
architecture beh of or3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4;
architecture beh of or4 is
begin
y <= d or c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4a;
architecture beh of or4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d or c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4b;
architecture beh of or4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d or c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4c;
architecture beh of or4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4d is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4d;
architecture beh of or4d is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
signal di : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
di <= not d;
y <= di or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity sub1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end sub1;
architecture beh of sub1 is
signal un1_b : std_logic;
signal un3_fco : std_logic;
signal un1_fco : std_logic;
signal un4_fco : std_logic;
begin
un1_b <= not b;
un3_fco <= a and fci;
s <= a xor fci xor un1_b;
un1_fco <= a and un1_b;
un4_fco <= fci and un1_b;
fco <= un1_fco or un3_fco or un4_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity vcc is
port(
y : out std_logic);
end vcc;
architecture beh of vcc is
begin
y <= '1';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xa1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xa1;
architecture beh of xa1 is
signal xab : std_logic;
begin
xab <= b xor a;
y <= c and xab;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xnor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xnor2;
architecture beh of xnor2 is
signal yi : std_logic;
begin
yi <= b xor a;
y <= not yi;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xor2;
architecture beh of xor2 is
begin
y <= b xor a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xor3;
architecture beh of xor3 is
begin
y <= (c xor b) xor a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor4 is
port(a,b,c,d : in std_logic;
y : out std_logic);
end xor4;
architecture beh of xor4 is
signal xab, xcd : std_logic;
begin
xab <= b xor a;
xcd <= c xor d;
y <= xab xor xcd;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor4_fci is
port(a,b,c,fci : in std_logic;
y : out std_logic);
end xor4_fci;
architecture beh of xor4_fci is
signal xab, xcd : std_logic;
begin
xab <= b xor a;
xcd <= c xor fci;
y <= xab xor xcd;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity mx2 is
port(
a : in std_logic;
s : in std_logic;
b : in std_logic;
y : out std_logic);
end mx2;
architecture beh of mx2 is
signal xab : std_logic;
begin
y <= b when s = '0' else a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity mx4 is
port(
d0 : in std_logic;
s0 : in std_logic;
d1 : in std_logic;
s1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
y : out std_logic);
end mx4;
architecture beh of mx4 is
begin
y <= d0 when (s1 = '0' and s0 = '0') else
d1 when (s1 = '0' and s0 = '1') else
d2 when (s1 = '1' and s0 = '0') else d3;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity bufd is
port(
a : in std_logic;
y : out std_logic);
end bufd;
architecture beh of bufd is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xai1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xai1;
architecture beh of xai1 is
begin
y <= not (c and not (a xor b));
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ax1c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end ;
architecture beh of ax1c is
begin
y <= (a and b) xor c;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ax1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end ax1;
architecture beh of ax1 is
begin
y <= (((not a) and b) xor c);
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cy2a is
port(
a1 : in std_logic;
b1 : in std_logic;
a0 : in std_logic;
b0 : in std_logic;
y : out std_logic);
end cy2a;
architecture beh of cy2a is
begin
y <= ((( a1 AND b1 ) OR (( a0 AND b0 ) AND a1 )) OR (( a0 AND b0 ) AND b1 ));
end beh;
-- pragma translate_on
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM64K36 is
-- pragma translate_off
generic (MEMORYFILE:string := "");
-- pragma translate_on
port(
DEPTH3, DEPTH2, DEPTH1, DEPTH0,
WRAD15, WRAD14, WRAD13, WRAD12, WRAD11, WRAD10, WRAD9 ,
WRAD8 , WRAD7 , WRAD6 , WRAD5 , WRAD4 , WRAD3 , WRAD2 ,
WRAD1 , WRAD0 , WD35 , WD34 , WD33 , WD32 , WD31 ,
WD30 , WD29 , WD28 , WD27 , WD26 , WD25 , WD24 ,
WD23 , WD22 , WD21 , WD20 , WD19 , WD18 , WD17 ,
WD16 , WD15 , WD14 , WD13 , WD12 , WD11 , WD10 ,
WD9 , WD8 , WD7 , WD6 , WD5 , WD4 , WD3 ,
WD2 , WD1 , WD0 , WW2 , WW1 , WW0 , WEN ,
WCLK , RDAD15, RDAD14, RDAD13, RDAD12, RDAD11, RDAD10,
RDAD9 , RDAD8 , RDAD7 , RDAD6 , RDAD5 , RDAD4 , RDAD3 ,
RDAD2 , RDAD1 , RDAD0 , RW2 , RW1 , RW0 , REN ,
RCLK : in std_ulogic ;
RD35 , RD34 , RD33 , RD32 , RD31 , RD30 , RD29 ,
RD28 , RD27 , RD26 , RD25 , RD24 , RD23 , RD22 ,
RD21 , RD20 , RD19 , RD18 , RD17 , RD16 , RD15 ,
RD14 , RD13 , RD12 , RD11 , RD10 , RD9 , RD8 ,
RD7 , RD6 , RD5 , RD4 , RD3 , RD2 , RD1 ,
RD0 : out std_ulogic);
end;
architecture rtl of RAM64K36 is
signal re : std_ulogic;
begin
rp : process(RCLK, WCLK)
constant words : integer := 2**16;
subtype word is std_logic_vector(35 downto 0);
type dregtype is array (0 to words - 1) of word;
variable rfd : dregtype;
variable wa, ra : std_logic_vector(15 downto 0);
variable q : std_logic_vector(35 downto 0);
begin
if rising_edge(RCLK) then
ra := RDAD15 & RDAD14 & RDAD13 & RDAD12 & RDAD11 & RDAD10 & RDAD9 &
RDAD8 & RDAD7 & RDAD6 & RDAD5 & RDAD4 & RDAD3 & RDAD2 & RDAD1 & RDAD0;
if not (is_x (ra)) and REN = '1' then
q := rfd(to_integer(unsigned(ra)) mod words);
else q := (others => 'X'); end if;
end if;
if rising_edge(WCLK) and (wen = '1') then
wa := WRAD15 & WRAD14 & WRAD13 & WRAD12 & WRAD11 & WRAD10 & WRAD9 &
WRAD8 & WRAD7 & WRAD6 & WRAD5 & WRAD4 & WRAD3 & WRAD2 & WRAD1 & WRAD0;
if not is_x (wa) then
rfd(to_integer(unsigned(wa)) mod words) :=
WD35 & WD34 & WD33 & WD32 & WD31 & WD30 & WD29 & WD28 & WD27 &
WD26 & WD25 & WD24 & WD23 & WD22 & WD21 & WD20 & WD19 & WD18 &
WD17 & WD16 & WD15 & WD14 & WD13 & WD12 & WD11 & WD10 & WD9 &
WD8 & WD7 & WD6 & WD5 & WD4 & WD3 & WD2 & WD1 & WD0;
end if;
if ra = wa then q := (others => 'X'); end if; -- no write-through
end if;
RD35 <= q(35); RD34 <= q(34); RD33 <= q(33); RD32 <= q(32); RD31 <= q(31);
RD30 <= q(30); RD29 <= q(29); RD28 <= q(28); RD27 <= q(27); RD26 <= q(26);
RD25 <= q(25); RD24 <= q(24); RD23 <= q(23); RD22 <= q(22); RD21 <= q(21);
RD20 <= q(20); RD19 <= q(19); RD18 <= q(18); RD17 <= q(17); RD16 <= q(16);
RD15 <= q(15); RD14 <= q(14); RD13 <= q(13); RD12 <= q(12); RD11 <= q(11);
RD10 <= q(10); RD9 <= q(9); RD8 <= q(8); RD7 <= q(7); RD6 <= q(6);
RD5 <= q(5); RD4 <= q(4); RD3 <= q(3); RD2 <= q(2); RD1 <= q(1);
RD0 <= q(0);
end process;
end;
-- PCI PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf_pci is begin y <= to_X01(pad) after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf_pci is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf_pci is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff_pci is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff_pci is begin
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_pci is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_pci is begin pad <= d after 5 ns; end;
-- STANDARD PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_in is port( pad : in std_logic; y : out std_logic); end;
architecture struct of iopad_in is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_in_u is port( pad : in std_logic; y : out std_logic); end;
architecture struct of iopad_in_u is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_in_u is port( pad : in std_logic; y : out std_logic); end;
architecture struct of iopad_in_u is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_bi is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of iopad_bi is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_tri is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopad_tri is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_tri_u is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopad_tri_u is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadp_tri is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopadp_tri is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadp_in is port (n2pin, pad : in std_logic; y : out std_logic ); end;
architecture struct of iopadp_in is begin
y <= pad after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadn_in is port ( pad : in std_logic; n2pout : out std_logic ); end;
architecture struct of iopadn_in is begin
n2pout <= pad after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadn_tri is port (db, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopadn_tri is begin
pad <= not db after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_8 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_8 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_12 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_12 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_16 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_16 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_24 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_24 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_lvds is port( y : out std_logic; padp, padn : in std_logic); end;
architecture struct of inbuf_lvds is
signal yn : std_ulogic := '0';
begin
yn <= to_X01(padp) after 1 ns when to_x01(padp xor padn) = '1' else yn after 1 ns;
y <= yn;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_lvds is port (d : in std_logic; padp, padn : out std_logic ); end;
architecture struct of outbuf_lvds is begin
padp <= d after 1 ns;
padn <= not d after 1 ns;
end;
-- clock buffers ----------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of hclkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of clkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity IOFIFO_BIBUF is
port( AIN : in std_logic;
AOUT : in std_logic;
YIN : out std_logic;
YOUT : out std_logic
);
end ;
architecture struct of IOFIFO_BIBUF is begin
YIN <= to_X01(AIN);
YOUT <= to_X01(AOUT);
end;
library ieee;
use ieee.std_logic_1164.all;
entity add1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end add1;
architecture beh of add1 is
signal un1_fco : std_logic;
signal un2_fco : std_logic;
signal un3_fco : std_logic;
begin
s <= a xor b xor fci;
un1_fco <= a and b;
un2_fco <= a and fci;
un3_fco <= b and fci;
fco <= un1_fco or un2_fco or un3_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2;
architecture beh of and2 is
begin
y <= b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2a;
architecture beh of and2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2b;
architecture beh of and2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3;
architecture beh of and3 is
begin
y <= c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3a;
architecture beh of and3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3b;
architecture beh of and3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3c;
architecture beh of and3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4;
architecture beh of and4 is
begin
y <= d and c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4a;
architecture beh of and4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d and c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4b;
architecture beh of and4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d and c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4c;
architecture beh of and4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d and ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity buff is
port(
a : in std_logic;
y : out std_logic);
end buff;
architecture beh of buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ioi_buff is
port(
a : in std_logic;
y : out std_logic);
end ioi_buff;
architecture beh of ioi_buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iooe_buff is
port(
a : in std_logic;
y : out std_logic);
end iooe_buff;
architecture beh of iooe_buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iofifo_outbuf is
port(
a : in std_logic;
y : out std_logic);
end iofifo_outbuf;
architecture beh of iofifo_outbuf is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8buff is
port(
a : in std_logic;
y : out std_logic);
end cm8buff;
architecture beh of cm8buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity hclkmux is
port(
a : in std_logic;
y : out std_logic);
end hclkmux;
architecture beh of hclkmux is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity rclkmux is
port(
a : in std_logic;
y : out std_logic);
end rclkmux;
architecture beh of rclkmux is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity IOFIFO_INBUF is
port(
a : in std_logic;
y : out std_logic);
end IOFIFO_INBUF;
architecture beh of IOFIFO_INBUF is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity CLKINT_W is
port(
a : in std_logic;
y : out std_logic);
end CLKINT_W;
architecture beh of CLKINT_W is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity fcend_buff is
port(
fci : in std_logic;
co : out std_logic);
end fcend_buff;
architecture beh of fcend_buff is
begin
co <= fci;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity fcinit_buff is
port(
a : in std_logic;
fco : out std_logic);
end fcinit_buff;
architecture beh of fcinit_buff is
begin
fco <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8 is
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
s00 : in std_logic;
s01 : in std_logic;
s10 : in std_logic;
s11 : in std_logic;
y : out std_logic);
end cm8;
architecture beh of cm8 is
signal s0 : std_logic;
signal s1 : std_logic;
signal m0 : std_logic;
signal m1 : std_logic;
begin
s0 <= s01 and s00;
s1 <= s11 or s10;
m0 <= d0 when s0 = '0' else d1;
m1 <= d2 when s0 = '0' else d3;
y <= m0 when s1 = '0' else m1;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8inv is
port(
a : in std_logic;
y : out std_logic);
end cm8inv;
architecture beh of cm8inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity df1 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end df1;
architecture beh of df1 is
begin
ff : process (clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity df1b is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end df1b;
architecture beh of df1b is
begin
ff : process (clk)
begin
if falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1b is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1b;
architecture beh of dfc1b is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1c is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1c;
architecture beh of dfc1c is
begin
ff : process (clk, clr)
begin
if clr = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= not d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1d is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1d;
architecture beh of dfc1d is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe1b is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end dfe1b;
architecture beh of dfe1b is
signal q_int_1 : std_logic;
signal nq : std_logic;
begin
nq <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk)
begin
if rising_edge(clk) then
q_int_1 <= nq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe3c is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfe3c;
architecture beh of dfe3c is
signal q_int_0 : std_logic;
signal md : std_logic;
begin
md <= d when e = '0' else q_int_0;
q <= q_int_0;
ff : process (clk, clr)
begin
if clr = '0' then
q_int_0 <= '0';
elsif rising_edge(clk) then
q_int_0 <= md;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe4f is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfe4f;
architecture beh of dfe4f is
signal q_int_1 : std_logic;
signal un1 : std_logic;
begin
un1 <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk, pre)
begin
if pre = '0' then
q_int_1 <= '1';
elsif rising_edge(clk) then
q_int_1 <= un1;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1 is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1;
architecture beh of dfp1 is
begin
ff : process (clk, pre)
begin
if pre = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1b is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1b;
architecture beh of dfp1b is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1d is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1d;
architecture beh of dfp1d is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfeh is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic);
end dfeh;
architecture beh of dfeh is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif falling_edge(clk) and (e = '0') then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iooe_dfeh is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic;
yout : out std_logic);
end iooe_dfeh;
architecture beh of iooe_dfeh is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
yout <= '0';
elsif pre = '0' then
q <= '1';
yout <= '1';
elsif falling_edge(clk) and (e = '0') then
q <= d;
yout <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfeg is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic);
end dfeg;
architecture beh of dfeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif rising_edge(clk) and (e = '0') then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfmeg is
port(
a : in std_logic;
b : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
s : in std_logic;
q : out std_logic);
end dfmeg;
architecture beh of dfmeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif rising_edge(clk) and (e = '0') then
if s = '0' then q <= a; else q <= b; end if;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ioi_dfeg is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic);
end ioi_dfeg;
architecture beh of ioi_dfeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif rising_edge(clk) and (e = '0') then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iooe_dfeg is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic;
yout : out std_logic);
end iooe_dfeg;
architecture beh of iooe_dfeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
yout <= '0';
elsif pre = '0' then
q <= '1';
yout <= '1';
elsif rising_edge(clk) and (e = '0') then
q <= d;
yout <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity gnd is
port(
y : out std_logic);
end gnd;
architecture beh of gnd is
begin
y <= '0';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfm is
port(
clk : in std_logic;
s : in std_logic;
a : in std_logic;
b : in std_logic;
q : out std_logic);
end dfm;
architecture beh of dfm is
begin
ff : process (clk)
begin
if rising_edge(clk) then
if s = '0' then q <= a;
else q <= b; end if;
end if;
end process ff;
end beh;
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity hclkbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end hclkbuf;
--architecture beh of hclkbuf is
--begin
-- y <= pad;
--end beh;
--
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity inbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end inbuf;
--architecture beh of inbuf is
--begin
-- y <= pad;
--end beh;
library ieee;
use ieee.std_logic_1164.all;
entity inv is
port(
a : in std_logic;
y : out std_logic);
end inv;
architecture beh of inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity nand2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end nand2;
architecture beh of nand2 is
signal yx : std_logic;
begin
yx <= b and a;
y <= not yx;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity nand4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end nand4;
architecture beh of nand4 is
signal yx : std_logic;
begin
yx <= d and c and b and a;
y <= not yx;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2;
architecture beh of or2 is
begin
y <= b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2a;
architecture beh of or2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2b;
architecture beh of or2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3;
architecture beh of or3 is
begin
y <= c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3a;
architecture beh of or3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3b;
architecture beh of or3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3c;
architecture beh of or3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4;
architecture beh of or4 is
begin
y <= d or c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4a;
architecture beh of or4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d or c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4b;
architecture beh of or4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d or c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4c;
architecture beh of or4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4d is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4d;
architecture beh of or4d is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
signal di : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
di <= not d;
y <= di or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity sub1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end sub1;
architecture beh of sub1 is
signal un1_b : std_logic;
signal un3_fco : std_logic;
signal un1_fco : std_logic;
signal un4_fco : std_logic;
begin
un1_b <= not b;
un3_fco <= a and fci;
s <= a xor fci xor un1_b;
un1_fco <= a and un1_b;
un4_fco <= fci and un1_b;
fco <= un1_fco or un3_fco or un4_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity vcc is
port(
y : out std_logic);
end vcc;
architecture beh of vcc is
begin
y <= '1';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xa1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xa1;
architecture beh of xa1 is
signal xab : std_logic;
begin
xab <= b xor a;
y <= c and xab;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xnor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xnor2;
architecture beh of xnor2 is
signal yi : std_logic;
begin
yi <= b xor a;
y <= not yi;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xor2;
architecture beh of xor2 is
begin
y <= b xor a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xor3;
architecture beh of xor3 is
begin
y <= (c xor b) xor a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor4 is
port(a,b,c,d : in std_logic;
y : out std_logic);
end xor4;
architecture beh of xor4 is
signal xab, xcd : std_logic;
begin
xab <= b xor a;
xcd <= c xor d;
y <= xab xor xcd;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor4_fci is
port(a,b,c,fci : in std_logic;
y : out std_logic);
end xor4_fci;
architecture beh of xor4_fci is
signal xab, xcd : std_logic;
begin
xab <= b xor a;
xcd <= c xor fci;
y <= xab xor xcd;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity mx2 is
port(
a : in std_logic;
s : in std_logic;
b : in std_logic;
y : out std_logic);
end mx2;
architecture beh of mx2 is
signal xab : std_logic;
begin
y <= b when s = '0' else a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity mx4 is
port(
d0 : in std_logic;
s0 : in std_logic;
d1 : in std_logic;
s1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
y : out std_logic);
end mx4;
architecture beh of mx4 is
begin
y <= d0 when (s1 = '0' and s0 = '0') else
d1 when (s1 = '0' and s0 = '1') else
d2 when (s1 = '1' and s0 = '0') else d3;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity bufd is
port(
a : in std_logic;
y : out std_logic);
end bufd;
architecture beh of bufd is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xai1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xai1;
architecture beh of xai1 is
begin
y <= not (c and not (a xor b));
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ax1c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end ;
architecture beh of ax1c is
begin
y <= (a and b) xor c;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ax1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end ax1;
architecture beh of ax1 is
begin
y <= (((not a) and b) xor c);
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cy2a is
port(
a1 : in std_logic;
b1 : in std_logic;
a0 : in std_logic;
b0 : in std_logic;
y : out std_logic);
end cy2a;
architecture beh of cy2a is
begin
y <= ((( a1 AND b1 ) OR (( a0 AND b0 ) AND a1 )) OR (( a0 AND b0 ) AND b1 ));
end beh;
-- pragma translate_on
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2776.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ALL is
end ALL;
ENTITY c13s09b00x00p99n01i02776ent IS
END c13s09b00x00p99n01i02776ent;
ARCHITECTURE c13s09b00x00p99n01i02776arch OF c13s09b00x00p99n01i02776ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02776 - Reserved word ALL can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02776arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2776.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ALL is
end ALL;
ENTITY c13s09b00x00p99n01i02776ent IS
END c13s09b00x00p99n01i02776ent;
ARCHITECTURE c13s09b00x00p99n01i02776arch OF c13s09b00x00p99n01i02776ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02776 - Reserved word ALL can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02776arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2776.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ALL is
end ALL;
ENTITY c13s09b00x00p99n01i02776ent IS
END c13s09b00x00p99n01i02776ent;
ARCHITECTURE c13s09b00x00p99n01i02776arch OF c13s09b00x00p99n01i02776ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02776 - Reserved word ALL can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02776arch;
|
-------------------------------------------------------------------------------
--
-- The Data Memory control unit.
-- All accesses to the Data Memory are managed here.
--
-- $Id: dmem_ctrl.vhd,v 1.5 2006-06-20 01:07:16 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.dmem_addr_t;
use work.t48_pack.word_t;
use work.t48_dmem_ctrl_pack.dmem_addr_ident_t;
entity t48_dmem_ctrl is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- Control Interface ------------------------------------------------------
data_i : in word_t;
write_dmem_addr_i : in boolean;
write_dmem_i : in boolean;
read_dmem_i : in boolean;
addr_type_i : in dmem_addr_ident_t;
bank_select_i : in std_logic;
data_o : out word_t;
-- Data Memory Interface --------------------------------------------------
dmem_data_i : in word_t;
dmem_addr_o : out dmem_addr_t;
dmem_we_o : out std_logic;
dmem_data_o : out word_t
);
end t48_dmem_ctrl;
library ieee;
use ieee.numeric_std.all;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.to_stdLogic;
use work.t48_dmem_ctrl_pack.all;
architecture rtl of t48_dmem_ctrl is
signal dmem_addr_s,
dmem_addr_q : dmem_addr_t;
begin
-----------------------------------------------------------------------------
-- Process addr_decode
--
-- Purpose:
-- Decode/multiplex the address information for the Data Memory.
--
addr_decode: process (data_i,
addr_type_i,
bank_select_i,
dmem_addr_q)
variable stack_addr_v : unsigned(5 downto 0);
begin
-- default assignment
dmem_addr_s <= dmem_addr_q;
stack_addr_v := (others => '0');
case addr_type_i is
when DM_PLAIN =>
dmem_addr_s <= data_i;
when DM_REG =>
dmem_addr_s <= (others => '0');
dmem_addr_s(2 downto 0) <= data_i(2 downto 0);
-- implement bank switching
if bank_select_i = '1' then
-- dmem address 24 - 31: access proper set
dmem_addr_s(4 downto 3) <= "11";
end if;
when DM_STACK =>
-- build address from stack pointer
stack_addr_v(3 downto 1) := unsigned(data_i(2 downto 0));
-- dmem address 8 - 23
stack_addr_v := stack_addr_v + 8;
dmem_addr_s <= (others => '0');
dmem_addr_s(5 downto 0) <= std_logic_vector(stack_addr_v);
when DM_STACK_HIGH =>
dmem_addr_s(0) <= '1';
when others =>
-- do nothing
-- pragma translate_off
assert false
report "Unknown address type identification for Data Memory controller!"
severity error;
-- pragma translate_on
end case;
end process addr_decode;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process dmem_addr_reg
--
-- Purpose:
-- Implements the Data Memory Address Register.
-- This register is required to hold the address during a write operation
-- as we cannot hold the address in the input register of the
-- synchronous RAM (no clock suppression/gating).
--
-- NOTE: May be obsoleted by clock enable feature of generic RTL RAM.
--
dmem_addr_reg: process (res_i, clk_i)
begin
if res_i = res_active_c then
dmem_addr_q <= (others => '0');
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if write_dmem_addr_i then
dmem_addr_q <= dmem_addr_s;
end if;
end if;
end if;
end process dmem_addr_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping.
-----------------------------------------------------------------------------
dmem_addr_o <= dmem_addr_s
when write_dmem_addr_i and en_clk_i else
dmem_addr_q;
-- data from bus is fed through
dmem_data_o <= data_i;
-- data to bus is enabled upon read request
data_o <= dmem_data_i
when read_dmem_i else
(others => bus_idle_level_c);
-- write enable to Data Memory is fed through
dmem_we_o <= to_stdLogic(write_dmem_i);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2005/06/11 10:08:43 arniml
-- introduce prefix 't48_' for all packages, entities and configurations
--
-- Revision 1.3 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.2 2004/04/18 18:58:29 arniml
-- clean up sensitivity list
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
entity GPIO is
port(
CLK : std_logic;
RST : std_logic;
DATA_IN : out std_logic_vector(31 downto 0);
DATA_IN_STB : out std_logic;
DATA_IN_ACK : in std_logic;
DATA_OUT : in std_logic_vector(31 downto 0);
DATA_OUT_STB : in std_logic;
DATA_OUT_ACK : out std_logic;
DATA_EN : in std_logic_vector(31 downto 0);
DATA_EN_STB : in std_logic;
DATA_EN_ACK : out std_logic;
DATA : inout std_logic_vector(31 downto 0)
);
end entity GPIO;
architecture RTL of GPIO is
signal S_DATA_IN : std_logic_vector(31 downto 0);
signal S_DATA_OUT : std_logic_vector(31 downto 0);
signal S_DATA_EN : std_logic_vector(31 downto 0);
signal DATA_DEL : std_logic_vector(31 downto 0);
signal DATA_DEL_DEL : std_logic_vector(31 downto 0);
begin
process
begin
wait until rising_edge(CLK);
DATA_IN <= DATA_DEL_DEL;
DATA_DEL_DEL <= DATA_DEL;
DATA_DEL <= DATA;
if DATA_EN_STB = '1' then
S_DATA_EN <= DATA_EN;
end if;
if DATA_OUT_STB = '1' then
S_DATA_OUT <= DATA_OUT;
end if;
if RST = '1' then
S_DATA_OUT <= (others => '0');
S_DATA_EN <= (others => '0');
end if;
end process;
GENERATE_TRISTATES : for I in 0 to 31 generate
DATA(I) <= S_DATA_OUT(I) when S_DATA_EN(I) = '1' else 'Z';
end generate;
DATA_IN_STB <= '1';
DATA_OUT_ACK <= '1';
DATA_EN_ACK <= '1';
end architecture RTL;
|
-----------------------------------------------------------------------
-- Test Bench for counter (ESD figure 2.6)
-- by Weijun Zhang, 04/2001
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity counter_TB is -- entity declaration
end counter_TB;
-----------------------------------------------------------------------
architecture TB of counter_TB is
component counter
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(1 downto 0)
);
end component;
signal T_clock: std_logic;
signal T_clear: std_logic;
signal T_count: std_logic;
signal T_Q: std_logic_vector(1 downto 0);
begin
U_counter: counter port map (T_clock, T_clear, T_count, T_Q);
process
begin
T_clock <= '0'; -- clock cycle is 10 ns
wait for 5 ns;
T_clock <= '1';
wait for 5 ns;
end process;
process
variable err_cnt: integer :=0;
begin
T_clear <= '1'; -- start counting
T_count <= '1';
wait for 20 ns;
T_clear <= '0'; -- clear output
-- test case 1
wait for 10 ns;
assert (T_Q=1) report "Failed case 1" severity error;
if (T_Q/=1) then
err_cnt := err_cnt+1;
end if;
-- test case 2
wait for 10 ns;
assert (T_Q=2) report "Failed case 2" severity error;
if (T_Q/=2) then
err_cnt := err_cnt+1;
end if;
-- test case 3
wait for 10 ns;
assert (T_Q=3) report "Failed case 3" severity error;
if (T_Q/=3) then
err_cnt := err_cnt+1;
end if;
-- test case 4
wait for 10 ns;
assert (T_Q=0) report "Failed case 4" severity error;
if (T_Q/=0) then
err_cnt := err_cnt+1;
end if;
-- test case 5
wait for 20 ns;
T_clear <= '1';
wait for 10 ns;
assert (T_Q=0) report "Failed case 5" severity error;
if (T_Q/=0) then
err_cnt := err_cnt+1;
end if;
-- summary of all the tests
if (err_cnt=0) then
assert false
report "Testbench of Adder completed successfully!"
severity note;
else
assert true
report "Something wrong, try again"
severity error;
end if;
wait;
end process;
end TB;
----------------------------------------------------------------
configuration CFG_TB of counter_TB is
for TB
end for;
end CFG_TB;
---------------------------------------------------------------- |
-----------------------------------------------------------------------
-- Test Bench for counter (ESD figure 2.6)
-- by Weijun Zhang, 04/2001
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity counter_TB is -- entity declaration
end counter_TB;
-----------------------------------------------------------------------
architecture TB of counter_TB is
component counter
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(1 downto 0)
);
end component;
signal T_clock: std_logic;
signal T_clear: std_logic;
signal T_count: std_logic;
signal T_Q: std_logic_vector(1 downto 0);
begin
U_counter: counter port map (T_clock, T_clear, T_count, T_Q);
process
begin
T_clock <= '0'; -- clock cycle is 10 ns
wait for 5 ns;
T_clock <= '1';
wait for 5 ns;
end process;
process
variable err_cnt: integer :=0;
begin
T_clear <= '1'; -- start counting
T_count <= '1';
wait for 20 ns;
T_clear <= '0'; -- clear output
-- test case 1
wait for 10 ns;
assert (T_Q=1) report "Failed case 1" severity error;
if (T_Q/=1) then
err_cnt := err_cnt+1;
end if;
-- test case 2
wait for 10 ns;
assert (T_Q=2) report "Failed case 2" severity error;
if (T_Q/=2) then
err_cnt := err_cnt+1;
end if;
-- test case 3
wait for 10 ns;
assert (T_Q=3) report "Failed case 3" severity error;
if (T_Q/=3) then
err_cnt := err_cnt+1;
end if;
-- test case 4
wait for 10 ns;
assert (T_Q=0) report "Failed case 4" severity error;
if (T_Q/=0) then
err_cnt := err_cnt+1;
end if;
-- test case 5
wait for 20 ns;
T_clear <= '1';
wait for 10 ns;
assert (T_Q=0) report "Failed case 5" severity error;
if (T_Q/=0) then
err_cnt := err_cnt+1;
end if;
-- summary of all the tests
if (err_cnt=0) then
assert false
report "Testbench of Adder completed successfully!"
severity note;
else
assert true
report "Something wrong, try again"
severity error;
end if;
wait;
end process;
end TB;
----------------------------------------------------------------
configuration CFG_TB of counter_TB is
for TB
end for;
end CFG_TB;
---------------------------------------------------------------- |
-----------------------------------------------------------------------
-- Test Bench for counter (ESD figure 2.6)
-- by Weijun Zhang, 04/2001
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity counter_TB is -- entity declaration
end counter_TB;
-----------------------------------------------------------------------
architecture TB of counter_TB is
component counter
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(1 downto 0)
);
end component;
signal T_clock: std_logic;
signal T_clear: std_logic;
signal T_count: std_logic;
signal T_Q: std_logic_vector(1 downto 0);
begin
U_counter: counter port map (T_clock, T_clear, T_count, T_Q);
process
begin
T_clock <= '0'; -- clock cycle is 10 ns
wait for 5 ns;
T_clock <= '1';
wait for 5 ns;
end process;
process
variable err_cnt: integer :=0;
begin
T_clear <= '1'; -- start counting
T_count <= '1';
wait for 20 ns;
T_clear <= '0'; -- clear output
-- test case 1
wait for 10 ns;
assert (T_Q=1) report "Failed case 1" severity error;
if (T_Q/=1) then
err_cnt := err_cnt+1;
end if;
-- test case 2
wait for 10 ns;
assert (T_Q=2) report "Failed case 2" severity error;
if (T_Q/=2) then
err_cnt := err_cnt+1;
end if;
-- test case 3
wait for 10 ns;
assert (T_Q=3) report "Failed case 3" severity error;
if (T_Q/=3) then
err_cnt := err_cnt+1;
end if;
-- test case 4
wait for 10 ns;
assert (T_Q=0) report "Failed case 4" severity error;
if (T_Q/=0) then
err_cnt := err_cnt+1;
end if;
-- test case 5
wait for 20 ns;
T_clear <= '1';
wait for 10 ns;
assert (T_Q=0) report "Failed case 5" severity error;
if (T_Q/=0) then
err_cnt := err_cnt+1;
end if;
-- summary of all the tests
if (err_cnt=0) then
assert false
report "Testbench of Adder completed successfully!"
severity note;
else
assert true
report "Something wrong, try again"
severity error;
end if;
wait;
end process;
end TB;
----------------------------------------------------------------
configuration CFG_TB of counter_TB is
for TB
end for;
end CFG_TB;
---------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- intc_core - entity / architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: intc_core.vhd
-- Version: v2.01a
-- Description: Interrupt controller without a bus interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- xps_intc.vhd (wrapper for top level)
-- -- plbv46_slave_single
-- -plb_slave_attachment
-- -plb_address_decoder
-- -- intc_core
--
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 2/23/2007 First version
-- ^^^^^^^
-- Version intc_core v1.00a functionality is based on intc_core v1.00d wherein
-- the design is completed recoded for better readiabilty, save resources,
-- increase frequecny and remove the structural code.
-- ~~~~~~~
-- NSK 6/07/2007
-- ^^^^^^^
-- Correct the logic for generation of ivr_data_in. This is now depend on isr
-- and ier. Removed irq_gen dependency on this signal.
-- The problem reported by Rick - When interrupt(2) and interrupt(3) are active
-- but only interrupt(3) is enabled. IVR reads 0x2 instead of 0x3.
-- ~~~~~~~
-- NSK 7/31/2007
-- ^^^^^^^
-- 1. Valid_rd and Valid_wr changed to 7-bit vector length.
-- 2. Deleted process decoding Reg_add to register_en. Removed signal
-- register_en.
-- 3. Added signal read and used for generation of rd_data_int.
-- 4. Deleted the output ports Wr_ack & Rd_ack. Also the logic to generate
-- these signals.
-- ~~~~~~~
-- NSK 8/10/2007
-- ^^^^^^^
-- Updated to fix CR #445886 (by Rick). IVR need to be 32-bit to work with the
-- existing SW. Note that the reason of changing 32-bit register to width
-- equal to C_NUM_INTR is to save resources (Flip Flops).
-- 1. Signals mer, ipr & ivr is changed to width equal to C_DWIDTH from
-- REG_WIDTH.
-- 2. Added signals ier_out & isr_out of width equal to C_DWIDTH.
-- 3. Replaced the two generate statement MER_EQ_GEN & MER_NOT_EQ_GEN with
-- the direct assignment as mer is of width equal to C_DWIDTH.
-- 4. Added two generate blocks for signals ier_out & isr_out
-- REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR (C_NUM_INTR_INPUTS /= C_DWIDTH) &
-- REG_OUT_GEN_DWIDTH_EQ_NUM_INTR (C_NUM_INTR_INPUTS = C_DWIDTH).
-- 5. In the process IPR_P generating ipr; isr & ier changed to isr_out &
-- ier_out respectively.
-- 6. In the generate block IVR_GEN signal ivr_data_in changed to width equal
-- to C_DWIDTH.
-- 7. In the process IVR_DATA_GEN_P variable ivr_in changed to width equal
-- to C_DWIDTH.
-- 8. Removed the two different generate statement (OUTPUT_DATA_ONE_INTR_GEN &
-- OUTPUT_DATA_MULTI_INTR_GEN) for generating rd_data_int.
-- 9. Rd_data is directly generate in process OUTPUT_DATA_GEN_P; not
-- not depending on rd_data_int.
-- 10. Removed the unused signal rd_data_int.
-- ~~~~~~~
-- NSK 9/13/2008 version v2.00.a
-- ^^^^^^^
-- NSK 9/13/2008
-- ^^^^^^^
-- 1. Rolled to revision v2.00.a.
-- 2. Changed the library proc_common from v2_00_a to v3_00_a.
-- 3. Fixed CR #442790 to support edge on Irq.
-- I. Added generic C_IRQ_IS_LEVEL
-- a. If set to 0 generates edge interrupt
-- b. If set to 1 generates level interrupt
-- II. Changed the definition of generic C_IRQ_ACTIVE
-- a. Defines the edge for output interrupt if C_IRQ_IS_LEVEL=0
-- -- "0" = FALLING EDGE
-- -- "1" = RISING EDGE
-- b. Defines the level for output interrupt if C_IRQ_IS_LEVEL=1
-- -- "0" = LOW LEVEL
-- -- "1" = HIGH LEVEL
-- III. Added generic C_IRQ_IS_LEVEL in generic map of instance INTC_CORE_I
-- for component "intc_core" from library "xps_intc_v2_00_a."
-- IV. Added "C_IRQ_IS_LEVEL" in Definition of Generics section in
-- comments.
-- V. Modified the logic for edge generation on Irq.
-- a. Variable "irq_int" in process "IRQ_GEN_P" is changed to
-- irq_gen_int.
-- b. Added to seperate generate statement for generating Irq
-- -- IRQ_LEVEL_GEN: if (C_IRQ_IS_LEVEL = 1)
-- -- IRQ_EDGE_GEN: if (C_IRQ_IS_LEVEL = 0)
-- ~~~~~~~
-- NSK 9/15/2008
-- ^^^^^^^
-- Removed unused parameter C_FAMILY.
-- ~~~~~~~
-- NSK 9/17/2008
-- ^^^^^^^
-- Update for linting: -
-- 1. Removed unused constant "REG_WIDTH" & function "get_reg_width".
-- 2. Process in generate block "RISING_EDGE_GEN" & "FALLING_EDGE_GEN" given
-- two different names "REG_INTR_RISE_P" & "REG_INTR_FALL_P" respectively.
-- 3. Corrected the same name conflict in the generate block "SIE_GEN" &
-- "CIE_GEN": -
-- a. Generate label in generate block "SIE_GEN" is chagned from "SIE_BIT"
-- to "SIE_BIT_GEN".
-- b. Generate label in generate block "CIE_GEN" is chagned from "SIE_BIT"
-- to "CIE_BIT_GEN".
-- ~~~~~~~
-- NSK 9/30/2008
-- ^^^^^^^
-- Type changed for the parameter C_DWIDTH & C_NUM_INTR_INPUTS from positive
-- to integer to have consistency with xps_intc.vhd.
-- ~~~~~~~
-- NSK 10/01/2008
-- ^^^^^^^
-- Updated the latest Copyright and removed XCS label.
-- ~~~~~~~
-- NSK 11/17/2008
-- ^^^^^^^
-- Update to fix IR #496531 - Irq toggles when C_IRQ_IS_LEVEL = 0
-- 1. Seperate generate blocks
-- a. ONE_INTR_IRQ_EDGE_GEN when C_IRQ_IS_LEVEL=0 & C_NUM_INTR_INPUTS=1.
-- b. MULTI_INTR_IRQ_EDGE_GEN when C_IRQ_IS_LEVEL=0 & C_NUM_INTR_INPUTS>1.
-- 2. Behavior of Irq is changed from pulse to a signal kind of level but goes
-- LOW when interrupt is ACKNOWLEDGED or DISABLED.
-- 3. For MULTI_INTR_IRQ_EDGE_GEN: -
-- a. Signal "active_intr" ANDing of ISE and IER detects active interrupts.
-- b. Signal "active_intr_d1" registers "active_intr".
-- c. Signal "deactive_intr_edge" detects the falling edge of "active_intr".
-- This means either the interrupt is acknowledge or disabled.
-- d. Signal "ack_disabled_detected" is ORed of "deactive_intr_edge". This
-- means any one of the active interrupt is acknowledge or disabled.
-- e. Signal "irq_int" goes to RESET when "ack_disabled_detected"=HIGH
--4. For ONE_INTR_IRQ_EDGE_GEN: -
-- Behavior is same as C_IRQ_IS_LEVEL=1 & C_NUM_INTR_INPUTS=1
-- ~~~~~~~
-- NSK 12/10/2008
-- ^^^^^^^
-- Update to fix IR #497895 - IRQ o/p for edge based interrupts does not
-- toggle to default value after a clock edge.
-- 1. Removed the logic added as above (Date - 11/17/2008) to fix IR #496531.
-- 2. Used generate block "ACK_OR_GEN" to generate the "ack_or" signal to
-- find if the current interrupt is acknowleged.
-- 3. Used state machine "GEN_CS_P" to generate "Irq".
-- ~~~~~~~--
-- NSK 12/11/2008
-- ^^^^^^^
-- Update for compile errors.
-- ~~~~~~~--
-- NSK 01/05/2009
-- ^^^^^^^
-- Update to fix IR #501183 - XPS INTC sometimes misses falling edge
-- interrupts, needs input synchronization
-- Below are the updates in generate block - INTR_DETECT_GEN/EDGE_DETECT_GEN
-- 1. Added signals
-- a. intr_sync - Assigned HIGH/LOW (depend on C_KIND_OF_EDGE) on event on
-- Intr (used as clock)
-- b. intr_p1 - register of intr_sync (Clk - used as clock)
-- c. intr_p2 - register of intr_p1 (Clk - used as clock)
-- 2. Assignment for intr_d1(i) is changed to intr_p2(i) (from Intr(i))
-- ~~~~~~~
-- NSK 01/07/2009
-- ^^^^^^^
-- Corrected:-
-- For intr_edge(i) assignment Intr(old) is changed to intr_p2(new).
-- ~~~~~~~
-- ~~~~~~~
-- BSB 01/31/2010
-- ^^^^^^^
-- New version v2.01.a created. attribute buffer type added on signal Intr
-- ~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
library proc_common_v3_00_a;
-------------------------------------------------------------------------
-- Package proc_common_pkg is used because it contains the RESET_ACTIVE
-- constant used to assign reset as active high status.
-------------------------------------------------------------------------
use proc_common_v3_00_a.proc_common_pkg.RESET_ACTIVE;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- -- Intc Parameters
-- C_DWIDTH -- Data bus width
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits
-- Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits
-- Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-------------------------------------------------------------------------------
-- Definition of Ports:
-- -- Clocks and reset
-- Clk -- Clock
-- Rst -- Reset
-- -- Intc Interface Signals
-- Intr -- Input Interruput request
-- Reg_addr -- Address bus
-- Valid_rd -- Read
-- Valid_wr -- Write
-- Wr_data -- Write data bus
-- Rd_data -- Read data bus
-- Irq -- Output Interruput request
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------
entity intc_core is
generic
(
C_DWIDTH : integer := 32;
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_KIND_OF_INTR : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1'
);
port
(
-- Inputs
Clk : in std_logic;
Rst : in std_logic;
Intr : in std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
Reg_addr : in std_logic_vector(2 downto 0);
Valid_rd : in std_logic_vector(0 to 7);
Valid_wr : in std_logic_vector(0 to 7);
Wr_data : in std_logic_vector(C_DWIDTH - 1 downto 0);
-- Outputs
Rd_data : out std_logic_vector(C_DWIDTH - 1 downto 0);
Irq : out std_logic
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
attribute buffer_type: string;
attribute buffer_type of Intr: signal is "none";
end intc_core;
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture imp of intc_core is
-- Signal declaration
-- ==================
signal wr_data_int : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal mer_int : std_logic_vector(1 downto 0);
signal mer : std_logic_vector(C_DWIDTH - 1 downto 0);
signal sie : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal cie : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal iar : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal ier : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr_en : std_logic;
signal hw_intr : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr_data_in : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal ipr : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ivr : std_logic_vector(C_DWIDTH - 1 downto 0);
signal irq_gen : std_logic;
signal read : std_logic;
signal ier_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal isr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ack_or : std_logic;
-- Begin of architecture
begin
read <= Valid_rd(0) or Valid_rd(1) or Valid_rd(2) or Valid_rd(6) or
Valid_rd(7);
--------------------------------------------------------------------------
-- GENERATING ALL REGISTERS
--------------------------------------------------------------------------
wr_data_int <= Wr_data(C_NUM_INTR_INPUTS - 1 downto 0);
--------------------------------------------------------------------------
-- Process MER_ME_P for MER ME bit generation
--------------------------------------------------------------------------
MER_ME_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
mer_int(0) <= '0';
elsif (Valid_wr(7) = '1') then
mer_int(0) <= Wr_data(0);
end if;
end if;
end process MER_ME_P;
--------------------------------------------------------------------------
-- Process MER_HIE_P for generating MER HIE bit
--------------------------------------------------------------------------
MER_HIE_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
mer_int(1) <= '0';
elsif ((Valid_wr(7) = '1') and (mer_int(1) = '0')) then
mer_int(1) <= Wr_data(1);
end if;
end if;
end process MER_HIE_P;
mer(1 downto 0) <= mer_int;
mer(C_DWIDTH - 1 downto 2) <= (others => '0');
----------------------------------------------------------------------
-- Generate SIE if (C_HAS_SIE = 1)
----------------------------------------------------------------------
SIE_GEN: if (C_HAS_SIE = 1) generate
SIE_BIT_GEN : for i in 0 to (C_NUM_INTR_INPUTS - 1) generate
--------------------------------------------------------------
-- Process SIE_P for generating SIE register
--------------------------------------------------------------
SIE_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (sie(i) = '1')) then
sie(i) <= '0';
elsif (Valid_wr(4) = '1') then
sie(i) <= wr_data_int(i);
end if;
end if;
end process SIE_P;
end generate SIE_BIT_GEN;
end generate SIE_GEN;
----------------------------------------------------------------------
-- Assign sie_out ALL ZEROS if (C_HAS_SIE = 0)
----------------------------------------------------------------------
SIE_NO_GEN: if (C_HAS_SIE = 0) generate
sie <= (others => '0');
end generate SIE_NO_GEN;
----------------------------------------------------------------------
-- Generate CIE if (C_HAS_CIE = 1)
----------------------------------------------------------------------
CIE_GEN: if (C_HAS_CIE = 1) generate
CIE_BIT_GEN : for i in 0 to (C_NUM_INTR_INPUTS - 1) generate
------------------------------------------------------------------
-- Process CIE_P for generating CIE register
------------------------------------------------------------------
CIE_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (cie(i) = '1')) then
cie(i) <= '0';
elsif (Valid_wr(5) = '1') then
cie(i) <= wr_data_int(i);
end if;
end if;
end process CIE_P;
end generate CIE_BIT_GEN;
end generate CIE_GEN;
----------------------------------------------------------------------
-- Assign cie_out ALL ZEROS if (C_HAS_CIE = 0)
----------------------------------------------------------------------
CIE_NO_GEN: if (C_HAS_CIE = 0) generate
cie <= (others => '0');
end generate CIE_NO_GEN;
-- Generating write enable & data input for ISR
isr_en <= mer(1) or Valid_wr(0);
isr_data_in <= hw_intr when mer(1) = '1' else
Wr_data(C_NUM_INTR_INPUTS - 1 downto 0);
--------------------------------------------------------------------------
-- Generate Registers of width equal C_NUM_INTR_INPUTS
--------------------------------------------------------------------------
REG_GEN : for i in 0 to (C_NUM_INTR_INPUTS - 1) generate
----------------------------------------------------------------------
-- Process IAR_BIT_P for generating IAR register
----------------------------------------------------------------------
IAR_BIT_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
iar(i) <= '0';
elsif (Valid_wr(3) = '1') then
iar(i) <= wr_data_int(i);
end if;
end if;
end process IAR_BIT_P;
----------------------------------------------------------------------
-- Process IER_BIT_P for generating IER register
----------------------------------------------------------------------
IER_BIT_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (cie(i) = '1')) then
ier(i) <= '0';
elsif (sie(i) = '1') then
ier(i) <= '1';
elsif (Valid_wr(2) = '1') then
ier(i) <= wr_data_int(i);
end if;
end if;
end process IER_BIT_P;
----------------------------------------------------------------------
-- Process ISR_P for generating ISR register
----------------------------------------------------------------------
ISR_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
isr(i) <= '0';
elsif (isr_en = '1') then
isr(i) <= isr_data_in(i);
end if;
end if;
end process ISR_P;
end generate REG_GEN;
-----------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR_INPUTS /= C_DWIDTH
-----------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR: if (C_NUM_INTR_INPUTS /= C_DWIDTH)
generate
ier_out(C_NUM_INTR_INPUTS - 1 downto 0) <= ier;
ier_out(C_DWIDTH - 1 downto C_NUM_INTR_INPUTS) <= (others => '0');
isr_out(C_NUM_INTR_INPUTS - 1 downto 0) <= isr;
isr_out(C_DWIDTH - 1 downto C_NUM_INTR_INPUTS) <= (others => '0');
end generate REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR;
------------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR_INPUTS = C_DWIDTH
------------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_EQ_NUM_INTR: if (C_NUM_INTR_INPUTS = C_DWIDTH)
generate
ier_out <= ier;
isr_out <= isr;
end generate REG_OUT_GEN_DWIDTH_EQ_NUM_INTR;
--------------------------------------------------------------------------
-- Generate IPR if (C_HAS_IPR = 1)
--------------------------------------------------------------------------
IPR_GEN: if (C_HAS_IPR = 1) generate
----------------------------------------------------------------------
-- Process IPR_P for generating IPR register
----------------------------------------------------------------------
IPR_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
ipr <= (others => '0');
else
ipr <= isr_out and ier_out;
end if;
end if;
end process IPR_P;
end generate IPR_GEN;
--------------------------------------------------------------------------
-- Assign IPR ALL ZEROS if (C_HAS_IPR = 0)
--------------------------------------------------------------------------
IPR_NO_GEN: if (C_HAS_IPR = 0) generate
ipr <= (others => '0');
end generate IPR_NO_GEN;
--------------------------------------------------------------------------
-- Generate IVR if (C_HAS_IVR = 1)
--------------------------------------------------------------------------
IVR_GEN: if (C_HAS_IVR = 1) generate
signal ivr_data_in : std_logic_vector(C_DWIDTH - 1 downto 0);
begin
----------------------------------------------------------------------
-- Process IVR_DATA_GEN_P for generating interrupt vector address
----------------------------------------------------------------------
IVR_DATA_GEN_P: process (isr, ier)
variable ivr_in : std_logic_vector(C_DWIDTH - 1 downto 0)
:= (others => '1');
begin
for i in 0 to (C_NUM_INTR_INPUTS - 1) loop
if ((isr(i) = '1') and (ier(i) = '1')) then
ivr_in := CONV_STD_LOGIC_VECTOR(i, C_DWIDTH);
exit;
else
ivr_in := (others => '1');
end if;
end loop;
ivr_data_in <= ivr_in;
end process IVR_DATA_GEN_P;
----------------------------------------------------------------------
-- Process IVR_P for generating IVR register
----------------------------------------------------------------------
IVR_P: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
ivr <= (others => '1');
else
ivr <= ivr_data_in;
end if;
end if;
end process IVR_P;
end generate IVR_GEN;
--------------------------------------------------------------------------
-- Assign IVR ALL ZEROS if (C_HAS_IVR = 0)
--------------------------------------------------------------------------
IVR_NO_GEN: if (C_HAS_IVR = 0) generate
ivr <= (others => '1');
end generate IVR_NO_GEN;
--------------------------------------------------------------------------
-- DETECTING HW INTERRUPT
--------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Detecting the interrupts
---------------------------------------------------------------------------
INTR_DETECT_GEN: for i in 0 to C_NUM_INTR_INPUTS - 1 generate
-----------------------------------------------------------------------
-- Generating the edge trigeered interrupts if C_KIND_OF_INTR(i) = 1
-----------------------------------------------------------------------
EDGE_DETECT_GEN: if (C_KIND_OF_INTR(i) = '1') generate
signal intr_d1 : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal intr_edge : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal intr_sync : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal intr_p1 : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal intr_p2 : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
begin
-------------------------------------------------------------------
-- Generating the rising edge interrupts if C_KIND_OF_EDGE(i) = 1
-------------------------------------------------------------------
RISING_EDGE_GEN: if (C_KIND_OF_EDGE(i) = '1') generate
---------------------------------------------------------------
-- Process SYNC_INTR_RISE_P to synchronize the interrupt signal
---------------------------------------------------------------
SYNC_INTR_RISE_P : process (Rst, Intr, iar) is
begin
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
intr_sync(i) <= '0';
elsif(Intr(i)'event and Intr(i)='1') then
intr_sync(i) <= '1';
end if;
end process SYNC_INTR_RISE_P;
---------------------------------------------------------------
-- Process REG_INTR_P to regiter the interrupt signal
---------------------------------------------------------------
REG_INTR_RISE_P : process (Clk) is
begin
if(Clk'event and Clk='1') then
if (Rst = RESET_ACTIVE) then
intr_p1(i) <= '0';
intr_p2(i) <= '0';
intr_d1(i) <= '1';
else
intr_p1(i) <= intr_sync(i);
intr_p2(i) <= intr_p1(i);
intr_d1(i) <= intr_p2(i);
end if;
end if;
end process REG_INTR_RISE_P;
-- Creating one-shot rising edge triggered interrupts
intr_edge(i) <= '1' when ( (intr_p2(i) = '1') and
(intr_d1(i) = '0') )
else '0';
end generate RISING_EDGE_GEN;
-------------------------------------------------------------------
-- Generating the falling edge interrupts if C_KIND_OF_EDGE(i) = 0
-------------------------------------------------------------------
FALLING_EDGE_GEN: if (C_KIND_OF_EDGE(i) = '0') generate
---------------------------------------------------------------
-- Process SYNC_INTR_FALL_P to synchronize the interrupt signal
---------------------------------------------------------------
SYNC_INTR_FALL_P : process (Rst, Intr, iar) is
begin
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
intr_sync(i) <= '1';
elsif(Intr(i)'event and Intr(i)='0') then
intr_sync(i) <= '0';
end if;
end process SYNC_INTR_FALL_P;
---------------------------------------------------------------
-- Process REG_INTR_P to regiter the interrupt signal
---------------------------------------------------------------
REG_INTR_FALL_P : process (Clk) is
begin
if(Clk'event and Clk='1') then
if (Rst = RESET_ACTIVE) then
intr_p1(i) <= '1';
intr_p2(i) <= '1';
intr_d1(i) <= '0';
else
intr_p1(i) <= intr_sync(i);
intr_p2(i) <= intr_p1(i);
intr_d1(i) <= intr_p2(i);
end if;
end if;
end process REG_INTR_FALL_P;
-- Creating one-shot falling edge triggered interrupts
intr_edge(i) <= '1' when ( (intr_p2(i) = '0') and
(intr_d1(i) = '1') )
else '0';
end generate FALLING_EDGE_GEN;
------------------------------------------------------------------
-- Process DETECT_INTR_P to generate the edge trigeered interrupts
------------------------------------------------------------------
DETECT_INTR_P : process (Clk) is
begin
if(Clk'event and Clk='1') then
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
hw_intr(i) <= '0';
elsif (intr_edge(i) = '1') then
hw_intr(i) <= '1';
end if;
end if;
end process DETECT_INTR_P;
end generate EDGE_DETECT_GEN;
----------------------------------------------------------------------
-- Generating the Level trigeered interrupts if C_KIND_OF_INTR(i) = 0
----------------------------------------------------------------------
LVL_DETECT_GEN: if (C_KIND_OF_INTR(i) = '0') generate
------------------------------------------------------------------
-- Generating the active high interrupts if C_KIND_OF_LVL(i) = 1
------------------------------------------------------------------
ACTIVE_HIGH_GEN: if (C_KIND_OF_LVL(i) = '1') generate
--------------------------------------------------------------
-- Process ACTIVE_HIGH_LVL_P to generate hw_intr (active high)
--------------------------------------------------------------
ACTIVE_HIGH_LVL_P : process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
hw_intr(i) <= '0';
elsif(Intr(i) = '1') then
hw_intr(i) <= '1';
end if;
end if;
end process ACTIVE_HIGH_LVL_P;
end generate ACTIVE_HIGH_GEN;
------------------------------------------------------------------
-- Generating the active low interrupts if C_KIND_OF_LVL(i) = 0
------------------------------------------------------------------
ACTIVE_LOW_GEN: if (C_KIND_OF_LVL(i) = '0') generate
--------------------------------------------------------------
-- Process ACTIVE_LOW_LVL_P to generate hw_intr (active low)
--------------------------------------------------------------
ACTIVE_LOW_LVL_P : process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (iar(i) = '1')) then
hw_intr(i) <= '0';
elsif(Intr(i) = '0') then
hw_intr(i) <= '1';
end if;
end if;
end process ACTIVE_LOW_LVL_P;
end generate ACTIVE_LOW_GEN;
end generate LVL_DETECT_GEN;
-----------------------------------------------------------------------
-- Generating All Interrupr Zero if C_KIND_OF_INTR(i) /= 1 or 0
-----------------------------------------------------------------------
NO_DETECT_GEN: if ( (C_KIND_OF_INTR(i) /= '1') and
(C_KIND_OF_INTR(i) /= '0') )
generate
hw_intr(i) <= '0';
end generate NO_DETECT_GEN;
end generate INTR_DETECT_GEN;
--------------------------------------------------------------------------
-- Checking Active Interrupt/Interrupts
--------------------------------------------------------------------------
IRQ_ONE_INTR_GEN: if (C_NUM_INTR_INPUTS = 1) generate
irq_gen <= isr(0) and ier(0);
end generate IRQ_ONE_INTR_GEN;
IRQ_MULTI_INTR_GEN: if (C_NUM_INTR_INPUTS > 1) generate
--------------------------------------------------------------
-- Process IRQ_GEN_P to generate irq_gen
--------------------------------------------------------------
IRQ_GEN_P: process (isr, ier)
variable irq_gen_int : std_logic := '0';
begin
irq_gen_int := isr(0) and ier(0);
for i in 1 to (isr'length - 1) loop
irq_gen_int := irq_gen_int or (isr(i) and ier(i));
end loop;
irq_gen <= irq_gen_int;
end process IRQ_GEN_P;
end generate IRQ_MULTI_INTR_GEN;
--------------------------------------------------------------------------
-- Generating LEVEL interrupt if C_IRQ_IS_LEVEL = 1
--------------------------------------------------------------------------
IRQ_LEVEL_GEN: if (C_IRQ_IS_LEVEL = 1) generate
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
IRQ_LEVEL_P: process (Clk) is
begin
if(Clk'event and Clk = '1') then
if ((Rst = RESET_ACTIVE) or (irq_gen = '0')) then
Irq <= not C_IRQ_ACTIVE;
elsif ((irq_gen = '1') and (mer(0) = '1')) then
Irq <= C_IRQ_ACTIVE;
end if;
end if;
end process IRQ_LEVEL_P;
end generate IRQ_LEVEL_GEN;
--------------------------------------------------------------------------
-- Generating ack_or for edge output interrupt (if C_IRQ_IS_LEVEL = 0)
--------------------------------------------------------------------------
ACK_OR_GEN: if (C_IRQ_IS_LEVEL = 0) generate
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR_INPUTS = 1
----------------------------------------------------------------------
ACK_OR_ONE_INTR_GEN: if (C_NUM_INTR_INPUTS = 1) generate
ack_or <= iar(0);
end generate ACK_OR_ONE_INTR_GEN;
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR_INPUTS > 1
----------------------------------------------------------------------
ACK_OR_MULTI_INTR_GEN: if (C_NUM_INTR_INPUTS > 1) generate
--------------------------------------------------------------
-- Process ACK_OR_GEN_P to generate ack_or (ORed Acks)
--------------------------------------------------------------
ACK_OR_GEN_P: process (iar)
variable ack_or_int : std_logic := '0';
begin
ack_or_int := iar(0);
for i in 1 to (iar'length - 1) loop
ack_or_int := ack_or_int or (iar(i));
end loop;
ack_or <= ack_or_int;
end process ACK_OR_GEN_P;
end generate ACK_OR_MULTI_INTR_GEN;
end generate ACK_OR_GEN;
--------------------------------------------------------------------------
-- Generating EDGE interrupt if C_IRQ_IS_LEVEL = 0
--------------------------------------------------------------------------
IRQ_EDGE_GEN: if (C_IRQ_IS_LEVEL = 0) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
signal irq_int : std_logic;
begin
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst = '1') then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((irq_gen='1') and (mer(0)='1')) then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE => current_state <= WAIT_ACK;
when WAIT_ACK => if (ack_or = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
end case;
end if;
end if;
end process GEN_CS_P;
Irq <= C_IRQ_ACTIVE when (current_state = GEN_PULSE) else
(not C_IRQ_ACTIVE);
end generate IRQ_EDGE_GEN;
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read, Reg_addr, isr_out, ipr, ier_out, ivr,
mer) is
begin
if (read = '1') then
case Reg_addr is
when "000" => Rd_data <= isr_out; -- ISR (R/W)
when "001" => Rd_data <= ipr; -- IPR (Read only)
when "010" => Rd_data <= ier_out; -- IER (R/W)
when "110" => Rd_data <= ivr; -- IVR (Read only)
when "111" => Rd_data <= mer; -- MER (R/W)
-- IAR, SIE, CIE (Write only)
when others => Rd_data <= (others => '0');
end case;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end imp;
|
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic(
WIDTH : natural := 8; -- number of bits in each FIFO word
DEPTH : natural := 4 -- 2**DEPTH gives number of words in FIFO
);
port(
clk_in : in std_logic;
reset_in : in std_logic;
depth_out : out std_logic_vector(DEPTH downto 0);
inputData_in : in std_logic_vector(WIDTH-1 downto 0);
inputValid_in : in std_logic;
inputReady_out : out std_logic;
outputData_out : out std_logic_vector(WIDTH-1 downto 0);
outputValid_out : out std_logic;
outputReady_in : in std_logic
);
end entity;
|
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"),
(name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array := (
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array := (
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array := (
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"); -- Comment
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent2 is
end entity;
architecture a of ent2 is
procedure proc(constant value : std_logic_vector) is
constant l : natural := maximum (value'length, value'length);
begin
end procedure;
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent2 is
end entity;
architecture a of ent2 is
procedure proc(constant value : std_logic_vector) is
constant l : natural := maximum (value'length, value'length);
begin
end procedure;
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent2 is
end entity;
architecture a of ent2 is
procedure proc(constant value : std_logic_vector) is
constant l : natural := maximum (value'length, value'length);
begin
end procedure;
begin
end architecture;
|
--------------------------------------------------------------------------------
-- Scheduler for running 5 concurrent SHA1 calcs and outputting sequentially
-- Copyright (C) 2016 Jarrett Rainier
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.sha1_pkg.all;
entity sha1_scheduler is
port(
clk_i : in std_ulogic;
load_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
sot_in : in std_ulogic;
dat_o : out std_ulogic_vector(0 to 31)
);
end sha1_scheduler;
architecture RTL of sha1_scheduler is
component sha1_load
port (
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in std_ulogic_vector(0 to 31);
sot_in : in std_ulogic;
dat_w_o : out w_input
);
end component;
component sha1_process_input
port (
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_input;
load_i : in std_ulogic;
dat_w_o : out w_full;
valid_o : out std_ulogic
);
end component;
component sha1_process_buffer
port (
clk_i : in std_ulogic;
rst_i : in std_ulogic;
dat_i : in w_full;
load_i : in std_ulogic;
new_i : in std_ulogic;
dat_w_i : in w_output;
dat_w_o : out w_output;
valid_o : out std_ulogic
);
end component;
signal w_load: w_input;
signal w_processed_input1: w_full;
signal w_processed_input2: w_full;
signal w_processed_input3: w_full;
signal w_processed_input4: w_full;
signal w_processed_input5: w_full;
signal w_processed_new: std_ulogic;
signal w_processed_buffer: w_output;
signal w_processed_buffer1: w_output;
signal w_processed_buffer2: w_output;
signal w_processed_buffer3: w_output;
signal w_processed_buffer4: w_output;
signal w_processed_buffer5: w_output;
signal w_buffer_valid1: std_ulogic;
signal w_buffer_valid2: std_ulogic;
signal w_buffer_valid3: std_ulogic;
signal w_buffer_valid4: std_ulogic;
signal w_buffer_valid5: std_ulogic;
signal w_pinput: w_input;
signal latch_pinput: std_ulogic_vector(0 to 4);
signal w_processed_valid: std_ulogic_vector(0 to 4);
signal i : integer range 0 to 16;
signal i_mux : integer range 0 to 4;
-- synthesis translate_off
signal test_sha1_process_input_o : std_ulogic_vector(0 to 31);
signal test_sha1_process_buffer0_o : std_ulogic_vector(0 to 31);
signal test_sha1_process_buffer_o : std_ulogic_vector(0 to 31);
signal test_sha1_load_o : std_ulogic_vector(0 to 31);
-- synthesis translate_on
begin
LOAD1: sha1_load port map (clk_i,rst_i,dat_i,sot_in,w_load);
--Alt: Use a generate statement
PINPUT1: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(0),w_processed_input1,w_processed_valid(0));
PBUFFER1: sha1_process_buffer port map (clk_i,rst_i,w_processed_input1,w_processed_valid(0),w_processed_valid(0),w_processed_buffer1,w_processed_buffer1,w_buffer_valid1);
PINPUT2: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(1),w_processed_input2,w_processed_valid(1));
PBUFFER2: sha1_process_buffer port map (clk_i,rst_i,w_processed_input2,w_processed_valid(1),w_processed_valid(1),w_processed_buffer2,w_processed_buffer2,w_buffer_valid2);
PINPUT3: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(2),w_processed_input3,w_processed_valid(2));
PBUFFER3: sha1_process_buffer port map (clk_i,rst_i,w_processed_input3,w_processed_valid(2),w_processed_valid(2),w_processed_buffer3,w_processed_buffer3,w_buffer_valid3);
PINPUT4: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(3),w_processed_input4,w_processed_valid(3));
PBUFFER4: sha1_process_buffer port map (clk_i,rst_i,w_processed_input4,w_processed_valid(3),w_processed_valid(3),w_processed_buffer4,w_processed_buffer4,w_buffer_valid4);
PINPUT5: sha1_process_input port map (clk_i,rst_i,w_pinput,latch_pinput(4),w_processed_input5,w_processed_valid(4));
PBUFFER5: sha1_process_buffer port map (clk_i,rst_i,w_processed_input5,w_processed_valid(4),w_processed_valid(4),w_processed_buffer5,w_processed_buffer5,w_buffer_valid5);
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if rst_i = '1' then
latch_pinput <= "00000";
i <= 0;
--Todo: start from 0 after testing
i_mux <= 0;
for x in 0 to 15 loop
w_pinput(x) <= "00000000000000000000000000000000";
end loop;
else
if i = 15 then
case i_mux is
when 0 => latch_pinput <= "10000";
when 1 => latch_pinput <= "01000";
when 2 => latch_pinput <= "00100";
when 3 => latch_pinput <= "00010";
when 4 => latch_pinput <= "00001";
end case;
w_pinput <= w_load;
i <= 0;
--i <= i + 1;
if i_mux = 4 then
i_mux <= 0;
else
i_mux <= i_mux + 1;
end if;
else
latch_pinput <= "00000";
i <= i + 1;
end if;
end if;
--Alt: Consider other conditionals
if w_processed_valid(0) = '1' then
w_processed_buffer <= w_processed_buffer1;
elsif w_processed_valid(1) = '1' then
w_processed_buffer <= w_processed_buffer2;
elsif w_processed_valid(2) = '1' then
w_processed_buffer <= w_processed_buffer3;
elsif w_processed_valid(3) = '1' then
w_processed_buffer <= w_processed_buffer4;
elsif w_processed_valid(4) = '1' then
w_processed_buffer <= w_processed_buffer5;
end if;
end if;
end process;
dat_1_o <= w_pinput(15);
-- synthesis translate_off
test_sha1_process_input_o <= w_processed_input1(16);
test_sha1_process_buffer0_o <= w_processed_buffer1(0);
test_sha1_process_buffer_o <= w_processed_buffer(0);
test_sha1_load_o <= w_load(15);
-- synthesis translate_on
end RTL; |
--This should pass
context c1 is
end context c1;
--This should fail
context c1 is
end context c1;
context c1 is
end context c1;
context c1 is
end context c1;
-- Split declaration across lines
context
c1
is
end
context
c1
;
|
--------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 09:22:39 09/15/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/Levi/Exam_SN74Ls42/SN74Ls42_TB.vhd
-- Project Name: Exam_SN74Ls42
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SN74Ls42
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SN74Ls42_TB IS
END SN74Ls42_TB;
ARCHITECTURE behavior OF SN74Ls42_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SN74Ls42
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
output : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
--Outputs
signal output : std_logic_vector(9 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SN74Ls42 PORT MAP (
A => A,
B => B,
C => C,
D => D,
output => output
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
--
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- wait for <clock>_period*10;
-- insert stimulus here
D <= '0'; C <= '0'; B <= '0'; A <= '0';
wait for 100 ns;
D <= '0'; C <= '0'; B <= '0'; A <= '1';
wait for 100 ns;
D <= '0'; C <= '0'; B <= '1'; A <= '0';
wait for 100 ns;
D <= '0'; C <= '0'; B <= '1'; A <= '1';
wait for 100 ns;
D <= '0'; C <= '1'; B <= '0'; A <= '0';
wait for 100 ns;
D <= '0'; C <= '1'; B <= '0'; A <= '1';
wait for 100 ns;
D <= '0'; C <= '1'; B <= '1'; A <= '0';
wait for 100 ns;
D <= '0'; C <= '1'; B <= '1'; A <= '1';
wait for 100 ns;
D <= '1'; C <= '0'; B <= '0'; A <= '0';
wait for 100 ns;
D <= '1'; C <= '0'; B <= '0'; A <= '1';
wait for 100 ns;
D <= '1'; C <= '0'; B <= '1'; A <= '0';
wait for 100 ns;
D <= '1'; C <= '0'; B <= '1'; A <= '1';
wait for 100 ns;
D <= '1'; C <= '1'; B <= '0'; A <= '0';
wait for 100 ns;
D <= '1'; C <= '1'; B <= '0'; A <= '1';
wait for 100 ns;
D <= '1'; C <= '1'; B <= '1'; A <= '0';
wait for 100 ns;
D <= '1'; C <= '1'; B <= '1'; A <= '1';
wait for 100 ns;
wait;
end process;
END;
|
-- $Id: $
-- File name: tb_computerInterceptor.vhd
-- Created: 4/19/2012
-- Author: John Wyant
-- Lab Section: 337-02
-- Version: 1.0 Initial Test Bench
library ieee;
--library gold_lib; --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use gold_lib.all; --UNCOMMENT if you're using a GOLD model
entity tb_computerInterceptor is
generic (Period : Time := 70 ns);
end tb_computerInterceptor;
architecture TEST of tb_computerInterceptor is
function UINT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
return STD_LOGIC_VECTOR is
begin
return std_logic_vector(to_unsigned(X, NumBits));
end;
function STD_LOGIC_TO_UINT( X: std_logic_vector)
return integer is
begin
return to_integer(unsigned(x));
end;
component computerInterceptor
PORT(
usbClk : in std_logic;
rst : in std_logic;
computerDataPlus : in std_logic;
computerDataMinus : in std_logic;
computerDataPlusOutput : out std_logic;
computerDataMinusOutput : out std_logic;
computerLock : out std_logic
);
end component;
-- Insert signals Declarations here
signal usbClk : std_logic;
signal rst : std_logic;
signal computerDataPlus : std_logic;
signal computerDataMinus : std_logic;
signal computerDataPlusOutput : std_logic;
signal computerDataMinusOutput : std_logic;
signal computerLock : std_logic;
-- signal <name> : <type>;
begin
CLKGEN: process
variable usbClk_tmp: std_logic := '0';
begin
usbClk_tmp := not usbClk_tmp;
usbClk <= usbClk_tmp;
wait for Period/2;
end process;
DUT: computerInterceptor port map(
usbClk => usbClk,
rst => rst,
computerDataPlus => computerDataPlus,
computerDataMinus => computerDataMinus,
computerDataPlusOutput => computerDataPlusOutput,
computerDataMinusOutput => computerDataMinusOutput,
computerLock => computerLock
);
-- GOLD: <GOLD_NAME> port map(<put mappings here>);
process
begin
-- Insert TEST BENCH Code Here
rst <= '1';
computerDataPlus <= '1';
computerDataMinus <= '1';
wait for 70 ns;
rst <= '0';
wait for 70 ns;
rst <= '1';
computerDataPlus <= '0';
wait for 70 ns;
computerDataPlus <= '1';
computerDataMinus <= '0';
wait for 70 ns;
computerDataPlus <= '0';
computerDataMinus <= '1';
wait for 70 ns;
computerDataPlus <= '1';
computerDataMinus <= '0';
wait for 70 ns;
computerDataPlus <= '0';
computerDataMinus <= '1';
wait for 70 ns;
computerDataPlus <= '1';
computerDataMinus <= '0';
wait for 70 ns;
computerDataPlus <= '0';
computerDataMinus <= '1';
wait for 70 ns;
computerDataPlus <= '1';
computerDataMinus <= '0';
wait for 140 ns;
computerDataPlus <= '0';
computerDataMinus <= '1';
wait for 70 ns;
computerDataPlus <= '1';
computerDataMinus <= '0';
wait for 70 ns;
computerDataPlus <= '0';
computerDataMinus <= '1';
wait for 70 ns;
computerDataPlus <= '1';
computerDataMinus <= '0';
wait for 70 ns;
computerDataPlus <= '0';
computerDataMinus <= '1';
wait for 70 ns;
computerDataPlus <= '1';
computerDataMinus <= '0';
wait for 70 ns;
computerDataPlus <= '0';
computerDataMinus <= '1';
wait for 70 ns;
computerDataPlus <= '1';
computerDataMinus <= '0';
wait for 70 ns;
computerDataPlus <= '0';
computerDataMinus <= '1';
wait for 70 ns;
computerDataPlus <= '1';
computerDataMinus <= '0';
wait for 70 ns;
computerDataPlus <= '0';
computerDataMinus <= '1';
wait for 70 ns;
computerDataPlus <= '1';
computerDataMinus <= '0';
wait for 70 ns;
computerDataPlus <= '0';
computerDataMinus <= '1';
wait for 70 ns;
computerDataPlus <= '1';
computerDataMinus <= '0';
wait for 70 ns;
computerDataPlus <= '0';
computerDataMinus <= '1';
wait for 70 ns;
computerDataPlus <= '1';
computerDataMinus <= '0';
wait for 70 ns;
computerDataPlus <= '0';
computerDataMinus <= '1';
wait for 70 ns;
computerDataPlus <= '1';
wait for 700 ns;
end process;
end TEST; |
----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Brian Nemetz
--
-- Create Date: 10:56:50 10/16/2012
-- Design Name:
-- Module Name: top_tb.vhd
-- Project Name: classicHp
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: classic
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
--
-- WARNING: I have not used htis test bench in a long time. I'm not sure if its
-- working any longer. BKN 4/1/2014
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY top_tb IS
END top_tb;
ARCHITECTURE behavior OF top_tb IS
-- -- Component Declaration for the Unit Under Test (UUT)
--
-- COMPONENT classic
-- PORT(
-- clk_i : IN std_logic;
-- rst_i : IN std_logic;
-- keycode_i : IN std_logic_vector(7 downto 0);
-- keyvalid_i : IN std_logic;
-- error_o : OUT std_logic;
-- xreg_o : OUT std_logic_vector(55 downto 0);
-- mask_o : OUT std_logic_vector(55 downto 0);
-- update_o : OUT std_logic
-- );
-- END COMPONENT;
--Inputs
signal clk_i : std_logic := '0';
signal rst_i : std_logic := '0';
signal keycode_i : std_logic_vector(7 downto 0) := (others => '0');
signal keyvalid_i : std_logic := '0';
--Outputs
signal error_o : std_logic;
signal xreg_o : std_logic_vector(55 downto 0);
signal mask_o : std_logic_vector(55 downto 0);
signal update_o : std_logic;
signal display : string(1 to 15);
-- Clock period definitions
constant clk_i_period : time := 5 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.classic(rtl)
PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
keycode_i => keycode_i,
keyvalid_i => keyvalid_i,
error_o => error_o,
xreg_o => xreg_o,
mask_o => mask_o,
update_o => update_o
);
-- Clock process definitions
clk_i_process :process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
dis_proc : process(clk_i)
function bcd2char(bcd : std_logic_vector(3 downto 0)) return character is
begin
case bcd is
when "0000" => return '0';
when "0001" => return '1';
when "0010" => return '2';
when "0011" => return '3';
when "0100" => return '4';
when "0101" => return '5';
when "0110" => return '6';
when "0111" => return '7';
when "1000" => return '8';
when "1001" => return '9';
when others => return '?';
end case;
end function bcd2char;
variable bcd : std_logic_vector(3 downto 0);
variable mask : std_logic_vector(3 downto 0);
variable n : natural;
variable flag : boolean;
begin
if rising_edge(clk_i) then
n := 15;
flag := false;
for i in 0 to 13 loop
bcd := xreg_o((i+1)*4-1 downto i*4);
mask := mask_o((i+1)*4-1 downto i*4);
if mask = "1001" then
display(n) <= ' ';
n := n - 1;
else
if mask = "0000" and (i=2 or i=13) then
if bcd = "1001" then
display(n) <= '-';
else
display(n) <= ' ';
end if;
n := n - 1;
elsif mask = "0000" then
display(n) <= bcd2char(bcd);
n := n - 1;
else
if flag = false then
display(n) <= '.';
n := n - 1;
end if;
flag := true;
display(n) <= bcd2char(bcd);
n := n - 1;
end if;
end if;
end loop;
end if;
end process dis_proc;
-- Stimulus process
stim_proc: process
begin
keycode_i <= X"00";
keyvalid_i <= '0';
-- hold reset state for 100 ns.
rst_i <= '1';
wait for 30 ns;
rst_i <= '0';
-- wait for clk_i_period*10;
wait for 2 us;
keycode_i <= X"13"; -- 5
wait until rising_edge(clk_i);
keyvalid_i <= '1';
wait until rising_edge(clk_i);
keyvalid_i <= '0';
wait for 4 us;
keycode_i <= "00" & O"76"; -- enter
wait until rising_edge(clk_i);
keyvalid_i <= '1';
wait until rising_edge(clk_i);
keyvalid_i <= '0';
wait for 4 us;
keycode_i <= X"12"; -- 6
wait until rising_edge(clk_i);
keyvalid_i <= '1';
wait until rising_edge(clk_i);
keyvalid_i <= '0';
wait for 4 us;
keycode_i <= "00" & O"26"; -- +
wait until rising_edge(clk_i);
keyvalid_i <= '1';
wait until rising_edge(clk_i);
keyvalid_i <= '0';
-- insert stimulus here
wait;
end process;
END;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: alltap
-- File: alltap.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG Test Access Port (TAP) Controller component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package alltap is
component tap_gen
generic (
irlen : integer range 2 to 8 := 2;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
trsten : integer range 0 to 1 := 1;
scantest : integer := 0;
oepol : integer := 1);
port (
trst : in std_ulogic;
tckp : in std_ulogic;
tckn : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapi_en1 : in std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
testoen : in std_ulogic := '0';
tdoen : out std_ulogic
);
end component;
component virtex_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex2_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex4_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex5_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component spartan3_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component altera_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component fusion_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
component proasic3_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
component proasic3e_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
component proasic3l_tap
port (
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
trst : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapi_en1 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0)
);
end component;
component virtex6_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component spartan6_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component virtex7_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component kintex7_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component artix7_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
component zynq_tap
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
-------------------------------------------------------------------------------
component scanregi_inf
generic (
intesten : integer := 1
);
port (
pad : in std_ulogic;
core : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive data reg to core
bshighz : in std_ulogic
);
end component;
component scanrego_inf
port (
pad : out std_ulogic;
core : in std_ulogic;
samp : in std_ulogic; -- normally same as core unless outpad has feedback
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic -- drive data reg to pad
);
end component;
component scanregio_inf -- 3 scan registers: tdo<--input<--output<--outputen<--tdi
generic (
hzsup : integer range 0 to 1 := 1;
intesten: integer := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
padi : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
corei : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic
);
end component;
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:31:31 07/06/05
-- Design Name:
-- Module Name: CPA - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPA is
port( A , B : in std_logic_vector(7 downto 0);
-- C0 : in std_logic;
S : out std_logic_vector(7 downto 0);
C8 : out std_logic );
end CPA;
architecture Behavioral of CPA is
signal sum : std_logic_vector( 8 downto 0);
begin
sum <= ('0'& A) + ('0' & B) ;
C8 <= sum(8);
S <= sum(7 downto 0);
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: side_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY side_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE side_synth_ARCH OF side_synth IS
COMPONENT side_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: side_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:42:41 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_dlmb_bram_if_cntlr_0/system_dlmb_bram_if_cntlr_0_sim_netlist.vhdl
-- Design : system_dlmb_bram_if_cntlr_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
LMB1_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB1_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB1_AddrStrobe : in STD_LOGIC;
LMB1_ReadStrobe : in STD_LOGIC;
LMB1_WriteStrobe : in STD_LOGIC;
LMB1_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl1_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl1_Ready : out STD_LOGIC;
Sl1_Wait : out STD_LOGIC;
Sl1_UE : out STD_LOGIC;
Sl1_CE : out STD_LOGIC;
LMB2_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB2_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB2_AddrStrobe : in STD_LOGIC;
LMB2_ReadStrobe : in STD_LOGIC;
LMB2_WriteStrobe : in STD_LOGIC;
LMB2_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl2_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl2_Ready : out STD_LOGIC;
Sl2_Wait : out STD_LOGIC;
Sl2_UE : out STD_LOGIC;
Sl2_CE : out STD_LOGIC;
LMB3_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB3_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB3_AddrStrobe : in STD_LOGIC;
LMB3_ReadStrobe : in STD_LOGIC;
LMB3_WriteStrobe : in STD_LOGIC;
LMB3_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl3_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl3_Ready : out STD_LOGIC;
Sl3_Wait : out STD_LOGIC;
Sl3_UE : out STD_LOGIC;
Sl3_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 );
S_AXI_CTRL_ACLK : in STD_LOGIC;
S_AXI_CTRL_ARESETN : in STD_LOGIC;
S_AXI_CTRL_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_AWVALID : in STD_LOGIC;
S_AXI_CTRL_AWREADY : out STD_LOGIC;
S_AXI_CTRL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_CTRL_WVALID : in STD_LOGIC;
S_AXI_CTRL_WREADY : out STD_LOGIC;
S_AXI_CTRL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_CTRL_BVALID : out STD_LOGIC;
S_AXI_CTRL_BREADY : in STD_LOGIC;
S_AXI_CTRL_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_ARVALID : in STD_LOGIC;
S_AXI_CTRL_ARREADY : out STD_LOGIC;
S_AXI_CTRL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_CTRL_RVALID : out STD_LOGIC;
S_AXI_CTRL_RREADY : in STD_LOGIC;
UE : out STD_LOGIC;
CE : out STD_LOGIC;
Interrupt : out STD_LOGIC
);
attribute C_BASEADDR : string;
attribute C_BASEADDR of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_BRAM_AWIDTH : integer;
attribute C_BRAM_AWIDTH of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_CE_COUNTER_WIDTH : integer;
attribute C_CE_COUNTER_WIDTH of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_CE_FAILING_REGISTERS : integer;
attribute C_CE_FAILING_REGISTERS of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_ECC : integer;
attribute C_ECC of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_ECC_ONOFF_REGISTER : integer;
attribute C_ECC_ONOFF_REGISTER of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 1;
attribute C_ECC_STATUS_REGISTERS : integer;
attribute C_ECC_STATUS_REGISTERS of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "artix7";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_HIGHADDR : string;
attribute C_HIGHADDR of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000000000000111111111111111";
attribute C_INTERCONNECT : integer;
attribute C_INTERCONNECT of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_LMB_AWIDTH : integer;
attribute C_LMB_AWIDTH of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_LMB_DWIDTH : integer;
attribute C_LMB_DWIDTH of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_MASK : string;
attribute C_MASK of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000011000000000000000000000000000000";
attribute C_MASK1 : string;
attribute C_MASK1 of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK2 : string;
attribute C_MASK2 of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK3 : string;
attribute C_MASK3 of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_NUM_LMB : integer;
attribute C_NUM_LMB of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 1;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_S_AXI_CTRL_BASEADDR : string;
attribute C_S_AXI_CTRL_BASEADDR of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "32'b11111111111111111111111111111111";
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_S_AXI_CTRL_HIGHADDR : string;
attribute C_S_AXI_CTRL_HIGHADDR of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "32'b00000000000000000000000000000000";
attribute C_UE_FAILING_REGISTERS : integer;
attribute C_UE_FAILING_REGISTERS of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_WRITE_ACCESS : integer;
attribute C_WRITE_ACCESS of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "lmb_bram_if_cntlr";
end system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr;
architecture STRUCTURE of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr is
signal \<const0>\ : STD_LOGIC;
signal \^bram_din_a\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \^lmb_abus\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \^lmb_addrstrobe\ : STD_LOGIC;
signal \^lmb_clk\ : STD_LOGIC;
signal \^lmb_writedbus\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \No_ECC.Sl_Rdy_i_1_n_0\ : STD_LOGIC;
signal \No_ECC.lmb_as_i_1_n_0\ : STD_LOGIC;
signal Sl_Rdy : STD_LOGIC;
signal lmb_as : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \BRAM_WEN_A[0]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \BRAM_WEN_A[1]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \BRAM_WEN_A[2]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \BRAM_WEN_A[3]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \No_ECC.Sl_Rdy_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \No_ECC.lmb_as_i_1\ : label is "soft_lutpair2";
begin
BRAM_Addr_A(0 to 31) <= \^lmb_abus\(0 to 31);
BRAM_Clk_A <= \^lmb_clk\;
BRAM_Dout_A(0 to 31) <= \^lmb_writedbus\(0 to 31);
BRAM_EN_A <= \^lmb_addrstrobe\;
BRAM_Rst_A <= \<const0>\;
CE <= \<const0>\;
Interrupt <= \<const0>\;
S_AXI_CTRL_ARREADY <= \<const0>\;
S_AXI_CTRL_AWREADY <= \<const0>\;
S_AXI_CTRL_BRESP(1) <= \<const0>\;
S_AXI_CTRL_BRESP(0) <= \<const0>\;
S_AXI_CTRL_BVALID <= \<const0>\;
S_AXI_CTRL_RDATA(31) <= \<const0>\;
S_AXI_CTRL_RDATA(30) <= \<const0>\;
S_AXI_CTRL_RDATA(29) <= \<const0>\;
S_AXI_CTRL_RDATA(28) <= \<const0>\;
S_AXI_CTRL_RDATA(27) <= \<const0>\;
S_AXI_CTRL_RDATA(26) <= \<const0>\;
S_AXI_CTRL_RDATA(25) <= \<const0>\;
S_AXI_CTRL_RDATA(24) <= \<const0>\;
S_AXI_CTRL_RDATA(23) <= \<const0>\;
S_AXI_CTRL_RDATA(22) <= \<const0>\;
S_AXI_CTRL_RDATA(21) <= \<const0>\;
S_AXI_CTRL_RDATA(20) <= \<const0>\;
S_AXI_CTRL_RDATA(19) <= \<const0>\;
S_AXI_CTRL_RDATA(18) <= \<const0>\;
S_AXI_CTRL_RDATA(17) <= \<const0>\;
S_AXI_CTRL_RDATA(16) <= \<const0>\;
S_AXI_CTRL_RDATA(15) <= \<const0>\;
S_AXI_CTRL_RDATA(14) <= \<const0>\;
S_AXI_CTRL_RDATA(13) <= \<const0>\;
S_AXI_CTRL_RDATA(12) <= \<const0>\;
S_AXI_CTRL_RDATA(11) <= \<const0>\;
S_AXI_CTRL_RDATA(10) <= \<const0>\;
S_AXI_CTRL_RDATA(9) <= \<const0>\;
S_AXI_CTRL_RDATA(8) <= \<const0>\;
S_AXI_CTRL_RDATA(7) <= \<const0>\;
S_AXI_CTRL_RDATA(6) <= \<const0>\;
S_AXI_CTRL_RDATA(5) <= \<const0>\;
S_AXI_CTRL_RDATA(4) <= \<const0>\;
S_AXI_CTRL_RDATA(3) <= \<const0>\;
S_AXI_CTRL_RDATA(2) <= \<const0>\;
S_AXI_CTRL_RDATA(1) <= \<const0>\;
S_AXI_CTRL_RDATA(0) <= \<const0>\;
S_AXI_CTRL_RRESP(1) <= \<const0>\;
S_AXI_CTRL_RRESP(0) <= \<const0>\;
S_AXI_CTRL_RVALID <= \<const0>\;
S_AXI_CTRL_WREADY <= \<const0>\;
Sl1_CE <= \<const0>\;
Sl1_DBus(0) <= \<const0>\;
Sl1_DBus(1) <= \<const0>\;
Sl1_DBus(2) <= \<const0>\;
Sl1_DBus(3) <= \<const0>\;
Sl1_DBus(4) <= \<const0>\;
Sl1_DBus(5) <= \<const0>\;
Sl1_DBus(6) <= \<const0>\;
Sl1_DBus(7) <= \<const0>\;
Sl1_DBus(8) <= \<const0>\;
Sl1_DBus(9) <= \<const0>\;
Sl1_DBus(10) <= \<const0>\;
Sl1_DBus(11) <= \<const0>\;
Sl1_DBus(12) <= \<const0>\;
Sl1_DBus(13) <= \<const0>\;
Sl1_DBus(14) <= \<const0>\;
Sl1_DBus(15) <= \<const0>\;
Sl1_DBus(16) <= \<const0>\;
Sl1_DBus(17) <= \<const0>\;
Sl1_DBus(18) <= \<const0>\;
Sl1_DBus(19) <= \<const0>\;
Sl1_DBus(20) <= \<const0>\;
Sl1_DBus(21) <= \<const0>\;
Sl1_DBus(22) <= \<const0>\;
Sl1_DBus(23) <= \<const0>\;
Sl1_DBus(24) <= \<const0>\;
Sl1_DBus(25) <= \<const0>\;
Sl1_DBus(26) <= \<const0>\;
Sl1_DBus(27) <= \<const0>\;
Sl1_DBus(28) <= \<const0>\;
Sl1_DBus(29) <= \<const0>\;
Sl1_DBus(30) <= \<const0>\;
Sl1_DBus(31) <= \<const0>\;
Sl1_Ready <= \<const0>\;
Sl1_UE <= \<const0>\;
Sl1_Wait <= \<const0>\;
Sl2_CE <= \<const0>\;
Sl2_DBus(0) <= \<const0>\;
Sl2_DBus(1) <= \<const0>\;
Sl2_DBus(2) <= \<const0>\;
Sl2_DBus(3) <= \<const0>\;
Sl2_DBus(4) <= \<const0>\;
Sl2_DBus(5) <= \<const0>\;
Sl2_DBus(6) <= \<const0>\;
Sl2_DBus(7) <= \<const0>\;
Sl2_DBus(8) <= \<const0>\;
Sl2_DBus(9) <= \<const0>\;
Sl2_DBus(10) <= \<const0>\;
Sl2_DBus(11) <= \<const0>\;
Sl2_DBus(12) <= \<const0>\;
Sl2_DBus(13) <= \<const0>\;
Sl2_DBus(14) <= \<const0>\;
Sl2_DBus(15) <= \<const0>\;
Sl2_DBus(16) <= \<const0>\;
Sl2_DBus(17) <= \<const0>\;
Sl2_DBus(18) <= \<const0>\;
Sl2_DBus(19) <= \<const0>\;
Sl2_DBus(20) <= \<const0>\;
Sl2_DBus(21) <= \<const0>\;
Sl2_DBus(22) <= \<const0>\;
Sl2_DBus(23) <= \<const0>\;
Sl2_DBus(24) <= \<const0>\;
Sl2_DBus(25) <= \<const0>\;
Sl2_DBus(26) <= \<const0>\;
Sl2_DBus(27) <= \<const0>\;
Sl2_DBus(28) <= \<const0>\;
Sl2_DBus(29) <= \<const0>\;
Sl2_DBus(30) <= \<const0>\;
Sl2_DBus(31) <= \<const0>\;
Sl2_Ready <= \<const0>\;
Sl2_UE <= \<const0>\;
Sl2_Wait <= \<const0>\;
Sl3_CE <= \<const0>\;
Sl3_DBus(0) <= \<const0>\;
Sl3_DBus(1) <= \<const0>\;
Sl3_DBus(2) <= \<const0>\;
Sl3_DBus(3) <= \<const0>\;
Sl3_DBus(4) <= \<const0>\;
Sl3_DBus(5) <= \<const0>\;
Sl3_DBus(6) <= \<const0>\;
Sl3_DBus(7) <= \<const0>\;
Sl3_DBus(8) <= \<const0>\;
Sl3_DBus(9) <= \<const0>\;
Sl3_DBus(10) <= \<const0>\;
Sl3_DBus(11) <= \<const0>\;
Sl3_DBus(12) <= \<const0>\;
Sl3_DBus(13) <= \<const0>\;
Sl3_DBus(14) <= \<const0>\;
Sl3_DBus(15) <= \<const0>\;
Sl3_DBus(16) <= \<const0>\;
Sl3_DBus(17) <= \<const0>\;
Sl3_DBus(18) <= \<const0>\;
Sl3_DBus(19) <= \<const0>\;
Sl3_DBus(20) <= \<const0>\;
Sl3_DBus(21) <= \<const0>\;
Sl3_DBus(22) <= \<const0>\;
Sl3_DBus(23) <= \<const0>\;
Sl3_DBus(24) <= \<const0>\;
Sl3_DBus(25) <= \<const0>\;
Sl3_DBus(26) <= \<const0>\;
Sl3_DBus(27) <= \<const0>\;
Sl3_DBus(28) <= \<const0>\;
Sl3_DBus(29) <= \<const0>\;
Sl3_DBus(30) <= \<const0>\;
Sl3_DBus(31) <= \<const0>\;
Sl3_Ready <= \<const0>\;
Sl3_UE <= \<const0>\;
Sl3_Wait <= \<const0>\;
Sl_CE <= \<const0>\;
Sl_DBus(0 to 31) <= \^bram_din_a\(0 to 31);
Sl_UE <= \<const0>\;
Sl_Wait <= \<const0>\;
UE <= \<const0>\;
\^bram_din_a\(0 to 31) <= BRAM_Din_A(0 to 31);
\^lmb_abus\(0 to 31) <= LMB_ABus(0 to 31);
\^lmb_addrstrobe\ <= LMB_AddrStrobe;
\^lmb_clk\ <= LMB_Clk;
\^lmb_writedbus\(0 to 31) <= LMB_WriteDBus(0 to 31);
\BRAM_WEN_A[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => LMB_WriteStrobe,
I1 => LMB_BE(0),
I2 => \^lmb_abus\(1),
I3 => \^lmb_abus\(0),
O => BRAM_WEN_A(0)
);
\BRAM_WEN_A[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \^lmb_abus\(1),
I1 => \^lmb_abus\(0),
I2 => LMB_WriteStrobe,
I3 => LMB_BE(1),
O => BRAM_WEN_A(1)
);
\BRAM_WEN_A[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \^lmb_abus\(1),
I1 => \^lmb_abus\(0),
I2 => LMB_WriteStrobe,
I3 => LMB_BE(2),
O => BRAM_WEN_A(2)
);
\BRAM_WEN_A[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \^lmb_abus\(1),
I1 => \^lmb_abus\(0),
I2 => LMB_WriteStrobe,
I3 => LMB_BE(3),
O => BRAM_WEN_A(3)
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\No_ECC.Sl_Rdy_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^lmb_abus\(0),
I1 => \^lmb_abus\(1),
I2 => LMB_Rst,
O => \No_ECC.Sl_Rdy_i_1_n_0\
);
\No_ECC.Sl_Rdy_reg\: unisim.vcomponents.FDRE
port map (
C => \^lmb_clk\,
CE => '1',
D => \No_ECC.Sl_Rdy_i_1_n_0\,
Q => Sl_Rdy,
R => '0'
);
\No_ECC.lmb_as_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^lmb_addrstrobe\,
I1 => LMB_Rst,
O => \No_ECC.lmb_as_i_1_n_0\
);
\No_ECC.lmb_as_reg\: unisim.vcomponents.FDRE
port map (
C => \^lmb_clk\,
CE => '1',
D => \No_ECC.lmb_as_i_1_n_0\,
Q => lmb_as,
R => '0'
);
Sl_Ready_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Sl_Rdy,
I1 => lmb_as,
O => Sl_Ready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_dlmb_bram_if_cntlr_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_dlmb_bram_if_cntlr_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_dlmb_bram_if_cntlr_0 : entity is "system_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_dlmb_bram_if_cntlr_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_dlmb_bram_if_cntlr_0 : entity is "lmb_bram_if_cntlr,Vivado 2016.4";
end system_dlmb_bram_if_cntlr_0;
architecture STRUCTURE of system_dlmb_bram_if_cntlr_0 is
signal NLW_U0_CE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl1_CE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl1_Ready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl1_UE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl1_Wait_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl2_CE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl2_Ready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl2_UE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl2_Wait_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl3_CE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl3_Ready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl3_UE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl3_Wait_UNCONNECTED : STD_LOGIC;
signal NLW_U0_UE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_Sl1_DBus_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_Sl2_DBus_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_Sl3_DBus_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
attribute C_BASEADDR : string;
attribute C_BASEADDR of U0 : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_BRAM_AWIDTH : integer;
attribute C_BRAM_AWIDTH of U0 : label is 32;
attribute C_CE_COUNTER_WIDTH : integer;
attribute C_CE_COUNTER_WIDTH of U0 : label is 0;
attribute C_CE_FAILING_REGISTERS : integer;
attribute C_CE_FAILING_REGISTERS of U0 : label is 0;
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_REGISTER : integer;
attribute C_ECC_ONOFF_REGISTER of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 1;
attribute C_ECC_STATUS_REGISTERS : integer;
attribute C_ECC_STATUS_REGISTERS of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_HIGHADDR : string;
attribute C_HIGHADDR of U0 : label is "64'b0000000000000000000000000000000000000000000000000111111111111111";
attribute C_INTERCONNECT : integer;
attribute C_INTERCONNECT of U0 : label is 0;
attribute C_LMB_AWIDTH : integer;
attribute C_LMB_AWIDTH of U0 : label is 32;
attribute C_LMB_DWIDTH : integer;
attribute C_LMB_DWIDTH of U0 : label is 32;
attribute C_MASK : string;
attribute C_MASK of U0 : label is "64'b0000000000000000000000000000000011000000000000000000000000000000";
attribute C_MASK1 : string;
attribute C_MASK1 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK2 : string;
attribute C_MASK2 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK3 : string;
attribute C_MASK3 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_NUM_LMB : integer;
attribute C_NUM_LMB of U0 : label is 1;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_BASEADDR : string;
attribute C_S_AXI_CTRL_BASEADDR of U0 : label is "32'b11111111111111111111111111111111";
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_HIGHADDR : string;
attribute C_S_AXI_CTRL_HIGHADDR of U0 : label is "32'b00000000000000000000000000000000";
attribute C_UE_FAILING_REGISTERS : integer;
attribute C_UE_FAILING_REGISTERS of U0 : label is 0;
attribute C_WRITE_ACCESS : integer;
attribute C_WRITE_ACCESS of U0 : label is 2;
begin
U0: entity work.system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr
port map (
BRAM_Addr_A(0 to 31) => BRAM_Addr_A(0 to 31),
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Din_A(0 to 31) => BRAM_Din_A(0 to 31),
BRAM_Dout_A(0 to 31) => BRAM_Dout_A(0 to 31),
BRAM_EN_A => BRAM_EN_A,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_WEN_A(0 to 3) => BRAM_WEN_A(0 to 3),
CE => NLW_U0_CE_UNCONNECTED,
Interrupt => NLW_U0_Interrupt_UNCONNECTED,
LMB1_ABus(0 to 31) => B"00000000000000000000000000000000",
LMB1_AddrStrobe => '0',
LMB1_BE(0 to 3) => B"0000",
LMB1_ReadStrobe => '0',
LMB1_WriteDBus(0 to 31) => B"00000000000000000000000000000000",
LMB1_WriteStrobe => '0',
LMB2_ABus(0 to 31) => B"00000000000000000000000000000000",
LMB2_AddrStrobe => '0',
LMB2_BE(0 to 3) => B"0000",
LMB2_ReadStrobe => '0',
LMB2_WriteDBus(0 to 31) => B"00000000000000000000000000000000",
LMB2_WriteStrobe => '0',
LMB3_ABus(0 to 31) => B"00000000000000000000000000000000",
LMB3_AddrStrobe => '0',
LMB3_BE(0 to 3) => B"0000",
LMB3_ReadStrobe => '0',
LMB3_WriteDBus(0 to 31) => B"00000000000000000000000000000000",
LMB3_WriteStrobe => '0',
LMB_ABus(0 to 31) => LMB_ABus(0 to 31),
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_BE(0 to 3) => LMB_BE(0 to 3),
LMB_Clk => LMB_Clk,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_Rst => LMB_Rst,
LMB_WriteDBus(0 to 31) => LMB_WriteDBus(0 to 31),
LMB_WriteStrobe => LMB_WriteStrobe,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_ARREADY => NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED,
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_CTRL_AWREADY => NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED,
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_BRESP(1 downto 0) => NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED(1 downto 0),
S_AXI_CTRL_BVALID => NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED,
S_AXI_CTRL_RDATA(31 downto 0) => NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED(31 downto 0),
S_AXI_CTRL_RREADY => '0',
S_AXI_CTRL_RRESP(1 downto 0) => NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED(1 downto 0),
S_AXI_CTRL_RVALID => NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED,
S_AXI_CTRL_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_CTRL_WREADY => NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED,
S_AXI_CTRL_WSTRB(3 downto 0) => B"0000",
S_AXI_CTRL_WVALID => '0',
Sl1_CE => NLW_U0_Sl1_CE_UNCONNECTED,
Sl1_DBus(0 to 31) => NLW_U0_Sl1_DBus_UNCONNECTED(0 to 31),
Sl1_Ready => NLW_U0_Sl1_Ready_UNCONNECTED,
Sl1_UE => NLW_U0_Sl1_UE_UNCONNECTED,
Sl1_Wait => NLW_U0_Sl1_Wait_UNCONNECTED,
Sl2_CE => NLW_U0_Sl2_CE_UNCONNECTED,
Sl2_DBus(0 to 31) => NLW_U0_Sl2_DBus_UNCONNECTED(0 to 31),
Sl2_Ready => NLW_U0_Sl2_Ready_UNCONNECTED,
Sl2_UE => NLW_U0_Sl2_UE_UNCONNECTED,
Sl2_Wait => NLW_U0_Sl2_Wait_UNCONNECTED,
Sl3_CE => NLW_U0_Sl3_CE_UNCONNECTED,
Sl3_DBus(0 to 31) => NLW_U0_Sl3_DBus_UNCONNECTED(0 to 31),
Sl3_Ready => NLW_U0_Sl3_Ready_UNCONNECTED,
Sl3_UE => NLW_U0_Sl3_UE_UNCONNECTED,
Sl3_Wait => NLW_U0_Sl3_Wait_UNCONNECTED,
Sl_CE => Sl_CE,
Sl_DBus(0 to 31) => Sl_DBus(0 to 31),
Sl_Ready => Sl_Ready,
Sl_UE => Sl_UE,
Sl_Wait => Sl_Wait,
UE => NLW_U0_UE_UNCONNECTED
);
end STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2394.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n02i02394ent IS
END c07s03b02x00p07n02i02394ent;
ARCHITECTURE c07s03b02x00p07n02i02394arch OF c07s03b02x00p07n02i02394ent IS
BEGIN
TESTING: PROCESS
type t26 is record
elem_1: integer;
end record;
variable v26 : t26;
BEGIN
v26 := (elem_1 => 26);
assert NOT(v26.elem_1=26)
report "***PASSED TEST: c07s03b02x00p07n02i02394"
severity NOTE;
assert (v26.elem_1=26)
report "***FAILED TEST: c07s03b02x00p07n02i02394 - Aggregate specification should be using named association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n02i02394arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2394.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n02i02394ent IS
END c07s03b02x00p07n02i02394ent;
ARCHITECTURE c07s03b02x00p07n02i02394arch OF c07s03b02x00p07n02i02394ent IS
BEGIN
TESTING: PROCESS
type t26 is record
elem_1: integer;
end record;
variable v26 : t26;
BEGIN
v26 := (elem_1 => 26);
assert NOT(v26.elem_1=26)
report "***PASSED TEST: c07s03b02x00p07n02i02394"
severity NOTE;
assert (v26.elem_1=26)
report "***FAILED TEST: c07s03b02x00p07n02i02394 - Aggregate specification should be using named association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n02i02394arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2394.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n02i02394ent IS
END c07s03b02x00p07n02i02394ent;
ARCHITECTURE c07s03b02x00p07n02i02394arch OF c07s03b02x00p07n02i02394ent IS
BEGIN
TESTING: PROCESS
type t26 is record
elem_1: integer;
end record;
variable v26 : t26;
BEGIN
v26 := (elem_1 => 26);
assert NOT(v26.elem_1=26)
report "***PASSED TEST: c07s03b02x00p07n02i02394"
severity NOTE;
assert (v26.elem_1=26)
report "***FAILED TEST: c07s03b02x00p07n02i02394 - Aggregate specification should be using named association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n02i02394arch;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
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`protect end_protected
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Sumador32bits_tb IS
END Sumador32bits_tb;
ARCHITECTURE behavior OF Sumador32bits_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Sumador32bits
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Result : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Sumador32bits PORT MAP (
Oper1 => Oper1,
Oper2 => Oper2,
Result => Result
);
-- Stimulus process
stim_proc: process
begin
Oper1<="11110000000000000000000000000000";
Oper2<="00000000000000000000000000000100";
wait for 20 ns;
Oper1<="01110000000000000000000000000111";
Oper2<="10000000000000000000000000000101";
wait for 20 ns;
Oper1<="11111111110000101100000011000111";
Oper2<="11100000100011111111111000001111";
wait for 20 ns;
Oper1<="00000000000000000000000011000111";
Oper2<="00000000111100001111000011111111";
wait;
end process;
END;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Sumador32bits_tb IS
END Sumador32bits_tb;
ARCHITECTURE behavior OF Sumador32bits_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Sumador32bits
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Result : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Sumador32bits PORT MAP (
Oper1 => Oper1,
Oper2 => Oper2,
Result => Result
);
-- Stimulus process
stim_proc: process
begin
Oper1<="11110000000000000000000000000000";
Oper2<="00000000000000000000000000000100";
wait for 20 ns;
Oper1<="01110000000000000000000000000111";
Oper2<="10000000000000000000000000000101";
wait for 20 ns;
Oper1<="11111111110000101100000011000111";
Oper2<="11100000100011111111111000001111";
wait for 20 ns;
Oper1<="00000000000000000000000011000111";
Oper2<="00000000111100001111000011111111";
wait;
end process;
END;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
sysace_clk : in std_ulogic;
errorn : out std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
rxd : in std_ulogic;
txd : out std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
eresetn : out std_ulogic;
etx_slew : out std_logic_vector(1 downto 0);
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
cf_mpa : out std_logic_vector(6 downto 0);
cf_mpd : inout std_logic_vector(15 downto 0);
cf_mp_ce_z : out std_ulogic;
cf_mp_oe_z : out std_ulogic;
cf_mp_we_z : out std_ulogic;
cf_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, ddrlock : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal duart, rserrx, rsertx, rdsuen, ldsuen : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal ldsubre, lresetn, lock, clkml, clk1x : std_ulogic;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of ddrlock : signal is true;
attribute syn_preserve of ddrlock : signal is true;
signal dac_clk,video_clk, clkvga : std_logic; -- Signals to vgaclock.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
attribute keep of clkvga : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
sysace_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_clk, clkace);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, pciclk, clkm, open, open, open, pciclk, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, ldsubre);
dsui.break <= not ldsubre;
ndsuact <= not dsuo.active;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd when dsuen = '1' else '1';
end generate;
led_rx <= rxd;
led_tx <= duo.txd when dsuen = '1' else u1o.txd;
txd <= duo.txd when dsuen = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddr0 : ddrspa generic map (
fabtech => fabtech, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000,
rskew => CFG_DDRSP_RSKEW )
port map (lresetn, rstn, clk1x, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq);
end generate;
noddr : if (CFG_DDRSP = 0) generate ddrlock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd; u1i.ctsn <= '0'; u1i.extclk <= '0'; --txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 7, paddr => 7, pirq => 4)
port map(rstn, clkm, apbi, apbo(7), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkm);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 20000, clk2 => CFG_CLKDIV*10000/CFG_CLKMUL, burstlen => 5)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkvga);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vga_pads : if (CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /=0) generate
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
etx_slew <= "00";
eresetn <= rstn;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 6,
haddr => 16#003#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo.addr <= (others => '0'); aceo.cen <= '1'; aceo.do <= (others => '0');
aceo.doen <= '1'; aceo.oen <= '1'; aceo.wen <= '0';
end generate nograce;
cf_mpa_pads : outpadv generic map
(width => 7, tech => padtech, level => cmos, voltage => x25v)
port map (cf_mpa, aceo.addr);
cf_mp_ce_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_ce_z, aceo.cen);
cf_mpd_pads : iopadv generic map
(tech => padtech, width => 16, level => cmos, voltage => x25v)
port map (cf_mpd, aceo.do, aceo.doen, acei.di);
cf_mp_oe_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_oe_z, aceo.oen);
cf_mp_we_z_pad : outpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mp_we_z, aceo.wen);
cf_mpirq_pad : inpad generic map
(tech => padtech, level => cmos, voltage => x25v)
port map (cf_mpirq, acei.irq);
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Debug ----------------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1));
-- pragma translate_on
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent Virtex2-Pro XUP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
entity SUB is
port (
USER_I : in bit_vector(1 downto 0);
RESULT : out boolean
);
end SUB;
architecture MODEL of SUB is
procedure match(user:in bit_vector; ok: out boolean) is begin
ok := (user(USER_I'range) = USER_I);
end procedure;
begin
process(USER_I)
variable ok : boolean;
constant user : bit_vector(1 downto 0) := "01";
begin
match(user, ok);
RESULT <= ok;
end process;
end MODEL;
entity issue217 is
end issue217;
architecture MODEL of issue217 is
signal USER : bit_vector(1 downto 0);
signal OK : boolean;
begin
U: entity WORK.SUB port map (
USER_I => USER,
RESULT => OK
);
user <= "01";
process is
begin
assert not ok;
wait on ok;
assert ok;
wait;
end process;
end MODEL;
|
entity SUB is
port (
USER_I : in bit_vector(1 downto 0);
RESULT : out boolean
);
end SUB;
architecture MODEL of SUB is
procedure match(user:in bit_vector; ok: out boolean) is begin
ok := (user(USER_I'range) = USER_I);
end procedure;
begin
process(USER_I)
variable ok : boolean;
constant user : bit_vector(1 downto 0) := "01";
begin
match(user, ok);
RESULT <= ok;
end process;
end MODEL;
entity issue217 is
end issue217;
architecture MODEL of issue217 is
signal USER : bit_vector(1 downto 0);
signal OK : boolean;
begin
U: entity WORK.SUB port map (
USER_I => USER,
RESULT => OK
);
user <= "01";
process is
begin
assert not ok;
wait on ok;
assert ok;
wait;
end process;
end MODEL;
|
entity SUB is
port (
USER_I : in bit_vector(1 downto 0);
RESULT : out boolean
);
end SUB;
architecture MODEL of SUB is
procedure match(user:in bit_vector; ok: out boolean) is begin
ok := (user(USER_I'range) = USER_I);
end procedure;
begin
process(USER_I)
variable ok : boolean;
constant user : bit_vector(1 downto 0) := "01";
begin
match(user, ok);
RESULT <= ok;
end process;
end MODEL;
entity issue217 is
end issue217;
architecture MODEL of issue217 is
signal USER : bit_vector(1 downto 0);
signal OK : boolean;
begin
U: entity WORK.SUB port map (
USER_I => USER,
RESULT => OK
);
user <= "01";
process is
begin
assert not ok;
wait on ok;
assert ok;
wait;
end process;
end MODEL;
|
entity SUB is
port (
USER_I : in bit_vector(1 downto 0);
RESULT : out boolean
);
end SUB;
architecture MODEL of SUB is
procedure match(user:in bit_vector; ok: out boolean) is begin
ok := (user(USER_I'range) = USER_I);
end procedure;
begin
process(USER_I)
variable ok : boolean;
constant user : bit_vector(1 downto 0) := "01";
begin
match(user, ok);
RESULT <= ok;
end process;
end MODEL;
entity issue217 is
end issue217;
architecture MODEL of issue217 is
signal USER : bit_vector(1 downto 0);
signal OK : boolean;
begin
U: entity WORK.SUB port map (
USER_I => USER,
RESULT => OK
);
user <= "01";
process is
begin
assert not ok;
wait on ok;
assert ok;
wait;
end process;
end MODEL;
|
entity SUB is
port (
USER_I : in bit_vector(1 downto 0);
RESULT : out boolean
);
end SUB;
architecture MODEL of SUB is
procedure match(user:in bit_vector; ok: out boolean) is begin
ok := (user(USER_I'range) = USER_I);
end procedure;
begin
process(USER_I)
variable ok : boolean;
constant user : bit_vector(1 downto 0) := "01";
begin
match(user, ok);
RESULT <= ok;
end process;
end MODEL;
entity issue217 is
end issue217;
architecture MODEL of issue217 is
signal USER : bit_vector(1 downto 0);
signal OK : boolean;
begin
U: entity WORK.SUB port map (
USER_I => USER,
RESULT => OK
);
user <= "01";
process is
begin
assert not ok;
wait on ok;
assert ok;
wait;
end process;
end MODEL;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY node_port_tb IS
END node_port_tb;
ARCHITECTURE behavior OF node_port_tb IS
constant PORT_SIZE: integer := 16;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT node_port
GENERIC (WIDTH: integer := PORT_SIZE);
PORT(
I_clk : IN std_logic;
I_reset : IN std_logic;
I_writeEnable : IN std_logic;
I_readEnable : IN std_logic;
I_dataIn : IN std_logic_vector(WIDTH-1 downto 0);
O_dataOut : OUT std_logic_vector(WIDTH-1 downto 0);
O_dataOutValid : OUT std_logic
);
END COMPONENT;
--Inputs
signal I_clk : std_logic := '0';
signal I_reset : std_logic := '0';
signal I_writeEnable : std_logic := '0';
signal I_readEnable : std_logic := '0';
signal I_dataIn : std_logic_vector(PORT_SIZE-1 downto 0) := (others => '0');
--Outputs
signal O_dataOut : std_logic_vector(PORT_SIZE-1 downto 0);
signal O_dataOutValid : std_logic;
-- Clock period definitions
constant I_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: node_port
GENERIC MAP (WIDTH => PORT_SIZE)
PORT MAP (
I_clk => I_clk,
I_reset => I_reset,
I_writeEnable => I_writeEnable,
I_readEnable => I_readEnable,
I_dataIn => I_dataIn,
O_dataOut => O_dataOut,
O_dataOutValid => O_dataOutValid
);
-- Clock process definitions
I_clk_process :process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- Reset FSM
I_reset <= '1';
wait for I_clk_period;
I_reset <= '0';
wait for I_clk_period/2;
I_writeEnable <= '1';
I_readEnable <= '1';
I_dataIn <= X"0001";
wait for I_clk_period;
I_writeEnable <= '0';
wait for I_clk_period;
I_writeEnable <= '1';
wait;
end process;
END;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity C1 is
port (A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
F: out std_logic_vector(3 downto 0)
);
end C1;
architecture circuito of C1 is
begin
F <= A + B;
end circuito; |
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity C1 is
port (A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
F: out std_logic_vector(3 downto 0)
);
end C1;
architecture circuito of C1 is
begin
F <= A + B;
end circuito; |
-------------------------------------------------------------------------------
--
-- File: AD96xx_92xxSPI_Model.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Simulation model for the AD9648 ADC. Currently only the configuration SPI
-- interface implemented. The following conditions are tested:
-- 1. sSpiClk pulse high and low times are respected
-- 2. sSpiClk maximum and minimum (optional) frequency
-- 3. sCS to sSPI_Clk setup and hold times are respected
-- 4. sCS has no glitches during the 1 data byte transaction supported
-- 5. decodes command word and input data for write transactions
-- 6. generates output data byte for read transactions
-- 7. sSDIO to sSPI_Clk setup and hold times are respected
-- 8. No transitions occur on sSDIO and sCS during the idle state
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodDigitizer.all;
entity AD96xx_92xxSPI_Model is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 6;
-- The number of data bits for the data phase of the transaction:
-- only 8 data bits currently supported.
kDataWidth : integer range 0 to 63 := 8;
-- The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 0 to 63 := 8
);
Port (
-- 100MHz clock used by the AD9648_RegisterDecode block
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain)
asRst_n : in STD_LOGIC;
-- When InsertError is asserted the model produces an erroneous
-- reading for register address x01
InsertError : in STD_LOGIC;
-- 2 wire SPI interface
sSPI_Clk : in STD_LOGIC;
sSDIO : inout STD_LOGIC := 'Z';
sCS : in STD_LOGIC
);
end AD96xx_92xxSPI_Model;
architecture Behavioral of AD96xx_92xxSPI_Model is
signal sR_W_Decode : std_logic;
signal sWidthDecode : std_logic_vector(1 downto 0);
signal sAddrDecode : std_logic_vector(kCommandWidth - 4 downto 0);
signal sAddrDecodeReady : std_logic;
signal sDataWriteDecodeReady : std_logic;
signal sTransactionInProgress : boolean := false;
signal sDataDecode : std_logic_vector(kDataWidth-1 downto 0);
signal sSPI_ClkRising : time := 0 ns;
signal sSPI_ClkCounter : integer := 0;
signal sLastSPI_ClkEdge : time := 0ns;
signal sLastSPI_ClkRisingEdge : time := 0ns;
signal sSclkHigh : time := 0ns;
signal sRegDataOut : std_logic_vector(kDataWidth-1 downto 0) := x"00";
begin
AD9648_RegisterDecode_inst: entity work.AD96xx_92xx_RegisterDecode
Generic Map(
kZmodID => kZmodID,
kAddrWidth => kCommandWidth-3,
kRegDataWidth => kDataWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
InsertError => InsertError,
sDataWriteDecodeReady => sDataWriteDecodeReady,
sAddrDecodeReady => sAddrDecodeReady,
sDataDecode => sDataDecode,
sAddrDecode => sAddrDecode,
sRegDataOut => sRegDataOut
);
-- ADC Main process; checks for:
-- 1. sSpiClk pulse high and low times are respected.
-- 2. sSpiClk maximum and minimum (optional) frequency.
-- 3. sCS to sSPI_Clk setup and hold times are respected.
-- 4. sCS has no glitches during the 1 data byte transaction supported.
-- 5. decodes command word and input data for write transactions.
-- 6. generates output data byte for read transactions.
-- A sSPI_Clk falling edge is expected before sCS is pulled high.
ADC_Main: process
begin
sAddrDecodeReady <= '0';
sDataWriteDecodeReady <= '0';
if (sCS /= '0') then
wait until sCS = '0';
end if;
sSPI_ClkCounter <= 0;
sTransactionInProgress <= true;
sSDIO <= 'Z';
-- Wait for first sSPI_Clk rising edge
if (sSPI_Clk /= '0') then
wait until sSPI_Clk = '0';
end if;
wait until sSPI_Clk = '1';
-- First clock rising edge detected
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
sR_W_Decode <= sSDIO;
-- Check sCS to sSPI_Clk setup time
assert ((sCS'delayed'last_event) >= ktS)
report "setup time between sCS and sSPI_Clk is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktS) & LF & HT & HT &
"Actual: " & time'image(sCS'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk pulse width high for MSB
wait until sSPI_Clk = '0';
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "sSPI_Clk pulse width high is smaller than minimum allowed for command MSB." & LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Repeat for the following kCommandWidth-1 sSPI_Clk periods
for i in (kCommandWidth - 2) downto 0 loop
wait until sSPI_Clk = '1';
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
-- Check sSPI_Clk pulse width low
assert ((sSPI_Clk'delayed'last_event) >= kSclkLow)
report "sSPI_Clk pulse width low is smaller than minimum allowed for command bit" & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is smaller than the max allowed
assert ((sSPI_Clk'delayed'last_event + sSclkHigh) >= kSclkT_Min)
report "sSPI_Clk period is smaller than the minimum allowed for command bit" & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkT_Min) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event + sSclkHigh)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is higher than the min allowed
-- assert ((aSclkLow + sSclkHigh) <= kSclkT_Max)
-- report "sSPI_Clk period is higher than the maximum allowed." & LF & HT & HT &
-- "Expected: " & time'image(kSclkT_Max) & LF & HT & HT &
-- "Actual: " & time'image(aSclkLow + sSclkHigh)
-- severity ERROR;
if (i = kCommandWidth - 2) then
sWidthDecode(1) <= sSDIO;
elsif (i = kCommandWidth - 3) then
sWidthDecode(0) <= sSDIO;
else
sAddrDecode(i) <= sSDIO;
if (i=0) then
sAddrDecodeReady <= '1';
end if;
end if;
-- Wait sSPI_Clk falling edge
wait until sSPI_Clk = '0';
-- Check sSPI_Clk pulse width high
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "aSCK pulse width high is smaller than minimum allowed for command bit" & integer'image(i)& LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Drive first data byte when bus changes direction
if (i=0) then
if (sR_W_Decode = '1') then
sSDIO <= sRegDataOut(7);
end if;
sAddrDecodeReady <= '0';
end if;
end loop;
for i in (kDataWidth - 1) downto 0 loop
wait until sSPI_Clk = '1';
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
-- Check sSPI_Clk pulse width low
assert ((sSPI_Clk'delayed'last_event) >= kSclkLow)
report "sSPI_Clk pulse width low is smaller than minimum allowed for data bit " & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is smaller than the max allowed
assert ((sSPI_Clk'delayed'last_event + sSclkHigh) >= kSclkT_Min)
report "sSPI_Clk period is smaller than the minimum allowed for data bit " & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkT_Min) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event + sSclkHigh)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is higher than the min allowed
-- assert ((aSclkLow + sSclkHigh) <= kSclkT_Max)
-- report "sSPI_Clk period is higher than the maximum allowed." & LF & HT & HT &
-- "Expected: " & time'image(kSclkT_Max) & LF & HT & HT &
-- "Actual: " & time'image(aSclkLow + sSclkHigh)
-- severity ERROR;
-- Sample sSDIO on rising edge for write operations
if (sR_W_Decode = '0') then
sDataDecode(i) <= sSDIO;
end if;
-- Wait sSPI_Clk falling edge
wait until sSPI_Clk = '0';
-- Check sSPI_Clk pulse width high
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "aSCK pulse width high is smaller than minimum allowed for data bit" & integer'image(i) & LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Assign SDIO on falling edge for read operations
if (sR_W_Decode = '1') then
if (i > 0) then
sSDIO <= sRegDataOut(i-1);
else
sSDIO <= 'Z';
end if;
else
if (i=0) then
sDataWriteDecodeReady <= '1';
end if;
end if;
end loop;
sLastSPI_ClkEdge <= now;
sTransactionInProgress <= false;
wait until sCS = '1';
-- Check hold time between SCLK and sCS
assert ((now - sLastSPI_ClkRisingEdge) >= ktH)
report "Hold time (sCS to sSPI_Clk) is smaller than the minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktH) & LF & HT & HT &
"Actual: " & time'image(now - sLastSPI_ClkRisingEdge)
severity ERROR;
-- Check if no more than 24 bits transferred
assert ((now - sLastSPI_ClkEdge) = sSPI_Clk'last_event)
report "More than 24 bits transfered for current transaction." & LF & HT & HT
severity FAILURE;
-- Check last sSPI_Clk pulse low duration
assert ((now - sLastSPI_ClkEdge) >= kSclkLow)
report "aSCK pulse width low is smaller than minimum allowed data bit 0" & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(now - sLastSPI_ClkEdge)
severity ERROR;
end process ADC_Main;
-- Check if sCS low pulse is held low for the entire transaction
CheckCS: process
begin
if (sCS /= '0') then
wait until sCS = '0';
end if;
wait until sCS = '1';
assert (sTransactionInProgress = false)
report "CS pulse high during transaction." & LF & HT & HT
severity FAILURE;
end process CheckCS;
-- Check if sSDIO to sSPI_Clk setup time is respected
CheckSetup: process
begin
if (sSPI_Clk /= '0') then
wait until sSPI_Clk = '0';
end if;
wait until sSPI_Clk = '1';
sSPI_ClkRising <= now;
-- Check Setup Time
assert (sSDIO'last_active >= ktDS)
report "Setup time (data to sSPI_Clk) is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktDS) & LF & HT & HT &
"Actual: " & time'image(sSDIO'last_active)
severity ERROR;
end process CheckSetup;
-- Check if sSDIO to sSPI_Clk hold time is respected
CheckHold: process
begin
-- Wait for first clock rising edge
wait until sSPI_ClkRising /= 0 ns;
-- Wait for SDIO next bit to be assigned
wait until sSDIO'event;
-- Check Hold Time
assert ((now - sSPI_ClkRising) >= ktDH)
report "Hold time (data to sSPI_Clk) is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktDH) & LF & HT & HT &
"Actual: " & time'image(now - sSPI_ClkRising)
severity ERROR;
end process CheckHold;
-- Check sSDIO idle condition
CheckSDIO_Idle: process
begin
wait until now /= 0 ps;
if (sCS = '0') then
wait until sCS = '1';
end if;
-- Check that sSDIO is in '0' when entering the idle state
assert (sSDIO = '0')
report "SDIO idle condition not respected."
severity WARNING;
-- Monitor all changes on the sSDIO signal and check if they occur during the idle state (sCS = '1');
wait until sSDIO'event;
assert (sCS = '0')
report "SDIO idle condition not respected."
severity WARNING;
end process CheckSDIO_Idle;
CheckSPI_ClkIdle: process
begin
wait until now /= 0 ps;
if (sCS = '0') then
wait until sCS = '1';
end if;
-- Check that sSDIO is in '0' when entering the idle state
assert (sSPI_Clk = '0')
report "sSPI_Clk idle condition not respected."
severity WARNING;
-- Monitor all changes on the sSPI_Clk signal and check if they occur during the idle state (sCS = '1');
wait until sSPI_Clk'event;
assert (sCS = '0')
report "sSPI_Clk idle condition not respected."
severity WARNING;
end process CheckSPI_ClkIdle;
end Behavioral; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:18:24 10/06/2010
-- Design Name:
-- Module Name: AlarmMod - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AlarmMod is
port (
DecHor : in STD_LOGIC_VECTOR (3 downto 0);
UniHor : in STD_LOGIC_VECTOR (3 downto 0);
DecMin : in STD_LOGIC_VECTOR (3 downto 0);
UniMin : in STD_LOGIC_VECTOR (3 downto 0);
DecEnt : in STD_LOGIC_VECTOR (3 downto 0);--switches
UniEnt : in STD_LOGIC_VECTOR (3 downto 0);--switches
LoadHor: in STD_LOGIC;
LoadMin: in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
RingFlag: out STD_LOGIC);
end AlarmMod;
architecture Behavioral of AlarmMod is
signal alarm_hour_dec : STD_LOGIC_VECTOR (3 downto 0);
signal alarm_hour_uni : STD_LOGIC_VECTOR (3 downto 0);
signal alarm_min_dec : STD_LOGIC_VECTOR (3 downto 0);
signal alarm_min_uni : STD_LOGIC_VECTOR (3 downto 0);
signal flag : STD_LOGIC;
begin
process (Clk, Rst,LoadMin,LoadHor,DecEnt,UniEnt,alarm_hour_dec,alarm_hour_uni,alarm_min_dec,alarm_min_uni,DecHor,UniHor,DecMin,UniMin)
begin
if (Rst = '1') then
alarm_hour_dec <= (others => '0');
alarm_hour_uni <= (others => '0');
alarm_min_dec <= (others => '0');
alarm_min_uni <= (others => '0');
elsif (rising_edge(Clk)) then
if (LoadHor = '1') then
alarm_hour_dec <= DecEnt(3 downto 0);
alarm_hour_uni <= UniEnt(3 downto 0);
elsif (LoadMin = '1') then
alarm_min_dec <= DecEnt(3 downto 0);
alarm_min_uni <= UniEnt(3 downto 0);
elsif(alarm_hour_dec = DecHor and alarm_hour_uni = UniHor and alarm_min_dec = DecMin and alarm_min_uni = UniMin) then
flag <= '1';
else
flag <= '0';
end if;
end if;
end process;
RingFlag <= flag;
end Behavioral;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file frame_buffer.vhd when simulating
-- the core, frame_buffer. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY frame_buffer IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END frame_buffer;
ARCHITECTURE frame_buffer_a OF frame_buffer IS
-- synthesis translate_off
COMPONENT wrapped_frame_buffer
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_frame_buffer USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 19,
c_addrb_width => 19,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "zynq",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 307200,
c_read_depth_b => 307200,
c_read_width_a => 12,
c_read_width_b => 12,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 307200,
c_write_depth_b => 307200,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 12,
c_write_width_b => 12,
c_xdevicefamily => "zynq"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_frame_buffer
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END frame_buffer_a;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
-- Company : None
--
--------------------------------------------------------------------------------
--
-- File : MDCT.VHD
-- Created : Sat Feb 25 16:12 2006
--
--------------------------------------------------------------------------------
--
-- Description : Discrete Cosine Transform - chip top level (w/ memories)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library WORK;
use WORK.MDCT_PKG.all;
entity MDCT is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(COE_W-1 downto 0);
-- debug
odv1 : out STD_LOGIC;
dcto1 : out std_logic_vector(OP_W-1 downto 0)
);
end MDCT;
architecture RTL of MDCT is
signal ramdatao_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramraddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal romedatao_s : T_ROM1DATAO;
signal romodatao_s : T_ROM1DATAO;
signal romeaddro_s : T_ROM1ADDRO;
signal romoaddro_s : T_ROM1ADDRO;
signal rome2datao_s : T_ROM2DATAO;
signal romo2datao_s : T_ROM2DATAO;
signal rome2addro_s : T_ROM2ADDRO;
signal romo2addro_s : T_ROM2ADDRO;
signal odv2_s : STD_LOGIC;
signal dcto2_s : STD_LOGIC_VECTOR(OP_W-1 downto 0);
signal trigger2_s : STD_LOGIC;
signal trigger1_s : STD_LOGIC;
signal ramdatao1_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramdatao2_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe1_s : STD_LOGIC;
signal ramwe2_s : STD_LOGIC;
signal memswitchrd_s : STD_LOGIC;
signal memswitchwr_s : STD_LOGIC;
signal wmemsel_s : STD_LOGIC;
signal rmemsel_s : STD_LOGIC;
signal dataready_s : STD_LOGIC;
signal datareadyack_s : STD_LOGIC;
begin
------------------------------
-- 1D DCT port map
------------------------------
U_DCT1D : entity work.DCT1D
port map(
clk => clk,
rst => rst,
dcti => dcti,
idv => idv,
romedatao => romedatao_s,
romodatao => romodatao_s,
odv => odv1,
dcto => dcto1,
romeaddro => romeaddro_s,
romoaddro => romoaddro_s,
ramwaddro => ramwaddro_s,
ramdatai => ramdatai_s,
ramwe => ramwe_s,
wmemsel => wmemsel_s
);
------------------------------
-- 1D DCT port map
------------------------------
U_DCT2D : entity work.DCT2D
port map(
clk => clk,
rst => rst,
romedatao => rome2datao_s,
romodatao => romo2datao_s,
ramdatao => ramdatao_s,
dataready => dataready_s,
odv => odv,
dcto => dcto,
romeaddro => rome2addro_s,
romoaddro => romo2addro_s,
ramraddro => ramraddro_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s
);
------------------------------
-- RAM1 port map
------------------------------
U1_RAM : entity work.RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
raddr => ramraddro_s,
we => ramwe1_s,
clk => clk,
q => ramdatao1_s
);
------------------------------
-- RAM2 port map
------------------------------
U2_RAM : entity work.RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
raddr => ramraddro_s,
we => ramwe2_s,
clk => clk,
q => ramdatao2_s
);
-- double buffer switch
ramwe1_s <= ramwe_s when memswitchwr_s = '0' else '0';
ramwe2_s <= ramwe_s when memswitchwr_s = '1' else '0';
ramdatao_s <= ramdatao1_s when memswitchrd_s = '0' else ramdatao2_s;
------------------------------
-- DBUFCTL
------------------------------
U_DBUFCTL : entity work.DBUFCTL
port map(
clk => clk,
rst => rst,
wmemsel => wmemsel_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s,
memswitchwr => memswitchwr_s,
memswitchrd => memswitchrd_s,
dataready => dataready_s
);
------------------------------
-- 1st stage ROMs
------------------------------
G_ROM_ST1 : for i in 0 to 8 generate
U1_ROME : entity work.ROME
port map(
addr => romeaddro_s(i),
clk => clk,
datao => romedatao_s(i)
);
U1_ROMO : entity work.ROMO
port map(
addr => romoaddro_s(i),
clk => clk,
datao => romodatao_s(i)
);
end generate G_ROM_ST1;
------------------------------
-- 2nd stage ROMs
------------------------------
G_ROM_ST2 : for i in 0 to 10 generate
U2_ROME : entity work.ROME
port map(
addr => rome2addro_s(i),
clk => clk,
datao => rome2datao_s(i)
);
U2_ROMO : entity work.ROMO
port map(
addr => romo2addro_s(i),
clk => clk,
datao => romo2datao_s(i)
);
end generate G_ROM_ST2;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
-- Company : None
--
--------------------------------------------------------------------------------
--
-- File : MDCT.VHD
-- Created : Sat Feb 25 16:12 2006
--
--------------------------------------------------------------------------------
--
-- Description : Discrete Cosine Transform - chip top level (w/ memories)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library WORK;
use WORK.MDCT_PKG.all;
entity MDCT is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(COE_W-1 downto 0);
-- debug
odv1 : out STD_LOGIC;
dcto1 : out std_logic_vector(OP_W-1 downto 0)
);
end MDCT;
architecture RTL of MDCT is
signal ramdatao_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramraddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal romedatao_s : T_ROM1DATAO;
signal romodatao_s : T_ROM1DATAO;
signal romeaddro_s : T_ROM1ADDRO;
signal romoaddro_s : T_ROM1ADDRO;
signal rome2datao_s : T_ROM2DATAO;
signal romo2datao_s : T_ROM2DATAO;
signal rome2addro_s : T_ROM2ADDRO;
signal romo2addro_s : T_ROM2ADDRO;
signal odv2_s : STD_LOGIC;
signal dcto2_s : STD_LOGIC_VECTOR(OP_W-1 downto 0);
signal trigger2_s : STD_LOGIC;
signal trigger1_s : STD_LOGIC;
signal ramdatao1_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramdatao2_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe1_s : STD_LOGIC;
signal ramwe2_s : STD_LOGIC;
signal memswitchrd_s : STD_LOGIC;
signal memswitchwr_s : STD_LOGIC;
signal wmemsel_s : STD_LOGIC;
signal rmemsel_s : STD_LOGIC;
signal dataready_s : STD_LOGIC;
signal datareadyack_s : STD_LOGIC;
begin
------------------------------
-- 1D DCT port map
------------------------------
U_DCT1D : entity work.DCT1D
port map(
clk => clk,
rst => rst,
dcti => dcti,
idv => idv,
romedatao => romedatao_s,
romodatao => romodatao_s,
odv => odv1,
dcto => dcto1,
romeaddro => romeaddro_s,
romoaddro => romoaddro_s,
ramwaddro => ramwaddro_s,
ramdatai => ramdatai_s,
ramwe => ramwe_s,
wmemsel => wmemsel_s
);
------------------------------
-- 1D DCT port map
------------------------------
U_DCT2D : entity work.DCT2D
port map(
clk => clk,
rst => rst,
romedatao => rome2datao_s,
romodatao => romo2datao_s,
ramdatao => ramdatao_s,
dataready => dataready_s,
odv => odv,
dcto => dcto,
romeaddro => rome2addro_s,
romoaddro => romo2addro_s,
ramraddro => ramraddro_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s
);
------------------------------
-- RAM1 port map
------------------------------
U1_RAM : entity work.RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
raddr => ramraddro_s,
we => ramwe1_s,
clk => clk,
q => ramdatao1_s
);
------------------------------
-- RAM2 port map
------------------------------
U2_RAM : entity work.RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
raddr => ramraddro_s,
we => ramwe2_s,
clk => clk,
q => ramdatao2_s
);
-- double buffer switch
ramwe1_s <= ramwe_s when memswitchwr_s = '0' else '0';
ramwe2_s <= ramwe_s when memswitchwr_s = '1' else '0';
ramdatao_s <= ramdatao1_s when memswitchrd_s = '0' else ramdatao2_s;
------------------------------
-- DBUFCTL
------------------------------
U_DBUFCTL : entity work.DBUFCTL
port map(
clk => clk,
rst => rst,
wmemsel => wmemsel_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s,
memswitchwr => memswitchwr_s,
memswitchrd => memswitchrd_s,
dataready => dataready_s
);
------------------------------
-- 1st stage ROMs
------------------------------
G_ROM_ST1 : for i in 0 to 8 generate
U1_ROME : entity work.ROME
port map(
addr => romeaddro_s(i),
clk => clk,
datao => romedatao_s(i)
);
U1_ROMO : entity work.ROMO
port map(
addr => romoaddro_s(i),
clk => clk,
datao => romodatao_s(i)
);
end generate G_ROM_ST1;
------------------------------
-- 2nd stage ROMs
------------------------------
G_ROM_ST2 : for i in 0 to 10 generate
U2_ROME : entity work.ROME
port map(
addr => rome2addro_s(i),
clk => clk,
datao => rome2datao_s(i)
);
U2_ROMO : entity work.ROMO
port map(
addr => romo2addro_s(i),
clk => clk,
datao => romo2datao_s(i)
);
end generate G_ROM_ST2;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
-- Company : None
--
--------------------------------------------------------------------------------
--
-- File : MDCT.VHD
-- Created : Sat Feb 25 16:12 2006
--
--------------------------------------------------------------------------------
--
-- Description : Discrete Cosine Transform - chip top level (w/ memories)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library WORK;
use WORK.MDCT_PKG.all;
entity MDCT is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(COE_W-1 downto 0);
-- debug
odv1 : out STD_LOGIC;
dcto1 : out std_logic_vector(OP_W-1 downto 0)
);
end MDCT;
architecture RTL of MDCT is
signal ramdatao_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramraddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal romedatao_s : T_ROM1DATAO;
signal romodatao_s : T_ROM1DATAO;
signal romeaddro_s : T_ROM1ADDRO;
signal romoaddro_s : T_ROM1ADDRO;
signal rome2datao_s : T_ROM2DATAO;
signal romo2datao_s : T_ROM2DATAO;
signal rome2addro_s : T_ROM2ADDRO;
signal romo2addro_s : T_ROM2ADDRO;
signal odv2_s : STD_LOGIC;
signal dcto2_s : STD_LOGIC_VECTOR(OP_W-1 downto 0);
signal trigger2_s : STD_LOGIC;
signal trigger1_s : STD_LOGIC;
signal ramdatao1_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramdatao2_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe1_s : STD_LOGIC;
signal ramwe2_s : STD_LOGIC;
signal memswitchrd_s : STD_LOGIC;
signal memswitchwr_s : STD_LOGIC;
signal wmemsel_s : STD_LOGIC;
signal rmemsel_s : STD_LOGIC;
signal dataready_s : STD_LOGIC;
signal datareadyack_s : STD_LOGIC;
begin
------------------------------
-- 1D DCT port map
------------------------------
U_DCT1D : entity work.DCT1D
port map(
clk => clk,
rst => rst,
dcti => dcti,
idv => idv,
romedatao => romedatao_s,
romodatao => romodatao_s,
odv => odv1,
dcto => dcto1,
romeaddro => romeaddro_s,
romoaddro => romoaddro_s,
ramwaddro => ramwaddro_s,
ramdatai => ramdatai_s,
ramwe => ramwe_s,
wmemsel => wmemsel_s
);
------------------------------
-- 1D DCT port map
------------------------------
U_DCT2D : entity work.DCT2D
port map(
clk => clk,
rst => rst,
romedatao => rome2datao_s,
romodatao => romo2datao_s,
ramdatao => ramdatao_s,
dataready => dataready_s,
odv => odv,
dcto => dcto,
romeaddro => rome2addro_s,
romoaddro => romo2addro_s,
ramraddro => ramraddro_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s
);
------------------------------
-- RAM1 port map
------------------------------
U1_RAM : entity work.RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
raddr => ramraddro_s,
we => ramwe1_s,
clk => clk,
q => ramdatao1_s
);
------------------------------
-- RAM2 port map
------------------------------
U2_RAM : entity work.RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
raddr => ramraddro_s,
we => ramwe2_s,
clk => clk,
q => ramdatao2_s
);
-- double buffer switch
ramwe1_s <= ramwe_s when memswitchwr_s = '0' else '0';
ramwe2_s <= ramwe_s when memswitchwr_s = '1' else '0';
ramdatao_s <= ramdatao1_s when memswitchrd_s = '0' else ramdatao2_s;
------------------------------
-- DBUFCTL
------------------------------
U_DBUFCTL : entity work.DBUFCTL
port map(
clk => clk,
rst => rst,
wmemsel => wmemsel_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s,
memswitchwr => memswitchwr_s,
memswitchrd => memswitchrd_s,
dataready => dataready_s
);
------------------------------
-- 1st stage ROMs
------------------------------
G_ROM_ST1 : for i in 0 to 8 generate
U1_ROME : entity work.ROME
port map(
addr => romeaddro_s(i),
clk => clk,
datao => romedatao_s(i)
);
U1_ROMO : entity work.ROMO
port map(
addr => romoaddro_s(i),
clk => clk,
datao => romodatao_s(i)
);
end generate G_ROM_ST1;
------------------------------
-- 2nd stage ROMs
------------------------------
G_ROM_ST2 : for i in 0 to 10 generate
U2_ROME : entity work.ROME
port map(
addr => rome2addro_s(i),
clk => clk,
datao => rome2datao_s(i)
);
U2_ROMO : entity work.ROMO
port map(
addr => romo2addro_s(i),
clk => clk,
datao => romo2datao_s(i)
);
end generate G_ROM_ST2;
end RTL;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s510_jed is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s510_jed;
architecture behaviour of s510_jed is
constant s000000: std_logic_vector(5 downto 0) := "011011";
constant s010010: std_logic_vector(5 downto 0) := "111010";
constant s010011: std_logic_vector(5 downto 0) := "110010";
constant s000100: std_logic_vector(5 downto 0) := "110011";
constant s000001: std_logic_vector(5 downto 0) := "111011";
constant s100101: std_logic_vector(5 downto 0) := "111100";
constant s100100: std_logic_vector(5 downto 0) := "111110";
constant s000010: std_logic_vector(5 downto 0) := "111101";
constant s000011: std_logic_vector(5 downto 0) := "111111";
constant s011100: std_logic_vector(5 downto 0) := "101000";
constant s011101: std_logic_vector(5 downto 0) := "100000";
constant s000111: std_logic_vector(5 downto 0) := "110110";
constant s000101: std_logic_vector(5 downto 0) := "110111";
constant s010000: std_logic_vector(5 downto 0) := "101110";
constant s010001: std_logic_vector(5 downto 0) := "101010";
constant s001000: std_logic_vector(5 downto 0) := "010110";
constant s001001: std_logic_vector(5 downto 0) := "000110";
constant s010100: std_logic_vector(5 downto 0) := "000010";
constant s010101: std_logic_vector(5 downto 0) := "000000";
constant s001010: std_logic_vector(5 downto 0) := "100110";
constant s001011: std_logic_vector(5 downto 0) := "100010";
constant s011000: std_logic_vector(5 downto 0) := "100011";
constant s011001: std_logic_vector(5 downto 0) := "100001";
constant s011010: std_logic_vector(5 downto 0) := "010000";
constant s011011: std_logic_vector(5 downto 0) := "010001";
constant s001100: std_logic_vector(5 downto 0) := "010101";
constant s001101: std_logic_vector(5 downto 0) := "010100";
constant s011110: std_logic_vector(5 downto 0) := "101100";
constant s011111: std_logic_vector(5 downto 0) := "100100";
constant s100000: std_logic_vector(5 downto 0) := "001010";
constant s100001: std_logic_vector(5 downto 0) := "001000";
constant s100010: std_logic_vector(5 downto 0) := "101101";
constant s100011: std_logic_vector(5 downto 0) := "101111";
constant s001110: std_logic_vector(5 downto 0) := "011100";
constant s001111: std_logic_vector(5 downto 0) := "011101";
constant s100110: std_logic_vector(5 downto 0) := "010111";
constant s100111: std_logic_vector(5 downto 0) := "000111";
constant s101000: std_logic_vector(5 downto 0) := "000011";
constant s101001: std_logic_vector(5 downto 0) := "001011";
constant s101010: std_logic_vector(5 downto 0) := "100101";
constant s101011: std_logic_vector(5 downto 0) := "100111";
constant s101100: std_logic_vector(5 downto 0) := "001100";
constant s101101: std_logic_vector(5 downto 0) := "001101";
constant s101110: std_logic_vector(5 downto 0) := "101001";
constant s010110: std_logic_vector(5 downto 0) := "000100";
constant s010111: std_logic_vector(5 downto 0) := "000101";
constant s000110: std_logic_vector(5 downto 0) := "011010";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------";
case current_state is
when s000000 =>
if std_match(input, "-------------------") then next_state <= s010010; output <= "0011100";
end if;
when s010010 =>
if std_match(input, "--1----------------") then next_state <= s010011; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010010; output <= "0000100";
end if;
when s010011 =>
if std_match(input, "-------------------") then next_state <= s000100; output <= "0001101";
end if;
when s000100 =>
if std_match(input, "---11--------------") then next_state <= s000001; output <= "0000101";
elsif std_match(input, "---10--------------") then next_state <= s000000; output <= "0000101";
elsif std_match(input, "---0---------------") then next_state <= s000100; output <= "0000101";
end if;
when s000001 =>
if std_match(input, "-------------------") then next_state <= s100101; output <= "0011000";
end if;
when s100101 =>
if std_match(input, "-----1-------------") then next_state <= s100100; output <= "0000000";
elsif std_match(input, "-----0-------------") then next_state <= s100101; output <= "0000000";
end if;
when s100100 =>
if std_match(input, "-------------------") then next_state <= s000010; output <= "0001001";
end if;
when s000010 =>
if std_match(input, "------0------------") then next_state <= s000010; output <= "0000001";
elsif std_match(input, "------10-----------") then next_state <= s000001; output <= "0000001";
elsif std_match(input, "------11-----------") then next_state <= s000011; output <= "0000001";
end if;
when s000011 =>
if std_match(input, "-------------------") then next_state <= s011100; output <= "0011100";
end if;
when s011100 =>
if std_match(input, "--1----------------") then next_state <= s011101; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s011100; output <= "0000100";
end if;
when s011101 =>
if std_match(input, "-------------------") then next_state <= s000111; output <= "0001101";
end if;
when s000111 =>
if std_match(input, "---0---------------") then next_state <= s000111; output <= "0000101";
elsif std_match(input, "---1----0----------") then next_state <= s000011; output <= "0000101";
elsif std_match(input, "---1----1----------") then next_state <= s000101; output <= "0000101";
end if;
when s000101 =>
if std_match(input, "-------------------") then next_state <= s010000; output <= "0001100";
end if;
when s010000 =>
if std_match(input, "--1----------------") then next_state <= s010001; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010000; output <= "0000100";
end if;
when s010001 =>
if std_match(input, "-------------------") then next_state <= s001000; output <= "0001101";
end if;
when s001000 =>
if std_match(input, "---------0---------") then next_state <= s001000; output <= "0000101";
elsif std_match(input, "---------1---------") then next_state <= s001001; output <= "0000101";
end if;
when s001001 =>
if std_match(input, "-------------------") then next_state <= s010100; output <= "0011100";
end if;
when s010100 =>
if std_match(input, "----------0--------") then next_state <= s010100; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s010101; output <= "0000100";
end if;
when s010101 =>
if std_match(input, "-------------------") then next_state <= s001010; output <= "0001101";
end if;
when s001010 =>
if std_match(input, "-----------00------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------10------") then next_state <= s001001; output <= "0000101";
elsif std_match(input, "-----------01------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------11------") then next_state <= s001011; output <= "0000101";
end if;
when s001011 =>
if std_match(input, "-------------------") then next_state <= s011000; output <= "0101100";
end if;
when s011000 =>
if std_match(input, "----------0--------") then next_state <= s011000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s011001; output <= "0000100";
end if;
when s011001 =>
if std_match(input, "-------------------") then next_state <= s011010; output <= "0001101";
end if;
when s011010 =>
if std_match(input, "-------------0-----") then next_state <= s011010; output <= "0000101";
elsif std_match(input, "-------------1-----") then next_state <= s011011; output <= "0000101";
end if;
when s011011 =>
if std_match(input, "-------------------") then next_state <= s001100; output <= "0001111";
end if;
when s001100 =>
if std_match(input, "--------------0----") then next_state <= s001100; output <= "0000111";
elsif std_match(input, "--------------1----") then next_state <= s001101; output <= "0000111";
end if;
when s001101 =>
if std_match(input, "-------------------") then next_state <= s011110; output <= "0001101";
end if;
when s011110 =>
if std_match(input, "---------------1---") then next_state <= s011111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s011110; output <= "0000101";
end if;
when s011111 =>
if std_match(input, "-------------------") then next_state <= s100000; output <= "0011100";
end if;
when s100000 =>
if std_match(input, "----------1--------") then next_state <= s100001; output <= "0000100";
elsif std_match(input, "----------0--------") then next_state <= s100000; output <= "0000100";
end if;
when s100001 =>
if std_match(input, "-------------------") then next_state <= s100010; output <= "0001101";
end if;
when s100010 =>
if std_match(input, "------0------------") then next_state <= s100010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s100011; output <= "0000101";
end if;
when s100011 =>
if std_match(input, "-------------------") then next_state <= s001110; output <= "0001111";
end if;
when s001110 =>
if std_match(input, "----------------00-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------10-") then next_state <= s001101; output <= "0000111";
elsif std_match(input, "----------------01-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------11-") then next_state <= s001111; output <= "0000111";
end if;
when s001111 =>
if std_match(input, "-------------------") then next_state <= s100110; output <= "0001101";
end if;
when s100110 =>
if std_match(input, "---------------1---") then next_state <= s100111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s100110; output <= "0000101";
end if;
when s100111 =>
if std_match(input, "-------------------") then next_state <= s101000; output <= "0001100";
end if;
when s101000 =>
if std_match(input, "----------0--------") then next_state <= s101000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s101001; output <= "0000100";
end if;
when s101001 =>
if std_match(input, "-------------------") then next_state <= s101010; output <= "0001101";
end if;
when s101010 =>
if std_match(input, "------0------------") then next_state <= s101010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s101011; output <= "0000101";
end if;
when s101011 =>
if std_match(input, "-------------------") then next_state <= s101100; output <= "0001111";
end if;
when s101100 =>
if std_match(input, "------------------1") then next_state <= s101101; output <= "0000111";
elsif std_match(input, "------------------0") then next_state <= s101100; output <= "0000111";
end if;
when s101101 =>
if std_match(input, "-------------------") then next_state <= s101110; output <= "1000111";
end if;
when s101110 =>
if std_match(input, "-------------------") then next_state <= s010110; output <= "1000111";
end if;
when s010110 =>
if std_match(input, "1------------------") then next_state <= s010111; output <= "0000000";
elsif std_match(input, "0------------------") then next_state <= s010110; output <= "0000000";
end if;
when s010111 =>
if std_match(input, "-------------------") then next_state <= s000110; output <= "0101100";
end if;
when s000110 =>
if std_match(input, "-1-----------------") then next_state <= s000000; output <= "0000100";
elsif std_match(input, "-0-----------------") then next_state <= s000110; output <= "0000100";
end if;
when others => next_state <= "------"; output <= "-------";
end case;
end process;
end behaviour;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
ibrary IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic;
full : in std_logic
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
alias intrfc2thrd_value : std_logic_vector(0 to 31) is intrfc2thrd(0 to 31);
alias intrfc2thrd_function : std_logic_vector(0 to 15) is intrfc2thrd(32 to 47);
alias intrfc2thrd_goWait : std_logic is intrfc2thrd(48);
alias thrd2intrfc_address : std_logic_vector(0 to 31) is thrd2intrfc( 32 to 63);
alias thrd2intrfc_value : std_logic_vector(0 to 31) is thrd2intrfc( 0 to 31);
alias thrd2intrfc_function : std_logic_vector(0 to 15) is thrd2intrfc( 64 to 79);
alias thrd2intrfc_opcode : std_logic_vector(0 to 5) is thrd2intrfc( 80 to 85) ;
signal new_request : std_logic; --when there is a new request to HWTI
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal structAddr, structAddr_next : std_logic_vector(0 to 31);
signal size, size_next : std_logic_vector(0 to 31);
signal index, index_next : std_logic_vector(0 to 31);
signal mutexAddr, mutexAddr_next : std_logic_vector(0 to 31);
signal condAddr, condAddr_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
wr <= '0' when ( current_state= WAIT_STATE ) else new_request ;
rd <= exist;
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
return_state <= return_state_next;
structAddr <= structAddr_next;
size <= size_next;
mutexAddr <= mutexAddr_next;
condAddr <= condAddr_next;
count <= count_next;
-- Find out if the HWTI is tell us what to do
if (exist = '1') then
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
elsif ( new_request = '0') then
current_state <= next_state;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
new_request <= '1';
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
structAddr_next <= structAddr;
size_next <= size;
mutexAddr_next <= mutexAddr;
condAddr_next<= condAddr;
count_next <= count;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
new_request <= '0';
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
-- Read the argument, which is an address of a struct
structAddr_next <= toUser_value;
-- Initiate the reading of the first variable in the struct, size
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of mutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg3_next <= intrfc2thrd_value;
-- Read the address of condvar
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
reg4_next <= intrfc2thrd_value;
next_state <= STATE_21;
new_request <= '0';
-- hthread_mutex_lock( data->completedMutex );
when STATE_21 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
-- while( *(data->numberOfTestsCompleted) < *(data->numberOfTestsToComplete) )
when STATE_7 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- Do the comparision between completed and toBeCompleted
if ( intrfc2thrd_value < reg1 ) then
next_state <= STATE_9;
else
next_state <= STATE_16;
end if;
new_request <= '0';
-- hthread_cond_signal( condvar );
when STATE_9 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- call COND_SIGNAL
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_11;
next_state <= WAIT_STATE;
-- hthread_cond_wait( condvar, mutex );
when STATE_11 =>
-- push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- call hthread_cond_wait
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_WAIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_14;
next_state <= WAIT_STATE;
-- *( data->numberOfTestsCompleted) += 1;
when STATE_14 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg2;
thrd2intrfc_value <= intrfc2thrd_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
-- END OF WHILE LOOP
-- hthread_cond_broadcast( condvar );
when STATE_16 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
-- call COND_BROADCAST
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_BROADCAST;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_18;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( data->completedMutex );
when STATE_18 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_19;
when STATE_19 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_20;
next_state <= WAIT_STATE;
when STATE_20 =>
next_state <= FUNCTION_EXIT;
new_request <= '0';
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
new_request <= '0';
when others =>
next_state <= ERROR_STATE;
new_request <= '0';
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
entity ovl_never_unknown is
generic (
severity_level : ovl_severity_level := OVL_SEVERITY_LEVEL_NOT_SET;
width : positive := 1;
property_type : ovl_property_type := OVL_PROPERTY_TYPE_NOT_SET;
msg : string := OVL_MSG_NOT_SET;
coverage_level : ovl_coverage_level := OVL_COVERAGE_LEVEL_NOT_SET;
clock_edge : ovl_active_edges := OVL_ACTIVE_EDGES_NOT_SET;
reset_polarity : ovl_reset_polarity := OVL_RESET_POLARITY_NOT_SET;
gating_type : ovl_gating_type := OVL_GATING_TYPE_NOT_SET;
controls : ovl_ctrl_record := OVL_CTRL_DEFAULTS
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
qualifier : in std_logic;
test_expr : in std_logic_vector(width - 1 downto 0);
fire : out std_logic_vector(OVL_FIRE_WIDTH - 1 downto 0)
);
end entity ovl_never_unknown;
|
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Generic_Equalizer_No_Change_Test is
port(clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end Generic_Equalizer_No_Change_Test;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Generic_Equalizer_No_Change_Test is
begin
Generic_Equalizer : entity work.Generic_Equalizer
generic map(NO_SECTIONS => 9,
INPUT_WIDTH => 16,
INPUT_FRACT => 14,
OUTPUT_WIDTH => 16,
OUTPUT_FRACT => 14,
SCALE_WIDTH => 16,
SCALE_FRACT => (14,14,14,14,14,14,14,14,14,14),
INTERNAL_WIDTH => 30,
INTERNAL_FRACT => 24,
COEFF_WIDTH_B => 16,
COEFF_FRACT_B => (14,14,14,14,14,14,14,14,14),
COEFF_WIDTH_A => 16,
COEFF_FRACT_A => (14,14,14,14,14,14,14,14,14))
port map(clk => clk,
reset => reset,
x => input,
scale => (x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"),
b0 => (x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"
& x"4000"),
b1 => (x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
b2 => (x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
a1 => (x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
a2 => (x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"
& x"0000"),
y => output);
end architecture; |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF MMU
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The memory management unit enables virtual address
-- support. Therefore it performs page table walks,
-- manages a TLB for faster translation and handles
-- page fault via the proc control unit.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_memif_mmu_microblaze_v1_00_a;
use reconos_memif_mmu_microblaze_v1_00_a.tlb;
entity reconos_memif_mmu_microblaze is
generic (
C_CTRL_FIFO_WIDTH : integer := 32;
C_MEMIF_LENGTH_WIDTH : integer := 24;
C_TLB_SIZE : integer := 128
);
port (
-- Input FIFO ports from the HWTs (via burst converter and transaction control)
CTRL_FIFO_In_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_In_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_In_Empty : in std_logic;
CTRL_FIFO_In_RE : out std_logic;
-- Output FIFO ports to memory controller
CTRL_FIFO_Out_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Out_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Out_Empty : out std_logic;
CTRL_FIFO_Out_RE : in std_logic;
-- Seperate control and data FIFOs (emulated) for page table walks
CTRL_FIFO_Mmu_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Mmu_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Mmu_Empty : out std_logic;
CTRL_FIFO_Mmu_RE : in std_logic;
MEMIF_FIFO_Mmu_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mmu_Rem : out std_logic_vector(15 downto 0);
MEMIF_FIFO_Mmu_Full : out std_logic;
MEMIF_FIFO_Mmu_WE : in std_logic;
-- MMU ports
MMU_Pgf : out std_logic;
MMU_Fault_addr : out std_logic_vector(31 downto 0);
MMU_Retry : in std_logic;
MMU_Pgd : in std_logic_vector(31 downto 0);
MMU_Tlb_Hits : out std_logic_vector(31 downto 0);
MMU_Tlb_Misses : out std_logic_vector(31 downto 0);
MMU_Clk : in std_logic;
MMU_Rst : in std_logic;
DEBUG_DATA : out std_logic_vector(203 downto 0)
);
attribute SIGIS : string;
attribute SIGIS of MMU_Clk : signal is "Clk";
attribute SIGIS of MMU_Rst : signal is "Rst";
end entity reconos_memif_mmu_microblaze;
architecture implementation of reconos_memif_mmu_microblaze is
constant C_MEMIF_CMD_WIDTH : integer := C_CTRL_FIFO_WIDTH - C_MEMIF_LENGTH_WIDTH;
signal ctrl_in_re : std_logic;
signal ctrl_out_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_out_fill : std_logic_vector(15 downto 0);
signal ctrl_out_empty : std_logic;
signal ctrl_mmu_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_mmu_fill : std_logic_vector(15 downto 0);
signal ctrl_mmu_empty : std_logic;
-- MMU signals
type STATE_TYPE is (WAIT_REQUEST, READ_CMD, READ_ADDR,
READ_L1_ENTRY_0, READ_L1_ENTRY_1, READ_L1_ENTRY_2,
READ_L2_ENTRY_0, READ_L2_ENTRY_1, READ_L2_ENTRY_2,
WRITE_CMD, WRITE_ADDR, PAGE_FAULT);
signal state : STATE_TYPE;
signal pgf : std_logic;
signal tlb_hits : std_logic_vector(31 downto 0);
signal tlb_misses : std_logic_vector(31 downto 0);
-- these signals contain the received request data unchanged
signal ctrl_cmd : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0);
signal ctrl_length : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
signal ctrl_addr : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal l1_table_addr : std_logic_vector(31 downto 0); -- address of the level 1 page table
signal l1_descriptor_addr : std_logic_vector(31 downto 0); -- address of the level 1 page table entry
signal l2_table_addr : std_logic_vector(31 downto 0); -- address of the level 2 page table
signal l2_descriptor_addr : std_logic_vector(31 downto 0); -- address of the level 2 page table entry
signal small_page_addr : std_logic_vector(31 downto 0); -- page table entry
signal physical_addr : std_logic_vector(31 downto 0); -- physical address
signal tlb_hit : std_logic;
signal tlb_tag : std_logic_vector(19 downto 0);
signal tlb_do : std_logic_vector(19 downto 0);
signal tlb_di : std_logic_vector(19 downto 0);
signal tlb_we : std_logic;
signal clk : std_logic;
signal rst : std_logic;
begin
DEBUG_DATA(0) <= '1' when state = WAIT_REQUEST else '0';
DEBUG_DATA(1) <= '1' when state = READ_CMD else '0';
DEBUG_DATA(2) <= '1' when state = READ_ADDR else '0';
DEBUG_DATA(3) <= '1' when state = READ_L1_ENTRY_0 else '0';
DEBUG_DATA(4) <= '1' when state = READ_L1_ENTRY_1 else '0';
DEBUG_DATA(5) <= '1' when state = READ_L1_ENTRY_2 else '0';
DEBUG_DATA(6) <= '1' when state = READ_L2_ENTRY_0 else '0';
DEBUG_DATA(7) <= '1' when state = READ_L2_ENTRY_1 else '0';
DEBUG_DATA(8) <= '1' when state = READ_L2_ENTRY_2 else '0';
DEBUG_DATA(9) <= '1' when state = WRITE_CMD else '0';
DEBUG_DATA(10) <= '1' when state = WRITE_ADDR else '0';
DEBUG_DATA(11) <= '1' when state = PAGE_FAULT else '0';
DEBUG_DATA(203 downto 172) <= l1_table_addr;
DEBUG_DATA(171 downto 140) <= l1_descriptor_addr;
DEBUG_DATA(139 downto 108) <= l2_table_addr;
DEBUG_DATA(107 downto 76) <= l2_descriptor_addr;
DEBUG_DATA(75 downto 44) <= small_page_addr;
DEBUG_DATA(43 downto 12) <= physical_addr;
clk <= MMU_Clk;
rst <= MMU_Rst;
CTRL_FIFO_In_RE <= ctrl_in_re;
CTRL_FIFO_Out_Data <= ctrl_out_data;
CTRL_FIFO_Out_Fill <= ctrl_out_fill;
CTRL_FIFO_Out_Empty <= ctrl_out_empty;
CTRL_FIFO_Mmu_Data <= ctrl_mmu_data;
CTRL_FIFO_Mmu_Fill <= ctrl_mmu_fill;
CTRL_FIFO_Mmu_Empty <= ctrl_mmu_empty;
MEMIF_FIFO_Mmu_Rem <= X"1111";
MEMIF_FIFO_Mmu_Full <= '0';
MMU_Pgf <= pgf;
MMU_Fault_Addr <= ctrl_addr;
MMU_Tlb_Hits <= tlb_hits;
MMU_Tlb_Misses <= tlb_misses;
-- some address calculations based on the page table architecture
-- for detailed information look into the TRM on page 80
l1_table_addr <= MMU_Pgd;
l1_descriptor_addr <= "00" & l1_table_addr(29 downto 12) & ctrl_addr(31 downto 22) & "00";
l2_descriptor_addr <= "00" & l2_table_addr(29 downto 12) & ctrl_addr(21 downto 12) & "00";
physical_addr <= small_page_addr(31 downto 12) & ctrl_addr(11 downto 0);
mmu_proc : process(clk,rst) is
begin
if rst = '1' then
state <= WAIT_REQUEST;
ctrl_cmd <= (others => '0');
ctrl_length <= (others => '0');
ctrl_addr <= (others => '0');
ctrl_out_empty <= '1';
ctrl_out_fill <= (others => '0');
ctrl_out_data <= (others => '0');
ctrl_in_re <= '0';
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= (others => '0');
ctrl_mmu_data <= (others => '0');
pgf <= '0';
tlb_hits <= (others => '0');
tlb_misses <= (others => '0');
elsif rising_edge(clk) then
tlb_we <= '0';
case state is
when WAIT_REQUEST =>
-- start reading if there are 2 word in FIFO
--if CTRL_FIFO_In_Empty = '0' and CTRL_FIFO_In_Fill >= X"0001" then
ctrl_in_re <= '1';
state <= READ_CMD;
--end if;
when READ_CMD =>
-- read cmd and length
if CTRL_FIFO_In_Empty = '0' then
ctrl_cmd <= CTRL_FIFO_In_Data(31 downto C_MEMIF_LENGTH_WIDTH);
ctrl_length <= CTRL_FIFO_In_Data(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
state <= READ_ADDR;
end if;
when READ_ADDR =>
-- read address
if CTRL_FIFO_In_Empty = '0' then
ctrl_addr <= CTRL_FIFO_In_Data;
ctrl_in_re <= '0';
state <= READ_L1_ENTRY_0;
end if;
when READ_L1_ENTRY_0 =>
if tlb_hit = '1' then
small_page_addr(31 downto 12) <= tlb_do;
ctrl_out_empty <= '0';
ctrl_out_fill <= X"0001";
ctrl_out_data <= ctrl_cmd & ctrl_length;
tlb_hits <= tlb_hits + 1;
state <= WRITE_CMD;
else
-- write command to memory controller
ctrl_mmu_empty <= '0';
ctrl_mmu_fill <= X"0001";
ctrl_mmu_data <= X"00000004";
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_fill <= X"0000";
ctrl_mmu_data <= l1_descriptor_addr;
tlb_misses <= tlb_misses + 1;
state <= READ_L1_ENTRY_1;
end if;
end if;
when READ_L1_ENTRY_1 =>
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= X"0000";
state <= READ_L1_ENTRY_2;
end if;
when READ_L1_ENTRY_2 =>
if MEMIF_FIFO_Mmu_WE = '1' then
l2_table_addr <= MEMIF_FIFO_Mmu_Data;
if or_reduce(MEMIF_FIFO_Mmu_Data) = '0' then
pgf <= '1';
state <= PAGE_FAULT;
else
state <= READ_L2_ENTRY_0;
end if;
end if;
when READ_L2_ENTRY_0 =>
ctrl_mmu_empty <= '0';
ctrl_mmu_fill <= X"0001";
ctrl_mmu_data <= X"00000004";
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_fill <= X"0000";
ctrl_mmu_data <= l2_descriptor_addr;
state <= READ_L2_ENTRY_1;
end if;
when READ_L2_ENTRY_1 =>
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= X"0000";
state <= READ_L2_ENTRY_2;
end if;
when READ_L2_ENTRY_2 =>
if MEMIF_FIFO_Mmu_WE = '1' then
small_page_addr <= MEMIF_FIFO_Mmu_Data;
if MEMIF_FIFO_Mmu_Data(1) = '0' then
pgf <= '1';
state <= PAGE_FAULT;
else
ctrl_out_empty <= '0';
ctrl_out_fill <= X"0001";
ctrl_out_data <= ctrl_cmd & ctrl_length;
tlb_we <= '1';
state <= WRITE_CMD;
end if;
end if;
when WRITE_CMD =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_fill <= X"0000";
ctrl_out_data <= physical_addr;
state <= WRITE_ADDR;
end if;
when WRITE_ADDR =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_empty <= '1';
ctrl_out_fill <= X"0000";
state <= WAIT_REQUEST;
end if;
when PAGE_FAULT =>
pgf <= '0';
if MMU_Retry = '1' then
pgf <= '0';
state <= READ_L1_ENTRY_0;
end if;
end case;
end if;
end process mmu_proc;
tlb_tag <= ctrl_addr(31 downto 12);
tlb_di <= small_page_addr(31 downto 12);
tlb_gen : if C_TLB_SIZE > 0 generate
tlb : entity reconos_memif_mmu_microblaze_v1_00_a.tlb
generic map (
C_TLB_SIZE => C_TLB_SIZE,
C_TAG_SIZE => 20,
C_DATA_SIZE => 20
)
port map (
TLB_Tag => tlb_tag,
TLB_DI => tlb_di,
TLB_DO => tlb_do,
TLB_WE => tlb_we,
TLB_Hit => tlb_hit,
TLB_Clk => clk,
TLB_Rst => rst
);
end generate;
end architecture implementation;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF MMU
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The memory management unit enables virtual address
-- support. Therefore it performs page table walks,
-- manages a TLB for faster translation and handles
-- page fault via the proc control unit.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_memif_mmu_microblaze_v1_00_a;
use reconos_memif_mmu_microblaze_v1_00_a.tlb;
entity reconos_memif_mmu_microblaze is
generic (
C_CTRL_FIFO_WIDTH : integer := 32;
C_MEMIF_LENGTH_WIDTH : integer := 24;
C_TLB_SIZE : integer := 128
);
port (
-- Input FIFO ports from the HWTs (via burst converter and transaction control)
CTRL_FIFO_In_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_In_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_In_Empty : in std_logic;
CTRL_FIFO_In_RE : out std_logic;
-- Output FIFO ports to memory controller
CTRL_FIFO_Out_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Out_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Out_Empty : out std_logic;
CTRL_FIFO_Out_RE : in std_logic;
-- Seperate control and data FIFOs (emulated) for page table walks
CTRL_FIFO_Mmu_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Mmu_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Mmu_Empty : out std_logic;
CTRL_FIFO_Mmu_RE : in std_logic;
MEMIF_FIFO_Mmu_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mmu_Rem : out std_logic_vector(15 downto 0);
MEMIF_FIFO_Mmu_Full : out std_logic;
MEMIF_FIFO_Mmu_WE : in std_logic;
-- MMU ports
MMU_Pgf : out std_logic;
MMU_Fault_addr : out std_logic_vector(31 downto 0);
MMU_Retry : in std_logic;
MMU_Pgd : in std_logic_vector(31 downto 0);
MMU_Tlb_Hits : out std_logic_vector(31 downto 0);
MMU_Tlb_Misses : out std_logic_vector(31 downto 0);
MMU_Clk : in std_logic;
MMU_Rst : in std_logic;
DEBUG_DATA : out std_logic_vector(203 downto 0)
);
attribute SIGIS : string;
attribute SIGIS of MMU_Clk : signal is "Clk";
attribute SIGIS of MMU_Rst : signal is "Rst";
end entity reconos_memif_mmu_microblaze;
architecture implementation of reconos_memif_mmu_microblaze is
constant C_MEMIF_CMD_WIDTH : integer := C_CTRL_FIFO_WIDTH - C_MEMIF_LENGTH_WIDTH;
signal ctrl_in_re : std_logic;
signal ctrl_out_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_out_fill : std_logic_vector(15 downto 0);
signal ctrl_out_empty : std_logic;
signal ctrl_mmu_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_mmu_fill : std_logic_vector(15 downto 0);
signal ctrl_mmu_empty : std_logic;
-- MMU signals
type STATE_TYPE is (WAIT_REQUEST, READ_CMD, READ_ADDR,
READ_L1_ENTRY_0, READ_L1_ENTRY_1, READ_L1_ENTRY_2,
READ_L2_ENTRY_0, READ_L2_ENTRY_1, READ_L2_ENTRY_2,
WRITE_CMD, WRITE_ADDR, PAGE_FAULT);
signal state : STATE_TYPE;
signal pgf : std_logic;
signal tlb_hits : std_logic_vector(31 downto 0);
signal tlb_misses : std_logic_vector(31 downto 0);
-- these signals contain the received request data unchanged
signal ctrl_cmd : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0);
signal ctrl_length : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
signal ctrl_addr : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal l1_table_addr : std_logic_vector(31 downto 0); -- address of the level 1 page table
signal l1_descriptor_addr : std_logic_vector(31 downto 0); -- address of the level 1 page table entry
signal l2_table_addr : std_logic_vector(31 downto 0); -- address of the level 2 page table
signal l2_descriptor_addr : std_logic_vector(31 downto 0); -- address of the level 2 page table entry
signal small_page_addr : std_logic_vector(31 downto 0); -- page table entry
signal physical_addr : std_logic_vector(31 downto 0); -- physical address
signal tlb_hit : std_logic;
signal tlb_tag : std_logic_vector(19 downto 0);
signal tlb_do : std_logic_vector(19 downto 0);
signal tlb_di : std_logic_vector(19 downto 0);
signal tlb_we : std_logic;
signal clk : std_logic;
signal rst : std_logic;
begin
DEBUG_DATA(0) <= '1' when state = WAIT_REQUEST else '0';
DEBUG_DATA(1) <= '1' when state = READ_CMD else '0';
DEBUG_DATA(2) <= '1' when state = READ_ADDR else '0';
DEBUG_DATA(3) <= '1' when state = READ_L1_ENTRY_0 else '0';
DEBUG_DATA(4) <= '1' when state = READ_L1_ENTRY_1 else '0';
DEBUG_DATA(5) <= '1' when state = READ_L1_ENTRY_2 else '0';
DEBUG_DATA(6) <= '1' when state = READ_L2_ENTRY_0 else '0';
DEBUG_DATA(7) <= '1' when state = READ_L2_ENTRY_1 else '0';
DEBUG_DATA(8) <= '1' when state = READ_L2_ENTRY_2 else '0';
DEBUG_DATA(9) <= '1' when state = WRITE_CMD else '0';
DEBUG_DATA(10) <= '1' when state = WRITE_ADDR else '0';
DEBUG_DATA(11) <= '1' when state = PAGE_FAULT else '0';
DEBUG_DATA(203 downto 172) <= l1_table_addr;
DEBUG_DATA(171 downto 140) <= l1_descriptor_addr;
DEBUG_DATA(139 downto 108) <= l2_table_addr;
DEBUG_DATA(107 downto 76) <= l2_descriptor_addr;
DEBUG_DATA(75 downto 44) <= small_page_addr;
DEBUG_DATA(43 downto 12) <= physical_addr;
clk <= MMU_Clk;
rst <= MMU_Rst;
CTRL_FIFO_In_RE <= ctrl_in_re;
CTRL_FIFO_Out_Data <= ctrl_out_data;
CTRL_FIFO_Out_Fill <= ctrl_out_fill;
CTRL_FIFO_Out_Empty <= ctrl_out_empty;
CTRL_FIFO_Mmu_Data <= ctrl_mmu_data;
CTRL_FIFO_Mmu_Fill <= ctrl_mmu_fill;
CTRL_FIFO_Mmu_Empty <= ctrl_mmu_empty;
MEMIF_FIFO_Mmu_Rem <= X"1111";
MEMIF_FIFO_Mmu_Full <= '0';
MMU_Pgf <= pgf;
MMU_Fault_Addr <= ctrl_addr;
MMU_Tlb_Hits <= tlb_hits;
MMU_Tlb_Misses <= tlb_misses;
-- some address calculations based on the page table architecture
-- for detailed information look into the TRM on page 80
l1_table_addr <= MMU_Pgd;
l1_descriptor_addr <= "00" & l1_table_addr(29 downto 12) & ctrl_addr(31 downto 22) & "00";
l2_descriptor_addr <= "00" & l2_table_addr(29 downto 12) & ctrl_addr(21 downto 12) & "00";
physical_addr <= small_page_addr(31 downto 12) & ctrl_addr(11 downto 0);
mmu_proc : process(clk,rst) is
begin
if rst = '1' then
state <= WAIT_REQUEST;
ctrl_cmd <= (others => '0');
ctrl_length <= (others => '0');
ctrl_addr <= (others => '0');
ctrl_out_empty <= '1';
ctrl_out_fill <= (others => '0');
ctrl_out_data <= (others => '0');
ctrl_in_re <= '0';
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= (others => '0');
ctrl_mmu_data <= (others => '0');
pgf <= '0';
tlb_hits <= (others => '0');
tlb_misses <= (others => '0');
elsif rising_edge(clk) then
tlb_we <= '0';
case state is
when WAIT_REQUEST =>
-- start reading if there are 2 word in FIFO
--if CTRL_FIFO_In_Empty = '0' and CTRL_FIFO_In_Fill >= X"0001" then
ctrl_in_re <= '1';
state <= READ_CMD;
--end if;
when READ_CMD =>
-- read cmd and length
if CTRL_FIFO_In_Empty = '0' then
ctrl_cmd <= CTRL_FIFO_In_Data(31 downto C_MEMIF_LENGTH_WIDTH);
ctrl_length <= CTRL_FIFO_In_Data(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
state <= READ_ADDR;
end if;
when READ_ADDR =>
-- read address
if CTRL_FIFO_In_Empty = '0' then
ctrl_addr <= CTRL_FIFO_In_Data;
ctrl_in_re <= '0';
state <= READ_L1_ENTRY_0;
end if;
when READ_L1_ENTRY_0 =>
if tlb_hit = '1' then
small_page_addr(31 downto 12) <= tlb_do;
ctrl_out_empty <= '0';
ctrl_out_fill <= X"0001";
ctrl_out_data <= ctrl_cmd & ctrl_length;
tlb_hits <= tlb_hits + 1;
state <= WRITE_CMD;
else
-- write command to memory controller
ctrl_mmu_empty <= '0';
ctrl_mmu_fill <= X"0001";
ctrl_mmu_data <= X"00000004";
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_fill <= X"0000";
ctrl_mmu_data <= l1_descriptor_addr;
tlb_misses <= tlb_misses + 1;
state <= READ_L1_ENTRY_1;
end if;
end if;
when READ_L1_ENTRY_1 =>
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= X"0000";
state <= READ_L1_ENTRY_2;
end if;
when READ_L1_ENTRY_2 =>
if MEMIF_FIFO_Mmu_WE = '1' then
l2_table_addr <= MEMIF_FIFO_Mmu_Data;
if or_reduce(MEMIF_FIFO_Mmu_Data) = '0' then
pgf <= '1';
state <= PAGE_FAULT;
else
state <= READ_L2_ENTRY_0;
end if;
end if;
when READ_L2_ENTRY_0 =>
ctrl_mmu_empty <= '0';
ctrl_mmu_fill <= X"0001";
ctrl_mmu_data <= X"00000004";
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_fill <= X"0000";
ctrl_mmu_data <= l2_descriptor_addr;
state <= READ_L2_ENTRY_1;
end if;
when READ_L2_ENTRY_1 =>
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= X"0000";
state <= READ_L2_ENTRY_2;
end if;
when READ_L2_ENTRY_2 =>
if MEMIF_FIFO_Mmu_WE = '1' then
small_page_addr <= MEMIF_FIFO_Mmu_Data;
if MEMIF_FIFO_Mmu_Data(1) = '0' then
pgf <= '1';
state <= PAGE_FAULT;
else
ctrl_out_empty <= '0';
ctrl_out_fill <= X"0001";
ctrl_out_data <= ctrl_cmd & ctrl_length;
tlb_we <= '1';
state <= WRITE_CMD;
end if;
end if;
when WRITE_CMD =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_fill <= X"0000";
ctrl_out_data <= physical_addr;
state <= WRITE_ADDR;
end if;
when WRITE_ADDR =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_empty <= '1';
ctrl_out_fill <= X"0000";
state <= WAIT_REQUEST;
end if;
when PAGE_FAULT =>
pgf <= '0';
if MMU_Retry = '1' then
pgf <= '0';
state <= READ_L1_ENTRY_0;
end if;
end case;
end if;
end process mmu_proc;
tlb_tag <= ctrl_addr(31 downto 12);
tlb_di <= small_page_addr(31 downto 12);
tlb_gen : if C_TLB_SIZE > 0 generate
tlb : entity reconos_memif_mmu_microblaze_v1_00_a.tlb
generic map (
C_TLB_SIZE => C_TLB_SIZE,
C_TAG_SIZE => 20,
C_DATA_SIZE => 20
)
port map (
TLB_Tag => tlb_tag,
TLB_DI => tlb_di,
TLB_DO => tlb_do,
TLB_WE => tlb_we,
TLB_Hit => tlb_hit,
TLB_Clk => clk,
TLB_Rst => rst
);
end generate;
end architecture implementation;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_icon_7_port.vhd
-- /___/ /\ Timestamp : Wed Apr 03 08:32:11 BRT 2013
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_icon_7_port IS
port (
CONTROL0: inout std_logic_vector(35 downto 0);
CONTROL1: inout std_logic_vector(35 downto 0);
CONTROL2: inout std_logic_vector(35 downto 0);
CONTROL3: inout std_logic_vector(35 downto 0);
CONTROL4: inout std_logic_vector(35 downto 0);
CONTROL5: inout std_logic_vector(35 downto 0);
CONTROL6: inout std_logic_vector(35 downto 0));
END chipscope_icon_7_port;
ARCHITECTURE chipscope_icon_7_port_a OF chipscope_icon_7_port IS
BEGIN
END chipscope_icon_7_port_a;
|
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Different to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_163 is
generic(
NUM_BITS : positive := 163
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_163 is
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
----------------------------------------------------------------------------------------------------
-- control signals
signal en_VS, C_0, C_3, ISPos: std_logic;
signal V, S, to_V, to_S : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, R, to_U, to_R : STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- Internal registers
signal u_div_2, v_div_2, r_div_2, s_div_2, p_div_2, op1: STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- Internal registers
signal D: STD_LOGIC_VECTOR(3 downto 0); -- Internal registers
signal counter: STD_LOGIC_VECTOR(8 downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, LOAD2, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
U_div_2 <= '0' & U(NUM_BITS-1 downto 1);
R_div_2 <= '0' & R(NUM_BITS-1 downto 1);
P_div_2 <= p(NUM_BITS downto 1);
S_div_2 <= S(NUM_BITS downto 1);
V_div_2 <= V(NUM_BITS downto 1);
to_U <= U_div_2 xor V_div_2 when c_0 = '1' else
U_div_2;
op1 <= R_div_2 xor P_div_2 when c_3 = '1' else
R_div_2;
to_R <= op1 xor S_div_2 when c_0 = '1' else
op1;
to_V <= Y & '0' when rst = '1' else
p when CurrentState = LOAD1 else
'0' & U;
to_S <= X & '0' when rst = '1' else
(others => '0') when CurrentState = LOAD1 else
'0' & R;
en_VS <= '1' when rst = '1' or CurrentState = LOAD1 or (U(0) = '1' and IsPos = '0') else
'0';
c_0 <= '1' when CurrentState = LOAD1 or U(0) = '1' else
'0';
c_3 <= '0' when (CurrentState = LOAD1 or R(0) = '0') else
'1';
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
R <= (others => '0');
U <= (others => '0');
x_div_y <= (others => '0');
if en_VS = '1' then
V <= to_V;
S <= to_S;
end if;
done <= '0';
counter <= "101000110"; --2*m - 2
IsPos <= '0';
D <= "0001";
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
R <= to_R;
U <= to_U;
if en_VS = '1' then
V <= to_V;
S <= to_S;
end if;
currentState <= Cycle;
when CYCLE =>
counter <= counter - 1;
R <= to_R;
U <= to_U;
if en_VS = '1' then
V <= to_V;
S <= to_S;
end if;
if U(0) = '0' then
if IsPos = '0' then D <= D + 1;
elsif D = "0000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
elsif IsPos = '1' then
if D = "0000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
else
D <= D - 1;
IsPos <= '1';
end if;
if counter = "000000000" then
done <= '1';
x_div_y <= S(NUM_BITS-1 downto 0);
CurrentState <= END_STATE;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY circuita IS
--
PORT (
INPUT : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- (2)=A, (1)=B, (0)=C
OUTPUT : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) -- F0, F1, F2
);
END circuita;
ARCHITECTURE Behavior OF circuita IS
BEGIN
OUTPUT(0) <= INPUT(0);
OUTPUT(1) <= NOT INPUT(1);
OUTPUT(2) <= INPUT(2) OR INPUT(1);
END Behavior; |
--------------------------------------------------------------------------------
-- Datapath made of the following stages:
-- fetch
-- decode
-- execute
-- memory
-- writeback
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity DataPath is
port(
-- INPUTS
clk : in std_logic;
rst : in std_logic;
fromIRAM : in std_logic_vector(31 downto 0); -- data coming from IRAM
cw : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0); -- Control Word + ALU operation for the current instruction decoded
-- OUTPUTS
opcode : out std_logic_vector(OPCODE_SIZE-1 downto 0); -- opcode field in instruction register
func : out std_logic_vector(FUNC_SIZE-1 downto 0); -- func field in instruction register
Addr : out std_logic_vector(31 downto 0) -- address coming from PC (goes to IRAM)
);
end DataPath;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture struct of DataPath is
-- component declarations
component fetch is
port (
--INPTUS
jump_address : in std_logic_vector(31 downto 0);
branch_target : in std_logic_vector(31 downto 0);
from_iram : in std_logic_vector(31 downto 0);
flush : in std_logic;
clk : in std_logic;
rst : in std_logic;
pcsrc : in std_logic;
jump : in std_logic;
pcwrite : in std_logic;
--OUTPUTS
to_iram : out std_logic_vector(31 downto 0);
pc_4 : out std_logic_vector(31 downto 0);
instruction_fetch : out std_logic_vector(31 downto 0)
);
end component;
component decode_unit is
port (
-- INPUTS
address_write : in std_logic_vector(4 downto 0); -- register address that should be written
data_write : in std_logic_vector(31 downto 0); -- data to be written in the reg file
pc_4_from_dec : in std_logic_vector(31 downto 0); -- Program counter incremented by 4
instruction : in std_logic_vector(31 downto 0); -- instruction fetched
idex_rt : in std_logic_vector(4 downto 0); -- Rt register coming from the ex stage
clk : in std_logic; -- global clock
rst : in std_logic; -- global reset signal
reg_write : in std_logic; -- Reg Write signal to enable the write operation
idex_mem_read : in std_logic_vector(3 downto 0); -- control signals for Mem Read (lb,lhu, lw, lbu)
cw : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0); -- control word + alu operation produced by the CU
-- OUTPUTS
cw_to_ex : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word + alu operation for the ex stage (-2 since unsigned control signal used i the decode stage)
jump_address : out std_logic_vector(31 downto 0); -- jump address sign-extended
pc_4_to_ex : out std_logic_vector(31 downto 0); -- Program counter incremented by 4 directed to the ex stage
data_read_1 : out std_logic_vector(31 downto 0); -- Output of read port 1 of reg file
data_read_2 : out std_logic_vector(31 downto 0); -- Output of read port 2 of reg file
immediate_ext : out std_logic_vector(31 downto 0); -- Immediate field signe-exntended
immediate : out std_logic_vector(15 downto 0); -- Immediate filed not sign extended (for LUI instruction)
rt : out std_logic_Vector(4 downto 0); -- rt address (instruction 20-16)
rd : out std_logic_vector(4 downto 0); -- rd address (instruction 15-11)
rs : out std_logic_vector(4 downto 0); -- rs address (instruction 25-21)
opcode : out std_logic_vector(OPCODE_SIZE-1 downto 0); -- opcode for the CU, instruction (31-26)
func : out std_logic_vector(FUNC_SIZE-1 downto 0); -- func field of instruction (10-0) to the CU
pcwrite : out std_logic; -- write enable generated by the Hazard Detection Unit for the PC
ifid_write : out std_logic -- write enable generated by the Hazard Detection Unit for the IF/ID pipeline register
);
end component;
component execute is
port(
clk : in std_logic;
rst : in std_logic;
-- inputs from IDEX pipeline reg
controls_in : in std_logic_vector(21 downto 0); -- we have 22 signals: CU generates a total of 23 signals (including 5 ALUOP signals), but 1 signal (unsigned) is already exhausted in the DECODE stage
ext25_0 : in std_logic_vector(31 downto 0); -- bits 25_0 of instr. sign/unsign extended to 32 bits
nextPC : in std_logic_vector(31 downto 0);
op_A : in std_logic_vector(31 downto 0);
op_B : in std_logic_vector(31 downto 0);
ext15_0 : in std_logic_vector(31 downto 0); -- bits 15_0 of instr. sign/unsign extended to 32 bits
inst15_0 : in std_logic_vector(15 downto 0); -- bits 15_0 of instr.
rt_inst : in std_logic_vector(4 downto 0);
rd_inst : in std_logic_vector(4 downto 0);
rs_inst : in std_logic_vector(4 downto 0);
-- inputs from other sources
unaligned : in std_logic; -- from MMU, '1' when an unaligned access to memory has been done
forw_dataWB : in std_logic_vector(31 downto 0); -- data from WB stage that is used if forwarding needed
forw_dataMEM : in std_logic_vector(31 downto 0); -- data from MEM stage that is used if forwarding needed
RFaddr_WB : in std_logic_vector(4 downto 0); -- addr of RF from WB stage, goes to forwarding unit
RFaddr_MEM : in std_logic_vector(4 downto 0); -- addr of RF from MEM stage, goes to forwarding unit
regwriteWB : in std_logic; -- reg_write ctrl signal from WB stage
regwriteMEM : in std_logic; -- reg_write ctrl signal from MEM stage
-- outputs
controls_out : out std_logic_vector(10 downto 0); -- 11 control signals go to MEM stage (11 are exhausted in the EXE stage)
toPC1 : out std_logic_vector(31 downto 0);
toPC2 : out std_logic_vector(31 downto 0);
branchTaken : out std_logic;
addrMem : out std_logic_vector(31 downto 0);
writeData : out std_logic_vector(31 downto 0);
addrRF : out std_logic_vector(4 downto 0);
IDEX_rt : out std_logic_vector(4 downto 0); -- goes to hazard unit
IDEX_memread : out std_logic_vector(3 downto 0) -- goes to hazard unit
);
end component;
component memory is
port(
-- inputs
rst : in std_logic;
controls_in : in std_logic_vector(10 downto 0);
PC1_in : in std_logic_vector(31 downto 0);
PC2_in : in std_logic_vector(31 downto 0);
takeBranch : in std_logic;
addrMem : in std_logic_vector(31 downto 0);
writeData : in std_logic_vector(31 downto 0);
RFaddr_in : in std_logic_vector(4 downto 0);
-- outputs
controls_out : out std_logic_vector(2 downto 0);
dataOut_mem : out std_logic_vector(31 downto 0); -- data that has been read directly from memory
dataOut_exe : out std_logic_vector(31 downto 0); -- data that has been produced in exe stage
RFaddr_out : out std_logic_vector(4 downto 0);
unaligned : out std_logic;
PCsrc : out std_logic;
flush : out std_logic;
jump : out std_logic;
PC1_out : out std_logic_vector(31 downto 0);
PC2_out : out std_logic_vector(31 downto 0);
regwrite_MEM : out std_logic; -- goes to forwarding unit
RFaddr_MEM : out std_logic_vector(4 downto 0); -- goes to forwarding unit
forw_addr_MEM : out std_logic_vector(31 downto 0) -- goes to EXE stage and is used if forwarding detected by forwarding unit
);
end component;
component writeback is
port(
-- inputs
from_mem_data : in std_logic_vector(31 downto 0);
from_alu_data : in std_logic_vector(31 downto 0); -- named from_alu but data can come from other sources as well, but not from memory
regfile_addr_in : in std_logic_vector(4 downto 0); -- address of register to write
regwrite_in : in std_logic; -- control signal (1 -> write in reg file)
link : in std_logic; -- control signal (1 -> link the instruction, save IP in R31)
memtoreg : in std_logic;
-- outputs
regwrite_out : out std_logic; -- control signal (send regwrite signal back to other stages)
regfile_data : out std_logic_vector(31 downto 0);
regfile_addr_out : out std_logic_vector(4 downto 0)
);
end component;
component ifid_reg is
port (
-- INPUTS
pc_4 : in std_logic_vector(31 downto 0); -- PC + 4 coming from the fetch stage
instruction_fetch : in std_logic_vector(31 downto 0); -- Instruction to be decoded
flush : in std_logic; -- flush control signal
ifid_write : in std_logic; -- write enable
clk : in std_logic; -- clock signal
rst : in std_logic; -- reset signal
-- OUTPUTS
instruction_decode : out std_logic_vector(31 downto 0); -- Instruction for the decode stage
new_pc : out std_logic_vector(31 downto 0) -- PC + 4 directed to the next pipeline register
);
end component;
component idex_reg is
port (
-- INPUTS
cw_to_ex_dec : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word directed to the ex stage (note -2 since unsigned control signal is alredy used in decode thus no need to propagate)
jump_address_dec : in std_logic_vector(31 downto 0); -- jump address extended
pc_4_dec : in std_logic_vector(31 downto 0); -- PC incremented by 4 from decode
read_data_1_dec : in std_logic_vector(31 downto 0); -- reg 1 read from decode
read_data_2_dec : in std_logic_vector(31 downto 0); -- reg 2 read from decode
immediate_ext_dec : in std_logic_vector(31 downto 0); -- immediate sign extended from decode
immediate_dec : in std_logic_vector(15 downto 0); -- immediate for lui instrucion from decode
rt_dec : in std_logic_vector(4 downto 0); -- rt address from decode
rd_dec : in std_logic_vector(4 downto 0); -- rs address from decode
rs_dec : in std_logic_vector(4 downto 0); -- rd address from decode
clk : in std_logic; -- global clock signal
rst : in std_logic; -- global reset signal
-- OUTPUTS
cw_to_ex : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word for ex stage
jump_address : out std_logic_vector(31 downto 0); -- jump address to ex stage
pc_4 : out std_logic_vector(31 downto 0);
read_data_1 : out std_logic_vector(31 downto 0);
read_data_2 : out std_logic_vector(31 downto 0);
immediate_ext : out std_logic_vector(31 downto 0);
immediate : out std_logic_vector(15 downto 0);
rt : out std_logic_vector(4 downto 0);
rd : out std_logic_vector(4 downto 0);
rs : out std_logic_vector(4 downto 0)
);
end component;
component EX_MEM_Reg is
port (
-- input signals
clk : in std_logic; -- clock source
rst : in std_logic; -- reset signal
controls_in : in std_logic_vector(10 downto 0); -- 11 control signals go from exe to mem stage
toPC1_in : in std_logic_vector(31 downto 0); -- from jreg controlled mux
toPC2_in : in std_logic_vector(31 downto 0); -- from adder2
takeBranch_in : in std_logic; -- from Branch circuit, if 1 branch must be taken (if inst. is a branch, see AND in MEM stage)
mem_addr_in : in std_logic_vector(31 downto 0);
mem_writedata_in : in std_logic_vector(31 downto 0);
regfile_addr_in : in std_logic_vector(4 downto 0);
-- output signals
controls_out : out std_logic_vector(10 downto 0);
toPC1_out : out std_logic_vector(31 downto 0);
toPC2_out : out std_logic_vector(31 downto 0);
takeBranch_out : out std_logic;
mem_addr_out : out std_logic_vector(31 downto 0);
mem_writedata_out : out std_logic_vector(31 downto 0);
regfile_addr_out : out std_logic_vector(4 downto 0)
);
end component;
component MEM_WB_Reg is
port (
-- input signals
clk : in std_logic; -- clock source
rst : in std_logic; -- reset signal
controls_in : in std_logic_vector(2 downto 0); -- in order, from MSB to LSB : regwrite, link, memtoreg
from_mem_data_in : in std_logic_vector(31 downto 0);
from_alu_data_in : in std_logic_vector(31 downto 0);
regfile_addr_in : in std_logic_vector(4 downto 0);
-- output signals
controls_out : out std_logic_vector(2 downto 0);
from_mem_data_out : out std_logic_vector(31 downto 0);
from_alu_data_out : out std_logic_vector(31 downto 0);
regfile_addr_out : out std_logic_vector(4 downto 0)
);
end component;
-- signal declarations
signal jump_address_i : std_logic_vector(31 downto 0);
signal branch_target_i : std_logic_vector(31 downto 0);
signal flush_i : std_logic;
signal pcsrc_i : std_logic;
signal jump_i : std_logic;
signal pcwrite_i : std_logic;
signal pc_4_i : std_logic_vector(31 downto 0);
signal instruction_fetch_i : std_logic_vector(31 downto 0);
signal instruction_decode_i : std_logic_vector(31 downto 0);
signal new_pc_i : std_logic_vector(31 downto 0);
signal ifid_write_i : std_logic;
signal address_write_i : std_logic_vector(4 downto 0);
signal data_write_i : std_logic_vector(31 downto 0);
signal idex_rt_i : std_logic_vector(4 downto 0);
signal reg_write_i : std_logic;
signal idex_mem_read_i : std_logic_vector(3 downto 0);
signal jaddr_i : std_logic_vector(31 downto 0);
signal pc4_to_idexreg_i : std_logic_vector(31 downto 0);
signal data_read_dec_1_i : std_logic_vector(31 downto 0);
signal data_read_dec_2_i : std_logic_vector(31 downto 0);
signal immediate_ext_dec_i : std_logic_vector(31 downto 0);
signal immediate_dec_i : std_logic_vector(15 downto 0);
signal rt_dec_i : std_logic_vector(4 downto 0);
signal rd_dec_i : std_logic_vector(4 downto 0);
signal rs_dec_i : std_logic_vector(4 downto 0);
signal cw_to_idex_i : std_logic_vector(21 downto 0);
signal cw_to_ex_i : std_logic_vector(21 downto 0);
signal jump_address_toex_i : std_logic_vector(31 downto 0);
signal pc_4_to_ex_i : std_logic_vector(31 downto 0);
signal data_read_ex_1_i : std_logic_vector(31 downto 0);
signal data_read_ex_2_i : std_logic_vector(31 downto 0);
signal immediate_ext_ex_i : std_logic_vector(31 downto 0);
signal immediate_ex_i : std_logic_vector(15 downto 0);
signal rt_ex_i : std_logic_vector(4 downto 0);
signal rd_ex_i : std_logic_vector(4 downto 0);
signal rs_ex_i : std_logic_vector(4 downto 0);
signal unaligned_i : std_logic;
signal forw_dataMEM_i : std_logic_vector(31 downto 0);
signal RFaddr_MEM_i : std_logic_vector(4 downto 0);
signal regwriteMEM_i : std_logic;
signal cw_exmem_i : std_logic_vector(10 downto 0);
signal toPC1_i : std_logic_vector(31 downto 0);
signal toPC2_i : std_logic_vector(31 downto 0);
signal branchTaken_i : std_logic;
signal addrMem_exmem_i : std_logic_vector(31 downto 0);
signal writeData_exmem_i : std_logic_vector(31 downto 0);
signal addrRF_exmem_i : std_logic_vector(4 downto 0);
signal cw_tomem_i : std_logic_vector(10 downto 0);
signal PC1_tomem_i : std_logic_vector(31 downto 0);
signal PC2_tomem_i : std_logic_vector(31 downto 0);
signal takeBranch_out_i : std_logic;
signal mem_addr_out_i : std_logic_vector(31 downto 0);
signal mem_writedata_out_i : std_logic_vector(31 downto 0);
signal regfile_addr_out_tomem_i : std_logic_vector(4 downto 0);
signal cw_memwb_i : std_logic_vector(2 downto 0);
signal dataOut_mem_i : std_logic_vector(31 downto 0);
signal dataOut_exe_i : std_logic_vector(31 downto 0);
signal RFaddr_out_memwb_i : std_logic_vector(4 downto 0);
signal cw_towb_i : std_logic_vector(2 downto 0);
signal from_mem_data_out_i : std_logic_vector(31 downto 0);
signal from_alu_data_out_i : std_logic_vector(31 downto 0);
signal regfile_addr_out_towb_i : std_logic_vector(4 downto 0);
begin
-- component instantiations
u_fetch: fetch
port map (
--INPTUS
jump_address => jump_address_i,
branch_target => branch_target_i,
from_iram => fromIRAM,
flush => flush_i,
clk => clk,
rst => rst,
pcsrc => pcsrc_i,
jump => jump_i,
pcwrite => pcwrite_i,
--OUTPUTS
to_iram => Addr,
pc_4 => pc_4_i,
instruction_fetch => instruction_fetch_i
);
u_ifidreg : ifid_reg port map(
-- INPUTS
pc_4 => pc_4_i, -- PC + 4 coming from the fetch stage
instruction_fetch => instruction_fetch_i, -- Instruction to be decoded
flush => flush_i, -- flush control signal
ifid_write => ifid_write_i, -- write enable
clk => clk, -- clock signal
rst => rst, -- reset signal
-- OUTPUTS
instruction_decode => instruction_decode_i, -- Instruction for the decode stage
new_pc => new_pc_i -- PC + 4 directed to the next pipeline register
);
u_decode_unit: decode_unit
port map (
-- INPUTS
address_write => address_write_i, -- regter address that should be written
data_write => data_write_i, -- data to be written in the reg file
pc_4_from_dec => new_pc_i, -- Program counter incremented by 4
instruction => instruction_decode_i, -- instruction fetched
idex_rt => idex_rt_i, -- Rt regter coming from the ex stage
clk => clk, -- global clock
rst => rst, -- global reset signal
reg_write => reg_write_i, -- Reg Write signal to enable the write operation
idex_mem_read => idex_mem_read_i, -- control signals for Mem Read (lb,lhu, lw, lbu)
cw => cw, -- control word + alu operation produced by the CU
-- OUTPUTS
cw_to_ex => cw_to_idex_i, -- control word + alu operation for the ex stage (-2 since unsigned control signal used i the decode stage)
jump_address => jaddr_i, -- jump address sign-extended
pc_4_to_ex => pc4_to_idexreg_i, -- Program counter incremented by 4 directed to the ex stage
data_read_1 => data_read_dec_1_i, -- Output of read port 1 of reg file
data_read_2 => data_read_dec_2_i, -- Output of read port 2 of reg file
immediate_ext => immediate_ext_dec_i, -- Immediate field signe-exntended
immediate => immediate_dec_i, -- Immediate filed not sign extended (for LUI instruction)
rt => rt_dec_i, -- rt address (instruction 20-16)
rd => rd_dec_i, -- rd address (instruction 15-11)
rs => rs_dec_i, -- rs address (instruction 25-21)
opcode => opcode, -- opcode for the CU, instruction (31-26)
func => func, -- func field of instruction (10-0) to the CU
pcwrite => pcwrite_i, -- write enable generated by the Hazard Detection Unit for the PC
ifid_write => ifid_write_i -- write enable generated by the Hazard Detection Unit for the IF/ID pipeline regter
);
u_idexreg: idex_reg port map(
-- INPUTS
cw_to_ex_dec => cw_to_idex_i, -- control word directed to the ex stage (note -2 since unsigned control signal is alredy used in decode thus no need to propagate)
jump_address_dec => jaddr_i, -- jump address extended
pc_4_dec => pc4_to_idexreg_i, -- PC incremented by 4 from decode
read_data_1_dec => data_read_dec_1_i, -- reg 1 read from decode
read_data_2_dec => data_read_dec_2_i, -- reg 2 read from decode
immediate_ext_dec => immediate_ext_dec_i, -- immediate sign extended from decode
immediate_dec => immediate_dec_i, -- immediate for lui instrucion from decode
rt_dec => rt_dec_i, -- rt address from decode
rd_dec => rd_dec_i, -- rs address from decode
rs_dec => rs_dec_i, -- rd address from decode
clk => clk, -- global clock signal
rst => rst, -- global reset signal
-- OUTPUTS
cw_to_ex => cw_to_ex_i, -- control word for ex stage
jump_address => jump_address_toex_i, -- jump address to ex stage
pc_4 => pc_4_to_ex_i,
read_data_1 => data_read_ex_1_i,
read_data_2 => data_read_ex_2_i,
immediate_ext => immediate_ext_ex_i,
immediate => immediate_ex_i,
rt => rt_ex_i,
rd => rd_ex_i,
rs => rs_ex_i
);
u_execute: execute
port map (
clk => clk,
rst => rst,
-- inputs from IDEX pipeline reg
controls_in => cw_to_ex_i, -- we have 22 signals: CU generates a total of 23 signals (including 5 ALUOP signals), but 1 signal (unsigned) already exhausted in the DECODE stage
ext25_0 => jump_address_toex_i, -- bits 25_0 of instr. sign/unsign extended to 32 bits
nextPC => pc_4_to_ex_i,
op_A => data_read_ex_1_i,
op_B => data_read_ex_2_i,
ext15_0 => immediate_ext_ex_i, -- bits 15_0 of instr. sign/unsign extended to 32 bits
inst15_0 => immediate_ex_i, -- bits 15_0 of instr.
rt_inst => rt_ex_i,
rd_inst => rd_ex_i,
rs_inst => rs_ex_i,
-- inputs from other sources
unaligned => unaligned_i, -- from MMU, '1' when an unaligned access to memory has been done
forw_dataWB => data_write_i, -- data from WB stage that used if forwarding needed
forw_dataMEM => forw_dataMEM_i, -- data from MEM stage that used if forwarding needed
RFaddr_WB => address_write_i, -- addr of RF from WB stage, goes to forwarding unit
RFaddr_MEM => RFaddr_MEM_i, -- addr of RF from MEM stage, goes to forwarding unit
regwriteWB => reg_write_i, -- reg_write ctrl signal from WB stage
regwriteMEM => regwriteMEM_i, -- reg_write ctrl signal from MEM stage
-- outputs
controls_out => cw_exmem_i, -- 11 control signals go to MEM stage (11 are exhausted in the EXE stage)
toPC1 => toPC1_i,
toPC2 => toPC2_i,
branchTaken => branchTaken_i,
addrMem => addrMem_exmem_i,
writeData => writeData_exmem_i,
addrRF => addrRF_exmem_i,
IDEX_rt => idex_rt_i, -- goes to hazard unit
IDEX_memread => idex_mem_read_i -- goes to hazard unit
);
u_exmemreg: EX_MEM_Reg port map (
-- input signals
clk => clk, -- clock source
rst => rst, -- reset signal
controls_in => cw_exmem_i, -- 11 control signals go from exe to mem stage
toPC1_in => toPC1_i, -- from jreg controlled mux
toPC2_in => toPC2_i, -- from adder2
takeBranch_in => branchTaken_i, -- from Branch circuit, if 1 branch must be taken (if inst. is a branch, see AND in MEM stage)
mem_addr_in => addrMem_exmem_i,
mem_writedata_in => writeData_exmem_i,
regfile_addr_in => addrRF_exmem_i,
-- output signals
controls_out => cw_tomem_i,
toPC1_out => PC1_tomem_i,
toPC2_out => PC2_tomem_i,
takeBranch_out => takeBranch_out_i,
mem_addr_out => mem_addr_out_i,
mem_writedata_out => mem_writedata_out_i,
regfile_addr_out => regfile_addr_out_tomem_i
);
u_memory: memory
port map (
-- inputs
rst => rst,
controls_in => cw_tomem_i,
PC1_in => PC1_tomem_i,
PC2_in => PC2_tomem_i,
takeBranch => takeBranch_out_i,
addrMem => mem_addr_out_i,
writeData => mem_writedata_out_i,
RFaddr_in => regfile_addr_out_tomem_i,
-- outputs
controls_out => cw_memwb_i,
dataOut_mem => dataOut_mem_i, -- data that has been read directly from memory
dataOut_exe => dataOut_exe_i, -- data that has been produced in exe stage
RFaddr_out => RFaddr_out_memwb_i,
unaligned => unaligned_i,
PCsrc => pcsrc_i,
flush => flush_i,
jump => jump_i,
PC1_out => jump_address_i,
PC2_out => branch_target_i,
regwrite_MEM => regwriteMEM_i, -- goes to forwarding unit
RFaddr_MEM => RFaddr_MEM_i, -- goes to forwarding unit
forw_addr_MEM => forw_dataMEM_i -- goes to EXE stage and used if forwarding detected by forwarding unit
);
u_memwbreg: MEM_WB_Reg port map (
clk => clk, -- clock source
rst => rst, -- reset signal
controls_in => cw_memwb_i, -- in order, from MSB to LSB : regwrite, link, memtoreg
from_mem_data_in => dataOut_mem_i,
from_alu_data_in => dataOut_exe_i,
regfile_addr_in => RFaddr_out_memwb_i,
-- output signals
controls_out => cw_towb_i,
from_mem_data_out => from_mem_data_out_i,
from_alu_data_out => from_alu_data_out_i,
regfile_addr_out => regfile_addr_out_towb_i
);
u_writeback: writeback
port map (
-- inputs
from_mem_data => from_mem_data_out_i,
from_alu_data => from_alu_data_out_i, -- named from_alu but data can come from other sources as well, but not from memory
regfile_addr_in => regfile_addr_out_towb_i, -- address of regter to write
regwrite_in => cw_towb_i(2), -- control signal (1 -> write in reg file)
link => cw_towb_i(1), -- control signal (1 -> link the instruction, save IP in R31)
memtoreg => cw_towb_i(0),
-- outputs
regwrite_out => reg_write_i, -- control signal (send regwrite signal back to other stages)
regfile_data => data_write_i,
regfile_addr_out => address_write_i
);
end struct;
|
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: MemoTableTOutput.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any Output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
use work.Constants.all;
use work.DefTypes.all;
ENTITY MemoTableTOutputWay IS
--ENTITY TraceMemory IS
PORT
(
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTOutputEntry;
--WData : IN STD_LOGIC_VECTOR (MemoTableTOutputEntryWidth-1 DOWNTO 0);
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTOutputEntry
--RData : OUT STD_LOGIC_VECTOR (MemoTableTOutputEntryWidth-1 DOWNTO 0)
);
END MemoTableTOutputWay;
--END TraceMemory;
ARCHITECTURE SYN OF MemoTableTOutputWay IS
--ARCHITECTURE SYN OF TraceMemory IS
SIGNAL RAuxVector : STD_LOGIC_VECTOR (MemoTableTOutputEntryWidth-1 DOWNTO 0);
SIGNAL WAuxObject : MemoTableTOutputEntry;
SIGNAL WAuxVector : STD_LOGIC_VECTOR (MemoTableTOutputEntryWidth-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
clock0 : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (MemoTableTOutputEntryWidth-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (MemoTableTOutputEntryWidth-1 DOWNTO 0);
wren_a : IN STD_LOGIC;
address_b: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
--RData <= RAuxVector;
RData <= StdLogicToOutput(RAuxVector);
--WAuxVector <= WData;
WAuxObject <= WData;
WAuxVector <= OutputToStdLogic(WAuxObject);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => MemoTableTWayLenght,
numwords_b => MemoTableTWayLenght,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => MemoTableTWayAddressLenght,
widthad_b => MemoTableTWayAddressLenght,
width_a => MemoTableTOutputEntryWidth,
width_b => MemoTableTOutputEntryWidth,
width_byteena_a => 1
)
PORT MAP (
address_a => WAddress,
clock0 => Clock,
data_a => WAuxVector,
wren_a => WEnable,
address_b => RAddress,
q_b => RAuxVector
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_Output_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_Output_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_Output_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_Output_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[MemoTableTOutputEntryWidth-1..0]"
-- Retrieval info: USED_PORT: q 0 0 64 0 Output NODEFVAL "q[MemoTableTOutputEntryWidth-1..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL "rdaddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL "wraddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0
-- Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTOutput.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTOutput.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTOutput.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTOutput.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTOutput_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTOutput_syn.v TRUE
-- Retrieval info: LIB_FILE: altera_mf
|
library IEEE, STD;
use IEEE.std_logic_1164.all;
use STD.textio.all;
--------------------------------------------------------------------------------
package junit is
----------------------------------------------------------------------------
-- Procedure: JUnit XML Declaration
-- * Outputs the XML declaration header to JUNIT_FILE
----------------------------------------------------------------------------
procedure junit_xml_declaration (variable JUNIT_FILE : in text);
----------------------------------------------------------------------------
-- Procedure: JUnit Start Testsuites
-- * Opening <testsuites> tag
----------------------------------------------------------------------------
procedure junit_start_testsuites (
variable JUNIT_FILE : in text;
ID : in string;
NAME : in string;
TESTS : in natural;
FAILURES : in natural;
RUNTIME : in time
);
----------------------------------------------------------------------------
-- Procedure: JUnit End Testsuites
-- * Closing </testsuites> tag
----------------------------------------------------------------------------
procedure junit_end_testsuites (variable JUNIT_FILE : in text);
----------------------------------------------------------------------------
-- Procedure: JUnit Start Testsuite
-- * Opening <testsuite> tag
----------------------------------------------------------------------------
procedure junit_start_testsuite (
variable JUNIT_FILE : in text;
ID : in string;
NAME : in string;
TESTS : in natural;
FAILURES : in natural;
RUNTIME : in time
);
----------------------------------------------------------------------------
-- Procedure: JUnit End Testsuite
-- * Closing </testsuite> tag
----------------------------------------------------------------------------
procedure junit_end_testsuite (variable JUNIT_FILE : in text);
----------------------------------------------------------------------------
-- Procedure: JUnit Start Testcase
-- * Opening <testcase> tag
----------------------------------------------------------------------------
procedure junit_start_testcase (
variable JUNIT_FILE : in text;
ID : in string;
NAME : in string;
RUNTIME : in time
);
----------------------------------------------------------------------------
-- Procedure: JUnit Testcase
-- * Opening and closing <testcase> tags, with no content
----------------------------------------------------------------------------
procedure junit_testcase (
variable JUNIT_FILE : in text;
ID : in string;
NAME : in string;
RUNTIME : in time
);
----------------------------------------------------------------------------
-- Procedure: JUnit End Testcase
-- * Closing </testcase> tag
----------------------------------------------------------------------------
procedure junit_end_testcase (variable JUNIT_FILE : in text);
----------------------------------------------------------------------------
-- Procedure: JUnit Failure
-- * <failure> tag and body
----------------------------------------------------------------------------
procedure junit_failure (
variable JUNIT_FILE : in text;
MESSAGE : in string;
DETAIL : in string
);
----------------------------------------------------------------------------
-- Procedure: JUnit Error
-- * <error> tag and body
----------------------------------------------------------------------------
procedure junit_error (
variable JUNIT_FILE : in text;
MESSAGE : in string;
DETAIL : in string
);
----------------------------------------------------------------------------
-- Procedure: JUnit Skipped
-- * <skipped /> self-closing tag
----------------------------------------------------------------------------
procedure junit_skipped (variable JUNIT_FILE : in text);
----------------------------------------------------------------------------
-- Function: JUnit Time
-- * Converts simulation time to real seconds
----------------------------------------------------------------------------
function junit_time (RUNTIME : in time) return real;
end junit; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX
-- doesnt handle reassembly
-- checks and filters for IP protocol
-- checks and filters for IP addr
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Improved error handling
-- Revision 0.03 - Added handling of broadcast address
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IPv4_RX is
port (
-- IP Layer signals
ip_rx : out ipv4_rx_type;
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
-- system signals
clk : in std_logic; -- same clock used to clock mac data and ip data
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
rx_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC layer RX signals
mac_data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in std_logic; -- indicates data_in valid on clock
mac_data_in_last : in std_logic -- indicates last data in frame
);
end IPv4_RX;
architecture Behavioral of IPv4_RX is
type rx_state_type is (IDLE, ETH_HDR, IP_HDR, USER_DATA, WAIT_END, ERR);
type rx_event_type is (NO_EVENT, DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal src_ip : std_logic_vector (31 downto 0); -- src IP captured from input
signal dst_ip : std_logic_vector (23 downto 0); -- 1st 3 bytes of dst IP captured from input
signal is_broadcast_reg : std_logic;
signal protocol : std_logic_vector (7 downto 0); -- src protocol captured from input
signal data_len : std_logic_vector (15 downto 0); -- src data length captured from input
signal ip_rx_start_reg : std_logic; -- indicates start of user data
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
signal frame_err_cnt : unsigned (7 downto 0); -- number of frame errors
signal error_code_reg : std_logic_vector (3 downto 0);
signal rx_pkt_counter : unsigned (7 downto 0); -- number of rx frames received for us
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal set_dst_ip3 : std_logic;
signal set_dst_ip2 : std_logic;
signal set_dst_ip1 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
signal set_protocol : std_logic;
signal set_len_H : std_logic;
signal set_len_L : std_logic;
signal set_ip_rx_start : set_clr_type;
signal set_hdr_valid : set_clr_type;
signal set_frame_err_cnt : count_mode_type;
signal dataval : std_logic_vector (7 downto 0);
signal rx_count_val : unsigned (15 downto 0);
signal set_error_code : std_logic;
signal error_code_val : std_logic_vector (3 downto 0);
signal set_pkt_cnt : count_mode_type;
signal set_data_last : std_logic;
signal dst_ip_rx : std_logic_vector (31 downto 0);
signal set_is_broadcast : set_clr_type;
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- * - in 32 bit words
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
rx_combinatorial : process (
-- input signals
mac_data_in, mac_data_in_valid, mac_data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, src_ip, dst_ip, protocol, data_len, ip_rx_start_reg, hdr_valid_reg,
frame_err_cnt, error_code_reg, rx_pkt_counter, is_broadcast_reg,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode,
set_ip3, set_ip2, set_ip1, set_ip0, set_protocol, set_len_H, set_len_L,
set_dst_ip3, set_dst_ip2, set_dst_ip1,
set_ip_rx_start, set_hdr_valid, set_frame_err_cnt, dataval, rx_count_val,
set_error_code, error_code_val, set_pkt_cnt, set_data_last, dst_ip_rx, set_is_broadcast
)
begin
-- set output followers
ip_rx_start <= ip_rx_start_reg;
ip_rx.hdr.is_valid <= hdr_valid_reg;
ip_rx.hdr.protocol <= protocol;
ip_rx.hdr.data_length <= data_len;
ip_rx.hdr.src_ip_addr <= src_ip;
ip_rx.hdr.num_frame_errors <= std_logic_vector(frame_err_cnt);
ip_rx.hdr.last_error_code <= error_code_reg;
ip_rx.hdr.is_broadcast <= is_broadcast_reg;
rx_pkt_count <= std_logic_vector(rx_pkt_counter);
-- transfer data upstream if in user data phase
if rx_state = USER_DATA then
ip_rx.data.data_in <= mac_data_in;
ip_rx.data.data_in_valid <= mac_data_in_valid;
ip_rx.data.data_in_last <= set_data_last;
else
ip_rx.data.data_in <= (others => '0');
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
end if;
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
set_dst_ip3 <= '0';
set_dst_ip2 <= '0';
set_dst_ip1 <= '0';
set_protocol <= '0';
set_len_H <= '0';
set_len_L <= '0';
set_ip_rx_start <= HOLD;
set_hdr_valid <= HOLD;
set_frame_err_cnt <= HOLD;
rx_count_val <= x"0000";
set_error_code <= '0';
error_code_val <= RX_EC_NONE;
set_pkt_cnt <= HOLD;
dataval <= (others => '0');
set_data_last <= '0';
dst_ip_rx <= (others => '0');
set_is_broadcast <= HOLD;
-- determine event (if any)
if mac_data_in_valid = '1' then
rx_event <= DATA;
dataval <= mac_data_in;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
set_hdr_valid <= CLR;
next_rx_state <= ETH_HDR;
set_rx_state <= '1';
end case;
when ETH_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"000d" then
rx_count_mode <= RST;
next_rx_state <= IP_HDR;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_ETH;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
else
case rx_count is
when x"000c" =>
if mac_data_in /= x"08" then -- ignore pkts that are not type=IP
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"000d" =>
if mac_data_in /= x"00" then -- ignore pkts that are not type=IP
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when others => -- ignore other bytes in eth header
end case;
end if;
end case;
when IP_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"0013" then
rx_count_val <= x"0001"; -- start counter at 1
rx_count_mode <= SET_VAL;
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_IP;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
else
case rx_count is
when x"0000" =>
if mac_data_in /= x"45" then -- ignore pkts that are not v4 with 5 header words
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0002" => set_len_H <= '1';
when x"0003" => set_len_L <= '1';
when x"0006" =>
if (mac_data_in(7) = '1') or (mac_data_in (4 downto 0) /= "00000") then
-- ignore pkts that require reassembly (MF=1 or frag offst /= 0)
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0007" =>
if mac_data_in /= x"00" then -- ignore pkts that require reassembly (frag offst /= 0)
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0009" => set_protocol <= '1';
when x"000c" => set_ip3 <= '1';
when x"000d" => set_ip2 <= '1';
when x"000e" => set_ip1 <= '1';
when x"000f" => set_ip0 <= '1';
when x"0010" => set_dst_ip3 <= '1';
if ((mac_data_in /= our_ip_address(31 downto 24)) and
(mac_data_in /= IP_BC_ADDR(31 downto 24)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0011" => set_dst_ip2 <= '1';
if ((mac_data_in /= our_ip_address(23 downto 16)) and
(mac_data_in /= IP_BC_ADDR(23 downto 16)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0012" => set_dst_ip1 <= '1';
if ((mac_data_in /= our_ip_address(15 downto 8)) and
(mac_data_in /= IP_BC_ADDR(15 downto 8)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0013" =>
if ((mac_data_in /= our_ip_address(7 downto 0)) and
(mac_data_in /= IP_BC_ADDR(7 downto 0)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= USER_DATA;
set_pkt_cnt <= INCR; -- count another pkt
set_rx_state <= '1';
set_ip_rx_start <= SET;
end if;
-- now have the dst IP addr
dst_ip_rx <= dst_ip & mac_data_in;
if dst_ip_rx = IP_BC_ADDR then
set_is_broadcast <= SET;
else
set_is_broadcast <= CLR;
end if;
set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
--if dst_ip_rx = our_ip_address or dst_ip_rx = IP_BC_ADDR then
-- next_rx_state <= USER_DATA;
-- set_pkt_cnt <= INCR; -- count another pkt received
-- set_rx_state <= '1';
-- set_ip_rx_start <= SET;
--else
-- next_rx_state <= WAIT_END;
-- set_rx_state <= '1';
--end if;
when others => -- ignore other bytes in ip header
end case;
end if;
end case;
when USER_DATA =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
-- note: data gets transfered upstream as part of "output followers" processing
if rx_count = unsigned(data_len) then
set_ip_rx_start <= CLR;
rx_count_mode <= RST;
set_data_last <= '1';
if mac_data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_ip_rx_start <= CLR;
else
next_rx_state <= WAIT_END;
end if;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
-- check for early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_USER;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
end if;
end case;
when ERR =>
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
if mac_data_in_last = '0' then
set_data_last <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if mac_data_in_last = '1' then
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
set_ip_rx_start <= CLR;
end if;
end case;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
rx_sequential : process (clk)--, reset)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"0000";
src_ip <= (others => '0');
dst_ip <= (others => '0');
protocol <= (others => '0');
data_len <= (others => '0');
ip_rx_start_reg <= '0';
hdr_valid_reg <= '0';
is_broadcast_reg <= '0';
frame_err_cnt <= (others => '0');
error_code_reg <= RX_EC_NONE;
rx_pkt_counter <= x"00";
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST => rx_count <= x"0000";
when INCR => rx_count <= rx_count + 1;
when SET_VAL => rx_count <= rx_count_val;
when HOLD => rx_count <= rx_count;
end case;
-- frame error count processing
case set_frame_err_cnt is
when RST => frame_err_cnt <= x"00";
when INCR => frame_err_cnt <= frame_err_cnt + 1;
when HOLD => frame_err_cnt <= frame_err_cnt;
end case;
-- ip pkt processing
case set_pkt_cnt is
when RST => rx_pkt_counter <= x"00";
when INCR => rx_pkt_counter <= rx_pkt_counter + 1;
when HOLD => rx_pkt_counter <= rx_pkt_counter;
end case;
-- source ip capture
if (set_ip3 = '1') then src_ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then src_ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then src_ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then src_ip(7 downto 0) <= dataval; end if;
-- dst ip capture
if (set_dst_ip3 = '1') then dst_ip(23 downto 16) <= dataval; end if;
if (set_dst_ip2 = '1') then dst_ip(15 downto 8) <= dataval; end if;
if (set_dst_ip1 = '1') then dst_ip(7 downto 0) <= dataval; end if;
if (set_protocol = '1') then
protocol <= dataval;
else
protocol <= protocol;
end if;
if (set_len_H = '1') then
data_len (15 downto 8) <= dataval;
data_len (7 downto 0) <= x"00";
elsif (set_len_L = '1') then
-- compute data length, taking into account that we need to subtract the header length
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 20);
else
data_len <= data_len;
end if;
case set_ip_rx_start is
when SET => ip_rx_start_reg <= '1';
when CLR => ip_rx_start_reg <= '0';
when HOLD => ip_rx_start_reg <= ip_rx_start_reg;
end case;
case set_is_broadcast is
when SET => is_broadcast_reg <= '1';
when CLR => is_broadcast_reg <= '0';
when HOLD => is_broadcast_reg <= is_broadcast_reg;
end case;
case set_hdr_valid is
when SET => hdr_valid_reg <= '1';
when CLR => hdr_valid_reg <= '0';
when HOLD => hdr_valid_reg <= hdr_valid_reg;
end case;
-- set error code
if set_error_code = '1' then
error_code_reg <= error_code_val;
else
error_code_reg <= error_code_reg;
end if;
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX
-- doesnt handle reassembly
-- checks and filters for IP protocol
-- checks and filters for IP addr
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Improved error handling
-- Revision 0.03 - Added handling of broadcast address
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IPv4_RX is
port (
-- IP Layer signals
ip_rx : out ipv4_rx_type;
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
-- system signals
clk : in std_logic; -- same clock used to clock mac data and ip data
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
rx_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC layer RX signals
mac_data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in std_logic; -- indicates data_in valid on clock
mac_data_in_last : in std_logic -- indicates last data in frame
);
end IPv4_RX;
architecture Behavioral of IPv4_RX is
type rx_state_type is (IDLE, ETH_HDR, IP_HDR, USER_DATA, WAIT_END, ERR);
type rx_event_type is (NO_EVENT, DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal src_ip : std_logic_vector (31 downto 0); -- src IP captured from input
signal dst_ip : std_logic_vector (23 downto 0); -- 1st 3 bytes of dst IP captured from input
signal is_broadcast_reg : std_logic;
signal protocol : std_logic_vector (7 downto 0); -- src protocol captured from input
signal data_len : std_logic_vector (15 downto 0); -- src data length captured from input
signal ip_rx_start_reg : std_logic; -- indicates start of user data
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
signal frame_err_cnt : unsigned (7 downto 0); -- number of frame errors
signal error_code_reg : std_logic_vector (3 downto 0);
signal rx_pkt_counter : unsigned (7 downto 0); -- number of rx frames received for us
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal set_dst_ip3 : std_logic;
signal set_dst_ip2 : std_logic;
signal set_dst_ip1 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
signal set_protocol : std_logic;
signal set_len_H : std_logic;
signal set_len_L : std_logic;
signal set_ip_rx_start : set_clr_type;
signal set_hdr_valid : set_clr_type;
signal set_frame_err_cnt : count_mode_type;
signal dataval : std_logic_vector (7 downto 0);
signal rx_count_val : unsigned (15 downto 0);
signal set_error_code : std_logic;
signal error_code_val : std_logic_vector (3 downto 0);
signal set_pkt_cnt : count_mode_type;
signal set_data_last : std_logic;
signal dst_ip_rx : std_logic_vector (31 downto 0);
signal set_is_broadcast : set_clr_type;
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- * - in 32 bit words
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
rx_combinatorial : process (
-- input signals
mac_data_in, mac_data_in_valid, mac_data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, src_ip, dst_ip, protocol, data_len, ip_rx_start_reg, hdr_valid_reg,
frame_err_cnt, error_code_reg, rx_pkt_counter, is_broadcast_reg,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode,
set_ip3, set_ip2, set_ip1, set_ip0, set_protocol, set_len_H, set_len_L,
set_dst_ip3, set_dst_ip2, set_dst_ip1,
set_ip_rx_start, set_hdr_valid, set_frame_err_cnt, dataval, rx_count_val,
set_error_code, error_code_val, set_pkt_cnt, set_data_last, dst_ip_rx, set_is_broadcast
)
begin
-- set output followers
ip_rx_start <= ip_rx_start_reg;
ip_rx.hdr.is_valid <= hdr_valid_reg;
ip_rx.hdr.protocol <= protocol;
ip_rx.hdr.data_length <= data_len;
ip_rx.hdr.src_ip_addr <= src_ip;
ip_rx.hdr.num_frame_errors <= std_logic_vector(frame_err_cnt);
ip_rx.hdr.last_error_code <= error_code_reg;
ip_rx.hdr.is_broadcast <= is_broadcast_reg;
rx_pkt_count <= std_logic_vector(rx_pkt_counter);
-- transfer data upstream if in user data phase
if rx_state = USER_DATA then
ip_rx.data.data_in <= mac_data_in;
ip_rx.data.data_in_valid <= mac_data_in_valid;
ip_rx.data.data_in_last <= set_data_last;
else
ip_rx.data.data_in <= (others => '0');
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
end if;
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
set_dst_ip3 <= '0';
set_dst_ip2 <= '0';
set_dst_ip1 <= '0';
set_protocol <= '0';
set_len_H <= '0';
set_len_L <= '0';
set_ip_rx_start <= HOLD;
set_hdr_valid <= HOLD;
set_frame_err_cnt <= HOLD;
rx_count_val <= x"0000";
set_error_code <= '0';
error_code_val <= RX_EC_NONE;
set_pkt_cnt <= HOLD;
dataval <= (others => '0');
set_data_last <= '0';
dst_ip_rx <= (others => '0');
set_is_broadcast <= HOLD;
-- determine event (if any)
if mac_data_in_valid = '1' then
rx_event <= DATA;
dataval <= mac_data_in;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
set_hdr_valid <= CLR;
next_rx_state <= ETH_HDR;
set_rx_state <= '1';
end case;
when ETH_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"000d" then
rx_count_mode <= RST;
next_rx_state <= IP_HDR;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_ETH;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
else
case rx_count is
when x"000c" =>
if mac_data_in /= x"08" then -- ignore pkts that are not type=IP
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"000d" =>
if mac_data_in /= x"00" then -- ignore pkts that are not type=IP
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when others => -- ignore other bytes in eth header
end case;
end if;
end case;
when IP_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"0013" then
rx_count_val <= x"0001"; -- start counter at 1
rx_count_mode <= SET_VAL;
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_IP;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
else
case rx_count is
when x"0000" =>
if mac_data_in /= x"45" then -- ignore pkts that are not v4 with 5 header words
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0002" => set_len_H <= '1';
when x"0003" => set_len_L <= '1';
when x"0006" =>
if (mac_data_in(7) = '1') or (mac_data_in (4 downto 0) /= "00000") then
-- ignore pkts that require reassembly (MF=1 or frag offst /= 0)
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0007" =>
if mac_data_in /= x"00" then -- ignore pkts that require reassembly (frag offst /= 0)
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0009" => set_protocol <= '1';
when x"000c" => set_ip3 <= '1';
when x"000d" => set_ip2 <= '1';
when x"000e" => set_ip1 <= '1';
when x"000f" => set_ip0 <= '1';
when x"0010" => set_dst_ip3 <= '1';
if ((mac_data_in /= our_ip_address(31 downto 24)) and
(mac_data_in /= IP_BC_ADDR(31 downto 24)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0011" => set_dst_ip2 <= '1';
if ((mac_data_in /= our_ip_address(23 downto 16)) and
(mac_data_in /= IP_BC_ADDR(23 downto 16)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0012" => set_dst_ip1 <= '1';
if ((mac_data_in /= our_ip_address(15 downto 8)) and
(mac_data_in /= IP_BC_ADDR(15 downto 8)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0013" =>
if ((mac_data_in /= our_ip_address(7 downto 0)) and
(mac_data_in /= IP_BC_ADDR(7 downto 0)))then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= USER_DATA;
set_pkt_cnt <= INCR; -- count another pkt
set_rx_state <= '1';
set_ip_rx_start <= SET;
end if;
-- now have the dst IP addr
dst_ip_rx <= dst_ip & mac_data_in;
if dst_ip_rx = IP_BC_ADDR then
set_is_broadcast <= SET;
else
set_is_broadcast <= CLR;
end if;
set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
--if dst_ip_rx = our_ip_address or dst_ip_rx = IP_BC_ADDR then
-- next_rx_state <= USER_DATA;
-- set_pkt_cnt <= INCR; -- count another pkt received
-- set_rx_state <= '1';
-- set_ip_rx_start <= SET;
--else
-- next_rx_state <= WAIT_END;
-- set_rx_state <= '1';
--end if;
when others => -- ignore other bytes in ip header
end case;
end if;
end case;
when USER_DATA =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
-- note: data gets transfered upstream as part of "output followers" processing
if rx_count = unsigned(data_len) then
set_ip_rx_start <= CLR;
rx_count_mode <= RST;
set_data_last <= '1';
if mac_data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_ip_rx_start <= CLR;
else
next_rx_state <= WAIT_END;
end if;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
-- check for early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_USER;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
end if;
end case;
when ERR =>
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
if mac_data_in_last = '0' then
set_data_last <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if mac_data_in_last = '1' then
set_data_last <= '1';
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
set_ip_rx_start <= CLR;
end if;
end case;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
rx_sequential : process (clk)--, reset)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"0000";
src_ip <= (others => '0');
dst_ip <= (others => '0');
protocol <= (others => '0');
data_len <= (others => '0');
ip_rx_start_reg <= '0';
hdr_valid_reg <= '0';
is_broadcast_reg <= '0';
frame_err_cnt <= (others => '0');
error_code_reg <= RX_EC_NONE;
rx_pkt_counter <= x"00";
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST => rx_count <= x"0000";
when INCR => rx_count <= rx_count + 1;
when SET_VAL => rx_count <= rx_count_val;
when HOLD => rx_count <= rx_count;
end case;
-- frame error count processing
case set_frame_err_cnt is
when RST => frame_err_cnt <= x"00";
when INCR => frame_err_cnt <= frame_err_cnt + 1;
when HOLD => frame_err_cnt <= frame_err_cnt;
end case;
-- ip pkt processing
case set_pkt_cnt is
when RST => rx_pkt_counter <= x"00";
when INCR => rx_pkt_counter <= rx_pkt_counter + 1;
when HOLD => rx_pkt_counter <= rx_pkt_counter;
end case;
-- source ip capture
if (set_ip3 = '1') then src_ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then src_ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then src_ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then src_ip(7 downto 0) <= dataval; end if;
-- dst ip capture
if (set_dst_ip3 = '1') then dst_ip(23 downto 16) <= dataval; end if;
if (set_dst_ip2 = '1') then dst_ip(15 downto 8) <= dataval; end if;
if (set_dst_ip1 = '1') then dst_ip(7 downto 0) <= dataval; end if;
if (set_protocol = '1') then
protocol <= dataval;
else
protocol <= protocol;
end if;
if (set_len_H = '1') then
data_len (15 downto 8) <= dataval;
data_len (7 downto 0) <= x"00";
elsif (set_len_L = '1') then
-- compute data length, taking into account that we need to subtract the header length
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 20);
else
data_len <= data_len;
end if;
case set_ip_rx_start is
when SET => ip_rx_start_reg <= '1';
when CLR => ip_rx_start_reg <= '0';
when HOLD => ip_rx_start_reg <= ip_rx_start_reg;
end case;
case set_is_broadcast is
when SET => is_broadcast_reg <= '1';
when CLR => is_broadcast_reg <= '0';
when HOLD => is_broadcast_reg <= is_broadcast_reg;
end case;
case set_hdr_valid is
when SET => hdr_valid_reg <= '1';
when CLR => hdr_valid_reg <= '0';
when HOLD => hdr_valid_reg <= hdr_valid_reg;
end case;
-- set error code
if set_error_code = '1' then
error_code_reg <= error_code_val;
else
error_code_reg <= error_code_reg;
end if;
end if;
end if;
end process;
end Behavioral;
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