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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- zobrazi 4 hexa cislice (DATA) na 4 mistnem 7segmentovem displeji (SEGMENT, DP, DIGIT)
entity HEX2SEG is
port (
DATA : in STD_LOGIC_VECTOR (15 downto 0); -- vstupni data k zobrazeni (4 sestnactkove cislice)
CLK : in STD_LOGIC;
SEGMENT : out STD_LOGIC_VECTOR (6 downto 0); -- 7 segmentu displeje
DP : out STD_LOGIC; -- desetinna tecka
DIGIT : out STD_LOGIC_VECTOR (3 downto 0) -- 4 cifry displeje
);
end HEX2SEG;
architecture HEX2SEG_BODY of HEX2SEG is
constant PRESCALER_WIDTH : integer := 16;
signal PRESCALER : std_logic_vector (PRESCALER_WIDTH-1 downto 0);
signal SEL : std_logic_vector (1 downto 0);
signal HEX : std_logic_vector (3 downto 0);
begin
-- hodinovy kmitocet 50 MHz vydelime pomoci 16 bitoveho citace
-- tim ziskame obnovovaci kmitocet displeje
P_PRESCALER : process (CLK)
begin
if CLK = '1' and CLK'event then
PRESCALER <= PRESCALER + 1;
end if;
end process;
-- nejvyssi 2 bity citace slouzi k prepinani 4 cifer displeje
SEL <= PRESCALER(PRESCALER_WIDTH-1 downto PRESCALER_WIDTH-2);
-- binarni kod prevedeme do kodu 1 z N
-- cifra I je aktivni, jestlize DIGIT(I) = '0'
SEL_DIGIT : process (SEL)
begin
case SEL is
when "00" => DIGIT <= "1110"; -- 0. cifra
when "01" => DIGIT <= "1101"; -- 1. cifra
when "10" => DIGIT <= "1011"; -- 2. cifra
when others => DIGIT <= "0111"; -- 3. cifra
end case;
end process;
-- a zaroven vybereme prislusnou ctverici bitu (sestnactkovou cifru) k zobrazeni
SEL_INPUT : process (SEL, DATA)
begin
case SEL is
when "00" => HEX <= DATA( 3 downto 0); -- 0. sestnactkova cifra
when "01" => HEX <= DATA( 7 downto 4); -- 1. sestnactkova cifra
when "10" => HEX <= DATA(11 downto 8); -- 2. sestnactkova cifra
when others => HEX <= DATA(15 downto 12); -- 3. sestnactkova cifra
end case;
end process;
-- ctverici bitu (sestnactkovou cifru) prevedeme na sedmici segmentu
-- segement J sviti, pokud SEGMENT(J) = '0'
HEX_2_7SEG : process (HEX)
begin
case HEX is
-- -- abcdefg
when "0000" => SEGMENT <= "0000001"; -- 0
when "0001" => SEGMENT <= "1001111"; -- 1
when "0010" => SEGMENT <= "0010010"; -- 2
when "0011" => SEGMENT <= "0000110"; -- 3
when "0100" => SEGMENT <= "1001100"; -- 4
when "0101" => SEGMENT <= "0100100"; -- 5
when "0110" => SEGMENT <= "0100000"; -- 6
when "0111" => SEGMENT <= "0001111"; -- 7
when "1000" => SEGMENT <= "0000000"; -- 8
when "1001" => SEGMENT <= "0000100"; -- 9
when "1010" => SEGMENT <= "0001000"; -- A
when "1011" => SEGMENT <= "1100000"; -- b
when "1100" => SEGMENT <= "0110001"; -- C
when "1101" => SEGMENT <= "1000010"; -- d
when "1110" => SEGMENT <= "0110000"; -- E
when others => SEGMENT <= "0111000"; -- F
end case;
end process;
-- desetinna tecka bude stale zhasnuta
DP <= '1';
end HEX2SEG_BODY; |
library verilog;
use verilog.vl_types.all;
entity Counter16anDisplay_vlg_vec_tst is
end Counter16anDisplay_vlg_vec_tst;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity zmux is
end entity zmux;
library util; use util.stimulus_generators.all;
architecture test of zmux is
signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
signal functional_z, equivalent_z : bit;
begin
functional_mux : block is
port ( z : out bit );
port map ( z => functional_z );
begin
-- code from book
zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
d1 when sel1 = '0' and sel0 = '1' else
d2 when sel1 = '1' and sel0 = '0' else
d3 when sel1 = '1' and sel0 = '1';
-- end code from book
end block functional_mux;
--------------------------------------------------
equivalent_mux : block is
port ( z : out bit );
port map ( z => equivalent_z );
begin
-- code from book
zmux : process is
begin
if sel1 = '0' and sel0 = '0' then
z <= d0;
elsif sel1 = '0' and sel0 = '1' then
z <= d1;
elsif sel1 = '1' and sel0 = '0' then
z <= d2;
elsif sel1 = '1' and sel0 = '1' then
z <= d3;
end if;
wait on d0, d1, d2, d3, sel0, sel1;
end process zmux;
-- end code from book
end block equivalent_mux;
--------------------------------------------------
stimulus :
all_possible_values( bv(0) => sel0, bv(1) => sel1,
bv(2) => d0, bv(3) => d1,
bv(4) => d2, bv(5) => d3,
delay_between_values => 10 ns );
verifier :
assert functional_z = equivalent_z
report "Functional and equivalent models give different results";
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity zmux is
end entity zmux;
library util; use util.stimulus_generators.all;
architecture test of zmux is
signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
signal functional_z, equivalent_z : bit;
begin
functional_mux : block is
port ( z : out bit );
port map ( z => functional_z );
begin
-- code from book
zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
d1 when sel1 = '0' and sel0 = '1' else
d2 when sel1 = '1' and sel0 = '0' else
d3 when sel1 = '1' and sel0 = '1';
-- end code from book
end block functional_mux;
--------------------------------------------------
equivalent_mux : block is
port ( z : out bit );
port map ( z => equivalent_z );
begin
-- code from book
zmux : process is
begin
if sel1 = '0' and sel0 = '0' then
z <= d0;
elsif sel1 = '0' and sel0 = '1' then
z <= d1;
elsif sel1 = '1' and sel0 = '0' then
z <= d2;
elsif sel1 = '1' and sel0 = '1' then
z <= d3;
end if;
wait on d0, d1, d2, d3, sel0, sel1;
end process zmux;
-- end code from book
end block equivalent_mux;
--------------------------------------------------
stimulus :
all_possible_values( bv(0) => sel0, bv(1) => sel1,
bv(2) => d0, bv(3) => d1,
bv(4) => d2, bv(5) => d3,
delay_between_values => 10 ns );
verifier :
assert functional_z = equivalent_z
report "Functional and equivalent models give different results";
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity zmux is
end entity zmux;
library util; use util.stimulus_generators.all;
architecture test of zmux is
signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
signal functional_z, equivalent_z : bit;
begin
functional_mux : block is
port ( z : out bit );
port map ( z => functional_z );
begin
-- code from book
zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
d1 when sel1 = '0' and sel0 = '1' else
d2 when sel1 = '1' and sel0 = '0' else
d3 when sel1 = '1' and sel0 = '1';
-- end code from book
end block functional_mux;
--------------------------------------------------
equivalent_mux : block is
port ( z : out bit );
port map ( z => equivalent_z );
begin
-- code from book
zmux : process is
begin
if sel1 = '0' and sel0 = '0' then
z <= d0;
elsif sel1 = '0' and sel0 = '1' then
z <= d1;
elsif sel1 = '1' and sel0 = '0' then
z <= d2;
elsif sel1 = '1' and sel0 = '1' then
z <= d3;
end if;
wait on d0, d1, d2, d3, sel0, sel1;
end process zmux;
-- end code from book
end block equivalent_mux;
--------------------------------------------------
stimulus :
all_possible_values( bv(0) => sel0, bv(1) => sel1,
bv(2) => d0, bv(3) => d1,
bv(4) => d2, bv(5) => d3,
delay_between_values => 10 ns );
verifier :
assert functional_z = equivalent_z
report "Functional and equivalent models give different results";
end architecture test;
|
library verilog;
use verilog.vl_types.all;
entity ama_signed_extension_function is
generic(
representation : string := "UNSIGNED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_ext : vl_notype;
wdith_data_ext_msb: vl_notype
);
port(
data_in : in vl_logic_vector;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of representation : constant is 1;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_ext : constant is 3;
attribute mti_svvh_generic_type of wdith_data_ext_msb : constant is 3;
end ama_signed_extension_function;
|
library verilog;
use verilog.vl_types.all;
entity ama_signed_extension_function is
generic(
representation : string := "UNSIGNED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_ext : vl_notype;
wdith_data_ext_msb: vl_notype
);
port(
data_in : in vl_logic_vector;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of representation : constant is 1;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_ext : constant is 3;
attribute mti_svvh_generic_type of wdith_data_ext_msb : constant is 3;
end ama_signed_extension_function;
|
library verilog;
use verilog.vl_types.all;
entity ama_signed_extension_function is
generic(
representation : string := "UNSIGNED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_ext : vl_notype;
wdith_data_ext_msb: vl_notype
);
port(
data_in : in vl_logic_vector;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of representation : constant is 1;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_ext : constant is 3;
attribute mti_svvh_generic_type of wdith_data_ext_msb : constant is 3;
end ama_signed_extension_function;
|
library verilog;
use verilog.vl_types.all;
entity ama_signed_extension_function is
generic(
representation : string := "UNSIGNED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_ext : vl_notype;
wdith_data_ext_msb: vl_notype
);
port(
data_in : in vl_logic_vector;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of representation : constant is 1;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_ext : constant is 3;
attribute mti_svvh_generic_type of wdith_data_ext_msb : constant is 3;
end ama_signed_extension_function;
|
library verilog;
use verilog.vl_types.all;
entity ama_signed_extension_function is
generic(
representation : string := "UNSIGNED";
width_data_in : integer := 1;
width_data_out : vl_notype;
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_ext : vl_notype;
wdith_data_ext_msb: vl_notype
);
port(
data_in : in vl_logic_vector;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of representation : constant is 1;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_ext : constant is 3;
attribute mti_svvh_generic_type of wdith_data_ext_msb : constant is 3;
end ama_signed_extension_function;
|
-----------------------------------------------------------------------------------------------------
-- Mux Stall
-- This mux is controlled by the Hazard Detection Unit. The control signal is mux_op, when asserted
-- the mux force a Control Word of a NOP (Control Word + ALU Opcode), otherwise the Control Word
-- produced by the CU passes.
-----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
entity mux_stall is
port (
-- INPUTS
cw_from_cu : in std_logic_vector((CW_SIZE + ALUOP_SIZE)-1 downto 0); -- control word produced by the CU
mux_op : in std_logic; -- control signal produced by the hazard detection unit
-- OUTPUTS
cw_from_mux : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0) -- control word produced by the mux
);
end mux_stall;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
architecture behavioral of mux_stall is
begin
cw_from_mux <= (others => '0') when (mux_op = '1') else cw_from_cu;
end behavioral;
|
-----------------------------------------------------------------------------------------------------
-- Mux Stall
-- This mux is controlled by the Hazard Detection Unit. The control signal is mux_op, when asserted
-- the mux force a Control Word of a NOP (Control Word + ALU Opcode), otherwise the Control Word
-- produced by the CU passes.
-----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
entity mux_stall is
port (
-- INPUTS
cw_from_cu : in std_logic_vector((CW_SIZE + ALUOP_SIZE)-1 downto 0); -- control word produced by the CU
mux_op : in std_logic; -- control signal produced by the hazard detection unit
-- OUTPUTS
cw_from_mux : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0) -- control word produced by the mux
);
end mux_stall;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
architecture behavioral of mux_stall is
begin
cw_from_mux <= (others => '0') when (mux_op = '1') else cw_from_cu;
end behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_k1_k4_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_k1_k4_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_k1_k4_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_k1_k4_e
--
architecture rtl of inst_k1_k4_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library OSVVM;
entity e is
end entity;
architecture a of e is
subtype T_DATA is std_logic_vector(31 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
type T_SCOREBOARD_DATA is record
IsKey : std_logic;
Meta : std_logic_vector(31 downto 0);
Data : T_DATA_VECTOR(15 downto 0);
end record;
function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean is
begin
return TRUE;
end function;
function to_string(vector : T_SCOREBOARD_DATA) return string is
begin
return "to_string";
end function;
package P_Scoreboard is new OSVVM.ScoreboardGenericPkg
generic map (
ExpectedType => T_SCOREBOARD_DATA,
ActualType => T_SCOREBOARD_DATA,
Match => match,
expected_to_string => to_string,
actual_to_string => to_string
);
alias T_SCOREBOARD is P_Scoreboard.ScoreBoardPType
shared variable ScoreBoard : T_SCOREBOARD; -- this causes the error message
begin
process
variable v : t_scoreboard_data;
begin
ScoreBoard.Push(v);
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library OSVVM;
entity e is
end entity;
architecture a of e is
subtype T_DATA is std_logic_vector(31 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
type T_SCOREBOARD_DATA is record
IsKey : std_logic;
Meta : std_logic_vector(31 downto 0);
Data : T_DATA_VECTOR(15 downto 0);
end record;
function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean is
begin
return TRUE;
end function;
function to_string(vector : T_SCOREBOARD_DATA) return string is
begin
return "to_string";
end function;
package P_Scoreboard is new OSVVM.ScoreboardGenericPkg
generic map (
ExpectedType => T_SCOREBOARD_DATA,
ActualType => T_SCOREBOARD_DATA,
Match => match,
expected_to_string => to_string,
actual_to_string => to_string
);
alias T_SCOREBOARD is P_Scoreboard.ScoreBoardPType
shared variable ScoreBoard : T_SCOREBOARD; -- this causes the error message
begin
process
variable v : t_scoreboard_data;
begin
ScoreBoard.Push(v);
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3175.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p27n01i03175ent IS
END c14s01b00x00p27n01i03175ent;
ARCHITECTURE c14s01b00x00p27n01i03175arch OF c14s01b00x00p27n01i03175ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'low = 0 and
roufbit'low = 0 )
report "***PASSED TEST: c14s01b00x00p27n01i03175"
severity NOTE;
assert ( fourbit'low = 0 and
roufbit'low = 0 )
report "***FAILED TEST: c14s01b00x00p27n01i03175 - Predefined attribute LOW for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p27n01i03175arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3175.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p27n01i03175ent IS
END c14s01b00x00p27n01i03175ent;
ARCHITECTURE c14s01b00x00p27n01i03175arch OF c14s01b00x00p27n01i03175ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'low = 0 and
roufbit'low = 0 )
report "***PASSED TEST: c14s01b00x00p27n01i03175"
severity NOTE;
assert ( fourbit'low = 0 and
roufbit'low = 0 )
report "***FAILED TEST: c14s01b00x00p27n01i03175 - Predefined attribute LOW for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p27n01i03175arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3175.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p27n01i03175ent IS
END c14s01b00x00p27n01i03175ent;
ARCHITECTURE c14s01b00x00p27n01i03175arch OF c14s01b00x00p27n01i03175ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'low = 0 and
roufbit'low = 0 )
report "***PASSED TEST: c14s01b00x00p27n01i03175"
severity NOTE;
assert ( fourbit'low = 0 and
roufbit'low = 0 )
report "***FAILED TEST: c14s01b00x00p27n01i03175 - Predefined attribute LOW for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p27n01i03175arch;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2012 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila.vhd
-- /___/ /\ Timestamp : Wed Dec 12 15:31:40 BRST 2012
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(31 downto 0);
TRIG1: in std_logic_vector(31 downto 0);
TRIG2: in std_logic_vector(31 downto 0);
TRIG3: in std_logic_vector(31 downto 0));
END chipscope_ila;
ARCHITECTURE chipscope_ila_a OF chipscope_ila IS
BEGIN
END chipscope_ila_a;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2012 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila.vhd
-- /___/ /\ Timestamp : Wed Dec 12 15:31:40 BRST 2012
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(31 downto 0);
TRIG1: in std_logic_vector(31 downto 0);
TRIG2: in std_logic_vector(31 downto 0);
TRIG3: in std_logic_vector(31 downto 0));
END chipscope_ila;
ARCHITECTURE chipscope_ila_a OF chipscope_ila IS
BEGIN
END chipscope_ila_a;
|
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0_cmd_demux is
port(
sink_valid : in vl_logic_vector(0 downto 0);
sink_data : in vl_logic_vector(104 downto 0);
sink_channel : in vl_logic_vector(5 downto 0);
sink_startofpacket: in vl_logic;
sink_endofpacket: in vl_logic;
sink_ready : out vl_logic;
src0_valid : out vl_logic;
src0_data : out vl_logic_vector(104 downto 0);
src0_channel : out vl_logic_vector(5 downto 0);
src0_startofpacket: out vl_logic;
src0_endofpacket: out vl_logic;
src0_ready : in vl_logic;
src1_valid : out vl_logic;
src1_data : out vl_logic_vector(104 downto 0);
src1_channel : out vl_logic_vector(5 downto 0);
src1_startofpacket: out vl_logic;
src1_endofpacket: out vl_logic;
src1_ready : in vl_logic;
src2_valid : out vl_logic;
src2_data : out vl_logic_vector(104 downto 0);
src2_channel : out vl_logic_vector(5 downto 0);
src2_startofpacket: out vl_logic;
src2_endofpacket: out vl_logic;
src2_ready : in vl_logic;
src3_valid : out vl_logic;
src3_data : out vl_logic_vector(104 downto 0);
src3_channel : out vl_logic_vector(5 downto 0);
src3_startofpacket: out vl_logic;
src3_endofpacket: out vl_logic;
src3_ready : in vl_logic;
src4_valid : out vl_logic;
src4_data : out vl_logic_vector(104 downto 0);
src4_channel : out vl_logic_vector(5 downto 0);
src4_startofpacket: out vl_logic;
src4_endofpacket: out vl_logic;
src4_ready : in vl_logic;
src5_valid : out vl_logic;
src5_data : out vl_logic_vector(104 downto 0);
src5_channel : out vl_logic_vector(5 downto 0);
src5_startofpacket: out vl_logic;
src5_endofpacket: out vl_logic;
src5_ready : in vl_logic;
clk : in vl_logic;
reset : in vl_logic
);
end usb_system_mm_interconnect_0_cmd_demux;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity mux19x1 is
port (H1, T1, U1, H2, T2, U2, H3, T3, U3, CTRL1, CTRL2, CTRL3: in std_logic_vector(7 downto 0);
mais, menos, vezes, barra, igual, dois, CTRLf: in std_logic_vector(7 downto 0);
s: in std_logic_vector(4 downto 0);
m: out std_logic_vector(7 downto 0)
);
end mux19x1;
architecture mux_estr of mux19x1 is
begin
m <= H1 when s = "00000" else
T1 when s = "00001" else
U1 when s = "00010" else
H2 when s = "00011" else
T2 when s = "00100" else
U2 when s = "00101" else
H3 when s = "00110" else
T3 when s = "00111" else
U3 when s = "01000" else
CTRL1 when s = "01001" else
CTRL2 when s = "01010" else
CTRL3 when s = "01011" else
mais when s = "01100" else
menos when s = "01101" else
vezes when s = "01110" else
barra when s = "01111" else
igual when s = "10000" else
dois when s = "10001" else
CTRLf;
end mux_estr; |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_rom0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_rom0;
ARCHITECTURE SYN OF lpm_rom0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "charmap.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 10,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "charmap.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "charmap.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_rom0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_rom0;
ARCHITECTURE SYN OF lpm_rom0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "charmap.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 10,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "charmap.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "charmap.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_rom0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_rom0;
ARCHITECTURE SYN OF lpm_rom0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "charmap.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 10,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "charmap.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "charmap.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_rom0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_rom0;
ARCHITECTURE SYN OF lpm_rom0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "charmap.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 10,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "charmap.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "charmap.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
entity test is
end test;
architecture only of test is
type int_array is array (3 downto 0) of integer;
begin -- only
p: process
variable w, x, y, z : integer := 0;
variable q : int_array := (3, 2, 1, 0);
begin -- process p
(w, x, y, z) := q;
assert w = 3 report "TEST FAILED" severity FAILURE;
assert x = 2 report "TEST FAILED" severity FAILURE;
assert y = 1 report "TEST FAILED" severity FAILURE;
assert z = 0 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type int_array is array (3 downto 0) of integer;
begin -- only
p: process
variable w, x, y, z : integer := 0;
variable q : int_array := (3, 2, 1, 0);
begin -- process p
(w, x, y, z) := q;
assert w = 3 report "TEST FAILED" severity FAILURE;
assert x = 2 report "TEST FAILED" severity FAILURE;
assert y = 1 report "TEST FAILED" severity FAILURE;
assert z = 0 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type int_array is array (3 downto 0) of integer;
begin -- only
p: process
variable w, x, y, z : integer := 0;
variable q : int_array := (3, 2, 1, 0);
begin -- process p
(w, x, y, z) := q;
assert w = 3 report "TEST FAILED" severity FAILURE;
assert x = 2 report "TEST FAILED" severity FAILURE;
assert y = 1 report "TEST FAILED" severity FAILURE;
assert z = 0 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity tb_assert2 is
end tb_assert2;
architecture behav of tb_assert2 is
signal v, res : natural;
signal en : boolean := false;
begin
dut: entity work.assert2
port map (v, en, res);
process
begin
en <= True;
v <= 2;
wait for 1 ns;
assert res = 3 severity failure;
v <= 11;
en <= False;
wait for 1 ns;
assert res = 0 severity failure;
-- wait for 10 ns;
-- en <= True;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity add32_tb is
end add32_tb;
architecture TB of add32_tb is
component add32
port(
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0);
cin : in std_logic;
cout : out std_logic;
sum : out std_logic_vector(31 downto 0)
);
end component;
signal in1 : std_logic_vector(31 downto 0);
signal in0 : std_logic_vector(31 downto 0);
signal sum : std_logic_vector(31 downto 0);
signal cin : std_logic;
signal cout : std_logic;
begin -- TB
UUT: entity work.add32
port map(
in1 => in1,
in0 => in0,
cin => cin,
cout => cout,
sum => sum
);
process
begin
-- test two positive numbers
cin <= '0';
in1 <= conv_std_logic_vector(1234, in1'length);
in0 <= conv_std_logic_vector(4321, in0'length);
wait for 20 ns;
-- test 2 negatve nums
in1 <= conv_std_logic_vector(-500, in1'length);
in0 <= conv_std_logic_vector(-250, in0'length);
wait for 20 ns;
--test one + and one -
in1 <= conv_std_logic_vector(2048, in1'length);
in0 <= conv_std_logic_vector(-1000, in0'length);
wait for 20 ns;
-- oth unsigned
in1 <= conv_std_logic_vector(5000, in1'length);
in0 <= conv_std_logic_vector(1000, in0'length);
wait for 20 ns;
-- oth FFFF
in1 <= x"FFFFFFFF";
in0 <= x"FFFFFFFF";
wait for 20 ns;
--oth are 0
in1 <= x"00000000";
in0 <= x"00000000";
wait for 20 ns;
-- oth are 80 80
in1 <= x"80000000";
in0 <= x"80000000";
wait for 20 ns;
wait;
end process;
end TB;
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library misclib;
use misclib.types_misc.all;
entity axi4_gptimers is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
tmr_total : integer := 2
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_pwm : out std_logic_vector(tmr_total-1 downto 0);
o_irq : out std_logic
);
end;
architecture arch_axi4_gptimers of axi4_gptimers is
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(xirq, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_GPTIMERS
);
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
type timer_type is record
count_ena : std_logic;
irq_ena : std_logic;
pwm_ena : std_logic;
pwm_polarity : std_logic;
value : std_logic_vector(63 downto 0);
init_value : std_logic_vector(63 downto 0);
pwm_threshold : std_logic_vector(63 downto 0);
end record;
constant timer_type_reset : timer_type :=
('0', '0',
'0', '0',
(others => '0'),
(others => '0'),
(others => '0'));
type vector_timer_type is array (0 to tmr_total-1) of timer_type;
type registers is record
tmr : vector_timer_type;
highcnt : std_logic_vector(63 downto 0);
pending : std_logic_vector(tmr_total-1 downto 0);
pwm : std_logic_vector(tmr_total-1 downto 0);
raddr : global_addr_array_type;
end record;
constant R_RESET : registers := (
(others => timer_type_reset), (others => '0'), (others => '0'),
(others => '0'), ((others => '0'), (others => '0'))
);
signal r, rin : registers;
signal wb_dev_rdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
signal wb_bus_raddr : global_addr_array_type;
signal w_bus_re : std_logic;
signal wb_bus_waddr : global_addr_array_type;
signal w_bus_we : std_logic;
signal wb_bus_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
signal wb_bus_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
begin
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i_axi,
o_xslvo => o_axi,
i_ready => '1',
i_rdata => wb_dev_rdata,
o_re => w_bus_re,
o_r32 => open,
o_radr => wb_bus_raddr,
o_wadr => wb_bus_waddr,
o_we => w_bus_we,
o_wstrb => wb_bus_wstrb,
o_wdata => wb_bus_wdata
);
comblogic : process(nrst, r, w_bus_re, wb_bus_raddr, wb_bus_waddr,
w_bus_we, wb_bus_wstrb, wb_bus_wdata)
variable v : registers;
variable raddr : integer;
variable waddr : integer;
variable vrdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable irq_ena : std_logic;
begin
v := r;
v.raddr := wb_bus_raddr;
v.highcnt := r.highcnt + 1;
irq_ena := '0';
for n in 0 to tmr_total-1 loop
if r.tmr(n).count_ena = '1' then
if r.tmr(n).pwm_ena = '1' and r.tmr(n).value = r.tmr(n).pwm_threshold then
v.pwm(n) := not r.pwm(n);
end if;
if r.tmr(n).value = zero64 then
irq_ena := irq_ena or r.tmr(n).irq_ena;
v.pending(n) := r.tmr(n).irq_ena;
v.pwm(n) := r.tmr(n).pwm_polarity;
v.tmr(n).value := r.tmr(n).init_value;
else
v.tmr(n).value := r.tmr(n).value - 1;
end if;
else
v.tmr(n).value := r.tmr(n).init_value;
v.pwm(n) := r.tmr(n).pwm_polarity;
end if;
end loop;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
tmp := (others => '0');
raddr := conv_integer(r.raddr(n)(11 downto 2));
case raddr is
when 0 =>
tmp := r.highcnt(31 downto 0);
when 1 =>
tmp := r.highcnt(63 downto 32);
when 2 =>
tmp(tmr_total-1 downto 0) := r.pending;
when 3 =>
tmp(tmr_total-1 downto 0) := r.pwm;
when others =>
for k in 0 to tmr_total-1 loop
if raddr = (16 + 8*k) then
tmp(0) := r.tmr(k).count_ena;
tmp(1) := r.tmr(k).irq_ena;
tmp(4) := r.tmr(k).pwm_ena;
tmp(5) := r.tmr(k).pwm_polarity;
elsif raddr = (16 + 8*k + 2) then
tmp := r.tmr(k).value(31 downto 0);
elsif raddr = (16 + 8*k + 3) then
tmp := r.tmr(k).value(63 downto 32);
elsif raddr = (16 + 8*k + 4) then
tmp := r.tmr(k).init_value(31 downto 0);
elsif raddr = (16 + 8*k + 5) then
tmp := r.tmr(k).init_value(63 downto 32);
elsif raddr = (16 + 8*k + 6) then
tmp := r.tmr(k).pwm_threshold(31 downto 0);
elsif raddr = (16 + 8*k + 7) then
tmp := r.tmr(k).pwm_threshold(63 downto 32);
end if;
end loop;
end case;
vrdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if w_bus_we = '1' then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
if conv_integer(wb_bus_wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n)) /= 0 then
tmp := wb_bus_wdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n);
waddr := conv_integer(wb_bus_waddr(n)(11 downto 2));
case waddr is
when 2 =>
v.pending := tmp(tmr_total-1 downto 0);
when others =>
for k in 0 to tmr_total-1 loop
if waddr = (16 + 8*k) then
v.tmr(k).count_ena := tmp(0);
v.tmr(k).irq_ena := tmp(1);
v.tmr(k).pwm_ena := tmp(4);
v.tmr(k).pwm_polarity := tmp(5);
elsif waddr = (16 + 8*k + 2) then
v.tmr(k).value(31 downto 0) := tmp;
elsif waddr = (16 + 8*k + 3) then
v.tmr(k).value(63 downto 32) := tmp;
elsif waddr = (16 + 8*k + 4) then
v.tmr(k).init_value(31 downto 0) := tmp;
elsif waddr = (16 + 8*k + 5) then
v.tmr(k).init_value(63 downto 32) := tmp;
elsif waddr = (16 + 8*k + 6) then
v.tmr(k).pwm_threshold(31 downto 0) := tmp;
elsif waddr = (16 + 8*k + 7) then
v.tmr(k).pwm_threshold(63 downto 32) := tmp;
end if;
end loop;
end case;
end if;
end loop;
end if;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
rin <= v;
o_irq <= irq_ena;
o_pwm <= r.pwm;
wb_dev_rdata <= vrdata;
end process;
cfg <= xconfig;
-- registers:
regs : process(clk, nrst)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Yuan Mei
--
-- Create Date: 12/13/2013 07:56:40 PM
-- Design Name:
-- Module Name: global_clock_reset - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- This module encapsulates the main clock generation and its proepr resetting.
-- It also provides a global reset signal output upon stable clock's pll lock.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY global_clock_reset IS
PORT (
SYS_CLK_P : IN std_logic;
SYS_CLK_N : IN std_logic;
FORCE_RST : IN std_logic;
-- output
GLOBAL_RST : OUT std_logic;
SYS_CLK : OUT std_logic;
LOCKED : OUT std_logic;
CLK_OUT1 : OUT std_logic;
CLK_OUT2 : OUT std_logic;
CLK_OUT3 : OUT std_logic;
CLK_OUT4 : OUT std_logic
);
END global_clock_reset;
ARCHITECTURE Behavioral OF global_clock_reset IS
COMPONENT clockwiz
PORT (
-- Clock in ports
clk_in1 : IN std_logic;
-- Clock out ports
clk_out1 : OUT std_logic;
clk_out2 : OUT std_logic;
clk_out3 : OUT std_logic;
clk_out4 : OUT std_logic;
-- Status and control signals
reset : IN std_logic;
locked : OUT std_logic
);
END COMPONENT;
COMPONENT GlobalResetter
PORT (
FORCE_RST : IN std_logic;
CLK : IN std_logic; -- system clock
DCM_LOCKED : IN std_logic;
CLK_RST : OUT std_logic;
GLOBAL_RST : OUT std_logic
);
END COMPONENT;
-- Signals
SIGNAL sys_clk_i : std_logic;
SIGNAL dcm_locked : std_logic;
SIGNAL dcm_reset : std_logic;
BEGIN
IBUFDS_inst : IBUFDS
GENERIC MAP (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
PORT MAP (
O => sys_clk_i, -- Buffer output
I => SYS_CLK_P, -- Diff_p buffer input (connect directly to top-level port)
IB => SYS_CLK_N -- Diff_n buffer input (connect directly to top-level port)
);
BUFG_inst : BUFG
PORT MAP (
I => sys_clk_i,
O => sys_clk
);
--sys_clk <= sys_clk_i;
clockwiz_inst : clockwiz
PORT MAP (
-- Clock in ports
clk_in1 => sys_clk_i,
-- Clock out ports
clk_out1 => CLK_OUT1,
clk_out2 => CLK_OUT2,
clk_out3 => CLK_OUT3,
clk_out4 => CLK_OUT4,
-- Status and control signals
reset => dcm_reset,
locked => dcm_locked
);
globalresetter_inst : GlobalResetter
PORT MAP (
FORCE_RST => FORCE_RST,
CLK => sys_clk_i,
DCM_LOCKED => dcm_locked,
CLK_RST => dcm_reset,
GLOBAL_RST => GLOBAL_RST
);
LOCKED <= dcm_locked;
END Behavioral;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 08-02-2016
-- Module Name: fulladdr.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity fulladdr is
port(a, b, c_in : in std_logic;
sum, c_out : out std_logic);
end entity fulladdr;
architecture arch_fulladdr of fulladdr is
begin
sum <= a xor b xor c_in;
c_out <= (a and b) or (a and c_in) or (b and c_in);
end architecture arch_fulladdr;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 08-02-2016
-- Module Name: fulladdr.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity fulladdr is
port(a, b, c_in : in std_logic;
sum, c_out : out std_logic);
end entity fulladdr;
architecture arch_fulladdr of fulladdr is
begin
sum <= a xor b xor c_in;
c_out <= (a and b) or (a and c_in) or (b and c_in);
end architecture arch_fulladdr;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/ball_pixel_1/ball_pixel_stub.vhdl
-- Design : ball_pixel
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ball_pixel is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end ball_pixel;
architecture stub of ball_pixel is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[11:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:31:20 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/ball_pixel_1/ball_pixel_stub.vhdl
-- Design : ball_pixel
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ball_pixel is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end ball_pixel;
architecture stub of ball_pixel is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[11:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_feature_transform is
generic (
NUM_FEATURES : integer := 64
);
port (
clk : in std_logic;
clk_x2 : in std_logic;
rst : in std_logic;
active : in std_logic;
vsync : in std_logic;
x_addr_0 : in std_logic_vector(9 downto 0);
y_addr_0 : in std_logic_vector(9 downto 0);
hessian_0 : in std_logic_vector(31 downto 0);
x_addr_1 : in std_logic_vector(9 downto 0);
y_addr_1 : in std_logic_vector(9 downto 0);
hessian_1 : in std_logic_vector(31 downto 0);
rot_m00 : out std_logic_vector(15 downto 0);
rot_m01 : out std_logic_vector(15 downto 0);
rot_m10 : out std_logic_vector(15 downto 0);
rot_m11 : out std_logic_vector(15 downto 0);
t_x : out std_logic_vector(9 downto 0);
t_y : out std_logic_vector(9 downto 0);
state : out std_logic_vector(1 downto 0)
);
end vga_feature_transform;
architecture Behavioral of vga_feature_transform is
component feature_buffer_block is
generic (
PARITY : std_logic := '0'
);
port (
clk_x2 : in std_logic;
enable : in std_logic;
clear : in std_logic;
x_in_left : in std_logic_vector(9 downto 0);
y_in_left : in std_logic_vector(9 downto 0);
hessian_in_left : in std_logic_vector(31 downto 0);
x_in_right : in std_logic_vector(9 downto 0);
y_in_right : in std_logic_vector(9 downto 0);
hessian_in_right : in std_logic_vector(31 downto 0);
x_out_left : out std_logic_vector(9 downto 0);
y_out_left : out std_logic_vector(9 downto 0);
hessian_out_left : out std_logic_vector(31 downto 0);
x_out_right : out std_logic_vector(9 downto 0);
y_out_right : out std_logic_vector(9 downto 0);
hessian_out_right : out std_logic_vector(31 downto 0)
);
end component;
type HESSIAN_ARRAY is array (NUM_FEATURES downto 0) of std_logic_vector(31 downto 0);
type POINT_ARRAY is array (NUM_FEATURES downto 0) of std_logic_vector(9 downto 0);
signal hessian_buffer_left_0 : HESSIAN_ARRAY;
signal hessian_buffer_right_0 : HESSIAN_ARRAY;
signal point_buffer_x_left_0 : POINT_ARRAY;
signal point_buffer_y_left_0 : POINT_ARRAY;
signal point_buffer_x_right_0 : POINT_ARRAY;
signal point_buffer_y_right_0 : POINT_ARRAY;
signal hessian_buffer_left_1 : HESSIAN_ARRAY;
signal hessian_buffer_right_1 : HESSIAN_ARRAY;
signal point_buffer_x_left_1 : POINT_ARRAY;
signal point_buffer_y_left_1 : POINT_ARRAY;
signal point_buffer_x_right_1 : POINT_ARRAY;
signal point_buffer_y_right_1 : POINT_ARRAY;
signal sort_enable : std_logic := '0';
signal clear : std_logic := '0';
signal sum_index : integer := 0;
signal state_s : std_logic_vector(1 downto 0) := "00";
signal sum_x_0, sum_x_1, sum_y_0, sum_y_1, center_x_0, center_x_1, center_y_0, center_y_1, t_xs, t_ys, last_t_xs, last_t_ys : unsigned(31 downto 0) := x"00000000";
signal ready : std_logic := '0';
begin
rot_m00 <= x"4000";
rot_m01 <= x"0000";
rot_m10 <= x"0000";
rot_m11 <= x"4000";
state <= state_s;
process(clk)
begin
if rising_edge(clk) then
if rst = '0' then
state_s <= "00";
clear <= '1';
ready <= '0';
sort_enable <= '0';
sum_x_0 <= x"00000000";
sum_y_0 <= x"00000000";
sum_x_1 <= x"00000000";
sum_y_1 <= x"00000000";
t_xs <= x"00000000";
t_ys <= x"00000000";
last_t_xs <= x"00000000";
last_t_ys <= x"00000000";
else
if state_s = "00" then
clear <= '0';
ready <= '0';
if vsync = '1' then
sort_enable <= '1';
if active = '1' and unsigned(x_addr_0) > 50 and unsigned(x_addr_0) < 590 and unsigned(y_addr_0) > 50 and unsigned(y_addr_0) < 430 then
hessian_buffer_left_0(0) <= hessian_0;
point_buffer_x_left_0(0) <= x_addr_0;
point_buffer_y_left_0(0) <= y_addr_0;
else
hessian_buffer_left_0(0) <= x"00000000";
point_buffer_x_left_0(0) <= "0000000000";
point_buffer_y_left_0(0) <= "0000000000";
end if;
if active = '1' and unsigned(x_addr_1) > 50 and unsigned(x_addr_1) < 590 and unsigned(y_addr_1) > 50 and unsigned(y_addr_1) < 430 then
hessian_buffer_left_1(0) <= hessian_1;
point_buffer_x_left_1(0) <= x_addr_1;
point_buffer_y_left_1(0) <= y_addr_1;
else
hessian_buffer_left_1(0) <= x"00000000";
point_buffer_x_left_1(0) <= "0000000000";
point_buffer_y_left_1(0) <= "0000000000";
end if;
else
state_s <= "01";
sort_enable <= '0';
sum_x_0 <= x"00000000";
sum_y_0 <= x"00000000";
sum_x_1 <= x"00000000";
sum_y_1 <= x"00000000";
sum_index <= 1;
end if;
elsif state_s = "01" then
if sum_index <= NUM_FEATURES then
sum_x_0 <= sum_x_0 + unsigned(point_buffer_x_left_0(sum_index));
sum_y_0 <= sum_y_0 + unsigned(point_buffer_y_left_0(sum_index));
sum_x_1 <= sum_x_1 + unsigned(point_buffer_x_left_1(sum_index));
sum_y_1 <= sum_y_1 + unsigned(point_buffer_y_left_1(sum_index));
sum_index <= sum_index + 1;
else
center_x_0 <= sum_x_0 srl 6;
center_y_0 <= sum_y_0 srl 6;
center_x_1 <= sum_x_1 srl 6;
center_y_1 <= sum_y_1 srl 6;
state_s <= "10";
end if;
elsif state_s = "10" then
t_xs <= (center_x_1 - center_x_0) + last_t_xs;
t_ys <= (center_y_1 - center_y_0) + last_t_ys;
state_s <= "11";
elsif state_s = "11" then
if vsync = '1' and ready = '1' then
last_t_xs <= t_xs;
last_t_ys <= t_ys;
t_x <= std_logic_vector(t_xs(9 downto 0));
t_y <= std_logic_vector(t_ys(9 downto 0));
clear <= '1';
state_s <= "00";
else
if vsync = '0' then
ready <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
GEN_FEATURE_BUFFER_0 : for i in 0 to NUM_FEATURES - 1 generate
U_EVEN : if i mod 2 = 0 generate
U: feature_buffer_block generic map (
PARITY => '0'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_0(i),
y_in_left => point_buffer_y_left_0(i),
hessian_in_left => hessian_buffer_left_0(i),
x_in_right => point_buffer_x_right_0(i+1),
y_in_right => point_buffer_y_right_0(i+1),
hessian_in_right => hessian_buffer_right_0(i+1),
x_out_left => point_buffer_x_left_0(i+1),
y_out_left => point_buffer_y_left_0(i+1),
hessian_out_left => hessian_buffer_left_0(i+1),
x_out_right => point_buffer_x_right_0(i),
y_out_right => point_buffer_y_right_0(i),
hessian_out_right => hessian_buffer_right_0(i)
);
end generate U_EVEN;
U_ODD : if i mod 2 = 1 generate
U: feature_buffer_block generic map (
PARITY => '1'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_0(i),
y_in_left => point_buffer_y_left_0(i),
hessian_in_left => hessian_buffer_left_0(i),
x_in_right => point_buffer_x_right_0(i+1),
y_in_right => point_buffer_y_right_0(i+1),
hessian_in_right => hessian_buffer_right_0(i+1),
x_out_left => point_buffer_x_left_0(i+1),
y_out_left => point_buffer_y_left_0(i+1),
hessian_out_left => hessian_buffer_left_0(i+1),
x_out_right => point_buffer_x_right_0(i),
y_out_right => point_buffer_y_right_0(i),
hessian_out_right => hessian_buffer_right_0(i)
);
end generate U_ODD;
end generate GEN_FEATURE_BUFFER_0;
GEN_FEATURE_BUFFER_1 : for i in 0 to NUM_FEATURES - 1 generate
U_EVEN : if i mod 2 = 0 generate
U: feature_buffer_block generic map (
PARITY => '0'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_1(i),
y_in_left => point_buffer_y_left_1(i),
hessian_in_left => hessian_buffer_left_1(i),
x_in_right => point_buffer_x_right_1(i+1),
y_in_right => point_buffer_y_right_1(i+1),
hessian_in_right => hessian_buffer_right_1(i+1),
x_out_left => point_buffer_x_left_1(i+1),
y_out_left => point_buffer_y_left_1(i+1),
hessian_out_left => hessian_buffer_left_1(i+1),
x_out_right => point_buffer_x_right_1(i),
y_out_right => point_buffer_y_right_1(i),
hessian_out_right => hessian_buffer_right_1(i)
);
end generate U_EVEN;
U_ODD : if i mod 2 = 1 generate
U: feature_buffer_block generic map (
PARITY => '1'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_1(i),
y_in_left => point_buffer_y_left_1(i),
hessian_in_left => hessian_buffer_left_1(i),
x_in_right => point_buffer_x_right_1(i+1),
y_in_right => point_buffer_y_right_1(i+1),
hessian_in_right => hessian_buffer_right_1(i+1),
x_out_left => point_buffer_x_left_1(i+1),
y_out_left => point_buffer_y_left_1(i+1),
hessian_out_left => hessian_buffer_left_1(i+1),
x_out_right => point_buffer_x_right_1(i),
y_out_right => point_buffer_y_right_1(i),
hessian_out_right => hessian_buffer_right_1(i)
);
end generate U_ODD;
end generate GEN_FEATURE_BUFFER_1;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_feature_transform is
generic (
NUM_FEATURES : integer := 64
);
port (
clk : in std_logic;
clk_x2 : in std_logic;
rst : in std_logic;
active : in std_logic;
vsync : in std_logic;
x_addr_0 : in std_logic_vector(9 downto 0);
y_addr_0 : in std_logic_vector(9 downto 0);
hessian_0 : in std_logic_vector(31 downto 0);
x_addr_1 : in std_logic_vector(9 downto 0);
y_addr_1 : in std_logic_vector(9 downto 0);
hessian_1 : in std_logic_vector(31 downto 0);
rot_m00 : out std_logic_vector(15 downto 0);
rot_m01 : out std_logic_vector(15 downto 0);
rot_m10 : out std_logic_vector(15 downto 0);
rot_m11 : out std_logic_vector(15 downto 0);
t_x : out std_logic_vector(9 downto 0);
t_y : out std_logic_vector(9 downto 0);
state : out std_logic_vector(1 downto 0)
);
end vga_feature_transform;
architecture Behavioral of vga_feature_transform is
component feature_buffer_block is
generic (
PARITY : std_logic := '0'
);
port (
clk_x2 : in std_logic;
enable : in std_logic;
clear : in std_logic;
x_in_left : in std_logic_vector(9 downto 0);
y_in_left : in std_logic_vector(9 downto 0);
hessian_in_left : in std_logic_vector(31 downto 0);
x_in_right : in std_logic_vector(9 downto 0);
y_in_right : in std_logic_vector(9 downto 0);
hessian_in_right : in std_logic_vector(31 downto 0);
x_out_left : out std_logic_vector(9 downto 0);
y_out_left : out std_logic_vector(9 downto 0);
hessian_out_left : out std_logic_vector(31 downto 0);
x_out_right : out std_logic_vector(9 downto 0);
y_out_right : out std_logic_vector(9 downto 0);
hessian_out_right : out std_logic_vector(31 downto 0)
);
end component;
type HESSIAN_ARRAY is array (NUM_FEATURES downto 0) of std_logic_vector(31 downto 0);
type POINT_ARRAY is array (NUM_FEATURES downto 0) of std_logic_vector(9 downto 0);
signal hessian_buffer_left_0 : HESSIAN_ARRAY;
signal hessian_buffer_right_0 : HESSIAN_ARRAY;
signal point_buffer_x_left_0 : POINT_ARRAY;
signal point_buffer_y_left_0 : POINT_ARRAY;
signal point_buffer_x_right_0 : POINT_ARRAY;
signal point_buffer_y_right_0 : POINT_ARRAY;
signal hessian_buffer_left_1 : HESSIAN_ARRAY;
signal hessian_buffer_right_1 : HESSIAN_ARRAY;
signal point_buffer_x_left_1 : POINT_ARRAY;
signal point_buffer_y_left_1 : POINT_ARRAY;
signal point_buffer_x_right_1 : POINT_ARRAY;
signal point_buffer_y_right_1 : POINT_ARRAY;
signal sort_enable : std_logic := '0';
signal clear : std_logic := '0';
signal sum_index : integer := 0;
signal state_s : std_logic_vector(1 downto 0) := "00";
signal sum_x_0, sum_x_1, sum_y_0, sum_y_1, center_x_0, center_x_1, center_y_0, center_y_1, t_xs, t_ys, last_t_xs, last_t_ys : unsigned(31 downto 0) := x"00000000";
signal ready : std_logic := '0';
begin
rot_m00 <= x"4000";
rot_m01 <= x"0000";
rot_m10 <= x"0000";
rot_m11 <= x"4000";
state <= state_s;
process(clk)
begin
if rising_edge(clk) then
if rst = '0' then
state_s <= "00";
clear <= '1';
ready <= '0';
sort_enable <= '0';
sum_x_0 <= x"00000000";
sum_y_0 <= x"00000000";
sum_x_1 <= x"00000000";
sum_y_1 <= x"00000000";
t_xs <= x"00000000";
t_ys <= x"00000000";
last_t_xs <= x"00000000";
last_t_ys <= x"00000000";
else
if state_s = "00" then
clear <= '0';
ready <= '0';
if vsync = '1' then
sort_enable <= '1';
if active = '1' and unsigned(x_addr_0) > 50 and unsigned(x_addr_0) < 590 and unsigned(y_addr_0) > 50 and unsigned(y_addr_0) < 430 then
hessian_buffer_left_0(0) <= hessian_0;
point_buffer_x_left_0(0) <= x_addr_0;
point_buffer_y_left_0(0) <= y_addr_0;
else
hessian_buffer_left_0(0) <= x"00000000";
point_buffer_x_left_0(0) <= "0000000000";
point_buffer_y_left_0(0) <= "0000000000";
end if;
if active = '1' and unsigned(x_addr_1) > 50 and unsigned(x_addr_1) < 590 and unsigned(y_addr_1) > 50 and unsigned(y_addr_1) < 430 then
hessian_buffer_left_1(0) <= hessian_1;
point_buffer_x_left_1(0) <= x_addr_1;
point_buffer_y_left_1(0) <= y_addr_1;
else
hessian_buffer_left_1(0) <= x"00000000";
point_buffer_x_left_1(0) <= "0000000000";
point_buffer_y_left_1(0) <= "0000000000";
end if;
else
state_s <= "01";
sort_enable <= '0';
sum_x_0 <= x"00000000";
sum_y_0 <= x"00000000";
sum_x_1 <= x"00000000";
sum_y_1 <= x"00000000";
sum_index <= 1;
end if;
elsif state_s = "01" then
if sum_index <= NUM_FEATURES then
sum_x_0 <= sum_x_0 + unsigned(point_buffer_x_left_0(sum_index));
sum_y_0 <= sum_y_0 + unsigned(point_buffer_y_left_0(sum_index));
sum_x_1 <= sum_x_1 + unsigned(point_buffer_x_left_1(sum_index));
sum_y_1 <= sum_y_1 + unsigned(point_buffer_y_left_1(sum_index));
sum_index <= sum_index + 1;
else
center_x_0 <= sum_x_0 srl 6;
center_y_0 <= sum_y_0 srl 6;
center_x_1 <= sum_x_1 srl 6;
center_y_1 <= sum_y_1 srl 6;
state_s <= "10";
end if;
elsif state_s = "10" then
t_xs <= (center_x_1 - center_x_0) + last_t_xs;
t_ys <= (center_y_1 - center_y_0) + last_t_ys;
state_s <= "11";
elsif state_s = "11" then
if vsync = '1' and ready = '1' then
last_t_xs <= t_xs;
last_t_ys <= t_ys;
t_x <= std_logic_vector(t_xs(9 downto 0));
t_y <= std_logic_vector(t_ys(9 downto 0));
clear <= '1';
state_s <= "00";
else
if vsync = '0' then
ready <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
GEN_FEATURE_BUFFER_0 : for i in 0 to NUM_FEATURES - 1 generate
U_EVEN : if i mod 2 = 0 generate
U: feature_buffer_block generic map (
PARITY => '0'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_0(i),
y_in_left => point_buffer_y_left_0(i),
hessian_in_left => hessian_buffer_left_0(i),
x_in_right => point_buffer_x_right_0(i+1),
y_in_right => point_buffer_y_right_0(i+1),
hessian_in_right => hessian_buffer_right_0(i+1),
x_out_left => point_buffer_x_left_0(i+1),
y_out_left => point_buffer_y_left_0(i+1),
hessian_out_left => hessian_buffer_left_0(i+1),
x_out_right => point_buffer_x_right_0(i),
y_out_right => point_buffer_y_right_0(i),
hessian_out_right => hessian_buffer_right_0(i)
);
end generate U_EVEN;
U_ODD : if i mod 2 = 1 generate
U: feature_buffer_block generic map (
PARITY => '1'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_0(i),
y_in_left => point_buffer_y_left_0(i),
hessian_in_left => hessian_buffer_left_0(i),
x_in_right => point_buffer_x_right_0(i+1),
y_in_right => point_buffer_y_right_0(i+1),
hessian_in_right => hessian_buffer_right_0(i+1),
x_out_left => point_buffer_x_left_0(i+1),
y_out_left => point_buffer_y_left_0(i+1),
hessian_out_left => hessian_buffer_left_0(i+1),
x_out_right => point_buffer_x_right_0(i),
y_out_right => point_buffer_y_right_0(i),
hessian_out_right => hessian_buffer_right_0(i)
);
end generate U_ODD;
end generate GEN_FEATURE_BUFFER_0;
GEN_FEATURE_BUFFER_1 : for i in 0 to NUM_FEATURES - 1 generate
U_EVEN : if i mod 2 = 0 generate
U: feature_buffer_block generic map (
PARITY => '0'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_1(i),
y_in_left => point_buffer_y_left_1(i),
hessian_in_left => hessian_buffer_left_1(i),
x_in_right => point_buffer_x_right_1(i+1),
y_in_right => point_buffer_y_right_1(i+1),
hessian_in_right => hessian_buffer_right_1(i+1),
x_out_left => point_buffer_x_left_1(i+1),
y_out_left => point_buffer_y_left_1(i+1),
hessian_out_left => hessian_buffer_left_1(i+1),
x_out_right => point_buffer_x_right_1(i),
y_out_right => point_buffer_y_right_1(i),
hessian_out_right => hessian_buffer_right_1(i)
);
end generate U_EVEN;
U_ODD : if i mod 2 = 1 generate
U: feature_buffer_block generic map (
PARITY => '1'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_1(i),
y_in_left => point_buffer_y_left_1(i),
hessian_in_left => hessian_buffer_left_1(i),
x_in_right => point_buffer_x_right_1(i+1),
y_in_right => point_buffer_y_right_1(i+1),
hessian_in_right => hessian_buffer_right_1(i+1),
x_out_left => point_buffer_x_left_1(i+1),
y_out_left => point_buffer_y_left_1(i+1),
hessian_out_left => hessian_buffer_left_1(i+1),
x_out_right => point_buffer_x_right_1(i),
y_out_right => point_buffer_y_right_1(i),
hessian_out_right => hessian_buffer_right_1(i)
);
end generate U_ODD;
end generate GEN_FEATURE_BUFFER_1;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_feature_transform is
generic (
NUM_FEATURES : integer := 64
);
port (
clk : in std_logic;
clk_x2 : in std_logic;
rst : in std_logic;
active : in std_logic;
vsync : in std_logic;
x_addr_0 : in std_logic_vector(9 downto 0);
y_addr_0 : in std_logic_vector(9 downto 0);
hessian_0 : in std_logic_vector(31 downto 0);
x_addr_1 : in std_logic_vector(9 downto 0);
y_addr_1 : in std_logic_vector(9 downto 0);
hessian_1 : in std_logic_vector(31 downto 0);
rot_m00 : out std_logic_vector(15 downto 0);
rot_m01 : out std_logic_vector(15 downto 0);
rot_m10 : out std_logic_vector(15 downto 0);
rot_m11 : out std_logic_vector(15 downto 0);
t_x : out std_logic_vector(9 downto 0);
t_y : out std_logic_vector(9 downto 0);
state : out std_logic_vector(1 downto 0)
);
end vga_feature_transform;
architecture Behavioral of vga_feature_transform is
component feature_buffer_block is
generic (
PARITY : std_logic := '0'
);
port (
clk_x2 : in std_logic;
enable : in std_logic;
clear : in std_logic;
x_in_left : in std_logic_vector(9 downto 0);
y_in_left : in std_logic_vector(9 downto 0);
hessian_in_left : in std_logic_vector(31 downto 0);
x_in_right : in std_logic_vector(9 downto 0);
y_in_right : in std_logic_vector(9 downto 0);
hessian_in_right : in std_logic_vector(31 downto 0);
x_out_left : out std_logic_vector(9 downto 0);
y_out_left : out std_logic_vector(9 downto 0);
hessian_out_left : out std_logic_vector(31 downto 0);
x_out_right : out std_logic_vector(9 downto 0);
y_out_right : out std_logic_vector(9 downto 0);
hessian_out_right : out std_logic_vector(31 downto 0)
);
end component;
type HESSIAN_ARRAY is array (NUM_FEATURES downto 0) of std_logic_vector(31 downto 0);
type POINT_ARRAY is array (NUM_FEATURES downto 0) of std_logic_vector(9 downto 0);
signal hessian_buffer_left_0 : HESSIAN_ARRAY;
signal hessian_buffer_right_0 : HESSIAN_ARRAY;
signal point_buffer_x_left_0 : POINT_ARRAY;
signal point_buffer_y_left_0 : POINT_ARRAY;
signal point_buffer_x_right_0 : POINT_ARRAY;
signal point_buffer_y_right_0 : POINT_ARRAY;
signal hessian_buffer_left_1 : HESSIAN_ARRAY;
signal hessian_buffer_right_1 : HESSIAN_ARRAY;
signal point_buffer_x_left_1 : POINT_ARRAY;
signal point_buffer_y_left_1 : POINT_ARRAY;
signal point_buffer_x_right_1 : POINT_ARRAY;
signal point_buffer_y_right_1 : POINT_ARRAY;
signal sort_enable : std_logic := '0';
signal clear : std_logic := '0';
signal sum_index : integer := 0;
signal state_s : std_logic_vector(1 downto 0) := "00";
signal sum_x_0, sum_x_1, sum_y_0, sum_y_1, center_x_0, center_x_1, center_y_0, center_y_1, t_xs, t_ys, last_t_xs, last_t_ys : unsigned(31 downto 0) := x"00000000";
signal ready : std_logic := '0';
begin
rot_m00 <= x"4000";
rot_m01 <= x"0000";
rot_m10 <= x"0000";
rot_m11 <= x"4000";
state <= state_s;
process(clk)
begin
if rising_edge(clk) then
if rst = '0' then
state_s <= "00";
clear <= '1';
ready <= '0';
sort_enable <= '0';
sum_x_0 <= x"00000000";
sum_y_0 <= x"00000000";
sum_x_1 <= x"00000000";
sum_y_1 <= x"00000000";
t_xs <= x"00000000";
t_ys <= x"00000000";
last_t_xs <= x"00000000";
last_t_ys <= x"00000000";
else
if state_s = "00" then
clear <= '0';
ready <= '0';
if vsync = '1' then
sort_enable <= '1';
if active = '1' and unsigned(x_addr_0) > 50 and unsigned(x_addr_0) < 590 and unsigned(y_addr_0) > 50 and unsigned(y_addr_0) < 430 then
hessian_buffer_left_0(0) <= hessian_0;
point_buffer_x_left_0(0) <= x_addr_0;
point_buffer_y_left_0(0) <= y_addr_0;
else
hessian_buffer_left_0(0) <= x"00000000";
point_buffer_x_left_0(0) <= "0000000000";
point_buffer_y_left_0(0) <= "0000000000";
end if;
if active = '1' and unsigned(x_addr_1) > 50 and unsigned(x_addr_1) < 590 and unsigned(y_addr_1) > 50 and unsigned(y_addr_1) < 430 then
hessian_buffer_left_1(0) <= hessian_1;
point_buffer_x_left_1(0) <= x_addr_1;
point_buffer_y_left_1(0) <= y_addr_1;
else
hessian_buffer_left_1(0) <= x"00000000";
point_buffer_x_left_1(0) <= "0000000000";
point_buffer_y_left_1(0) <= "0000000000";
end if;
else
state_s <= "01";
sort_enable <= '0';
sum_x_0 <= x"00000000";
sum_y_0 <= x"00000000";
sum_x_1 <= x"00000000";
sum_y_1 <= x"00000000";
sum_index <= 1;
end if;
elsif state_s = "01" then
if sum_index <= NUM_FEATURES then
sum_x_0 <= sum_x_0 + unsigned(point_buffer_x_left_0(sum_index));
sum_y_0 <= sum_y_0 + unsigned(point_buffer_y_left_0(sum_index));
sum_x_1 <= sum_x_1 + unsigned(point_buffer_x_left_1(sum_index));
sum_y_1 <= sum_y_1 + unsigned(point_buffer_y_left_1(sum_index));
sum_index <= sum_index + 1;
else
center_x_0 <= sum_x_0 srl 6;
center_y_0 <= sum_y_0 srl 6;
center_x_1 <= sum_x_1 srl 6;
center_y_1 <= sum_y_1 srl 6;
state_s <= "10";
end if;
elsif state_s = "10" then
t_xs <= (center_x_1 - center_x_0) + last_t_xs;
t_ys <= (center_y_1 - center_y_0) + last_t_ys;
state_s <= "11";
elsif state_s = "11" then
if vsync = '1' and ready = '1' then
last_t_xs <= t_xs;
last_t_ys <= t_ys;
t_x <= std_logic_vector(t_xs(9 downto 0));
t_y <= std_logic_vector(t_ys(9 downto 0));
clear <= '1';
state_s <= "00";
else
if vsync = '0' then
ready <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
GEN_FEATURE_BUFFER_0 : for i in 0 to NUM_FEATURES - 1 generate
U_EVEN : if i mod 2 = 0 generate
U: feature_buffer_block generic map (
PARITY => '0'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_0(i),
y_in_left => point_buffer_y_left_0(i),
hessian_in_left => hessian_buffer_left_0(i),
x_in_right => point_buffer_x_right_0(i+1),
y_in_right => point_buffer_y_right_0(i+1),
hessian_in_right => hessian_buffer_right_0(i+1),
x_out_left => point_buffer_x_left_0(i+1),
y_out_left => point_buffer_y_left_0(i+1),
hessian_out_left => hessian_buffer_left_0(i+1),
x_out_right => point_buffer_x_right_0(i),
y_out_right => point_buffer_y_right_0(i),
hessian_out_right => hessian_buffer_right_0(i)
);
end generate U_EVEN;
U_ODD : if i mod 2 = 1 generate
U: feature_buffer_block generic map (
PARITY => '1'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_0(i),
y_in_left => point_buffer_y_left_0(i),
hessian_in_left => hessian_buffer_left_0(i),
x_in_right => point_buffer_x_right_0(i+1),
y_in_right => point_buffer_y_right_0(i+1),
hessian_in_right => hessian_buffer_right_0(i+1),
x_out_left => point_buffer_x_left_0(i+1),
y_out_left => point_buffer_y_left_0(i+1),
hessian_out_left => hessian_buffer_left_0(i+1),
x_out_right => point_buffer_x_right_0(i),
y_out_right => point_buffer_y_right_0(i),
hessian_out_right => hessian_buffer_right_0(i)
);
end generate U_ODD;
end generate GEN_FEATURE_BUFFER_0;
GEN_FEATURE_BUFFER_1 : for i in 0 to NUM_FEATURES - 1 generate
U_EVEN : if i mod 2 = 0 generate
U: feature_buffer_block generic map (
PARITY => '0'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_1(i),
y_in_left => point_buffer_y_left_1(i),
hessian_in_left => hessian_buffer_left_1(i),
x_in_right => point_buffer_x_right_1(i+1),
y_in_right => point_buffer_y_right_1(i+1),
hessian_in_right => hessian_buffer_right_1(i+1),
x_out_left => point_buffer_x_left_1(i+1),
y_out_left => point_buffer_y_left_1(i+1),
hessian_out_left => hessian_buffer_left_1(i+1),
x_out_right => point_buffer_x_right_1(i),
y_out_right => point_buffer_y_right_1(i),
hessian_out_right => hessian_buffer_right_1(i)
);
end generate U_EVEN;
U_ODD : if i mod 2 = 1 generate
U: feature_buffer_block generic map (
PARITY => '1'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_1(i),
y_in_left => point_buffer_y_left_1(i),
hessian_in_left => hessian_buffer_left_1(i),
x_in_right => point_buffer_x_right_1(i+1),
y_in_right => point_buffer_y_right_1(i+1),
hessian_in_right => hessian_buffer_right_1(i+1),
x_out_left => point_buffer_x_left_1(i+1),
y_out_left => point_buffer_y_left_1(i+1),
hessian_out_left => hessian_buffer_left_1(i+1),
x_out_right => point_buffer_x_right_1(i),
y_out_right => point_buffer_y_right_1(i),
hessian_out_right => hessian_buffer_right_1(i)
);
end generate U_ODD;
end generate GEN_FEATURE_BUFFER_1;
end Behavioral;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_9;
USE proc_sys_reset_v5_0_9.proc_sys_reset;
ENTITY dma_loopback_rst_processing_system7_0_50M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END dma_loopback_rst_processing_system7_0_50M_0;
ARCHITECTURE dma_loopback_rst_processing_system7_0_50M_0_arch OF dma_loopback_rst_processing_system7_0_50M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dma_loopback_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END dma_loopback_rst_processing_system7_0_50M_0_arch;
|
component wasca is
port (
abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_slave_0_abus_read : in std_logic := 'X'; -- read
abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
abus_slave_0_abus_waitrequest : out std_logic; -- waitrequest
abus_slave_0_abus_interrupt : out std_logic; -- interrupt
abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
abus_slave_0_abus_direction : out std_logic; -- direction
abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_slave_0_abus_disableout : out std_logic; -- disableout
abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := 'X'; -- saturn_reset
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- ba
external_sdram_controller_wire_cas_n : out std_logic; -- cas_n
external_sdram_controller_wire_cke : out std_logic; -- cke
external_sdram_controller_wire_cs_n : out std_logic; -- cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
external_sdram_controller_wire_ras_n : out std_logic; -- ras_n
external_sdram_controller_wire_we_n : out std_logic; -- we_n
leds_conn_export : out std_logic_vector(3 downto 0); -- export
sdram_clkout_clk : out std_logic; -- clk
switches_conn_export : in std_logic_vector(2 downto 0) := (others => 'X'); -- export
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
u0 : component wasca
port map (
abus_slave_0_abus_address => CONNECTED_TO_abus_slave_0_abus_address, -- abus_slave_0_abus.address
abus_slave_0_abus_chipselect => CONNECTED_TO_abus_slave_0_abus_chipselect, -- .chipselect
abus_slave_0_abus_read => CONNECTED_TO_abus_slave_0_abus_read, -- .read
abus_slave_0_abus_write => CONNECTED_TO_abus_slave_0_abus_write, -- .write
abus_slave_0_abus_waitrequest => CONNECTED_TO_abus_slave_0_abus_waitrequest, -- .waitrequest
abus_slave_0_abus_interrupt => CONNECTED_TO_abus_slave_0_abus_interrupt, -- .interrupt
abus_slave_0_abus_addressdata => CONNECTED_TO_abus_slave_0_abus_addressdata, -- .addressdata
abus_slave_0_abus_direction => CONNECTED_TO_abus_slave_0_abus_direction, -- .direction
abus_slave_0_abus_muxing => CONNECTED_TO_abus_slave_0_abus_muxing, -- .muxing
abus_slave_0_abus_disableout => CONNECTED_TO_abus_slave_0_abus_disableout, -- .disableout
abus_slave_0_conduit_saturn_reset_saturn_reset => CONNECTED_TO_abus_slave_0_conduit_saturn_reset_saturn_reset, -- abus_slave_0_conduit_saturn_reset.saturn_reset
altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export => CONNECTED_TO_altpll_0_phasedone_conduit_export, -- altpll_0_phasedone_conduit.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
external_sdram_controller_wire_addr => CONNECTED_TO_external_sdram_controller_wire_addr, -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => CONNECTED_TO_external_sdram_controller_wire_ba, -- .ba
external_sdram_controller_wire_cas_n => CONNECTED_TO_external_sdram_controller_wire_cas_n, -- .cas_n
external_sdram_controller_wire_cke => CONNECTED_TO_external_sdram_controller_wire_cke, -- .cke
external_sdram_controller_wire_cs_n => CONNECTED_TO_external_sdram_controller_wire_cs_n, -- .cs_n
external_sdram_controller_wire_dq => CONNECTED_TO_external_sdram_controller_wire_dq, -- .dq
external_sdram_controller_wire_dqm => CONNECTED_TO_external_sdram_controller_wire_dqm, -- .dqm
external_sdram_controller_wire_ras_n => CONNECTED_TO_external_sdram_controller_wire_ras_n, -- .ras_n
external_sdram_controller_wire_we_n => CONNECTED_TO_external_sdram_controller_wire_we_n, -- .we_n
leds_conn_export => CONNECTED_TO_leds_conn_export, -- leds_conn.export
sdram_clkout_clk => CONNECTED_TO_sdram_clkout_clk, -- sdram_clkout.clk
switches_conn_export => CONNECTED_TO_switches_conn_export, -- switches_conn.export
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd
);
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use work.zyehw_pkg.all;
package lut_pkg is
subtype lut_t is bit_vector(63 downto 0);
type pe_lut_t is array (cgp_t'reverse_range) of lut_t;
type pe_lut_arr_t is array (0 to (rows-1), 0 to (columns-1)) of pe_lut_t;
-- these are random numbers because otherwise the synthesizer would
-- remove some of the PE items
constant dummy_pe_lut_arr: pe_lut_arr_t:= (
(
(
X"000000005851F42D",
X"40B18CCF4BB5F646",
X"4703312930705B04",
X"20FD5DB41A8B7F78",
X"502959D82B894868",
X"6C0356A708CDB7FF",
X"3477D43F70A3A52B",
X"28E4BAF17D8341FC"
),
(
X"0AE16FD9742D2F7A",
X"0D1F079676035E09",
X"40F7702C6FA72CA5",
X"2AA8415758A0DF74",
X"474A03642E533CC4",
X"04185FAF6DE3B115",
X"0CAB86287043BFA4",
X"398150E937521657"
),
(
X"4D9A2FDB76C3625E",
X"55075020329B54FB",
X"381FC0385378D5A8",
X"76E5004E797D87A6",
X"2756C7144C598D93",
X"643BD7252B449456",
X"671286247899E644",
X"088232DF6DB50559"
),
(
X"7D157D8D71DFED43",
X"45CB977B6EA3BBBE",
X"3A984B90666D9716",
X"6FD595896931589D",
X"17C5E07E0B0ABB77",
X"51AF16C61DEE132F",
X"3B3A772600F32298",
X"5148068835EB8DF5"
),
(
X"7A1179B41AE53A30",
X"7C418DD42170B934",
X"6DB4489D4A691C3A",
X"5A89680D249AD60F",
X"28BAE6BD526D022F",
X"6DE3EDA1559E2FF7",
X"38B9210F072790D9",
X"638391684C1EE2F4"
),
(
X"0D1102D92657C93C",
X"79B12BA855365135",
X"794F06E57091758F",
X"59B5FE2A302059CD",
X"4E8694C26E7B6440",
X"116E0FC138479ACF",
X"23252C5217E96171",
X"40C9FE6A49067A72"
),
(
X"561F3B294FD30023",
X"07D89DB046755A5B",
X"482FA51B44AEB1A3",
X"0D57872A4CBD7E82",
X"235E94882BD25B44",
X"5EC1CC197B5F2B0E",
X"27DE5630302D71F2",
X"47A3556B3C7F6AA3"
),
(
X"7C55D8AE512B300F",
X"2D5E8A842FBE7DCD",
X"2B847F490057B6D6",
X"5DF6E2834B941D42",
X"4CC54C177044FFE7",
X"274A1FA301B18039",
X"7FDF0C93446D8073",
X"6A50ABC676E04EE6"
)
),
(
(
X"00611EF139B7048A",
X"5CFAA8FE26FAAC21",
X"77E1241B0E63C119",
X"29AE8B7E0F90F8E4",
X"755B6B7570C23C8E",
X"72F7FCC6205C9587",
X"43AF20857ABEBC58",
X"1F1B54DD340C3024"
),
(
X"7B7620E675214E9D",
X"5AEC5E5D0CAD3244",
X"587F60406E6AA68B",
X"1FD3905A22C4F223",
X"7C06BA5E0CF05DA9",
X"36745DEF7325D2EC",
X"775CFE3F0E223791",
X"7502199C312FAB7A"
),
(
X"6559AA410BBADF17",
X"2A16DB1800985972",
X"75C9AEEB4EA0C606",
X"1A637BF20DD45F91",
X"227B64EE121412B8",
X"42967A6C4BB1E6BE",
X"1C2099D9500F7B34",
X"7E0D3DF744AC5234"
),
(
X"142FEF23690AE306",
X"6849ED7A25D23D33",
X"426B1E70040E4297",
X"2E03D8D7274EE452",
X"0346C6125E36B2F5",
X"74A7347E742072D2",
X"20F8FF943D044295",
X"0C75DB6622FEFE06"
),
(
X"63D6E1236C52F559",
X"13DE80F246AC426F",
X"6A4677FA1203EEE7",
X"767BB4EC22E2E0A9",
X"467C6EE63E0E58AB",
X"665297AA003A5839",
X"773336BF05DF1FBA",
X"0D20D75F5F6694A5"
),
(
X"2C86C8B15DE2D8AE",
X"7FDD81242AD45A81",
X"14CC39617DC30B8A",
X"521B4C7811305745",
X"4817E9E417E9263C",
X"09EFFE474CBE2C78",
X"7756E63935F58C47",
X"14B17CC737B9759D"
),
(
X"455E81D9476E8C4A",
X"7B6797AF3BCBFD61",
X"0C2CB017268FBB3B",
X"4681C3BD0C7FE26A",
X"080778F52FCBC7D0",
X"000135441E63235B",
X"4272E9912930A9CD",
X"78AB7F5F24308D75"
),
(
X"1B5A7B5F49202F41",
X"2103FBB8713585D5",
X"00D9443830D8D007",
X"289C95FE48D313D8",
X"25A5CD5A391204B1",
X"4170B52F1DE77846",
X"7F31C5BC4206B48E",
X"07BFF03541F7C92A"
)
),
(
(
X"43FF573804D5E4CC",
X"1EDC4A2A7B8D5AAF",
X"28ADC2AF30C25462",
X"5498210F72A45A86",
X"332A78752C2EF355",
X"332EC7743FEC221C",
X"557BAC7028E1EBA3",
X"1F746A094E0C64E3"
),
(
X"40BACB5F48E2ACBE",
X"4DBB1DB34CA91014",
X"7EF0357A1132F327",
X"44C47458033D4927",
X"354A946B1FA92310",
X"17552ED80A7C5CB1",
X"7AB97D104170719A",
X"75D77CAE515A5105"
),
(
X"40A722086FBFE338",
X"55E2DD847DCB6BD6",
X"0A1B990A24872187",
X"242D4A553FCAD87A",
X"03E4E3A35E1DCE75",
X"51F0AA352AEC52BF",
X"1809F23E5A736871",
X"6FE91E6C2322A884"
),
(
X"6DF778271E63DA77",
X"2A81F9C13740F7D1",
X"621F7DC2473FADE0",
X"0ECFD39645480065",
X"562666204BF4E964",
X"57F7686D7936F374",
X"6EE7EB0755EE4C0B",
X"44C1AA5D4F7DF387"
),
(
X"16DC99605368C1DE",
X"0AA98CB7314D8D5D",
X"5964648B6F641684",
X"09F4BA361AF7C2E0",
X"6B1623BB127E9DBF",
X"19CB4497662FBE85",
X"7BDE7EA20E124E0A",
X"7655B2C10945B15A"
),
(
X"232C184841D5CD1C",
X"353B17C935B804C5",
X"407A658958E3CB69",
X"574084D2137883AA",
X"52E8AA321F7189CF",
X"0BEE617173BA11C8",
X"0DF549D77AEC3614",
X"4EF8AE5164D964A2"
),
(
X"247D020667334E8D",
X"5041D31D4075F3CD",
X"5BDD6FED24043DC9",
X"18883FFA157B47C9",
X"39DD7E18032FD357",
X"54487B0545C44367",
X"787D24FD01B60989",
X"12744794780C1CEA"
),
(
X"41C74C53599937BD",
X"679BC6FF08DE2644",
X"68B031DC1ADC60A5",
X"4564152004DA37D5",
X"16BA7DA341D7E24C",
X"5483058E24019394",
X"47D331934CB87DA1",
X"66ADD5246F103874"
)
),
(
(
X"25DCDCCD1B9E331A",
X"16B6A604675D3BA3",
X"14B4777F5A00FD41",
X"31D535FF3F2A8012",
X"213AF44F6EF45642",
X"0699F098734AC0CB",
X"548DEE737DE2F6F6",
X"1E6741F97A6FD954"
),
(
X"4D4CC8B3057449D4",
X"29741EEC41EC94B5",
X"331D901E32D7FE82",
X"5320437F3FF66956",
X"53F9DE63159D897B",
X"23C6A5604E29C9A7",
X"4F55C1AA6AAB997F",
X"04AC6CAC7B0948E1"
),
(
X"706B2BF03016C8E4",
X"7D091D3877807C4D",
X"571F0866378B963A",
X"0939171E548D45B7",
X"55809B502B0DB4AA",
X"1362976702622738",
X"066826E04163ABEE",
X"04F1C4B64A9F4466"
),
(
X"2D51B68C7533D847",
X"66DB2F8334473607",
X"724FC8C36548DF64",
X"73C895C319C78C0C",
X"51350DEA44078660",
X"63467E4861438AEE",
X"507271666AF75183",
X"0ECCACAB3DD5EE27"
),
(
X"5FB6CF733072F75C",
X"20FF0A9439E75E18",
X"3C1F66D73D586049",
X"3DF0F31F1B3E3D30",
X"66E3E98129FDC121",
X"49830FCD0E41EB0D",
X"530ED0D91C0A5D46",
X"5881E8714B6DDDB1"
),
(
X"1D72EB9A28E05172",
X"6E0AE02A03F0C525",
X"1CB139113CB18F8C",
X"4F808C811F456E1A",
X"4295AAD467A9332D",
X"2417D13456AA68AA",
X"61BC0768418EC1AC",
X"256A1E7670378A72"
),
(
X"727578810F9B9D87",
X"0C6F008B5567B32B",
X"34767B5A6FED3F2F",
X"713F4226417A91BE",
X"023E7BDE21A91AEC",
X"528456BF2A595A38",
X"10A600AD334BDFB0",
X"706032DF3B920BA3"
),
(
X"11C4790D7F6FFC29",
X"6876FDC834B73C6F",
X"7ED693DF4AED9078",
X"286DF60642E7DDB8",
X"27AB01843AE8CB0A",
X"5AB80872141285A2",
X"6903382A4658B84C",
X"4B1103AE3950E877"
)
)
);
end;
package body lut_pkg is
end package body;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2005 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file romo_xil.vhd when simulating
-- the core, romo_xil. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY romo_xil IS
port (
A: IN std_logic_VECTOR(5 downto 0);
CLK: IN std_logic;
QSPO: OUT std_logic_VECTOR(13 downto 0));
END romo_xil;
ARCHITECTURE romo_xil_a OF romo_xil IS
-- synopsys translate_off
component wrapped_romo_xil
port (
A: IN std_logic_VECTOR(5 downto 0);
CLK: IN std_logic;
QSPO: OUT std_logic_VECTOR(13 downto 0));
end component;
-- Configuration specification
for all : wrapped_romo_xil use entity XilinxCoreLib.C_DIST_MEM_V7_1(behavioral)
generic map(
c_qualify_we => 0,
c_mem_type => 0,
c_has_qdpo_rst => 0,
c_has_qspo => 1,
c_has_qspo_rst => 0,
c_has_dpo => 0,
c_has_qdpo_clk => 0,
c_has_d => 0,
c_qce_joined => 0,
c_width => 14,
c_reg_a_d_inputs => 0,
c_latency => 1,
c_has_spo => 0,
c_has_we => 0,
c_depth => 64,
c_has_i_ce => 0,
c_default_data_radix => 2,
c_default_data => "0",
c_has_dpra => 0,
c_has_clk => 1,
c_enable_rlocs => 0,
c_generate_mif => 1,
c_has_qspo_ce => 0,
c_addr_width => 6,
c_has_qdpo_srst => 0,
c_mux_type => 0,
c_has_spra => 0,
c_has_qdpo => 0,
c_mem_init_file => "c:/elektronika/dct/mdct/source/xilinx/romo_xil.mif",
c_reg_dpra_input => 0,
c_has_qspo_srst => 0,
c_has_rd_en => 0,
c_read_mif => 1,
c_sync_enable => 0,
c_has_qdpo_ce => 0);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_romo_xil
port map (
A => A,
CLK => CLK,
QSPO => QSPO);
-- synopsys translate_on
END romo_xil_a;
|
package std is end;
|
-- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8
-- Date: Thu Aug 21 10:54:44 2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_08;
package body pck_myhdl_08 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_08;
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_sm
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_sm.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/10/10 v1_00_a
-- ^^^^^^
-- Fixed issue with fetch idle asserting too soon when simultaneous update
-- decode error and stale descriptor error detected. This fixes CR564855.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 12/07/10 v4_03
-- ^^^^^^
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under
-- associated generate
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_sg_ftch_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
updt_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_sg_idle : in std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
ch1_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_sg_idle : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
--
-- DataMover Command --
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
-- DataMover Status --
ftch_done : in std_logic ; --
ftch_error : in std_logic ; --
ftch_interr : in std_logic ; --
ftch_slverr : in std_logic ; --
ftch_decerr : in std_logic ; --
ftch_stale_desc : in std_logic ; --
ftch_error_early : in std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_ftch_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant FETCH_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
constant FETCH_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant FETCH_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant FETCH_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant FETCH_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant FETCH_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant FETCH_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- Required width in bits for C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
--
---- Vector version of C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_FTCH_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
FETCH_STATUS,
FETCH_ERROR
);
signal ftch_cs : SG_FTCH_STATE_TYPE;
signal ftch_ns : SG_FTCH_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_ftch_sm_idle : std_logic := '0';
signal ch2_ftch_sm_idle : std_logic := '0';
signal ch1_pause_fetch : std_logic := '0';
signal ch2_pause_fetch : std_logic := '0';
-- Misc Signals
signal fetch_cmd_addr : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal fetch_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal ch1_stale_descriptor : std_logic := '0';
signal ch2_stale_descriptor : std_logic := '0';
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- counts for keeping track of queue descriptors to prevent
-- fifo fill
--signal ch1_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--signal ch2_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_ftch_active <= ch1_active_i;
ch2_ftch_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_FTCH_MACHINE : process(ftch_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ftch_error,
ftch_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_ftch_sm_idle <= '0';
ch2_ftch_sm_idle <= '0';
ftch_ns <= ftch_cs;
case ftch_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_ftch_sm_idle <= not service_ch1;
ch2_ftch_sm_idle <= not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
else
ftch_ns <= IDLE;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
else
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_STATUS =>
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
elsif(ftch_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, fetch descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 2 still ready then fetch
-- another descriptor for channel 2
elsif(service_ch2 = '1')then
ch1_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, fetch descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 1 still ready then fetch
-- another descriptor for channel 1
elsif(service_ch1 = '1')then
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_ERROR =>
ch1_ftch_sm_idle <= '1';
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_ERROR;
-------------------------------------------------------------------
when others =>
ftch_ns <= IDLE;
end case;
end process SG_FTCH_MACHINE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_cs <= IDLE;
else
ftch_cs <= ftch_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_FETCH : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_active_set = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 IDLE process. Indicates channel 1 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH1_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
--elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch1_ftch_interr_set_i = '1')then
ch1_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch1_sg_idle = '0')then
ch1_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch1_sg_idle = '1' and ch1_ftch_queue_empty = '1' and ch1_ftch_sm_idle = '1')then
ch1_ftch_idle <= '1';
end if;
end if;
end process CH1_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH1_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch1_updt_done = '1')then
ch1_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch1_active_i='1' and write_cmnd_cmb = '1')then
ch1_pause_fetch <= '1';
end if;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH1_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH1_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch1_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-- begin
--
-- desc_queued_incr <= '1' when ch1_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch1_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch1_ftch_descpulled = '1'
-- and not (ch1_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_pause_fetch <= '0';
-- elsif(ch1_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch1_pause_fetch <= '1';
-- else
-- ch1_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
--
--
ch1_pause_fetch <= ch1_ftch_pause;
end generate GEN_CH1_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_run_stop = '1' -- Channel running
and ch1_sg_idle = '0' -- SG Engine running
and ch1_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch1_stale_descriptor = '0' -- No Stale Descriptors
and ch1_desc_flush = '0' -- Not flushing desc
and ch1_pause_fetch = '0' -- Not pausing
else '0';
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch1_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch1_stale_descriptor = '1'))then
ch1_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_slverr_set <= '0';
elsif(ch1_active_i = '1' and ftch_slverr = '1')then
ch1_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_decerr_set <= '0';
elsif(ch1_active_i = '1' and ftch_decerr = '1')then
ch1_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch1_ftch_err_early <= '1' when ftch_error_early = '1' and ch1_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH1_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH1_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch1_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch1_active_i = '1' )then
ch1_stale_descriptor <= '1';
end if;
end if;
end process CH1_STALE_DESC;
end generate GEN_CH1_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH1_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 generate
begin
ch1_stale_descriptor <= '0';
end generate GEN_CH1_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch1_ftch_stale_desc <= ch1_stale_descriptor;
end generate GEN_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_FETCH : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_ftch_idle <= '0';
ch1_ftch_interr_set <= '0';
ch1_ftch_slverr_set <= '0';
ch1_ftch_decerr_set <= '0';
ch1_ftch_err_early <= '0';
ch1_ftch_stale_desc <= '0';
end generate GEN_NO_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_FETCH : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_active_set = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 IDLE process. Indicates channel 2 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH2_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
-- elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch2_ftch_interr_set_i = '1')then
ch2_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch2_sg_idle = '0')then
ch2_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch2_sg_idle = '1' and ch2_ftch_queue_empty = '1' and ch2_ftch_sm_idle = '1')then
ch2_ftch_idle <= '1';
end if;
end if;
end process CH2_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH2_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch2_updt_done = '1')then
ch2_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch2_active_i='1' and write_cmnd_cmb = '1')then
ch2_pause_fetch <= '1';
end if;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH2_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH2_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch2_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--
-- begin
--
-- desc_queued_incr <= '1' when ch2_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch2_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch2_ftch_descpulled = '1'
-- and not (ch2_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_pause_fetch <= '0';
-- elsif(ch2_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch2_pause_fetch <= '1';
-- else
-- ch2_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
ch2_pause_fetch <= ch2_ftch_pause;
end generate GEN_CH2_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running
and ch2_sg_idle = '0' -- SG Engine running
and ch2_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch2_stale_descriptor = '0' -- No Stale Descriptors
and ch2_desc_flush = '0' -- Not flushing desc
and ch2_pause_fetch = '0' -- No fetch pause
else '0';
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch2_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch2_stale_descriptor = '1'))then
ch2_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_slverr_set <= '0';
elsif(ch2_active_i = '1' and ftch_slverr = '1')then
ch2_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_decerr_set <= '0';
elsif(ch2_active_i = '1' and ftch_decerr = '1')then
ch2_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch2_ftch_err_early <= '1' when ftch_error_early = '1' and ch2_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH2_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH2_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch2_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch2_active_i = '1' )then
ch2_stale_descriptor <= '1';
end if;
end if;
end process CH2_STALE_DESC;
end generate GEN_CH2_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH2_NO_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ch2_stale_descriptor <= '0';
end generate GEN_CH2_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch2_ftch_stale_desc <= ch2_stale_descriptor;
end generate GEN_CH2_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_FETCH : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_ftch_idle <= '0';
ch2_ftch_interr_set <= '0';
ch2_ftch_slverr_set <= '0';
ch2_ftch_decerr_set <= '0';
ch2_ftch_err_early <= '0';
ch2_ftch_stale_desc <= '0';
end generate GEN_NO_CH2_FETCH;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- Assign fetch address
fetch_cmd_addr <= ch1_fetch_address when ch1_active_i = '1'
else ch2_fetch_address;
-- Assign bytes to transfer (BTT)
fetch_cmd_btt <= FETCH_CH1_CMD_BTT when ch1_active_i = '1'
else FETCH_CH2_CMD_BTT;
-- When command by sm, drive command to ftch_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_cmnd_wr <= '0';
ftch_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
ftch_cmnd_wr <= '1';
ftch_cmnd_data <= FETCH_CMD_RSVD
& FETCH_CMD_TAG
& fetch_cmd_addr
& FETCH_MSB_IGNORED
& FETCH_CMD_TYPE
& FETCH_LSB_IGNORED
& fetch_cmd_btt;
else
ftch_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_addr <= (others => '0');
elsif(write_cmnd_cmb = '1')then
ftch_error_addr <= fetch_cmd_addr;
end if;
end if;
end process LOG_ERROR_ADDR;
end implementation;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for pad_pads_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pad_pads_e-e.vhd,v 1.2 2005/07/19 07:13:14 wig Exp $
-- $Date: 2005/07/19 07:13:14 $
-- $Log: pad_pads_e-e.vhd,v $
-- Revision 1.2 2005/07/19 07:13:14 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity pad_pads_e
--
entity pad_pads_e is
-- Generics:
-- No Generated Generics for Entity pad_pads_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity pad_pads_e
p_mix_pad_di_12_go : out std_ulogic;
p_mix_pad_di_13_go : out std_ulogic;
p_mix_pad_di_14_go : out std_ulogic;
p_mix_pad_di_15_go : out std_ulogic;
p_mix_pad_di_16_go : out std_ulogic;
p_mix_pad_di_17_go : out std_ulogic;
p_mix_pad_di_18_go : out std_ulogic;
p_mix_pad_di_1_go : out std_ulogic;
p_mix_pad_di_31_go : out std_ulogic;
p_mix_pad_di_32_go : out std_ulogic;
p_mix_pad_di_33_go : out std_ulogic;
p_mix_pad_di_34_go : out std_ulogic;
p_mix_pad_di_39_go : out std_ulogic;
p_mix_pad_di_40_go : out std_ulogic;
p_mix_pad_do_12_gi : in std_ulogic;
p_mix_pad_do_13_gi : in std_ulogic;
p_mix_pad_do_14_gi : in std_ulogic;
p_mix_pad_do_15_gi : in std_ulogic;
p_mix_pad_do_16_gi : in std_ulogic;
p_mix_pad_do_17_gi : in std_ulogic;
p_mix_pad_do_18_gi : in std_ulogic;
p_mix_pad_do_2_gi : in std_ulogic;
p_mix_pad_do_31_gi : in std_ulogic;
p_mix_pad_do_32_gi : in std_ulogic;
p_mix_pad_do_35_gi : in std_ulogic;
p_mix_pad_do_36_gi : in std_ulogic;
p_mix_pad_do_39_gi : in std_ulogic;
p_mix_pad_do_40_gi : in std_ulogic;
p_mix_pad_en_12_gi : in std_ulogic;
p_mix_pad_en_13_gi : in std_ulogic;
p_mix_pad_en_14_gi : in std_ulogic;
p_mix_pad_en_15_gi : in std_ulogic;
p_mix_pad_en_16_gi : in std_ulogic;
p_mix_pad_en_17_gi : in std_ulogic;
p_mix_pad_en_18_gi : in std_ulogic;
p_mix_pad_en_2_gi : in std_ulogic;
p_mix_pad_en_31_gi : in std_ulogic;
p_mix_pad_en_32_gi : in std_ulogic;
p_mix_pad_en_35_gi : in std_ulogic;
p_mix_pad_en_36_gi : in std_ulogic;
p_mix_pad_en_39_gi : in std_ulogic;
p_mix_pad_en_40_gi : in std_ulogic;
p_mix_pad_pu_31_gi : in std_ulogic;
p_mix_pad_pu_32_gi : in std_ulogic
-- End of Generated Port for Entity pad_pads_e
);
end pad_pads_e;
--
-- End of Generated Entity pad_pads_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SReg is
Generic ( Size : positive := 7);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end SReg;
architecture SReg_arch of SReg is
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (Size-1 downto 0);
component ScanRegister is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
constant ResetValue : STD_LOGIC_VECTOR (Size-1 downto 0) := (others => '0'); -- ResetValue 1'b0
begin
SO <= SR_so; -- Source SR
DO <= SR_do; -- Source SR
SR : ScanRegister
Generic map (Size => Size,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0, -- Source SR[0]
ResetValue => ResetValue)
Port map ( SI => SI, -- ScanInSource SI
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => DI, -- CaptureSource DI
ScanRegister_out => SR_do);
end SReg_arch; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SReg is
Generic ( Size : positive := 7);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end SReg;
architecture SReg_arch of SReg is
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (Size-1 downto 0);
component ScanRegister is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
constant ResetValue : STD_LOGIC_VECTOR (Size-1 downto 0) := (others => '0'); -- ResetValue 1'b0
begin
SO <= SR_so; -- Source SR
DO <= SR_do; -- Source SR
SR : ScanRegister
Generic map (Size => Size,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0, -- Source SR[0]
ResetValue => ResetValue)
Port map ( SI => SI, -- ScanInSource SI
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => DI, -- CaptureSource DI
ScanRegister_out => SR_do);
end SReg_arch; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SReg is
Generic ( Size : positive := 7);
Port ( -- Scan Interface scan_client ----------
SI : in STD_LOGIC; -- ScanInPort
SO : out STD_LOGIC; -- ScanOutPort
SEL : in STD_LOGIC; -- SelectPort
----------------------------------------
SE : in STD_LOGIC; -- ShiftEnPort
CE : in STD_LOGIC; -- CaptureEnPort
UE : in STD_LOGIC; -- UpdateEnPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
DI : in STD_LOGIC_VECTOR (Size-1 downto 0); --DataInPort
DO : out STD_LOGIC_VECTOR (Size-1 downto 0)); --DataOutPort
end SReg;
architecture SReg_arch of SReg is
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (Size-1 downto 0);
component ScanRegister is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
constant ResetValue : STD_LOGIC_VECTOR (Size-1 downto 0) := (others => '0'); -- ResetValue 1'b0
begin
SO <= SR_so; -- Source SR
DO <= SR_do; -- Source SR
SR : ScanRegister
Generic map (Size => Size,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0, -- Source SR[0]
ResetValue => ResetValue)
Port map ( SI => SI, -- ScanInSource SI
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => DI, -- CaptureSource DI
ScanRegister_out => SR_do);
end SReg_arch; |
-------------------------------------------------------------------------------
-- microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_00_a;
use microblaze_v8_00_a.all;
entity microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 3);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 31);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 31);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 3);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 31);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 31);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of microblaze_0_wrapper : entity is "microblaze_v8_00_a";
end microblaze_0_wrapper;
architecture STRUCTURE of microblaze_0_wrapper is
component microblaze is
generic (
C_SCO : integer;
C_FREQ : integer;
C_DATA_SIZE : integer;
C_DYNAMIC_BUS_SIZING : integer;
C_FAMILY : string;
C_INSTANCE : string;
C_FAULT_TOLERANT : integer;
C_ECC_USE_CE_EXCEPTION : integer;
C_ENDIANNESS : integer;
C_AREA_OPTIMIZED : integer;
C_OPTIMIZATION : integer;
C_INTERCONNECT : integer;
C_STREAM_INTERCONNECT : integer;
C_DPLB_DWIDTH : integer;
C_DPLB_NATIVE_DWIDTH : integer;
C_DPLB_BURST_EN : integer;
C_DPLB_P2P : integer;
C_IPLB_DWIDTH : integer;
C_IPLB_NATIVE_DWIDTH : integer;
C_IPLB_BURST_EN : integer;
C_IPLB_P2P : integer;
C_M_AXI_DP_THREAD_ID_WIDTH : integer;
C_M_AXI_DP_DATA_WIDTH : integer;
C_M_AXI_DP_ADDR_WIDTH : integer;
C_M_AXI_IP_THREAD_ID_WIDTH : integer;
C_M_AXI_IP_DATA_WIDTH : integer;
C_M_AXI_IP_ADDR_WIDTH : integer;
C_D_AXI : integer;
C_D_PLB : integer;
C_D_LMB : integer;
C_I_AXI : integer;
C_I_PLB : integer;
C_I_LMB : integer;
C_USE_MSR_INSTR : integer;
C_USE_PCMP_INSTR : integer;
C_USE_BARREL : integer;
C_USE_DIV : integer;
C_USE_HW_MUL : integer;
C_USE_FPU : integer;
C_UNALIGNED_EXCEPTIONS : integer;
C_ILL_OPCODE_EXCEPTION : integer;
C_M_AXI_I_BUS_EXCEPTION : integer;
C_M_AXI_D_BUS_EXCEPTION : integer;
C_IPLB_BUS_EXCEPTION : integer;
C_DPLB_BUS_EXCEPTION : integer;
C_DIV_ZERO_EXCEPTION : integer;
C_FPU_EXCEPTION : integer;
C_FSL_EXCEPTION : integer;
C_PVR : integer;
C_PVR_USER1 : std_logic_vector(0 to 7);
C_PVR_USER2 : std_logic_vector(0 to 31);
C_DEBUG_ENABLED : integer;
C_NUMBER_OF_PC_BRK : integer;
C_NUMBER_OF_RD_ADDR_BRK : integer;
C_NUMBER_OF_WR_ADDR_BRK : integer;
C_INTERRUPT_IS_EDGE : integer;
C_EDGE_IS_POSITIVE : integer;
C_RESET_MSR : std_logic_vector;
C_OPCODE_0x0_ILLEGAL : integer;
C_FSL_LINKS : integer;
C_FSL_DATA_SIZE : integer;
C_USE_EXTENDED_FSL_INSTR : integer;
C_M0_AXIS_DATA_WIDTH : integer;
C_S0_AXIS_DATA_WIDTH : integer;
C_M1_AXIS_DATA_WIDTH : integer;
C_S1_AXIS_DATA_WIDTH : integer;
C_M2_AXIS_DATA_WIDTH : integer;
C_S2_AXIS_DATA_WIDTH : integer;
C_M3_AXIS_DATA_WIDTH : integer;
C_S3_AXIS_DATA_WIDTH : integer;
C_M4_AXIS_DATA_WIDTH : integer;
C_S4_AXIS_DATA_WIDTH : integer;
C_M5_AXIS_DATA_WIDTH : integer;
C_S5_AXIS_DATA_WIDTH : integer;
C_M6_AXIS_DATA_WIDTH : integer;
C_S6_AXIS_DATA_WIDTH : integer;
C_M7_AXIS_DATA_WIDTH : integer;
C_S7_AXIS_DATA_WIDTH : integer;
C_M8_AXIS_DATA_WIDTH : integer;
C_S8_AXIS_DATA_WIDTH : integer;
C_M9_AXIS_DATA_WIDTH : integer;
C_S9_AXIS_DATA_WIDTH : integer;
C_M10_AXIS_DATA_WIDTH : integer;
C_S10_AXIS_DATA_WIDTH : integer;
C_M11_AXIS_DATA_WIDTH : integer;
C_S11_AXIS_DATA_WIDTH : integer;
C_M12_AXIS_DATA_WIDTH : integer;
C_S12_AXIS_DATA_WIDTH : integer;
C_M13_AXIS_DATA_WIDTH : integer;
C_S13_AXIS_DATA_WIDTH : integer;
C_M14_AXIS_DATA_WIDTH : integer;
C_S14_AXIS_DATA_WIDTH : integer;
C_M15_AXIS_DATA_WIDTH : integer;
C_S15_AXIS_DATA_WIDTH : integer;
C_ICACHE_BASEADDR : std_logic_vector;
C_ICACHE_HIGHADDR : std_logic_vector;
C_USE_ICACHE : integer;
C_ALLOW_ICACHE_WR : integer;
C_ADDR_TAG_BITS : integer;
C_CACHE_BYTE_SIZE : integer;
C_ICACHE_USE_FSL : integer;
C_ICACHE_LINE_LEN : integer;
C_ICACHE_ALWAYS_USED : integer;
C_ICACHE_INTERFACE : integer;
C_ICACHE_VICTIMS : integer;
C_ICACHE_STREAMS : integer;
C_ICACHE_FORCE_TAG_LUTRAM : integer;
C_ICACHE_DATA_WIDTH : integer;
C_M_AXI_IC_THREAD_ID_WIDTH : integer;
C_M_AXI_IC_DATA_WIDTH : integer;
C_M_AXI_IC_ADDR_WIDTH : integer;
C_DCACHE_BASEADDR : std_logic_vector;
C_DCACHE_HIGHADDR : std_logic_vector;
C_USE_DCACHE : integer;
C_ALLOW_DCACHE_WR : integer;
C_DCACHE_ADDR_TAG : integer;
C_DCACHE_BYTE_SIZE : integer;
C_DCACHE_USE_FSL : integer;
C_DCACHE_LINE_LEN : integer;
C_DCACHE_ALWAYS_USED : integer;
C_DCACHE_INTERFACE : integer;
C_DCACHE_USE_WRITEBACK : integer;
C_DCACHE_VICTIMS : integer;
C_DCACHE_FORCE_TAG_LUTRAM : integer;
C_DCACHE_DATA_WIDTH : integer;
C_M_AXI_DC_THREAD_ID_WIDTH : integer;
C_M_AXI_DC_DATA_WIDTH : integer;
C_M_AXI_DC_ADDR_WIDTH : integer;
C_USE_MMU : integer;
C_MMU_DTLB_SIZE : integer;
C_MMU_ITLB_SIZE : integer;
C_MMU_TLB_ACCESS : integer;
C_MMU_ZONES : integer;
C_USE_INTERRUPT : integer;
C_USE_EXT_BRK : integer;
C_USE_EXT_NM_BRK : integer;
C_USE_BRANCH_TARGET_CACHE : integer;
C_BRANCH_TARGET_CACHE_SIZE : integer
);
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_AWADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(((C_M_AXI_IP_DATA_WIDTH/8)-1) downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_ARADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_RDATA : in std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_AWADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(((C_M_AXI_DP_DATA_WIDTH/8)-1) downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_ARADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_RDATA : in std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_AWADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_WDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(((C_M_AXI_IC_DATA_WIDTH/8)-1) downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_BID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_ARID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_ARADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_RID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_RDATA : in std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_DC_AWID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_AWADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_WDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(((C_M_AXI_DC_DATA_WIDTH/8)-1) downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_BID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_ARID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_ARADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_RID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_RDATA : in std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(C_M0_AXIS_DATA_WIDTH-1 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(C_S0_AXIS_DATA_WIDTH-1 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(C_M1_AXIS_DATA_WIDTH-1 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(C_S1_AXIS_DATA_WIDTH-1 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(C_M2_AXIS_DATA_WIDTH-1 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(C_S2_AXIS_DATA_WIDTH-1 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(C_M3_AXIS_DATA_WIDTH-1 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(C_S3_AXIS_DATA_WIDTH-1 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(C_M4_AXIS_DATA_WIDTH-1 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(C_S4_AXIS_DATA_WIDTH-1 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(C_M5_AXIS_DATA_WIDTH-1 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(C_S5_AXIS_DATA_WIDTH-1 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(C_M6_AXIS_DATA_WIDTH-1 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(C_S6_AXIS_DATA_WIDTH-1 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(C_M7_AXIS_DATA_WIDTH-1 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(C_S7_AXIS_DATA_WIDTH-1 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(C_M8_AXIS_DATA_WIDTH-1 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(C_S8_AXIS_DATA_WIDTH-1 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(C_M9_AXIS_DATA_WIDTH-1 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(C_S9_AXIS_DATA_WIDTH-1 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(C_M10_AXIS_DATA_WIDTH-1 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(C_S10_AXIS_DATA_WIDTH-1 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(C_M11_AXIS_DATA_WIDTH-1 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(C_S11_AXIS_DATA_WIDTH-1 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(C_M12_AXIS_DATA_WIDTH-1 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(C_S12_AXIS_DATA_WIDTH-1 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(C_M13_AXIS_DATA_WIDTH-1 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(C_S13_AXIS_DATA_WIDTH-1 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(C_M14_AXIS_DATA_WIDTH-1 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(C_S14_AXIS_DATA_WIDTH-1 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(C_M15_AXIS_DATA_WIDTH-1 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(C_S15_AXIS_DATA_WIDTH-1 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
begin
microblaze_0 : microblaze
generic map (
C_SCO => 0,
C_FREQ => 66666666,
C_DATA_SIZE => 32,
C_DYNAMIC_BUS_SIZING => 1,
C_FAMILY => "spartan3a",
C_INSTANCE => "microblaze_0",
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_ENDIANNESS => 0,
C_AREA_OPTIMIZED => 1,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 1,
C_STREAM_INTERCONNECT => 0,
C_DPLB_DWIDTH => 32,
C_DPLB_NATIVE_DWIDTH => 32,
C_DPLB_BURST_EN => 0,
C_DPLB_P2P => 0,
C_IPLB_DWIDTH => 32,
C_IPLB_NATIVE_DWIDTH => 32,
C_IPLB_BURST_EN => 0,
C_IPLB_P2P => 0,
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_D_AXI => 0,
C_D_PLB => 1,
C_D_LMB => 1,
C_I_AXI => 0,
C_I_PLB => 1,
C_I_LMB => 1,
C_USE_MSR_INSTR => 1,
C_USE_PCMP_INSTR => 1,
C_USE_BARREL => 1,
C_USE_DIV => 0,
C_USE_HW_MUL => 1,
C_USE_FPU => 0,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_IPLB_BUS_EXCEPTION => 0,
C_DPLB_BUS_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_EXCEPTION => 0,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_FSL_LINKS => 0,
C_FSL_DATA_SIZE => 32,
C_USE_EXTENDED_FSL_INSTR => 0,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"84c00000",
C_ICACHE_HIGHADDR => X"84ffffff",
C_USE_ICACHE => 1,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 11,
C_CACHE_BYTE_SIZE => 2048,
C_ICACHE_USE_FSL => 1,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 1,
C_ICACHE_INTERFACE => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_STREAMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_DCACHE_BASEADDR => X"00000000",
C_DCACHE_HIGHADDR => X"3FFFFFFF",
C_USE_DCACHE => 0,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 0,
C_DCACHE_BYTE_SIZE => 8192,
C_DCACHE_USE_FSL => 1,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 0,
C_DCACHE_INTERFACE => 0,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_USE_INTERRUPT => 1,
C_USE_EXT_BRK => 1,
C_USE_EXT_NM_BRK => 1,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0
)
port map (
CLK => CLK,
RESET => RESET,
MB_RESET => MB_RESET,
INTERRUPT => INTERRUPT,
EXT_BRK => EXT_BRK,
EXT_NM_BRK => EXT_NM_BRK,
DBG_STOP => DBG_STOP,
MB_Halted => MB_Halted,
MB_Error => MB_Error,
INSTR => INSTR,
IREADY => IREADY,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
INSTR_ADDR => INSTR_ADDR,
IFETCH => IFETCH,
I_AS => I_AS,
IPLB_M_ABort => IPLB_M_ABort,
IPLB_M_ABus => IPLB_M_ABus,
IPLB_M_UABus => IPLB_M_UABus,
IPLB_M_BE => IPLB_M_BE,
IPLB_M_busLock => IPLB_M_busLock,
IPLB_M_lockErr => IPLB_M_lockErr,
IPLB_M_MSize => IPLB_M_MSize,
IPLB_M_priority => IPLB_M_priority,
IPLB_M_rdBurst => IPLB_M_rdBurst,
IPLB_M_request => IPLB_M_request,
IPLB_M_RNW => IPLB_M_RNW,
IPLB_M_size => IPLB_M_size,
IPLB_M_TAttribute => IPLB_M_TAttribute,
IPLB_M_type => IPLB_M_type,
IPLB_M_wrBurst => IPLB_M_wrBurst,
IPLB_M_wrDBus => IPLB_M_wrDBus,
IPLB_MBusy => IPLB_MBusy,
IPLB_MRdErr => IPLB_MRdErr,
IPLB_MWrErr => IPLB_MWrErr,
IPLB_MIRQ => IPLB_MIRQ,
IPLB_MWrBTerm => IPLB_MWrBTerm,
IPLB_MWrDAck => IPLB_MWrDAck,
IPLB_MAddrAck => IPLB_MAddrAck,
IPLB_MRdBTerm => IPLB_MRdBTerm,
IPLB_MRdDAck => IPLB_MRdDAck,
IPLB_MRdDBus => IPLB_MRdDBus,
IPLB_MRdWdAddr => IPLB_MRdWdAddr,
IPLB_MRearbitrate => IPLB_MRearbitrate,
IPLB_MSSize => IPLB_MSSize,
IPLB_MTimeout => IPLB_MTimeout,
DATA_READ => DATA_READ,
DREADY => DREADY,
DWAIT => DWAIT,
DCE => DCE,
DUE => DUE,
DATA_WRITE => DATA_WRITE,
DATA_ADDR => DATA_ADDR,
D_AS => D_AS,
READ_STROBE => READ_STROBE,
WRITE_STROBE => WRITE_STROBE,
BYTE_ENABLE => BYTE_ENABLE,
DPLB_M_ABort => DPLB_M_ABort,
DPLB_M_ABus => DPLB_M_ABus,
DPLB_M_UABus => DPLB_M_UABus,
DPLB_M_BE => DPLB_M_BE,
DPLB_M_busLock => DPLB_M_busLock,
DPLB_M_lockErr => DPLB_M_lockErr,
DPLB_M_MSize => DPLB_M_MSize,
DPLB_M_priority => DPLB_M_priority,
DPLB_M_rdBurst => DPLB_M_rdBurst,
DPLB_M_request => DPLB_M_request,
DPLB_M_RNW => DPLB_M_RNW,
DPLB_M_size => DPLB_M_size,
DPLB_M_TAttribute => DPLB_M_TAttribute,
DPLB_M_type => DPLB_M_type,
DPLB_M_wrBurst => DPLB_M_wrBurst,
DPLB_M_wrDBus => DPLB_M_wrDBus,
DPLB_MBusy => DPLB_MBusy,
DPLB_MRdErr => DPLB_MRdErr,
DPLB_MWrErr => DPLB_MWrErr,
DPLB_MIRQ => DPLB_MIRQ,
DPLB_MWrBTerm => DPLB_MWrBTerm,
DPLB_MWrDAck => DPLB_MWrDAck,
DPLB_MAddrAck => DPLB_MAddrAck,
DPLB_MRdBTerm => DPLB_MRdBTerm,
DPLB_MRdDAck => DPLB_MRdDAck,
DPLB_MRdDBus => DPLB_MRdDBus,
DPLB_MRdWdAddr => DPLB_MRdWdAddr,
DPLB_MRearbitrate => DPLB_MRearbitrate,
DPLB_MSSize => DPLB_MSSize,
DPLB_MTimeout => DPLB_MTimeout,
M_AXI_IP_AWID => M_AXI_IP_AWID,
M_AXI_IP_AWADDR => M_AXI_IP_AWADDR,
M_AXI_IP_AWLEN => M_AXI_IP_AWLEN,
M_AXI_IP_AWSIZE => M_AXI_IP_AWSIZE,
M_AXI_IP_AWBURST => M_AXI_IP_AWBURST,
M_AXI_IP_AWLOCK => M_AXI_IP_AWLOCK,
M_AXI_IP_AWCACHE => M_AXI_IP_AWCACHE,
M_AXI_IP_AWPROT => M_AXI_IP_AWPROT,
M_AXI_IP_AWQOS => M_AXI_IP_AWQOS,
M_AXI_IP_AWVALID => M_AXI_IP_AWVALID,
M_AXI_IP_AWREADY => M_AXI_IP_AWREADY,
M_AXI_IP_WDATA => M_AXI_IP_WDATA,
M_AXI_IP_WSTRB => M_AXI_IP_WSTRB,
M_AXI_IP_WLAST => M_AXI_IP_WLAST,
M_AXI_IP_WVALID => M_AXI_IP_WVALID,
M_AXI_IP_WREADY => M_AXI_IP_WREADY,
M_AXI_IP_BID => M_AXI_IP_BID,
M_AXI_IP_BRESP => M_AXI_IP_BRESP,
M_AXI_IP_BVALID => M_AXI_IP_BVALID,
M_AXI_IP_BREADY => M_AXI_IP_BREADY,
M_AXI_IP_ARID => M_AXI_IP_ARID,
M_AXI_IP_ARADDR => M_AXI_IP_ARADDR,
M_AXI_IP_ARLEN => M_AXI_IP_ARLEN,
M_AXI_IP_ARSIZE => M_AXI_IP_ARSIZE,
M_AXI_IP_ARBURST => M_AXI_IP_ARBURST,
M_AXI_IP_ARLOCK => M_AXI_IP_ARLOCK,
M_AXI_IP_ARCACHE => M_AXI_IP_ARCACHE,
M_AXI_IP_ARPROT => M_AXI_IP_ARPROT,
M_AXI_IP_ARQOS => M_AXI_IP_ARQOS,
M_AXI_IP_ARVALID => M_AXI_IP_ARVALID,
M_AXI_IP_ARREADY => M_AXI_IP_ARREADY,
M_AXI_IP_RID => M_AXI_IP_RID,
M_AXI_IP_RDATA => M_AXI_IP_RDATA,
M_AXI_IP_RRESP => M_AXI_IP_RRESP,
M_AXI_IP_RLAST => M_AXI_IP_RLAST,
M_AXI_IP_RVALID => M_AXI_IP_RVALID,
M_AXI_IP_RREADY => M_AXI_IP_RREADY,
M_AXI_DP_AWID => M_AXI_DP_AWID,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWLEN => M_AXI_DP_AWLEN,
M_AXI_DP_AWSIZE => M_AXI_DP_AWSIZE,
M_AXI_DP_AWBURST => M_AXI_DP_AWBURST,
M_AXI_DP_AWLOCK => M_AXI_DP_AWLOCK,
M_AXI_DP_AWCACHE => M_AXI_DP_AWCACHE,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWQOS => M_AXI_DP_AWQOS,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WLAST => M_AXI_DP_WLAST,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => M_AXI_DP_BID,
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARID => M_AXI_DP_ARID,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARLEN => M_AXI_DP_ARLEN,
M_AXI_DP_ARSIZE => M_AXI_DP_ARSIZE,
M_AXI_DP_ARBURST => M_AXI_DP_ARBURST,
M_AXI_DP_ARLOCK => M_AXI_DP_ARLOCK,
M_AXI_DP_ARCACHE => M_AXI_DP_ARCACHE,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARQOS => M_AXI_DP_ARQOS,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => M_AXI_DP_RID,
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => M_AXI_DP_RLAST,
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
DBG_CLK => DBG_CLK,
DBG_TDI => DBG_TDI,
DBG_TDO => DBG_TDO,
DBG_REG_EN => DBG_REG_EN,
DBG_SHIFT => DBG_SHIFT,
DBG_CAPTURE => DBG_CAPTURE,
DBG_UPDATE => DBG_UPDATE,
DEBUG_RST => DEBUG_RST,
Trace_Instruction => Trace_Instruction,
Trace_Valid_Instr => Trace_Valid_Instr,
Trace_PC => Trace_PC,
Trace_Reg_Write => Trace_Reg_Write,
Trace_Reg_Addr => Trace_Reg_Addr,
Trace_MSR_Reg => Trace_MSR_Reg,
Trace_PID_Reg => Trace_PID_Reg,
Trace_New_Reg_Value => Trace_New_Reg_Value,
Trace_Exception_Taken => Trace_Exception_Taken,
Trace_Exception_Kind => Trace_Exception_Kind,
Trace_Jump_Taken => Trace_Jump_Taken,
Trace_Delay_Slot => Trace_Delay_Slot,
Trace_Data_Address => Trace_Data_Address,
Trace_Data_Access => Trace_Data_Access,
Trace_Data_Read => Trace_Data_Read,
Trace_Data_Write => Trace_Data_Write,
Trace_Data_Write_Value => Trace_Data_Write_Value,
Trace_Data_Byte_Enable => Trace_Data_Byte_Enable,
Trace_DCache_Req => Trace_DCache_Req,
Trace_DCache_Hit => Trace_DCache_Hit,
Trace_DCache_Rdy => Trace_DCache_Rdy,
Trace_DCache_Read => Trace_DCache_Read,
Trace_ICache_Req => Trace_ICache_Req,
Trace_ICache_Hit => Trace_ICache_Hit,
Trace_ICache_Rdy => Trace_ICache_Rdy,
Trace_OF_PipeRun => Trace_OF_PipeRun,
Trace_EX_PipeRun => Trace_EX_PipeRun,
Trace_MEM_PipeRun => Trace_MEM_PipeRun,
Trace_MB_Halted => Trace_MB_Halted,
Trace_Jump_Hit => Trace_Jump_Hit,
FSL0_S_CLK => FSL0_S_CLK,
FSL0_S_READ => FSL0_S_READ,
FSL0_S_DATA => FSL0_S_DATA,
FSL0_S_CONTROL => FSL0_S_CONTROL,
FSL0_S_EXISTS => FSL0_S_EXISTS,
FSL0_M_CLK => FSL0_M_CLK,
FSL0_M_WRITE => FSL0_M_WRITE,
FSL0_M_DATA => FSL0_M_DATA,
FSL0_M_CONTROL => FSL0_M_CONTROL,
FSL0_M_FULL => FSL0_M_FULL,
FSL1_S_CLK => FSL1_S_CLK,
FSL1_S_READ => FSL1_S_READ,
FSL1_S_DATA => FSL1_S_DATA,
FSL1_S_CONTROL => FSL1_S_CONTROL,
FSL1_S_EXISTS => FSL1_S_EXISTS,
FSL1_M_CLK => FSL1_M_CLK,
FSL1_M_WRITE => FSL1_M_WRITE,
FSL1_M_DATA => FSL1_M_DATA,
FSL1_M_CONTROL => FSL1_M_CONTROL,
FSL1_M_FULL => FSL1_M_FULL,
FSL2_S_CLK => FSL2_S_CLK,
FSL2_S_READ => FSL2_S_READ,
FSL2_S_DATA => FSL2_S_DATA,
FSL2_S_CONTROL => FSL2_S_CONTROL,
FSL2_S_EXISTS => FSL2_S_EXISTS,
FSL2_M_CLK => FSL2_M_CLK,
FSL2_M_WRITE => FSL2_M_WRITE,
FSL2_M_DATA => FSL2_M_DATA,
FSL2_M_CONTROL => FSL2_M_CONTROL,
FSL2_M_FULL => FSL2_M_FULL,
FSL3_S_CLK => FSL3_S_CLK,
FSL3_S_READ => FSL3_S_READ,
FSL3_S_DATA => FSL3_S_DATA,
FSL3_S_CONTROL => FSL3_S_CONTROL,
FSL3_S_EXISTS => FSL3_S_EXISTS,
FSL3_M_CLK => FSL3_M_CLK,
FSL3_M_WRITE => FSL3_M_WRITE,
FSL3_M_DATA => FSL3_M_DATA,
FSL3_M_CONTROL => FSL3_M_CONTROL,
FSL3_M_FULL => FSL3_M_FULL,
FSL4_S_CLK => FSL4_S_CLK,
FSL4_S_READ => FSL4_S_READ,
FSL4_S_DATA => FSL4_S_DATA,
FSL4_S_CONTROL => FSL4_S_CONTROL,
FSL4_S_EXISTS => FSL4_S_EXISTS,
FSL4_M_CLK => FSL4_M_CLK,
FSL4_M_WRITE => FSL4_M_WRITE,
FSL4_M_DATA => FSL4_M_DATA,
FSL4_M_CONTROL => FSL4_M_CONTROL,
FSL4_M_FULL => FSL4_M_FULL,
FSL5_S_CLK => FSL5_S_CLK,
FSL5_S_READ => FSL5_S_READ,
FSL5_S_DATA => FSL5_S_DATA,
FSL5_S_CONTROL => FSL5_S_CONTROL,
FSL5_S_EXISTS => FSL5_S_EXISTS,
FSL5_M_CLK => FSL5_M_CLK,
FSL5_M_WRITE => FSL5_M_WRITE,
FSL5_M_DATA => FSL5_M_DATA,
FSL5_M_CONTROL => FSL5_M_CONTROL,
FSL5_M_FULL => FSL5_M_FULL,
FSL6_S_CLK => FSL6_S_CLK,
FSL6_S_READ => FSL6_S_READ,
FSL6_S_DATA => FSL6_S_DATA,
FSL6_S_CONTROL => FSL6_S_CONTROL,
FSL6_S_EXISTS => FSL6_S_EXISTS,
FSL6_M_CLK => FSL6_M_CLK,
FSL6_M_WRITE => FSL6_M_WRITE,
FSL6_M_DATA => FSL6_M_DATA,
FSL6_M_CONTROL => FSL6_M_CONTROL,
FSL6_M_FULL => FSL6_M_FULL,
FSL7_S_CLK => FSL7_S_CLK,
FSL7_S_READ => FSL7_S_READ,
FSL7_S_DATA => FSL7_S_DATA,
FSL7_S_CONTROL => FSL7_S_CONTROL,
FSL7_S_EXISTS => FSL7_S_EXISTS,
FSL7_M_CLK => FSL7_M_CLK,
FSL7_M_WRITE => FSL7_M_WRITE,
FSL7_M_DATA => FSL7_M_DATA,
FSL7_M_CONTROL => FSL7_M_CONTROL,
FSL7_M_FULL => FSL7_M_FULL,
FSL8_S_CLK => FSL8_S_CLK,
FSL8_S_READ => FSL8_S_READ,
FSL8_S_DATA => FSL8_S_DATA,
FSL8_S_CONTROL => FSL8_S_CONTROL,
FSL8_S_EXISTS => FSL8_S_EXISTS,
FSL8_M_CLK => FSL8_M_CLK,
FSL8_M_WRITE => FSL8_M_WRITE,
FSL8_M_DATA => FSL8_M_DATA,
FSL8_M_CONTROL => FSL8_M_CONTROL,
FSL8_M_FULL => FSL8_M_FULL,
FSL9_S_CLK => FSL9_S_CLK,
FSL9_S_READ => FSL9_S_READ,
FSL9_S_DATA => FSL9_S_DATA,
FSL9_S_CONTROL => FSL9_S_CONTROL,
FSL9_S_EXISTS => FSL9_S_EXISTS,
FSL9_M_CLK => FSL9_M_CLK,
FSL9_M_WRITE => FSL9_M_WRITE,
FSL9_M_DATA => FSL9_M_DATA,
FSL9_M_CONTROL => FSL9_M_CONTROL,
FSL9_M_FULL => FSL9_M_FULL,
FSL10_S_CLK => FSL10_S_CLK,
FSL10_S_READ => FSL10_S_READ,
FSL10_S_DATA => FSL10_S_DATA,
FSL10_S_CONTROL => FSL10_S_CONTROL,
FSL10_S_EXISTS => FSL10_S_EXISTS,
FSL10_M_CLK => FSL10_M_CLK,
FSL10_M_WRITE => FSL10_M_WRITE,
FSL10_M_DATA => FSL10_M_DATA,
FSL10_M_CONTROL => FSL10_M_CONTROL,
FSL10_M_FULL => FSL10_M_FULL,
FSL11_S_CLK => FSL11_S_CLK,
FSL11_S_READ => FSL11_S_READ,
FSL11_S_DATA => FSL11_S_DATA,
FSL11_S_CONTROL => FSL11_S_CONTROL,
FSL11_S_EXISTS => FSL11_S_EXISTS,
FSL11_M_CLK => FSL11_M_CLK,
FSL11_M_WRITE => FSL11_M_WRITE,
FSL11_M_DATA => FSL11_M_DATA,
FSL11_M_CONTROL => FSL11_M_CONTROL,
FSL11_M_FULL => FSL11_M_FULL,
FSL12_S_CLK => FSL12_S_CLK,
FSL12_S_READ => FSL12_S_READ,
FSL12_S_DATA => FSL12_S_DATA,
FSL12_S_CONTROL => FSL12_S_CONTROL,
FSL12_S_EXISTS => FSL12_S_EXISTS,
FSL12_M_CLK => FSL12_M_CLK,
FSL12_M_WRITE => FSL12_M_WRITE,
FSL12_M_DATA => FSL12_M_DATA,
FSL12_M_CONTROL => FSL12_M_CONTROL,
FSL12_M_FULL => FSL12_M_FULL,
FSL13_S_CLK => FSL13_S_CLK,
FSL13_S_READ => FSL13_S_READ,
FSL13_S_DATA => FSL13_S_DATA,
FSL13_S_CONTROL => FSL13_S_CONTROL,
FSL13_S_EXISTS => FSL13_S_EXISTS,
FSL13_M_CLK => FSL13_M_CLK,
FSL13_M_WRITE => FSL13_M_WRITE,
FSL13_M_DATA => FSL13_M_DATA,
FSL13_M_CONTROL => FSL13_M_CONTROL,
FSL13_M_FULL => FSL13_M_FULL,
FSL14_S_CLK => FSL14_S_CLK,
FSL14_S_READ => FSL14_S_READ,
FSL14_S_DATA => FSL14_S_DATA,
FSL14_S_CONTROL => FSL14_S_CONTROL,
FSL14_S_EXISTS => FSL14_S_EXISTS,
FSL14_M_CLK => FSL14_M_CLK,
FSL14_M_WRITE => FSL14_M_WRITE,
FSL14_M_DATA => FSL14_M_DATA,
FSL14_M_CONTROL => FSL14_M_CONTROL,
FSL14_M_FULL => FSL14_M_FULL,
FSL15_S_CLK => FSL15_S_CLK,
FSL15_S_READ => FSL15_S_READ,
FSL15_S_DATA => FSL15_S_DATA,
FSL15_S_CONTROL => FSL15_S_CONTROL,
FSL15_S_EXISTS => FSL15_S_EXISTS,
FSL15_M_CLK => FSL15_M_CLK,
FSL15_M_WRITE => FSL15_M_WRITE,
FSL15_M_DATA => FSL15_M_DATA,
FSL15_M_CONTROL => FSL15_M_CONTROL,
FSL15_M_FULL => FSL15_M_FULL,
M0_AXIS_TLAST => M0_AXIS_TLAST,
M0_AXIS_TDATA => M0_AXIS_TDATA,
M0_AXIS_TVALID => M0_AXIS_TVALID,
M0_AXIS_TREADY => M0_AXIS_TREADY,
S0_AXIS_TLAST => S0_AXIS_TLAST,
S0_AXIS_TDATA => S0_AXIS_TDATA,
S0_AXIS_TVALID => S0_AXIS_TVALID,
S0_AXIS_TREADY => S0_AXIS_TREADY,
M1_AXIS_TLAST => M1_AXIS_TLAST,
M1_AXIS_TDATA => M1_AXIS_TDATA,
M1_AXIS_TVALID => M1_AXIS_TVALID,
M1_AXIS_TREADY => M1_AXIS_TREADY,
S1_AXIS_TLAST => S1_AXIS_TLAST,
S1_AXIS_TDATA => S1_AXIS_TDATA,
S1_AXIS_TVALID => S1_AXIS_TVALID,
S1_AXIS_TREADY => S1_AXIS_TREADY,
M2_AXIS_TLAST => M2_AXIS_TLAST,
M2_AXIS_TDATA => M2_AXIS_TDATA,
M2_AXIS_TVALID => M2_AXIS_TVALID,
M2_AXIS_TREADY => M2_AXIS_TREADY,
S2_AXIS_TLAST => S2_AXIS_TLAST,
S2_AXIS_TDATA => S2_AXIS_TDATA,
S2_AXIS_TVALID => S2_AXIS_TVALID,
S2_AXIS_TREADY => S2_AXIS_TREADY,
M3_AXIS_TLAST => M3_AXIS_TLAST,
M3_AXIS_TDATA => M3_AXIS_TDATA,
M3_AXIS_TVALID => M3_AXIS_TVALID,
M3_AXIS_TREADY => M3_AXIS_TREADY,
S3_AXIS_TLAST => S3_AXIS_TLAST,
S3_AXIS_TDATA => S3_AXIS_TDATA,
S3_AXIS_TVALID => S3_AXIS_TVALID,
S3_AXIS_TREADY => S3_AXIS_TREADY,
M4_AXIS_TLAST => M4_AXIS_TLAST,
M4_AXIS_TDATA => M4_AXIS_TDATA,
M4_AXIS_TVALID => M4_AXIS_TVALID,
M4_AXIS_TREADY => M4_AXIS_TREADY,
S4_AXIS_TLAST => S4_AXIS_TLAST,
S4_AXIS_TDATA => S4_AXIS_TDATA,
S4_AXIS_TVALID => S4_AXIS_TVALID,
S4_AXIS_TREADY => S4_AXIS_TREADY,
M5_AXIS_TLAST => M5_AXIS_TLAST,
M5_AXIS_TDATA => M5_AXIS_TDATA,
M5_AXIS_TVALID => M5_AXIS_TVALID,
M5_AXIS_TREADY => M5_AXIS_TREADY,
S5_AXIS_TLAST => S5_AXIS_TLAST,
S5_AXIS_TDATA => S5_AXIS_TDATA,
S5_AXIS_TVALID => S5_AXIS_TVALID,
S5_AXIS_TREADY => S5_AXIS_TREADY,
M6_AXIS_TLAST => M6_AXIS_TLAST,
M6_AXIS_TDATA => M6_AXIS_TDATA,
M6_AXIS_TVALID => M6_AXIS_TVALID,
M6_AXIS_TREADY => M6_AXIS_TREADY,
S6_AXIS_TLAST => S6_AXIS_TLAST,
S6_AXIS_TDATA => S6_AXIS_TDATA,
S6_AXIS_TVALID => S6_AXIS_TVALID,
S6_AXIS_TREADY => S6_AXIS_TREADY,
M7_AXIS_TLAST => M7_AXIS_TLAST,
M7_AXIS_TDATA => M7_AXIS_TDATA,
M7_AXIS_TVALID => M7_AXIS_TVALID,
M7_AXIS_TREADY => M7_AXIS_TREADY,
S7_AXIS_TLAST => S7_AXIS_TLAST,
S7_AXIS_TDATA => S7_AXIS_TDATA,
S7_AXIS_TVALID => S7_AXIS_TVALID,
S7_AXIS_TREADY => S7_AXIS_TREADY,
M8_AXIS_TLAST => M8_AXIS_TLAST,
M8_AXIS_TDATA => M8_AXIS_TDATA,
M8_AXIS_TVALID => M8_AXIS_TVALID,
M8_AXIS_TREADY => M8_AXIS_TREADY,
S8_AXIS_TLAST => S8_AXIS_TLAST,
S8_AXIS_TDATA => S8_AXIS_TDATA,
S8_AXIS_TVALID => S8_AXIS_TVALID,
S8_AXIS_TREADY => S8_AXIS_TREADY,
M9_AXIS_TLAST => M9_AXIS_TLAST,
M9_AXIS_TDATA => M9_AXIS_TDATA,
M9_AXIS_TVALID => M9_AXIS_TVALID,
M9_AXIS_TREADY => M9_AXIS_TREADY,
S9_AXIS_TLAST => S9_AXIS_TLAST,
S9_AXIS_TDATA => S9_AXIS_TDATA,
S9_AXIS_TVALID => S9_AXIS_TVALID,
S9_AXIS_TREADY => S9_AXIS_TREADY,
M10_AXIS_TLAST => M10_AXIS_TLAST,
M10_AXIS_TDATA => M10_AXIS_TDATA,
M10_AXIS_TVALID => M10_AXIS_TVALID,
M10_AXIS_TREADY => M10_AXIS_TREADY,
S10_AXIS_TLAST => S10_AXIS_TLAST,
S10_AXIS_TDATA => S10_AXIS_TDATA,
S10_AXIS_TVALID => S10_AXIS_TVALID,
S10_AXIS_TREADY => S10_AXIS_TREADY,
M11_AXIS_TLAST => M11_AXIS_TLAST,
M11_AXIS_TDATA => M11_AXIS_TDATA,
M11_AXIS_TVALID => M11_AXIS_TVALID,
M11_AXIS_TREADY => M11_AXIS_TREADY,
S11_AXIS_TLAST => S11_AXIS_TLAST,
S11_AXIS_TDATA => S11_AXIS_TDATA,
S11_AXIS_TVALID => S11_AXIS_TVALID,
S11_AXIS_TREADY => S11_AXIS_TREADY,
M12_AXIS_TLAST => M12_AXIS_TLAST,
M12_AXIS_TDATA => M12_AXIS_TDATA,
M12_AXIS_TVALID => M12_AXIS_TVALID,
M12_AXIS_TREADY => M12_AXIS_TREADY,
S12_AXIS_TLAST => S12_AXIS_TLAST,
S12_AXIS_TDATA => S12_AXIS_TDATA,
S12_AXIS_TVALID => S12_AXIS_TVALID,
S12_AXIS_TREADY => S12_AXIS_TREADY,
M13_AXIS_TLAST => M13_AXIS_TLAST,
M13_AXIS_TDATA => M13_AXIS_TDATA,
M13_AXIS_TVALID => M13_AXIS_TVALID,
M13_AXIS_TREADY => M13_AXIS_TREADY,
S13_AXIS_TLAST => S13_AXIS_TLAST,
S13_AXIS_TDATA => S13_AXIS_TDATA,
S13_AXIS_TVALID => S13_AXIS_TVALID,
S13_AXIS_TREADY => S13_AXIS_TREADY,
M14_AXIS_TLAST => M14_AXIS_TLAST,
M14_AXIS_TDATA => M14_AXIS_TDATA,
M14_AXIS_TVALID => M14_AXIS_TVALID,
M14_AXIS_TREADY => M14_AXIS_TREADY,
S14_AXIS_TLAST => S14_AXIS_TLAST,
S14_AXIS_TDATA => S14_AXIS_TDATA,
S14_AXIS_TVALID => S14_AXIS_TVALID,
S14_AXIS_TREADY => S14_AXIS_TREADY,
M15_AXIS_TLAST => M15_AXIS_TLAST,
M15_AXIS_TDATA => M15_AXIS_TDATA,
M15_AXIS_TVALID => M15_AXIS_TVALID,
M15_AXIS_TREADY => M15_AXIS_TREADY,
S15_AXIS_TLAST => S15_AXIS_TLAST,
S15_AXIS_TDATA => S15_AXIS_TDATA,
S15_AXIS_TVALID => S15_AXIS_TVALID,
S15_AXIS_TREADY => S15_AXIS_TREADY,
ICACHE_FSL_IN_CLK => ICACHE_FSL_IN_CLK,
ICACHE_FSL_IN_READ => ICACHE_FSL_IN_READ,
ICACHE_FSL_IN_DATA => ICACHE_FSL_IN_DATA,
ICACHE_FSL_IN_CONTROL => ICACHE_FSL_IN_CONTROL,
ICACHE_FSL_IN_EXISTS => ICACHE_FSL_IN_EXISTS,
ICACHE_FSL_OUT_CLK => ICACHE_FSL_OUT_CLK,
ICACHE_FSL_OUT_WRITE => ICACHE_FSL_OUT_WRITE,
ICACHE_FSL_OUT_DATA => ICACHE_FSL_OUT_DATA,
ICACHE_FSL_OUT_CONTROL => ICACHE_FSL_OUT_CONTROL,
ICACHE_FSL_OUT_FULL => ICACHE_FSL_OUT_FULL,
DCACHE_FSL_IN_CLK => DCACHE_FSL_IN_CLK,
DCACHE_FSL_IN_READ => DCACHE_FSL_IN_READ,
DCACHE_FSL_IN_DATA => DCACHE_FSL_IN_DATA,
DCACHE_FSL_IN_CONTROL => DCACHE_FSL_IN_CONTROL,
DCACHE_FSL_IN_EXISTS => DCACHE_FSL_IN_EXISTS,
DCACHE_FSL_OUT_CLK => DCACHE_FSL_OUT_CLK,
DCACHE_FSL_OUT_WRITE => DCACHE_FSL_OUT_WRITE,
DCACHE_FSL_OUT_DATA => DCACHE_FSL_OUT_DATA,
DCACHE_FSL_OUT_CONTROL => DCACHE_FSL_OUT_CONTROL,
DCACHE_FSL_OUT_FULL => DCACHE_FSL_OUT_FULL
);
end architecture STRUCTURE;
|
-- Top level of the com block, contains the flow to com and com to flow mux.
-- Also instantiates the flow to com and com to flow block.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.com_package.all;
entity com is
generic (
FIFO_IN_N : integer := 4;
FIFO_IN_ID : fifo_ID := ("000001","000010","000011",x"000100",others=>"000000");
FIFO_IN_SIZE : fifo_size := (2048,1024,2048,512,others=>0);
ONE_PACKET : integer := 1450;
FIFO_OUT_N : integer := 3;
FIFO_OUT_ID : fifo_ID := ("110000","100001","100010",others=>x"100000");--- the first one is the master ID
FIFO_OUT_SIZE : fifo_size := (512,1024,others=>0)
);
port (
clk_hal : in std_logic;
clk_proc : in std_logic;
reset_n : in std_logic;
--- From flows in to HAL
data_o : out std_logic_vector(7 downto 0);
data_size_o : out std_logic_vector(15 downto 0);
read_data_i : in std_logic;
ready_o : out std_logic;
hal_ready : in std_logic;
--- Flow to master
flow_master : out flow_t;
--- From HAL to flows out
data_i : in std_logic_vector(7 downto 0);
write_i : in std_logic;
--- Flows in and out
flow_in0 : in flow_t;
flow_in1 : in flow_t;
flow_in2 : in flow_t;
flow_in3 : in flow_t;
flow_out0 : out flow_t;
flow_out1 : out flow_t;
--- Parameters from slave
enable_eth : in std_logic;
enable_in0 : in std_logic;
enable_in1 : in std_logic;
enable_in2 : in std_logic;
enable_in3 : in std_logic
);
end com;
architecture RTL of com is
----- Signals for fifos receiving flows (flow_to_com)
signal ready : array_std_logic;
signal enable_i : array_std_logic;
signal read_data : array_std_logic;
signal fifo_in_flow_i : array_flow_t;
signal data : array_bus8;
signal data_size : array_bus16;
signal count_in,count_in_dl : integer range 0 to fifo_in_N-1;
signal HAL_busy_dl : std_logic;
signal wait_for_hal : std_logic;
signal ready_dl,ready_s : std_logic;
signal hal_ready_dl : std_logic;
----- Signals for fifos sending flows (com_to_flow)
signal enable_o : std_logic;
signal fifo_out_flow_o : array_flow_t;
begin
---------------------------------------------------------------------------------------------------------
-------------------------- FLOW_TO_COM_MUX
---------------------------------------------------------------------------------------------------------
----- Checking ready signals from fifos receiving flows
process(clk_hal,reset_n)
begin
if reset_n ='0' then
count_in <= 0;
wait_for_hal <= '0';
elsif clk_hal'event and clk_hal='1' then
ready_dl <= ready(count_in);
if ready(count_in)='0' and ready_dl='1' then
wait_for_hal <= '1';
elsif wait_for_hal='1' and hal_ready='1' then --- Increment count between each packet sent
wait_for_hal <= '0';
count_in <= count_in+1;
elsif wait_for_hal='0' and hal_ready='1' and ready(count_in)='0' and read_data_i='0' then --- Increment when flow not ready
count_in <= count_in+1;
end if;
end if;
end process;
ready_s <= '0' when wait_for_hal='1' else ready(count_in);
ready_o <= ready_s;
data_o <= data(count_in);
data_size_o <= data_size(count_in);
read_data(count_in) <= read_data_i;
----- Instantiating fifo receiving flows
flow_to_com_gen : for i in 0 to FIFO_IN_N-1 generate
flow_to_com_inst : entity work.flow_to_com
generic map (
ID_FIFO => fifo_in_ID(i),
FIFO_DEPTH => fifo_in_size(i),
ONE_PACKET => (ONE_PACKET)
)
port map (
clk_hal => clk_hal,
clk_proc => clk_proc,
reset_n => reset_n,
enable => enable_i(i),
flow_in => fifo_in_flow_i(i),
data_size => data_size(i),
read_data => read_data(i),
ready => ready(i),
data_out => data(i)
);
end generate flow_to_com_gen;
------------à generer
fifo_in_flow_i(0) <= flow_in0;
fifo_in_flow_i(1) <= flow_in1;
fifo_in_flow_i(2) <= flow_in2;
fifo_in_flow_i(3) <= flow_in3;
---------------------------------------------------------------------------------------------------------
-------------------------- COM_TO_FLOW_MUX
---------------------------------------------------------------------------------------------------------
----- Instantiating com_to_flows blocks
com_to_flow_gen : for i in 0 to FIFO_OUT_N-1 generate
com_to_flow_inst : entity work.com_to_flow
generic map (
ID_FIFO => fifo_out_ID(i),
FIFO_DEPTH => fifo_out_size(i))
port map (
clk_hal => clk_hal,
clk_proc => clk_proc,
reset_n => reset_n,
enable => enable_o,
flow_out => fifo_out_flow_o(i),
write_data => write_i,
data_in => data_i
);
end generate com_to_flow_gen;
flow_master <= fifo_out_flow_o(0);
flow_out0 <= fifo_out_flow_o(1);
flow_out1 <= fifo_out_flow_o(2);
----- Enable flows in and out
enable_i(0) <= enable_eth and enable_in0;
enable_i(1) <= enable_eth and enable_in1;
enable_i(2) <= enable_eth and enable_in2;
enable_i(3) <= enable_eth and enable_in3;
enable_o <= '1';
end RTL;
|
architecture rtl of fifo is
begin
process begin
report "hello";
report "hello";
end process;
end architecture rtl;
|
----------------------------------------------------------------------
-- brdConst_pkg (for SmartFusion(1) Evaluation Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constants
-- Handling examples :
-- constant c_lex : std_logic := BRD_LED_POL;
-- constant c_pbx : std_logic := BRD_BTN_POL;
--
-- LED0 <= c_lex xor s_led(0);
-- LED2 <= c_lex; -- force idle LEDs OFF on all boards
-- s_pb1 <= c_pbx xor PB1; -- force '1' only if pressed
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
package brdConst_pkg is
constant BRD_OSC_CLK_MHZ : positive;
constant BRD_LED_POL : std_logic;
constant BRD_BTN_POL : std_logic;
end brdConst_pkg;
----------------------------------------------------------------------
package body brdConst_pkg is
-- Frequency of signal o_clk from brdRstClk to system
--constant BRD_OSC_CLK_MHZ : positive := 100_000_000; -- direct
constant BRD_OSC_CLK_MHZ : positive := 50_000_000; -- divided
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
constant BRD_LED_POL : std_logic := '0';
-- polarity of push button switches
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
constant BRD_BTN_POL : std_logic := '0';
end brdConst_pkg;
----------------------------------------------------------------------
|
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity fsm is
port(
clock : in std_logic;
reset : in std_logic;
--prog interface
instr_next : in instruction;
step : out std_logic;
--uut interface
cp_ok : in std_logic;
stdin_rdy : in std_logic;
stdin_ack : in std_logic;
reset_fsm : out std_logic;
start : out std_logic;
cp_en : out std_logic;
cp_rest : out std_logic;
--ram interface
ram_1 : out ram_instruction;
ram_2 : out ram_instruction;
--assert_uut interface
context_uut : out context_t;
en_feed : out std_logic;
en_check : out std_logic;
vecs_found : in std_logic;
vec_read : in std_logic;
--tb interface
stopped : out std_logic
);
end fsm;
architecture rtl of fsm is
-- read output
signal step_sig : std_logic;
-- FSM signals
signal instr_c : instruction := instr_rst;
signal instr_n : instruction := instr_rst;
-- TIMER signal
signal times_en : std_logic := '0';
signal times_z : std_logic := '0';
signal times : unsigned(ARG_WIDTH - 1 downto 0);
signal times_max : unsigned(ARG_WIDTH - 1 downto 0);
signal times_ok : std_logic := '0';
-- COUNTER signal
signal count_en : std_logic := '0';
signal count_z : std_logic := '0';
signal count : unsigned(ARG_WIDTH - 1 downto 0);
signal count_max : unsigned(ARG_WIDTH - 1 downto 0);
signal count_ok : std_logic := '0';
-- runtime counter
signal runtime_en : std_logic := '0';
signal runtime : integer range 0 to 99999999; --100 million cycles
begin
-- FSM
state_reg : process (clock, reset) is
begin
if (reset = '1') then
instr_c <= instr_rst;
elsif rising_edge(clock) then
instr_c <= instr_n;
end if;
end process state_reg;
comb_logic: process(instr_next, instr_c, stdin_rdy, count_ok, times_ok, cp_ok, stdin_ack, vecs_found, vec_read)
begin
--default definition for fsm control signals
instr_n <= instr_rst;
step_sig <= '0';
--top
reset_fsm <= '0';
start <= '0';
cp_en <= '0';
cp_rest <= '0';
--counter & timer
times_en <= '0';
times_max <= (others => '0');
count_en <= '0';
count_max <= (others => '0');
--runtime counter
runtime_en <= '0';
--ram
ram_1 <= ram_instr_z;
ram_2 <= ram_instr_z;
--assert_uut
en_feed <= '0';
en_check <= '0';
--tb interface
stopped <= '0';
case instr_c.state is
when Rst =>
--signals
reset_fsm <= '1';
ram_1.addr_z <= '1';
ram_2.addr_z <= '1';
step_sig <= '1'; --demand for next instruction
--transition
instr_n <= instr_next;
when Sig_start =>
--signals
start <= '1';
step_sig <= '1'; --demand for next instruction
--transition
instr_n <= instr_next;
--if (instr_next.state = Ack_data) then
--en_feed <= '1';
--end if;
when Ack_data =>
times_max <= instr_c.arg - 1;
--signals
en_feed <= '1';
--transition
if (stdin_rdy = '1' and stdin_ack = '1') then
times_en <= '1';
end if;
if (times_ok = '1') then
en_feed <= '0';
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Running =>
--signals
count_max <= instr_c.arg;
count_en <= '1';
--en_check <= '1';
--runtime counter
if(vecs_found = '0') then
runtime_en <= '1';
end if;
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Waitfor =>
--signals
count_max <= instr_c.arg;
en_check <= '1';
if(vec_read = '1') then
count_en <= '1';
end if;
--runtime counter
if(vecs_found = '0') then
runtime_en <= '1';
end if;
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Cp_search =>
--signals
cp_en <= '1';
--transition
if (cp_ok = '1') then
case instr_c.context_uut is
when "01" =>
ram_1.we <= '1';
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.we <= '1';
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
instr_n <= (state => Cp_save, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
else
instr_n <= instr_c;
end if;
when Cp_save =>
--signals
cp_en <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.we <= '1';
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.we <= '1';
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
if (cp_ok = '0') then
case instr_c.context_uut is
when "01" =>
ram_1.we <= '0';
ram_1.addr_up <= '0';
when "10" =>
ram_2.we <= '0';
ram_2.addr_up <= '0';
when others =>
end case;
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Idle =>
--signals
count_max <= instr_c.arg;
count_en <= '1';
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Rst_uut =>
--signals
reset_fsm <= '1';
ram_1.addr_z <= '1';
ram_2.addr_z <= '1';
--transition
step_sig <= '1';
instr_n <= instr_next;
when Rest_ini0 =>
--signals
start <= '1';
cp_en <= '1';
cp_rest <= '1';
--this is for restoration : reading the first word of the right memory
case instr_c.context_uut is
when "01" =>
ram_1.sel <= '1';
when "10" =>
ram_2.sel <= '1';
when others =>
end case;
--transition
instr_n <= (state => Rest_ini1, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
when Rest_ini1 =>
--signals
cp_en <= '1';
cp_rest <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
instr_n <= (state => Rest, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
when Rest =>
--signals
cp_en <= '1';
cp_rest <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
if (cp_ok = '0') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Stop =>
--signals
stopped <= '1';
reset_fsm <= '1';
report "RUNTIME:" & integer'image(runtime);
assert (vecs_found = '0')
report "END_OF_SIM ---> Stop state reached, some output vectors were read." severity note;
--transition
instr_n <= (state => Stop, context_uut => "00", arg => (others => '0')); --hard coded
when others =>
end case;
end process comb_logic;
--*ER reset combo logic
--if a step_sig signal is sent, it means a instr_next will be consumed
reseter : process(step_sig)
begin
if (step_sig = '0') then
times_z <= '0';
count_z <= '0';
else
times_z <= '1';
count_z <= '1';
end if;
end process reseter;
--TIMER
timer : process(clock, reset)
begin
if (reset = '1') then
times <= (others => '0');
times_ok <= '0';
elsif rising_edge(clock) then
if (times_z = '1') then
times <= (others => '0');
times_ok <= '0';
else
if (times_en = '1') then
times <= times + 1;
if (times = times_max) then
times_ok <= '1';
else
times_ok <= '0';
end if;
end if;
end if;
end if;
end process timer;
--COUNTER
counter : process(clock, reset)
begin
if (reset = '1') then
count <= (others => '0');
count_ok <= '0';
elsif rising_edge(clock) then
--count_ok driving if
if (count_z = '1') then
count_ok <= '0';
count <= (others => '0');
else
if (count = count_max) then
count_ok <= '1';
else
count_ok <= '0';
if (count_en = '1') then
count <= count + 1;
end if;
end if;
end if;
end if;
end process counter;
--Runtime counter
runtime_counter : process(clock, reset)
begin
if (reset = '1') then
runtime <= 0;
elsif rising_edge(clock) then
if (runtime_en = '1') then
runtime <= runtime + 1;
if ((runtime mod 1000) = 0) then
report "Running since:" & integer'image(runtime) severity note;
end if;
end if;
end if;
end process runtime_counter;
-- process only used for reporting current instruction
reporter : process(instr_c)
begin
--report "Instruction: " & state_t'image(instr_c.state) severity note;
report "Instruction: " & state_t'image(instr_c.state) & " (context " & integer'image(to_integer(unsigned(instr_c.context_uut))) & ")" severity note;
end process reporter;
--Combinational
step <= step_sig;
context_uut <= instr_c.context_uut;
end rtl;
|
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity fsm is
port(
clock : in std_logic;
reset : in std_logic;
--prog interface
instr_next : in instruction;
step : out std_logic;
--uut interface
cp_ok : in std_logic;
stdin_rdy : in std_logic;
stdin_ack : in std_logic;
reset_fsm : out std_logic;
start : out std_logic;
cp_en : out std_logic;
cp_rest : out std_logic;
--ram interface
ram_1 : out ram_instruction;
ram_2 : out ram_instruction;
--assert_uut interface
context_uut : out context_t;
en_feed : out std_logic;
en_check : out std_logic;
vecs_found : in std_logic;
vec_read : in std_logic;
--tb interface
stopped : out std_logic
);
end fsm;
architecture rtl of fsm is
-- read output
signal step_sig : std_logic;
-- FSM signals
signal instr_c : instruction := instr_rst;
signal instr_n : instruction := instr_rst;
-- TIMER signal
signal times_en : std_logic := '0';
signal times_z : std_logic := '0';
signal times : unsigned(ARG_WIDTH - 1 downto 0);
signal times_max : unsigned(ARG_WIDTH - 1 downto 0);
signal times_ok : std_logic := '0';
-- COUNTER signal
signal count_en : std_logic := '0';
signal count_z : std_logic := '0';
signal count : unsigned(ARG_WIDTH - 1 downto 0);
signal count_max : unsigned(ARG_WIDTH - 1 downto 0);
signal count_ok : std_logic := '0';
-- runtime counter
signal runtime_en : std_logic := '0';
signal runtime : integer range 0 to 99999999; --100 million cycles
begin
-- FSM
state_reg : process (clock, reset) is
begin
if (reset = '1') then
instr_c <= instr_rst;
elsif rising_edge(clock) then
instr_c <= instr_n;
end if;
end process state_reg;
comb_logic: process(instr_next, instr_c, stdin_rdy, count_ok, times_ok, cp_ok, stdin_ack, vecs_found, vec_read)
begin
--default definition for fsm control signals
instr_n <= instr_rst;
step_sig <= '0';
--top
reset_fsm <= '0';
start <= '0';
cp_en <= '0';
cp_rest <= '0';
--counter & timer
times_en <= '0';
times_max <= (others => '0');
count_en <= '0';
count_max <= (others => '0');
--runtime counter
runtime_en <= '0';
--ram
ram_1 <= ram_instr_z;
ram_2 <= ram_instr_z;
--assert_uut
en_feed <= '0';
en_check <= '0';
--tb interface
stopped <= '0';
case instr_c.state is
when Rst =>
--signals
reset_fsm <= '1';
ram_1.addr_z <= '1';
ram_2.addr_z <= '1';
step_sig <= '1'; --demand for next instruction
--transition
instr_n <= instr_next;
when Sig_start =>
--signals
start <= '1';
step_sig <= '1'; --demand for next instruction
--transition
instr_n <= instr_next;
--if (instr_next.state = Ack_data) then
--en_feed <= '1';
--end if;
when Ack_data =>
times_max <= instr_c.arg - 1;
--signals
en_feed <= '1';
--transition
if (stdin_rdy = '1' and stdin_ack = '1') then
times_en <= '1';
end if;
if (times_ok = '1') then
en_feed <= '0';
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Running =>
--signals
count_max <= instr_c.arg;
count_en <= '1';
--en_check <= '1';
--runtime counter
if(vecs_found = '0') then
runtime_en <= '1';
end if;
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Waitfor =>
--signals
count_max <= instr_c.arg;
en_check <= '1';
if(vec_read = '1') then
count_en <= '1';
end if;
--runtime counter
if(vecs_found = '0') then
runtime_en <= '1';
end if;
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Cp_search =>
--signals
cp_en <= '1';
--transition
if (cp_ok = '1') then
case instr_c.context_uut is
when "01" =>
ram_1.we <= '1';
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.we <= '1';
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
instr_n <= (state => Cp_save, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
else
instr_n <= instr_c;
end if;
when Cp_save =>
--signals
cp_en <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.we <= '1';
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.we <= '1';
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
if (cp_ok = '0') then
case instr_c.context_uut is
when "01" =>
ram_1.we <= '0';
ram_1.addr_up <= '0';
when "10" =>
ram_2.we <= '0';
ram_2.addr_up <= '0';
when others =>
end case;
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Idle =>
--signals
count_max <= instr_c.arg;
count_en <= '1';
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Rst_uut =>
--signals
reset_fsm <= '1';
ram_1.addr_z <= '1';
ram_2.addr_z <= '1';
--transition
step_sig <= '1';
instr_n <= instr_next;
when Rest_ini0 =>
--signals
start <= '1';
cp_en <= '1';
cp_rest <= '1';
--this is for restoration : reading the first word of the right memory
case instr_c.context_uut is
when "01" =>
ram_1.sel <= '1';
when "10" =>
ram_2.sel <= '1';
when others =>
end case;
--transition
instr_n <= (state => Rest_ini1, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
when Rest_ini1 =>
--signals
cp_en <= '1';
cp_rest <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
instr_n <= (state => Rest, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
when Rest =>
--signals
cp_en <= '1';
cp_rest <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
if (cp_ok = '0') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Stop =>
--signals
stopped <= '1';
reset_fsm <= '1';
report "RUNTIME:" & integer'image(runtime);
assert (vecs_found = '0')
report "END_OF_SIM ---> Stop state reached, some output vectors were read." severity note;
--transition
instr_n <= (state => Stop, context_uut => "00", arg => (others => '0')); --hard coded
when others =>
end case;
end process comb_logic;
--*ER reset combo logic
--if a step_sig signal is sent, it means a instr_next will be consumed
reseter : process(step_sig)
begin
if (step_sig = '0') then
times_z <= '0';
count_z <= '0';
else
times_z <= '1';
count_z <= '1';
end if;
end process reseter;
--TIMER
timer : process(clock, reset)
begin
if (reset = '1') then
times <= (others => '0');
times_ok <= '0';
elsif rising_edge(clock) then
if (times_z = '1') then
times <= (others => '0');
times_ok <= '0';
else
if (times_en = '1') then
times <= times + 1;
if (times = times_max) then
times_ok <= '1';
else
times_ok <= '0';
end if;
end if;
end if;
end if;
end process timer;
--COUNTER
counter : process(clock, reset)
begin
if (reset = '1') then
count <= (others => '0');
count_ok <= '0';
elsif rising_edge(clock) then
--count_ok driving if
if (count_z = '1') then
count_ok <= '0';
count <= (others => '0');
else
if (count = count_max) then
count_ok <= '1';
else
count_ok <= '0';
if (count_en = '1') then
count <= count + 1;
end if;
end if;
end if;
end if;
end process counter;
--Runtime counter
runtime_counter : process(clock, reset)
begin
if (reset = '1') then
runtime <= 0;
elsif rising_edge(clock) then
if (runtime_en = '1') then
runtime <= runtime + 1;
if ((runtime mod 1000) = 0) then
report "Running since:" & integer'image(runtime) severity note;
end if;
end if;
end if;
end process runtime_counter;
-- process only used for reporting current instruction
reporter : process(instr_c)
begin
--report "Instruction: " & state_t'image(instr_c.state) severity note;
report "Instruction: " & state_t'image(instr_c.state) & " (context " & integer'image(to_integer(unsigned(instr_c.context_uut))) & ")" severity note;
end process reporter;
--Combinational
step <= step_sig;
context_uut <= instr_c.context_uut;
end rtl;
|
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity fsm is
port(
clock : in std_logic;
reset : in std_logic;
--prog interface
instr_next : in instruction;
step : out std_logic;
--uut interface
cp_ok : in std_logic;
stdin_rdy : in std_logic;
stdin_ack : in std_logic;
reset_fsm : out std_logic;
start : out std_logic;
cp_en : out std_logic;
cp_rest : out std_logic;
--ram interface
ram_1 : out ram_instruction;
ram_2 : out ram_instruction;
--assert_uut interface
context_uut : out context_t;
en_feed : out std_logic;
en_check : out std_logic;
vecs_found : in std_logic;
vec_read : in std_logic;
--tb interface
stopped : out std_logic
);
end fsm;
architecture rtl of fsm is
-- read output
signal step_sig : std_logic;
-- FSM signals
signal instr_c : instruction := instr_rst;
signal instr_n : instruction := instr_rst;
-- TIMER signal
signal times_en : std_logic := '0';
signal times_z : std_logic := '0';
signal times : unsigned(ARG_WIDTH - 1 downto 0);
signal times_max : unsigned(ARG_WIDTH - 1 downto 0);
signal times_ok : std_logic := '0';
-- COUNTER signal
signal count_en : std_logic := '0';
signal count_z : std_logic := '0';
signal count : unsigned(ARG_WIDTH - 1 downto 0);
signal count_max : unsigned(ARG_WIDTH - 1 downto 0);
signal count_ok : std_logic := '0';
-- runtime counter
signal runtime_en : std_logic := '0';
signal runtime : integer range 0 to 99999999; --100 million cycles
begin
-- FSM
state_reg : process (clock, reset) is
begin
if (reset = '1') then
instr_c <= instr_rst;
elsif rising_edge(clock) then
instr_c <= instr_n;
end if;
end process state_reg;
comb_logic: process(instr_next, instr_c, stdin_rdy, count_ok, times_ok, cp_ok, stdin_ack, vecs_found, vec_read)
begin
--default definition for fsm control signals
instr_n <= instr_rst;
step_sig <= '0';
--top
reset_fsm <= '0';
start <= '0';
cp_en <= '0';
cp_rest <= '0';
--counter & timer
times_en <= '0';
times_max <= (others => '0');
count_en <= '0';
count_max <= (others => '0');
--runtime counter
runtime_en <= '0';
--ram
ram_1 <= ram_instr_z;
ram_2 <= ram_instr_z;
--assert_uut
en_feed <= '0';
en_check <= '0';
--tb interface
stopped <= '0';
case instr_c.state is
when Rst =>
--signals
reset_fsm <= '1';
ram_1.addr_z <= '1';
ram_2.addr_z <= '1';
step_sig <= '1'; --demand for next instruction
--transition
instr_n <= instr_next;
when Sig_start =>
--signals
start <= '1';
step_sig <= '1'; --demand for next instruction
--transition
instr_n <= instr_next;
--if (instr_next.state = Ack_data) then
--en_feed <= '1';
--end if;
when Ack_data =>
times_max <= instr_c.arg - 1;
--signals
en_feed <= '1';
--transition
if (stdin_rdy = '1' and stdin_ack = '1') then
times_en <= '1';
end if;
if (times_ok = '1') then
en_feed <= '0';
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Running =>
--signals
count_max <= instr_c.arg;
count_en <= '1';
--en_check <= '1';
--runtime counter
if(vecs_found = '0') then
runtime_en <= '1';
end if;
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Waitfor =>
--signals
count_max <= instr_c.arg;
en_check <= '1';
if(vec_read = '1') then
count_en <= '1';
end if;
--runtime counter
if(vecs_found = '0') then
runtime_en <= '1';
end if;
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Cp_search =>
--signals
cp_en <= '1';
--transition
if (cp_ok = '1') then
case instr_c.context_uut is
when "01" =>
ram_1.we <= '1';
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.we <= '1';
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
instr_n <= (state => Cp_save, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
else
instr_n <= instr_c;
end if;
when Cp_save =>
--signals
cp_en <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.we <= '1';
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.we <= '1';
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
if (cp_ok = '0') then
case instr_c.context_uut is
when "01" =>
ram_1.we <= '0';
ram_1.addr_up <= '0';
when "10" =>
ram_2.we <= '0';
ram_2.addr_up <= '0';
when others =>
end case;
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Idle =>
--signals
count_max <= instr_c.arg;
count_en <= '1';
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Rst_uut =>
--signals
reset_fsm <= '1';
ram_1.addr_z <= '1';
ram_2.addr_z <= '1';
--transition
step_sig <= '1';
instr_n <= instr_next;
when Rest_ini0 =>
--signals
start <= '1';
cp_en <= '1';
cp_rest <= '1';
--this is for restoration : reading the first word of the right memory
case instr_c.context_uut is
when "01" =>
ram_1.sel <= '1';
when "10" =>
ram_2.sel <= '1';
when others =>
end case;
--transition
instr_n <= (state => Rest_ini1, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
when Rest_ini1 =>
--signals
cp_en <= '1';
cp_rest <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
instr_n <= (state => Rest, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
when Rest =>
--signals
cp_en <= '1';
cp_rest <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
if (cp_ok = '0') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Stop =>
--signals
stopped <= '1';
reset_fsm <= '1';
report "RUNTIME:" & integer'image(runtime);
assert (vecs_found = '0')
report "END_OF_SIM ---> Stop state reached, some output vectors were read." severity note;
--transition
instr_n <= (state => Stop, context_uut => "00", arg => (others => '0')); --hard coded
when others =>
end case;
end process comb_logic;
--*ER reset combo logic
--if a step_sig signal is sent, it means a instr_next will be consumed
reseter : process(step_sig)
begin
if (step_sig = '0') then
times_z <= '0';
count_z <= '0';
else
times_z <= '1';
count_z <= '1';
end if;
end process reseter;
--TIMER
timer : process(clock, reset)
begin
if (reset = '1') then
times <= (others => '0');
times_ok <= '0';
elsif rising_edge(clock) then
if (times_z = '1') then
times <= (others => '0');
times_ok <= '0';
else
if (times_en = '1') then
times <= times + 1;
if (times = times_max) then
times_ok <= '1';
else
times_ok <= '0';
end if;
end if;
end if;
end if;
end process timer;
--COUNTER
counter : process(clock, reset)
begin
if (reset = '1') then
count <= (others => '0');
count_ok <= '0';
elsif rising_edge(clock) then
--count_ok driving if
if (count_z = '1') then
count_ok <= '0';
count <= (others => '0');
else
if (count = count_max) then
count_ok <= '1';
else
count_ok <= '0';
if (count_en = '1') then
count <= count + 1;
end if;
end if;
end if;
end if;
end process counter;
--Runtime counter
runtime_counter : process(clock, reset)
begin
if (reset = '1') then
runtime <= 0;
elsif rising_edge(clock) then
if (runtime_en = '1') then
runtime <= runtime + 1;
if ((runtime mod 1000) = 0) then
report "Running since:" & integer'image(runtime) severity note;
end if;
end if;
end if;
end process runtime_counter;
-- process only used for reporting current instruction
reporter : process(instr_c)
begin
--report "Instruction: " & state_t'image(instr_c.state) severity note;
report "Instruction: " & state_t'image(instr_c.state) & " (context " & integer'image(to_integer(unsigned(instr_c.context_uut))) & ")" severity note;
end process reporter;
--Combinational
step <= step_sig;
context_uut <= instr_c.context_uut;
end rtl;
|
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity fsm is
port(
clock : in std_logic;
reset : in std_logic;
--prog interface
instr_next : in instruction;
step : out std_logic;
--uut interface
cp_ok : in std_logic;
stdin_rdy : in std_logic;
stdin_ack : in std_logic;
reset_fsm : out std_logic;
start : out std_logic;
cp_en : out std_logic;
cp_rest : out std_logic;
--ram interface
ram_1 : out ram_instruction;
ram_2 : out ram_instruction;
--assert_uut interface
context_uut : out context_t;
en_feed : out std_logic;
en_check : out std_logic;
vecs_found : in std_logic;
vec_read : in std_logic;
--tb interface
stopped : out std_logic
);
end fsm;
architecture rtl of fsm is
-- read output
signal step_sig : std_logic;
-- FSM signals
signal instr_c : instruction := instr_rst;
signal instr_n : instruction := instr_rst;
-- TIMER signal
signal times_en : std_logic := '0';
signal times_z : std_logic := '0';
signal times : unsigned(ARG_WIDTH - 1 downto 0);
signal times_max : unsigned(ARG_WIDTH - 1 downto 0);
signal times_ok : std_logic := '0';
-- COUNTER signal
signal count_en : std_logic := '0';
signal count_z : std_logic := '0';
signal count : unsigned(ARG_WIDTH - 1 downto 0);
signal count_max : unsigned(ARG_WIDTH - 1 downto 0);
signal count_ok : std_logic := '0';
-- runtime counter
signal runtime_en : std_logic := '0';
signal runtime : integer range 0 to 99999999; --100 million cycles
begin
-- FSM
state_reg : process (clock, reset) is
begin
if (reset = '1') then
instr_c <= instr_rst;
elsif rising_edge(clock) then
instr_c <= instr_n;
end if;
end process state_reg;
comb_logic: process(instr_next, instr_c, stdin_rdy, count_ok, times_ok, cp_ok, stdin_ack, vecs_found, vec_read)
begin
--default definition for fsm control signals
instr_n <= instr_rst;
step_sig <= '0';
--top
reset_fsm <= '0';
start <= '0';
cp_en <= '0';
cp_rest <= '0';
--counter & timer
times_en <= '0';
times_max <= (others => '0');
count_en <= '0';
count_max <= (others => '0');
--runtime counter
runtime_en <= '0';
--ram
ram_1 <= ram_instr_z;
ram_2 <= ram_instr_z;
--assert_uut
en_feed <= '0';
en_check <= '0';
--tb interface
stopped <= '0';
case instr_c.state is
when Rst =>
--signals
reset_fsm <= '1';
ram_1.addr_z <= '1';
ram_2.addr_z <= '1';
step_sig <= '1'; --demand for next instruction
--transition
instr_n <= instr_next;
when Sig_start =>
--signals
start <= '1';
step_sig <= '1'; --demand for next instruction
--transition
instr_n <= instr_next;
--if (instr_next.state = Ack_data) then
--en_feed <= '1';
--end if;
when Ack_data =>
times_max <= instr_c.arg - 1;
--signals
en_feed <= '1';
--transition
if (stdin_rdy = '1' and stdin_ack = '1') then
times_en <= '1';
end if;
if (times_ok = '1') then
en_feed <= '0';
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Running =>
--signals
count_max <= instr_c.arg;
count_en <= '1';
--en_check <= '1';
--runtime counter
if(vecs_found = '0') then
runtime_en <= '1';
end if;
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Waitfor =>
--signals
count_max <= instr_c.arg;
en_check <= '1';
if(vec_read = '1') then
count_en <= '1';
end if;
--runtime counter
if(vecs_found = '0') then
runtime_en <= '1';
end if;
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Cp_search =>
--signals
cp_en <= '1';
--transition
if (cp_ok = '1') then
case instr_c.context_uut is
when "01" =>
ram_1.we <= '1';
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.we <= '1';
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
instr_n <= (state => Cp_save, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
else
instr_n <= instr_c;
end if;
when Cp_save =>
--signals
cp_en <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.we <= '1';
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.we <= '1';
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
if (cp_ok = '0') then
case instr_c.context_uut is
when "01" =>
ram_1.we <= '0';
ram_1.addr_up <= '0';
when "10" =>
ram_2.we <= '0';
ram_2.addr_up <= '0';
when others =>
end case;
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Idle =>
--signals
count_max <= instr_c.arg;
count_en <= '1';
--transition
if (count_ok = '1') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Rst_uut =>
--signals
reset_fsm <= '1';
ram_1.addr_z <= '1';
ram_2.addr_z <= '1';
--transition
step_sig <= '1';
instr_n <= instr_next;
when Rest_ini0 =>
--signals
start <= '1';
cp_en <= '1';
cp_rest <= '1';
--this is for restoration : reading the first word of the right memory
case instr_c.context_uut is
when "01" =>
ram_1.sel <= '1';
when "10" =>
ram_2.sel <= '1';
when others =>
end case;
--transition
instr_n <= (state => Rest_ini1, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
when Rest_ini1 =>
--signals
cp_en <= '1';
cp_rest <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
instr_n <= (state => Rest, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
when Rest =>
--signals
cp_en <= '1';
cp_rest <= '1';
case instr_c.context_uut is
when "01" =>
ram_1.addr_up <= '1';
ram_1.sel <= '1';
when "10" =>
ram_2.addr_up <= '1';
ram_2.sel <= '1';
when others =>
end case;
--transition
if (cp_ok = '0') then
step_sig <= '1';
instr_n <= instr_next;
else
instr_n <= instr_c;
end if;
when Stop =>
--signals
stopped <= '1';
reset_fsm <= '1';
report "RUNTIME:" & integer'image(runtime);
assert (vecs_found = '0')
report "END_OF_SIM ---> Stop state reached, some output vectors were read." severity note;
--transition
instr_n <= (state => Stop, context_uut => "00", arg => (others => '0')); --hard coded
when others =>
end case;
end process comb_logic;
--*ER reset combo logic
--if a step_sig signal is sent, it means a instr_next will be consumed
reseter : process(step_sig)
begin
if (step_sig = '0') then
times_z <= '0';
count_z <= '0';
else
times_z <= '1';
count_z <= '1';
end if;
end process reseter;
--TIMER
timer : process(clock, reset)
begin
if (reset = '1') then
times <= (others => '0');
times_ok <= '0';
elsif rising_edge(clock) then
if (times_z = '1') then
times <= (others => '0');
times_ok <= '0';
else
if (times_en = '1') then
times <= times + 1;
if (times = times_max) then
times_ok <= '1';
else
times_ok <= '0';
end if;
end if;
end if;
end if;
end process timer;
--COUNTER
counter : process(clock, reset)
begin
if (reset = '1') then
count <= (others => '0');
count_ok <= '0';
elsif rising_edge(clock) then
--count_ok driving if
if (count_z = '1') then
count_ok <= '0';
count <= (others => '0');
else
if (count = count_max) then
count_ok <= '1';
else
count_ok <= '0';
if (count_en = '1') then
count <= count + 1;
end if;
end if;
end if;
end if;
end process counter;
--Runtime counter
runtime_counter : process(clock, reset)
begin
if (reset = '1') then
runtime <= 0;
elsif rising_edge(clock) then
if (runtime_en = '1') then
runtime <= runtime + 1;
if ((runtime mod 1000) = 0) then
report "Running since:" & integer'image(runtime) severity note;
end if;
end if;
end if;
end process runtime_counter;
-- process only used for reporting current instruction
reporter : process(instr_c)
begin
--report "Instruction: " & state_t'image(instr_c.state) severity note;
report "Instruction: " & state_t'image(instr_c.state) & " (context " & integer'image(to_integer(unsigned(instr_c.context_uut))) & ")" severity note;
end process reporter;
--Combinational
step <= step_sig;
context_uut <= instr_c.context_uut;
end rtl;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06a is
-- code from book:
impure function now return delay_length;
-- end of code from book
impure function now return delay_length is
begin
return std.standard.now;
end function now;
-- code from book:
impure function now return real;
-- end of code from book
impure function now return real is
begin
return std.standard.now;
end function now;
end entity inline_06a;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06a is
-- code from book:
impure function now return delay_length;
-- end of code from book
impure function now return delay_length is
begin
return std.standard.now;
end function now;
-- code from book:
impure function now return real;
-- end of code from book
impure function now return real is
begin
return std.standard.now;
end function now;
end entity inline_06a;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06a is
-- code from book:
impure function now return delay_length;
-- end of code from book
impure function now return delay_length is
begin
return std.standard.now;
end function now;
-- code from book:
impure function now return real;
-- end of code from book
impure function now return real is
begin
return std.standard.now;
end function now;
end entity inline_06a;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2492.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n01i02492ent IS
END c07s03b03x00p04n01i02492ent;
ARCHITECTURE c07s03b03x00p04n01i02492arch OF c07s03b03x00p04n01i02492ent IS
BEGIN
TESTING: PROCESS
type SNACK is
range 1 to 1e8
units
fn; -- figanewton
bf = 12 fn; -- boxafiganewton
end units;
function F_SNACK ( A : REAL := 1.0;
B : INTEGER;
C : SNACK ) return SNACK is
begin
return C;
end F_SNACK;
BEGIN
PT <= F_SNACK(B=>5); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s03b03x00p04n01i02492 - Each formal parameter of a function should have exactly one actual parameter associated with it in a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n01i02492arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2492.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n01i02492ent IS
END c07s03b03x00p04n01i02492ent;
ARCHITECTURE c07s03b03x00p04n01i02492arch OF c07s03b03x00p04n01i02492ent IS
BEGIN
TESTING: PROCESS
type SNACK is
range 1 to 1e8
units
fn; -- figanewton
bf = 12 fn; -- boxafiganewton
end units;
function F_SNACK ( A : REAL := 1.0;
B : INTEGER;
C : SNACK ) return SNACK is
begin
return C;
end F_SNACK;
BEGIN
PT <= F_SNACK(B=>5); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s03b03x00p04n01i02492 - Each formal parameter of a function should have exactly one actual parameter associated with it in a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n01i02492arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2492.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n01i02492ent IS
END c07s03b03x00p04n01i02492ent;
ARCHITECTURE c07s03b03x00p04n01i02492arch OF c07s03b03x00p04n01i02492ent IS
BEGIN
TESTING: PROCESS
type SNACK is
range 1 to 1e8
units
fn; -- figanewton
bf = 12 fn; -- boxafiganewton
end units;
function F_SNACK ( A : REAL := 1.0;
B : INTEGER;
C : SNACK ) return SNACK is
begin
return C;
end F_SNACK;
BEGIN
PT <= F_SNACK(B=>5); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s03b03x00p04n01i02492 - Each formal parameter of a function should have exactly one actual parameter associated with it in a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n01i02492arch;
|
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use work.array32.all;
entity mul32booth is
port(
mr,md : in std_logic_vector(31 downto 0);
out1 : out std_logic_vector(63 downto 0)
);
end mul32booth;
architecture rtl of mul32booth is
signal outDecoder : reg_array;
signal sOutAdd : reg_array;
signal test : std_logic_vector(2 downto 0);
component RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (32 downto 0);
SomaResult: out std_logic_vector (32 downto 0);
outpart: out std_logic_vector (1 downto 0);
CarryOut: out std_logic
);
END component;
component boothDecoder is
port(
md : in std_logic_vector(31 downto 0);
decMr : in std_logic_vector(2 downto 0);
out1 : out std_logic_vector(32 downto 0)
);
end component;
begin
test <= mr(1 downto 0) & '0';
decoder1: boothDecoder PORT MAP (
md, test, outDecoder(0)
);
GDEC: for i IN 0 TO 14 generate
decoders: boothDecoder PORT MAP (
md, mr(((i*2)+3) downto ((i*2)+1)), outDecoder(i+1)
);
end generate;
adder1: RCA PORT MAP (
'0', (others => '0'), outDecoder(0), sOutAdd(0), out1(1 downto 0)
);
GSOM: for i IN 0 TO 14 generate
adders: RCA PORT MAP (
'0', sOutAdd(i), outDecoder(i+1), sOutAdd(i+1), out1(((i*2)+3) downto ((i*2)+2))
);
end generate;
out1(63 downto 32) <= sOutAdd(15)(31 downto 0);
end rtl;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_b
--
-- Generated
-- by: wig
-- on: Thu Jun 29 16:41:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-rtl-a.vhd,v 1.2 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: ent_b-rtl-a.vhd,v $
-- Revision 1.2 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- modifiy vhdl_use_arch
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
typedef vhdl_use_arch_def std_ulogic_vector;
-- end of vhdl_use_arch
--
--
-- Start of Generated Architecture rtl of ent_b
--
architecture rtl of ent_b is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_ba
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ent_bb
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
Use macro vhdl_hook_arch_body
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba
inst_ba: ent_ba
;
-- End of Generated Instance Port Map for inst_ba
-- Generated Instance Port Map for inst_bb
inst_bb: ent_bb
;
-- End of Generated Instance Port Map for inst_bb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.s_1164.all;
entity clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic := '0');
end clkgen;
architecture behav of clkgen is
begin
process
begin
clk <= not clk;
wait for period / 2;
end process;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : std_logic;
signal rst_n : std_logic;
signal din, dout, dout2 : std_logic_vector (7 downto 0);
component clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic);
end component;
begin
cclk : clkgen
generic map (period => 20 ns)
port map (clk => clk);
rst_n <= '0' after 0 ns, '1' after 4 ns;
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else q <= d;
end if;
end if;
end process p;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report 2start of tb" severity note;
for i in 0 to 10 loop
group i is
when 0 | 3 =>
for i in din'range loop
din(i) <= '0';
end loop;
when 1 => din <= b"00110011";
when 2 =>ehav;
|
--Practica5 de Diseño Automatico de Sistemas
--Piano Electronico.
--Altavoz.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity speaker is
port(
clk : in std_logic;
rst : in std_logic;
note_in : in std_logic_vector (7 downto 0);
new_data : in std_logic;
sound : out std_logic;
ack : out std_logic;
sound_active : out std_logic_vector (7 downto 0)
);
end speaker;
architecture rtl of speaker is
component gen_onda is
port(
clk : in std_logic;
rst : in std_logic;
note_in : in std_logic_vector(17 downto 0);
clear : in std_logic;
onda_out : out std_logic
);
end component;
type states_piano is (wait_press,state_f0,wait_depress);
signal current_state,next_state : states_piano;
signal n : std_logic_vector(18 downto 0);
signal silence : std_logic;
signal note_out :std_logic;
signal clear_s,load_note,clear_note : std_logic;
signal reg_note : std_logic_vector (7 downto 0);
begin
--rom memory
n <= "0101110101010011010" when reg_note = x"1c" else--a
"0101100000010010110" when reg_note = x"1d" else--w
"0101001000110011110" when reg_note = x"1b" else--s
"0100111001111001111" when reg_note = x"24" else--e
"0100101000010010010" when reg_note = x"23" else--d
"0100010111101001111" when reg_note = x"2b" else--f
"0100000111111011110" when reg_note = x"2c" else--t
"0011111001000111110" when reg_note = x"34" else--g
"0011101011001001010" when reg_note = x"35" else--y
"0011011101111100011" when reg_note = x"33" else--h
"0011010001011110001" when reg_note = x"3c" else--u
"0011000101101110010" when reg_note = x"3b" else--j
"0010111010100111010" when reg_note = x"42" else--k
"1000000000000000000";
p_state : process(clk,rst)
begin
if (rst = '0') then
current_state <= wait_press;
elsif(rising_edge(clk)) then
current_state <= next_state;
end if;
end process;
gen_state : process(current_state,reg_note,new_data)
begin
next_state <= current_state;
case current_state is
when wait_press =>
if(reg_note = x"f0") then
next_state <= state_f0;
end if;
when state_f0 =>
if(new_data = '1') then
next_state <= wait_depress;
end if;
when wait_depress =>
next_state <= wait_press;
end case;
end process;
gen_signals : process(current_state)
begin
case current_state is
when wait_press =>
load_note <= '1';
clear_note <= '0';
when state_f0 =>
load_note <= '0';
clear_note <= '1';
when wait_depress =>
load_note <= '0';
clear_note <= '0';
end case;
end process;
reg_note_p : process(clk,rst,clear_note)
begin
if(rst = '0') then
reg_note <= x"00";
ack <= '0';
elsif(rising_edge(clk)) then
if(new_data = '1') then
if(clear_note = '1') then
reg_note <= x"00";
elsif(load_note = '1') then
reg_note <= note_in;
end if;
ack <= '1';
else
ack <= '0';
end if;
end if;
end process;
silence <= n(18);
sound_active <= reg_note;
clear_s <= '1' when reg_note /= note_in else '0';
sound <= note_out and not(silence);
u_gen_onda : gen_onda port map(clk =>clk,rst=>rst,note_in=>n(17 downto 0),clear=>clear_s,onda_out=>note_out);
end rtl;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:42 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_processing_system7_0_2_stub.vhdl
-- Design : gcd_block_design_processing_system7_0_2
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2018.2";
begin
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:06:05 07/16/2014
-- Design Name:
-- Module Name: cipher_cu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cipher_cu is
port(
clk : in std_logic;
reset : in std_logic;
x_start : in std_logic; -- start encryption
x_comp : in std_logic; -- '1' if last round is reached
y_1_2 : out std_logic_vector(1 downto 0); -- controlling values for cipher
y_3_4 : out std_logic_vector(1 downto 0); -- controlling values for counter
y_end : out std_logic -- encryption finished
);
end cipher_cu;
architecture Behavioral of cipher_cu is
type States is (S0, S1, S2, S3, S4, S5);
signal S, S_next : States;
begin
delta : process (S, x_start, x_comp)
begin
case S is
when S0 => y_1_2 <="--";
y_3_4 <="00"; -- initialize counter
y_end <= '0';
if x_start = '1' then
S_next <= S1;
else
S_next <= S0;
end if;
when S1 => y_1_2 <= "--"; -- round key 0 not yet available (due to synchonous read)
y_3_4 <= "01"; -- increment counter
y_end <= '0';
S_next <= S2;
when S2 => y_1_2 <= "00"; -- load in plaintext (round key 0 now available)
y_3_4 <= "01"; -- increment counter
y_end <= '0';
S_next <= S3;
when S3 => y_1_2 <= "01"; -- include mix columns stage
y_3_4 <= "01";
y_end <= '0';
if x_comp = '1' then
S_next <= S4; -- last round starts after the next cycle
else
S_next <= S3;
end if;
when S4 => y_1_2 <= "10"; -- leave out mix columns stage
y_3_4 <= "--";
y_end <= '0';
S_next <= S5;
when S5 => y_1_2 <= "--";
y_3_4 <= "--";
y_end <= '1'; -- finished (output valid for one cycle)
S_next <= S0;
end case;
end process delta;
feedback_loop : process (clk, reset, S_next)
begin
if reset = '1' then
S <= S0;
elsif rising_edge(clk) then
S <= S_next;
end if;
end process feedback_loop;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ok_1_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ok_1_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_ok_1_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ok_1_e
--
architecture rtl of inst_ok_1_e is
#
# Generated Constant Declarations
#
#
# Generated Components
#
#
# Generated Signal List
#
#
# End of Generated Signal List
#
begin
--
-- Generated Concurrent Statements
--
#
# Generated Signal Assignments
#
#
# Generated Instances and Port Mappings
#
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: txreg_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.txreg_pkg.ALL;
ENTITY txreg_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF txreg_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:txreg_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:txreg_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbp
-- File: ahbtbp.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AHB Testbench package
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
package ahbtbp is
type ahbtbm_ctrl_type is record
delay : std_logic_vector(7 downto 0);
dbgl : integer;
reset : std_logic;
use128 : integer;
end record;
type ahbtbm_access_type is record
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hdata128 : std_logic_vector(127 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hprot : std_logic_vector(3 downto 0);
hwrite : std_logic;
ctrl : ahbtbm_ctrl_type;
end record;
type ahbtbm_status_type is record
err : std_logic;
ecount : std_logic_vector(15 downto 0);
eaddr : std_logic_vector(31 downto 0);
edatac : std_logic_vector(31 downto 0);
edatar : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
end record;
type ahbtbm_access_array_type is array (0 to 1) of ahbtbm_access_type;
type ahbtbm_ctrl_in_type is record
ac : ahbtbm_access_type;
end record;
type ahbtbm_ctrl_out_type is record
rst : std_logic;
clk : std_logic;
update : std_logic;
dvalid : std_logic;
hrdata : std_logic_vector(31 downto 0);
hrdata128 : std_logic_vector(127 downto 0);
status : ahbtbm_status_type;
end record;
type ahbtb_ctrl_type is record
i : ahbtbm_ctrl_in_type;
o : ahbtbm_ctrl_out_type;
end record;
constant ac_idle : ahbtbm_access_type :=
(haddr => x"00000000", hdata => x"00000000",
hdata128 => x"00000000000000000000000000000000",
htrans => "00", hburst =>"000", hsize => "000", hprot => "0000", hwrite => '0',
ctrl => (delay => x"00", dbgl => 100, reset =>'0', use128 => 0));
constant ctrli_idle : ahbtbm_ctrl_in_type :=(ac => ac_idle);
constant ctrlo_nodrive : ahbtbm_ctrl_out_type :=(rst => 'H', clk => 'H',
update => 'H', dvalid => 'H', hrdata => (others => 'H'), hrdata128 => (others => 'H'),
status => (err => 'H', ecount => (others => 'H'), eaddr => (others => 'H'),
edatac => (others => 'H'), edatar => (others => 'H'),
hresp => (others => 'H')));
impure function ptime return string;
-- pragma translate_off
-----------------------------------------------------------------------------
-- AHB testbench Master
-----------------------------------------------------------------------------
component ahbtbm is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := 0;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in ahbtbm_ctrl_in_type;
ctrlo : out ahbtbm_ctrl_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- AHB testbench Slave
-----------------------------------------------------------------------------
component ahbtbs is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string);
procedure dprint(
constant s : in string);
-----------------------------------------------------------------------------
-- AMBATB Init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Start address
constant data : in std_logic_vector(31 downto 0); -- Start data
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
end ahbtbp;
package body ahbtbp is
impure function ptime return string is
variable s : string(1 to 20);
variable length : integer := tost(NOW / 1 ns)'length;
begin
s(1 to length + 9) :="Time: " & tost(NOW / 1 ns) & "ns ";
return s(1 to length + 9);
end function ptime;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string) is
begin
if doprint = true then
print(s);
end if;
end procedure dprint;
procedure dprint(
constant s : in string) is
begin
print(s);
end procedure dprint;
-----------------------------------------------------------------------------
-- AHBTB init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type) is
begin
ctrl.o <= ctrlo_nodrive;
ctrl.i <= ctrli_idle;
--ctrli.ac.hburst <= "000"; ctrli.ac.hsize <= "010";
--ctrli.ac.haddr <= x"00000000"; ctrli.ac.hdata <= x"00000000";
--ctrli.ac.htrans <= "00"; ctrli.ac.hwrite <= '0';
wait until ctrl.o.rst = '1';
print("**********************************************************");
print(" AHBTBM Testbench Init");
print("**********************************************************");
end procedure ahbtbminit;
-----------------------------------------------------------------------------
-- AMBTB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
print("**********************************************************");
print(" AHBTBM Testbench Done");
print("**********************************************************");
wait for 100 ns;
assert stop = 0
report "ahbtb testbench done!"
severity FAILURE;
end procedure ahbtbmdone;
-----------------------------------------------------------------------------
-- AMBTB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
if sync = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
end if;
end procedure ahbtbmidle;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-- pragma translate_on
end ahbtbp;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY datapath_line IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
RESETX, RESETY, incr_y, incr_x, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0); -- x0
y : OUT STD_LOGIC_VECTOR(6 downto 0);
x1in : IN STD_LOGIC_VECTOR(7 downto 0); -- x1
y1in : IN STD_LOGIC_VECTOR(6 downto 0);
x0in : IN STD_LOGIC_VECTOR(7 downto 0); -- x1
y0in : IN STD_LOGIC_VECTOR(6 downto 0);
xdone, ydone, ldone : OUT STD_LOGIC
);
END datapath_line;
ARCHITECTURE mixed OF datapath_line IS
BEGIN
PROCESS(clock, resetb)
VARIABLE x_tmp : unsigned(7 downto 0) := "00000000";
VARIABLE y_tmp : unsigned(6 downto 0) := "0000000";
VARIABLE dx : signed(8 downto 0);
VARIABLE dy : signed(7 downto 0);
VARIABLE x0 : unsigned(7 downto 0) := "01010000"; -- 80
VARIABLE y0 : unsigned(6 downto 0) := "0111100"; -- 60
VARIABLE x1 : unsigned(7 downto 0) := "01010000";
VARIABLE y1 : unsigned(6 downto 0) := "0111100";
VARIABLE sx : signed(1 downto 0);
VARIABLE sy : signed(1 downto 0);
VARIABLE error : signed(8 downto 0);
VARIABLE e2 : signed(9 downto 0);
BEGIN
IF (resetb = '0') THEN
y_tmp := "0000000";
x_tmp := "00000000";
x0 := "01010000"; -- 80
y0 := "0111100"; -- 60
x1 := "01010000"; -- 80
y1 := "0111100"; -- 60
ELSIF rising_edge(clock) THEN
--initialize line
IF (initl = '1') THEN
x0 := unsigned(x0in); -- start point
y0 := unsigned(x0in);
x1 := unsigned(x1in); -- end point
y1 := unsigned(yin);
dx := to_signed(abs(to_integer(x1) - to_integer(x0)), 9);
dy := to_signed(abs(to_integer(y1) - to_integer(y0)), 8);
IF (x0 < x1) THEN
sx := to_signed(1, 2);
ELSE
sx := to_signed(-1, 2);
END IF;
IF (y0 < y1) THEN
sy := to_signed(1, 2);
ELSE
sy := to_signed(-1, 2);
END IF;
error := to_signed(to_integer(dx) - to_integer(dy), 9);
ldone <= '0';
--draw line loop
ELSIF (drawl = '1') THEN
x <= STD_LOGIC_VECTOR(x0);
y <= STD_LOGIC_VECTOR(y0);
-- Exit loop if we are at destination point
IF (x0 = x1) THEN
IF(y0 = y1) THEN
ldone <= '1';
END IF;
ELSE
e2 := signed(2*error)(9 downto 0);
IF (e2 > -dy) THEN
error := error - dy;
x0 := unsigned(signed(x0) + sx);
END IF;
IF (e2 < dx) THEN
error := error + dx;
y0 := unsigned(signed(y0) + sy);
END IF;
END IF;
--clear screen
ELSE
IF (RESETY = '1') THEN
y_tmp := "0000000";
ELSIF (INCR_Y = '1') THEN
y_tmp := y_tmp + 1;
IF (y_tmp = 119) THEN
YDONE <= '1';
ELSE
YDONE <= '0';
END IF;
END IF;
Y <= std_logic_vector(y_tmp);
IF (RESETX = '1') THEN
x_tmp := "00000000";
ELSIF (INCR_X = '1') THEN
x_tmp := x_tmp + 1;
IF (x_tmp = 159) THEN
XDONE <= '1';
ELSE
XDONE <= '0';
END IF;
END IF;
X <= std_logic_vector(x_tmp);
END IF;
END IF;
END PROCESS;
END mixed;
|
----------------------------------------------------------------------
-- Design : Counter VHDL top module, Altera CycloneIII Starter Kit
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cyclone3_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(3 downto 0)
);
end cyclone3_top;
----------------------------------------------------------------------
architecture structure of cyclone3_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= not clear_i;
s_count <= not count_i;
led_o(3 downto 0) <= not s_Q(7 downto 4);
end architecture structure;
-----------------------------------------------------------------------
|
----------------------------------------------------------------------
-- Design : Counter VHDL top module, Altera CycloneIII Starter Kit
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cyclone3_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(3 downto 0)
);
end cyclone3_top;
----------------------------------------------------------------------
architecture structure of cyclone3_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= not clear_i;
s_count <= not count_i;
led_o(3 downto 0) <= not s_Q(7 downto 4);
end architecture structure;
-----------------------------------------------------------------------
|
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5664)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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vo7JvkAsWw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5664)
`protect data_block
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`protect begin_protected
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|
--------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Feb 19, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.types.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity multiplexer is
port (
R_sel : in MVL7;
D_sel : in MVL7;
uPC_sel : in MVL7;
stack_sel : in MVL7;
OEBAR : in MVL7;
sp : in INTEGER range 0 to 5;
D : in MVL7_VECTOR(11 downto 0);
RE : in MVL7_VECTOR(11 downto 0);
uPC : in MVL7_VECTOR(11 downto 0);
Y : out MVL7_VECTOR(11 downto 0)
);
end multiplexer;
architecture multiplexer of multiplexer is
begin
-------------------------------------------------------------------------------
muxr : block
signal Y_temp : MVL7_VECTOR(11 downto 0);
signal reg_file : MEMORY_12_BIT(5 downto 0) := (
("000000000000"),
("111111111111"),
("000000000000"),
("111111111111"),
("000000000000"),
("111111111111")
);
begin
Y_temp <= RE WHEN R_sel = '1' ELSE
D WHEN D_sel = '1' ELSE
uPC WHEN uPC_sel = '1' ELSE
reg_file(sp) WHEN stack_sel = '1' ELSE
"000000000000";
Y <= Y_temp when OEbar = '0' else
"ZZZZZZZZZZZZ";
end block muxr;
-------------------------------------------------------------------------------
end multiplexer;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12528)
`protect data_block
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12528)
`protect data_block
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`protect end_protected
|
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Simple testbench for playing around with the CRC calculation code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.crc32.all;
use work.utility.all;
entity crc32_tb is
end entity;
architecture behavioral of crc32_tb is
-- "Known good" function for comparison
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8(DATA : std_ulogic_vector(7 downto 0);
CRC : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
variable D : std_ulogic_vector(7 downto 0);
variable C : std_ulogic_vector(31 downto 0);
variable NEWCRC : std_ulogic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0) := C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1) := C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(2) := C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(3) := C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(4) := C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(5) := C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6) := C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7) := C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24) xor D(7);
NewCRC(8) := C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6) xor C(24) xor D(7);
NewCRC(9) := C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5) xor C(25) xor D(6);
NewCRC(10) := C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24) xor D(7);
NewCRC(11) := C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6) xor C(24) xor D(7);
NewCRC(12) := C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13) := C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14) := C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15) := C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4);
NewCRC(16) := C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17) := C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18) := C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19) := C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20) := C(12) xor C(28) xor D(3);
NewCRC(21) := C(13) xor C(29) xor D(2);
NewCRC(22) := C(14) xor C(24) xor D(7);
NewCRC(23) := C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24) := C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25) := C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26) := C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(27) := C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(28) := C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29) := C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30) := C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31) := C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Signals as isim cannot trace variables
signal crc : t_crc32;
signal comparison_crc : t_crc32;
signal data : std_ulogic_vector(7 downto 0);
constant WAIT_PERIOD : time := 40 ns;
begin
test_crc32 : process
variable saved_crc : t_crc32;
begin
crc <= (others => '1');
comparison_crc <= (others => '1');
data <= (others => '0');
wait for WAIT_PERIOD;
for cnt in 0 to 10 loop
crc <= update_crc32(crc, data);
comparison_crc <= NEXTCRC32_D8(data, crc);
if cnt >= 7 then
data <= (others => '0');
else
data <= std_ulogic_vector(to_unsigned(cnt + 1, 8));
end if;
wait for WAIT_PERIOD;
if crc /= comparison_crc then
report "CRC mismatch" severity note;
end if;
end loop;
saved_crc := not reverse_vector(crc);
wait for 100 ns;
for j in 0 to 3 loop
crc <= update_crc32(crc, saved_crc(((j + 1) * 8) - 1 downto j * 8));
comparison_crc <= NEXTCRC32_D8(saved_crc(((j + 1) * 8) - 1 downto j * 8), crc);
wait for WAIT_PERIOD;
end loop;
--crc <= reverse_vector(crc);
wait for WAIT_PERIOD;
if crc /= X"C704dd7B" then
report "Final CRC wrong" severity note;
end if;
wait;
end process;
end architecture;
|
library IEEE, STD;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_1164.all;
entity ledramp_tb is
end ledramp_tb;
architecture tb_arch of ledramp_tb is
-- UUT component
component ledramp
generic (
PWM_RANGE_MAX : integer := 5000000
);
port (
clk : in std_logic;
ramp : out std_logic_vector(7 downto 0)
);
end component;
-- I/O signals
signal clk : std_logic := '0';
signal ramp : std_logic_vector(7 downto 0);
-- Constant declarations
constant CLK_PERIOD : time := 20 ns;
-- Declare results file
file ResultsFile: text open write_mode is "ledramp_results.txt";
begin
uut : ledramp
generic map (
PWM_RANGE_MAX => 1000
)
port map (
clk => clk,
ramp => ramp
);
CLK_GEN_PROC: process(clk)
begin
if (clk = '0') then
clk <= '1';
else
clk <= not clk after CLK_PERIOD/2;
end if;
end process CLK_GEN_PROC;
process (clk)
variable line_el: line;
variable ramp_ext : std_logic_vector(7 downto 0);
begin
if rising_edge(clk) then
-- Write the time
write(line_el, now); -- write the line
write(line_el, ':'); -- write the line
-- Write the ramp signal
write(line_el, ' ');
write(line_el, ramp); -- write the line
writeline(ResultsFile, line_el); -- write the contents into the file
end if;
end process;
end tb_arch;
|
-- This is the implementation of a constant delay
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
package const_delay_pkg is
component const_delay
generic(
data_width : integer;
delay_in_clks : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end const_delay_pkg;
package body const_delay_pkg is
end const_delay_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
entity const_delay is
generic(
data_width : integer := 16;
delay_in_clks : integer := 10
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end const_delay;
architecture const_delay_arch of const_delay is
type register_line is array(0 to delay_in_clks-1) of std_logic_vector(data_width-1 downto 0);
type data_str_line is array(0 to delay_in_clks-1) of std_logic;
signal data_int : register_line;
signal data_str_int : data_str_line;
begin
process (clk_i, rst_i)
begin
if rst_i = '1' then
for i in 0 to delay_in_clks-1 loop
data_int(i) <= (others => '0');
data_str_int(i) <= '0';
end loop;
elsif clk_i'EVENT and clk_i = '1' then
data_int(0) <= data_i;
data_str_int(0) <= data_str_i;
for i in 0 to delay_in_clks-2 loop
data_int(i+1) <= data_int(i);
data_str_int(i+1) <= data_str_int(i);
end loop;
end if;
end process;
data_o <= data_int(delay_in_clks-1);
data_str_o <= data_str_int(delay_in_clks-1);
end const_delay_arch; |
-- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______200.000____150.000
-- CLK_OUT2____25.000______0.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
CLK50 : in std_logic;
-- Clock out ports
CLK : out std_logic;
VGA_CLK : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
end clock;
architecture xilinx of clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock,clk_wiz_v3_3,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out1_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK50);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
clkfb <= clk_out1_internal;
clkout1_buf : BUFG
port map
(O => clk_out1_internal,
I => clk0);
CLK <= clk_out1_internal;
clkout2_buf : BUFG
port map
(O => VGA_CLK,
I => clkdv);
end xilinx;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_gray_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_gray_rows_V_shiftReg;
architecture rtl of FIFO_image_filter_gray_rows_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_gray_rows_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_gray_rows_V is
component FIFO_image_filter_gray_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_gray_rows_V_shiftReg : FIFO_image_filter_gray_rows_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_gray_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_gray_rows_V_shiftReg;
architecture rtl of FIFO_image_filter_gray_rows_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_gray_rows_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_gray_rows_V is
component FIFO_image_filter_gray_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_gray_rows_V_shiftReg : FIFO_image_filter_gray_rows_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity comparator is
port (
a_31 : in std_logic;
b_31 : in std_logic;
diff_31 : in std_logic;
carry : in std_logic;
zero : in std_logic;
op : in std_logic_vector( 2 downto 0);
r : out std_logic
);
end comparator;
architecture synth of comparator is
begin
process (op, zero, carry, a_31, b_31, diff_31)
begin
-- all bits to 0
r <= zero;
-- here we modify only the least significant bit.
case op is
-- >=
when "001" =>
-- take care to surround all logical operation with parenthesis:
-- there's no priority between them.
r <= (not a_31 and b_31) or ((not a_31 xor b_31) and not diff_31);
-- <
when "010" =>
r <= (a_31 and not b_31) or ((not a_31 xor b_31) and diff_31);
-- !=
when "011" => r <= not zero;
-- >= unsigned
when "101" => r <= carry;
-- < unsigned
when "110" => r <= not carry;
-- 0, 4, 7: =
when others => r <= zero;
end case;
end process;
end synth;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Mon Mar 20 20:54:09 2017
--Host : N73-PC running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1RZ0IW6 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_1RZ0IW6;
architecture STRUCTURE of m00_couplers_imp_1RZ0IW6 is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1TEAG88 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC;
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC;
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1TEAG88;
architecture STRUCTURE of m00_couplers_imp_1TEAG88 is
component system_auto_cc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component system_auto_cc_0;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_cc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 27 downto 0 );
signal auto_cc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_cc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_cc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_cc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 27 downto 0 );
signal auto_cc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_cc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_cc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_cc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_cc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_cc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal auto_cc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_m00_couplers_RLAST : STD_LOGIC;
signal auto_cc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_cc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_cc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal auto_cc_to_m00_couplers_WLAST : STD_LOGIC;
signal auto_cc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_cc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal auto_cc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_cc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_cc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_cc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_cc_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_cc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_cc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_cc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_cc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_cc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_cc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_cc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_cc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_cc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_cc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_cc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_cc_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_cc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_cc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_cc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_cc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_cc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_cc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_cc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_cc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_cc_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_cc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_cc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_cc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_cc_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal m00_couplers_to_auto_cc_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_cc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_cc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_cc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_cc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_cc_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal m00_couplers_to_auto_cc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_cc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_cc_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal m00_couplers_to_auto_cc_WVALID : STD_LOGIC;
signal NLW_auto_cc_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_cc_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1 <= M_ARESETN;
M_AXI_araddr(27 downto 0) <= auto_cc_to_m00_couplers_ARADDR(27 downto 0);
M_AXI_arburst(1 downto 0) <= auto_cc_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_cc_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= auto_cc_to_m00_couplers_ARID(0);
M_AXI_arlen(7 downto 0) <= auto_cc_to_m00_couplers_ARLEN(7 downto 0);
M_AXI_arlock <= auto_cc_to_m00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_cc_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_cc_to_m00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_cc_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_cc_to_m00_couplers_ARVALID;
M_AXI_awaddr(27 downto 0) <= auto_cc_to_m00_couplers_AWADDR(27 downto 0);
M_AXI_awburst(1 downto 0) <= auto_cc_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_cc_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= auto_cc_to_m00_couplers_AWID(0);
M_AXI_awlen(7 downto 0) <= auto_cc_to_m00_couplers_AWLEN(7 downto 0);
M_AXI_awlock <= auto_cc_to_m00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_cc_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_cc_to_m00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_cc_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_cc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_cc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_cc_to_m00_couplers_RREADY;
M_AXI_wdata(127 downto 0) <= auto_cc_to_m00_couplers_WDATA(127 downto 0);
M_AXI_wlast <= auto_cc_to_m00_couplers_WLAST;
M_AXI_wstrb(15 downto 0) <= auto_cc_to_m00_couplers_WSTRB(15 downto 0);
M_AXI_wvalid <= auto_cc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= m00_couplers_to_auto_cc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_cc_AWREADY;
S_AXI_bid(0) <= m00_couplers_to_auto_cc_BID(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_cc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_cc_BVALID;
S_AXI_rdata(127 downto 0) <= m00_couplers_to_auto_cc_RDATA(127 downto 0);
S_AXI_rid(0) <= m00_couplers_to_auto_cc_RID(0);
S_AXI_rlast <= m00_couplers_to_auto_cc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_cc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_cc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_cc_WREADY;
auto_cc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_cc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_cc_to_m00_couplers_BID(0) <= M_AXI_bid(0);
auto_cc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_cc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_cc_to_m00_couplers_RDATA(127 downto 0) <= M_AXI_rdata(127 downto 0);
auto_cc_to_m00_couplers_RID(0) <= M_AXI_rid(0);
auto_cc_to_m00_couplers_RLAST <= M_AXI_rlast;
auto_cc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_cc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_cc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_cc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_cc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_cc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_cc_ARID(0) <= S_AXI_arid(0);
m00_couplers_to_auto_cc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_cc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_cc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_cc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_cc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_cc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_cc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_cc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_cc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_cc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_cc_AWID(0) <= S_AXI_awid(0);
m00_couplers_to_auto_cc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_cc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_cc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_cc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_cc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_cc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_cc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_cc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_cc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_cc_WDATA(127 downto 0) <= S_AXI_wdata(127 downto 0);
m00_couplers_to_auto_cc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_cc_WSTRB(15 downto 0) <= S_AXI_wstrb(15 downto 0);
m00_couplers_to_auto_cc_WVALID <= S_AXI_wvalid;
auto_cc: component system_auto_cc_0
port map (
m_axi_aclk => M_ACLK_1,
m_axi_araddr(27 downto 0) => auto_cc_to_m00_couplers_ARADDR(27 downto 0),
m_axi_arburst(1 downto 0) => auto_cc_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_cc_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_aresetn => M_ARESETN_1,
m_axi_arid(0) => auto_cc_to_m00_couplers_ARID(0),
m_axi_arlen(7 downto 0) => auto_cc_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_cc_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_cc_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_cc_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_cc_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_cc_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_cc_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_cc_to_m00_couplers_ARVALID,
m_axi_awaddr(27 downto 0) => auto_cc_to_m00_couplers_AWADDR(27 downto 0),
m_axi_awburst(1 downto 0) => auto_cc_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_cc_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => auto_cc_to_m00_couplers_AWID(0),
m_axi_awlen(7 downto 0) => auto_cc_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_cc_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_cc_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_cc_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_cc_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_cc_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_cc_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_cc_to_m00_couplers_AWVALID,
m_axi_bid(0) => auto_cc_to_m00_couplers_BID(0),
m_axi_bready => auto_cc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_cc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_cc_to_m00_couplers_BVALID,
m_axi_rdata(127 downto 0) => auto_cc_to_m00_couplers_RDATA(127 downto 0),
m_axi_rid(0) => auto_cc_to_m00_couplers_RID(0),
m_axi_rlast => auto_cc_to_m00_couplers_RLAST,
m_axi_rready => auto_cc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_cc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_cc_to_m00_couplers_RVALID,
m_axi_wdata(127 downto 0) => auto_cc_to_m00_couplers_WDATA(127 downto 0),
m_axi_wlast => auto_cc_to_m00_couplers_WLAST,
m_axi_wready => auto_cc_to_m00_couplers_WREADY,
m_axi_wstrb(15 downto 0) => auto_cc_to_m00_couplers_WSTRB(15 downto 0),
m_axi_wvalid => auto_cc_to_m00_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(27 downto 0) => m00_couplers_to_auto_cc_ARADDR(27 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_cc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_cc_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arid(0) => m00_couplers_to_auto_cc_ARID(0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_cc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_cc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_cc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_cc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_cc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_cc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_cc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_cc_ARVALID,
s_axi_awaddr(27 downto 0) => m00_couplers_to_auto_cc_AWADDR(27 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_cc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_cc_AWCACHE(3 downto 0),
s_axi_awid(0) => m00_couplers_to_auto_cc_AWID(0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_cc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_cc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_cc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_cc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_cc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_cc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_cc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_cc_AWVALID,
s_axi_bid(0) => m00_couplers_to_auto_cc_BID(0),
s_axi_bready => m00_couplers_to_auto_cc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_cc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_cc_BVALID,
s_axi_rdata(127 downto 0) => m00_couplers_to_auto_cc_RDATA(127 downto 0),
s_axi_rid(0) => m00_couplers_to_auto_cc_RID(0),
s_axi_rlast => m00_couplers_to_auto_cc_RLAST,
s_axi_rready => m00_couplers_to_auto_cc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_cc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_cc_RVALID,
s_axi_wdata(127 downto 0) => m00_couplers_to_auto_cc_WDATA(127 downto 0),
s_axi_wlast => m00_couplers_to_auto_cc_WLAST,
s_axi_wready => m00_couplers_to_auto_cc_WREADY,
s_axi_wstrb(15 downto 0) => m00_couplers_to_auto_cc_WSTRB(15 downto 0),
s_axi_wvalid => m00_couplers_to_auto_cc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_K87I2F is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_K87I2F;
architecture STRUCTURE of m01_couplers_imp_K87I2F is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_QYRHL1 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m02_couplers_imp_QYRHL1;
architecture STRUCTURE of m02_couplers_imp_QYRHL1 is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m02_couplers_to_m02_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m02_couplers_to_m02_couplers_AWVALID(0);
M_AXI_bready(0) <= m02_couplers_to_m02_couplers_BREADY(0);
M_AXI_rready(0) <= m02_couplers_to_m02_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m02_couplers_to_m02_couplers_WVALID(0);
S_AXI_arready(0) <= m02_couplers_to_m02_couplers_ARREADY(0);
S_AXI_awready(0) <= m02_couplers_to_m02_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m02_couplers_to_m02_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m02_couplers_to_m02_couplers_RVALID(0);
S_AXI_wready(0) <= m02_couplers_to_m02_couplers_WREADY(0);
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARREADY(0) <= M_AXI_arready(0);
m02_couplers_to_m02_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWREADY(0) <= M_AXI_awready(0);
m02_couplers_to_m02_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m02_couplers_to_m02_couplers_BREADY(0) <= S_AXI_bready(0);
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID(0) <= M_AXI_bvalid(0);
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY(0) <= S_AXI_rready(0);
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID(0) <= M_AXI_rvalid(0);
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY(0) <= M_AXI_wready(0);
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_1LIFQL0 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m03_couplers_imp_1LIFQL0;
architecture STRUCTURE of m03_couplers_imp_1LIFQL0 is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m03_couplers_to_m03_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m03_couplers_to_m03_couplers_AWVALID(0);
M_AXI_bready(0) <= m03_couplers_to_m03_couplers_BREADY(0);
M_AXI_rready(0) <= m03_couplers_to_m03_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m03_couplers_to_m03_couplers_WVALID(0);
S_AXI_arready(0) <= m03_couplers_to_m03_couplers_ARREADY(0);
S_AXI_awready(0) <= m03_couplers_to_m03_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m03_couplers_to_m03_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m03_couplers_to_m03_couplers_RVALID(0);
S_AXI_wready(0) <= m03_couplers_to_m03_couplers_WREADY(0);
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARREADY(0) <= M_AXI_arready(0);
m03_couplers_to_m03_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWREADY(0) <= M_AXI_awready(0);
m03_couplers_to_m03_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m03_couplers_to_m03_couplers_BREADY(0) <= S_AXI_bready(0);
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID(0) <= M_AXI_bvalid(0);
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY(0) <= S_AXI_rready(0);
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID(0) <= M_AXI_rvalid(0);
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY(0) <= M_AXI_wready(0);
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_E2VWV5 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m04_couplers_imp_E2VWV5;
architecture STRUCTURE of m04_couplers_imp_E2VWV5 is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m04_couplers_to_m04_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m04_couplers_to_m04_couplers_AWVALID(0);
M_AXI_bready(0) <= m04_couplers_to_m04_couplers_BREADY(0);
M_AXI_rready(0) <= m04_couplers_to_m04_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m04_couplers_to_m04_couplers_WVALID(0);
S_AXI_arready(0) <= m04_couplers_to_m04_couplers_ARREADY(0);
S_AXI_awready(0) <= m04_couplers_to_m04_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m04_couplers_to_m04_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m04_couplers_to_m04_couplers_RVALID(0);
S_AXI_wready(0) <= m04_couplers_to_m04_couplers_WREADY(0);
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY(0) <= M_AXI_arready(0);
m04_couplers_to_m04_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY(0) <= M_AXI_awready(0);
m04_couplers_to_m04_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m04_couplers_to_m04_couplers_BREADY(0) <= S_AXI_bready(0);
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID(0) <= M_AXI_bvalid(0);
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY(0) <= S_AXI_rready(0);
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID(0) <= M_AXI_rvalid(0);
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY(0) <= M_AXI_wready(0);
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_17ILSXC is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m05_couplers_imp_17ILSXC;
architecture STRUCTURE of m05_couplers_imp_17ILSXC is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m05_couplers_to_m05_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m05_couplers_to_m05_couplers_AWVALID(0);
M_AXI_bready(0) <= m05_couplers_to_m05_couplers_BREADY(0);
M_AXI_rready(0) <= m05_couplers_to_m05_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m05_couplers_to_m05_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m05_couplers_to_m05_couplers_WVALID(0);
S_AXI_arready(0) <= m05_couplers_to_m05_couplers_ARREADY(0);
S_AXI_awready(0) <= m05_couplers_to_m05_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m05_couplers_to_m05_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m05_couplers_to_m05_couplers_RVALID(0);
S_AXI_wready(0) <= m05_couplers_to_m05_couplers_WREADY(0);
m05_couplers_to_m05_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m05_couplers_to_m05_couplers_ARREADY(0) <= M_AXI_arready(0);
m05_couplers_to_m05_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m05_couplers_to_m05_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m05_couplers_to_m05_couplers_AWREADY(0) <= M_AXI_awready(0);
m05_couplers_to_m05_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m05_couplers_to_m05_couplers_BREADY(0) <= S_AXI_bready(0);
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID(0) <= M_AXI_bvalid(0);
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY(0) <= S_AXI_rready(0);
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID(0) <= M_AXI_rvalid(0);
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY(0) <= M_AXI_wready(0);
m05_couplers_to_m05_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m05_couplers_to_m05_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m06_couplers_imp_1E95TTU is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m06_couplers_imp_1E95TTU;
architecture STRUCTURE of m06_couplers_imp_1E95TTU is
signal m06_couplers_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m06_couplers_to_m06_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m06_couplers_to_m06_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m06_couplers_to_m06_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m06_couplers_to_m06_couplers_AWVALID(0);
M_AXI_bready(0) <= m06_couplers_to_m06_couplers_BREADY(0);
M_AXI_rready(0) <= m06_couplers_to_m06_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m06_couplers_to_m06_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m06_couplers_to_m06_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m06_couplers_to_m06_couplers_WVALID(0);
S_AXI_arready(0) <= m06_couplers_to_m06_couplers_ARREADY(0);
S_AXI_awready(0) <= m06_couplers_to_m06_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m06_couplers_to_m06_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m06_couplers_to_m06_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m06_couplers_to_m06_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m06_couplers_to_m06_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m06_couplers_to_m06_couplers_RVALID(0);
S_AXI_wready(0) <= m06_couplers_to_m06_couplers_WREADY(0);
m06_couplers_to_m06_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m06_couplers_to_m06_couplers_ARREADY(0) <= M_AXI_arready(0);
m06_couplers_to_m06_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m06_couplers_to_m06_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m06_couplers_to_m06_couplers_AWREADY(0) <= M_AXI_awready(0);
m06_couplers_to_m06_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m06_couplers_to_m06_couplers_BREADY(0) <= S_AXI_bready(0);
m06_couplers_to_m06_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m06_couplers_to_m06_couplers_BVALID(0) <= M_AXI_bvalid(0);
m06_couplers_to_m06_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m06_couplers_to_m06_couplers_RREADY(0) <= S_AXI_rready(0);
m06_couplers_to_m06_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m06_couplers_to_m06_couplers_RVALID(0) <= M_AXI_rvalid(0);
m06_couplers_to_m06_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m06_couplers_to_m06_couplers_WREADY(0) <= M_AXI_wready(0);
m06_couplers_to_m06_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m06_couplers_to_m06_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m07_couplers_imp_7MB6C3 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m07_couplers_imp_7MB6C3;
architecture STRUCTURE of m07_couplers_imp_7MB6C3 is
signal m07_couplers_to_m07_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_m07_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_m07_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m07_couplers_to_m07_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_m07_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m07_couplers_to_m07_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_m07_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m07_couplers_to_m07_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m07_couplers_to_m07_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m07_couplers_to_m07_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m07_couplers_to_m07_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m07_couplers_to_m07_couplers_AWVALID(0);
M_AXI_bready(0) <= m07_couplers_to_m07_couplers_BREADY(0);
M_AXI_rready(0) <= m07_couplers_to_m07_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m07_couplers_to_m07_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m07_couplers_to_m07_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m07_couplers_to_m07_couplers_WVALID(0);
S_AXI_arready(0) <= m07_couplers_to_m07_couplers_ARREADY(0);
S_AXI_awready(0) <= m07_couplers_to_m07_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m07_couplers_to_m07_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m07_couplers_to_m07_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m07_couplers_to_m07_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m07_couplers_to_m07_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m07_couplers_to_m07_couplers_RVALID(0);
S_AXI_wready(0) <= m07_couplers_to_m07_couplers_WREADY(0);
m07_couplers_to_m07_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m07_couplers_to_m07_couplers_ARREADY(0) <= M_AXI_arready(0);
m07_couplers_to_m07_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m07_couplers_to_m07_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m07_couplers_to_m07_couplers_AWREADY(0) <= M_AXI_awready(0);
m07_couplers_to_m07_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m07_couplers_to_m07_couplers_BREADY(0) <= S_AXI_bready(0);
m07_couplers_to_m07_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m07_couplers_to_m07_couplers_BVALID(0) <= M_AXI_bvalid(0);
m07_couplers_to_m07_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m07_couplers_to_m07_couplers_RREADY(0) <= S_AXI_rready(0);
m07_couplers_to_m07_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m07_couplers_to_m07_couplers_RVALID(0) <= M_AXI_rvalid(0);
m07_couplers_to_m07_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m07_couplers_to_m07_couplers_WREADY(0) <= M_AXI_wready(0);
m07_couplers_to_m07_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m07_couplers_to_m07_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m08_couplers_imp_15IETBD is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m08_couplers_imp_15IETBD;
architecture STRUCTURE of m08_couplers_imp_15IETBD is
signal m08_couplers_to_m08_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_m08_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_m08_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m08_couplers_to_m08_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_m08_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m08_couplers_to_m08_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_m08_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m08_couplers_to_m08_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m08_couplers_to_m08_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m08_couplers_to_m08_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m08_couplers_to_m08_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m08_couplers_to_m08_couplers_AWVALID(0);
M_AXI_bready(0) <= m08_couplers_to_m08_couplers_BREADY(0);
M_AXI_rready(0) <= m08_couplers_to_m08_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m08_couplers_to_m08_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m08_couplers_to_m08_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m08_couplers_to_m08_couplers_WVALID(0);
S_AXI_arready(0) <= m08_couplers_to_m08_couplers_ARREADY(0);
S_AXI_awready(0) <= m08_couplers_to_m08_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m08_couplers_to_m08_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m08_couplers_to_m08_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m08_couplers_to_m08_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m08_couplers_to_m08_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m08_couplers_to_m08_couplers_RVALID(0);
S_AXI_wready(0) <= m08_couplers_to_m08_couplers_WREADY(0);
m08_couplers_to_m08_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m08_couplers_to_m08_couplers_ARREADY(0) <= M_AXI_arready(0);
m08_couplers_to_m08_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m08_couplers_to_m08_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m08_couplers_to_m08_couplers_AWREADY(0) <= M_AXI_awready(0);
m08_couplers_to_m08_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m08_couplers_to_m08_couplers_BREADY(0) <= S_AXI_bready(0);
m08_couplers_to_m08_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m08_couplers_to_m08_couplers_BVALID(0) <= M_AXI_bvalid(0);
m08_couplers_to_m08_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m08_couplers_to_m08_couplers_RREADY(0) <= S_AXI_rready(0);
m08_couplers_to_m08_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m08_couplers_to_m08_couplers_RVALID(0) <= M_AXI_rvalid(0);
m08_couplers_to_m08_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m08_couplers_to_m08_couplers_WREADY(0) <= M_AXI_wready(0);
m08_couplers_to_m08_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m08_couplers_to_m08_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m09_couplers_imp_GMVR08 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m09_couplers_imp_GMVR08;
architecture STRUCTURE of m09_couplers_imp_GMVR08 is
signal m09_couplers_to_m09_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_m09_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_m09_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m09_couplers_to_m09_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_m09_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m09_couplers_to_m09_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_m09_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m09_couplers_to_m09_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m09_couplers_to_m09_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m09_couplers_to_m09_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m09_couplers_to_m09_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m09_couplers_to_m09_couplers_AWVALID(0);
M_AXI_bready(0) <= m09_couplers_to_m09_couplers_BREADY(0);
M_AXI_rready(0) <= m09_couplers_to_m09_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m09_couplers_to_m09_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m09_couplers_to_m09_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m09_couplers_to_m09_couplers_WVALID(0);
S_AXI_arready(0) <= m09_couplers_to_m09_couplers_ARREADY(0);
S_AXI_awready(0) <= m09_couplers_to_m09_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m09_couplers_to_m09_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m09_couplers_to_m09_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m09_couplers_to_m09_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m09_couplers_to_m09_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m09_couplers_to_m09_couplers_RVALID(0);
S_AXI_wready(0) <= m09_couplers_to_m09_couplers_WREADY(0);
m09_couplers_to_m09_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m09_couplers_to_m09_couplers_ARREADY(0) <= M_AXI_arready(0);
m09_couplers_to_m09_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m09_couplers_to_m09_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m09_couplers_to_m09_couplers_AWREADY(0) <= M_AXI_awready(0);
m09_couplers_to_m09_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m09_couplers_to_m09_couplers_BREADY(0) <= S_AXI_bready(0);
m09_couplers_to_m09_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m09_couplers_to_m09_couplers_BVALID(0) <= M_AXI_bvalid(0);
m09_couplers_to_m09_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m09_couplers_to_m09_couplers_RREADY(0) <= S_AXI_rready(0);
m09_couplers_to_m09_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m09_couplers_to_m09_couplers_RVALID(0) <= M_AXI_rvalid(0);
m09_couplers_to_m09_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m09_couplers_to_m09_couplers_WREADY(0) <= M_AXI_wready(0);
m09_couplers_to_m09_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m09_couplers_to_m09_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m10_couplers_imp_QYIUP1 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC;
M_AXI_arprot : out STD_LOGIC;
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC;
M_AXI_awprot : out STD_LOGIC;
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC;
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC;
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC;
S_AXI_arprot : in STD_LOGIC;
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC;
S_AXI_awprot : in STD_LOGIC;
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC;
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC;
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC
);
end m10_couplers_imp_QYIUP1;
architecture STRUCTURE of m10_couplers_imp_QYIUP1 is
signal m10_couplers_to_m10_couplers_ARADDR : STD_LOGIC;
signal m10_couplers_to_m10_couplers_ARPROT : STD_LOGIC;
signal m10_couplers_to_m10_couplers_ARREADY : STD_LOGIC;
signal m10_couplers_to_m10_couplers_ARVALID : STD_LOGIC;
signal m10_couplers_to_m10_couplers_AWADDR : STD_LOGIC;
signal m10_couplers_to_m10_couplers_AWPROT : STD_LOGIC;
signal m10_couplers_to_m10_couplers_AWREADY : STD_LOGIC;
signal m10_couplers_to_m10_couplers_AWVALID : STD_LOGIC;
signal m10_couplers_to_m10_couplers_BREADY : STD_LOGIC;
signal m10_couplers_to_m10_couplers_BRESP : STD_LOGIC;
signal m10_couplers_to_m10_couplers_BVALID : STD_LOGIC;
signal m10_couplers_to_m10_couplers_RDATA : STD_LOGIC;
signal m10_couplers_to_m10_couplers_RREADY : STD_LOGIC;
signal m10_couplers_to_m10_couplers_RRESP : STD_LOGIC;
signal m10_couplers_to_m10_couplers_RVALID : STD_LOGIC;
signal m10_couplers_to_m10_couplers_WDATA : STD_LOGIC;
signal m10_couplers_to_m10_couplers_WREADY : STD_LOGIC;
signal m10_couplers_to_m10_couplers_WSTRB : STD_LOGIC;
signal m10_couplers_to_m10_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr <= m10_couplers_to_m10_couplers_ARADDR;
M_AXI_arprot <= m10_couplers_to_m10_couplers_ARPROT;
M_AXI_arvalid <= m10_couplers_to_m10_couplers_ARVALID;
M_AXI_awaddr <= m10_couplers_to_m10_couplers_AWADDR;
M_AXI_awprot <= m10_couplers_to_m10_couplers_AWPROT;
M_AXI_awvalid <= m10_couplers_to_m10_couplers_AWVALID;
M_AXI_bready <= m10_couplers_to_m10_couplers_BREADY;
M_AXI_rready <= m10_couplers_to_m10_couplers_RREADY;
M_AXI_wdata <= m10_couplers_to_m10_couplers_WDATA;
M_AXI_wstrb <= m10_couplers_to_m10_couplers_WSTRB;
M_AXI_wvalid <= m10_couplers_to_m10_couplers_WVALID;
S_AXI_arready <= m10_couplers_to_m10_couplers_ARREADY;
S_AXI_awready <= m10_couplers_to_m10_couplers_AWREADY;
S_AXI_bresp <= m10_couplers_to_m10_couplers_BRESP;
S_AXI_bvalid <= m10_couplers_to_m10_couplers_BVALID;
S_AXI_rdata <= m10_couplers_to_m10_couplers_RDATA;
S_AXI_rresp <= m10_couplers_to_m10_couplers_RRESP;
S_AXI_rvalid <= m10_couplers_to_m10_couplers_RVALID;
S_AXI_wready <= m10_couplers_to_m10_couplers_WREADY;
m10_couplers_to_m10_couplers_ARADDR <= S_AXI_araddr;
m10_couplers_to_m10_couplers_ARPROT <= S_AXI_arprot;
m10_couplers_to_m10_couplers_ARREADY <= M_AXI_arready;
m10_couplers_to_m10_couplers_ARVALID <= S_AXI_arvalid;
m10_couplers_to_m10_couplers_AWADDR <= S_AXI_awaddr;
m10_couplers_to_m10_couplers_AWPROT <= S_AXI_awprot;
m10_couplers_to_m10_couplers_AWREADY <= M_AXI_awready;
m10_couplers_to_m10_couplers_AWVALID <= S_AXI_awvalid;
m10_couplers_to_m10_couplers_BREADY <= S_AXI_bready;
m10_couplers_to_m10_couplers_BRESP <= M_AXI_bresp;
m10_couplers_to_m10_couplers_BVALID <= M_AXI_bvalid;
m10_couplers_to_m10_couplers_RDATA <= M_AXI_rdata;
m10_couplers_to_m10_couplers_RREADY <= S_AXI_rready;
m10_couplers_to_m10_couplers_RRESP <= M_AXI_rresp;
m10_couplers_to_m10_couplers_RVALID <= M_AXI_rvalid;
m10_couplers_to_m10_couplers_WDATA <= S_AXI_wdata;
m10_couplers_to_m10_couplers_WREADY <= M_AXI_wready;
m10_couplers_to_m10_couplers_WSTRB <= S_AXI_wstrb;
m10_couplers_to_m10_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m11_couplers_imp_1LI8I9G is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m11_couplers_imp_1LI8I9G;
architecture STRUCTURE of m11_couplers_imp_1LI8I9G is
signal m11_couplers_to_m11_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_m11_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_m11_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m11_couplers_to_m11_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_m11_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m11_couplers_to_m11_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_m11_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m11_couplers_to_m11_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m11_couplers_to_m11_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m11_couplers_to_m11_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m11_couplers_to_m11_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m11_couplers_to_m11_couplers_AWVALID(0);
M_AXI_bready(0) <= m11_couplers_to_m11_couplers_BREADY(0);
M_AXI_rready(0) <= m11_couplers_to_m11_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m11_couplers_to_m11_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m11_couplers_to_m11_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m11_couplers_to_m11_couplers_WVALID(0);
S_AXI_arready(0) <= m11_couplers_to_m11_couplers_ARREADY(0);
S_AXI_awready(0) <= m11_couplers_to_m11_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m11_couplers_to_m11_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m11_couplers_to_m11_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m11_couplers_to_m11_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m11_couplers_to_m11_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m11_couplers_to_m11_couplers_RVALID(0);
S_AXI_wready(0) <= m11_couplers_to_m11_couplers_WREADY(0);
m11_couplers_to_m11_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m11_couplers_to_m11_couplers_ARREADY(0) <= M_AXI_arready(0);
m11_couplers_to_m11_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m11_couplers_to_m11_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m11_couplers_to_m11_couplers_AWREADY(0) <= M_AXI_awready(0);
m11_couplers_to_m11_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m11_couplers_to_m11_couplers_BREADY(0) <= S_AXI_bready(0);
m11_couplers_to_m11_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m11_couplers_to_m11_couplers_BVALID(0) <= M_AXI_bvalid(0);
m11_couplers_to_m11_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m11_couplers_to_m11_couplers_RREADY(0) <= S_AXI_rready(0);
m11_couplers_to_m11_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m11_couplers_to_m11_couplers_RVALID(0) <= M_AXI_rvalid(0);
m11_couplers_to_m11_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m11_couplers_to_m11_couplers_WREADY(0) <= M_AXI_wready(0);
m11_couplers_to_m11_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m11_couplers_to_m11_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m12_couplers_imp_1RYRHQE is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m12_couplers_imp_1RYRHQE;
architecture STRUCTURE of m12_couplers_imp_1RYRHQE is
signal m12_couplers_to_m12_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_m12_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_m12_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m12_couplers_to_m12_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_m12_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m12_couplers_to_m12_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_m12_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m12_couplers_to_m12_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m12_couplers_to_m12_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m12_couplers_to_m12_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m12_couplers_to_m12_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m12_couplers_to_m12_couplers_AWVALID(0);
M_AXI_bready(0) <= m12_couplers_to_m12_couplers_BREADY(0);
M_AXI_rready(0) <= m12_couplers_to_m12_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m12_couplers_to_m12_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m12_couplers_to_m12_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m12_couplers_to_m12_couplers_WVALID(0);
S_AXI_arready(0) <= m12_couplers_to_m12_couplers_ARREADY(0);
S_AXI_awready(0) <= m12_couplers_to_m12_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m12_couplers_to_m12_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m12_couplers_to_m12_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m12_couplers_to_m12_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m12_couplers_to_m12_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m12_couplers_to_m12_couplers_RVALID(0);
S_AXI_wready(0) <= m12_couplers_to_m12_couplers_WREADY(0);
m12_couplers_to_m12_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m12_couplers_to_m12_couplers_ARREADY(0) <= M_AXI_arready(0);
m12_couplers_to_m12_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m12_couplers_to_m12_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m12_couplers_to_m12_couplers_AWREADY(0) <= M_AXI_awready(0);
m12_couplers_to_m12_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m12_couplers_to_m12_couplers_BREADY(0) <= S_AXI_bready(0);
m12_couplers_to_m12_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m12_couplers_to_m12_couplers_BVALID(0) <= M_AXI_bvalid(0);
m12_couplers_to_m12_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m12_couplers_to_m12_couplers_RREADY(0) <= S_AXI_rready(0);
m12_couplers_to_m12_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m12_couplers_to_m12_couplers_RVALID(0) <= M_AXI_rvalid(0);
m12_couplers_to_m12_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m12_couplers_to_m12_couplers_WREADY(0) <= M_AXI_wready(0);
m12_couplers_to_m12_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m12_couplers_to_m12_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m13_couplers_imp_K7ZVH3 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m13_couplers_imp_K7ZVH3;
architecture STRUCTURE of m13_couplers_imp_K7ZVH3 is
component system_auto_cc_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component system_auto_cc_1;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_cc_to_m13_couplers_ARADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal auto_cc_to_m13_couplers_ARREADY : STD_LOGIC;
signal auto_cc_to_m13_couplers_ARVALID : STD_LOGIC;
signal auto_cc_to_m13_couplers_AWADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal auto_cc_to_m13_couplers_AWREADY : STD_LOGIC;
signal auto_cc_to_m13_couplers_AWVALID : STD_LOGIC;
signal auto_cc_to_m13_couplers_BREADY : STD_LOGIC;
signal auto_cc_to_m13_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_m13_couplers_BVALID : STD_LOGIC;
signal auto_cc_to_m13_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_m13_couplers_RREADY : STD_LOGIC;
signal auto_cc_to_m13_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_m13_couplers_RVALID : STD_LOGIC;
signal auto_cc_to_m13_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_m13_couplers_WREADY : STD_LOGIC;
signal auto_cc_to_m13_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_m13_couplers_WVALID : STD_LOGIC;
signal m13_couplers_to_auto_cc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m13_couplers_to_auto_cc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m13_couplers_to_auto_cc_ARREADY : STD_LOGIC;
signal m13_couplers_to_auto_cc_ARVALID : STD_LOGIC;
signal m13_couplers_to_auto_cc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m13_couplers_to_auto_cc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m13_couplers_to_auto_cc_AWREADY : STD_LOGIC;
signal m13_couplers_to_auto_cc_AWVALID : STD_LOGIC;
signal m13_couplers_to_auto_cc_BREADY : STD_LOGIC;
signal m13_couplers_to_auto_cc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m13_couplers_to_auto_cc_BVALID : STD_LOGIC;
signal m13_couplers_to_auto_cc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m13_couplers_to_auto_cc_RREADY : STD_LOGIC;
signal m13_couplers_to_auto_cc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m13_couplers_to_auto_cc_RVALID : STD_LOGIC;
signal m13_couplers_to_auto_cc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m13_couplers_to_auto_cc_WREADY : STD_LOGIC;
signal m13_couplers_to_auto_cc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m13_couplers_to_auto_cc_WVALID : STD_LOGIC;
signal NLW_auto_cc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_cc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1 <= M_ARESETN;
M_AXI_araddr(10 downto 0) <= auto_cc_to_m13_couplers_ARADDR(10 downto 0);
M_AXI_arvalid <= auto_cc_to_m13_couplers_ARVALID;
M_AXI_awaddr(10 downto 0) <= auto_cc_to_m13_couplers_AWADDR(10 downto 0);
M_AXI_awvalid <= auto_cc_to_m13_couplers_AWVALID;
M_AXI_bready <= auto_cc_to_m13_couplers_BREADY;
M_AXI_rready <= auto_cc_to_m13_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_cc_to_m13_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_cc_to_m13_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_cc_to_m13_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= m13_couplers_to_auto_cc_ARREADY;
S_AXI_awready <= m13_couplers_to_auto_cc_AWREADY;
S_AXI_bresp(1 downto 0) <= m13_couplers_to_auto_cc_BRESP(1 downto 0);
S_AXI_bvalid <= m13_couplers_to_auto_cc_BVALID;
S_AXI_rdata(31 downto 0) <= m13_couplers_to_auto_cc_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m13_couplers_to_auto_cc_RRESP(1 downto 0);
S_AXI_rvalid <= m13_couplers_to_auto_cc_RVALID;
S_AXI_wready <= m13_couplers_to_auto_cc_WREADY;
auto_cc_to_m13_couplers_ARREADY <= M_AXI_arready;
auto_cc_to_m13_couplers_AWREADY <= M_AXI_awready;
auto_cc_to_m13_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_cc_to_m13_couplers_BVALID <= M_AXI_bvalid;
auto_cc_to_m13_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_cc_to_m13_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_cc_to_m13_couplers_RVALID <= M_AXI_rvalid;
auto_cc_to_m13_couplers_WREADY <= M_AXI_wready;
m13_couplers_to_auto_cc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m13_couplers_to_auto_cc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m13_couplers_to_auto_cc_ARVALID <= S_AXI_arvalid;
m13_couplers_to_auto_cc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m13_couplers_to_auto_cc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m13_couplers_to_auto_cc_AWVALID <= S_AXI_awvalid;
m13_couplers_to_auto_cc_BREADY <= S_AXI_bready;
m13_couplers_to_auto_cc_RREADY <= S_AXI_rready;
m13_couplers_to_auto_cc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m13_couplers_to_auto_cc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m13_couplers_to_auto_cc_WVALID <= S_AXI_wvalid;
auto_cc: component system_auto_cc_1
port map (
m_axi_aclk => M_ACLK_1,
m_axi_araddr(10 downto 0) => auto_cc_to_m13_couplers_ARADDR(10 downto 0),
m_axi_aresetn => M_ARESETN_1,
m_axi_arprot(2 downto 0) => NLW_auto_cc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_cc_to_m13_couplers_ARREADY,
m_axi_arvalid => auto_cc_to_m13_couplers_ARVALID,
m_axi_awaddr(10 downto 0) => auto_cc_to_m13_couplers_AWADDR(10 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_cc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_cc_to_m13_couplers_AWREADY,
m_axi_awvalid => auto_cc_to_m13_couplers_AWVALID,
m_axi_bready => auto_cc_to_m13_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_cc_to_m13_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_cc_to_m13_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_cc_to_m13_couplers_RDATA(31 downto 0),
m_axi_rready => auto_cc_to_m13_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_cc_to_m13_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_cc_to_m13_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_cc_to_m13_couplers_WDATA(31 downto 0),
m_axi_wready => auto_cc_to_m13_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_cc_to_m13_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_cc_to_m13_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(10 downto 0) => m13_couplers_to_auto_cc_ARADDR(10 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arprot(2 downto 0) => m13_couplers_to_auto_cc_ARPROT(2 downto 0),
s_axi_arready => m13_couplers_to_auto_cc_ARREADY,
s_axi_arvalid => m13_couplers_to_auto_cc_ARVALID,
s_axi_awaddr(10 downto 0) => m13_couplers_to_auto_cc_AWADDR(10 downto 0),
s_axi_awprot(2 downto 0) => m13_couplers_to_auto_cc_AWPROT(2 downto 0),
s_axi_awready => m13_couplers_to_auto_cc_AWREADY,
s_axi_awvalid => m13_couplers_to_auto_cc_AWVALID,
s_axi_bready => m13_couplers_to_auto_cc_BREADY,
s_axi_bresp(1 downto 0) => m13_couplers_to_auto_cc_BRESP(1 downto 0),
s_axi_bvalid => m13_couplers_to_auto_cc_BVALID,
s_axi_rdata(31 downto 0) => m13_couplers_to_auto_cc_RDATA(31 downto 0),
s_axi_rready => m13_couplers_to_auto_cc_RREADY,
s_axi_rresp(1 downto 0) => m13_couplers_to_auto_cc_RRESP(1 downto 0),
s_axi_rvalid => m13_couplers_to_auto_cc_RVALID,
s_axi_wdata(31 downto 0) => m13_couplers_to_auto_cc_WDATA(31 downto 0),
s_axi_wready => m13_couplers_to_auto_cc_WREADY,
s_axi_wstrb(3 downto 0) => m13_couplers_to_auto_cc_WSTRB(3 downto 0),
s_axi_wvalid => m13_couplers_to_auto_cc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity microblaze_0_local_memory_imp_OGE0N8 is
port (
DLMB_abus : in STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_addrstrobe : in STD_LOGIC;
DLMB_be : in STD_LOGIC_VECTOR ( 0 to 3 );
DLMB_ce : out STD_LOGIC;
DLMB_readdbus : out STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_readstrobe : in STD_LOGIC;
DLMB_ready : out STD_LOGIC;
DLMB_ue : out STD_LOGIC;
DLMB_wait : out STD_LOGIC;
DLMB_writedbus : in STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_writestrobe : in STD_LOGIC;
ILMB_abus : in STD_LOGIC_VECTOR ( 0 to 31 );
ILMB_addrstrobe : in STD_LOGIC;
ILMB_ce : out STD_LOGIC;
ILMB_readdbus : out STD_LOGIC_VECTOR ( 0 to 31 );
ILMB_readstrobe : in STD_LOGIC;
ILMB_ready : out STD_LOGIC;
ILMB_ue : out STD_LOGIC;
ILMB_wait : out STD_LOGIC;
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end microblaze_0_local_memory_imp_OGE0N8;
architecture STRUCTURE of microblaze_0_local_memory_imp_OGE0N8 is
component system_dlmb_bram_if_cntlr_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component system_dlmb_bram_if_cntlr_0;
component system_dlmb_v10_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component system_dlmb_v10_0;
component system_ilmb_bram_if_cntlr_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component system_ilmb_bram_if_cntlr_0;
component system_ilmb_v10_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component system_ilmb_v10_0;
component system_lmb_bram_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_lmb_bram_0;
signal SYS_Rst_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_Clk : STD_LOGIC;
signal microblaze_0_dlmb_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_CE : STD_LOGIC;
signal microblaze_0_dlmb_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_READY : STD_LOGIC;
signal microblaze_0_dlmb_UE : STD_LOGIC;
signal microblaze_0_dlmb_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_WRITESTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_bus_CE : STD_LOGIC;
signal microblaze_0_dlmb_bus_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_READY : STD_LOGIC;
signal microblaze_0_dlmb_bus_UE : STD_LOGIC;
signal microblaze_0_dlmb_bus_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_bus_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_WRITESTROBE : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_cntlr_CLK : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_cntlr_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_dlmb_cntlr_EN : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_RST : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_ilmb_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_CE : STD_LOGIC;
signal microblaze_0_ilmb_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_READY : STD_LOGIC;
signal microblaze_0_ilmb_UE : STD_LOGIC;
signal microblaze_0_ilmb_WAIT : STD_LOGIC;
signal microblaze_0_ilmb_bus_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_bus_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_ilmb_bus_CE : STD_LOGIC;
signal microblaze_0_ilmb_bus_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_bus_READY : STD_LOGIC;
signal microblaze_0_ilmb_bus_UE : STD_LOGIC;
signal microblaze_0_ilmb_bus_WAIT : STD_LOGIC;
signal microblaze_0_ilmb_bus_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_WRITESTROBE : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_cntlr_CLK : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_cntlr_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_ilmb_cntlr_EN : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_RST : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_dlmb_v10_LMB_Rst_UNCONNECTED : STD_LOGIC;
signal NLW_ilmb_v10_LMB_Rst_UNCONNECTED : STD_LOGIC;
attribute BMM_INFO_ADDRESS_SPACE : string;
attribute BMM_INFO_ADDRESS_SPACE of dlmb_bram_if_cntlr : label is "byte 0x00000000 32 > system microblaze_0_local_memory/lmb_bram";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of dlmb_bram_if_cntlr : label is "yes";
begin
DLMB_ce <= microblaze_0_dlmb_CE;
DLMB_readdbus(0 to 31) <= microblaze_0_dlmb_READDBUS(0 to 31);
DLMB_ready <= microblaze_0_dlmb_READY;
DLMB_ue <= microblaze_0_dlmb_UE;
DLMB_wait <= microblaze_0_dlmb_WAIT;
ILMB_ce <= microblaze_0_ilmb_CE;
ILMB_readdbus(0 to 31) <= microblaze_0_ilmb_READDBUS(0 to 31);
ILMB_ready <= microblaze_0_ilmb_READY;
ILMB_ue <= microblaze_0_ilmb_UE;
ILMB_wait <= microblaze_0_ilmb_WAIT;
SYS_Rst_1(0) <= SYS_Rst(0);
microblaze_0_Clk <= LMB_Clk;
microblaze_0_dlmb_ABUS(0 to 31) <= DLMB_abus(0 to 31);
microblaze_0_dlmb_ADDRSTROBE <= DLMB_addrstrobe;
microblaze_0_dlmb_BE(0 to 3) <= DLMB_be(0 to 3);
microblaze_0_dlmb_READSTROBE <= DLMB_readstrobe;
microblaze_0_dlmb_WRITEDBUS(0 to 31) <= DLMB_writedbus(0 to 31);
microblaze_0_dlmb_WRITESTROBE <= DLMB_writestrobe;
microblaze_0_ilmb_ABUS(0 to 31) <= ILMB_abus(0 to 31);
microblaze_0_ilmb_ADDRSTROBE <= ILMB_addrstrobe;
microblaze_0_ilmb_READSTROBE <= ILMB_readstrobe;
dlmb_bram_if_cntlr: component system_dlmb_bram_if_cntlr_0
port map (
BRAM_Addr_A(0 to 31) => microblaze_0_dlmb_cntlr_ADDR(0 to 31),
BRAM_Clk_A => microblaze_0_dlmb_cntlr_CLK,
BRAM_Din_A(0) => microblaze_0_dlmb_cntlr_DOUT(31),
BRAM_Din_A(1) => microblaze_0_dlmb_cntlr_DOUT(30),
BRAM_Din_A(2) => microblaze_0_dlmb_cntlr_DOUT(29),
BRAM_Din_A(3) => microblaze_0_dlmb_cntlr_DOUT(28),
BRAM_Din_A(4) => microblaze_0_dlmb_cntlr_DOUT(27),
BRAM_Din_A(5) => microblaze_0_dlmb_cntlr_DOUT(26),
BRAM_Din_A(6) => microblaze_0_dlmb_cntlr_DOUT(25),
BRAM_Din_A(7) => microblaze_0_dlmb_cntlr_DOUT(24),
BRAM_Din_A(8) => microblaze_0_dlmb_cntlr_DOUT(23),
BRAM_Din_A(9) => microblaze_0_dlmb_cntlr_DOUT(22),
BRAM_Din_A(10) => microblaze_0_dlmb_cntlr_DOUT(21),
BRAM_Din_A(11) => microblaze_0_dlmb_cntlr_DOUT(20),
BRAM_Din_A(12) => microblaze_0_dlmb_cntlr_DOUT(19),
BRAM_Din_A(13) => microblaze_0_dlmb_cntlr_DOUT(18),
BRAM_Din_A(14) => microblaze_0_dlmb_cntlr_DOUT(17),
BRAM_Din_A(15) => microblaze_0_dlmb_cntlr_DOUT(16),
BRAM_Din_A(16) => microblaze_0_dlmb_cntlr_DOUT(15),
BRAM_Din_A(17) => microblaze_0_dlmb_cntlr_DOUT(14),
BRAM_Din_A(18) => microblaze_0_dlmb_cntlr_DOUT(13),
BRAM_Din_A(19) => microblaze_0_dlmb_cntlr_DOUT(12),
BRAM_Din_A(20) => microblaze_0_dlmb_cntlr_DOUT(11),
BRAM_Din_A(21) => microblaze_0_dlmb_cntlr_DOUT(10),
BRAM_Din_A(22) => microblaze_0_dlmb_cntlr_DOUT(9),
BRAM_Din_A(23) => microblaze_0_dlmb_cntlr_DOUT(8),
BRAM_Din_A(24) => microblaze_0_dlmb_cntlr_DOUT(7),
BRAM_Din_A(25) => microblaze_0_dlmb_cntlr_DOUT(6),
BRAM_Din_A(26) => microblaze_0_dlmb_cntlr_DOUT(5),
BRAM_Din_A(27) => microblaze_0_dlmb_cntlr_DOUT(4),
BRAM_Din_A(28) => microblaze_0_dlmb_cntlr_DOUT(3),
BRAM_Din_A(29) => microblaze_0_dlmb_cntlr_DOUT(2),
BRAM_Din_A(30) => microblaze_0_dlmb_cntlr_DOUT(1),
BRAM_Din_A(31) => microblaze_0_dlmb_cntlr_DOUT(0),
BRAM_Dout_A(0 to 31) => microblaze_0_dlmb_cntlr_DIN(0 to 31),
BRAM_EN_A => microblaze_0_dlmb_cntlr_EN,
BRAM_Rst_A => microblaze_0_dlmb_cntlr_RST,
BRAM_WEN_A(0 to 3) => microblaze_0_dlmb_cntlr_WE(0 to 3),
LMB_ABus(0 to 31) => microblaze_0_dlmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_dlmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_dlmb_bus_BE(0 to 3),
LMB_Clk => microblaze_0_Clk,
LMB_ReadStrobe => microblaze_0_dlmb_bus_READSTROBE,
LMB_Rst => SYS_Rst_1(0),
LMB_WriteDBus(0 to 31) => microblaze_0_dlmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_dlmb_bus_WRITESTROBE,
Sl_CE => microblaze_0_dlmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_dlmb_bus_READDBUS(0 to 31),
Sl_Ready => microblaze_0_dlmb_bus_READY,
Sl_UE => microblaze_0_dlmb_bus_UE,
Sl_Wait => microblaze_0_dlmb_bus_WAIT
);
dlmb_v10: component system_dlmb_v10_0
port map (
LMB_ABus(0 to 31) => microblaze_0_dlmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_dlmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_dlmb_bus_BE(0 to 3),
LMB_CE => microblaze_0_dlmb_CE,
LMB_Clk => microblaze_0_Clk,
LMB_ReadDBus(0 to 31) => microblaze_0_dlmb_READDBUS(0 to 31),
LMB_ReadStrobe => microblaze_0_dlmb_bus_READSTROBE,
LMB_Ready => microblaze_0_dlmb_READY,
LMB_Rst => NLW_dlmb_v10_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_dlmb_UE,
LMB_Wait => microblaze_0_dlmb_WAIT,
LMB_WriteDBus(0 to 31) => microblaze_0_dlmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_dlmb_bus_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_dlmb_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_dlmb_ADDRSTROBE,
M_BE(0 to 3) => microblaze_0_dlmb_BE(0 to 3),
M_DBus(0 to 31) => microblaze_0_dlmb_WRITEDBUS(0 to 31),
M_ReadStrobe => microblaze_0_dlmb_READSTROBE,
M_WriteStrobe => microblaze_0_dlmb_WRITESTROBE,
SYS_Rst => SYS_Rst_1(0),
Sl_CE(0) => microblaze_0_dlmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_dlmb_bus_READDBUS(0 to 31),
Sl_Ready(0) => microblaze_0_dlmb_bus_READY,
Sl_UE(0) => microblaze_0_dlmb_bus_UE,
Sl_Wait(0) => microblaze_0_dlmb_bus_WAIT
);
ilmb_bram_if_cntlr: component system_ilmb_bram_if_cntlr_0
port map (
BRAM_Addr_A(0 to 31) => microblaze_0_ilmb_cntlr_ADDR(0 to 31),
BRAM_Clk_A => microblaze_0_ilmb_cntlr_CLK,
BRAM_Din_A(0) => microblaze_0_ilmb_cntlr_DOUT(31),
BRAM_Din_A(1) => microblaze_0_ilmb_cntlr_DOUT(30),
BRAM_Din_A(2) => microblaze_0_ilmb_cntlr_DOUT(29),
BRAM_Din_A(3) => microblaze_0_ilmb_cntlr_DOUT(28),
BRAM_Din_A(4) => microblaze_0_ilmb_cntlr_DOUT(27),
BRAM_Din_A(5) => microblaze_0_ilmb_cntlr_DOUT(26),
BRAM_Din_A(6) => microblaze_0_ilmb_cntlr_DOUT(25),
BRAM_Din_A(7) => microblaze_0_ilmb_cntlr_DOUT(24),
BRAM_Din_A(8) => microblaze_0_ilmb_cntlr_DOUT(23),
BRAM_Din_A(9) => microblaze_0_ilmb_cntlr_DOUT(22),
BRAM_Din_A(10) => microblaze_0_ilmb_cntlr_DOUT(21),
BRAM_Din_A(11) => microblaze_0_ilmb_cntlr_DOUT(20),
BRAM_Din_A(12) => microblaze_0_ilmb_cntlr_DOUT(19),
BRAM_Din_A(13) => microblaze_0_ilmb_cntlr_DOUT(18),
BRAM_Din_A(14) => microblaze_0_ilmb_cntlr_DOUT(17),
BRAM_Din_A(15) => microblaze_0_ilmb_cntlr_DOUT(16),
BRAM_Din_A(16) => microblaze_0_ilmb_cntlr_DOUT(15),
BRAM_Din_A(17) => microblaze_0_ilmb_cntlr_DOUT(14),
BRAM_Din_A(18) => microblaze_0_ilmb_cntlr_DOUT(13),
BRAM_Din_A(19) => microblaze_0_ilmb_cntlr_DOUT(12),
BRAM_Din_A(20) => microblaze_0_ilmb_cntlr_DOUT(11),
BRAM_Din_A(21) => microblaze_0_ilmb_cntlr_DOUT(10),
BRAM_Din_A(22) => microblaze_0_ilmb_cntlr_DOUT(9),
BRAM_Din_A(23) => microblaze_0_ilmb_cntlr_DOUT(8),
BRAM_Din_A(24) => microblaze_0_ilmb_cntlr_DOUT(7),
BRAM_Din_A(25) => microblaze_0_ilmb_cntlr_DOUT(6),
BRAM_Din_A(26) => microblaze_0_ilmb_cntlr_DOUT(5),
BRAM_Din_A(27) => microblaze_0_ilmb_cntlr_DOUT(4),
BRAM_Din_A(28) => microblaze_0_ilmb_cntlr_DOUT(3),
BRAM_Din_A(29) => microblaze_0_ilmb_cntlr_DOUT(2),
BRAM_Din_A(30) => microblaze_0_ilmb_cntlr_DOUT(1),
BRAM_Din_A(31) => microblaze_0_ilmb_cntlr_DOUT(0),
BRAM_Dout_A(0 to 31) => microblaze_0_ilmb_cntlr_DIN(0 to 31),
BRAM_EN_A => microblaze_0_ilmb_cntlr_EN,
BRAM_Rst_A => microblaze_0_ilmb_cntlr_RST,
BRAM_WEN_A(0 to 3) => microblaze_0_ilmb_cntlr_WE(0 to 3),
LMB_ABus(0 to 31) => microblaze_0_ilmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_ilmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_ilmb_bus_BE(0 to 3),
LMB_Clk => microblaze_0_Clk,
LMB_ReadStrobe => microblaze_0_ilmb_bus_READSTROBE,
LMB_Rst => SYS_Rst_1(0),
LMB_WriteDBus(0 to 31) => microblaze_0_ilmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_ilmb_bus_WRITESTROBE,
Sl_CE => microblaze_0_ilmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_ilmb_bus_READDBUS(0 to 31),
Sl_Ready => microblaze_0_ilmb_bus_READY,
Sl_UE => microblaze_0_ilmb_bus_UE,
Sl_Wait => microblaze_0_ilmb_bus_WAIT
);
ilmb_v10: component system_ilmb_v10_0
port map (
LMB_ABus(0 to 31) => microblaze_0_ilmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_ilmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_ilmb_bus_BE(0 to 3),
LMB_CE => microblaze_0_ilmb_CE,
LMB_Clk => microblaze_0_Clk,
LMB_ReadDBus(0 to 31) => microblaze_0_ilmb_READDBUS(0 to 31),
LMB_ReadStrobe => microblaze_0_ilmb_bus_READSTROBE,
LMB_Ready => microblaze_0_ilmb_READY,
LMB_Rst => NLW_ilmb_v10_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_ilmb_UE,
LMB_Wait => microblaze_0_ilmb_WAIT,
LMB_WriteDBus(0 to 31) => microblaze_0_ilmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_ilmb_bus_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_ilmb_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_ilmb_ADDRSTROBE,
M_BE(0 to 3) => B"0000",
M_DBus(0 to 31) => B"00000000000000000000000000000000",
M_ReadStrobe => microblaze_0_ilmb_READSTROBE,
M_WriteStrobe => '0',
SYS_Rst => SYS_Rst_1(0),
Sl_CE(0) => microblaze_0_ilmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_ilmb_bus_READDBUS(0 to 31),
Sl_Ready(0) => microblaze_0_ilmb_bus_READY,
Sl_UE(0) => microblaze_0_ilmb_bus_UE,
Sl_Wait(0) => microblaze_0_ilmb_bus_WAIT
);
lmb_bram: component system_lmb_bram_0
port map (
addra(31) => microblaze_0_dlmb_cntlr_ADDR(0),
addra(30) => microblaze_0_dlmb_cntlr_ADDR(1),
addra(29) => microblaze_0_dlmb_cntlr_ADDR(2),
addra(28) => microblaze_0_dlmb_cntlr_ADDR(3),
addra(27) => microblaze_0_dlmb_cntlr_ADDR(4),
addra(26) => microblaze_0_dlmb_cntlr_ADDR(5),
addra(25) => microblaze_0_dlmb_cntlr_ADDR(6),
addra(24) => microblaze_0_dlmb_cntlr_ADDR(7),
addra(23) => microblaze_0_dlmb_cntlr_ADDR(8),
addra(22) => microblaze_0_dlmb_cntlr_ADDR(9),
addra(21) => microblaze_0_dlmb_cntlr_ADDR(10),
addra(20) => microblaze_0_dlmb_cntlr_ADDR(11),
addra(19) => microblaze_0_dlmb_cntlr_ADDR(12),
addra(18) => microblaze_0_dlmb_cntlr_ADDR(13),
addra(17) => microblaze_0_dlmb_cntlr_ADDR(14),
addra(16) => microblaze_0_dlmb_cntlr_ADDR(15),
addra(15) => microblaze_0_dlmb_cntlr_ADDR(16),
addra(14) => microblaze_0_dlmb_cntlr_ADDR(17),
addra(13) => microblaze_0_dlmb_cntlr_ADDR(18),
addra(12) => microblaze_0_dlmb_cntlr_ADDR(19),
addra(11) => microblaze_0_dlmb_cntlr_ADDR(20),
addra(10) => microblaze_0_dlmb_cntlr_ADDR(21),
addra(9) => microblaze_0_dlmb_cntlr_ADDR(22),
addra(8) => microblaze_0_dlmb_cntlr_ADDR(23),
addra(7) => microblaze_0_dlmb_cntlr_ADDR(24),
addra(6) => microblaze_0_dlmb_cntlr_ADDR(25),
addra(5) => microblaze_0_dlmb_cntlr_ADDR(26),
addra(4) => microblaze_0_dlmb_cntlr_ADDR(27),
addra(3) => microblaze_0_dlmb_cntlr_ADDR(28),
addra(2) => microblaze_0_dlmb_cntlr_ADDR(29),
addra(1) => microblaze_0_dlmb_cntlr_ADDR(30),
addra(0) => microblaze_0_dlmb_cntlr_ADDR(31),
addrb(31) => microblaze_0_ilmb_cntlr_ADDR(0),
addrb(30) => microblaze_0_ilmb_cntlr_ADDR(1),
addrb(29) => microblaze_0_ilmb_cntlr_ADDR(2),
addrb(28) => microblaze_0_ilmb_cntlr_ADDR(3),
addrb(27) => microblaze_0_ilmb_cntlr_ADDR(4),
addrb(26) => microblaze_0_ilmb_cntlr_ADDR(5),
addrb(25) => microblaze_0_ilmb_cntlr_ADDR(6),
addrb(24) => microblaze_0_ilmb_cntlr_ADDR(7),
addrb(23) => microblaze_0_ilmb_cntlr_ADDR(8),
addrb(22) => microblaze_0_ilmb_cntlr_ADDR(9),
addrb(21) => microblaze_0_ilmb_cntlr_ADDR(10),
addrb(20) => microblaze_0_ilmb_cntlr_ADDR(11),
addrb(19) => microblaze_0_ilmb_cntlr_ADDR(12),
addrb(18) => microblaze_0_ilmb_cntlr_ADDR(13),
addrb(17) => microblaze_0_ilmb_cntlr_ADDR(14),
addrb(16) => microblaze_0_ilmb_cntlr_ADDR(15),
addrb(15) => microblaze_0_ilmb_cntlr_ADDR(16),
addrb(14) => microblaze_0_ilmb_cntlr_ADDR(17),
addrb(13) => microblaze_0_ilmb_cntlr_ADDR(18),
addrb(12) => microblaze_0_ilmb_cntlr_ADDR(19),
addrb(11) => microblaze_0_ilmb_cntlr_ADDR(20),
addrb(10) => microblaze_0_ilmb_cntlr_ADDR(21),
addrb(9) => microblaze_0_ilmb_cntlr_ADDR(22),
addrb(8) => microblaze_0_ilmb_cntlr_ADDR(23),
addrb(7) => microblaze_0_ilmb_cntlr_ADDR(24),
addrb(6) => microblaze_0_ilmb_cntlr_ADDR(25),
addrb(5) => microblaze_0_ilmb_cntlr_ADDR(26),
addrb(4) => microblaze_0_ilmb_cntlr_ADDR(27),
addrb(3) => microblaze_0_ilmb_cntlr_ADDR(28),
addrb(2) => microblaze_0_ilmb_cntlr_ADDR(29),
addrb(1) => microblaze_0_ilmb_cntlr_ADDR(30),
addrb(0) => microblaze_0_ilmb_cntlr_ADDR(31),
clka => microblaze_0_dlmb_cntlr_CLK,
clkb => microblaze_0_ilmb_cntlr_CLK,
dina(31) => microblaze_0_dlmb_cntlr_DIN(0),
dina(30) => microblaze_0_dlmb_cntlr_DIN(1),
dina(29) => microblaze_0_dlmb_cntlr_DIN(2),
dina(28) => microblaze_0_dlmb_cntlr_DIN(3),
dina(27) => microblaze_0_dlmb_cntlr_DIN(4),
dina(26) => microblaze_0_dlmb_cntlr_DIN(5),
dina(25) => microblaze_0_dlmb_cntlr_DIN(6),
dina(24) => microblaze_0_dlmb_cntlr_DIN(7),
dina(23) => microblaze_0_dlmb_cntlr_DIN(8),
dina(22) => microblaze_0_dlmb_cntlr_DIN(9),
dina(21) => microblaze_0_dlmb_cntlr_DIN(10),
dina(20) => microblaze_0_dlmb_cntlr_DIN(11),
dina(19) => microblaze_0_dlmb_cntlr_DIN(12),
dina(18) => microblaze_0_dlmb_cntlr_DIN(13),
dina(17) => microblaze_0_dlmb_cntlr_DIN(14),
dina(16) => microblaze_0_dlmb_cntlr_DIN(15),
dina(15) => microblaze_0_dlmb_cntlr_DIN(16),
dina(14) => microblaze_0_dlmb_cntlr_DIN(17),
dina(13) => microblaze_0_dlmb_cntlr_DIN(18),
dina(12) => microblaze_0_dlmb_cntlr_DIN(19),
dina(11) => microblaze_0_dlmb_cntlr_DIN(20),
dina(10) => microblaze_0_dlmb_cntlr_DIN(21),
dina(9) => microblaze_0_dlmb_cntlr_DIN(22),
dina(8) => microblaze_0_dlmb_cntlr_DIN(23),
dina(7) => microblaze_0_dlmb_cntlr_DIN(24),
dina(6) => microblaze_0_dlmb_cntlr_DIN(25),
dina(5) => microblaze_0_dlmb_cntlr_DIN(26),
dina(4) => microblaze_0_dlmb_cntlr_DIN(27),
dina(3) => microblaze_0_dlmb_cntlr_DIN(28),
dina(2) => microblaze_0_dlmb_cntlr_DIN(29),
dina(1) => microblaze_0_dlmb_cntlr_DIN(30),
dina(0) => microblaze_0_dlmb_cntlr_DIN(31),
dinb(31) => microblaze_0_ilmb_cntlr_DIN(0),
dinb(30) => microblaze_0_ilmb_cntlr_DIN(1),
dinb(29) => microblaze_0_ilmb_cntlr_DIN(2),
dinb(28) => microblaze_0_ilmb_cntlr_DIN(3),
dinb(27) => microblaze_0_ilmb_cntlr_DIN(4),
dinb(26) => microblaze_0_ilmb_cntlr_DIN(5),
dinb(25) => microblaze_0_ilmb_cntlr_DIN(6),
dinb(24) => microblaze_0_ilmb_cntlr_DIN(7),
dinb(23) => microblaze_0_ilmb_cntlr_DIN(8),
dinb(22) => microblaze_0_ilmb_cntlr_DIN(9),
dinb(21) => microblaze_0_ilmb_cntlr_DIN(10),
dinb(20) => microblaze_0_ilmb_cntlr_DIN(11),
dinb(19) => microblaze_0_ilmb_cntlr_DIN(12),
dinb(18) => microblaze_0_ilmb_cntlr_DIN(13),
dinb(17) => microblaze_0_ilmb_cntlr_DIN(14),
dinb(16) => microblaze_0_ilmb_cntlr_DIN(15),
dinb(15) => microblaze_0_ilmb_cntlr_DIN(16),
dinb(14) => microblaze_0_ilmb_cntlr_DIN(17),
dinb(13) => microblaze_0_ilmb_cntlr_DIN(18),
dinb(12) => microblaze_0_ilmb_cntlr_DIN(19),
dinb(11) => microblaze_0_ilmb_cntlr_DIN(20),
dinb(10) => microblaze_0_ilmb_cntlr_DIN(21),
dinb(9) => microblaze_0_ilmb_cntlr_DIN(22),
dinb(8) => microblaze_0_ilmb_cntlr_DIN(23),
dinb(7) => microblaze_0_ilmb_cntlr_DIN(24),
dinb(6) => microblaze_0_ilmb_cntlr_DIN(25),
dinb(5) => microblaze_0_ilmb_cntlr_DIN(26),
dinb(4) => microblaze_0_ilmb_cntlr_DIN(27),
dinb(3) => microblaze_0_ilmb_cntlr_DIN(28),
dinb(2) => microblaze_0_ilmb_cntlr_DIN(29),
dinb(1) => microblaze_0_ilmb_cntlr_DIN(30),
dinb(0) => microblaze_0_ilmb_cntlr_DIN(31),
douta(31 downto 0) => microblaze_0_dlmb_cntlr_DOUT(31 downto 0),
doutb(31 downto 0) => microblaze_0_ilmb_cntlr_DOUT(31 downto 0),
ena => microblaze_0_dlmb_cntlr_EN,
enb => microblaze_0_ilmb_cntlr_EN,
rsta => microblaze_0_dlmb_cntlr_RST,
rstb => microblaze_0_ilmb_cntlr_RST,
wea(3) => microblaze_0_dlmb_cntlr_WE(0),
wea(2) => microblaze_0_dlmb_cntlr_WE(1),
wea(1) => microblaze_0_dlmb_cntlr_WE(2),
wea(0) => microblaze_0_dlmb_cntlr_WE(3),
web(3) => microblaze_0_ilmb_cntlr_WE(0),
web(2) => microblaze_0_ilmb_cntlr_WE(1),
web(1) => microblaze_0_ilmb_cntlr_WE(2),
web(0) => microblaze_0_ilmb_cntlr_WE(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1LZPV07 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_1LZPV07;
architecture STRUCTURE of s00_couplers_imp_1LZPV07 is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= s00_couplers_to_s00_couplers_AWVALID(0);
M_AXI_bready(0) <= s00_couplers_to_s00_couplers_BREADY(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s00_couplers_to_s00_couplers_WVALID(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_awready(0) <= s00_couplers_to_s00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s00_couplers_to_s00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
S_AXI_wready(0) <= s00_couplers_to_s00_couplers_WREADY(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWREADY(0) <= M_AXI_awready(0);
s00_couplers_to_s00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s00_couplers_to_s00_couplers_BREADY(0) <= S_AXI_bready(0);
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID(0) <= M_AXI_bvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WREADY(0) <= M_AXI_wready(0);
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1P403ZT is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC;
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC;
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1P403ZT;
architecture STRUCTURE of s00_couplers_imp_1P403ZT is
component system_auto_us_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component system_auto_us_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal auto_us_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal auto_us_to_s00_couplers_WLAST : STD_LOGIC;
signal auto_us_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal auto_us_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_us_ARLOCK : STD_LOGIC;
signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_us_AWLOCK : STD_LOGIC;
signal s00_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_us_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_WVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_us_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_us_to_s00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_us_to_s00_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_us_to_s00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_us_to_s00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_us_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_us_to_s00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_us_to_s00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_us_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_us_to_s00_couplers_BREADY;
M_AXI_rready <= auto_us_to_s00_couplers_RREADY;
M_AXI_wdata(127 downto 0) <= auto_us_to_s00_couplers_WDATA(127 downto 0);
M_AXI_wlast <= auto_us_to_s00_couplers_WLAST;
M_AXI_wstrb(15 downto 0) <= auto_us_to_s00_couplers_WSTRB(15 downto 0);
M_AXI_wvalid <= auto_us_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_auto_us_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_us_AWREADY;
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_us_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_us_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID;
S_AXI_wready <= s00_couplers_to_auto_us_WREADY;
auto_us_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_us_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_us_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_us_to_s00_couplers_RDATA(127 downto 0) <= M_AXI_rdata(127 downto 0);
auto_us_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_us_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_auto_us_ARLOCK <= S_AXI_arlock;
s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_us_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s00_couplers_to_auto_us_AWLOCK <= S_AXI_awlock;
s00_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_us_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_us_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_us_BREADY <= S_AXI_bready;
s00_couplers_to_auto_us_RREADY <= S_AXI_rready;
s00_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_us_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_us_WVALID <= S_AXI_wvalid;
auto_us: component system_auto_us_0
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_us_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_us_to_s00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_us_to_s00_couplers_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => auto_us_to_s00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_us_to_s00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_us_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_us_to_s00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_us_to_s00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_us_to_s00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_us_to_s00_couplers_AWVALID,
m_axi_bready => auto_us_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_us_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_us_to_s00_couplers_BVALID,
m_axi_rdata(127 downto 0) => auto_us_to_s00_couplers_RDATA(127 downto 0),
m_axi_rlast => auto_us_to_s00_couplers_RLAST,
m_axi_rready => auto_us_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s00_couplers_RVALID,
m_axi_wdata(127 downto 0) => auto_us_to_s00_couplers_WDATA(127 downto 0),
m_axi_wlast => auto_us_to_s00_couplers_WLAST,
m_axi_wready => auto_us_to_s00_couplers_WREADY,
m_axi_wstrb(15 downto 0) => auto_us_to_s00_couplers_WSTRB(15 downto 0),
m_axi_wvalid => auto_us_to_s00_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arlen(7 downto 0) => s00_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => s00_couplers_to_auto_us_ARLOCK,
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_us_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_us_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_us_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_us_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_us_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_us_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => s00_couplers_to_auto_us_AWLEN(7 downto 0),
s_axi_awlock(0) => s00_couplers_to_auto_us_AWLOCK,
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_us_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_us_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_us_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_us_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_us_AWVALID,
s_axi_bready => s00_couplers_to_auto_us_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_us_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_us_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s00_couplers_to_auto_us_RLAST,
s_axi_rready => s00_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_us_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_us_WDATA(31 downto 0),
s_axi_wlast => s00_couplers_to_auto_us_WLAST,
s_axi_wready => s00_couplers_to_auto_us_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_us_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_us_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_VQ497S is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC;
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s01_couplers_imp_VQ497S;
architecture STRUCTURE of s01_couplers_imp_VQ497S is
component system_auto_us_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component system_auto_us_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s01_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal auto_us_to_s01_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s01_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_RVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_auto_us_ARLOCK : STD_LOGIC;
signal s01_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s01_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_RVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s01_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s01_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s01_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s01_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s01_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s01_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s01_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s01_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s01_couplers_ARVALID;
M_AXI_rready <= auto_us_to_s01_couplers_RREADY;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s01_couplers_to_auto_us_ARREADY;
S_AXI_rdata(31 downto 0) <= s01_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s01_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s01_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s01_couplers_to_auto_us_RVALID;
auto_us_to_s01_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s01_couplers_RDATA(127 downto 0) <= M_AXI_rdata(127 downto 0);
auto_us_to_s01_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s01_couplers_RVALID <= M_AXI_rvalid;
s01_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s01_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s01_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s01_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s01_couplers_to_auto_us_ARLOCK <= S_AXI_arlock;
s01_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s01_couplers_to_auto_us_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s01_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s01_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s01_couplers_to_auto_us_RREADY <= S_AXI_rready;
auto_us: component system_auto_us_1
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s01_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s01_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s01_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s01_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s01_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s01_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s01_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s01_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s01_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s01_couplers_ARVALID,
m_axi_rdata(127 downto 0) => auto_us_to_s01_couplers_RDATA(127 downto 0),
m_axi_rlast => auto_us_to_s01_couplers_RLAST,
m_axi_rready => auto_us_to_s01_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s01_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s01_couplers_RVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s01_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s01_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s01_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arlen(7 downto 0) => s01_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => s01_couplers_to_auto_us_ARLOCK,
s_axi_arprot(2 downto 0) => s01_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s01_couplers_to_auto_us_ARQOS(3 downto 0),
s_axi_arready => s01_couplers_to_auto_us_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s01_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s01_couplers_to_auto_us_ARVALID,
s_axi_rdata(31 downto 0) => s01_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s01_couplers_to_auto_us_RLAST,
s_axi_rready => s01_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s01_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s01_couplers_to_auto_us_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arlock : out STD_LOGIC;
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awlock : out STD_LOGIC;
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC;
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC;
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC;
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_arlock : in STD_LOGIC;
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arready : out STD_LOGIC;
S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arvalid : in STD_LOGIC;
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_rlast : out STD_LOGIC;
S01_AXI_rready : in STD_LOGIC;
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rvalid : out STD_LOGIC
);
end system_axi_mem_intercon_0;
architecture STRUCTURE of system_axi_mem_intercon_0 is
component system_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC;
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLOCK : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWLOCK : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARLOCK : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 27 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 27 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal s00_couplers_to_xbar_WLAST : STD_LOGIC;
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal s01_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s01_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 255 downto 128 );
signal s01_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RREADY : STD_LOGIC;
signal s01_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(27 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(27 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(0) <= m00_couplers_to_axi_mem_intercon_ARID(0);
M00_AXI_arlen(7 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(7 downto 0);
M00_AXI_arlock <= m00_couplers_to_axi_mem_intercon_ARLOCK;
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(27 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(27 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(0) <= m00_couplers_to_axi_mem_intercon_AWID(0);
M00_AXI_awlen(7 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(7 downto 0);
M00_AXI_awlock <= m00_couplers_to_axi_mem_intercon_AWLOCK;
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(127 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(127 downto 0);
M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(15 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(15 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_mem_intercon_to_s00_couplers_AWREADY;
S00_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_mem_intercon_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_mem_intercon_to_s00_couplers_WREADY;
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1 <= S01_ARESETN;
S01_AXI_arready <= axi_mem_intercon_to_s01_couplers_ARREADY;
S01_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s01_couplers_RDATA(31 downto 0);
S01_AXI_rlast <= axi_mem_intercon_to_s01_couplers_RLAST;
S01_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_RRESP(1 downto 0);
S01_AXI_rvalid <= axi_mem_intercon_to_s01_couplers_RVALID;
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net <= ARESETN;
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARLOCK <= S00_AXI_arlock;
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWLEN(7 downto 0) <= S00_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_AWLOCK <= S00_AXI_awlock;
axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_mem_intercon_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s00_couplers_WVALID <= S00_AXI_wvalid;
axi_mem_intercon_to_s01_couplers_ARADDR(31 downto 0) <= S01_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_ARBURST(1 downto 0) <= S01_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_ARCACHE(3 downto 0) <= S01_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_ARLEN(7 downto 0) <= S01_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_ARLOCK <= S01_AXI_arlock;
axi_mem_intercon_to_s01_couplers_ARPROT(2 downto 0) <= S01_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_ARQOS(3 downto 0) <= S01_AXI_arqos(3 downto 0);
axi_mem_intercon_to_s01_couplers_ARSIZE(2 downto 0) <= S01_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_ARVALID <= S01_AXI_arvalid;
axi_mem_intercon_to_s01_couplers_RREADY <= S01_AXI_rready;
m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_mem_intercon_BID(0) <= M00_AXI_bid(0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_mem_intercon_RDATA(127 downto 0) <= M00_AXI_rdata(127 downto 0);
m00_couplers_to_axi_mem_intercon_RID(0) <= M00_AXI_rid(0);
m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_1TEAG88
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(27 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(27 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(0) => m00_couplers_to_axi_mem_intercon_ARID(0),
M_AXI_arlen(7 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(7 downto 0),
M_AXI_arlock => m00_couplers_to_axi_mem_intercon_ARLOCK,
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0),
M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(27 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(27 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(0) => m00_couplers_to_axi_mem_intercon_AWID(0),
M_AXI_awlen(7 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(7 downto 0),
M_AXI_awlock => m00_couplers_to_axi_mem_intercon_AWLOCK,
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0),
M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(0) => m00_couplers_to_axi_mem_intercon_BID(0),
M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(127 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(127 downto 0),
M_AXI_rid(0) => m00_couplers_to_axi_mem_intercon_RID(0),
M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(127 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(127 downto 0),
M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(15 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(15 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN => axi_mem_intercon_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => xbar_to_m00_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => xbar_to_m00_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(0) => xbar_to_m00_couplers_BID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(127 downto 0) => xbar_to_m00_couplers_RDATA(127 downto 0),
S_AXI_rid(0) => xbar_to_m00_couplers_RID(0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(127 downto 0) => xbar_to_m00_couplers_WDATA(127 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(15 downto 0) => xbar_to_m00_couplers_WSTRB(15 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_1P403ZT
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(127 downto 0) => s00_couplers_to_xbar_RDATA(127 downto 0),
M_AXI_rlast => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(127 downto 0) => s00_couplers_to_xbar_WDATA(127 downto 0),
M_AXI_wlast => s00_couplers_to_xbar_WLAST,
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(15 downto 0) => s00_couplers_to_xbar_WSTRB(15 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arlock => axi_mem_intercon_to_s00_couplers_ARLOCK,
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_AWLEN(7 downto 0),
S_AXI_awlock => axi_mem_intercon_to_s00_couplers_AWLOCK,
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => axi_mem_intercon_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s00_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s00_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s00_couplers_WVALID
);
s01_couplers: entity work.s01_couplers_imp_VQ497S
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_araddr(31 downto 0) => s01_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s01_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s01_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s01_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s01_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s01_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s01_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s01_couplers_to_xbar_ARREADY(1),
M_AXI_arsize(2 downto 0) => s01_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s01_couplers_to_xbar_ARVALID,
M_AXI_rdata(127 downto 0) => s01_couplers_to_xbar_RDATA(255 downto 128),
M_AXI_rlast => s01_couplers_to_xbar_RLAST(1),
M_AXI_rready => s01_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s01_couplers_to_xbar_RRESP(3 downto 2),
M_AXI_rvalid => s01_couplers_to_xbar_RVALID(1),
S_ACLK => S01_ACLK_1,
S_ARESETN => S01_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_ARLEN(7 downto 0),
S_AXI_arlock => axi_mem_intercon_to_s01_couplers_ARLOCK,
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_mem_intercon_to_s01_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_mem_intercon_to_s01_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s01_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s01_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s01_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s01_couplers_RVALID
);
xbar: component system_xbar_0
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net,
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => xbar_to_m00_couplers_ARID(0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => xbar_to_m00_couplers_AWID(0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(0) => xbar_to_m00_couplers_BID(0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(127 downto 0) => xbar_to_m00_couplers_RDATA(127 downto 0),
m_axi_rid(0) => xbar_to_m00_couplers_RID(0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(127 downto 0) => xbar_to_m00_couplers_WDATA(127 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(15 downto 0) => xbar_to_m00_couplers_WSTRB(15 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(63 downto 32) => s01_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(3 downto 2) => s01_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(7 downto 4) => s01_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(1 downto 0) => B"00",
s_axi_arlen(15 downto 8) => s01_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(1) => s01_couplers_to_xbar_ARLOCK(0),
s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
s_axi_arprot(5 downto 3) => s01_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(7 downto 4) => s01_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arready(1) => s01_couplers_to_xbar_ARREADY(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(5 downto 3) => s01_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(1) => s01_couplers_to_xbar_ARVALID,
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(63 downto 32) => B"00000000000000000000000000000000",
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awburst(3 downto 2) => B"00",
s_axi_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awcache(7 downto 4) => B"0000",
s_axi_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awid(1 downto 0) => B"00",
s_axi_awlen(15 downto 8) => B"00000000",
s_axi_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlock(1) => '0',
s_axi_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
s_axi_awprot(5 downto 3) => B"000",
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awqos(7 downto 4) => B"0000",
s_axi_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awready(1) => NLW_xbar_s_axi_awready_UNCONNECTED(1),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awsize(5 downto 3) => B"000",
s_axi_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awvalid(1) => '0',
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bid(1 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(1 downto 0),
s_axi_bready(1) => '0',
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(3 downto 2) => NLW_xbar_s_axi_bresp_UNCONNECTED(3 downto 2),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(1) => NLW_xbar_s_axi_bvalid_UNCONNECTED(1),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(255 downto 128) => s01_couplers_to_xbar_RDATA(255 downto 128),
s_axi_rdata(127 downto 0) => s00_couplers_to_xbar_RDATA(127 downto 0),
s_axi_rid(1 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(1 downto 0),
s_axi_rlast(1) => s01_couplers_to_xbar_RLAST(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(1) => s01_couplers_to_xbar_RREADY,
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(3 downto 2) => s01_couplers_to_xbar_RRESP(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(1) => s01_couplers_to_xbar_RVALID(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(255 downto 128) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
s_axi_wdata(127 downto 0) => s00_couplers_to_xbar_WDATA(127 downto 0),
s_axi_wlast(1) => '1',
s_axi_wlast(0) => s00_couplers_to_xbar_WLAST,
s_axi_wready(1) => NLW_xbar_s_axi_wready_UNCONNECTED(1),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(31 downto 16) => B"1111111111111111",
s_axi_wstrb(15 downto 0) => s00_couplers_to_xbar_WSTRB(15 downto 0),
s_axi_wvalid(1) => '0',
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC;
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC;
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M05_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_ACLK : in STD_LOGIC;
M06_ARESETN : in STD_LOGIC;
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_ACLK : in STD_LOGIC;
M07_ARESETN : in STD_LOGIC;
M07_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M07_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M07_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M07_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M07_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M07_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M07_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M07_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_ACLK : in STD_LOGIC;
M08_ARESETN : in STD_LOGIC;
M08_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M08_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M08_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M08_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M08_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M08_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M08_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M08_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M09_ACLK : in STD_LOGIC;
M09_ARESETN : in STD_LOGIC;
M09_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M09_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M09_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M09_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M09_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M09_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M09_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M09_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M10_ACLK : in STD_LOGIC;
M10_ARESETN : in STD_LOGIC;
M10_AXI_araddr : out STD_LOGIC;
M10_AXI_arprot : out STD_LOGIC;
M10_AXI_arready : in STD_LOGIC;
M10_AXI_arvalid : out STD_LOGIC;
M10_AXI_awaddr : out STD_LOGIC;
M10_AXI_awprot : out STD_LOGIC;
M10_AXI_awready : in STD_LOGIC;
M10_AXI_awvalid : out STD_LOGIC;
M10_AXI_bready : out STD_LOGIC;
M10_AXI_bresp : in STD_LOGIC;
M10_AXI_bvalid : in STD_LOGIC;
M10_AXI_rdata : in STD_LOGIC;
M10_AXI_rready : out STD_LOGIC;
M10_AXI_rresp : in STD_LOGIC;
M10_AXI_rvalid : in STD_LOGIC;
M10_AXI_wdata : out STD_LOGIC;
M10_AXI_wready : in STD_LOGIC;
M10_AXI_wstrb : out STD_LOGIC;
M10_AXI_wvalid : out STD_LOGIC;
M11_ACLK : in STD_LOGIC;
M11_ARESETN : in STD_LOGIC;
M11_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M11_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M11_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M11_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M11_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M11_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M11_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M11_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M12_ACLK : in STD_LOGIC;
M12_ARESETN : in STD_LOGIC;
M12_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M12_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M12_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M12_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M12_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M12_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M12_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M12_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M13_ACLK : in STD_LOGIC;
M13_ARESETN : in STD_LOGIC;
M13_AXI_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M13_AXI_arready : in STD_LOGIC;
M13_AXI_arvalid : out STD_LOGIC;
M13_AXI_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M13_AXI_awready : in STD_LOGIC;
M13_AXI_awvalid : out STD_LOGIC;
M13_AXI_bready : out STD_LOGIC;
M13_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M13_AXI_bvalid : in STD_LOGIC;
M13_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M13_AXI_rready : out STD_LOGIC;
M13_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M13_AXI_rvalid : in STD_LOGIC;
M13_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M13_AXI_wready : in STD_LOGIC;
M13_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M13_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_microblaze_0_axi_periph_0;
architecture STRUCTURE of system_microblaze_0_axi_periph_0 is
component system_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 55 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
end component system_xbar_1;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC;
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC;
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC;
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC;
signal M05_ACLK_1 : STD_LOGIC;
signal M05_ARESETN_1 : STD_LOGIC;
signal M06_ACLK_1 : STD_LOGIC;
signal M06_ARESETN_1 : STD_LOGIC;
signal M07_ACLK_1 : STD_LOGIC;
signal M07_ARESETN_1 : STD_LOGIC;
signal M08_ACLK_1 : STD_LOGIC;
signal M08_ARESETN_1 : STD_LOGIC;
signal M09_ACLK_1 : STD_LOGIC;
signal M09_ARESETN_1 : STD_LOGIC;
signal M10_ACLK_1 : STD_LOGIC;
signal M10_ARESETN_1 : STD_LOGIC;
signal M11_ACLK_1 : STD_LOGIC;
signal M11_ARESETN_1 : STD_LOGIC;
signal M12_ACLK_1 : STD_LOGIC;
signal M12_ARESETN_1 : STD_LOGIC;
signal M13_ACLK_1 : STD_LOGIC;
signal M13_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m10_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_ARPROT : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_AWPROT : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m11_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m13_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_ACLK_net : STD_LOGIC;
signal microblaze_0_axi_periph_ARESETN_net : STD_LOGIC;
signal microblaze_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 23 downto 20 );
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 27 downto 24 );
signal xbar_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m07_couplers_ARADDR : STD_LOGIC_VECTOR ( 255 downto 224 );
signal xbar_to_m07_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_ARVALID : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m07_couplers_AWADDR : STD_LOGIC_VECTOR ( 255 downto 224 );
signal xbar_to_m07_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_AWVALID : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m07_couplers_BREADY : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m07_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m07_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m07_couplers_RREADY : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m07_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m07_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_WDATA : STD_LOGIC_VECTOR ( 255 downto 224 );
signal xbar_to_m07_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_WSTRB : STD_LOGIC_VECTOR ( 31 downto 28 );
signal xbar_to_m07_couplers_WVALID : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m08_couplers_ARADDR : STD_LOGIC_VECTOR ( 287 downto 256 );
signal xbar_to_m08_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_ARVALID : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m08_couplers_AWADDR : STD_LOGIC_VECTOR ( 287 downto 256 );
signal xbar_to_m08_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_AWVALID : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m08_couplers_BREADY : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m08_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m08_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m08_couplers_RREADY : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m08_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m08_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_WDATA : STD_LOGIC_VECTOR ( 287 downto 256 );
signal xbar_to_m08_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_WSTRB : STD_LOGIC_VECTOR ( 35 downto 32 );
signal xbar_to_m08_couplers_WVALID : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m09_couplers_ARADDR : STD_LOGIC_VECTOR ( 319 downto 288 );
signal xbar_to_m09_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m09_couplers_ARVALID : STD_LOGIC_VECTOR ( 9 to 9 );
signal xbar_to_m09_couplers_AWADDR : STD_LOGIC_VECTOR ( 319 downto 288 );
signal xbar_to_m09_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m09_couplers_AWVALID : STD_LOGIC_VECTOR ( 9 to 9 );
signal xbar_to_m09_couplers_BREADY : STD_LOGIC_VECTOR ( 9 to 9 );
signal xbar_to_m09_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m09_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m09_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m09_couplers_RREADY : STD_LOGIC_VECTOR ( 9 to 9 );
signal xbar_to_m09_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m09_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m09_couplers_WDATA : STD_LOGIC_VECTOR ( 319 downto 288 );
signal xbar_to_m09_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m09_couplers_WSTRB : STD_LOGIC_VECTOR ( 39 downto 36 );
signal xbar_to_m09_couplers_WVALID : STD_LOGIC_VECTOR ( 9 to 9 );
signal xbar_to_m10_couplers_ARADDR : STD_LOGIC_VECTOR ( 351 downto 320 );
signal xbar_to_m10_couplers_ARPROT : STD_LOGIC_VECTOR ( 32 downto 30 );
signal xbar_to_m10_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m10_couplers_ARVALID : STD_LOGIC_VECTOR ( 10 to 10 );
signal xbar_to_m10_couplers_AWADDR : STD_LOGIC_VECTOR ( 351 downto 320 );
signal xbar_to_m10_couplers_AWPROT : STD_LOGIC_VECTOR ( 32 downto 30 );
signal xbar_to_m10_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m10_couplers_AWVALID : STD_LOGIC_VECTOR ( 10 to 10 );
signal xbar_to_m10_couplers_BREADY : STD_LOGIC_VECTOR ( 10 to 10 );
signal xbar_to_m10_couplers_BRESP : STD_LOGIC;
signal xbar_to_m10_couplers_BVALID : STD_LOGIC;
signal xbar_to_m10_couplers_RDATA : STD_LOGIC;
signal xbar_to_m10_couplers_RREADY : STD_LOGIC_VECTOR ( 10 to 10 );
signal xbar_to_m10_couplers_RRESP : STD_LOGIC;
signal xbar_to_m10_couplers_RVALID : STD_LOGIC;
signal xbar_to_m10_couplers_WDATA : STD_LOGIC_VECTOR ( 351 downto 320 );
signal xbar_to_m10_couplers_WREADY : STD_LOGIC;
signal xbar_to_m10_couplers_WSTRB : STD_LOGIC_VECTOR ( 43 downto 40 );
signal xbar_to_m10_couplers_WVALID : STD_LOGIC_VECTOR ( 10 to 10 );
signal xbar_to_m11_couplers_ARADDR : STD_LOGIC_VECTOR ( 383 downto 352 );
signal xbar_to_m11_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m11_couplers_ARVALID : STD_LOGIC_VECTOR ( 11 to 11 );
signal xbar_to_m11_couplers_AWADDR : STD_LOGIC_VECTOR ( 383 downto 352 );
signal xbar_to_m11_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m11_couplers_AWVALID : STD_LOGIC_VECTOR ( 11 to 11 );
signal xbar_to_m11_couplers_BREADY : STD_LOGIC_VECTOR ( 11 to 11 );
signal xbar_to_m11_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m11_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m11_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m11_couplers_RREADY : STD_LOGIC_VECTOR ( 11 to 11 );
signal xbar_to_m11_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m11_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m11_couplers_WDATA : STD_LOGIC_VECTOR ( 383 downto 352 );
signal xbar_to_m11_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m11_couplers_WSTRB : STD_LOGIC_VECTOR ( 47 downto 44 );
signal xbar_to_m11_couplers_WVALID : STD_LOGIC_VECTOR ( 11 to 11 );
signal xbar_to_m12_couplers_ARADDR : STD_LOGIC_VECTOR ( 415 downto 384 );
signal xbar_to_m12_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m12_couplers_ARVALID : STD_LOGIC_VECTOR ( 12 to 12 );
signal xbar_to_m12_couplers_AWADDR : STD_LOGIC_VECTOR ( 415 downto 384 );
signal xbar_to_m12_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m12_couplers_AWVALID : STD_LOGIC_VECTOR ( 12 to 12 );
signal xbar_to_m12_couplers_BREADY : STD_LOGIC_VECTOR ( 12 to 12 );
signal xbar_to_m12_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m12_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m12_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m12_couplers_RREADY : STD_LOGIC_VECTOR ( 12 to 12 );
signal xbar_to_m12_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m12_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m12_couplers_WDATA : STD_LOGIC_VECTOR ( 415 downto 384 );
signal xbar_to_m12_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m12_couplers_WSTRB : STD_LOGIC_VECTOR ( 51 downto 48 );
signal xbar_to_m12_couplers_WVALID : STD_LOGIC_VECTOR ( 12 to 12 );
signal xbar_to_m13_couplers_ARADDR : STD_LOGIC_VECTOR ( 447 downto 416 );
signal xbar_to_m13_couplers_ARPROT : STD_LOGIC_VECTOR ( 41 downto 39 );
signal xbar_to_m13_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m13_couplers_ARVALID : STD_LOGIC_VECTOR ( 13 to 13 );
signal xbar_to_m13_couplers_AWADDR : STD_LOGIC_VECTOR ( 447 downto 416 );
signal xbar_to_m13_couplers_AWPROT : STD_LOGIC_VECTOR ( 41 downto 39 );
signal xbar_to_m13_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m13_couplers_AWVALID : STD_LOGIC_VECTOR ( 13 to 13 );
signal xbar_to_m13_couplers_BREADY : STD_LOGIC_VECTOR ( 13 to 13 );
signal xbar_to_m13_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m13_couplers_BVALID : STD_LOGIC;
signal xbar_to_m13_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m13_couplers_RREADY : STD_LOGIC_VECTOR ( 13 to 13 );
signal xbar_to_m13_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m13_couplers_RVALID : STD_LOGIC;
signal xbar_to_m13_couplers_WDATA : STD_LOGIC_VECTOR ( 447 downto 416 );
signal xbar_to_m13_couplers_WREADY : STD_LOGIC;
signal xbar_to_m13_couplers_WSTRB : STD_LOGIC_VECTOR ( 55 downto 52 );
signal xbar_to_m13_couplers_WVALID : STD_LOGIC_VECTOR ( 13 to 13 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 38 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 38 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_microblaze_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_microblaze_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_microblaze_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1 <= M01_ARESETN;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_microblaze_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_microblaze_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_microblaze_0_axi_periph_WVALID(0);
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1 <= M02_ARESETN;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M02_AXI_arvalid(0) <= m02_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M02_AXI_awvalid(0) <= m02_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M02_AXI_bready(0) <= m02_couplers_to_microblaze_0_axi_periph_BREADY(0);
M02_AXI_rready(0) <= m02_couplers_to_microblaze_0_axi_periph_RREADY(0);
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid(0) <= m02_couplers_to_microblaze_0_axi_periph_WVALID(0);
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1 <= M03_ARESETN;
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M03_AXI_arvalid(0) <= m03_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M03_AXI_awvalid(0) <= m03_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M03_AXI_bready(0) <= m03_couplers_to_microblaze_0_axi_periph_BREADY(0);
M03_AXI_rready(0) <= m03_couplers_to_microblaze_0_axi_periph_RREADY(0);
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M03_AXI_wvalid(0) <= m03_couplers_to_microblaze_0_axi_periph_WVALID(0);
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1 <= M04_ARESETN;
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M04_AXI_arvalid(0) <= m04_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M04_AXI_awvalid(0) <= m04_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M04_AXI_bready(0) <= m04_couplers_to_microblaze_0_axi_periph_BREADY(0);
M04_AXI_rready(0) <= m04_couplers_to_microblaze_0_axi_periph_RREADY(0);
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M04_AXI_wvalid(0) <= m04_couplers_to_microblaze_0_axi_periph_WVALID(0);
M05_ACLK_1 <= M05_ACLK;
M05_ARESETN_1 <= M05_ARESETN;
M05_AXI_araddr(31 downto 0) <= m05_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M05_AXI_arvalid(0) <= m05_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M05_AXI_awaddr(31 downto 0) <= m05_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M05_AXI_awvalid(0) <= m05_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M05_AXI_bready(0) <= m05_couplers_to_microblaze_0_axi_periph_BREADY(0);
M05_AXI_rready(0) <= m05_couplers_to_microblaze_0_axi_periph_RREADY(0);
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M05_AXI_wstrb(3 downto 0) <= m05_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M05_AXI_wvalid(0) <= m05_couplers_to_microblaze_0_axi_periph_WVALID(0);
M06_ACLK_1 <= M06_ACLK;
M06_ARESETN_1 <= M06_ARESETN;
M06_AXI_araddr(31 downto 0) <= m06_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M06_AXI_arvalid(0) <= m06_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M06_AXI_awaddr(31 downto 0) <= m06_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M06_AXI_awvalid(0) <= m06_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M06_AXI_bready(0) <= m06_couplers_to_microblaze_0_axi_periph_BREADY(0);
M06_AXI_rready(0) <= m06_couplers_to_microblaze_0_axi_periph_RREADY(0);
M06_AXI_wdata(31 downto 0) <= m06_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M06_AXI_wstrb(3 downto 0) <= m06_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M06_AXI_wvalid(0) <= m06_couplers_to_microblaze_0_axi_periph_WVALID(0);
M07_ACLK_1 <= M07_ACLK;
M07_ARESETN_1 <= M07_ARESETN;
M07_AXI_araddr(31 downto 0) <= m07_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M07_AXI_arvalid(0) <= m07_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M07_AXI_awaddr(31 downto 0) <= m07_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M07_AXI_awvalid(0) <= m07_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M07_AXI_bready(0) <= m07_couplers_to_microblaze_0_axi_periph_BREADY(0);
M07_AXI_rready(0) <= m07_couplers_to_microblaze_0_axi_periph_RREADY(0);
M07_AXI_wdata(31 downto 0) <= m07_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M07_AXI_wstrb(3 downto 0) <= m07_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M07_AXI_wvalid(0) <= m07_couplers_to_microblaze_0_axi_periph_WVALID(0);
M08_ACLK_1 <= M08_ACLK;
M08_ARESETN_1 <= M08_ARESETN;
M08_AXI_araddr(31 downto 0) <= m08_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M08_AXI_arvalid(0) <= m08_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M08_AXI_awaddr(31 downto 0) <= m08_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M08_AXI_awvalid(0) <= m08_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M08_AXI_bready(0) <= m08_couplers_to_microblaze_0_axi_periph_BREADY(0);
M08_AXI_rready(0) <= m08_couplers_to_microblaze_0_axi_periph_RREADY(0);
M08_AXI_wdata(31 downto 0) <= m08_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M08_AXI_wstrb(3 downto 0) <= m08_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M08_AXI_wvalid(0) <= m08_couplers_to_microblaze_0_axi_periph_WVALID(0);
M09_ACLK_1 <= M09_ACLK;
M09_ARESETN_1 <= M09_ARESETN;
M09_AXI_araddr(31 downto 0) <= m09_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M09_AXI_arvalid(0) <= m09_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M09_AXI_awaddr(31 downto 0) <= m09_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M09_AXI_awvalid(0) <= m09_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M09_AXI_bready(0) <= m09_couplers_to_microblaze_0_axi_periph_BREADY(0);
M09_AXI_rready(0) <= m09_couplers_to_microblaze_0_axi_periph_RREADY(0);
M09_AXI_wdata(31 downto 0) <= m09_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M09_AXI_wstrb(3 downto 0) <= m09_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M09_AXI_wvalid(0) <= m09_couplers_to_microblaze_0_axi_periph_WVALID(0);
M10_ACLK_1 <= M10_ACLK;
M10_ARESETN_1 <= M10_ARESETN;
M10_AXI_araddr <= m10_couplers_to_microblaze_0_axi_periph_ARADDR;
M10_AXI_arprot <= m10_couplers_to_microblaze_0_axi_periph_ARPROT;
M10_AXI_arvalid <= m10_couplers_to_microblaze_0_axi_periph_ARVALID;
M10_AXI_awaddr <= m10_couplers_to_microblaze_0_axi_periph_AWADDR;
M10_AXI_awprot <= m10_couplers_to_microblaze_0_axi_periph_AWPROT;
M10_AXI_awvalid <= m10_couplers_to_microblaze_0_axi_periph_AWVALID;
M10_AXI_bready <= m10_couplers_to_microblaze_0_axi_periph_BREADY;
M10_AXI_rready <= m10_couplers_to_microblaze_0_axi_periph_RREADY;
M10_AXI_wdata <= m10_couplers_to_microblaze_0_axi_periph_WDATA;
M10_AXI_wstrb <= m10_couplers_to_microblaze_0_axi_periph_WSTRB;
M10_AXI_wvalid <= m10_couplers_to_microblaze_0_axi_periph_WVALID;
M11_ACLK_1 <= M11_ACLK;
M11_ARESETN_1 <= M11_ARESETN;
M11_AXI_araddr(31 downto 0) <= m11_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M11_AXI_arvalid(0) <= m11_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M11_AXI_awaddr(31 downto 0) <= m11_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M11_AXI_awvalid(0) <= m11_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M11_AXI_bready(0) <= m11_couplers_to_microblaze_0_axi_periph_BREADY(0);
M11_AXI_rready(0) <= m11_couplers_to_microblaze_0_axi_periph_RREADY(0);
M11_AXI_wdata(31 downto 0) <= m11_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M11_AXI_wstrb(3 downto 0) <= m11_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M11_AXI_wvalid(0) <= m11_couplers_to_microblaze_0_axi_periph_WVALID(0);
M12_ACLK_1 <= M12_ACLK;
M12_ARESETN_1 <= M12_ARESETN;
M12_AXI_araddr(31 downto 0) <= m12_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M12_AXI_arvalid(0) <= m12_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M12_AXI_awaddr(31 downto 0) <= m12_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M12_AXI_awvalid(0) <= m12_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M12_AXI_bready(0) <= m12_couplers_to_microblaze_0_axi_periph_BREADY(0);
M12_AXI_rready(0) <= m12_couplers_to_microblaze_0_axi_periph_RREADY(0);
M12_AXI_wdata(31 downto 0) <= m12_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M12_AXI_wstrb(3 downto 0) <= m12_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M12_AXI_wvalid(0) <= m12_couplers_to_microblaze_0_axi_periph_WVALID(0);
M13_ACLK_1 <= M13_ACLK;
M13_ARESETN_1 <= M13_ARESETN;
M13_AXI_araddr(10 downto 0) <= m13_couplers_to_microblaze_0_axi_periph_ARADDR(10 downto 0);
M13_AXI_arvalid <= m13_couplers_to_microblaze_0_axi_periph_ARVALID;
M13_AXI_awaddr(10 downto 0) <= m13_couplers_to_microblaze_0_axi_periph_AWADDR(10 downto 0);
M13_AXI_awvalid <= m13_couplers_to_microblaze_0_axi_periph_AWVALID;
M13_AXI_bready <= m13_couplers_to_microblaze_0_axi_periph_BREADY;
M13_AXI_rready <= m13_couplers_to_microblaze_0_axi_periph_RREADY;
M13_AXI_wdata(31 downto 0) <= m13_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M13_AXI_wstrb(3 downto 0) <= m13_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M13_AXI_wvalid <= m13_couplers_to_microblaze_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready(0) <= microblaze_0_axi_periph_to_s00_couplers_ARREADY(0);
S00_AXI_awready(0) <= microblaze_0_axi_periph_to_s00_couplers_AWREADY(0);
S00_AXI_bresp(1 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid(0) <= microblaze_0_axi_periph_to_s00_couplers_BVALID(0);
S00_AXI_rdata(31 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rresp(1 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= microblaze_0_axi_periph_to_s00_couplers_RVALID(0);
S00_AXI_wready(0) <= microblaze_0_axi_periph_to_s00_couplers_WREADY(0);
m00_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
m02_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M02_AXI_arready(0);
m02_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M02_AXI_awready(0);
m02_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M02_AXI_bvalid(0);
m02_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M02_AXI_rvalid(0);
m02_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M02_AXI_wready(0);
m03_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M03_AXI_arready(0);
m03_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M03_AXI_awready(0);
m03_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M03_AXI_bvalid(0);
m03_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M03_AXI_rvalid(0);
m03_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M03_AXI_wready(0);
m04_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M04_AXI_arready(0);
m04_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M04_AXI_awready(0);
m04_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M04_AXI_bvalid(0);
m04_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M04_AXI_rvalid(0);
m04_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M04_AXI_wready(0);
m05_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M05_AXI_arready(0);
m05_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M05_AXI_awready(0);
m05_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M05_AXI_bvalid(0);
m05_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M05_AXI_rvalid(0);
m05_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M05_AXI_wready(0);
m06_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M06_AXI_arready(0);
m06_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M06_AXI_awready(0);
m06_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M06_AXI_bresp(1 downto 0);
m06_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M06_AXI_bvalid(0);
m06_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M06_AXI_rdata(31 downto 0);
m06_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M06_AXI_rresp(1 downto 0);
m06_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M06_AXI_rvalid(0);
m06_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M06_AXI_wready(0);
m07_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M07_AXI_arready(0);
m07_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M07_AXI_awready(0);
m07_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M07_AXI_bresp(1 downto 0);
m07_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M07_AXI_bvalid(0);
m07_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M07_AXI_rdata(31 downto 0);
m07_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M07_AXI_rresp(1 downto 0);
m07_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M07_AXI_rvalid(0);
m07_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M07_AXI_wready(0);
m08_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M08_AXI_arready(0);
m08_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M08_AXI_awready(0);
m08_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M08_AXI_bresp(1 downto 0);
m08_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M08_AXI_bvalid(0);
m08_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M08_AXI_rdata(31 downto 0);
m08_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M08_AXI_rresp(1 downto 0);
m08_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M08_AXI_rvalid(0);
m08_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M08_AXI_wready(0);
m09_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M09_AXI_arready(0);
m09_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M09_AXI_awready(0);
m09_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M09_AXI_bresp(1 downto 0);
m09_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M09_AXI_bvalid(0);
m09_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M09_AXI_rdata(31 downto 0);
m09_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M09_AXI_rresp(1 downto 0);
m09_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M09_AXI_rvalid(0);
m09_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M09_AXI_wready(0);
m10_couplers_to_microblaze_0_axi_periph_ARREADY <= M10_AXI_arready;
m10_couplers_to_microblaze_0_axi_periph_AWREADY <= M10_AXI_awready;
m10_couplers_to_microblaze_0_axi_periph_BRESP <= M10_AXI_bresp;
m10_couplers_to_microblaze_0_axi_periph_BVALID <= M10_AXI_bvalid;
m10_couplers_to_microblaze_0_axi_periph_RDATA <= M10_AXI_rdata;
m10_couplers_to_microblaze_0_axi_periph_RRESP <= M10_AXI_rresp;
m10_couplers_to_microblaze_0_axi_periph_RVALID <= M10_AXI_rvalid;
m10_couplers_to_microblaze_0_axi_periph_WREADY <= M10_AXI_wready;
m11_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M11_AXI_arready(0);
m11_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M11_AXI_awready(0);
m11_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M11_AXI_bresp(1 downto 0);
m11_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M11_AXI_bvalid(0);
m11_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M11_AXI_rdata(31 downto 0);
m11_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M11_AXI_rresp(1 downto 0);
m11_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M11_AXI_rvalid(0);
m11_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M11_AXI_wready(0);
m12_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M12_AXI_arready(0);
m12_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M12_AXI_awready(0);
m12_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M12_AXI_bresp(1 downto 0);
m12_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M12_AXI_bvalid(0);
m12_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M12_AXI_rdata(31 downto 0);
m12_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M12_AXI_rresp(1 downto 0);
m12_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M12_AXI_rvalid(0);
m12_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M12_AXI_wready(0);
m13_couplers_to_microblaze_0_axi_periph_ARREADY <= M13_AXI_arready;
m13_couplers_to_microblaze_0_axi_periph_AWREADY <= M13_AXI_awready;
m13_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M13_AXI_bresp(1 downto 0);
m13_couplers_to_microblaze_0_axi_periph_BVALID <= M13_AXI_bvalid;
m13_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M13_AXI_rdata(31 downto 0);
m13_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M13_AXI_rresp(1 downto 0);
m13_couplers_to_microblaze_0_axi_periph_RVALID <= M13_AXI_rvalid;
m13_couplers_to_microblaze_0_axi_periph_WREADY <= M13_AXI_wready;
microblaze_0_axi_periph_ACLK_net <= ACLK;
microblaze_0_axi_periph_ARESETN_net <= ARESETN;
microblaze_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
microblaze_0_axi_periph_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
microblaze_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
microblaze_0_axi_periph_to_s00_couplers_AWVALID(0) <= S00_AXI_awvalid(0);
microblaze_0_axi_periph_to_s00_couplers_BREADY(0) <= S00_AXI_bready(0);
microblaze_0_axi_periph_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
microblaze_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
microblaze_0_axi_periph_to_s00_couplers_WVALID(0) <= S00_AXI_wvalid(0);
m00_couplers: entity work.m00_couplers_imp_1RZ0IW6
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m00_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m00_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_K87I2F
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN => M01_ARESETN_1,
M_AXI_araddr(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m01_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m01_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m01_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m01_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m01_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m01_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m01_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m01_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_QYRHL1
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN => M02_ARESETN_1,
M_AXI_araddr(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m02_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m02_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m02_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m02_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m02_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m02_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m02_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m02_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m02_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m02_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m02_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m02_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m02_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arready(0) => xbar_to_m02_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awready(0) => xbar_to_m02_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready(0) => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m02_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m02_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready(0) => xbar_to_m02_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid(0) => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_1LIFQL0
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN => M03_ARESETN_1,
M_AXI_araddr(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m03_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m03_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m03_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m03_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m03_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m03_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m03_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m03_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m03_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m03_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m03_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m03_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m03_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arready(0) => xbar_to_m03_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awready(0) => xbar_to_m03_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready(0) => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m03_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m03_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready(0) => xbar_to_m03_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid(0) => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_E2VWV5
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN => M04_ARESETN_1,
M_AXI_araddr(31 downto 0) => m04_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m04_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m04_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m04_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m04_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m04_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m04_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m04_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m04_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m04_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m04_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m04_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m04_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m04_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m04_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m04_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m04_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready(0) => xbar_to_m04_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready(0) => xbar_to_m04_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready(0) => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m04_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m04_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready(0) => xbar_to_m04_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid(0) => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_17ILSXC
port map (
M_ACLK => M05_ACLK_1,
M_ARESETN => M05_ARESETN_1,
M_AXI_araddr(31 downto 0) => m05_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m05_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m05_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m05_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m05_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m05_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m05_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m05_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m05_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m05_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m05_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m05_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m05_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m05_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m05_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m05_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m05_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m05_couplers_ARADDR(191 downto 160),
S_AXI_arready(0) => xbar_to_m05_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(31 downto 0) => xbar_to_m05_couplers_AWADDR(191 downto 160),
S_AXI_awready(0) => xbar_to_m05_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready(0) => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m05_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m05_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready(0) => xbar_to_m05_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m05_couplers_WSTRB(23 downto 20),
S_AXI_wvalid(0) => xbar_to_m05_couplers_WVALID(5)
);
m06_couplers: entity work.m06_couplers_imp_1E95TTU
port map (
M_ACLK => M06_ACLK_1,
M_ARESETN => M06_ARESETN_1,
M_AXI_araddr(31 downto 0) => m06_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m06_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m06_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m06_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m06_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m06_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m06_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m06_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m06_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m06_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m06_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m06_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m06_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m06_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m06_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m06_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m06_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m06_couplers_ARADDR(223 downto 192),
S_AXI_arready(0) => xbar_to_m06_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m06_couplers_ARVALID(6),
S_AXI_awaddr(31 downto 0) => xbar_to_m06_couplers_AWADDR(223 downto 192),
S_AXI_awready(0) => xbar_to_m06_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m06_couplers_AWVALID(6),
S_AXI_bready(0) => xbar_to_m06_couplers_BREADY(6),
S_AXI_bresp(1 downto 0) => xbar_to_m06_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m06_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m06_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m06_couplers_RREADY(6),
S_AXI_rresp(1 downto 0) => xbar_to_m06_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m06_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m06_couplers_WDATA(223 downto 192),
S_AXI_wready(0) => xbar_to_m06_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m06_couplers_WSTRB(27 downto 24),
S_AXI_wvalid(0) => xbar_to_m06_couplers_WVALID(6)
);
m07_couplers: entity work.m07_couplers_imp_7MB6C3
port map (
M_ACLK => M07_ACLK_1,
M_ARESETN => M07_ARESETN_1,
M_AXI_araddr(31 downto 0) => m07_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m07_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m07_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m07_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m07_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m07_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m07_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m07_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m07_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m07_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m07_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m07_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m07_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m07_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m07_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m07_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m07_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m07_couplers_ARADDR(255 downto 224),
S_AXI_arready(0) => xbar_to_m07_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m07_couplers_ARVALID(7),
S_AXI_awaddr(31 downto 0) => xbar_to_m07_couplers_AWADDR(255 downto 224),
S_AXI_awready(0) => xbar_to_m07_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m07_couplers_AWVALID(7),
S_AXI_bready(0) => xbar_to_m07_couplers_BREADY(7),
S_AXI_bresp(1 downto 0) => xbar_to_m07_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m07_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m07_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m07_couplers_RREADY(7),
S_AXI_rresp(1 downto 0) => xbar_to_m07_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m07_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m07_couplers_WDATA(255 downto 224),
S_AXI_wready(0) => xbar_to_m07_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m07_couplers_WSTRB(31 downto 28),
S_AXI_wvalid(0) => xbar_to_m07_couplers_WVALID(7)
);
m08_couplers: entity work.m08_couplers_imp_15IETBD
port map (
M_ACLK => M08_ACLK_1,
M_ARESETN => M08_ARESETN_1,
M_AXI_araddr(31 downto 0) => m08_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m08_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m08_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m08_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m08_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m08_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m08_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m08_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m08_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m08_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m08_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m08_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m08_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m08_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m08_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m08_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m08_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m08_couplers_ARADDR(287 downto 256),
S_AXI_arready(0) => xbar_to_m08_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m08_couplers_ARVALID(8),
S_AXI_awaddr(31 downto 0) => xbar_to_m08_couplers_AWADDR(287 downto 256),
S_AXI_awready(0) => xbar_to_m08_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m08_couplers_AWVALID(8),
S_AXI_bready(0) => xbar_to_m08_couplers_BREADY(8),
S_AXI_bresp(1 downto 0) => xbar_to_m08_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m08_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m08_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m08_couplers_RREADY(8),
S_AXI_rresp(1 downto 0) => xbar_to_m08_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m08_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m08_couplers_WDATA(287 downto 256),
S_AXI_wready(0) => xbar_to_m08_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m08_couplers_WSTRB(35 downto 32),
S_AXI_wvalid(0) => xbar_to_m08_couplers_WVALID(8)
);
m09_couplers: entity work.m09_couplers_imp_GMVR08
port map (
M_ACLK => M09_ACLK_1,
M_ARESETN => M09_ARESETN_1,
M_AXI_araddr(31 downto 0) => m09_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m09_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m09_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m09_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m09_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m09_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m09_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m09_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m09_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m09_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m09_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m09_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m09_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m09_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m09_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m09_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m09_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m09_couplers_ARADDR(319 downto 288),
S_AXI_arready(0) => xbar_to_m09_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m09_couplers_ARVALID(9),
S_AXI_awaddr(31 downto 0) => xbar_to_m09_couplers_AWADDR(319 downto 288),
S_AXI_awready(0) => xbar_to_m09_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m09_couplers_AWVALID(9),
S_AXI_bready(0) => xbar_to_m09_couplers_BREADY(9),
S_AXI_bresp(1 downto 0) => xbar_to_m09_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m09_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m09_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m09_couplers_RREADY(9),
S_AXI_rresp(1 downto 0) => xbar_to_m09_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m09_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m09_couplers_WDATA(319 downto 288),
S_AXI_wready(0) => xbar_to_m09_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m09_couplers_WSTRB(39 downto 36),
S_AXI_wvalid(0) => xbar_to_m09_couplers_WVALID(9)
);
m10_couplers: entity work.m10_couplers_imp_QYIUP1
port map (
M_ACLK => M10_ACLK_1,
M_ARESETN => M10_ARESETN_1,
M_AXI_araddr => m10_couplers_to_microblaze_0_axi_periph_ARADDR,
M_AXI_arprot => m10_couplers_to_microblaze_0_axi_periph_ARPROT,
M_AXI_arready => m10_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m10_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr => m10_couplers_to_microblaze_0_axi_periph_AWADDR,
M_AXI_awprot => m10_couplers_to_microblaze_0_axi_periph_AWPROT,
M_AXI_awready => m10_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m10_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m10_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp => m10_couplers_to_microblaze_0_axi_periph_BRESP,
M_AXI_bvalid => m10_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata => m10_couplers_to_microblaze_0_axi_periph_RDATA,
M_AXI_rready => m10_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp => m10_couplers_to_microblaze_0_axi_periph_RRESP,
M_AXI_rvalid => m10_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata => m10_couplers_to_microblaze_0_axi_periph_WDATA,
M_AXI_wready => m10_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb => m10_couplers_to_microblaze_0_axi_periph_WSTRB,
M_AXI_wvalid => m10_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr => xbar_to_m10_couplers_ARADDR(320),
S_AXI_arprot => xbar_to_m10_couplers_ARPROT(30),
S_AXI_arready => xbar_to_m10_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m10_couplers_ARVALID(10),
S_AXI_awaddr => xbar_to_m10_couplers_AWADDR(320),
S_AXI_awprot => xbar_to_m10_couplers_AWPROT(30),
S_AXI_awready => xbar_to_m10_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m10_couplers_AWVALID(10),
S_AXI_bready => xbar_to_m10_couplers_BREADY(10),
S_AXI_bresp => xbar_to_m10_couplers_BRESP,
S_AXI_bvalid => xbar_to_m10_couplers_BVALID,
S_AXI_rdata => xbar_to_m10_couplers_RDATA,
S_AXI_rready => xbar_to_m10_couplers_RREADY(10),
S_AXI_rresp => xbar_to_m10_couplers_RRESP,
S_AXI_rvalid => xbar_to_m10_couplers_RVALID,
S_AXI_wdata => xbar_to_m10_couplers_WDATA(320),
S_AXI_wready => xbar_to_m10_couplers_WREADY,
S_AXI_wstrb => xbar_to_m10_couplers_WSTRB(40),
S_AXI_wvalid => xbar_to_m10_couplers_WVALID(10)
);
m11_couplers: entity work.m11_couplers_imp_1LI8I9G
port map (
M_ACLK => M11_ACLK_1,
M_ARESETN => M11_ARESETN_1,
M_AXI_araddr(31 downto 0) => m11_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m11_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m11_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m11_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m11_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m11_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m11_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m11_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m11_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m11_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m11_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m11_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m11_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m11_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m11_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m11_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m11_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m11_couplers_ARADDR(383 downto 352),
S_AXI_arready(0) => xbar_to_m11_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m11_couplers_ARVALID(11),
S_AXI_awaddr(31 downto 0) => xbar_to_m11_couplers_AWADDR(383 downto 352),
S_AXI_awready(0) => xbar_to_m11_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m11_couplers_AWVALID(11),
S_AXI_bready(0) => xbar_to_m11_couplers_BREADY(11),
S_AXI_bresp(1 downto 0) => xbar_to_m11_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m11_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m11_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m11_couplers_RREADY(11),
S_AXI_rresp(1 downto 0) => xbar_to_m11_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m11_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m11_couplers_WDATA(383 downto 352),
S_AXI_wready(0) => xbar_to_m11_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m11_couplers_WSTRB(47 downto 44),
S_AXI_wvalid(0) => xbar_to_m11_couplers_WVALID(11)
);
m12_couplers: entity work.m12_couplers_imp_1RYRHQE
port map (
M_ACLK => M12_ACLK_1,
M_ARESETN => M12_ARESETN_1,
M_AXI_araddr(31 downto 0) => m12_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m12_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m12_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m12_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m12_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m12_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m12_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m12_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m12_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m12_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m12_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m12_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m12_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m12_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m12_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m12_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m12_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m12_couplers_ARADDR(415 downto 384),
S_AXI_arready(0) => xbar_to_m12_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m12_couplers_ARVALID(12),
S_AXI_awaddr(31 downto 0) => xbar_to_m12_couplers_AWADDR(415 downto 384),
S_AXI_awready(0) => xbar_to_m12_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m12_couplers_AWVALID(12),
S_AXI_bready(0) => xbar_to_m12_couplers_BREADY(12),
S_AXI_bresp(1 downto 0) => xbar_to_m12_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m12_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m12_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m12_couplers_RREADY(12),
S_AXI_rresp(1 downto 0) => xbar_to_m12_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m12_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m12_couplers_WDATA(415 downto 384),
S_AXI_wready(0) => xbar_to_m12_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m12_couplers_WSTRB(51 downto 48),
S_AXI_wvalid(0) => xbar_to_m12_couplers_WVALID(12)
);
m13_couplers: entity work.m13_couplers_imp_K7ZVH3
port map (
M_ACLK => M13_ACLK_1,
M_ARESETN => M13_ARESETN_1,
M_AXI_araddr(10 downto 0) => m13_couplers_to_microblaze_0_axi_periph_ARADDR(10 downto 0),
M_AXI_arready => m13_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m13_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(10 downto 0) => m13_couplers_to_microblaze_0_axi_periph_AWADDR(10 downto 0),
M_AXI_awready => m13_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m13_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m13_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m13_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m13_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m13_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m13_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m13_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m13_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m13_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m13_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m13_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m13_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m13_couplers_ARADDR(447 downto 416),
S_AXI_arprot(2 downto 0) => xbar_to_m13_couplers_ARPROT(41 downto 39),
S_AXI_arready => xbar_to_m13_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m13_couplers_ARVALID(13),
S_AXI_awaddr(31 downto 0) => xbar_to_m13_couplers_AWADDR(447 downto 416),
S_AXI_awprot(2 downto 0) => xbar_to_m13_couplers_AWPROT(41 downto 39),
S_AXI_awready => xbar_to_m13_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m13_couplers_AWVALID(13),
S_AXI_bready => xbar_to_m13_couplers_BREADY(13),
S_AXI_bresp(1 downto 0) => xbar_to_m13_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m13_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m13_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m13_couplers_RREADY(13),
S_AXI_rresp(1 downto 0) => xbar_to_m13_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m13_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m13_couplers_WDATA(447 downto 416),
S_AXI_wready => xbar_to_m13_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m13_couplers_WSTRB(55 downto 52),
S_AXI_wvalid => xbar_to_m13_couplers_WVALID(13)
);
s00_couplers: entity work.s00_couplers_imp_1LZPV07
port map (
M_ACLK => microblaze_0_axi_periph_ACLK_net,
M_ARESETN => microblaze_0_axi_periph_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready(0) => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
M_AXI_bready(0) => s00_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready(0) => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s00_couplers_to_xbar_WVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => microblaze_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => microblaze_0_axi_periph_to_s00_couplers_ARREADY(0),
S_AXI_arvalid(0) => microblaze_0_axi_periph_to_s00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => microblaze_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => microblaze_0_axi_periph_to_s00_couplers_AWREADY(0),
S_AXI_awvalid(0) => microblaze_0_axi_periph_to_s00_couplers_AWVALID(0),
S_AXI_bready(0) => microblaze_0_axi_periph_to_s00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => microblaze_0_axi_periph_to_s00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => microblaze_0_axi_periph_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => microblaze_0_axi_periph_to_s00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => microblaze_0_axi_periph_to_s00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => microblaze_0_axi_periph_to_s00_couplers_WVALID(0)
);
xbar: component system_xbar_1
port map (
aclk => microblaze_0_axi_periph_ACLK_net,
aresetn => microblaze_0_axi_periph_ARESETN_net,
m_axi_araddr(447 downto 416) => xbar_to_m13_couplers_ARADDR(447 downto 416),
m_axi_araddr(415 downto 384) => xbar_to_m12_couplers_ARADDR(415 downto 384),
m_axi_araddr(383 downto 352) => xbar_to_m11_couplers_ARADDR(383 downto 352),
m_axi_araddr(351 downto 320) => xbar_to_m10_couplers_ARADDR(351 downto 320),
m_axi_araddr(319 downto 288) => xbar_to_m09_couplers_ARADDR(319 downto 288),
m_axi_araddr(287 downto 256) => xbar_to_m08_couplers_ARADDR(287 downto 256),
m_axi_araddr(255 downto 224) => xbar_to_m07_couplers_ARADDR(255 downto 224),
m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192),
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(41 downto 39) => xbar_to_m13_couplers_ARPROT(41 downto 39),
m_axi_arprot(38 downto 33) => NLW_xbar_m_axi_arprot_UNCONNECTED(38 downto 33),
m_axi_arprot(32 downto 30) => xbar_to_m10_couplers_ARPROT(32 downto 30),
m_axi_arprot(29 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(29 downto 0),
m_axi_arready(13) => xbar_to_m13_couplers_ARREADY,
m_axi_arready(12) => xbar_to_m12_couplers_ARREADY(0),
m_axi_arready(11) => xbar_to_m11_couplers_ARREADY(0),
m_axi_arready(10) => xbar_to_m10_couplers_ARREADY,
m_axi_arready(9) => xbar_to_m09_couplers_ARREADY(0),
m_axi_arready(8) => xbar_to_m08_couplers_ARREADY(0),
m_axi_arready(7) => xbar_to_m07_couplers_ARREADY(0),
m_axi_arready(6) => xbar_to_m06_couplers_ARREADY(0),
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY(0),
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY(0),
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY(0),
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY(0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(13) => xbar_to_m13_couplers_ARVALID(13),
m_axi_arvalid(12) => xbar_to_m12_couplers_ARVALID(12),
m_axi_arvalid(11) => xbar_to_m11_couplers_ARVALID(11),
m_axi_arvalid(10) => xbar_to_m10_couplers_ARVALID(10),
m_axi_arvalid(9) => xbar_to_m09_couplers_ARVALID(9),
m_axi_arvalid(8) => xbar_to_m08_couplers_ARVALID(8),
m_axi_arvalid(7) => xbar_to_m07_couplers_ARVALID(7),
m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(447 downto 416) => xbar_to_m13_couplers_AWADDR(447 downto 416),
m_axi_awaddr(415 downto 384) => xbar_to_m12_couplers_AWADDR(415 downto 384),
m_axi_awaddr(383 downto 352) => xbar_to_m11_couplers_AWADDR(383 downto 352),
m_axi_awaddr(351 downto 320) => xbar_to_m10_couplers_AWADDR(351 downto 320),
m_axi_awaddr(319 downto 288) => xbar_to_m09_couplers_AWADDR(319 downto 288),
m_axi_awaddr(287 downto 256) => xbar_to_m08_couplers_AWADDR(287 downto 256),
m_axi_awaddr(255 downto 224) => xbar_to_m07_couplers_AWADDR(255 downto 224),
m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(41 downto 39) => xbar_to_m13_couplers_AWPROT(41 downto 39),
m_axi_awprot(38 downto 33) => NLW_xbar_m_axi_awprot_UNCONNECTED(38 downto 33),
m_axi_awprot(32 downto 30) => xbar_to_m10_couplers_AWPROT(32 downto 30),
m_axi_awprot(29 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(29 downto 0),
m_axi_awready(13) => xbar_to_m13_couplers_AWREADY,
m_axi_awready(12) => xbar_to_m12_couplers_AWREADY(0),
m_axi_awready(11) => xbar_to_m11_couplers_AWREADY(0),
m_axi_awready(10) => xbar_to_m10_couplers_AWREADY,
m_axi_awready(9) => xbar_to_m09_couplers_AWREADY(0),
m_axi_awready(8) => xbar_to_m08_couplers_AWREADY(0),
m_axi_awready(7) => xbar_to_m07_couplers_AWREADY(0),
m_axi_awready(6) => xbar_to_m06_couplers_AWREADY(0),
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY(0),
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY(0),
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY(0),
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY(0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(13) => xbar_to_m13_couplers_AWVALID(13),
m_axi_awvalid(12) => xbar_to_m12_couplers_AWVALID(12),
m_axi_awvalid(11) => xbar_to_m11_couplers_AWVALID(11),
m_axi_awvalid(10) => xbar_to_m10_couplers_AWVALID(10),
m_axi_awvalid(9) => xbar_to_m09_couplers_AWVALID(9),
m_axi_awvalid(8) => xbar_to_m08_couplers_AWVALID(8),
m_axi_awvalid(7) => xbar_to_m07_couplers_AWVALID(7),
m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(13) => xbar_to_m13_couplers_BREADY(13),
m_axi_bready(12) => xbar_to_m12_couplers_BREADY(12),
m_axi_bready(11) => xbar_to_m11_couplers_BREADY(11),
m_axi_bready(10) => xbar_to_m10_couplers_BREADY(10),
m_axi_bready(9) => xbar_to_m09_couplers_BREADY(9),
m_axi_bready(8) => xbar_to_m08_couplers_BREADY(8),
m_axi_bready(7) => xbar_to_m07_couplers_BREADY(7),
m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(27 downto 26) => xbar_to_m13_couplers_BRESP(1 downto 0),
m_axi_bresp(25 downto 24) => xbar_to_m12_couplers_BRESP(1 downto 0),
m_axi_bresp(23 downto 22) => xbar_to_m11_couplers_BRESP(1 downto 0),
m_axi_bresp(21) => xbar_to_m10_couplers_BRESP,
m_axi_bresp(20) => xbar_to_m10_couplers_BRESP,
m_axi_bresp(19 downto 18) => xbar_to_m09_couplers_BRESP(1 downto 0),
m_axi_bresp(17 downto 16) => xbar_to_m08_couplers_BRESP(1 downto 0),
m_axi_bresp(15 downto 14) => xbar_to_m07_couplers_BRESP(1 downto 0),
m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(13) => xbar_to_m13_couplers_BVALID,
m_axi_bvalid(12) => xbar_to_m12_couplers_BVALID(0),
m_axi_bvalid(11) => xbar_to_m11_couplers_BVALID(0),
m_axi_bvalid(10) => xbar_to_m10_couplers_BVALID,
m_axi_bvalid(9) => xbar_to_m09_couplers_BVALID(0),
m_axi_bvalid(8) => xbar_to_m08_couplers_BVALID(0),
m_axi_bvalid(7) => xbar_to_m07_couplers_BVALID(0),
m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID(0),
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID(0),
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID(0),
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID(0),
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID(0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(447 downto 416) => xbar_to_m13_couplers_RDATA(31 downto 0),
m_axi_rdata(415 downto 384) => xbar_to_m12_couplers_RDATA(31 downto 0),
m_axi_rdata(383 downto 352) => xbar_to_m11_couplers_RDATA(31 downto 0),
m_axi_rdata(351) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(350) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(349) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(348) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(347) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(346) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(345) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(344) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(343) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(342) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(341) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(340) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(339) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(338) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(337) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(336) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(335) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(334) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(333) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(332) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(331) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(330) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(329) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(328) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(327) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(326) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(325) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(324) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(323) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(322) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(321) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(320) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(319 downto 288) => xbar_to_m09_couplers_RDATA(31 downto 0),
m_axi_rdata(287 downto 256) => xbar_to_m08_couplers_RDATA(31 downto 0),
m_axi_rdata(255 downto 224) => xbar_to_m07_couplers_RDATA(31 downto 0),
m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(13) => xbar_to_m13_couplers_RREADY(13),
m_axi_rready(12) => xbar_to_m12_couplers_RREADY(12),
m_axi_rready(11) => xbar_to_m11_couplers_RREADY(11),
m_axi_rready(10) => xbar_to_m10_couplers_RREADY(10),
m_axi_rready(9) => xbar_to_m09_couplers_RREADY(9),
m_axi_rready(8) => xbar_to_m08_couplers_RREADY(8),
m_axi_rready(7) => xbar_to_m07_couplers_RREADY(7),
m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(27 downto 26) => xbar_to_m13_couplers_RRESP(1 downto 0),
m_axi_rresp(25 downto 24) => xbar_to_m12_couplers_RRESP(1 downto 0),
m_axi_rresp(23 downto 22) => xbar_to_m11_couplers_RRESP(1 downto 0),
m_axi_rresp(21) => xbar_to_m10_couplers_RRESP,
m_axi_rresp(20) => xbar_to_m10_couplers_RRESP,
m_axi_rresp(19 downto 18) => xbar_to_m09_couplers_RRESP(1 downto 0),
m_axi_rresp(17 downto 16) => xbar_to_m08_couplers_RRESP(1 downto 0),
m_axi_rresp(15 downto 14) => xbar_to_m07_couplers_RRESP(1 downto 0),
m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(13) => xbar_to_m13_couplers_RVALID,
m_axi_rvalid(12) => xbar_to_m12_couplers_RVALID(0),
m_axi_rvalid(11) => xbar_to_m11_couplers_RVALID(0),
m_axi_rvalid(10) => xbar_to_m10_couplers_RVALID,
m_axi_rvalid(9) => xbar_to_m09_couplers_RVALID(0),
m_axi_rvalid(8) => xbar_to_m08_couplers_RVALID(0),
m_axi_rvalid(7) => xbar_to_m07_couplers_RVALID(0),
m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID(0),
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID(0),
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID(0),
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID(0),
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID(0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(447 downto 416) => xbar_to_m13_couplers_WDATA(447 downto 416),
m_axi_wdata(415 downto 384) => xbar_to_m12_couplers_WDATA(415 downto 384),
m_axi_wdata(383 downto 352) => xbar_to_m11_couplers_WDATA(383 downto 352),
m_axi_wdata(351 downto 320) => xbar_to_m10_couplers_WDATA(351 downto 320),
m_axi_wdata(319 downto 288) => xbar_to_m09_couplers_WDATA(319 downto 288),
m_axi_wdata(287 downto 256) => xbar_to_m08_couplers_WDATA(287 downto 256),
m_axi_wdata(255 downto 224) => xbar_to_m07_couplers_WDATA(255 downto 224),
m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(13) => xbar_to_m13_couplers_WREADY,
m_axi_wready(12) => xbar_to_m12_couplers_WREADY(0),
m_axi_wready(11) => xbar_to_m11_couplers_WREADY(0),
m_axi_wready(10) => xbar_to_m10_couplers_WREADY,
m_axi_wready(9) => xbar_to_m09_couplers_WREADY(0),
m_axi_wready(8) => xbar_to_m08_couplers_WREADY(0),
m_axi_wready(7) => xbar_to_m07_couplers_WREADY(0),
m_axi_wready(6) => xbar_to_m06_couplers_WREADY(0),
m_axi_wready(5) => xbar_to_m05_couplers_WREADY(0),
m_axi_wready(4) => xbar_to_m04_couplers_WREADY(0),
m_axi_wready(3) => xbar_to_m03_couplers_WREADY(0),
m_axi_wready(2) => xbar_to_m02_couplers_WREADY(0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(55 downto 52) => xbar_to_m13_couplers_WSTRB(55 downto 52),
m_axi_wstrb(51 downto 48) => xbar_to_m12_couplers_WSTRB(51 downto 48),
m_axi_wstrb(47 downto 44) => xbar_to_m11_couplers_WSTRB(47 downto 44),
m_axi_wstrb(43 downto 40) => xbar_to_m10_couplers_WSTRB(43 downto 40),
m_axi_wstrb(39 downto 36) => xbar_to_m09_couplers_WSTRB(39 downto 36),
m_axi_wstrb(35 downto 32) => xbar_to_m08_couplers_WSTRB(35 downto 32),
m_axi_wstrb(31 downto 28) => xbar_to_m07_couplers_WSTRB(31 downto 28),
m_axi_wstrb(27 downto 24) => xbar_to_m06_couplers_WSTRB(27 downto 24),
m_axi_wstrb(23 downto 20) => xbar_to_m05_couplers_WSTRB(23 downto 20),
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(13) => xbar_to_m13_couplers_WVALID(13),
m_axi_wvalid(12) => xbar_to_m12_couplers_WVALID(12),
m_axi_wvalid(11) => xbar_to_m11_couplers_WVALID(11),
m_axi_wvalid(10) => xbar_to_m10_couplers_WVALID(10),
m_axi_wvalid(9) => xbar_to_m09_couplers_WVALID(9),
m_axi_wvalid(8) => xbar_to_m08_couplers_WVALID(8),
m_axi_wvalid(7) => xbar_to_m07_couplers_WVALID(7),
m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
s_axi_bready(0) => s00_couplers_to_xbar_BREADY(0),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
DDR3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR3_cas_n : out STD_LOGIC;
DDR3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ras_n : out STD_LOGIC;
DDR3_reset_n : out STD_LOGIC;
DDR3_we_n : out STD_LOGIC;
Vaux0_v_n : in STD_LOGIC;
Vaux0_v_p : in STD_LOGIC;
Vaux10_v_n : in STD_LOGIC;
Vaux10_v_p : in STD_LOGIC;
Vaux12_v_n : in STD_LOGIC;
Vaux12_v_p : in STD_LOGIC;
Vaux13_v_n : in STD_LOGIC;
Vaux13_v_p : in STD_LOGIC;
Vaux14_v_n : in STD_LOGIC;
Vaux14_v_p : in STD_LOGIC;
Vaux15_v_n : in STD_LOGIC;
Vaux15_v_p : in STD_LOGIC;
Vaux1_v_n : in STD_LOGIC;
Vaux1_v_p : in STD_LOGIC;
Vaux2_v_n : in STD_LOGIC;
Vaux2_v_p : in STD_LOGIC;
Vaux4_v_n : in STD_LOGIC;
Vaux4_v_p : in STD_LOGIC;
Vaux5_v_n : in STD_LOGIC;
Vaux5_v_p : in STD_LOGIC;
Vaux6_v_n : in STD_LOGIC;
Vaux6_v_p : in STD_LOGIC;
Vaux7_v_n : in STD_LOGIC;
Vaux7_v_p : in STD_LOGIC;
Vaux9_v_n : in STD_LOGIC;
Vaux9_v_p : in STD_LOGIC;
Vp_Vn_v_n : in STD_LOGIC;
Vp_Vn_v_p : in STD_LOGIC;
dip_switches_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_i : in STD_LOGIC;
eth_mdio_mdc_mdio_o : out STD_LOGIC;
eth_mdio_mdc_mdio_t : out STD_LOGIC;
eth_mii_col : in STD_LOGIC;
eth_mii_crs : in STD_LOGIC;
eth_mii_rst_n : out STD_LOGIC;
eth_mii_rx_clk : in STD_LOGIC;
eth_mii_rx_dv : in STD_LOGIC;
eth_mii_rx_er : in STD_LOGIC;
eth_mii_rxd : in STD_LOGIC_VECTOR ( 3 downto 0 );
eth_mii_tx_clk : in STD_LOGIC;
eth_mii_tx_en : out STD_LOGIC;
eth_mii_txd : out STD_LOGIC_VECTOR ( 3 downto 0 );
eth_ref_clk : out STD_LOGIC;
i2c_pullups_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
i2c_pullups_tri_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
i2c_pullups_tri_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
i2c_scl_i : in STD_LOGIC;
i2c_scl_o : out STD_LOGIC;
i2c_scl_t : out STD_LOGIC;
i2c_sda_i : in STD_LOGIC;
i2c_sda_o : out STD_LOGIC;
i2c_sda_t : out STD_LOGIC;
led_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
led_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
push_buttons_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
qspi_flash_io0_i : in STD_LOGIC;
qspi_flash_io0_o : out STD_LOGIC;
qspi_flash_io0_t : out STD_LOGIC;
qspi_flash_io1_i : in STD_LOGIC;
qspi_flash_io1_o : out STD_LOGIC;
qspi_flash_io1_t : out STD_LOGIC;
qspi_flash_io2_i : in STD_LOGIC;
qspi_flash_io2_o : out STD_LOGIC;
qspi_flash_io2_t : out STD_LOGIC;
qspi_flash_io3_i : in STD_LOGIC;
qspi_flash_io3_o : out STD_LOGIC;
qspi_flash_io3_t : out STD_LOGIC;
qspi_flash_sck_i : in STD_LOGIC;
qspi_flash_sck_o : out STD_LOGIC;
qspi_flash_sck_t : out STD_LOGIC;
qspi_flash_ss_i : in STD_LOGIC;
qspi_flash_ss_o : out STD_LOGIC;
qspi_flash_ss_t : out STD_LOGIC;
reset : in STD_LOGIC;
rgb_led_tri_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
rgb_led_tri_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
rgb_led_tri_t : out STD_LOGIC_VECTOR ( 11 downto 0 );
shield_dp0_dp19_tri_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp0_dp19_tri_o : out STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp0_dp19_tri_t : out STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp26_dp41_tri_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
shield_dp26_dp41_tri_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
shield_dp26_dp41_tri_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
spi_io0_i : in STD_LOGIC;
spi_io0_o : out STD_LOGIC;
spi_io0_t : out STD_LOGIC;
spi_io1_i : in STD_LOGIC;
spi_io1_o : out STD_LOGIC;
spi_io1_t : out STD_LOGIC;
spi_sck_i : in STD_LOGIC;
spi_sck_o : out STD_LOGIC;
spi_sck_t : out STD_LOGIC;
spi_ss_i : in STD_LOGIC;
spi_ss_o : out STD_LOGIC;
spi_ss_t : out STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=52,numReposBlks=31,numNonXlnxBlks=0,numHierBlks=21,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_microblaze_0_xlconcat_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
In2 : in STD_LOGIC_VECTOR ( 0 to 0 );
In3 : in STD_LOGIC_VECTOR ( 0 to 0 );
In4 : in STD_LOGIC_VECTOR ( 0 to 0 );
In5 : in STD_LOGIC_VECTOR ( 0 to 0 );
In6 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
end component system_microblaze_0_xlconcat_0;
component system_axi_ethernetlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
phy_rx_clk : in STD_LOGIC;
phy_crs : in STD_LOGIC;
phy_dv : in STD_LOGIC;
phy_rx_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
phy_col : in STD_LOGIC;
phy_rx_er : in STD_LOGIC;
phy_rst_n : out STD_LOGIC;
phy_tx_en : out STD_LOGIC;
phy_tx_data : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_mdio_i : in STD_LOGIC;
phy_mdio_o : out STD_LOGIC;
phy_mdio_t : out STD_LOGIC;
phy_mdc : out STD_LOGIC
);
end component system_axi_ethernetlite_0_0;
component system_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
end component system_axi_gpio_0_0;
component system_axi_gpio_1_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_axi_gpio_1_0;
component system_axi_gpio_led_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end component system_axi_gpio_led_0;
component system_axi_gpio_pullup_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component system_axi_gpio_pullup_0;
component system_axi_gpio_sw_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component system_axi_gpio_sw_0;
component system_axi_iic_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
iic2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
sda_t : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
scl_t : out STD_LOGIC;
gpo : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_axi_iic_0_0;
component system_axi_quad_spi_flash_0 is
port (
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
io2_i : in STD_LOGIC;
io2_o : out STD_LOGIC;
io2_t : out STD_LOGIC;
io3_i : in STD_LOGIC;
io3_o : out STD_LOGIC;
io3_t : out STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
end component system_axi_quad_spi_flash_0;
component system_axi_quad_spi_shield_0 is
port (
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
end component system_axi_quad_spi_shield_0;
component system_axi_timer_0_0 is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
end component system_axi_timer_0_0;
component system_axi_uartlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
interrupt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
rx : in STD_LOGIC;
tx : out STD_LOGIC
);
end component system_axi_uartlite_0_0;
component system_clk_wiz_1_0 is
port (
resetn : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_1_0;
component system_mdm_1_0 is
port (
Debug_SYS_Rst : out STD_LOGIC;
Dbg_Clk_0 : out STD_LOGIC;
Dbg_TDI_0 : out STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
Dbg_Update_0 : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Disable_0 : out STD_LOGIC
);
end component system_mdm_1_0;
component system_microblaze_0_0 is
port (
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Interrupt : in STD_LOGIC;
Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
IFetch : out STD_LOGIC;
I_AS : out STD_LOGIC;
IReady : in STD_LOGIC;
IWAIT : in STD_LOGIC;
ICE : in STD_LOGIC;
IUE : in STD_LOGIC;
Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
D_AS : out STD_LOGIC;
Read_Strobe : out STD_LOGIC;
Write_Strobe : out STD_LOGIC;
DReady : in STD_LOGIC;
DWait : in STD_LOGIC;
DCE : in STD_LOGIC;
DUE : in STD_LOGIC;
Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_AWVALID : out STD_LOGIC;
M_AXI_DP_AWREADY : in STD_LOGIC;
M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DP_WVALID : out STD_LOGIC;
M_AXI_DP_WREADY : in STD_LOGIC;
M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_BVALID : in STD_LOGIC;
M_AXI_DP_BREADY : out STD_LOGIC;
M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_ARVALID : out STD_LOGIC;
M_AXI_DP_ARREADY : in STD_LOGIC;
M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_RVALID : in STD_LOGIC;
M_AXI_DP_RREADY : out STD_LOGIC;
Dbg_Clk : in STD_LOGIC;
Dbg_TDI : in STD_LOGIC;
Dbg_TDO : out STD_LOGIC;
Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Shift : in STD_LOGIC;
Dbg_Capture : in STD_LOGIC;
Dbg_Update : in STD_LOGIC;
Debug_Rst : in STD_LOGIC;
Dbg_Disable : in STD_LOGIC;
M_AXI_IC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_IC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_AWLOCK : out STD_LOGIC;
M_AXI_IC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_AWVALID : out STD_LOGIC;
M_AXI_IC_AWREADY : in STD_LOGIC;
M_AXI_IC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_WLAST : out STD_LOGIC;
M_AXI_IC_WVALID : out STD_LOGIC;
M_AXI_IC_WREADY : in STD_LOGIC;
M_AXI_IC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_BVALID : in STD_LOGIC;
M_AXI_IC_BREADY : out STD_LOGIC;
M_AXI_IC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_IC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_ARLOCK : out STD_LOGIC;
M_AXI_IC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_ARVALID : out STD_LOGIC;
M_AXI_IC_ARREADY : in STD_LOGIC;
M_AXI_IC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_RLAST : in STD_LOGIC;
M_AXI_IC_RVALID : in STD_LOGIC;
M_AXI_IC_RREADY : out STD_LOGIC;
M_AXI_DC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_DC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_AWLOCK : out STD_LOGIC;
M_AXI_DC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_AWVALID : out STD_LOGIC;
M_AXI_DC_AWREADY : in STD_LOGIC;
M_AXI_DC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_WLAST : out STD_LOGIC;
M_AXI_DC_WVALID : out STD_LOGIC;
M_AXI_DC_WREADY : in STD_LOGIC;
M_AXI_DC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_BVALID : in STD_LOGIC;
M_AXI_DC_BREADY : out STD_LOGIC;
M_AXI_DC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_DC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_ARLOCK : out STD_LOGIC;
M_AXI_DC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_ARVALID : out STD_LOGIC;
M_AXI_DC_ARREADY : in STD_LOGIC;
M_AXI_DC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_RLAST : in STD_LOGIC;
M_AXI_DC_RVALID : in STD_LOGIC;
M_AXI_DC_RREADY : out STD_LOGIC
);
end component system_microblaze_0_0;
component system_microblaze_0_axi_intc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 6 downto 0 );
processor_clk : in STD_LOGIC;
processor_rst : in STD_LOGIC;
irq : out STD_LOGIC;
processor_ack : in STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_microblaze_0_axi_intc_0;
component system_mig_7series_0_0 is
port (
device_temp_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
sys_rst : in STD_LOGIC;
clk_ref_i : in STD_LOGIC;
ddr3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
ddr3_ras_n : out STD_LOGIC;
ddr3_cas_n : out STD_LOGIC;
ddr3_we_n : out STD_LOGIC;
ddr3_reset_n : out STD_LOGIC;
ddr3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
ui_clk_sync_rst : out STD_LOGIC;
ui_clk : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
mmcm_locked : out STD_LOGIC;
sys_clk_i : in STD_LOGIC;
init_calib_complete : out STD_LOGIC;
aresetn : in STD_LOGIC
);
end component system_mig_7series_0_0;
component system_rst_clk_wiz_1_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_rst_clk_wiz_1_100M_0;
component system_rst_mig_7series_0_83M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_rst_mig_7series_0_83M_0;
component system_xadc_wiz_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
vp_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
vauxp0 : in STD_LOGIC;
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC;
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC;
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC;
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC;
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC;
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC;
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC;
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC;
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC;
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC;
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC;
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC;
vauxn15 : in STD_LOGIC;
user_temp_alarm_out : out STD_LOGIC;
vccint_alarm_out : out STD_LOGIC;
vccaux_alarm_out : out STD_LOGIC;
channel_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
eoc_out : out STD_LOGIC;
alarm_out : out STD_LOGIC;
eos_out : out STD_LOGIC;
busy_out : out STD_LOGIC;
temp_out : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end component system_xadc_wiz_0_0;
signal Vaux0_1_V_N : STD_LOGIC;
signal Vaux0_1_V_P : STD_LOGIC;
signal Vaux10_1_V_N : STD_LOGIC;
signal Vaux10_1_V_P : STD_LOGIC;
signal Vaux12_1_V_N : STD_LOGIC;
signal Vaux12_1_V_P : STD_LOGIC;
signal Vaux13_1_V_N : STD_LOGIC;
signal Vaux13_1_V_P : STD_LOGIC;
signal Vaux14_1_V_N : STD_LOGIC;
signal Vaux14_1_V_P : STD_LOGIC;
signal Vaux15_1_V_N : STD_LOGIC;
signal Vaux15_1_V_P : STD_LOGIC;
signal Vaux1_1_V_N : STD_LOGIC;
signal Vaux1_1_V_P : STD_LOGIC;
signal Vaux2_1_V_N : STD_LOGIC;
signal Vaux2_1_V_P : STD_LOGIC;
signal Vaux4_1_V_N : STD_LOGIC;
signal Vaux4_1_V_P : STD_LOGIC;
signal Vaux5_1_V_N : STD_LOGIC;
signal Vaux5_1_V_P : STD_LOGIC;
signal Vaux6_1_V_N : STD_LOGIC;
signal Vaux6_1_V_P : STD_LOGIC;
signal Vaux7_1_V_N : STD_LOGIC;
signal Vaux7_1_V_P : STD_LOGIC;
signal Vaux9_1_V_N : STD_LOGIC;
signal Vaux9_1_V_P : STD_LOGIC;
signal Vp_Vn_1_V_N : STD_LOGIC;
signal Vp_Vn_1_V_P : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDC : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDIO_I : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDIO_O : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDIO_T : STD_LOGIC;
signal axi_ethernetlite_0_MII_COL : STD_LOGIC;
signal axi_ethernetlite_0_MII_CRS : STD_LOGIC;
signal axi_ethernetlite_0_MII_RST_N : STD_LOGIC;
signal axi_ethernetlite_0_MII_RXD : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_ethernetlite_0_MII_RX_CLK : STD_LOGIC;
signal axi_ethernetlite_0_MII_RX_DV : STD_LOGIC;
signal axi_ethernetlite_0_MII_RX_ER : STD_LOGIC;
signal axi_ethernetlite_0_MII_TXD : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_ethernetlite_0_MII_TX_CLK : STD_LOGIC;
signal axi_ethernetlite_0_MII_TX_EN : STD_LOGIC;
signal axi_ethernetlite_0_ip2intc_irpt : STD_LOGIC;
signal axi_gpio_0_GPIO2_TRI_I : STD_LOGIC_VECTOR ( 19 downto 0 );
signal axi_gpio_0_GPIO2_TRI_O : STD_LOGIC_VECTOR ( 19 downto 0 );
signal axi_gpio_0_GPIO2_TRI_T : STD_LOGIC_VECTOR ( 19 downto 0 );
signal axi_gpio_1_GPIO1_TRI_I : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_gpio_1_GPIO1_TRI_O : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_gpio_1_GPIO1_TRI_T : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_gpio_2_GPIO2_TRI_I : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_gpio_2_GPIO2_TRI_O : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_gpio_2_GPIO2_TRI_T : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_gpio_2_GPIO_TRI_I : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_2_GPIO_TRI_O : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_2_GPIO_TRI_T : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_pullup_GPIO_TRI_I : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_gpio_pullup_GPIO_TRI_O : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_gpio_pullup_GPIO_TRI_T : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_gpio_sw_GPIO2_TRI_I : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_sw_GPIO_TRI_I : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_sw_ip2intc_irpt : STD_LOGIC;
signal axi_iic_0_IIC_SCL_I : STD_LOGIC;
signal axi_iic_0_IIC_SCL_O : STD_LOGIC;
signal axi_iic_0_IIC_SCL_T : STD_LOGIC;
signal axi_iic_0_IIC_SDA_I : STD_LOGIC;
signal axi_iic_0_IIC_SDA_O : STD_LOGIC;
signal axi_iic_0_IIC_SDA_T : STD_LOGIC;
signal axi_iic_0_iic2intc_irpt : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 27 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 27 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_IO0_I : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_IO0_O : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_IO0_T : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_IO1_I : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_IO1_O : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_IO1_T : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_SCK_I : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_SCK_O : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_SCK_T : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_SS_I : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_SS_O : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_quad_spi_0_SPI_0_SS_T : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO0_I : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO0_O : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO0_T : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO1_I : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO1_O : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO1_T : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO2_I : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO2_O : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO2_T : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO3_I : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO3_O : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO3_T : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_SCK_I : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_SCK_O : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_SCK_T : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_SS_I : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_SS_O : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_quad_spi_1_SPI_0_SS_T : STD_LOGIC;
signal axi_quad_spi_flash_ip2intc_irpt : STD_LOGIC;
signal axi_quad_spi_shield_ip2intc_irpt : STD_LOGIC;
signal axi_timer_0_interrupt : STD_LOGIC;
signal axi_uartlite_0_UART_RxD : STD_LOGIC;
signal axi_uartlite_0_UART_TxD : STD_LOGIC;
signal clk_wiz_1_clk_out2 : STD_LOGIC;
signal clk_wiz_1_clk_out3 : STD_LOGIC;
signal clk_wiz_1_clk_out4 : STD_LOGIC;
signal clk_wiz_1_locked : STD_LOGIC;
signal mdm_1_debug_sys_rst : STD_LOGIC;
signal microblaze_0_Clk : STD_LOGIC;
signal microblaze_0_M_AXI_DC_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_DC_ARLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_DC_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_ARREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_ARVALID : STD_LOGIC;
signal microblaze_0_M_AXI_DC_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_DC_AWLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_DC_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_AWREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_AWVALID : STD_LOGIC;
signal microblaze_0_M_AXI_DC_BREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_BVALID : STD_LOGIC;
signal microblaze_0_M_AXI_DC_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_RLAST : STD_LOGIC;
signal microblaze_0_M_AXI_DC_RREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_RVALID : STD_LOGIC;
signal microblaze_0_M_AXI_DC_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_WLAST : STD_LOGIC;
signal microblaze_0_M_AXI_DC_WREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_WVALID : STD_LOGIC;
signal microblaze_0_M_AXI_IC_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_IC_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_IC_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_IC_ARLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_IC_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_IC_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_ARREADY : STD_LOGIC;
signal microblaze_0_M_AXI_IC_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_IC_ARVALID : STD_LOGIC;
signal microblaze_0_M_AXI_IC_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_IC_RLAST : STD_LOGIC;
signal microblaze_0_M_AXI_IC_RREADY : STD_LOGIC;
signal microblaze_0_M_AXI_IC_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_IC_RVALID : STD_LOGIC;
signal microblaze_0_axi_dp_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_dp_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_ARVALID : STD_LOGIC;
signal microblaze_0_axi_dp_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_dp_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_AWVALID : STD_LOGIC;
signal microblaze_0_axi_dp_BREADY : STD_LOGIC;
signal microblaze_0_axi_dp_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_dp_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_RREADY : STD_LOGIC;
signal microblaze_0_axi_dp_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_dp_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_dp_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M02_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M03_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M04_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M05_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M06_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M06_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M06_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M06_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M06_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M07_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M07_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M07_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M07_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M07_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M07_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M07_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M07_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M07_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M07_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M08_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M08_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M08_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M08_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M08_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M08_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M08_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M08_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M08_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M08_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M09_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M09_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M09_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M09_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M09_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M09_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M09_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M09_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M09_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M09_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M11_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M11_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M11_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M11_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M11_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M11_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M11_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M11_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M11_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M11_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M12_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M12_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M12_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M12_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M12_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M12_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M12_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M12_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M12_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M12_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M13_AXI_ARADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_AWADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_WVALID : STD_LOGIC;
signal microblaze_0_debug_CAPTURE : STD_LOGIC;
signal microblaze_0_debug_CLK : STD_LOGIC;
signal microblaze_0_debug_DISABLE : STD_LOGIC;
signal microblaze_0_debug_REG_EN : STD_LOGIC_VECTOR ( 0 to 7 );
signal microblaze_0_debug_RST : STD_LOGIC;
signal microblaze_0_debug_SHIFT : STD_LOGIC;
signal microblaze_0_debug_TDI : STD_LOGIC;
signal microblaze_0_debug_TDO : STD_LOGIC;
signal microblaze_0_debug_UPDATE : STD_LOGIC;
signal microblaze_0_dlmb_1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_1_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_1_CE : STD_LOGIC;
signal microblaze_0_dlmb_1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_1_READY : STD_LOGIC;
signal microblaze_0_dlmb_1_UE : STD_LOGIC;
signal microblaze_0_dlmb_1_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_1_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_WRITESTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_1_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_CE : STD_LOGIC;
signal microblaze_0_ilmb_1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_1_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_READY : STD_LOGIC;
signal microblaze_0_ilmb_1_UE : STD_LOGIC;
signal microblaze_0_ilmb_1_WAIT : STD_LOGIC;
signal microblaze_0_intc_axi_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_ARREADY : STD_LOGIC;
signal microblaze_0_intc_axi_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_intc_axi_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_AWREADY : STD_LOGIC;
signal microblaze_0_intc_axi_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_intc_axi_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_intc_axi_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_intc_axi_BVALID : STD_LOGIC;
signal microblaze_0_intc_axi_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_intc_axi_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_intc_axi_RVALID : STD_LOGIC;
signal microblaze_0_intc_axi_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_WREADY : STD_LOGIC;
signal microblaze_0_intc_axi_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_intc_axi_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_interrupt_ACK : STD_LOGIC_VECTOR ( 0 to 1 );
signal microblaze_0_interrupt_ADDRESS : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_interrupt_INTERRUPT : STD_LOGIC;
signal microblaze_0_intr : STD_LOGIC_VECTOR ( 6 downto 0 );
signal mig_7series_0_DDR3_ADDR : STD_LOGIC_VECTOR ( 13 downto 0 );
signal mig_7series_0_DDR3_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal mig_7series_0_DDR3_CAS_N : STD_LOGIC;
signal mig_7series_0_DDR3_CKE : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_CK_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_CK_P : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_CS_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_DM : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mig_7series_0_DDR3_DQ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal mig_7series_0_DDR3_DQS_N : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mig_7series_0_DDR3_DQS_P : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mig_7series_0_DDR3_ODT : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_RAS_N : STD_LOGIC;
signal mig_7series_0_DDR3_RESET_N : STD_LOGIC;
signal mig_7series_0_DDR3_WE_N : STD_LOGIC;
signal mig_7series_0_mmcm_locked : STD_LOGIC;
signal mig_7series_0_ui_clk : STD_LOGIC;
signal mig_7series_0_ui_clk_sync_rst : STD_LOGIC;
signal reset_1 : STD_LOGIC;
signal rst_clk_wiz_1_100M_bus_struct_reset : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_clk_wiz_1_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_clk_wiz_1_100M_mb_reset : STD_LOGIC;
signal rst_clk_wiz_1_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_mig_7series_0_83M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal sys_clock_1 : STD_LOGIC;
signal xadc_wiz_0_ip2intc_irpt : STD_LOGIC;
signal xadc_wiz_0_temp_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_axi_gpio_0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_axi_gpio_1_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_axi_iic_0_gpo_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_uartlite_0_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_M_AXI_IC_AWLOCK_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_M_AXI_IC_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_M_AXI_IC_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_M_AXI_IC_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_M_AXI_IC_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_M_AXI_DC_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_microblaze_0_M_AXI_DC_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_microblaze_0_M_AXI_IC_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_microblaze_0_M_AXI_IC_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_microblaze_0_M_AXI_IC_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_microblaze_0_axi_periph_M10_AXI_araddr_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_arprot_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_awaddr_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_awprot_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_bready_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_rready_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_wdata_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_wstrb_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_mig_7series_0_init_calib_complete_UNCONNECTED : STD_LOGIC;
signal NLW_rst_clk_wiz_1_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_mig_7series_0_83M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_mig_7series_0_83M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_mig_7series_0_83M_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_mig_7series_0_83M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xadc_wiz_0_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_busy_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_eoc_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_eos_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_user_temp_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccaux_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccint_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_channel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute BMM_INFO_PROCESSOR : string;
attribute BMM_INFO_PROCESSOR of microblaze_0 : label is "microblaze-le > system microblaze_0_local_memory/dlmb_bram_if_cntlr";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of microblaze_0 : label is "yes";
begin
DDR3_addr(13 downto 0) <= mig_7series_0_DDR3_ADDR(13 downto 0);
DDR3_ba(2 downto 0) <= mig_7series_0_DDR3_BA(2 downto 0);
DDR3_cas_n <= mig_7series_0_DDR3_CAS_N;
DDR3_ck_n(0) <= mig_7series_0_DDR3_CK_N(0);
DDR3_ck_p(0) <= mig_7series_0_DDR3_CK_P(0);
DDR3_cke(0) <= mig_7series_0_DDR3_CKE(0);
DDR3_cs_n(0) <= mig_7series_0_DDR3_CS_N(0);
DDR3_dm(1 downto 0) <= mig_7series_0_DDR3_DM(1 downto 0);
DDR3_odt(0) <= mig_7series_0_DDR3_ODT(0);
DDR3_ras_n <= mig_7series_0_DDR3_RAS_N;
DDR3_reset_n <= mig_7series_0_DDR3_RESET_N;
DDR3_we_n <= mig_7series_0_DDR3_WE_N;
Vaux0_1_V_N <= Vaux0_v_n;
Vaux0_1_V_P <= Vaux0_v_p;
Vaux10_1_V_N <= Vaux10_v_n;
Vaux10_1_V_P <= Vaux10_v_p;
Vaux12_1_V_N <= Vaux12_v_n;
Vaux12_1_V_P <= Vaux12_v_p;
Vaux13_1_V_N <= Vaux13_v_n;
Vaux13_1_V_P <= Vaux13_v_p;
Vaux14_1_V_N <= Vaux14_v_n;
Vaux14_1_V_P <= Vaux14_v_p;
Vaux15_1_V_N <= Vaux15_v_n;
Vaux15_1_V_P <= Vaux15_v_p;
Vaux1_1_V_N <= Vaux1_v_n;
Vaux1_1_V_P <= Vaux1_v_p;
Vaux2_1_V_N <= Vaux2_v_n;
Vaux2_1_V_P <= Vaux2_v_p;
Vaux4_1_V_N <= Vaux4_v_n;
Vaux4_1_V_P <= Vaux4_v_p;
Vaux5_1_V_N <= Vaux5_v_n;
Vaux5_1_V_P <= Vaux5_v_p;
Vaux6_1_V_N <= Vaux6_v_n;
Vaux6_1_V_P <= Vaux6_v_p;
Vaux7_1_V_N <= Vaux7_v_n;
Vaux7_1_V_P <= Vaux7_v_p;
Vaux9_1_V_N <= Vaux9_v_n;
Vaux9_1_V_P <= Vaux9_v_p;
Vp_Vn_1_V_N <= Vp_Vn_v_n;
Vp_Vn_1_V_P <= Vp_Vn_v_p;
axi_ethernetlite_0_MDIO_MDIO_I <= eth_mdio_mdc_mdio_i;
axi_ethernetlite_0_MII_COL <= eth_mii_col;
axi_ethernetlite_0_MII_CRS <= eth_mii_crs;
axi_ethernetlite_0_MII_RXD(3 downto 0) <= eth_mii_rxd(3 downto 0);
axi_ethernetlite_0_MII_RX_CLK <= eth_mii_rx_clk;
axi_ethernetlite_0_MII_RX_DV <= eth_mii_rx_dv;
axi_ethernetlite_0_MII_RX_ER <= eth_mii_rx_er;
axi_ethernetlite_0_MII_TX_CLK <= eth_mii_tx_clk;
axi_gpio_0_GPIO2_TRI_I(19 downto 0) <= shield_dp0_dp19_tri_i(19 downto 0);
axi_gpio_1_GPIO1_TRI_I(15 downto 0) <= shield_dp26_dp41_tri_i(15 downto 0);
axi_gpio_2_GPIO2_TRI_I(11 downto 0) <= rgb_led_tri_i(11 downto 0);
axi_gpio_2_GPIO_TRI_I(3 downto 0) <= led_4bits_tri_i(3 downto 0);
axi_gpio_pullup_GPIO_TRI_I(1 downto 0) <= i2c_pullups_tri_i(1 downto 0);
axi_gpio_sw_GPIO2_TRI_I(3 downto 0) <= push_buttons_4bits_tri_i(3 downto 0);
axi_gpio_sw_GPIO_TRI_I(3 downto 0) <= dip_switches_4bits_tri_i(3 downto 0);
axi_iic_0_IIC_SCL_I <= i2c_scl_i;
axi_iic_0_IIC_SDA_I <= i2c_sda_i;
axi_quad_spi_0_SPI_0_IO0_I <= spi_io0_i;
axi_quad_spi_0_SPI_0_IO1_I <= spi_io1_i;
axi_quad_spi_0_SPI_0_SCK_I <= spi_sck_i;
axi_quad_spi_0_SPI_0_SS_I <= spi_ss_i;
axi_quad_spi_1_SPI_0_IO0_I <= qspi_flash_io0_i;
axi_quad_spi_1_SPI_0_IO1_I <= qspi_flash_io1_i;
axi_quad_spi_1_SPI_0_IO2_I <= qspi_flash_io2_i;
axi_quad_spi_1_SPI_0_IO3_I <= qspi_flash_io3_i;
axi_quad_spi_1_SPI_0_SCK_I <= qspi_flash_sck_i;
axi_quad_spi_1_SPI_0_SS_I <= qspi_flash_ss_i;
axi_uartlite_0_UART_RxD <= usb_uart_rxd;
eth_mdio_mdc_mdc <= axi_ethernetlite_0_MDIO_MDC;
eth_mdio_mdc_mdio_o <= axi_ethernetlite_0_MDIO_MDIO_O;
eth_mdio_mdc_mdio_t <= axi_ethernetlite_0_MDIO_MDIO_T;
eth_mii_rst_n <= axi_ethernetlite_0_MII_RST_N;
eth_mii_tx_en <= axi_ethernetlite_0_MII_TX_EN;
eth_mii_txd(3 downto 0) <= axi_ethernetlite_0_MII_TXD(3 downto 0);
eth_ref_clk <= clk_wiz_1_clk_out4;
i2c_pullups_tri_o(1 downto 0) <= axi_gpio_pullup_GPIO_TRI_O(1 downto 0);
i2c_pullups_tri_t(1 downto 0) <= axi_gpio_pullup_GPIO_TRI_T(1 downto 0);
i2c_scl_o <= axi_iic_0_IIC_SCL_O;
i2c_scl_t <= axi_iic_0_IIC_SCL_T;
i2c_sda_o <= axi_iic_0_IIC_SDA_O;
i2c_sda_t <= axi_iic_0_IIC_SDA_T;
led_4bits_tri_o(3 downto 0) <= axi_gpio_2_GPIO_TRI_O(3 downto 0);
led_4bits_tri_t(3 downto 0) <= axi_gpio_2_GPIO_TRI_T(3 downto 0);
qspi_flash_io0_o <= axi_quad_spi_1_SPI_0_IO0_O;
qspi_flash_io0_t <= axi_quad_spi_1_SPI_0_IO0_T;
qspi_flash_io1_o <= axi_quad_spi_1_SPI_0_IO1_O;
qspi_flash_io1_t <= axi_quad_spi_1_SPI_0_IO1_T;
qspi_flash_io2_o <= axi_quad_spi_1_SPI_0_IO2_O;
qspi_flash_io2_t <= axi_quad_spi_1_SPI_0_IO2_T;
qspi_flash_io3_o <= axi_quad_spi_1_SPI_0_IO3_O;
qspi_flash_io3_t <= axi_quad_spi_1_SPI_0_IO3_T;
qspi_flash_sck_o <= axi_quad_spi_1_SPI_0_SCK_O;
qspi_flash_sck_t <= axi_quad_spi_1_SPI_0_SCK_T;
qspi_flash_ss_o <= axi_quad_spi_1_SPI_0_SS_O(0);
qspi_flash_ss_t <= axi_quad_spi_1_SPI_0_SS_T;
reset_1 <= reset;
rgb_led_tri_o(11 downto 0) <= axi_gpio_2_GPIO2_TRI_O(11 downto 0);
rgb_led_tri_t(11 downto 0) <= axi_gpio_2_GPIO2_TRI_T(11 downto 0);
shield_dp0_dp19_tri_o(19 downto 0) <= axi_gpio_0_GPIO2_TRI_O(19 downto 0);
shield_dp0_dp19_tri_t(19 downto 0) <= axi_gpio_0_GPIO2_TRI_T(19 downto 0);
shield_dp26_dp41_tri_o(15 downto 0) <= axi_gpio_1_GPIO1_TRI_O(15 downto 0);
shield_dp26_dp41_tri_t(15 downto 0) <= axi_gpio_1_GPIO1_TRI_T(15 downto 0);
spi_io0_o <= axi_quad_spi_0_SPI_0_IO0_O;
spi_io0_t <= axi_quad_spi_0_SPI_0_IO0_T;
spi_io1_o <= axi_quad_spi_0_SPI_0_IO1_O;
spi_io1_t <= axi_quad_spi_0_SPI_0_IO1_T;
spi_sck_o <= axi_quad_spi_0_SPI_0_SCK_O;
spi_sck_t <= axi_quad_spi_0_SPI_0_SCK_T;
spi_ss_o <= axi_quad_spi_0_SPI_0_SS_O(0);
spi_ss_t <= axi_quad_spi_0_SPI_0_SS_T;
sys_clock_1 <= sys_clock;
usb_uart_txd <= axi_uartlite_0_UART_TxD;
axi_ethernetlite_0: component system_axi_ethernetlite_0_0
port map (
ip2intc_irpt => axi_ethernetlite_0_ip2intc_irpt,
phy_col => axi_ethernetlite_0_MII_COL,
phy_crs => axi_ethernetlite_0_MII_CRS,
phy_dv => axi_ethernetlite_0_MII_RX_DV,
phy_mdc => axi_ethernetlite_0_MDIO_MDC,
phy_mdio_i => axi_ethernetlite_0_MDIO_MDIO_I,
phy_mdio_o => axi_ethernetlite_0_MDIO_MDIO_O,
phy_mdio_t => axi_ethernetlite_0_MDIO_MDIO_T,
phy_rst_n => axi_ethernetlite_0_MII_RST_N,
phy_rx_clk => axi_ethernetlite_0_MII_RX_CLK,
phy_rx_data(3 downto 0) => axi_ethernetlite_0_MII_RXD(3 downto 0),
phy_rx_er => axi_ethernetlite_0_MII_RX_ER,
phy_tx_clk => axi_ethernetlite_0_MII_TX_CLK,
phy_tx_data(3 downto 0) => axi_ethernetlite_0_MII_TXD(3 downto 0),
phy_tx_en => axi_ethernetlite_0_MII_TX_EN,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(12 downto 0) => microblaze_0_axi_periph_M01_AXI_ARADDR(12 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M01_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M01_AXI_ARVALID(0),
s_axi_awaddr(12 downto 0) => microblaze_0_axi_periph_M01_AXI_AWADDR(12 downto 0),
s_axi_awready => microblaze_0_axi_periph_M01_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M01_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M01_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M01_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M01_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M01_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M01_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M01_AXI_WVALID(0)
);
axi_gpio_0: component system_axi_gpio_0_0
port map (
gpio_io_i(19 downto 0) => axi_gpio_0_GPIO2_TRI_I(19 downto 0),
gpio_io_o(19 downto 0) => axi_gpio_0_GPIO2_TRI_O(19 downto 0),
gpio_io_t(19 downto 0) => axi_gpio_0_GPIO2_TRI_T(19 downto 0),
ip2intc_irpt => NLW_axi_gpio_0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M11_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M11_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M11_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M11_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M11_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M11_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M11_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M11_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M11_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M11_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M11_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M11_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M11_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M11_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M11_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M11_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M11_AXI_WVALID(0)
);
axi_gpio_1: component system_axi_gpio_1_0
port map (
gpio_io_i(15 downto 0) => axi_gpio_1_GPIO1_TRI_I(15 downto 0),
gpio_io_o(15 downto 0) => axi_gpio_1_GPIO1_TRI_O(15 downto 0),
gpio_io_t(15 downto 0) => axi_gpio_1_GPIO1_TRI_T(15 downto 0),
ip2intc_irpt => NLW_axi_gpio_1_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M12_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M12_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M12_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M12_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M12_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M12_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M12_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M12_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M12_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M12_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M12_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M12_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M12_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M12_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M12_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M12_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M12_AXI_WVALID(0)
);
axi_gpio_led: component system_axi_gpio_led_0
port map (
gpio2_io_i(11 downto 0) => axi_gpio_2_GPIO2_TRI_I(11 downto 0),
gpio2_io_o(11 downto 0) => axi_gpio_2_GPIO2_TRI_O(11 downto 0),
gpio2_io_t(11 downto 0) => axi_gpio_2_GPIO2_TRI_T(11 downto 0),
gpio_io_i(3 downto 0) => axi_gpio_2_GPIO_TRI_I(3 downto 0),
gpio_io_o(3 downto 0) => axi_gpio_2_GPIO_TRI_O(3 downto 0),
gpio_io_t(3 downto 0) => axi_gpio_2_GPIO_TRI_T(3 downto 0),
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M08_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M08_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M08_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M08_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M08_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M08_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M08_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M08_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M08_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M08_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M08_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M08_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M08_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M08_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M08_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M08_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M08_AXI_WVALID(0)
);
axi_gpio_pullup: component system_axi_gpio_pullup_0
port map (
gpio_io_i(1 downto 0) => axi_gpio_pullup_GPIO_TRI_I(1 downto 0),
gpio_io_o(1 downto 0) => axi_gpio_pullup_GPIO_TRI_O(1 downto 0),
gpio_io_t(1 downto 0) => axi_gpio_pullup_GPIO_TRI_T(1 downto 0),
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M09_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M09_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M09_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M09_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M09_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M09_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M09_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M09_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M09_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M09_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M09_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M09_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M09_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M09_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M09_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M09_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M09_AXI_WVALID(0)
);
axi_gpio_sw: component system_axi_gpio_sw_0
port map (
gpio2_io_i(3 downto 0) => axi_gpio_sw_GPIO2_TRI_I(3 downto 0),
gpio_io_i(3 downto 0) => axi_gpio_sw_GPIO_TRI_I(3 downto 0),
ip2intc_irpt => axi_gpio_sw_ip2intc_irpt,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M07_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M07_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M07_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M07_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M07_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M07_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M07_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M07_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M07_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M07_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M07_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M07_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M07_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M07_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M07_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M07_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M07_AXI_WVALID(0)
);
axi_iic_0: component system_axi_iic_0_0
port map (
gpo(0) => NLW_axi_iic_0_gpo_UNCONNECTED(0),
iic2intc_irpt => axi_iic_0_iic2intc_irpt,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M06_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M06_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M06_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M06_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M06_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M06_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M06_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M06_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M06_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M06_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M06_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M06_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M06_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M06_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M06_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M06_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M06_AXI_WVALID(0),
scl_i => axi_iic_0_IIC_SCL_I,
scl_o => axi_iic_0_IIC_SCL_O,
scl_t => axi_iic_0_IIC_SCL_T,
sda_i => axi_iic_0_IIC_SDA_I,
sda_o => axi_iic_0_IIC_SDA_O,
sda_t => axi_iic_0_IIC_SDA_T
);
axi_mem_intercon: entity work.system_axi_mem_intercon_0
port map (
ACLK => microblaze_0_Clk,
ARESETN => rst_clk_wiz_1_100M_interconnect_aresetn(0),
M00_ACLK => mig_7series_0_ui_clk,
M00_ARESETN => rst_mig_7series_0_83M_peripheral_aresetn(0),
M00_AXI_araddr(27 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(27 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
M00_AXI_arlen(7 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(7 downto 0),
M00_AXI_arlock => axi_mem_intercon_M00_AXI_ARLOCK,
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(27 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(27 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
M00_AXI_awlen(7 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(7 downto 0),
M00_AXI_awlock => axi_mem_intercon_M00_AXI_AWLOCK,
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(0) => axi_mem_intercon_M00_AXI_BID(0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(127 downto 0) => axi_mem_intercon_M00_AXI_RDATA(127 downto 0),
M00_AXI_rid(0) => axi_mem_intercon_M00_AXI_RID(0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(127 downto 0) => axi_mem_intercon_M00_AXI_WDATA(127 downto 0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(15 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(15 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => microblaze_0_Clk,
S00_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => microblaze_0_M_AXI_DC_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => microblaze_0_M_AXI_DC_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => microblaze_0_M_AXI_DC_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => microblaze_0_M_AXI_DC_ARLEN(7 downto 0),
S00_AXI_arlock => microblaze_0_M_AXI_DC_ARLOCK,
S00_AXI_arprot(2 downto 0) => microblaze_0_M_AXI_DC_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => microblaze_0_M_AXI_DC_ARQOS(3 downto 0),
S00_AXI_arready => microblaze_0_M_AXI_DC_ARREADY,
S00_AXI_arsize(2 downto 0) => microblaze_0_M_AXI_DC_ARSIZE(2 downto 0),
S00_AXI_arvalid => microblaze_0_M_AXI_DC_ARVALID,
S00_AXI_awaddr(31 downto 0) => microblaze_0_M_AXI_DC_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => microblaze_0_M_AXI_DC_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => microblaze_0_M_AXI_DC_AWCACHE(3 downto 0),
S00_AXI_awlen(7 downto 0) => microblaze_0_M_AXI_DC_AWLEN(7 downto 0),
S00_AXI_awlock => microblaze_0_M_AXI_DC_AWLOCK,
S00_AXI_awprot(2 downto 0) => microblaze_0_M_AXI_DC_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => microblaze_0_M_AXI_DC_AWQOS(3 downto 0),
S00_AXI_awready => microblaze_0_M_AXI_DC_AWREADY,
S00_AXI_awsize(2 downto 0) => microblaze_0_M_AXI_DC_AWSIZE(2 downto 0),
S00_AXI_awvalid => microblaze_0_M_AXI_DC_AWVALID,
S00_AXI_bready => microblaze_0_M_AXI_DC_BREADY,
S00_AXI_bresp(1 downto 0) => microblaze_0_M_AXI_DC_BRESP(1 downto 0),
S00_AXI_bvalid => microblaze_0_M_AXI_DC_BVALID,
S00_AXI_rdata(31 downto 0) => microblaze_0_M_AXI_DC_RDATA(31 downto 0),
S00_AXI_rlast => microblaze_0_M_AXI_DC_RLAST,
S00_AXI_rready => microblaze_0_M_AXI_DC_RREADY,
S00_AXI_rresp(1 downto 0) => microblaze_0_M_AXI_DC_RRESP(1 downto 0),
S00_AXI_rvalid => microblaze_0_M_AXI_DC_RVALID,
S00_AXI_wdata(31 downto 0) => microblaze_0_M_AXI_DC_WDATA(31 downto 0),
S00_AXI_wlast => microblaze_0_M_AXI_DC_WLAST,
S00_AXI_wready => microblaze_0_M_AXI_DC_WREADY,
S00_AXI_wstrb(3 downto 0) => microblaze_0_M_AXI_DC_WSTRB(3 downto 0),
S00_AXI_wvalid => microblaze_0_M_AXI_DC_WVALID,
S01_ACLK => microblaze_0_Clk,
S01_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S01_AXI_araddr(31 downto 0) => microblaze_0_M_AXI_IC_ARADDR(31 downto 0),
S01_AXI_arburst(1 downto 0) => microblaze_0_M_AXI_IC_ARBURST(1 downto 0),
S01_AXI_arcache(3 downto 0) => microblaze_0_M_AXI_IC_ARCACHE(3 downto 0),
S01_AXI_arlen(7 downto 0) => microblaze_0_M_AXI_IC_ARLEN(7 downto 0),
S01_AXI_arlock => microblaze_0_M_AXI_IC_ARLOCK,
S01_AXI_arprot(2 downto 0) => microblaze_0_M_AXI_IC_ARPROT(2 downto 0),
S01_AXI_arqos(3 downto 0) => microblaze_0_M_AXI_IC_ARQOS(3 downto 0),
S01_AXI_arready => microblaze_0_M_AXI_IC_ARREADY,
S01_AXI_arsize(2 downto 0) => microblaze_0_M_AXI_IC_ARSIZE(2 downto 0),
S01_AXI_arvalid => microblaze_0_M_AXI_IC_ARVALID,
S01_AXI_rdata(31 downto 0) => microblaze_0_M_AXI_IC_RDATA(31 downto 0),
S01_AXI_rlast => microblaze_0_M_AXI_IC_RLAST,
S01_AXI_rready => microblaze_0_M_AXI_IC_RREADY,
S01_AXI_rresp(1 downto 0) => microblaze_0_M_AXI_IC_RRESP(1 downto 0),
S01_AXI_rvalid => microblaze_0_M_AXI_IC_RVALID
);
axi_quad_spi_flash: component system_axi_quad_spi_flash_0
port map (
ext_spi_clk => microblaze_0_Clk,
io0_i => axi_quad_spi_1_SPI_0_IO0_I,
io0_o => axi_quad_spi_1_SPI_0_IO0_O,
io0_t => axi_quad_spi_1_SPI_0_IO0_T,
io1_i => axi_quad_spi_1_SPI_0_IO1_I,
io1_o => axi_quad_spi_1_SPI_0_IO1_O,
io1_t => axi_quad_spi_1_SPI_0_IO1_T,
io2_i => axi_quad_spi_1_SPI_0_IO2_I,
io2_o => axi_quad_spi_1_SPI_0_IO2_O,
io2_t => axi_quad_spi_1_SPI_0_IO2_T,
io3_i => axi_quad_spi_1_SPI_0_IO3_I,
io3_o => axi_quad_spi_1_SPI_0_IO3_O,
io3_t => axi_quad_spi_1_SPI_0_IO3_T,
ip2intc_irpt => axi_quad_spi_flash_ip2intc_irpt,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(6 downto 0) => microblaze_0_axi_periph_M05_AXI_ARADDR(6 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M05_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M05_AXI_ARVALID(0),
s_axi_awaddr(6 downto 0) => microblaze_0_axi_periph_M05_AXI_AWADDR(6 downto 0),
s_axi_awready => microblaze_0_axi_periph_M05_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M05_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M05_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M05_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M05_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M05_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M05_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M05_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M05_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M05_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M05_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M05_AXI_WVALID(0),
sck_i => axi_quad_spi_1_SPI_0_SCK_I,
sck_o => axi_quad_spi_1_SPI_0_SCK_O,
sck_t => axi_quad_spi_1_SPI_0_SCK_T,
ss_i(0) => axi_quad_spi_1_SPI_0_SS_I,
ss_o(0) => axi_quad_spi_1_SPI_0_SS_O(0),
ss_t => axi_quad_spi_1_SPI_0_SS_T
);
axi_quad_spi_shield: component system_axi_quad_spi_shield_0
port map (
ext_spi_clk => microblaze_0_Clk,
io0_i => axi_quad_spi_0_SPI_0_IO0_I,
io0_o => axi_quad_spi_0_SPI_0_IO0_O,
io0_t => axi_quad_spi_0_SPI_0_IO0_T,
io1_i => axi_quad_spi_0_SPI_0_IO1_I,
io1_o => axi_quad_spi_0_SPI_0_IO1_O,
io1_t => axi_quad_spi_0_SPI_0_IO1_T,
ip2intc_irpt => axi_quad_spi_shield_ip2intc_irpt,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(6 downto 0) => microblaze_0_axi_periph_M04_AXI_ARADDR(6 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M04_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M04_AXI_ARVALID(0),
s_axi_awaddr(6 downto 0) => microblaze_0_axi_periph_M04_AXI_AWADDR(6 downto 0),
s_axi_awready => microblaze_0_axi_periph_M04_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M04_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M04_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M04_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M04_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M04_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M04_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M04_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M04_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M04_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M04_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M04_AXI_WVALID(0),
sck_i => axi_quad_spi_0_SPI_0_SCK_I,
sck_o => axi_quad_spi_0_SPI_0_SCK_O,
sck_t => axi_quad_spi_0_SPI_0_SCK_T,
ss_i(0) => axi_quad_spi_0_SPI_0_SS_I,
ss_o(0) => axi_quad_spi_0_SPI_0_SS_O(0),
ss_t => axi_quad_spi_0_SPI_0_SS_T
);
axi_timer_0: component system_axi_timer_0_0
port map (
capturetrig0 => '0',
capturetrig1 => '0',
freeze => '0',
generateout0 => NLW_axi_timer_0_generateout0_UNCONNECTED,
generateout1 => NLW_axi_timer_0_generateout1_UNCONNECTED,
interrupt => axi_timer_0_interrupt,
pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(4 downto 0) => microblaze_0_axi_periph_M02_AXI_ARADDR(4 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M02_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M02_AXI_ARVALID(0),
s_axi_awaddr(4 downto 0) => microblaze_0_axi_periph_M02_AXI_AWADDR(4 downto 0),
s_axi_awready => microblaze_0_axi_periph_M02_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M02_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M02_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M02_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M02_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M02_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M02_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M02_AXI_WVALID(0)
);
axi_uartlite_0: component system_axi_uartlite_0_0
port map (
interrupt => NLW_axi_uartlite_0_interrupt_UNCONNECTED,
rx => axi_uartlite_0_UART_RxD,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(3 downto 0) => microblaze_0_axi_periph_M03_AXI_ARADDR(3 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M03_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M03_AXI_ARVALID(0),
s_axi_awaddr(3 downto 0) => microblaze_0_axi_periph_M03_AXI_AWADDR(3 downto 0),
s_axi_awready => microblaze_0_axi_periph_M03_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M03_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M03_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M03_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M03_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M03_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M03_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M03_AXI_WVALID(0),
tx => axi_uartlite_0_UART_TxD
);
clk_wiz_1: component system_clk_wiz_1_0
port map (
clk_in1 => sys_clock_1,
clk_out1 => microblaze_0_Clk,
clk_out2 => clk_wiz_1_clk_out2,
clk_out3 => clk_wiz_1_clk_out3,
clk_out4 => clk_wiz_1_clk_out4,
locked => clk_wiz_1_locked,
resetn => reset_1
);
mdm_1: component system_mdm_1_0
port map (
Dbg_Capture_0 => microblaze_0_debug_CAPTURE,
Dbg_Clk_0 => microblaze_0_debug_CLK,
Dbg_Disable_0 => microblaze_0_debug_DISABLE,
Dbg_Reg_En_0(0 to 7) => microblaze_0_debug_REG_EN(0 to 7),
Dbg_Rst_0 => microblaze_0_debug_RST,
Dbg_Shift_0 => microblaze_0_debug_SHIFT,
Dbg_TDI_0 => microblaze_0_debug_TDI,
Dbg_TDO_0 => microblaze_0_debug_TDO,
Dbg_Update_0 => microblaze_0_debug_UPDATE,
Debug_SYS_Rst => mdm_1_debug_sys_rst
);
microblaze_0: component system_microblaze_0_0
port map (
Byte_Enable(0 to 3) => microblaze_0_dlmb_1_BE(0 to 3),
Clk => microblaze_0_Clk,
DCE => microblaze_0_dlmb_1_CE,
DReady => microblaze_0_dlmb_1_READY,
DUE => microblaze_0_dlmb_1_UE,
DWait => microblaze_0_dlmb_1_WAIT,
D_AS => microblaze_0_dlmb_1_ADDRSTROBE,
Data_Addr(0 to 31) => microblaze_0_dlmb_1_ABUS(0 to 31),
Data_Read(0 to 31) => microblaze_0_dlmb_1_READDBUS(0 to 31),
Data_Write(0 to 31) => microblaze_0_dlmb_1_WRITEDBUS(0 to 31),
Dbg_Capture => microblaze_0_debug_CAPTURE,
Dbg_Clk => microblaze_0_debug_CLK,
Dbg_Disable => microblaze_0_debug_DISABLE,
Dbg_Reg_En(0 to 7) => microblaze_0_debug_REG_EN(0 to 7),
Dbg_Shift => microblaze_0_debug_SHIFT,
Dbg_TDI => microblaze_0_debug_TDI,
Dbg_TDO => microblaze_0_debug_TDO,
Dbg_Update => microblaze_0_debug_UPDATE,
Debug_Rst => microblaze_0_debug_RST,
ICE => microblaze_0_ilmb_1_CE,
IFetch => microblaze_0_ilmb_1_READSTROBE,
IReady => microblaze_0_ilmb_1_READY,
IUE => microblaze_0_ilmb_1_UE,
IWAIT => microblaze_0_ilmb_1_WAIT,
I_AS => microblaze_0_ilmb_1_ADDRSTROBE,
Instr(0 to 31) => microblaze_0_ilmb_1_READDBUS(0 to 31),
Instr_Addr(0 to 31) => microblaze_0_ilmb_1_ABUS(0 to 31),
Interrupt => microblaze_0_interrupt_INTERRUPT,
Interrupt_Ack(0 to 1) => microblaze_0_interrupt_ACK(0 to 1),
Interrupt_Address(0) => microblaze_0_interrupt_ADDRESS(31),
Interrupt_Address(1) => microblaze_0_interrupt_ADDRESS(30),
Interrupt_Address(2) => microblaze_0_interrupt_ADDRESS(29),
Interrupt_Address(3) => microblaze_0_interrupt_ADDRESS(28),
Interrupt_Address(4) => microblaze_0_interrupt_ADDRESS(27),
Interrupt_Address(5) => microblaze_0_interrupt_ADDRESS(26),
Interrupt_Address(6) => microblaze_0_interrupt_ADDRESS(25),
Interrupt_Address(7) => microblaze_0_interrupt_ADDRESS(24),
Interrupt_Address(8) => microblaze_0_interrupt_ADDRESS(23),
Interrupt_Address(9) => microblaze_0_interrupt_ADDRESS(22),
Interrupt_Address(10) => microblaze_0_interrupt_ADDRESS(21),
Interrupt_Address(11) => microblaze_0_interrupt_ADDRESS(20),
Interrupt_Address(12) => microblaze_0_interrupt_ADDRESS(19),
Interrupt_Address(13) => microblaze_0_interrupt_ADDRESS(18),
Interrupt_Address(14) => microblaze_0_interrupt_ADDRESS(17),
Interrupt_Address(15) => microblaze_0_interrupt_ADDRESS(16),
Interrupt_Address(16) => microblaze_0_interrupt_ADDRESS(15),
Interrupt_Address(17) => microblaze_0_interrupt_ADDRESS(14),
Interrupt_Address(18) => microblaze_0_interrupt_ADDRESS(13),
Interrupt_Address(19) => microblaze_0_interrupt_ADDRESS(12),
Interrupt_Address(20) => microblaze_0_interrupt_ADDRESS(11),
Interrupt_Address(21) => microblaze_0_interrupt_ADDRESS(10),
Interrupt_Address(22) => microblaze_0_interrupt_ADDRESS(9),
Interrupt_Address(23) => microblaze_0_interrupt_ADDRESS(8),
Interrupt_Address(24) => microblaze_0_interrupt_ADDRESS(7),
Interrupt_Address(25) => microblaze_0_interrupt_ADDRESS(6),
Interrupt_Address(26) => microblaze_0_interrupt_ADDRESS(5),
Interrupt_Address(27) => microblaze_0_interrupt_ADDRESS(4),
Interrupt_Address(28) => microblaze_0_interrupt_ADDRESS(3),
Interrupt_Address(29) => microblaze_0_interrupt_ADDRESS(2),
Interrupt_Address(30) => microblaze_0_interrupt_ADDRESS(1),
Interrupt_Address(31) => microblaze_0_interrupt_ADDRESS(0),
M_AXI_DC_ARADDR(31 downto 0) => microblaze_0_M_AXI_DC_ARADDR(31 downto 0),
M_AXI_DC_ARBURST(1 downto 0) => microblaze_0_M_AXI_DC_ARBURST(1 downto 0),
M_AXI_DC_ARCACHE(3 downto 0) => microblaze_0_M_AXI_DC_ARCACHE(3 downto 0),
M_AXI_DC_ARID(0) => NLW_microblaze_0_M_AXI_DC_ARID_UNCONNECTED(0),
M_AXI_DC_ARLEN(7 downto 0) => microblaze_0_M_AXI_DC_ARLEN(7 downto 0),
M_AXI_DC_ARLOCK => microblaze_0_M_AXI_DC_ARLOCK,
M_AXI_DC_ARPROT(2 downto 0) => microblaze_0_M_AXI_DC_ARPROT(2 downto 0),
M_AXI_DC_ARQOS(3 downto 0) => microblaze_0_M_AXI_DC_ARQOS(3 downto 0),
M_AXI_DC_ARREADY => microblaze_0_M_AXI_DC_ARREADY,
M_AXI_DC_ARSIZE(2 downto 0) => microblaze_0_M_AXI_DC_ARSIZE(2 downto 0),
M_AXI_DC_ARVALID => microblaze_0_M_AXI_DC_ARVALID,
M_AXI_DC_AWADDR(31 downto 0) => microblaze_0_M_AXI_DC_AWADDR(31 downto 0),
M_AXI_DC_AWBURST(1 downto 0) => microblaze_0_M_AXI_DC_AWBURST(1 downto 0),
M_AXI_DC_AWCACHE(3 downto 0) => microblaze_0_M_AXI_DC_AWCACHE(3 downto 0),
M_AXI_DC_AWID(0) => NLW_microblaze_0_M_AXI_DC_AWID_UNCONNECTED(0),
M_AXI_DC_AWLEN(7 downto 0) => microblaze_0_M_AXI_DC_AWLEN(7 downto 0),
M_AXI_DC_AWLOCK => microblaze_0_M_AXI_DC_AWLOCK,
M_AXI_DC_AWPROT(2 downto 0) => microblaze_0_M_AXI_DC_AWPROT(2 downto 0),
M_AXI_DC_AWQOS(3 downto 0) => microblaze_0_M_AXI_DC_AWQOS(3 downto 0),
M_AXI_DC_AWREADY => microblaze_0_M_AXI_DC_AWREADY,
M_AXI_DC_AWSIZE(2 downto 0) => microblaze_0_M_AXI_DC_AWSIZE(2 downto 0),
M_AXI_DC_AWVALID => microblaze_0_M_AXI_DC_AWVALID,
M_AXI_DC_BID(0) => '0',
M_AXI_DC_BREADY => microblaze_0_M_AXI_DC_BREADY,
M_AXI_DC_BRESP(1 downto 0) => microblaze_0_M_AXI_DC_BRESP(1 downto 0),
M_AXI_DC_BVALID => microblaze_0_M_AXI_DC_BVALID,
M_AXI_DC_RDATA(31 downto 0) => microblaze_0_M_AXI_DC_RDATA(31 downto 0),
M_AXI_DC_RID(0) => '0',
M_AXI_DC_RLAST => microblaze_0_M_AXI_DC_RLAST,
M_AXI_DC_RREADY => microblaze_0_M_AXI_DC_RREADY,
M_AXI_DC_RRESP(1 downto 0) => microblaze_0_M_AXI_DC_RRESP(1 downto 0),
M_AXI_DC_RVALID => microblaze_0_M_AXI_DC_RVALID,
M_AXI_DC_WDATA(31 downto 0) => microblaze_0_M_AXI_DC_WDATA(31 downto 0),
M_AXI_DC_WLAST => microblaze_0_M_AXI_DC_WLAST,
M_AXI_DC_WREADY => microblaze_0_M_AXI_DC_WREADY,
M_AXI_DC_WSTRB(3 downto 0) => microblaze_0_M_AXI_DC_WSTRB(3 downto 0),
M_AXI_DC_WVALID => microblaze_0_M_AXI_DC_WVALID,
M_AXI_DP_ARADDR(31 downto 0) => microblaze_0_axi_dp_ARADDR(31 downto 0),
M_AXI_DP_ARPROT(2 downto 0) => microblaze_0_axi_dp_ARPROT(2 downto 0),
M_AXI_DP_ARREADY => microblaze_0_axi_dp_ARREADY(0),
M_AXI_DP_ARVALID => microblaze_0_axi_dp_ARVALID,
M_AXI_DP_AWADDR(31 downto 0) => microblaze_0_axi_dp_AWADDR(31 downto 0),
M_AXI_DP_AWPROT(2 downto 0) => microblaze_0_axi_dp_AWPROT(2 downto 0),
M_AXI_DP_AWREADY => microblaze_0_axi_dp_AWREADY(0),
M_AXI_DP_AWVALID => microblaze_0_axi_dp_AWVALID,
M_AXI_DP_BREADY => microblaze_0_axi_dp_BREADY,
M_AXI_DP_BRESP(1 downto 0) => microblaze_0_axi_dp_BRESP(1 downto 0),
M_AXI_DP_BVALID => microblaze_0_axi_dp_BVALID(0),
M_AXI_DP_RDATA(31 downto 0) => microblaze_0_axi_dp_RDATA(31 downto 0),
M_AXI_DP_RREADY => microblaze_0_axi_dp_RREADY,
M_AXI_DP_RRESP(1 downto 0) => microblaze_0_axi_dp_RRESP(1 downto 0),
M_AXI_DP_RVALID => microblaze_0_axi_dp_RVALID(0),
M_AXI_DP_WDATA(31 downto 0) => microblaze_0_axi_dp_WDATA(31 downto 0),
M_AXI_DP_WREADY => microblaze_0_axi_dp_WREADY(0),
M_AXI_DP_WSTRB(3 downto 0) => microblaze_0_axi_dp_WSTRB(3 downto 0),
M_AXI_DP_WVALID => microblaze_0_axi_dp_WVALID,
M_AXI_IC_ARADDR(31 downto 0) => microblaze_0_M_AXI_IC_ARADDR(31 downto 0),
M_AXI_IC_ARBURST(1 downto 0) => microblaze_0_M_AXI_IC_ARBURST(1 downto 0),
M_AXI_IC_ARCACHE(3 downto 0) => microblaze_0_M_AXI_IC_ARCACHE(3 downto 0),
M_AXI_IC_ARID(0) => NLW_microblaze_0_M_AXI_IC_ARID_UNCONNECTED(0),
M_AXI_IC_ARLEN(7 downto 0) => microblaze_0_M_AXI_IC_ARLEN(7 downto 0),
M_AXI_IC_ARLOCK => microblaze_0_M_AXI_IC_ARLOCK,
M_AXI_IC_ARPROT(2 downto 0) => microblaze_0_M_AXI_IC_ARPROT(2 downto 0),
M_AXI_IC_ARQOS(3 downto 0) => microblaze_0_M_AXI_IC_ARQOS(3 downto 0),
M_AXI_IC_ARREADY => microblaze_0_M_AXI_IC_ARREADY,
M_AXI_IC_ARSIZE(2 downto 0) => microblaze_0_M_AXI_IC_ARSIZE(2 downto 0),
M_AXI_IC_ARVALID => microblaze_0_M_AXI_IC_ARVALID,
M_AXI_IC_AWADDR(31 downto 0) => NLW_microblaze_0_M_AXI_IC_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_IC_AWBURST(1 downto 0) => NLW_microblaze_0_M_AXI_IC_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_IC_AWCACHE(3 downto 0) => NLW_microblaze_0_M_AXI_IC_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_IC_AWID(0) => NLW_microblaze_0_M_AXI_IC_AWID_UNCONNECTED(0),
M_AXI_IC_AWLEN(7 downto 0) => NLW_microblaze_0_M_AXI_IC_AWLEN_UNCONNECTED(7 downto 0),
M_AXI_IC_AWLOCK => NLW_microblaze_0_M_AXI_IC_AWLOCK_UNCONNECTED,
M_AXI_IC_AWPROT(2 downto 0) => NLW_microblaze_0_M_AXI_IC_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_IC_AWQOS(3 downto 0) => NLW_microblaze_0_M_AXI_IC_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_IC_AWREADY => '0',
M_AXI_IC_AWSIZE(2 downto 0) => NLW_microblaze_0_M_AXI_IC_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_IC_AWVALID => NLW_microblaze_0_M_AXI_IC_AWVALID_UNCONNECTED,
M_AXI_IC_BID(0) => '0',
M_AXI_IC_BREADY => NLW_microblaze_0_M_AXI_IC_BREADY_UNCONNECTED,
M_AXI_IC_BRESP(1 downto 0) => B"00",
M_AXI_IC_BVALID => '0',
M_AXI_IC_RDATA(31 downto 0) => microblaze_0_M_AXI_IC_RDATA(31 downto 0),
M_AXI_IC_RID(0) => '0',
M_AXI_IC_RLAST => microblaze_0_M_AXI_IC_RLAST,
M_AXI_IC_RREADY => microblaze_0_M_AXI_IC_RREADY,
M_AXI_IC_RRESP(1 downto 0) => microblaze_0_M_AXI_IC_RRESP(1 downto 0),
M_AXI_IC_RVALID => microblaze_0_M_AXI_IC_RVALID,
M_AXI_IC_WDATA(31 downto 0) => NLW_microblaze_0_M_AXI_IC_WDATA_UNCONNECTED(31 downto 0),
M_AXI_IC_WLAST => NLW_microblaze_0_M_AXI_IC_WLAST_UNCONNECTED,
M_AXI_IC_WREADY => '0',
M_AXI_IC_WSTRB(3 downto 0) => NLW_microblaze_0_M_AXI_IC_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_IC_WVALID => NLW_microblaze_0_M_AXI_IC_WVALID_UNCONNECTED,
Read_Strobe => microblaze_0_dlmb_1_READSTROBE,
Reset => rst_clk_wiz_1_100M_mb_reset,
Write_Strobe => microblaze_0_dlmb_1_WRITESTROBE
);
microblaze_0_axi_intc: component system_microblaze_0_axi_intc_0
port map (
interrupt_address(31 downto 0) => microblaze_0_interrupt_ADDRESS(31 downto 0),
intr(6 downto 0) => microblaze_0_intr(6 downto 0),
irq => microblaze_0_interrupt_INTERRUPT,
processor_ack(1) => microblaze_0_interrupt_ACK(0),
processor_ack(0) => microblaze_0_interrupt_ACK(1),
processor_clk => microblaze_0_Clk,
processor_rst => rst_clk_wiz_1_100M_mb_reset,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_intc_axi_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_intc_axi_ARREADY,
s_axi_arvalid => microblaze_0_intc_axi_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_intc_axi_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_intc_axi_AWREADY,
s_axi_awvalid => microblaze_0_intc_axi_AWVALID(0),
s_axi_bready => microblaze_0_intc_axi_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_intc_axi_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_intc_axi_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_intc_axi_RDATA(31 downto 0),
s_axi_rready => microblaze_0_intc_axi_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_intc_axi_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_intc_axi_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_intc_axi_WDATA(31 downto 0),
s_axi_wready => microblaze_0_intc_axi_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_intc_axi_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_intc_axi_WVALID(0)
);
microblaze_0_axi_periph: entity work.system_microblaze_0_axi_periph_0
port map (
ACLK => microblaze_0_Clk,
ARESETN => rst_clk_wiz_1_100M_interconnect_aresetn(0),
M00_ACLK => microblaze_0_Clk,
M00_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => microblaze_0_intc_axi_ARADDR(31 downto 0),
M00_AXI_arready(0) => microblaze_0_intc_axi_ARREADY,
M00_AXI_arvalid(0) => microblaze_0_intc_axi_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => microblaze_0_intc_axi_AWADDR(31 downto 0),
M00_AXI_awready(0) => microblaze_0_intc_axi_AWREADY,
M00_AXI_awvalid(0) => microblaze_0_intc_axi_AWVALID(0),
M00_AXI_bready(0) => microblaze_0_intc_axi_BREADY(0),
M00_AXI_bresp(1 downto 0) => microblaze_0_intc_axi_BRESP(1 downto 0),
M00_AXI_bvalid(0) => microblaze_0_intc_axi_BVALID,
M00_AXI_rdata(31 downto 0) => microblaze_0_intc_axi_RDATA(31 downto 0),
M00_AXI_rready(0) => microblaze_0_intc_axi_RREADY(0),
M00_AXI_rresp(1 downto 0) => microblaze_0_intc_axi_RRESP(1 downto 0),
M00_AXI_rvalid(0) => microblaze_0_intc_axi_RVALID,
M00_AXI_wdata(31 downto 0) => microblaze_0_intc_axi_WDATA(31 downto 0),
M00_AXI_wready(0) => microblaze_0_intc_axi_WREADY,
M00_AXI_wstrb(3 downto 0) => microblaze_0_intc_axi_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => microblaze_0_intc_axi_WVALID(0),
M01_ACLK => microblaze_0_Clk,
M01_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready(0) => microblaze_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid(0) => microblaze_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready(0) => microblaze_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid(0) => microblaze_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => microblaze_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => microblaze_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => microblaze_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => microblaze_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => microblaze_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid(0) => microblaze_0_axi_periph_M01_AXI_WVALID(0),
M02_ACLK => microblaze_0_Clk,
M02_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready(0) => microblaze_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid(0) => microblaze_0_axi_periph_M02_AXI_ARVALID(0),
M02_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready(0) => microblaze_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid(0) => microblaze_0_axi_periph_M02_AXI_AWVALID(0),
M02_AXI_bready(0) => microblaze_0_axi_periph_M02_AXI_BREADY(0),
M02_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid(0) => microblaze_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready(0) => microblaze_0_axi_periph_M02_AXI_RREADY(0),
M02_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid(0) => microblaze_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready(0) => microblaze_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid(0) => microblaze_0_axi_periph_M02_AXI_WVALID(0),
M03_ACLK => microblaze_0_Clk,
M03_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M03_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arready(0) => microblaze_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid(0) => microblaze_0_axi_periph_M03_AXI_ARVALID(0),
M03_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awready(0) => microblaze_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid(0) => microblaze_0_axi_periph_M03_AXI_AWVALID(0),
M03_AXI_bready(0) => microblaze_0_axi_periph_M03_AXI_BREADY(0),
M03_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid(0) => microblaze_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready(0) => microblaze_0_axi_periph_M03_AXI_RREADY(0),
M03_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid(0) => microblaze_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready(0) => microblaze_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid(0) => microblaze_0_axi_periph_M03_AXI_WVALID(0),
M04_ACLK => microblaze_0_Clk,
M04_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M04_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready(0) => microblaze_0_axi_periph_M04_AXI_ARREADY,
M04_AXI_arvalid(0) => microblaze_0_axi_periph_M04_AXI_ARVALID(0),
M04_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready(0) => microblaze_0_axi_periph_M04_AXI_AWREADY,
M04_AXI_awvalid(0) => microblaze_0_axi_periph_M04_AXI_AWVALID(0),
M04_AXI_bready(0) => microblaze_0_axi_periph_M04_AXI_BREADY(0),
M04_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid(0) => microblaze_0_axi_periph_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready(0) => microblaze_0_axi_periph_M04_AXI_RREADY(0),
M04_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid(0) => microblaze_0_axi_periph_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready(0) => microblaze_0_axi_periph_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid(0) => microblaze_0_axi_periph_M04_AXI_WVALID(0),
M05_ACLK => microblaze_0_Clk,
M05_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M05_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M05_AXI_ARADDR(31 downto 0),
M05_AXI_arready(0) => microblaze_0_axi_periph_M05_AXI_ARREADY,
M05_AXI_arvalid(0) => microblaze_0_axi_periph_M05_AXI_ARVALID(0),
M05_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M05_AXI_AWADDR(31 downto 0),
M05_AXI_awready(0) => microblaze_0_axi_periph_M05_AXI_AWREADY,
M05_AXI_awvalid(0) => microblaze_0_axi_periph_M05_AXI_AWVALID(0),
M05_AXI_bready(0) => microblaze_0_axi_periph_M05_AXI_BREADY(0),
M05_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid(0) => microblaze_0_axi_periph_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready(0) => microblaze_0_axi_periph_M05_AXI_RREADY(0),
M05_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid(0) => microblaze_0_axi_periph_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready(0) => microblaze_0_axi_periph_M05_AXI_WREADY,
M05_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
M05_AXI_wvalid(0) => microblaze_0_axi_periph_M05_AXI_WVALID(0),
M06_ACLK => microblaze_0_Clk,
M06_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M06_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M06_AXI_ARADDR(31 downto 0),
M06_AXI_arready(0) => microblaze_0_axi_periph_M06_AXI_ARREADY,
M06_AXI_arvalid(0) => microblaze_0_axi_periph_M06_AXI_ARVALID(0),
M06_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M06_AXI_AWADDR(31 downto 0),
M06_AXI_awready(0) => microblaze_0_axi_periph_M06_AXI_AWREADY,
M06_AXI_awvalid(0) => microblaze_0_axi_periph_M06_AXI_AWVALID(0),
M06_AXI_bready(0) => microblaze_0_axi_periph_M06_AXI_BREADY(0),
M06_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M06_AXI_BRESP(1 downto 0),
M06_AXI_bvalid(0) => microblaze_0_axi_periph_M06_AXI_BVALID,
M06_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M06_AXI_RDATA(31 downto 0),
M06_AXI_rready(0) => microblaze_0_axi_periph_M06_AXI_RREADY(0),
M06_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M06_AXI_RRESP(1 downto 0),
M06_AXI_rvalid(0) => microblaze_0_axi_periph_M06_AXI_RVALID,
M06_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M06_AXI_WDATA(31 downto 0),
M06_AXI_wready(0) => microblaze_0_axi_periph_M06_AXI_WREADY,
M06_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M06_AXI_WSTRB(3 downto 0),
M06_AXI_wvalid(0) => microblaze_0_axi_periph_M06_AXI_WVALID(0),
M07_ACLK => microblaze_0_Clk,
M07_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M07_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M07_AXI_ARADDR(31 downto 0),
M07_AXI_arready(0) => microblaze_0_axi_periph_M07_AXI_ARREADY,
M07_AXI_arvalid(0) => microblaze_0_axi_periph_M07_AXI_ARVALID(0),
M07_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M07_AXI_AWADDR(31 downto 0),
M07_AXI_awready(0) => microblaze_0_axi_periph_M07_AXI_AWREADY,
M07_AXI_awvalid(0) => microblaze_0_axi_periph_M07_AXI_AWVALID(0),
M07_AXI_bready(0) => microblaze_0_axi_periph_M07_AXI_BREADY(0),
M07_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M07_AXI_BRESP(1 downto 0),
M07_AXI_bvalid(0) => microblaze_0_axi_periph_M07_AXI_BVALID,
M07_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M07_AXI_RDATA(31 downto 0),
M07_AXI_rready(0) => microblaze_0_axi_periph_M07_AXI_RREADY(0),
M07_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M07_AXI_RRESP(1 downto 0),
M07_AXI_rvalid(0) => microblaze_0_axi_periph_M07_AXI_RVALID,
M07_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M07_AXI_WDATA(31 downto 0),
M07_AXI_wready(0) => microblaze_0_axi_periph_M07_AXI_WREADY,
M07_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M07_AXI_WSTRB(3 downto 0),
M07_AXI_wvalid(0) => microblaze_0_axi_periph_M07_AXI_WVALID(0),
M08_ACLK => microblaze_0_Clk,
M08_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M08_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M08_AXI_ARADDR(31 downto 0),
M08_AXI_arready(0) => microblaze_0_axi_periph_M08_AXI_ARREADY,
M08_AXI_arvalid(0) => microblaze_0_axi_periph_M08_AXI_ARVALID(0),
M08_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M08_AXI_AWADDR(31 downto 0),
M08_AXI_awready(0) => microblaze_0_axi_periph_M08_AXI_AWREADY,
M08_AXI_awvalid(0) => microblaze_0_axi_periph_M08_AXI_AWVALID(0),
M08_AXI_bready(0) => microblaze_0_axi_periph_M08_AXI_BREADY(0),
M08_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M08_AXI_BRESP(1 downto 0),
M08_AXI_bvalid(0) => microblaze_0_axi_periph_M08_AXI_BVALID,
M08_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M08_AXI_RDATA(31 downto 0),
M08_AXI_rready(0) => microblaze_0_axi_periph_M08_AXI_RREADY(0),
M08_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M08_AXI_RRESP(1 downto 0),
M08_AXI_rvalid(0) => microblaze_0_axi_periph_M08_AXI_RVALID,
M08_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M08_AXI_WDATA(31 downto 0),
M08_AXI_wready(0) => microblaze_0_axi_periph_M08_AXI_WREADY,
M08_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M08_AXI_WSTRB(3 downto 0),
M08_AXI_wvalid(0) => microblaze_0_axi_periph_M08_AXI_WVALID(0),
M09_ACLK => microblaze_0_Clk,
M09_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M09_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M09_AXI_ARADDR(31 downto 0),
M09_AXI_arready(0) => microblaze_0_axi_periph_M09_AXI_ARREADY,
M09_AXI_arvalid(0) => microblaze_0_axi_periph_M09_AXI_ARVALID(0),
M09_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M09_AXI_AWADDR(31 downto 0),
M09_AXI_awready(0) => microblaze_0_axi_periph_M09_AXI_AWREADY,
M09_AXI_awvalid(0) => microblaze_0_axi_periph_M09_AXI_AWVALID(0),
M09_AXI_bready(0) => microblaze_0_axi_periph_M09_AXI_BREADY(0),
M09_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M09_AXI_BRESP(1 downto 0),
M09_AXI_bvalid(0) => microblaze_0_axi_periph_M09_AXI_BVALID,
M09_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M09_AXI_RDATA(31 downto 0),
M09_AXI_rready(0) => microblaze_0_axi_periph_M09_AXI_RREADY(0),
M09_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M09_AXI_RRESP(1 downto 0),
M09_AXI_rvalid(0) => microblaze_0_axi_periph_M09_AXI_RVALID,
M09_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M09_AXI_WDATA(31 downto 0),
M09_AXI_wready(0) => microblaze_0_axi_periph_M09_AXI_WREADY,
M09_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M09_AXI_WSTRB(3 downto 0),
M09_AXI_wvalid(0) => microblaze_0_axi_periph_M09_AXI_WVALID(0),
M10_ACLK => microblaze_0_Clk,
M10_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M10_AXI_araddr => NLW_microblaze_0_axi_periph_M10_AXI_araddr_UNCONNECTED,
M10_AXI_arprot => NLW_microblaze_0_axi_periph_M10_AXI_arprot_UNCONNECTED,
M10_AXI_arready => '0',
M10_AXI_arvalid => NLW_microblaze_0_axi_periph_M10_AXI_arvalid_UNCONNECTED,
M10_AXI_awaddr => NLW_microblaze_0_axi_periph_M10_AXI_awaddr_UNCONNECTED,
M10_AXI_awprot => NLW_microblaze_0_axi_periph_M10_AXI_awprot_UNCONNECTED,
M10_AXI_awready => '0',
M10_AXI_awvalid => NLW_microblaze_0_axi_periph_M10_AXI_awvalid_UNCONNECTED,
M10_AXI_bready => NLW_microblaze_0_axi_periph_M10_AXI_bready_UNCONNECTED,
M10_AXI_bresp => '0',
M10_AXI_bvalid => '0',
M10_AXI_rdata => '0',
M10_AXI_rready => NLW_microblaze_0_axi_periph_M10_AXI_rready_UNCONNECTED,
M10_AXI_rresp => '0',
M10_AXI_rvalid => '0',
M10_AXI_wdata => NLW_microblaze_0_axi_periph_M10_AXI_wdata_UNCONNECTED,
M10_AXI_wready => '0',
M10_AXI_wstrb => NLW_microblaze_0_axi_periph_M10_AXI_wstrb_UNCONNECTED,
M10_AXI_wvalid => NLW_microblaze_0_axi_periph_M10_AXI_wvalid_UNCONNECTED,
M11_ACLK => microblaze_0_Clk,
M11_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M11_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M11_AXI_ARADDR(31 downto 0),
M11_AXI_arready(0) => microblaze_0_axi_periph_M11_AXI_ARREADY,
M11_AXI_arvalid(0) => microblaze_0_axi_periph_M11_AXI_ARVALID(0),
M11_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M11_AXI_AWADDR(31 downto 0),
M11_AXI_awready(0) => microblaze_0_axi_periph_M11_AXI_AWREADY,
M11_AXI_awvalid(0) => microblaze_0_axi_periph_M11_AXI_AWVALID(0),
M11_AXI_bready(0) => microblaze_0_axi_periph_M11_AXI_BREADY(0),
M11_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M11_AXI_BRESP(1 downto 0),
M11_AXI_bvalid(0) => microblaze_0_axi_periph_M11_AXI_BVALID,
M11_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M11_AXI_RDATA(31 downto 0),
M11_AXI_rready(0) => microblaze_0_axi_periph_M11_AXI_RREADY(0),
M11_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M11_AXI_RRESP(1 downto 0),
M11_AXI_rvalid(0) => microblaze_0_axi_periph_M11_AXI_RVALID,
M11_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M11_AXI_WDATA(31 downto 0),
M11_AXI_wready(0) => microblaze_0_axi_periph_M11_AXI_WREADY,
M11_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M11_AXI_WSTRB(3 downto 0),
M11_AXI_wvalid(0) => microblaze_0_axi_periph_M11_AXI_WVALID(0),
M12_ACLK => microblaze_0_Clk,
M12_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M12_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M12_AXI_ARADDR(31 downto 0),
M12_AXI_arready(0) => microblaze_0_axi_periph_M12_AXI_ARREADY,
M12_AXI_arvalid(0) => microblaze_0_axi_periph_M12_AXI_ARVALID(0),
M12_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M12_AXI_AWADDR(31 downto 0),
M12_AXI_awready(0) => microblaze_0_axi_periph_M12_AXI_AWREADY,
M12_AXI_awvalid(0) => microblaze_0_axi_periph_M12_AXI_AWVALID(0),
M12_AXI_bready(0) => microblaze_0_axi_periph_M12_AXI_BREADY(0),
M12_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M12_AXI_BRESP(1 downto 0),
M12_AXI_bvalid(0) => microblaze_0_axi_periph_M12_AXI_BVALID,
M12_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M12_AXI_RDATA(31 downto 0),
M12_AXI_rready(0) => microblaze_0_axi_periph_M12_AXI_RREADY(0),
M12_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M12_AXI_RRESP(1 downto 0),
M12_AXI_rvalid(0) => microblaze_0_axi_periph_M12_AXI_RVALID,
M12_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M12_AXI_WDATA(31 downto 0),
M12_AXI_wready(0) => microblaze_0_axi_periph_M12_AXI_WREADY,
M12_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M12_AXI_WSTRB(3 downto 0),
M12_AXI_wvalid(0) => microblaze_0_axi_periph_M12_AXI_WVALID(0),
M13_ACLK => mig_7series_0_ui_clk,
M13_ARESETN => rst_mig_7series_0_83M_peripheral_aresetn(0),
M13_AXI_araddr(10 downto 0) => microblaze_0_axi_periph_M13_AXI_ARADDR(10 downto 0),
M13_AXI_arready => microblaze_0_axi_periph_M13_AXI_ARREADY,
M13_AXI_arvalid => microblaze_0_axi_periph_M13_AXI_ARVALID,
M13_AXI_awaddr(10 downto 0) => microblaze_0_axi_periph_M13_AXI_AWADDR(10 downto 0),
M13_AXI_awready => microblaze_0_axi_periph_M13_AXI_AWREADY,
M13_AXI_awvalid => microblaze_0_axi_periph_M13_AXI_AWVALID,
M13_AXI_bready => microblaze_0_axi_periph_M13_AXI_BREADY,
M13_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M13_AXI_BRESP(1 downto 0),
M13_AXI_bvalid => microblaze_0_axi_periph_M13_AXI_BVALID,
M13_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M13_AXI_RDATA(31 downto 0),
M13_AXI_rready => microblaze_0_axi_periph_M13_AXI_RREADY,
M13_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M13_AXI_RRESP(1 downto 0),
M13_AXI_rvalid => microblaze_0_axi_periph_M13_AXI_RVALID,
M13_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M13_AXI_WDATA(31 downto 0),
M13_AXI_wready => microblaze_0_axi_periph_M13_AXI_WREADY,
M13_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M13_AXI_WSTRB(3 downto 0),
M13_AXI_wvalid => microblaze_0_axi_periph_M13_AXI_WVALID,
S00_ACLK => microblaze_0_Clk,
S00_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => microblaze_0_axi_dp_ARADDR(31 downto 0),
S00_AXI_arprot(2 downto 0) => microblaze_0_axi_dp_ARPROT(2 downto 0),
S00_AXI_arready(0) => microblaze_0_axi_dp_ARREADY(0),
S00_AXI_arvalid(0) => microblaze_0_axi_dp_ARVALID,
S00_AXI_awaddr(31 downto 0) => microblaze_0_axi_dp_AWADDR(31 downto 0),
S00_AXI_awprot(2 downto 0) => microblaze_0_axi_dp_AWPROT(2 downto 0),
S00_AXI_awready(0) => microblaze_0_axi_dp_AWREADY(0),
S00_AXI_awvalid(0) => microblaze_0_axi_dp_AWVALID,
S00_AXI_bready(0) => microblaze_0_axi_dp_BREADY,
S00_AXI_bresp(1 downto 0) => microblaze_0_axi_dp_BRESP(1 downto 0),
S00_AXI_bvalid(0) => microblaze_0_axi_dp_BVALID(0),
S00_AXI_rdata(31 downto 0) => microblaze_0_axi_dp_RDATA(31 downto 0),
S00_AXI_rready(0) => microblaze_0_axi_dp_RREADY,
S00_AXI_rresp(1 downto 0) => microblaze_0_axi_dp_RRESP(1 downto 0),
S00_AXI_rvalid(0) => microblaze_0_axi_dp_RVALID(0),
S00_AXI_wdata(31 downto 0) => microblaze_0_axi_dp_WDATA(31 downto 0),
S00_AXI_wready(0) => microblaze_0_axi_dp_WREADY(0),
S00_AXI_wstrb(3 downto 0) => microblaze_0_axi_dp_WSTRB(3 downto 0),
S00_AXI_wvalid(0) => microblaze_0_axi_dp_WVALID
);
microblaze_0_local_memory: entity work.microblaze_0_local_memory_imp_OGE0N8
port map (
DLMB_abus(0 to 31) => microblaze_0_dlmb_1_ABUS(0 to 31),
DLMB_addrstrobe => microblaze_0_dlmb_1_ADDRSTROBE,
DLMB_be(0 to 3) => microblaze_0_dlmb_1_BE(0 to 3),
DLMB_ce => microblaze_0_dlmb_1_CE,
DLMB_readdbus(0 to 31) => microblaze_0_dlmb_1_READDBUS(0 to 31),
DLMB_readstrobe => microblaze_0_dlmb_1_READSTROBE,
DLMB_ready => microblaze_0_dlmb_1_READY,
DLMB_ue => microblaze_0_dlmb_1_UE,
DLMB_wait => microblaze_0_dlmb_1_WAIT,
DLMB_writedbus(0 to 31) => microblaze_0_dlmb_1_WRITEDBUS(0 to 31),
DLMB_writestrobe => microblaze_0_dlmb_1_WRITESTROBE,
ILMB_abus(0 to 31) => microblaze_0_ilmb_1_ABUS(0 to 31),
ILMB_addrstrobe => microblaze_0_ilmb_1_ADDRSTROBE,
ILMB_ce => microblaze_0_ilmb_1_CE,
ILMB_readdbus(0 to 31) => microblaze_0_ilmb_1_READDBUS(0 to 31),
ILMB_readstrobe => microblaze_0_ilmb_1_READSTROBE,
ILMB_ready => microblaze_0_ilmb_1_READY,
ILMB_ue => microblaze_0_ilmb_1_UE,
ILMB_wait => microblaze_0_ilmb_1_WAIT,
LMB_Clk => microblaze_0_Clk,
SYS_Rst(0) => rst_clk_wiz_1_100M_bus_struct_reset(0)
);
microblaze_0_xlconcat: component system_microblaze_0_xlconcat_0
port map (
In0(0) => axi_timer_0_interrupt,
In1(0) => axi_ethernetlite_0_ip2intc_irpt,
In2(0) => axi_iic_0_iic2intc_irpt,
In3(0) => axi_gpio_sw_ip2intc_irpt,
In4(0) => axi_quad_spi_flash_ip2intc_irpt,
In5(0) => axi_quad_spi_shield_ip2intc_irpt,
In6(0) => xadc_wiz_0_ip2intc_irpt,
dout(6 downto 0) => microblaze_0_intr(6 downto 0)
);
mig_7series_0: component system_mig_7series_0_0
port map (
aresetn => rst_mig_7series_0_83M_peripheral_aresetn(0),
clk_ref_i => clk_wiz_1_clk_out3,
ddr3_addr(13 downto 0) => mig_7series_0_DDR3_ADDR(13 downto 0),
ddr3_ba(2 downto 0) => mig_7series_0_DDR3_BA(2 downto 0),
ddr3_cas_n => mig_7series_0_DDR3_CAS_N,
ddr3_ck_n(0) => mig_7series_0_DDR3_CK_N(0),
ddr3_ck_p(0) => mig_7series_0_DDR3_CK_P(0),
ddr3_cke(0) => mig_7series_0_DDR3_CKE(0),
ddr3_cs_n(0) => mig_7series_0_DDR3_CS_N(0),
ddr3_dm(1 downto 0) => mig_7series_0_DDR3_DM(1 downto 0),
ddr3_dq(15 downto 0) => DDR3_dq(15 downto 0),
ddr3_dqs_n(1 downto 0) => DDR3_dqs_n(1 downto 0),
ddr3_dqs_p(1 downto 0) => DDR3_dqs_p(1 downto 0),
ddr3_odt(0) => mig_7series_0_DDR3_ODT(0),
ddr3_ras_n => mig_7series_0_DDR3_RAS_N,
ddr3_reset_n => mig_7series_0_DDR3_RESET_N,
ddr3_we_n => mig_7series_0_DDR3_WE_N,
device_temp_i(11 downto 0) => xadc_wiz_0_temp_out(11 downto 0),
init_calib_complete => NLW_mig_7series_0_init_calib_complete_UNCONNECTED,
mmcm_locked => mig_7series_0_mmcm_locked,
s_axi_araddr(27 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(27 downto 0),
s_axi_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
s_axi_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
s_axi_arlen(7 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(7 downto 0),
s_axi_arlock => axi_mem_intercon_M00_AXI_ARLOCK,
s_axi_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
s_axi_arready => axi_mem_intercon_M00_AXI_ARREADY,
s_axi_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
s_axi_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
s_axi_awaddr(27 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(27 downto 0),
s_axi_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
s_axi_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
s_axi_awlen(7 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(7 downto 0),
s_axi_awlock => axi_mem_intercon_M00_AXI_AWLOCK,
s_axi_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
s_axi_awready => axi_mem_intercon_M00_AXI_AWREADY,
s_axi_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
s_axi_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
s_axi_bid(0) => axi_mem_intercon_M00_AXI_BID(0),
s_axi_bready => axi_mem_intercon_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_mem_intercon_M00_AXI_BVALID,
s_axi_rdata(127 downto 0) => axi_mem_intercon_M00_AXI_RDATA(127 downto 0),
s_axi_rid(0) => axi_mem_intercon_M00_AXI_RID(0),
s_axi_rlast => axi_mem_intercon_M00_AXI_RLAST,
s_axi_rready => axi_mem_intercon_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_mem_intercon_M00_AXI_RVALID,
s_axi_wdata(127 downto 0) => axi_mem_intercon_M00_AXI_WDATA(127 downto 0),
s_axi_wlast => axi_mem_intercon_M00_AXI_WLAST,
s_axi_wready => axi_mem_intercon_M00_AXI_WREADY,
s_axi_wstrb(15 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(15 downto 0),
s_axi_wvalid => axi_mem_intercon_M00_AXI_WVALID,
sys_clk_i => clk_wiz_1_clk_out2,
sys_rst => reset_1,
ui_clk => mig_7series_0_ui_clk,
ui_clk_sync_rst => mig_7series_0_ui_clk_sync_rst
);
rst_clk_wiz_1_100M: component system_rst_clk_wiz_1_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => rst_clk_wiz_1_100M_bus_struct_reset(0),
dcm_locked => clk_wiz_1_locked,
ext_reset_in => reset_1,
interconnect_aresetn(0) => rst_clk_wiz_1_100M_interconnect_aresetn(0),
mb_debug_sys_rst => mdm_1_debug_sys_rst,
mb_reset => rst_clk_wiz_1_100M_mb_reset,
peripheral_aresetn(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_clk_wiz_1_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => microblaze_0_Clk
);
rst_mig_7series_0_83M: component system_rst_mig_7series_0_83M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_mig_7series_0_83M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => mig_7series_0_mmcm_locked,
ext_reset_in => mig_7series_0_ui_clk_sync_rst,
interconnect_aresetn(0) => NLW_rst_mig_7series_0_83M_interconnect_aresetn_UNCONNECTED(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_mig_7series_0_83M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_mig_7series_0_83M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_mig_7series_0_83M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => mig_7series_0_ui_clk
);
xadc_wiz_0: component system_xadc_wiz_0_0
port map (
alarm_out => NLW_xadc_wiz_0_alarm_out_UNCONNECTED,
busy_out => NLW_xadc_wiz_0_busy_out_UNCONNECTED,
channel_out(4 downto 0) => NLW_xadc_wiz_0_channel_out_UNCONNECTED(4 downto 0),
eoc_out => NLW_xadc_wiz_0_eoc_out_UNCONNECTED,
eos_out => NLW_xadc_wiz_0_eos_out_UNCONNECTED,
ip2intc_irpt => xadc_wiz_0_ip2intc_irpt,
s_axi_aclk => mig_7series_0_ui_clk,
s_axi_araddr(10 downto 0) => microblaze_0_axi_periph_M13_AXI_ARADDR(10 downto 0),
s_axi_aresetn => rst_mig_7series_0_83M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M13_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M13_AXI_ARVALID,
s_axi_awaddr(10 downto 0) => microblaze_0_axi_periph_M13_AXI_AWADDR(10 downto 0),
s_axi_awready => microblaze_0_axi_periph_M13_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M13_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M13_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M13_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M13_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M13_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M13_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M13_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M13_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M13_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M13_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M13_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M13_AXI_WVALID,
temp_out(11 downto 0) => xadc_wiz_0_temp_out(11 downto 0),
user_temp_alarm_out => NLW_xadc_wiz_0_user_temp_alarm_out_UNCONNECTED,
vauxn0 => Vaux0_1_V_N,
vauxn1 => Vaux1_1_V_N,
vauxn10 => Vaux10_1_V_N,
vauxn12 => Vaux12_1_V_N,
vauxn13 => Vaux13_1_V_N,
vauxn14 => Vaux14_1_V_N,
vauxn15 => Vaux15_1_V_N,
vauxn2 => Vaux2_1_V_N,
vauxn4 => Vaux4_1_V_N,
vauxn5 => Vaux5_1_V_N,
vauxn6 => Vaux6_1_V_N,
vauxn7 => Vaux7_1_V_N,
vauxn9 => Vaux9_1_V_N,
vauxp0 => Vaux0_1_V_P,
vauxp1 => Vaux1_1_V_P,
vauxp10 => Vaux10_1_V_P,
vauxp12 => Vaux12_1_V_P,
vauxp13 => Vaux13_1_V_P,
vauxp14 => Vaux14_1_V_P,
vauxp15 => Vaux15_1_V_P,
vauxp2 => Vaux2_1_V_P,
vauxp4 => Vaux4_1_V_P,
vauxp5 => Vaux5_1_V_P,
vauxp6 => Vaux6_1_V_P,
vauxp7 => Vaux7_1_V_P,
vauxp9 => Vaux9_1_V_P,
vccaux_alarm_out => NLW_xadc_wiz_0_vccaux_alarm_out_UNCONNECTED,
vccint_alarm_out => NLW_xadc_wiz_0_vccint_alarm_out_UNCONNECTED,
vn_in => Vp_Vn_1_V_N,
vp_in => Vp_Vn_1_V_P
);
end STRUCTURE;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.jtagtst.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : in std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "sram.srec"; -- ram contents
constant sdramfile : string := "sdram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART1 tx data
rxd2 : in std_ulogic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : in std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
can_stb : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_ulogic;
tdo : out std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_ulogic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_ulogic;
signal can_rxd : std_ulogic;
signal can_stb : std_ulogic;
signal spw_clk : std_ulogic := '0';
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal tck, tms, tdi, tdo : std_ulogic;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;
begin
-- clock and reset
spw_clk <= not spw_clk after 20 ns;
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
--## can_rxd <= '1';
can_rxd <= can_txd; -- CAN LOOP BACK ##
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs,
spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, tck, tms, tdi, tdo);
-- optional sdram
sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 /= 0) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sbanks : for k in 0 to srambanks-1 generate
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8),
ramsn(k), rwen(i), ramoen(k));
end generate;
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
jtagproc : process
begin
wait;
jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true);
wait;
end process;
end;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.jtagtst.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : in std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "sram.srec"; -- ram contents
constant sdramfile : string := "sdram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART1 tx data
rxd2 : in std_ulogic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : in std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
can_stb : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_ulogic;
tdo : out std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_ulogic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_ulogic;
signal can_rxd : std_ulogic;
signal can_stb : std_ulogic;
signal spw_clk : std_ulogic := '0';
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal tck, tms, tdi, tdo : std_ulogic;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;
begin
-- clock and reset
spw_clk <= not spw_clk after 20 ns;
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
--## can_rxd <= '1';
can_rxd <= can_txd; -- CAN LOOP BACK ##
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs,
spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, tck, tms, tdi, tdo);
-- optional sdram
sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 /= 0) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sbanks : for k in 0 to srambanks-1 generate
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8),
ramsn(k), rwen(i), ramoen(k));
end generate;
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
jtagproc : process
begin
wait;
jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true);
wait;
end process;
end;
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