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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2234.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02234ent IS
END c07s02b06x00p01n01i02234ent;
ARCHITECTURE c07s02b06x00p01n01i02234arch OF c07s02b06x00p01n01i02234ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
variable k : integer;
BEGIN
k := 4 nm mod 1 A;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02234 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02234arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2234.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02234ent IS
END c07s02b06x00p01n01i02234ent;
ARCHITECTURE c07s02b06x00p01n01i02234arch OF c07s02b06x00p01n01i02234ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
variable k : integer;
BEGIN
k := 4 nm mod 1 A;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02234 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02234arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2234.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02234ent IS
END c07s02b06x00p01n01i02234ent;
ARCHITECTURE c07s02b06x00p01n01i02234arch OF c07s02b06x00p01n01i02234ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
variable k : integer;
BEGIN
k := 4 nm mod 1 A;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02234 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02234arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:10:53 04/11/2016
-- Design Name:
-- Module Name: PCStack - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity PCStack is
generic(PCWIDTH:integer:=16);
Port ( EN : in STD_LOGIC;
OP : in STD_LOGIC;
INADR : in STD_LOGIC_VECTOR (PCWIDTH-1 downto 0);
OUTADR : in STD_LOGIC_VECTOR (PCWIDTH-1 downto 0));
end PCStack;
architecture Behavioral of PCStack is
begin
process(EN)
begin
if(EN = '1') then;
case OP is
when '0' =>
when '1' =>
when OTHERS =>
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:10:53 04/11/2016
-- Design Name:
-- Module Name: PCStack - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity PCStack is
generic(PCWIDTH:integer:=16);
Port ( EN : in STD_LOGIC;
OP : in STD_LOGIC;
INADR : in STD_LOGIC_VECTOR (PCWIDTH-1 downto 0);
OUTADR : in STD_LOGIC_VECTOR (PCWIDTH-1 downto 0));
end PCStack;
architecture Behavioral of PCStack is
begin
process(EN)
begin
if(EN = '1') then;
case OP is
when '0' =>
when '1' =>
when OTHERS =>
end case;
end if;
end process;
end Behavioral;
|
entity wait11 is
end entity;
architecture test of wait11 is
begin
process is
begin
wait for 0.1 ns;
assert now = 100 ps;
wait for 0.5 ns;
assert now = 600 ps;
wait for 1 ns / 10.0;
assert now = 700 ps;
wait for 10 ps * 10.0;
assert now = 800 ps;
wait;
end process;
end architecture;
|
entity wait11 is
end entity;
architecture test of wait11 is
begin
process is
begin
wait for 0.1 ns;
assert now = 100 ps;
wait for 0.5 ns;
assert now = 600 ps;
wait for 1 ns / 10.0;
assert now = 700 ps;
wait for 10 ps * 10.0;
assert now = 800 ps;
wait;
end process;
end architecture;
|
entity wait11 is
end entity;
architecture test of wait11 is
begin
process is
begin
wait for 0.1 ns;
assert now = 100 ps;
wait for 0.5 ns;
assert now = 600 ps;
wait for 1 ns / 10.0;
assert now = 700 ps;
wait for 10 ps * 10.0;
assert now = 800 ps;
wait;
end process;
end architecture;
|
entity wait11 is
end entity;
architecture test of wait11 is
begin
process is
begin
wait for 0.1 ns;
assert now = 100 ps;
wait for 0.5 ns;
assert now = 600 ps;
wait for 1 ns / 10.0;
assert now = 700 ps;
wait for 10 ps * 10.0;
assert now = 800 ps;
wait;
end process;
end architecture;
|
entity wait11 is
end entity;
architecture test of wait11 is
begin
process is
begin
wait for 0.1 ns;
assert now = 100 ps;
wait for 0.5 ns;
assert now = 600 ps;
wait for 1 ns / 10.0;
assert now = 700 ps;
wait for 10 ps * 10.0;
assert now = 800 ps;
wait;
end process;
end architecture;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_sbi;
use bitvis_vip_sbi.sbi_bfm_pkg.all;
library bitvis_vip_gmii;
use bitvis_vip_gmii.gmii_bfm_pkg.all;
library bitvis_vip_ethernet;
use work.ethernet_mac_pkg.all;
--=================================================================================================
-- Test harness entity
--=================================================================================================
entity ethernet_sbi_gmii_demo_th is
generic(
GC_CLK_PERIOD : time
);
end entity ethernet_sbi_gmii_demo_th;
--=================================================================================================
-- Test harness architecture
--=================================================================================================
architecture struct of ethernet_sbi_gmii_demo_th is
-- VVC instance indexes
constant C_VVC_ETH_SBI : natural := 1;
constant C_VVC_SBI : natural := 1;
constant C_VVC_ETH_GMII : natural := 2;
constant C_VVC_GMII : natural := 2;
signal clk : std_logic;
signal sbi_if : t_sbi_if(addr(C_SBI_ADDR_WIDTH-1 downto 0),
wdata(C_SBI_DATA_WIDTH-1 downto 0),
rdata(C_SBI_DATA_WIDTH-1 downto 0));
signal gmii_vvc_tx_if : t_gmii_tx_if;
signal gmii_vvc_rx_if : t_gmii_rx_if;
-- Configuration for the Ethernet MAC field addresses (only applicable for SBI, use default for GMII).
constant C_DUT_IF_FIELD_CONFIG_DIRECTION_ARRAY : t_dut_if_field_config_direction_array(TRANSMIT to RECEIVE)(0 to 5) :=
(TRANSMIT => (0 => (dut_address => C_ETH_ADDR_INVALID, dut_address_increment => 0, data_width => C_SBI_DATA_WIDTH, use_field => false, field_description => "TX Preamble and SFD"),
1 => (dut_address => C_ETH_ADDR_MAC_DEST, dut_address_increment => 0, data_width => C_SBI_DATA_WIDTH, use_field => true, field_description => "TX MAC destination "),
2 => (dut_address => C_ETH_ADDR_MAC_SRC, dut_address_increment => 0, data_width => C_SBI_DATA_WIDTH, use_field => true, field_description => "TX MAC source "),
3 => (dut_address => C_ETH_ADDR_PAY_LEN, dut_address_increment => 0, data_width => C_SBI_DATA_WIDTH, use_field => true, field_description => "TX payload length "),
4 => (dut_address => C_ETH_ADDR_PAYLOAD, dut_address_increment => 0, data_width => C_SBI_DATA_WIDTH, use_field => true, field_description => "TX payload "),
5 => (dut_address => C_ETH_ADDR_INVALID, dut_address_increment => 0, data_width => C_SBI_DATA_WIDTH, use_field => false, field_description => "TX FCS ")),
RECEIVE => (0 => (dut_address => C_ETH_ADDR_INVALID, dut_address_increment => 0, data_width => C_SBI_DATA_WIDTH, use_field => true, field_description => "RX NOT USING ADDR "),
1 => (dut_address => C_ETH_ADDR_INVALID, dut_address_increment => 0, data_width => C_SBI_DATA_WIDTH, use_field => true, field_description => "RX NOT USING ADDR "),
2 => (dut_address => C_ETH_ADDR_INVALID, dut_address_increment => 0, data_width => C_SBI_DATA_WIDTH, use_field => true, field_description => "RX NOT USING ADDR "),
3 => (dut_address => C_ETH_ADDR_INVALID, dut_address_increment => 0, data_width => C_SBI_DATA_WIDTH, use_field => true, field_description => "RX NOT USING ADDR "),
4 => (dut_address => C_ETH_ADDR_INVALID, dut_address_increment => 0, data_width => C_SBI_DATA_WIDTH, use_field => true, field_description => "RX NOT USING ADDR "),
5 => (dut_address => C_ETH_ADDR_INVALID, dut_address_increment => 0, data_width => C_SBI_DATA_WIDTH, use_field => true, field_description => "RX NOT USING ADDR "))
);
begin
------------------------------------------
-- Clock generator
------------------------------------------
p_clk : clock_generator(clk, GC_CLK_PERIOD);
------------------------------------------
-- CPU to MAC interface
------------------------------------------
i1_ethernet_vvc : entity bitvis_vip_ethernet.ethernet_vvc
generic map(
GC_INSTANCE_IDX => C_VVC_ETH_SBI,
GC_PHY_INTERFACE => SBI,
GC_PHY_VVC_INSTANCE_IDX => C_VVC_SBI,
GC_PHY_MAX_ACCESS_TIME => GC_CLK_PERIOD*2, -- add some margin in case of SBI ready low
GC_DUT_IF_FIELD_CONFIG => C_DUT_IF_FIELD_CONFIG_DIRECTION_ARRAY
);
i1_sbi_vvc : entity bitvis_vip_sbi.sbi_vvc
generic map(
GC_ADDR_WIDTH => C_SBI_ADDR_WIDTH,
GC_DATA_WIDTH => C_SBI_DATA_WIDTH,
GC_INSTANCE_IDX => C_VVC_SBI
)
port map(
clk => clk,
sbi_vvc_master_if => sbi_if
);
------------------------------------------
-- Ethernet MAC
------------------------------------------
i_ethernet_mac : entity work.ethernet_mac
port map (
-- SBI interface
clk => clk,
sbi_cs => sbi_if.cs,
sbi_addr => sbi_if.addr,
sbi_rena => sbi_if.rena,
sbi_wena => sbi_if.wena,
sbi_wdata => sbi_if.wdata,
sbi_ready => sbi_if.ready,
sbi_rdata => sbi_if.rdata,
-- GMII interface (only TX)
gtxclk => gmii_vvc_rx_if.rxclk,
txd => gmii_vvc_rx_if.rxd,
txen => gmii_vvc_rx_if.rxdv
);
------------------------------------------
-- MAC to PHY interface
------------------------------------------
i2_ethernet_vvc : entity bitvis_vip_ethernet.ethernet_vvc
generic map(
GC_INSTANCE_IDX => C_VVC_ETH_GMII,
GC_PHY_INTERFACE => GMII,
GC_PHY_VVC_INSTANCE_IDX => C_VVC_GMII,
GC_PHY_MAX_ACCESS_TIME => GC_CLK_PERIOD*4, -- add some margin
GC_DUT_IF_FIELD_CONFIG => C_DUT_IF_FIELD_CONFIG_DIRECTION_ARRAY
);
i2_gmii_vvc : entity bitvis_vip_gmii.gmii_vvc
generic map (
GC_INSTANCE_IDX => C_VVC_GMII
)
port map (
gmii_vvc_tx_if => gmii_vvc_tx_if,
gmii_vvc_rx_if => gmii_vvc_rx_if
);
end architecture struct; |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:52:13 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/scfifo_24in_24out_12kb_synth_1/scfifo_24in_24out_12kb_sim_netlist.vhdl
-- Design : scfifo_24in_24out_12kb
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_blk_mem_gen_prim_wrapper is
port (
D : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end scfifo_24in_24out_12kb_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of scfifo_24in_24out_12kb_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_1\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_8\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_9\ : STD_LOGIC;
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
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INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13 downto 5) => \gc0.count_d1_reg[8]\(8 downto 0),
ADDRARDADDR(4 downto 0) => B"00000",
ADDRBWRADDR(13 downto 5) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ADDRBWRADDR(4 downto 0) => B"00000",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 14) => B"00",
DIADI(13 downto 8) => din(11 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => din(5 downto 0),
DIBDI(15 downto 14) => B"00",
DIBDI(13 downto 8) => din(23 downto 18),
DIBDI(7 downto 6) => B"00",
DIBDI(5 downto 0) => din(17 downto 12),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_0\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_1\,
DOADO(13 downto 8) => D(11 downto 6),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_8\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_9\,
DOADO(5 downto 0) => D(5 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_17\,
DOBDO(13 downto 8) => D(23 downto 18),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_25\,
DOBDO(5 downto 0) => D(17 downto 12),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\,
ENARDEN => tmp_ram_rd_en,
ENBWREN => E(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_compare is
port (
comp0 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_compare : entity is "compare";
end scfifo_24in_24out_12kb_compare;
architecture STRUCTURE of scfifo_24in_24out_12kb_compare is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_d1_reg[8]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_compare_0 : entity is "compare";
end scfifo_24in_24out_12kb_compare_0;
architecture STRUCTURE of scfifo_24in_24out_12kb_compare_0 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_compare_1 is
port (
comp0 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_compare_1 : entity is "compare";
end scfifo_24in_24out_12kb_compare_1;
architecture STRUCTURE of scfifo_24in_24out_12kb_compare_1 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_d1_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_compare_2 is
port (
comp1 : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_compare_2 : entity is "compare";
end scfifo_24in_24out_12kb_compare_2;
architecture STRUCTURE of scfifo_24in_24out_12kb_compare_2 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => \gcc0.gc0.count_d1_reg[6]\(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_rd_bin_cntr is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_comb : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_full_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_fb_i_reg_0 : out STD_LOGIC;
p_18_out : in STD_LOGIC;
comp0_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
comp1_2 : in STD_LOGIC;
p_1_out : in STD_LOGIC;
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
comp0 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_rd_bin_cntr : entity is "rd_bin_cntr";
end scfifo_24in_24out_12kb_rd_bin_cntr;
architecture STRUCTURE of scfifo_24in_24out_12kb_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 8 to 8 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair3";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8 downto 0);
Q(7 downto 0) <= \^q\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \gc0.count[8]_i_2_n_0\,
I1 => \^q\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[8]_i_2_n_0\,
I2 => \^q\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[8]_i_2_n_0\,
I2 => \^q\(6),
I3 => rd_pntr_plus1(8),
O => plusOp(8)
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(8),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(8),
Q => rd_pntr_plus1(8)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I1 => \gcc0.gc0.count_reg[8]\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I3 => \gcc0.gc0.count_reg[8]\(1),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I1 => \gcc0.gc0.count_reg[8]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I3 => \gcc0.gc0.count_reg[8]\(3),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I1 => \gcc0.gc0.count_reg[8]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I3 => \gcc0.gc0.count_reg[8]\(5),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6),
I1 => \gcc0.gc0.count_reg[8]\(6),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7),
I3 => \gcc0.gc0.count_reg[8]\(7),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => ram_full_i_reg(0)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => v1_reg_0(0)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8),
I1 => \gcc0.gc0.count_reg[8]\(8),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => ram_empty_fb_i_reg_0
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FAAA2222FAAAFAAA"
)
port map (
I0 => p_18_out,
I1 => comp0_1,
I2 => E(0),
I3 => comp1_2,
I4 => p_1_out,
I5 => wr_en,
O => ram_empty_fb_i_reg
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000880FFF0088"
)
port map (
I0 => wr_en,
I1 => comp1,
I2 => comp0,
I3 => E(0),
I4 => p_1_out,
I5 => rst_full_gen_i,
O => ram_full_comb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_rd_fwft is
port (
empty : out STD_LOGIC;
valid_fwft : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
\gc0.count_d1_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_bm.dout_i_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_18_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_rd_fwft : entity is "rd_fwft";
end scfifo_24in_24out_12kb_rd_fwft;
architecture STRUCTURE of scfifo_24in_24out_12kb_rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state_reg_n_0_[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^valid_fwft\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair1";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \goreg_bm.dout_i[23]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair0";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
valid_fwft <= \^valid_fwft\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF4555"
)
port map (
I0 => p_18_out,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I4 => Q(0),
O => tmp_ram_rd_en
);
\count[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8788"
)
port map (
I0 => \^valid_fwft\,
I1 => rd_en,
I2 => p_1_out,
I3 => wr_en,
O => E(0)
);
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88EA"
)
port map (
I0 => empty_fwft_fb,
I1 => curr_fwft_state(0),
I2 => rd_en,
I3 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty
);
\gc0.count_d1[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0B0F"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => p_18_out,
I3 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => \gc0.count_d1_reg[8]\(0)
);
\goreg_bm.dout_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => \goreg_bm.dout_i_reg[23]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3B33"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => p_18_out,
I2 => rd_en,
I3 => curr_fwft_state(0),
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(1),
Q => \gpregsm1.curr_fwft_state_reg_n_0_[1]\
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(0),
Q => \^valid_fwft\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_reset_blk_ramfifo is
port (
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end scfifo_24in_24out_12kb_reset_blk_ramfifo;
architecture STRUCTURE of scfifo_24in_24out_12kb_reset_blk_ramfifo is
signal inverted_reset : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
begin
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => inverted_reset,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => inverted_reset,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => inverted_reset
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \scfifo_24in_24out_12kb_reset_blk_ramfifo__parameterized0\ is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \scfifo_24in_24out_12kb_reset_blk_ramfifo__parameterized0\ : entity is "reset_blk_ramfifo";
end \scfifo_24in_24out_12kb_reset_blk_ramfifo__parameterized0\;
architecture STRUCTURE of \scfifo_24in_24out_12kb_reset_blk_ramfifo__parameterized0\ is
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_full_ff_i <= rst_d2;
rst_full_gen_i <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg,
Q => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg,
Q => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => AR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_updn_cntr is
port (
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
valid_fwft : in STD_LOGIC;
rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_updn_cntr : entity is "updn_cntr";
end scfifo_24in_24out_12kb_updn_cntr;
architecture STRUCTURE of scfifo_24in_24out_12kb_updn_cntr is
signal \count[3]_i_2_n_0\ : STD_LOGIC;
signal \count[3]_i_3_n_0\ : STD_LOGIC;
signal \count[3]_i_4_n_0\ : STD_LOGIC;
signal \count[3]_i_5_n_0\ : STD_LOGIC;
signal \count[3]_i_6_n_0\ : STD_LOGIC;
signal \count[7]_i_2_n_0\ : STD_LOGIC;
signal \count[7]_i_3_n_0\ : STD_LOGIC;
signal \count[7]_i_4_n_0\ : STD_LOGIC;
signal \count[7]_i_5_n_0\ : STD_LOGIC;
signal \count[9]_i_3_n_0\ : STD_LOGIC;
signal \count[9]_i_4_n_0\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \count_reg[9]_i_2_n_3\ : STD_LOGIC;
signal \count_reg[9]_i_2_n_6\ : STD_LOGIC;
signal \count_reg[9]_i_2_n_7\ : STD_LOGIC;
signal \count_reg_n_0_[0]\ : STD_LOGIC;
signal \count_reg_n_0_[1]\ : STD_LOGIC;
signal \count_reg_n_0_[2]\ : STD_LOGIC;
signal \count_reg_n_0_[3]\ : STD_LOGIC;
signal \count_reg_n_0_[4]\ : STD_LOGIC;
signal \count_reg_n_0_[5]\ : STD_LOGIC;
signal \count_reg_n_0_[6]\ : STD_LOGIC;
signal \count_reg_n_0_[7]\ : STD_LOGIC;
signal \count_reg_n_0_[8]\ : STD_LOGIC;
signal \^data_count\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_count_reg[9]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_count_reg[9]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \count_reg[3]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \count_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \count_reg[9]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
data_count(0) <= \^data_count\(0);
\count[3]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \count_reg_n_0_[1]\,
O => \count[3]_i_2_n_0\
);
\count[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[2]\,
I1 => \count_reg_n_0_[3]\,
O => \count[3]_i_3_n_0\
);
\count[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[1]\,
I1 => \count_reg_n_0_[2]\,
O => \count[3]_i_4_n_0\
);
\count[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \count_reg_n_0_[1]\,
I1 => valid_fwft,
I2 => rd_en,
O => \count[3]_i_5_n_0\
);
\count[3]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \count_reg_n_0_[0]\,
O => \count[3]_i_6_n_0\
);
\count[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[6]\,
I1 => \count_reg_n_0_[7]\,
O => \count[7]_i_2_n_0\
);
\count[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[5]\,
I1 => \count_reg_n_0_[6]\,
O => \count[7]_i_3_n_0\
);
\count[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[4]\,
I1 => \count_reg_n_0_[5]\,
O => \count[7]_i_4_n_0\
);
\count[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[3]\,
I1 => \count_reg_n_0_[4]\,
O => \count[7]_i_5_n_0\
);
\count[9]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[8]\,
I1 => \^data_count\(0),
O => \count[9]_i_3_n_0\
);
\count[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[7]\,
I1 => \count_reg_n_0_[8]\,
O => \count[9]_i_4_n_0\
);
\count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[3]_i_1_n_7\,
Q => \count_reg_n_0_[0]\
);
\count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[3]_i_1_n_6\,
Q => \count_reg_n_0_[1]\
);
\count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[3]_i_1_n_5\,
Q => \count_reg_n_0_[2]\
);
\count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[3]_i_1_n_4\,
Q => \count_reg_n_0_[3]\
);
\count_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \count_reg[3]_i_1_n_0\,
CO(2) => \count_reg[3]_i_1_n_1\,
CO(1) => \count_reg[3]_i_1_n_2\,
CO(0) => \count_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => \count_reg_n_0_[2]\,
DI(2) => \count_reg_n_0_[1]\,
DI(1) => \count[3]_i_2_n_0\,
DI(0) => \count_reg_n_0_[0]\,
O(3) => \count_reg[3]_i_1_n_4\,
O(2) => \count_reg[3]_i_1_n_5\,
O(1) => \count_reg[3]_i_1_n_6\,
O(0) => \count_reg[3]_i_1_n_7\,
S(3) => \count[3]_i_3_n_0\,
S(2) => \count[3]_i_4_n_0\,
S(1) => \count[3]_i_5_n_0\,
S(0) => \count[3]_i_6_n_0\
);
\count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[7]_i_1_n_7\,
Q => \count_reg_n_0_[4]\
);
\count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[7]_i_1_n_6\,
Q => \count_reg_n_0_[5]\
);
\count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[7]_i_1_n_5\,
Q => \count_reg_n_0_[6]\
);
\count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[7]_i_1_n_4\,
Q => \count_reg_n_0_[7]\
);
\count_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \count_reg[3]_i_1_n_0\,
CO(3) => \count_reg[7]_i_1_n_0\,
CO(2) => \count_reg[7]_i_1_n_1\,
CO(1) => \count_reg[7]_i_1_n_2\,
CO(0) => \count_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \count_reg_n_0_[6]\,
DI(2) => \count_reg_n_0_[5]\,
DI(1) => \count_reg_n_0_[4]\,
DI(0) => \count_reg_n_0_[3]\,
O(3) => \count_reg[7]_i_1_n_4\,
O(2) => \count_reg[7]_i_1_n_5\,
O(1) => \count_reg[7]_i_1_n_6\,
O(0) => \count_reg[7]_i_1_n_7\,
S(3) => \count[7]_i_2_n_0\,
S(2) => \count[7]_i_3_n_0\,
S(1) => \count[7]_i_4_n_0\,
S(0) => \count[7]_i_5_n_0\
);
\count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[9]_i_2_n_7\,
Q => \count_reg_n_0_[8]\
);
\count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[9]_i_2_n_6\,
Q => \^data_count\(0)
);
\count_reg[9]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \count_reg[7]_i_1_n_0\,
CO(3 downto 1) => \NLW_count_reg[9]_i_2_CO_UNCONNECTED\(3 downto 1),
CO(0) => \count_reg[9]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \count_reg_n_0_[7]\,
O(3 downto 2) => \NLW_count_reg[9]_i_2_O_UNCONNECTED\(3 downto 2),
O(1) => \count_reg[9]_i_2_n_6\,
O(0) => \count_reg[9]_i_2_n_7\,
S(3 downto 2) => B"00",
S(1) => \count[9]_i_3_n_0\,
S(0) => \count[9]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_wr_bin_cntr : entity is "wr_bin_cntr";
end scfifo_24in_24out_12kb_wr_bin_cntr;
architecture STRUCTURE of scfifo_24in_24out_12kb_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gcc0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair6";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8 downto 0);
Q(8 downto 0) <= \^q\(8 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \gcc0.gc0.count[8]_i_2_n_0\,
I1 => \^q\(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^q\(6),
I1 => \gcc0.gc0.count[8]_i_2_n_0\,
I2 => \^q\(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \^q\(7),
I1 => \gcc0.gc0.count[8]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gcc0.gc0.count[8]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7)
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => \^q\(4)
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => \^q\(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => \^q\(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => \^q\(7)
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => \^q\(8)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I1 => \gc0.count_d1_reg[7]\(1),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I3 => \gc0.count_d1_reg[7]\(0),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I1 => \gc0.count_d1_reg[7]\(1),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I3 => \gc0.count_d1_reg[7]\(0),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I1 => \gc0.count_reg[7]\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I3 => \gc0.count_reg[7]\(1),
O => ram_empty_fb_i_reg(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I1 => \gc0.count_d1_reg[7]\(3),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I3 => \gc0.count_d1_reg[7]\(2),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I1 => \gc0.count_d1_reg[7]\(3),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I3 => \gc0.count_d1_reg[7]\(2),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I1 => \gc0.count_reg[7]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I3 => \gc0.count_reg[7]\(3),
O => ram_empty_fb_i_reg(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I1 => \gc0.count_d1_reg[7]\(5),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I3 => \gc0.count_d1_reg[7]\(4),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I1 => \gc0.count_d1_reg[7]\(5),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I3 => \gc0.count_d1_reg[7]\(4),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I1 => \gc0.count_reg[7]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I3 => \gc0.count_reg[7]\(5),
O => ram_empty_fb_i_reg(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7),
I1 => \gc0.count_d1_reg[7]\(7),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6),
I3 => \gc0.count_d1_reg[7]\(6),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7),
I1 => \gc0.count_d1_reg[7]\(7),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6),
I3 => \gc0.count_d1_reg[7]\(6),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6),
I1 => \gc0.count_reg[7]\(6),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7),
I3 => \gc0.count_reg[7]\(7),
O => ram_empty_fb_i_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_blk_mem_gen_prim_width is
port (
D : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end scfifo_24in_24out_12kb_blk_mem_gen_prim_width;
architecture STRUCTURE of scfifo_24in_24out_12kb_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.scfifo_24in_24out_12kb_blk_mem_gen_prim_wrapper
port map (
D(23 downto 0) => D(23 downto 0),
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_dc_ss_fwft is
port (
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
valid_fwft : in STD_LOGIC;
rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_dc_ss_fwft : entity is "dc_ss_fwft";
end scfifo_24in_24out_12kb_dc_ss_fwft;
architecture STRUCTURE of scfifo_24in_24out_12kb_dc_ss_fwft is
begin
dc: entity work.scfifo_24in_24out_12kb_updn_cntr
port map (
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
data_count(0) => data_count(0),
rd_en => rd_en,
valid_fwft => valid_fwft
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_rd_status_flags_ss is
port (
comp0 : out STD_LOGIC;
comp1 : out STD_LOGIC;
p_18_out : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_rd_status_flags_ss : entity is "rd_status_flags_ss";
end scfifo_24in_24out_12kb_rd_status_flags_ss;
architecture STRUCTURE of scfifo_24in_24out_12kb_rd_status_flags_ss is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
c1: entity work.scfifo_24in_24out_12kb_compare_1
port map (
comp0 => comp0,
\gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]\,
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0)
);
c2: entity work.scfifo_24in_24out_12kb_compare_2
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[6]\(3 downto 0) => \gcc0.gc0.count_d1_reg[6]\(3 downto 0),
v1_reg(0) => v1_reg(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_wr_status_flags_ss is
port (
comp0 : out STD_LOGIC;
comp1 : out STD_LOGIC;
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_wr_status_flags_ss : entity is "wr_status_flags_ss";
end scfifo_24in_24out_12kb_wr_status_flags_ss;
architecture STRUCTURE of scfifo_24in_24out_12kb_wr_status_flags_ss is
signal \^p_1_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_1_out <= \^p_1_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => E(0)
);
c0: entity work.scfifo_24in_24out_12kb_compare
port map (
comp0 => comp0,
\gc0.count_d1_reg[8]\(0) => \gc0.count_d1_reg[8]\(0),
v1_reg(3 downto 0) => v1_reg(3 downto 0)
);
c1: entity work.scfifo_24in_24out_12kb_compare_0
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => \^p_1_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_blk_mem_gen_generic_cstr is
port (
D : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end scfifo_24in_24out_12kb_blk_mem_gen_generic_cstr;
architecture STRUCTURE of scfifo_24in_24out_12kb_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.scfifo_24in_24out_12kb_blk_mem_gen_prim_width
port map (
D(23 downto 0) => D(23 downto 0),
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_rd_logic is
port (
empty : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : out STD_LOGIC;
\gc0.count_d1_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
comp0 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_rd_logic : entity is "rd_logic";
end scfifo_24in_24out_12kb_rd_logic;
architecture STRUCTURE of scfifo_24in_24out_12kb_rd_logic is
signal \c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 to 4 );
signal cntr_en : STD_LOGIC;
signal comp0_1 : STD_LOGIC;
signal comp1_0 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal rpntr_n_0 : STD_LOGIC;
signal rpntr_n_26 : STD_LOGIC;
signal valid_fwft : STD_LOGIC;
begin
\gr1.gdcf.dc\: entity work.scfifo_24in_24out_12kb_dc_ss_fwft
port map (
E(0) => cntr_en,
Q(0) => Q(1),
clk => clk,
data_count(0) => data_count(0),
rd_en => rd_en,
valid_fwft => valid_fwft
);
\gr1.rfwft\: entity work.scfifo_24in_24out_12kb_rd_fwft
port map (
E(0) => cntr_en,
Q(1 downto 0) => Q(1 downto 0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[8]\(0) => p_14_out,
\goreg_bm.dout_i_reg[23]\(0) => E(0),
p_18_out => p_18_out,
p_1_out => p_1_out,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en,
valid_fwft => valid_fwft,
wr_en => wr_en
);
\grss.rsts\: entity work.scfifo_24in_24out_12kb_rd_status_flags_ss
port map (
Q(0) => Q(1),
clk => clk,
comp0 => comp0_1,
comp1 => comp1_0,
\gc0.count_d1_reg[8]\ => rpntr_n_26,
\gcc0.gc0.count_d1_reg[6]\(3 downto 0) => \gcc0.gc0.count_d1_reg[6]\(3 downto 0),
p_18_out => p_18_out,
ram_empty_fb_i_reg_0 => rpntr_n_0,
v1_reg(0) => \c2/v1_reg\(4),
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0)
);
rpntr: entity work.scfifo_24in_24out_12kb_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0),
E(0) => p_14_out,
Q(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
clk => clk,
comp0 => comp0,
comp0_1 => comp0_1,
comp1 => comp1,
comp1_2 => comp1_0,
\gcc0.gc0.count_d1_reg[8]\(0) => \gcc0.gc0.count_d1_reg[8]\(0),
\gcc0.gc0.count_reg[8]\(8 downto 0) => \gcc0.gc0.count_reg[8]\(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => Q(1),
p_18_out => p_18_out,
p_1_out => p_1_out,
ram_empty_fb_i_reg => rpntr_n_0,
ram_empty_fb_i_reg_0 => rpntr_n_26,
ram_full_comb => ram_full_comb,
ram_full_i_reg(0) => ram_full_i_reg(0),
rst_full_gen_i => rst_full_gen_i,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(0) => \c2/v1_reg\(4),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_wr_logic is
port (
comp0 : out STD_LOGIC;
comp1 : out STD_LOGIC;
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_wr_logic : entity is "wr_logic";
end scfifo_24in_24out_12kb_wr_logic;
architecture STRUCTURE of scfifo_24in_24out_12kb_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
E(0) <= \^e\(0);
\gwss.wsts\: entity work.scfifo_24in_24out_12kb_wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
comp0 => comp0,
comp1 => comp1,
full => full,
\gc0.count_d1_reg[8]\(0) => \gc0.count_d1_reg[8]\(0),
p_1_out => p_1_out,
ram_full_comb => ram_full_comb,
rst_full_ff_i => rst_full_ff_i,
v1_reg(3 downto 0) => \c0/v1_reg\(3 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0),
wr_en => wr_en
);
wpntr: entity work.scfifo_24in_24out_12kb_wr_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0),
E(0) => \^e\(0),
Q(8 downto 0) => Q(8 downto 0),
clk => clk,
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gc0.count_reg[7]\(7 downto 0) => \gc0.count_reg[7]\(7 downto 0),
ram_empty_fb_i_reg(3 downto 0) => ram_empty_fb_i_reg(3 downto 0),
v1_reg(3 downto 0) => v1_reg(3 downto 0),
v1_reg_0(3 downto 0) => \c0/v1_reg\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_blk_mem_gen_top is
port (
D : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_blk_mem_gen_top : entity is "blk_mem_gen_top";
end scfifo_24in_24out_12kb_blk_mem_gen_top;
architecture STRUCTURE of scfifo_24in_24out_12kb_blk_mem_gen_top is
begin
\valid.cstr\: entity work.scfifo_24in_24out_12kb_blk_mem_gen_generic_cstr
port map (
D(23 downto 0) => D(23 downto 0),
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0_synth is
port (
D : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0_synth : entity is "blk_mem_gen_v8_3_0_synth";
end scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0_synth;
architecture STRUCTURE of scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.scfifo_24in_24out_12kb_blk_mem_gen_top
port map (
D(23 downto 0) => D(23 downto 0),
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0 is
port (
D : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0 : entity is "blk_mem_gen_v8_3_0";
end scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0;
architecture STRUCTURE of scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0 is
begin
inst_blk_mem_gen: entity work.scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0_synth
port map (
D(23 downto 0) => D(23 downto 0),
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_memory is
port (
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_memory : entity is "memory";
end scfifo_24in_24out_12kb_memory;
architecture STRUCTURE of scfifo_24in_24out_12kb_memory is
signal doutb : STD_LOGIC_VECTOR ( 23 downto 0 );
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0
port map (
D(23 downto 0) => doutb(23 downto 0),
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
tmp_ram_rd_en => tmp_ram_rd_en
);
\goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(0),
Q => dout(0),
R => Q(0)
);
\goreg_bm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(10),
Q => dout(10),
R => Q(0)
);
\goreg_bm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(11),
Q => dout(11),
R => Q(0)
);
\goreg_bm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(12),
Q => dout(12),
R => Q(0)
);
\goreg_bm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(13),
Q => dout(13),
R => Q(0)
);
\goreg_bm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(14),
Q => dout(14),
R => Q(0)
);
\goreg_bm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(15),
Q => dout(15),
R => Q(0)
);
\goreg_bm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(16),
Q => dout(16),
R => Q(0)
);
\goreg_bm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(17),
Q => dout(17),
R => Q(0)
);
\goreg_bm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(18),
Q => dout(18),
R => Q(0)
);
\goreg_bm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(19),
Q => dout(19),
R => Q(0)
);
\goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(1),
Q => dout(1),
R => Q(0)
);
\goreg_bm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(20),
Q => dout(20),
R => Q(0)
);
\goreg_bm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(21),
Q => dout(21),
R => Q(0)
);
\goreg_bm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(22),
Q => dout(22),
R => Q(0)
);
\goreg_bm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(23),
Q => dout(23),
R => Q(0)
);
\goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(2),
Q => dout(2),
R => Q(0)
);
\goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(3),
Q => dout(3),
R => Q(0)
);
\goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(4),
Q => dout(4),
R => Q(0)
);
\goreg_bm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(5),
Q => dout(5),
R => Q(0)
);
\goreg_bm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(6),
Q => dout(6),
R => Q(0)
);
\goreg_bm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(7),
Q => dout(7),
R => Q(0)
);
\goreg_bm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(8),
Q => dout(8),
R => Q(0)
);
\goreg_bm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(9),
Q => dout(9),
R => Q(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_fifo_generator_ramfifo is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end scfifo_24in_24out_12kb_fifo_generator_ramfifo;
architecture STRUCTURE of scfifo_24in_24out_12kb_fifo_generator_ramfifo is
signal \^rst\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal \grss.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gwss.wsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gwss.wsts/comp0\ : STD_LOGIC;
signal \gwss.wsts/comp1\ : STD_LOGIC;
signal \gwss.wsts/ram_full_comb\ : STD_LOGIC;
signal p_10_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_20_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.scfifo_24in_24out_12kb_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => p_20_out(8 downto 0),
E(0) => p_15_out,
Q(1) => clear,
Q(0) => rd_rst_i(0),
clk => clk,
comp0 => \gwss.wsts/comp0\,
comp1 => \gwss.wsts/comp1\,
data_count(0) => data_count(0),
empty => empty,
\gc0.count_d1_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
\gcc0.gc0.count_d1_reg[6]\(3 downto 0) => \grss.rsts/c2/v1_reg\(3 downto 0),
\gcc0.gc0.count_d1_reg[8]\(0) => p_10_out(8),
\gcc0.gc0.count_reg[8]\(8 downto 0) => p_9_out(8 downto 0),
p_1_out => p_1_out,
ram_full_comb => \gwss.wsts/ram_full_comb\,
ram_full_i_reg(0) => \grss.rsts/c1/v1_reg\(4),
rd_en => rd_en,
rst_full_gen_i => rst_full_gen_i,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => \gwss.wsts/c1/v1_reg\(4 downto 0),
v1_reg_0(3 downto 0) => \grss.rsts/c1/v1_reg\(3 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.scfifo_24in_24out_12kb_wr_logic
port map (
AR(0) => \^rst\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => p_10_out(8 downto 0),
E(0) => p_4_out,
Q(8 downto 0) => p_9_out(8 downto 0),
clk => clk,
comp0 => \gwss.wsts/comp0\,
comp1 => \gwss.wsts/comp1\,
full => full,
\gc0.count_d1_reg[7]\(7 downto 0) => p_20_out(7 downto 0),
\gc0.count_d1_reg[8]\(0) => \grss.rsts/c1/v1_reg\(4),
\gc0.count_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
p_1_out => p_1_out,
ram_empty_fb_i_reg(3 downto 0) => \grss.rsts/c2/v1_reg\(3 downto 0),
ram_full_comb => \gwss.wsts/ram_full_comb\,
rst_full_ff_i => rst_full_ff_i,
v1_reg(3 downto 0) => \grss.rsts/c1/v1_reg\(3 downto 0),
v1_reg_0(4 downto 0) => \gwss.wsts/c1/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.scfifo_24in_24out_12kb_memory
port map (
E(0) => p_4_out,
Q(0) => rd_rst_i(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
dout(23 downto 0) => dout(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => p_20_out(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => p_10_out(8 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\(0) => p_15_out,
tmp_ram_rd_en => tmp_ram_rd_en
);
rstblk: entity work.\scfifo_24in_24out_12kb_reset_blk_ramfifo__parameterized0\
port map (
AR(0) => \^rst\,
Q(1) => clear,
Q(0) => rd_rst_i(0),
clk => clk,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_fifo_generator_top is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_fifo_generator_top : entity is "fifo_generator_top";
end scfifo_24in_24out_12kb_fifo_generator_top;
architecture STRUCTURE of scfifo_24in_24out_12kb_fifo_generator_top is
begin
\grf.rf\: entity work.scfifo_24in_24out_12kb_fifo_generator_ramfifo
port map (
clk => clk,
data_count(0) => data_count(0),
din(23 downto 0) => din(23 downto 0),
dout(23 downto 0) => dout(23 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_fifo_generator_v13_0_0_synth is
port (
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_aclk : in STD_LOGIC;
rst : in STD_LOGIC;
wr_en : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_fifo_generator_v13_0_0_synth : entity is "fifo_generator_v13_0_0_synth";
end scfifo_24in_24out_12kb_fifo_generator_v13_0_0_synth;
architecture STRUCTURE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0_synth is
begin
\gconvfifo.rf\: entity work.scfifo_24in_24out_12kb_fifo_generator_top
port map (
clk => clk,
data_count(0) => data_count(0),
din(23 downto 0) => din(23 downto 0),
dout(23 downto 0) => dout(23 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
\reset_gen_cc.rstblk_cc\: entity work.scfifo_24in_24out_12kb_reset_blk_ramfifo
port map (
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_fifo_generator_v13_0_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 24;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 24;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 511;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 510;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "fifo_generator_v13_0_0";
end scfifo_24in_24out_12kb_fifo_generator_v13_0_0;
architecture STRUCTURE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.scfifo_24in_24out_12kb_fifo_generator_v13_0_0_synth
port map (
clk => clk,
data_count(0) => data_count(0),
din(23 downto 0) => din(23 downto 0),
dout(23 downto 0) => dout(23 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of scfifo_24in_24out_12kb : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of scfifo_24in_24out_12kb : entity is "scfifo_24in_24out_12kb,fifo_generator_v13_0_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of scfifo_24in_24out_12kb : entity is "scfifo_24in_24out_12kb,fifo_generator_v13_0_0,{x_ipProduct=Vivado 2015.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=1,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=24,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=24,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=511,C_PROG_FULL_THRESH_NEGATE_VAL=510,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of scfifo_24in_24out_12kb : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of scfifo_24in_24out_12kb : entity is "fifo_generator_v13_0_0,Vivado 2015.3";
end scfifo_24in_24out_12kb;
architecture STRUCTURE of scfifo_24in_24out_12kb is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 1;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 24;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 24;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 1;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 511;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 510;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of U0 : label is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
begin
U0: entity work.scfifo_24in_24out_12kb_fifo_generator_v13_0_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(0) => data_count(0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(23 downto 0) => din(23 downto 0),
dout(23 downto 0) => dout(23 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(8 downto 0) => B"000000000",
prog_empty_thresh_assert(8 downto 0) => B"000000000",
prog_empty_thresh_negate(8 downto 0) => B"000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(8 downto 0) => B"000000000",
prog_full_thresh_assert(8 downto 0) => B"000000000",
prog_full_thresh_negate(8 downto 0) => B"000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-- Date : Wed Mar 30 14:52:13 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/scfifo_24in_24out_12kb_synth_1/scfifo_24in_24out_12kb_sim_netlist.vhdl
-- Design : scfifo_24in_24out_12kb
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_blk_mem_gen_prim_wrapper is
port (
D : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end scfifo_24in_24out_12kb_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of scfifo_24in_24out_12kb_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_1\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_8\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_9\ : STD_LOGIC;
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13 downto 5) => \gc0.count_d1_reg[8]\(8 downto 0),
ADDRARDADDR(4 downto 0) => B"00000",
ADDRBWRADDR(13 downto 5) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
ADDRBWRADDR(4 downto 0) => B"00000",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 14) => B"00",
DIADI(13 downto 8) => din(11 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => din(5 downto 0),
DIBDI(15 downto 14) => B"00",
DIBDI(13 downto 8) => din(23 downto 18),
DIBDI(7 downto 6) => B"00",
DIBDI(5 downto 0) => din(17 downto 12),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_0\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_1\,
DOADO(13 downto 8) => D(11 downto 6),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_8\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_9\,
DOADO(5 downto 0) => D(5 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_17\,
DOBDO(13 downto 8) => D(23 downto 18),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_25\,
DOBDO(5 downto 0) => D(17 downto 12),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\,
ENARDEN => tmp_ram_rd_en,
ENBWREN => E(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_compare is
port (
comp0 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_compare : entity is "compare";
end scfifo_24in_24out_12kb_compare;
architecture STRUCTURE of scfifo_24in_24out_12kb_compare is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_d1_reg[8]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_compare_0 : entity is "compare";
end scfifo_24in_24out_12kb_compare_0;
architecture STRUCTURE of scfifo_24in_24out_12kb_compare_0 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_compare_1 is
port (
comp0 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_compare_1 : entity is "compare";
end scfifo_24in_24out_12kb_compare_1;
architecture STRUCTURE of scfifo_24in_24out_12kb_compare_1 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_d1_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_compare_2 is
port (
comp1 : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_compare_2 : entity is "compare";
end scfifo_24in_24out_12kb_compare_2;
architecture STRUCTURE of scfifo_24in_24out_12kb_compare_2 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => \gcc0.gc0.count_d1_reg[6]\(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_rd_bin_cntr is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_comb : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_full_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_fb_i_reg_0 : out STD_LOGIC;
p_18_out : in STD_LOGIC;
comp0_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
comp1_2 : in STD_LOGIC;
p_1_out : in STD_LOGIC;
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
comp0 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_rd_bin_cntr : entity is "rd_bin_cntr";
end scfifo_24in_24out_12kb_rd_bin_cntr;
architecture STRUCTURE of scfifo_24in_24out_12kb_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 8 to 8 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair3";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8 downto 0);
Q(7 downto 0) <= \^q\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \gc0.count[8]_i_2_n_0\,
I1 => \^q\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[8]_i_2_n_0\,
I2 => \^q\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[8]_i_2_n_0\,
I2 => \^q\(6),
I3 => rd_pntr_plus1(8),
O => plusOp(8)
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(8),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(8),
Q => rd_pntr_plus1(8)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I1 => \gcc0.gc0.count_reg[8]\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I3 => \gcc0.gc0.count_reg[8]\(1),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I1 => \gcc0.gc0.count_reg[8]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I3 => \gcc0.gc0.count_reg[8]\(3),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I1 => \gcc0.gc0.count_reg[8]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I3 => \gcc0.gc0.count_reg[8]\(5),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6),
I1 => \gcc0.gc0.count_reg[8]\(6),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7),
I3 => \gcc0.gc0.count_reg[8]\(7),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => ram_full_i_reg(0)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => v1_reg_0(0)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8),
I1 => \gcc0.gc0.count_reg[8]\(8),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8),
I1 => \gcc0.gc0.count_d1_reg[8]\(0),
O => ram_empty_fb_i_reg_0
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FAAA2222FAAAFAAA"
)
port map (
I0 => p_18_out,
I1 => comp0_1,
I2 => E(0),
I3 => comp1_2,
I4 => p_1_out,
I5 => wr_en,
O => ram_empty_fb_i_reg
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000880FFF0088"
)
port map (
I0 => wr_en,
I1 => comp1,
I2 => comp0,
I3 => E(0),
I4 => p_1_out,
I5 => rst_full_gen_i,
O => ram_full_comb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_rd_fwft is
port (
empty : out STD_LOGIC;
valid_fwft : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
\gc0.count_d1_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_bm.dout_i_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_18_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_rd_fwft : entity is "rd_fwft";
end scfifo_24in_24out_12kb_rd_fwft;
architecture STRUCTURE of scfifo_24in_24out_12kb_rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state_reg_n_0_[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^valid_fwft\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair1";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \goreg_bm.dout_i[23]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair0";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
valid_fwft <= \^valid_fwft\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF4555"
)
port map (
I0 => p_18_out,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I4 => Q(0),
O => tmp_ram_rd_en
);
\count[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8788"
)
port map (
I0 => \^valid_fwft\,
I1 => rd_en,
I2 => p_1_out,
I3 => wr_en,
O => E(0)
);
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88EA"
)
port map (
I0 => empty_fwft_fb,
I1 => curr_fwft_state(0),
I2 => rd_en,
I3 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty
);
\gc0.count_d1[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0B0F"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => p_18_out,
I3 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => \gc0.count_d1_reg[8]\(0)
);
\goreg_bm.dout_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
O => \goreg_bm.dout_i_reg[23]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3B33"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg_n_0_[1]\,
I1 => p_18_out,
I2 => rd_en,
I3 => curr_fwft_state(0),
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(1),
Q => \gpregsm1.curr_fwft_state_reg_n_0_[1]\
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(0),
Q => \^valid_fwft\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_reset_blk_ramfifo is
port (
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end scfifo_24in_24out_12kb_reset_blk_ramfifo;
architecture STRUCTURE of scfifo_24in_24out_12kb_reset_blk_ramfifo is
signal inverted_reset : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
begin
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => inverted_reset,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => inverted_reset,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => inverted_reset
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \scfifo_24in_24out_12kb_reset_blk_ramfifo__parameterized0\ is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \scfifo_24in_24out_12kb_reset_blk_ramfifo__parameterized0\ : entity is "reset_blk_ramfifo";
end \scfifo_24in_24out_12kb_reset_blk_ramfifo__parameterized0\;
architecture STRUCTURE of \scfifo_24in_24out_12kb_reset_blk_ramfifo__parameterized0\ is
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_full_ff_i <= rst_d2;
rst_full_gen_i <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg,
Q => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg,
Q => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => AR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_updn_cntr is
port (
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
valid_fwft : in STD_LOGIC;
rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_updn_cntr : entity is "updn_cntr";
end scfifo_24in_24out_12kb_updn_cntr;
architecture STRUCTURE of scfifo_24in_24out_12kb_updn_cntr is
signal \count[3]_i_2_n_0\ : STD_LOGIC;
signal \count[3]_i_3_n_0\ : STD_LOGIC;
signal \count[3]_i_4_n_0\ : STD_LOGIC;
signal \count[3]_i_5_n_0\ : STD_LOGIC;
signal \count[3]_i_6_n_0\ : STD_LOGIC;
signal \count[7]_i_2_n_0\ : STD_LOGIC;
signal \count[7]_i_3_n_0\ : STD_LOGIC;
signal \count[7]_i_4_n_0\ : STD_LOGIC;
signal \count[7]_i_5_n_0\ : STD_LOGIC;
signal \count[9]_i_3_n_0\ : STD_LOGIC;
signal \count[9]_i_4_n_0\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \count_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \count_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \count_reg[9]_i_2_n_3\ : STD_LOGIC;
signal \count_reg[9]_i_2_n_6\ : STD_LOGIC;
signal \count_reg[9]_i_2_n_7\ : STD_LOGIC;
signal \count_reg_n_0_[0]\ : STD_LOGIC;
signal \count_reg_n_0_[1]\ : STD_LOGIC;
signal \count_reg_n_0_[2]\ : STD_LOGIC;
signal \count_reg_n_0_[3]\ : STD_LOGIC;
signal \count_reg_n_0_[4]\ : STD_LOGIC;
signal \count_reg_n_0_[5]\ : STD_LOGIC;
signal \count_reg_n_0_[6]\ : STD_LOGIC;
signal \count_reg_n_0_[7]\ : STD_LOGIC;
signal \count_reg_n_0_[8]\ : STD_LOGIC;
signal \^data_count\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_count_reg[9]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_count_reg[9]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \count_reg[3]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \count_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \count_reg[9]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
data_count(0) <= \^data_count\(0);
\count[3]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \count_reg_n_0_[1]\,
O => \count[3]_i_2_n_0\
);
\count[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[2]\,
I1 => \count_reg_n_0_[3]\,
O => \count[3]_i_3_n_0\
);
\count[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[1]\,
I1 => \count_reg_n_0_[2]\,
O => \count[3]_i_4_n_0\
);
\count[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \count_reg_n_0_[1]\,
I1 => valid_fwft,
I2 => rd_en,
O => \count[3]_i_5_n_0\
);
\count[3]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \count_reg_n_0_[0]\,
O => \count[3]_i_6_n_0\
);
\count[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[6]\,
I1 => \count_reg_n_0_[7]\,
O => \count[7]_i_2_n_0\
);
\count[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[5]\,
I1 => \count_reg_n_0_[6]\,
O => \count[7]_i_3_n_0\
);
\count[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[4]\,
I1 => \count_reg_n_0_[5]\,
O => \count[7]_i_4_n_0\
);
\count[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[3]\,
I1 => \count_reg_n_0_[4]\,
O => \count[7]_i_5_n_0\
);
\count[9]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[8]\,
I1 => \^data_count\(0),
O => \count[9]_i_3_n_0\
);
\count[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \count_reg_n_0_[7]\,
I1 => \count_reg_n_0_[8]\,
O => \count[9]_i_4_n_0\
);
\count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[3]_i_1_n_7\,
Q => \count_reg_n_0_[0]\
);
\count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[3]_i_1_n_6\,
Q => \count_reg_n_0_[1]\
);
\count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[3]_i_1_n_5\,
Q => \count_reg_n_0_[2]\
);
\count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[3]_i_1_n_4\,
Q => \count_reg_n_0_[3]\
);
\count_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \count_reg[3]_i_1_n_0\,
CO(2) => \count_reg[3]_i_1_n_1\,
CO(1) => \count_reg[3]_i_1_n_2\,
CO(0) => \count_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => \count_reg_n_0_[2]\,
DI(2) => \count_reg_n_0_[1]\,
DI(1) => \count[3]_i_2_n_0\,
DI(0) => \count_reg_n_0_[0]\,
O(3) => \count_reg[3]_i_1_n_4\,
O(2) => \count_reg[3]_i_1_n_5\,
O(1) => \count_reg[3]_i_1_n_6\,
O(0) => \count_reg[3]_i_1_n_7\,
S(3) => \count[3]_i_3_n_0\,
S(2) => \count[3]_i_4_n_0\,
S(1) => \count[3]_i_5_n_0\,
S(0) => \count[3]_i_6_n_0\
);
\count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[7]_i_1_n_7\,
Q => \count_reg_n_0_[4]\
);
\count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[7]_i_1_n_6\,
Q => \count_reg_n_0_[5]\
);
\count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[7]_i_1_n_5\,
Q => \count_reg_n_0_[6]\
);
\count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[7]_i_1_n_4\,
Q => \count_reg_n_0_[7]\
);
\count_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \count_reg[3]_i_1_n_0\,
CO(3) => \count_reg[7]_i_1_n_0\,
CO(2) => \count_reg[7]_i_1_n_1\,
CO(1) => \count_reg[7]_i_1_n_2\,
CO(0) => \count_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \count_reg_n_0_[6]\,
DI(2) => \count_reg_n_0_[5]\,
DI(1) => \count_reg_n_0_[4]\,
DI(0) => \count_reg_n_0_[3]\,
O(3) => \count_reg[7]_i_1_n_4\,
O(2) => \count_reg[7]_i_1_n_5\,
O(1) => \count_reg[7]_i_1_n_6\,
O(0) => \count_reg[7]_i_1_n_7\,
S(3) => \count[7]_i_2_n_0\,
S(2) => \count[7]_i_3_n_0\,
S(1) => \count[7]_i_4_n_0\,
S(0) => \count[7]_i_5_n_0\
);
\count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[9]_i_2_n_7\,
Q => \count_reg_n_0_[8]\
);
\count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => \count_reg[9]_i_2_n_6\,
Q => \^data_count\(0)
);
\count_reg[9]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \count_reg[7]_i_1_n_0\,
CO(3 downto 1) => \NLW_count_reg[9]_i_2_CO_UNCONNECTED\(3 downto 1),
CO(0) => \count_reg[9]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \count_reg_n_0_[7]\,
O(3 downto 2) => \NLW_count_reg[9]_i_2_O_UNCONNECTED\(3 downto 2),
O(1) => \count_reg[9]_i_2_n_6\,
O(0) => \count_reg[9]_i_2_n_7\,
S(3 downto 2) => B"00",
S(1) => \count[9]_i_3_n_0\,
S(0) => \count[9]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_wr_bin_cntr : entity is "wr_bin_cntr";
end scfifo_24in_24out_12kb_wr_bin_cntr;
architecture STRUCTURE of scfifo_24in_24out_12kb_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gcc0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair6";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8 downto 0);
Q(8 downto 0) <= \^q\(8 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \gcc0.gc0.count[8]_i_2_n_0\,
I1 => \^q\(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^q\(6),
I1 => \gcc0.gc0.count[8]_i_2_n_0\,
I2 => \^q\(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \^q\(7),
I1 => \gcc0.gc0.count[8]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gcc0.gc0.count[8]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7)
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(8)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => \^q\(4)
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => \^q\(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => \^q\(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => \^q\(7)
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => \^q\(8)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I1 => \gc0.count_d1_reg[7]\(1),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I3 => \gc0.count_d1_reg[7]\(0),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I1 => \gc0.count_d1_reg[7]\(1),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I3 => \gc0.count_d1_reg[7]\(0),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I1 => \gc0.count_reg[7]\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I3 => \gc0.count_reg[7]\(1),
O => ram_empty_fb_i_reg(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I1 => \gc0.count_d1_reg[7]\(3),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I3 => \gc0.count_d1_reg[7]\(2),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I1 => \gc0.count_d1_reg[7]\(3),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I3 => \gc0.count_d1_reg[7]\(2),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I1 => \gc0.count_reg[7]\(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I3 => \gc0.count_reg[7]\(3),
O => ram_empty_fb_i_reg(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I1 => \gc0.count_d1_reg[7]\(5),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I3 => \gc0.count_d1_reg[7]\(4),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I1 => \gc0.count_d1_reg[7]\(5),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I3 => \gc0.count_d1_reg[7]\(4),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I1 => \gc0.count_reg[7]\(4),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I3 => \gc0.count_reg[7]\(5),
O => ram_empty_fb_i_reg(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7),
I1 => \gc0.count_d1_reg[7]\(7),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6),
I3 => \gc0.count_d1_reg[7]\(6),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7),
I1 => \gc0.count_d1_reg[7]\(7),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6),
I3 => \gc0.count_d1_reg[7]\(6),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6),
I1 => \gc0.count_reg[7]\(6),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7),
I3 => \gc0.count_reg[7]\(7),
O => ram_empty_fb_i_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_blk_mem_gen_prim_width is
port (
D : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end scfifo_24in_24out_12kb_blk_mem_gen_prim_width;
architecture STRUCTURE of scfifo_24in_24out_12kb_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.scfifo_24in_24out_12kb_blk_mem_gen_prim_wrapper
port map (
D(23 downto 0) => D(23 downto 0),
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_dc_ss_fwft is
port (
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
valid_fwft : in STD_LOGIC;
rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_dc_ss_fwft : entity is "dc_ss_fwft";
end scfifo_24in_24out_12kb_dc_ss_fwft;
architecture STRUCTURE of scfifo_24in_24out_12kb_dc_ss_fwft is
begin
dc: entity work.scfifo_24in_24out_12kb_updn_cntr
port map (
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
data_count(0) => data_count(0),
rd_en => rd_en,
valid_fwft => valid_fwft
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_rd_status_flags_ss is
port (
comp0 : out STD_LOGIC;
comp1 : out STD_LOGIC;
p_18_out : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_rd_status_flags_ss : entity is "rd_status_flags_ss";
end scfifo_24in_24out_12kb_rd_status_flags_ss;
architecture STRUCTURE of scfifo_24in_24out_12kb_rd_status_flags_ss is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
c1: entity work.scfifo_24in_24out_12kb_compare_1
port map (
comp0 => comp0,
\gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]\,
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0)
);
c2: entity work.scfifo_24in_24out_12kb_compare_2
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[6]\(3 downto 0) => \gcc0.gc0.count_d1_reg[6]\(3 downto 0),
v1_reg(0) => v1_reg(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_wr_status_flags_ss is
port (
comp0 : out STD_LOGIC;
comp1 : out STD_LOGIC;
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_wr_status_flags_ss : entity is "wr_status_flags_ss";
end scfifo_24in_24out_12kb_wr_status_flags_ss;
architecture STRUCTURE of scfifo_24in_24out_12kb_wr_status_flags_ss is
signal \^p_1_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_1_out <= \^p_1_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => E(0)
);
c0: entity work.scfifo_24in_24out_12kb_compare
port map (
comp0 => comp0,
\gc0.count_d1_reg[8]\(0) => \gc0.count_d1_reg[8]\(0),
v1_reg(3 downto 0) => v1_reg(3 downto 0)
);
c1: entity work.scfifo_24in_24out_12kb_compare_0
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => \^p_1_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_blk_mem_gen_generic_cstr is
port (
D : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end scfifo_24in_24out_12kb_blk_mem_gen_generic_cstr;
architecture STRUCTURE of scfifo_24in_24out_12kb_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.scfifo_24in_24out_12kb_blk_mem_gen_prim_width
port map (
D(23 downto 0) => D(23 downto 0),
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_rd_logic is
port (
empty : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : out STD_LOGIC;
\gc0.count_d1_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
comp0 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gcc0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_rd_logic : entity is "rd_logic";
end scfifo_24in_24out_12kb_rd_logic;
architecture STRUCTURE of scfifo_24in_24out_12kb_rd_logic is
signal \c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 to 4 );
signal cntr_en : STD_LOGIC;
signal comp0_1 : STD_LOGIC;
signal comp1_0 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal rpntr_n_0 : STD_LOGIC;
signal rpntr_n_26 : STD_LOGIC;
signal valid_fwft : STD_LOGIC;
begin
\gr1.gdcf.dc\: entity work.scfifo_24in_24out_12kb_dc_ss_fwft
port map (
E(0) => cntr_en,
Q(0) => Q(1),
clk => clk,
data_count(0) => data_count(0),
rd_en => rd_en,
valid_fwft => valid_fwft
);
\gr1.rfwft\: entity work.scfifo_24in_24out_12kb_rd_fwft
port map (
E(0) => cntr_en,
Q(1 downto 0) => Q(1 downto 0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[8]\(0) => p_14_out,
\goreg_bm.dout_i_reg[23]\(0) => E(0),
p_18_out => p_18_out,
p_1_out => p_1_out,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en,
valid_fwft => valid_fwft,
wr_en => wr_en
);
\grss.rsts\: entity work.scfifo_24in_24out_12kb_rd_status_flags_ss
port map (
Q(0) => Q(1),
clk => clk,
comp0 => comp0_1,
comp1 => comp1_0,
\gc0.count_d1_reg[8]\ => rpntr_n_26,
\gcc0.gc0.count_d1_reg[6]\(3 downto 0) => \gcc0.gc0.count_d1_reg[6]\(3 downto 0),
p_18_out => p_18_out,
ram_empty_fb_i_reg_0 => rpntr_n_0,
v1_reg(0) => \c2/v1_reg\(4),
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0)
);
rpntr: entity work.scfifo_24in_24out_12kb_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0),
E(0) => p_14_out,
Q(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
clk => clk,
comp0 => comp0,
comp0_1 => comp0_1,
comp1 => comp1,
comp1_2 => comp1_0,
\gcc0.gc0.count_d1_reg[8]\(0) => \gcc0.gc0.count_d1_reg[8]\(0),
\gcc0.gc0.count_reg[8]\(8 downto 0) => \gcc0.gc0.count_reg[8]\(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => Q(1),
p_18_out => p_18_out,
p_1_out => p_1_out,
ram_empty_fb_i_reg => rpntr_n_0,
ram_empty_fb_i_reg_0 => rpntr_n_26,
ram_full_comb => ram_full_comb,
ram_full_i_reg(0) => ram_full_i_reg(0),
rst_full_gen_i => rst_full_gen_i,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(0) => \c2/v1_reg\(4),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_wr_logic is
port (
comp0 : out STD_LOGIC;
comp1 : out STD_LOGIC;
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_wr_logic : entity is "wr_logic";
end scfifo_24in_24out_12kb_wr_logic;
architecture STRUCTURE of scfifo_24in_24out_12kb_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
E(0) <= \^e\(0);
\gwss.wsts\: entity work.scfifo_24in_24out_12kb_wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
comp0 => comp0,
comp1 => comp1,
full => full,
\gc0.count_d1_reg[8]\(0) => \gc0.count_d1_reg[8]\(0),
p_1_out => p_1_out,
ram_full_comb => ram_full_comb,
rst_full_ff_i => rst_full_ff_i,
v1_reg(3 downto 0) => \c0/v1_reg\(3 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0),
wr_en => wr_en
);
wpntr: entity work.scfifo_24in_24out_12kb_wr_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0),
E(0) => \^e\(0),
Q(8 downto 0) => Q(8 downto 0),
clk => clk,
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gc0.count_reg[7]\(7 downto 0) => \gc0.count_reg[7]\(7 downto 0),
ram_empty_fb_i_reg(3 downto 0) => ram_empty_fb_i_reg(3 downto 0),
v1_reg(3 downto 0) => v1_reg(3 downto 0),
v1_reg_0(3 downto 0) => \c0/v1_reg\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_blk_mem_gen_top is
port (
D : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_blk_mem_gen_top : entity is "blk_mem_gen_top";
end scfifo_24in_24out_12kb_blk_mem_gen_top;
architecture STRUCTURE of scfifo_24in_24out_12kb_blk_mem_gen_top is
begin
\valid.cstr\: entity work.scfifo_24in_24out_12kb_blk_mem_gen_generic_cstr
port map (
D(23 downto 0) => D(23 downto 0),
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0_synth is
port (
D : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0_synth : entity is "blk_mem_gen_v8_3_0_synth";
end scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0_synth;
architecture STRUCTURE of scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.scfifo_24in_24out_12kb_blk_mem_gen_top
port map (
D(23 downto 0) => D(23 downto 0),
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0 is
port (
D : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0 : entity is "blk_mem_gen_v8_3_0";
end scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0;
architecture STRUCTURE of scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0 is
begin
inst_blk_mem_gen: entity work.scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0_synth
port map (
D(23 downto 0) => D(23 downto 0),
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_memory is
port (
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_memory : entity is "memory";
end scfifo_24in_24out_12kb_memory;
architecture STRUCTURE of scfifo_24in_24out_12kb_memory is
signal doutb : STD_LOGIC_VECTOR ( 23 downto 0 );
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.scfifo_24in_24out_12kb_blk_mem_gen_v8_3_0
port map (
D(23 downto 0) => doutb(23 downto 0),
E(0) => E(0),
Q(0) => Q(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]\(8 downto 0),
tmp_ram_rd_en => tmp_ram_rd_en
);
\goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(0),
Q => dout(0),
R => Q(0)
);
\goreg_bm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(10),
Q => dout(10),
R => Q(0)
);
\goreg_bm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(11),
Q => dout(11),
R => Q(0)
);
\goreg_bm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(12),
Q => dout(12),
R => Q(0)
);
\goreg_bm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(13),
Q => dout(13),
R => Q(0)
);
\goreg_bm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(14),
Q => dout(14),
R => Q(0)
);
\goreg_bm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(15),
Q => dout(15),
R => Q(0)
);
\goreg_bm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(16),
Q => dout(16),
R => Q(0)
);
\goreg_bm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(17),
Q => dout(17),
R => Q(0)
);
\goreg_bm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(18),
Q => dout(18),
R => Q(0)
);
\goreg_bm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(19),
Q => dout(19),
R => Q(0)
);
\goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(1),
Q => dout(1),
R => Q(0)
);
\goreg_bm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(20),
Q => dout(20),
R => Q(0)
);
\goreg_bm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(21),
Q => dout(21),
R => Q(0)
);
\goreg_bm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(22),
Q => dout(22),
R => Q(0)
);
\goreg_bm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(23),
Q => dout(23),
R => Q(0)
);
\goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(2),
Q => dout(2),
R => Q(0)
);
\goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(3),
Q => dout(3),
R => Q(0)
);
\goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(4),
Q => dout(4),
R => Q(0)
);
\goreg_bm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(5),
Q => dout(5),
R => Q(0)
);
\goreg_bm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(6),
Q => dout(6),
R => Q(0)
);
\goreg_bm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(7),
Q => dout(7),
R => Q(0)
);
\goreg_bm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(8),
Q => dout(8),
R => Q(0)
);
\goreg_bm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
D => doutb(9),
Q => dout(9),
R => Q(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_fifo_generator_ramfifo is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end scfifo_24in_24out_12kb_fifo_generator_ramfifo;
architecture STRUCTURE of scfifo_24in_24out_12kb_fifo_generator_ramfifo is
signal \^rst\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal \grss.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gwss.wsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gwss.wsts/comp0\ : STD_LOGIC;
signal \gwss.wsts/comp1\ : STD_LOGIC;
signal \gwss.wsts/ram_full_comb\ : STD_LOGIC;
signal p_10_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_20_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.scfifo_24in_24out_12kb_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => p_20_out(8 downto 0),
E(0) => p_15_out,
Q(1) => clear,
Q(0) => rd_rst_i(0),
clk => clk,
comp0 => \gwss.wsts/comp0\,
comp1 => \gwss.wsts/comp1\,
data_count(0) => data_count(0),
empty => empty,
\gc0.count_d1_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
\gcc0.gc0.count_d1_reg[6]\(3 downto 0) => \grss.rsts/c2/v1_reg\(3 downto 0),
\gcc0.gc0.count_d1_reg[8]\(0) => p_10_out(8),
\gcc0.gc0.count_reg[8]\(8 downto 0) => p_9_out(8 downto 0),
p_1_out => p_1_out,
ram_full_comb => \gwss.wsts/ram_full_comb\,
ram_full_i_reg(0) => \grss.rsts/c1/v1_reg\(4),
rd_en => rd_en,
rst_full_gen_i => rst_full_gen_i,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => \gwss.wsts/c1/v1_reg\(4 downto 0),
v1_reg_0(3 downto 0) => \grss.rsts/c1/v1_reg\(3 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.scfifo_24in_24out_12kb_wr_logic
port map (
AR(0) => \^rst\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(8 downto 0) => p_10_out(8 downto 0),
E(0) => p_4_out,
Q(8 downto 0) => p_9_out(8 downto 0),
clk => clk,
comp0 => \gwss.wsts/comp0\,
comp1 => \gwss.wsts/comp1\,
full => full,
\gc0.count_d1_reg[7]\(7 downto 0) => p_20_out(7 downto 0),
\gc0.count_d1_reg[8]\(0) => \grss.rsts/c1/v1_reg\(4),
\gc0.count_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
p_1_out => p_1_out,
ram_empty_fb_i_reg(3 downto 0) => \grss.rsts/c2/v1_reg\(3 downto 0),
ram_full_comb => \gwss.wsts/ram_full_comb\,
rst_full_ff_i => rst_full_ff_i,
v1_reg(3 downto 0) => \grss.rsts/c1/v1_reg\(3 downto 0),
v1_reg_0(4 downto 0) => \gwss.wsts/c1/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.scfifo_24in_24out_12kb_memory
port map (
E(0) => p_4_out,
Q(0) => rd_rst_i(0),
clk => clk,
din(23 downto 0) => din(23 downto 0),
dout(23 downto 0) => dout(23 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => p_20_out(8 downto 0),
\gcc0.gc0.count_d1_reg[8]\(8 downto 0) => p_10_out(8 downto 0),
\gpregsm1.curr_fwft_state_reg[0]\(0) => p_15_out,
tmp_ram_rd_en => tmp_ram_rd_en
);
rstblk: entity work.\scfifo_24in_24out_12kb_reset_blk_ramfifo__parameterized0\
port map (
AR(0) => \^rst\,
Q(1) => clear,
Q(0) => rd_rst_i(0),
clk => clk,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_fifo_generator_top is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_fifo_generator_top : entity is "fifo_generator_top";
end scfifo_24in_24out_12kb_fifo_generator_top;
architecture STRUCTURE of scfifo_24in_24out_12kb_fifo_generator_top is
begin
\grf.rf\: entity work.scfifo_24in_24out_12kb_fifo_generator_ramfifo
port map (
clk => clk,
data_count(0) => data_count(0),
din(23 downto 0) => din(23 downto 0),
dout(23 downto 0) => dout(23 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_fifo_generator_v13_0_0_synth is
port (
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_aclk : in STD_LOGIC;
rst : in STD_LOGIC;
wr_en : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_fifo_generator_v13_0_0_synth : entity is "fifo_generator_v13_0_0_synth";
end scfifo_24in_24out_12kb_fifo_generator_v13_0_0_synth;
architecture STRUCTURE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0_synth is
begin
\gconvfifo.rf\: entity work.scfifo_24in_24out_12kb_fifo_generator_top
port map (
clk => clk,
data_count(0) => data_count(0),
din(23 downto 0) => din(23 downto 0),
dout(23 downto 0) => dout(23 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
\reset_gen_cc.rstblk_cc\: entity work.scfifo_24in_24out_12kb_reset_blk_ramfifo
port map (
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb_fifo_generator_v13_0_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 24;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 24;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 511;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 510;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 : entity is "fifo_generator_v13_0_0";
end scfifo_24in_24out_12kb_fifo_generator_v13_0_0;
architecture STRUCTURE of scfifo_24in_24out_12kb_fifo_generator_v13_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.scfifo_24in_24out_12kb_fifo_generator_v13_0_0_synth
port map (
clk => clk,
data_count(0) => data_count(0),
din(23 downto 0) => din(23 downto 0),
dout(23 downto 0) => dout(23 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scfifo_24in_24out_12kb is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 23 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 23 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of scfifo_24in_24out_12kb : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of scfifo_24in_24out_12kb : entity is "scfifo_24in_24out_12kb,fifo_generator_v13_0_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of scfifo_24in_24out_12kb : entity is "scfifo_24in_24out_12kb,fifo_generator_v13_0_0,{x_ipProduct=Vivado 2015.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=1,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=24,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=24,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=511,C_PROG_FULL_THRESH_NEGATE_VAL=510,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of scfifo_24in_24out_12kb : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of scfifo_24in_24out_12kb : entity is "fifo_generator_v13_0_0,Vivado 2015.3";
end scfifo_24in_24out_12kb;
architecture STRUCTURE of scfifo_24in_24out_12kb is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 1;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 24;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 24;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 1;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 511;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 510;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of U0 : label is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
begin
U0: entity work.scfifo_24in_24out_12kb_fifo_generator_v13_0_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(0) => data_count(0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(23 downto 0) => din(23 downto 0),
dout(23 downto 0) => dout(23 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(8 downto 0) => B"000000000",
prog_empty_thresh_assert(8 downto 0) => B"000000000",
prog_empty_thresh_negate(8 downto 0) => B"000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(8 downto 0) => B"000000000",
prog_full_thresh_assert(8 downto 0) => B"000000000",
prog_full_thresh_negate(8 downto 0) => B"000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity select_data is
port(
clk_in : in std_logic;
configuring : in std_logic;
data_acq : in std_logic;
we_data : in std_logic;
we_conf : in std_logic;
daq_data_in : in std_logic_vector(63 downto 0);
conf_data_in : in std_logic_vector(63 downto 0);
data_packet_length : in integer;
conf_packet_length : in integer;
end_packet_conf : in std_logic;
end_packet_daq : in std_logic;
data_out : out std_logic_vector(63 downto 0);
packet_length : out integer;
we : out std_logic;
end_packet : out std_logic
);
end select_data;
architecture Behavioral of select_data is
begin
data_selection : process(clk_in, configuring, data_acq)
begin
if rising_edge(clk_in) then
if configuring = '1' then
we <= we_conf;
data_out <= conf_data_in;
packet_length <= 2;--conf_packet_length;
end_packet <= end_packet_conf;
elsif data_acq = '1' then
we <= we_data;
data_out <= daq_data_in;
packet_length <= data_packet_length;
end_packet <= end_packet_daq;
else
we <= '0';
data_out <= (others => '0');
packet_length <= 0;
end_packet <= '0';
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
-------------------------------------------------------------------------------
-- File : simple_sram.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access sram controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity simple_sram is
generic (
tag_width : integer := 2;
SRAM_Byte_Lanes : integer := 4;
SRAM_Data_Width : integer := 32;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
SRAM_A_Width : integer := 18 );
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
req : in std_logic;
req_tag : in std_logic_vector(1 to tag_width) := (others => '0');
readwriten : in std_logic;
address : in std_logic_vector(SRAM_A_Width-1 downto 0);
rack : out std_logic;
dack : out std_logic;
rack_tag : out std_logic_vector(1 to tag_width);
dack_tag : out std_logic_vector(1 to tag_width);
wdata : in std_logic_vector(SRAM_Data_Width-1 downto 0);
wdata_mask : in std_logic_vector(SRAM_Byte_Lanes-1 downto 0) := (others => '0');
rdata : out std_logic_vector(SRAM_Data_Width-1 downto 0);
--
SRAM_A : out std_logic_vector(SRAM_A_Width-1 downto 0);
SRAM_OEn : out std_logic;
SRAM_WEn : out std_logic;
SRAM_CSn : out std_logic;
SRAM_D : inout std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => 'Z');
SRAM_BEn : out std_logic_vector(SRAM_Byte_Lanes-1 downto 0) );
end simple_sram;
architecture Gideon of simple_sram is
type t_state is (idle, setup, pulse, hold);
signal state : t_state;
signal sram_d_o : std_logic_vector(SRAM_D'range);
signal sram_d_t : std_logic;
signal delay : integer range 0 to 7;
signal rwn_i : std_logic;
signal tag : std_logic_vector(1 to tag_width);
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
process(clock)
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
rdata <= SRAM_D; -- clock in
case state is
when idle =>
if req='1' then
rack <= '1';
rack_tag <= req_tag;
tag <= req_tag;
rwn_i <= readwriten;
SRAM_A <= address;
sram_d_t <= not readwriten;
sram_d_o <= wdata;
if readwriten='0' then -- write
SRAM_BEn <= not wdata_mask;
if SRAM_WR_ASU=0 then
SRAM_WEn <= '0';
state <= pulse;
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
SRAM_BEn <= (others => '0');
if SRAM_RD_ASU=0 then
SRAM_OEn <= '0';
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
end if;
when setup =>
if delay = 1 then
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
SRAM_WEn <= '0';
state <= pulse;
else
delay <= SRAM_RD_Pulse;
SRAM_OEn <= '0';
state <= pulse;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
SRAM_OEn <= '1';
SRAM_WEn <= '1';
dack <= '1';
dack_tag <= tag;
if rwn_i='0' and SRAM_WR_Hold > 1 then
delay <= SRAM_WR_Hold - 1;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 1 then
state <= hold;
delay <= SRAM_RD_Hold - 1;
else
sram_d_t <= '0';
state <= idle;
end if;
else
delay <= delay - 1;
end if;
when hold =>
if delay = 1 then
sram_d_t <= '0';
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if reset='1' then
SRAM_BEn <= (others => '1');
sram_d_o <= (others => '1');
sram_d_t <= '0';
SRAM_OEn <= '1';
SRAM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
end if;
end if;
end process;
SRAM_CSn <= '0';
SRAM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
end Gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
-------------------------------------------------------------------------------
-- File : simple_sram.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access sram controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity simple_sram is
generic (
tag_width : integer := 2;
SRAM_Byte_Lanes : integer := 4;
SRAM_Data_Width : integer := 32;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
SRAM_A_Width : integer := 18 );
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
req : in std_logic;
req_tag : in std_logic_vector(1 to tag_width) := (others => '0');
readwriten : in std_logic;
address : in std_logic_vector(SRAM_A_Width-1 downto 0);
rack : out std_logic;
dack : out std_logic;
rack_tag : out std_logic_vector(1 to tag_width);
dack_tag : out std_logic_vector(1 to tag_width);
wdata : in std_logic_vector(SRAM_Data_Width-1 downto 0);
wdata_mask : in std_logic_vector(SRAM_Byte_Lanes-1 downto 0) := (others => '0');
rdata : out std_logic_vector(SRAM_Data_Width-1 downto 0);
--
SRAM_A : out std_logic_vector(SRAM_A_Width-1 downto 0);
SRAM_OEn : out std_logic;
SRAM_WEn : out std_logic;
SRAM_CSn : out std_logic;
SRAM_D : inout std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => 'Z');
SRAM_BEn : out std_logic_vector(SRAM_Byte_Lanes-1 downto 0) );
end simple_sram;
architecture Gideon of simple_sram is
type t_state is (idle, setup, pulse, hold);
signal state : t_state;
signal sram_d_o : std_logic_vector(SRAM_D'range);
signal sram_d_t : std_logic;
signal delay : integer range 0 to 7;
signal rwn_i : std_logic;
signal tag : std_logic_vector(1 to tag_width);
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
process(clock)
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
rdata <= SRAM_D; -- clock in
case state is
when idle =>
if req='1' then
rack <= '1';
rack_tag <= req_tag;
tag <= req_tag;
rwn_i <= readwriten;
SRAM_A <= address;
sram_d_t <= not readwriten;
sram_d_o <= wdata;
if readwriten='0' then -- write
SRAM_BEn <= not wdata_mask;
if SRAM_WR_ASU=0 then
SRAM_WEn <= '0';
state <= pulse;
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
SRAM_BEn <= (others => '0');
if SRAM_RD_ASU=0 then
SRAM_OEn <= '0';
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
end if;
when setup =>
if delay = 1 then
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
SRAM_WEn <= '0';
state <= pulse;
else
delay <= SRAM_RD_Pulse;
SRAM_OEn <= '0';
state <= pulse;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
SRAM_OEn <= '1';
SRAM_WEn <= '1';
dack <= '1';
dack_tag <= tag;
if rwn_i='0' and SRAM_WR_Hold > 1 then
delay <= SRAM_WR_Hold - 1;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 1 then
state <= hold;
delay <= SRAM_RD_Hold - 1;
else
sram_d_t <= '0';
state <= idle;
end if;
else
delay <= delay - 1;
end if;
when hold =>
if delay = 1 then
sram_d_t <= '0';
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if reset='1' then
SRAM_BEn <= (others => '1');
sram_d_o <= (others => '1');
sram_d_t <= '0';
SRAM_OEn <= '1';
SRAM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
end if;
end if;
end process;
SRAM_CSn <= '0';
SRAM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
end Gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
-------------------------------------------------------------------------------
-- File : simple_sram.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access sram controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity simple_sram is
generic (
tag_width : integer := 2;
SRAM_Byte_Lanes : integer := 4;
SRAM_Data_Width : integer := 32;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
SRAM_A_Width : integer := 18 );
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
req : in std_logic;
req_tag : in std_logic_vector(1 to tag_width) := (others => '0');
readwriten : in std_logic;
address : in std_logic_vector(SRAM_A_Width-1 downto 0);
rack : out std_logic;
dack : out std_logic;
rack_tag : out std_logic_vector(1 to tag_width);
dack_tag : out std_logic_vector(1 to tag_width);
wdata : in std_logic_vector(SRAM_Data_Width-1 downto 0);
wdata_mask : in std_logic_vector(SRAM_Byte_Lanes-1 downto 0) := (others => '0');
rdata : out std_logic_vector(SRAM_Data_Width-1 downto 0);
--
SRAM_A : out std_logic_vector(SRAM_A_Width-1 downto 0);
SRAM_OEn : out std_logic;
SRAM_WEn : out std_logic;
SRAM_CSn : out std_logic;
SRAM_D : inout std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => 'Z');
SRAM_BEn : out std_logic_vector(SRAM_Byte_Lanes-1 downto 0) );
end simple_sram;
architecture Gideon of simple_sram is
type t_state is (idle, setup, pulse, hold);
signal state : t_state;
signal sram_d_o : std_logic_vector(SRAM_D'range);
signal sram_d_t : std_logic;
signal delay : integer range 0 to 7;
signal rwn_i : std_logic;
signal tag : std_logic_vector(1 to tag_width);
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
process(clock)
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
rdata <= SRAM_D; -- clock in
case state is
when idle =>
if req='1' then
rack <= '1';
rack_tag <= req_tag;
tag <= req_tag;
rwn_i <= readwriten;
SRAM_A <= address;
sram_d_t <= not readwriten;
sram_d_o <= wdata;
if readwriten='0' then -- write
SRAM_BEn <= not wdata_mask;
if SRAM_WR_ASU=0 then
SRAM_WEn <= '0';
state <= pulse;
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
SRAM_BEn <= (others => '0');
if SRAM_RD_ASU=0 then
SRAM_OEn <= '0';
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
end if;
when setup =>
if delay = 1 then
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
SRAM_WEn <= '0';
state <= pulse;
else
delay <= SRAM_RD_Pulse;
SRAM_OEn <= '0';
state <= pulse;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
SRAM_OEn <= '1';
SRAM_WEn <= '1';
dack <= '1';
dack_tag <= tag;
if rwn_i='0' and SRAM_WR_Hold > 1 then
delay <= SRAM_WR_Hold - 1;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 1 then
state <= hold;
delay <= SRAM_RD_Hold - 1;
else
sram_d_t <= '0';
state <= idle;
end if;
else
delay <= delay - 1;
end if;
when hold =>
if delay = 1 then
sram_d_t <= '0';
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if reset='1' then
SRAM_BEn <= (others => '1');
sram_d_o <= (others => '1');
sram_d_t <= '0';
SRAM_OEn <= '1';
SRAM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
end if;
end if;
end process;
SRAM_CSn <= '0';
SRAM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
end Gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
-------------------------------------------------------------------------------
-- File : simple_sram.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access sram controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity simple_sram is
generic (
tag_width : integer := 2;
SRAM_Byte_Lanes : integer := 4;
SRAM_Data_Width : integer := 32;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
SRAM_A_Width : integer := 18 );
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
req : in std_logic;
req_tag : in std_logic_vector(1 to tag_width) := (others => '0');
readwriten : in std_logic;
address : in std_logic_vector(SRAM_A_Width-1 downto 0);
rack : out std_logic;
dack : out std_logic;
rack_tag : out std_logic_vector(1 to tag_width);
dack_tag : out std_logic_vector(1 to tag_width);
wdata : in std_logic_vector(SRAM_Data_Width-1 downto 0);
wdata_mask : in std_logic_vector(SRAM_Byte_Lanes-1 downto 0) := (others => '0');
rdata : out std_logic_vector(SRAM_Data_Width-1 downto 0);
--
SRAM_A : out std_logic_vector(SRAM_A_Width-1 downto 0);
SRAM_OEn : out std_logic;
SRAM_WEn : out std_logic;
SRAM_CSn : out std_logic;
SRAM_D : inout std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => 'Z');
SRAM_BEn : out std_logic_vector(SRAM_Byte_Lanes-1 downto 0) );
end simple_sram;
architecture Gideon of simple_sram is
type t_state is (idle, setup, pulse, hold);
signal state : t_state;
signal sram_d_o : std_logic_vector(SRAM_D'range);
signal sram_d_t : std_logic;
signal delay : integer range 0 to 7;
signal rwn_i : std_logic;
signal tag : std_logic_vector(1 to tag_width);
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
process(clock)
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
rdata <= SRAM_D; -- clock in
case state is
when idle =>
if req='1' then
rack <= '1';
rack_tag <= req_tag;
tag <= req_tag;
rwn_i <= readwriten;
SRAM_A <= address;
sram_d_t <= not readwriten;
sram_d_o <= wdata;
if readwriten='0' then -- write
SRAM_BEn <= not wdata_mask;
if SRAM_WR_ASU=0 then
SRAM_WEn <= '0';
state <= pulse;
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
SRAM_BEn <= (others => '0');
if SRAM_RD_ASU=0 then
SRAM_OEn <= '0';
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
end if;
when setup =>
if delay = 1 then
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
SRAM_WEn <= '0';
state <= pulse;
else
delay <= SRAM_RD_Pulse;
SRAM_OEn <= '0';
state <= pulse;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
SRAM_OEn <= '1';
SRAM_WEn <= '1';
dack <= '1';
dack_tag <= tag;
if rwn_i='0' and SRAM_WR_Hold > 1 then
delay <= SRAM_WR_Hold - 1;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 1 then
state <= hold;
delay <= SRAM_RD_Hold - 1;
else
sram_d_t <= '0';
state <= idle;
end if;
else
delay <= delay - 1;
end if;
when hold =>
if delay = 1 then
sram_d_t <= '0';
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if reset='1' then
SRAM_BEn <= (others => '1');
sram_d_o <= (others => '1');
sram_d_t <= '0';
SRAM_OEn <= '1';
SRAM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
end if;
end if;
end process;
SRAM_CSn <= '0';
SRAM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
end Gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
-------------------------------------------------------------------------------
-- File : simple_sram.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access sram controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity simple_sram is
generic (
tag_width : integer := 2;
SRAM_Byte_Lanes : integer := 4;
SRAM_Data_Width : integer := 32;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
SRAM_A_Width : integer := 18 );
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
req : in std_logic;
req_tag : in std_logic_vector(1 to tag_width) := (others => '0');
readwriten : in std_logic;
address : in std_logic_vector(SRAM_A_Width-1 downto 0);
rack : out std_logic;
dack : out std_logic;
rack_tag : out std_logic_vector(1 to tag_width);
dack_tag : out std_logic_vector(1 to tag_width);
wdata : in std_logic_vector(SRAM_Data_Width-1 downto 0);
wdata_mask : in std_logic_vector(SRAM_Byte_Lanes-1 downto 0) := (others => '0');
rdata : out std_logic_vector(SRAM_Data_Width-1 downto 0);
--
SRAM_A : out std_logic_vector(SRAM_A_Width-1 downto 0);
SRAM_OEn : out std_logic;
SRAM_WEn : out std_logic;
SRAM_CSn : out std_logic;
SRAM_D : inout std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => 'Z');
SRAM_BEn : out std_logic_vector(SRAM_Byte_Lanes-1 downto 0) );
end simple_sram;
architecture Gideon of simple_sram is
type t_state is (idle, setup, pulse, hold);
signal state : t_state;
signal sram_d_o : std_logic_vector(SRAM_D'range);
signal sram_d_t : std_logic;
signal delay : integer range 0 to 7;
signal rwn_i : std_logic;
signal tag : std_logic_vector(1 to tag_width);
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
process(clock)
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
rdata <= SRAM_D; -- clock in
case state is
when idle =>
if req='1' then
rack <= '1';
rack_tag <= req_tag;
tag <= req_tag;
rwn_i <= readwriten;
SRAM_A <= address;
sram_d_t <= not readwriten;
sram_d_o <= wdata;
if readwriten='0' then -- write
SRAM_BEn <= not wdata_mask;
if SRAM_WR_ASU=0 then
SRAM_WEn <= '0';
state <= pulse;
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
SRAM_BEn <= (others => '0');
if SRAM_RD_ASU=0 then
SRAM_OEn <= '0';
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
end if;
when setup =>
if delay = 1 then
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
SRAM_WEn <= '0';
state <= pulse;
else
delay <= SRAM_RD_Pulse;
SRAM_OEn <= '0';
state <= pulse;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
SRAM_OEn <= '1';
SRAM_WEn <= '1';
dack <= '1';
dack_tag <= tag;
if rwn_i='0' and SRAM_WR_Hold > 1 then
delay <= SRAM_WR_Hold - 1;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 1 then
state <= hold;
delay <= SRAM_RD_Hold - 1;
else
sram_d_t <= '0';
state <= idle;
end if;
else
delay <= delay - 1;
end if;
when hold =>
if delay = 1 then
sram_d_t <= '0';
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if reset='1' then
SRAM_BEn <= (others => '1');
sram_d_o <= (others => '1');
sram_d_t <= '0';
SRAM_OEn <= '1';
SRAM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
end if;
end if;
end process;
SRAM_CSn <= '0';
SRAM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
end Gideon;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- fifo_in_8b_sync_1.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fifo_in_8b_sync_1 is
port (
byte_en : in std_logic_vector(3 downto 0) := (others => '0'); -- avalon_slave_0.byteenable
in_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(31 downto 0); -- .readdata
rd_en : in std_logic := '0'; -- .read
wait_req : out std_logic; -- .waitrequest
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- .address
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
st_data : in std_logic_vector(7 downto 0) := (others => '0'); -- avalon_streaming_sink.data
st_valid : in std_logic := '0'; -- .valid
st_ready : out std_logic; -- .ready
irq : out std_logic -- conduit_end.export
);
end entity fifo_in_8b_sync_1;
architecture rtl of fifo_in_8b_sync_1 is
component fifo_in_8b_sync is
generic (
FIFO_DEPTH : integer := 16;
BUS_WIDTH : integer := 32
);
port (
byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(31 downto 0); -- readdata
rd_en : in std_logic := 'X'; -- read
wait_req : out std_logic; -- waitrequest
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
st_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
st_valid : in std_logic := 'X'; -- valid
st_ready : out std_logic; -- ready
irq : out std_logic -- export
);
end component fifo_in_8b_sync;
begin
fifo_in_8b_sync_1 : component fifo_in_8b_sync
generic map (
FIFO_DEPTH => 16,
BUS_WIDTH => 32
)
port map (
byte_en => byte_en, -- avalon_slave_0.byteenable
in_data => in_data, -- .writedata
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
rd_en => rd_en, -- .read
wait_req => wait_req, -- .waitrequest
addr => addr, -- .address
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
st_data => st_data, -- avalon_streaming_sink.data
st_valid => st_valid, -- .valid
st_ready => st_ready, -- .ready
irq => irq -- conduit_end.export
);
end architecture rtl; -- of fifo_in_8b_sync_1
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
entity STOP_32b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of STOP_32b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
printmsg("(IMS) STOP_32b : ALLOCATION OK !");
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
process (INPUT_1)
begin
OUTPUT_1 <= INPUT_1;
end process;
-------------------------------------------------------------------------
end;
|
----------------------------------------------------------------------------------
-- Company: PWr
-- Engineer: Kacper Witkowski
-- Module Name: Serializer
-- Project Name: Nadajnik i odbiornik szeregowy z kontrolą poprawności przesyłu CRC16
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.PCK_CRC16_D1.all;
entity serializer is
Port (
parallel_in : in STD_LOGIC_vector(7 downto 0); --dane wejściowe
serial_out : out STD_LOGIC;
serial_in : in std_logic;
clk : in STD_LOGIC;
reset : in STD_LOGIC);
end serializer;
architecture Behavioral of serializer is
signal cnt : std_logic_vector(2 downto 0):= "000"; -- licznik
signal d : std_logic_vector(7 downto 0) := (others => '0'); -- rejestr danych
signal transmission_running : std_logic := '0'; -- czy transmisja działa? generowane po sygnale 0x7e
signal crc_running : std_logic := '0'; -- po przesłaniu całego pakietu kontrolnego, działa crc
signal pckg_cnt : std_logic_vector(4 downto 0) := (others => '0'); --licznik wysłanych pakietów
signal newCRC : std_logic_vector(15 downto 0) := (others => '0'); -- wektor aktualnej wartosci crc
begin
counter : process (reset, clk)
begin
if reset='0' then
cnt <= ( others => '0' );
elsif (clk'event and clk ='1') then
if transmission_running = '1' then
cnt <= cnt + "01"; -- licznik bitów
if cnt = "111" and pckg_cnt = "10010" then -- po wysłaniu wszystkiego wraz z CRC
pckg_cnt <= "00000";
elsif cnt = "111" then
pckg_cnt <= pckg_cnt + "01"; -- licznik bajtów
end if;
end if;
end if;
end process counter;
transmission_control : process(reset, clk, d)
begin
if reset='0' then
transmission_running <= '0';
crc_running <= '0';
elsif clk'event and clk = '1' then
if d = "01111110" or (pckg_cnt = "00000" and serial_in = '1') then -- wystartuj dopiero po 0x7e
transmission_running <= '1';
end if;
if transmission_running = '1' and cnt = "111" and pckg_cnt = "00000" then
crc_running <= '1'; -- zacznij liczyć crc po wysłaniu nagłówka
elsif pckg_cnt = "10001" and cnt = "000" then
crc_running <= '0'; -- skończ liczyć crc po 16 bajtach
elsif (cnt = "111" and pckg_cnt = "10010") then -- zatrzymaj się i wyzeruj crc po wysłaniu wszystkiego
transmission_running <= '0';
end if;
end if;
end process transmission_control;
crc_calc : process(reset, clk)
begin
if clk'event and clk = '1' then
if crc_running = '1' then
newCRC <= nextCRC16(d(7), newCRC); -- obliczanie crc
elsif pckg_cnt = "10010" and cnt = "111" then
newCRC <= (others => '0');
end if;
end if;
end process crc_calc;
piso : process (reset, clk)
begin
if reset='0' then
d <= (others => '0');
elsif (clk'event and clk = '1') then
if cnt = "000" then -- zareaguj dopiero na 0x7e lub potwierdzenie zgodnosci crc
if pckg_cnt = "10001" then
d <= newCRC(14 downto 7); -- wyslij pierwszą połowę crc
elsif pckg_cnt = "10010" then
d <= newCRC(7 downto 0); -- wyślij drugą połowę crc
else
d <= parallel_in; -- wyślij to co na wejściu
end if;
else
d(7 downto 0) <= d(6 downto 0) & '0'; -- rejestr wysyłanych danych
end if;
end if;
end process piso;
serial_out <= d(7); -- wyślij
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : Deadtime generation
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.motor_control_pkg.all;
entity deadtime is
generic (
T_DEAD : natural -- Number of Deadtime cycles
);
port (
in_p : in std_logic;
out_p : out std_logic := '0';
clk : in std_logic
);
end deadtime;
architecture behavioral of deadtime is
signal delay : integer range 0 to T_DEAD - 1 := 0;
begin
process
begin
wait until rising_edge(clk);
if (in_p = '0') then
out_p <= '0';
delay <= 0;
else
if (delay < (T_DEAD - 1)) then
delay <= delay + 1;
else
out_p <= '1';
end if;
end if;
end process;
end behavioral;
|
-------------------------------------------------------------------------------
-- Title : Deadtime generation
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.motor_control_pkg.all;
entity deadtime is
generic (
T_DEAD : natural -- Number of Deadtime cycles
);
port (
in_p : in std_logic;
out_p : out std_logic := '0';
clk : in std_logic
);
end deadtime;
architecture behavioral of deadtime is
signal delay : integer range 0 to T_DEAD - 1 := 0;
begin
process
begin
wait until rising_edge(clk);
if (in_p = '0') then
out_p <= '0';
delay <= 0;
else
if (delay < (T_DEAD - 1)) then
delay <= delay + 1;
else
out_p <= '1';
end if;
end if;
end process;
end behavioral;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:09:13 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_rst_ps7_0_100M_0_stub.vhdl
-- Design : zqynq_lab_1_design_rst_ps7_0_100M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2017.2";
begin
end;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package transaction_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
WRITE, READ, CHECK, RESET, LOCK, UNLOCK);
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 1024;
constant C_VVC_CMD_ADDR_MAX_LENGTH : natural := 64;
constant C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH : natural := 128;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--==========================================================================================
--
-- Transaction info types, constants and global signal
--
--==========================================================================================
-- Transaction status
type t_transaction_status is (INACTIVE, IN_PROGRESS, FAILED, SUCCEEDED);
constant C_TRANSACTION_STATUS_DEFAULT : t_transaction_status := INACTIVE;
-- VVC Meta
type t_vvc_meta is record
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : integer;
end record;
constant C_VVC_META_DEFAULT : t_vvc_meta := (
msg => (others => ' '),
cmd_idx => -1
);
-- Base transaction
type t_base_transaction is record
operation : t_operation;
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
byte_enable : std_logic_vector(C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH-1 downto 0);
vvc_meta : t_vvc_meta;
transaction_status : t_transaction_status;
end record;
constant C_BASE_TRANSACTION_SET_DEFAULT : t_base_transaction := (
operation => NO_OPERATION,
addr => (others => '0'),
data => (others => '0'),
byte_enable => (others => '0'),
vvc_meta => C_VVC_META_DEFAULT,
transaction_status => C_TRANSACTION_STATUS_DEFAULT
);
-- Sub transaction
type t_sub_transaction is record
operation : t_operation;
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
vvc_meta : t_vvc_meta;
transaction_status : t_transaction_status;
end record;
constant C_SUB_TRANSACTION_SET_DEFAULT : t_sub_transaction := (
operation => NO_OPERATION,
addr => (others => '0'),
data => (others => '0'),
vvc_meta => C_VVC_META_DEFAULT,
transaction_status => C_TRANSACTION_STATUS_DEFAULT
);
-- Transaction group
type t_transaction_group is record
bt : t_base_transaction;
st : t_sub_transaction;
end record;
constant C_TRANSACTION_GROUP_DEFAULT : t_transaction_group := (
bt => C_BASE_TRANSACTION_SET_DEFAULT,
st => C_SUB_TRANSACTION_SET_DEFAULT
);
-- Global transaction info trigger signal
type t_avalon_mm_transaction_trigger_array is array (natural range <>) of std_logic;
signal global_avalon_mm_vvc_transaction_trigger : t_avalon_mm_transaction_trigger_array(0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => '0');
-- Type is defined as array to coincide with channel based VVCs
type t_avalon_mm_transaction_group_array is array (natural range <>) of t_transaction_group;
-- Shared transaction info variable
shared variable shared_avalon_mm_vvc_transaction_info : t_avalon_mm_transaction_group_array(0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => C_TRANSACTION_GROUP_DEFAULT);
end package transaction_pkg; |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: txreg_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY txreg_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF txreg_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
QHXZLftMI3X2EADKiowve9cyHRguZaviGrkS9D/PHFJxYfkY/BjBdrkTcWjIW8hORbSWsqiGqZWu
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10112)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10112)
`protect data_block
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/07/2015 10:17:42 PM
-- Design Name:
-- Module Name: Increment16Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Increment16Bit is
Port
(
Input : in BIT_VECTOR(15 downto 0); -- 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(15 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end Increment16Bit;
architecture Behavioral of Increment16Bit is
component RippleCarryAdder8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component RippleCarryAdder8Bit;
signal Carry1 : BIT;
begin
INC_Impl1: RippleCarryAdder8Bit port map (Input(7 downto 0), "00000001", '0', Output(7 downto 0), Carry1);
INC_Impl2: RippleCarryAdder8Bit port map (Input(15 downto 8), "00000000", Carry1, Output(15 downto 8), Cout);
end Behavioral;
|
entity e is
end entity;
architecture a of e is
begin
process is
variable r : real;
variable i : integer;
begin
r := 1.5 * 2; -- OK
r := r * 2; -- Error
r := 6 * 5.15; -- OK
r := i * 1.51; -- Error
r := 62.3 / 6; -- OK
r := 1.51 / i; -- Error
wait;
end process;
end architecture;
|
entity e is
end entity;
architecture a of e is
begin
process is
variable r : real;
variable i : integer;
begin
r := 1.5 * 2; -- OK
r := r * 2; -- Error
r := 6 * 5.15; -- OK
r := i * 1.51; -- Error
r := 62.3 / 6; -- OK
r := 1.51 / i; -- Error
wait;
end process;
end architecture;
|
entity e is
end entity;
architecture a of e is
begin
process is
variable r : real;
variable i : integer;
begin
r := 1.5 * 2; -- OK
r := r * 2; -- Error
r := 6 * 5.15; -- OK
r := i * 1.51; -- Error
r := 62.3 / 6; -- OK
r := 1.51 / i; -- Error
wait;
end process;
end architecture;
|
entity e is
end entity;
architecture a of e is
begin
process is
variable r : real;
variable i : integer;
begin
r := 1.5 * 2; -- OK
r := r * 2; -- Error
r := 6 * 5.15; -- OK
r := i * 1.51; -- Error
r := 62.3 / 6; -- OK
r := 1.51 / i; -- Error
wait;
end process;
end architecture;
|
entity e is
end entity;
architecture a of e is
begin
process is
variable r : real;
variable i : integer;
begin
r := 1.5 * 2; -- OK
r := r * 2; -- Error
r := 6 * 5.15; -- OK
r := i * 1.51; -- Error
r := 62.3 / 6; -- OK
r := 1.51 / i; -- Error
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahbx
-- File: spi2ahbx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- This entity is typically wrapped with spi2ahb or spi2ahb_apb.
-------------------------------------------------------------------------------
--
-- Short core documentation, for additional information see the GRLIB IP
-- Library User's Manual (GRIP):
--
-- The core functions as a SPI memory device. To write to the core, issue the
-- following SPI bus sequence:
--
-- 0. Assert chip select
-- 1. Write instruction
-- 2. Send 32-bit address
-- 3. Send data to be written
-- 4. Deassert chip select
--
-- The core will expect 32-bits of data and write these as a word. This can be
-- changed by writing to the core's control register. See documentation further
-- down. If less than HSIZE bytes are transferred the core will drop the data.
-- After HSIZE bytes has been transferred the core will perform the write to
-- memory. If another byte is received before the core has written its data
-- then the core will discard the current and any following bytes. This
-- condition can be detected by checking the MALFUNCTION bit in the core's
-- status register.
--
-- To read to the core, issue the following SPI bus sequence:
--
-- 0. Assert chip select
-- 1. Send read instruction
-- 2. Send 32-bit address to be used
-- 3. Send dummy byte (depending on read instruction used)
-- 4. Read bytes
-- 5. Deassert chip select
--
-- The core will perform 32-bit data accesses to fill its internal buffer. This
-- can be changed by writing to the core's control register (see documentation
-- further down). If the buffer is empty when the core should return the first
-- byte then the core will return invalid data. This condition can be later
-- detected by checking the MALFUNCTION bit in the core's status register.
-- When the core initiates additional data fetches can be configured via the
-- RAHEAD bit in the control/status register.
--
-- The cores control/status register is read via the RDSR instruction and
-- written via the WRSR instruction.
--
-- +--------+-----------------------------------------------------------------+
-- | Bit(s) | Description |
-- +--------+-----------------------------------------------------------------+
-- | 7 | Reserved, always zero (RO) |
-- | 6 | RAHEAD: Read ahead. When this bit is set the core will make a |
-- | | new access to fetch data as soon as the last current data bit |
-- | | has been moved. Otherwise the core will not attempt the new |
-- | | access until the 'change' transition on SCK. See GRIP doc. for |
-- | | details. Default value is '1'. (RW) |
-- | 5 | PROT: Memory protection triggered. Last access was outside |
-- | | range. Updated after each AMBA access (RO) |
-- | 4 | MEXC: Memory exception. Gets set if core receives AMBA ERROR |
-- | | response. Updated after each AMBA access. (RO) |
-- | 3 | DMAACT: Core is currently performing DMA (RO) |
-- | 2 | MALFUNCTION: Set to 1 if DMA is not finished when new byte |
-- | | starts getting shifted |
-- | 1:0 | HSIZE: Controls the access size core will use for AMBA accesses |
-- | | Default is HSIZE = WORD. HSIZE 11 is illegal (RW) |
-- +--------+-----------------------------------------------------------------+
--
-- Documentation of generics:
--
-- [hindex] AHB master index
--
-- [oepol] Output enable polarity
--
-- [filter] Length of filter used on SCK
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.spi.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity spi2ahbx is
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
--
spi2ahbi : in spi2ahb_in_type;
spi2ahbo : out spi2ahb_out_type
);
end entity spi2ahbx;
architecture rtl of spi2ahbx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OE : std_ulogic := conv_std_logic(oepol = 1);
constant HIZ : std_ulogic := not OE;
-----------------------------------------------------------------------------
-- Instructions
-----------------------------------------------------------------------------
constant RDSR_INST : std_logic_vector(7 downto 0) := X"05";
constant WRSR_INST : std_logic_vector(7 downto 0) := X"01";
constant READ_INST : std_logic_vector(7 downto 0) := X"03";
constant READD_INST : std_logic_vector(7 downto 0) := X"0B"; -- with dummy
constant WRITE_INST : std_logic_vector(7 downto 0) := X"02";
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type state_type is (decode, rdsr, wrsr, addr, dummy, rd, wr, idle, malfunction);
type spi2ahb_reg_type is record
state : state_type;
--
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hsize : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
--
rahead : std_ulogic;
mexc : std_ulogic;
dodma : std_ulogic;
prot : std_ulogic;
malf : std_ulogic;
--
brec : std_ulogic;
rec : std_ulogic;
dummy : std_ulogic;
cnt : std_logic_vector(2 downto 0);
bcnt : std_logic_vector(1 downto 0);
sreg : std_logic_vector(7 downto 0);
miso : std_ulogic;
rdop : std_logic_vector(1 downto 0);
--
misooen : std_ulogic;
sel : std_logic_vector(1 downto 0);
psck : std_ulogic;
sck : std_logic_vector(filter downto 0);
mosi : std_logic_vector(1 downto 0);
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal ami : ahb_dma_in_type;
signal amo : ahb_dma_out_type;
signal r, rin : spi2ahb_reg_type;
begin
-- Generic AHB master interface
ahbmst0 : ahbmst
generic map (hindex => hindex, hirq => 0, venid => VENDOR_GAISLER,
devid => GAISLER_SPI2AHB, version => 0,
chprot => 3, incaddr => 0)
port map (rstn, clk, ami, amo, ahbi, ahbo);
comb: process (r, rstn, spii, amo, spi2ahbi)
variable v : spi2ahb_reg_type;
variable hrdata : std_logic_vector(31 downto 0);
variable ahbreq : std_ulogic;
variable lb : std_ulogic;
variable sample : std_ulogic;
variable change : std_ulogic;
begin
v := r; ahbreq := '0'; lb := '0'; hrdata := (others => '0');
sample := '0'; change := '0'; v.brec := '0';
---------------------------------------------------------------------------
-- Sync input signals
---------------------------------------------------------------------------
v.sel := r.sel(0) & spii.spisel;
v.sck := r.sck(filter-1 downto 0) & spii.sck;
v.mosi := r.mosi(0) & spii.mosi;
---------------------------------------------------------------------------
-- DMA control
---------------------------------------------------------------------------
if r.dodma = '1' then
if amo.active = '1' then
if amo.ready = '1' then
hrdata := ahbreadword(amo.rdata);
case r.hsize is
when "00" =>
v.haddr := r.haddr + 1;
for i in 1 to 3 loop
if i = conv_integer(r.haddr(1 downto 0)) then
hrdata(31 downto 24) := hrdata(31-8*i downto 24-8*i);
end if;
end loop;
when "01" =>
v.haddr := r.haddr + 2;
if r.haddr(1) = '1' then
hrdata(31 downto 16) := hrdata(15 downto 0);
end if;
when others =>
v.haddr := r.haddr + 4;
end case;
v.sreg := hrdata(31 downto 24);
v.hdata(31 downto 8) := hrdata(23 downto 0);
v.mexc := '0';
v.dodma := '0';
end if;
if amo.mexc = '1' then
v.mexc := '1';
v.dodma := '0';
end if;
else
ahbreq := '1';
end if;
end if;
---------------------------------------------------------------------------
-- SPI communication
---------------------------------------------------------------------------
if andv(r.sck(filter downto 1)) = '1' then v.psck := '1'; end if;
if orv(r.sck(filter downto 1)) = '0' then v.psck := '0'; end if;
if (r.psck xor v.psck) = '1' then
if r.psck = conv_std_logic(cpol = 1) then
sample := not conv_std_logic(cpha = 1);
change := conv_std_logic(cpha = 1);
else
sample := conv_std_logic(cpha = 1);
change := not conv_std_logic(cpha = 1);
end if;
end if;
if sample = '1' then
v.cnt := r.cnt + 1;
if r.cnt = "111" then
v.cnt := (others => '0');
v.brec := '1';
end if;
if r.state /= dummy then
v.sreg := r.sreg(6 downto 0) & r.mosi(1);
end if;
end if;
if change = '1' then
v.miso := r.sreg(7);
end if;
---------------------------------------------------------------------------
-- SPI slave control FSM
---------------------------------------------------------------------------
if ((r.hsize = "00") or ((r.hsize(0) and r.bcnt(0)) = '1') or
(r.bcnt = "11")) then
lb := '1';
end if;
case r.state is
when decode =>
if r.brec = '1' then
case r.sreg is
when RDSR_INST =>
v.state := rdsr;
v.sreg := '0' & r.rahead & r.prot & r.mexc &
r.dodma & r.malf & r.hsize;
when WRSR_INST => v.state := wrsr;
when READ_INST | READD_INST=>
v.state := addr; v.rec := '0';
v.dummy := r.sreg(3);
when WRITE_INST => v.state := addr; v.rec := '1';
when others => null;
end case;
end if;
when rdsr =>
if r.brec = '1' then
v.sreg := '0' & r.rahead & r.prot & r.mexc &
r.dodma & r.malf & r.hsize;
end if;
when wrsr =>
if r.brec = '1' then
v.rahead := r.sreg(6);
v.hsize := r.sreg(1 downto 0);
end if;
when addr =>
-- First we need a 4 byte address, then we handle data.
if r.brec = '1' then
if r.dodma = '1' then
v.state := malfunction;
else
v.haddr := r.haddr(23 downto 0) & r.sreg;
end if;
v.bcnt := r.bcnt + 1;
if r.bcnt = "11" then
if r.rec = '1' then
v.state := wr;
else
if r.dummy = '1' then
v.state := dummy;
else
v.state := rd;
end if;
v.malf := '0';
v.dodma := '1';
v.hwrite := '0';
end if;
end if;
end if;
when dummy =>
if r.brec = '1' then
v.state := rd;
end if;
when rd =>
if r.brec = '1' then
v.bcnt := r.bcnt + 1;
v.hdata(31 downto 8) := r.hdata(23 downto 0);
v.sreg := r.hdata(31 downto 24);
if (lb and r.rahead) = '1' then
v.dodma := '1';
v.bcnt := "00";
end if;
v.rdop(0) := lb and not r.rahead;
end if;
if (change and v.dodma) = '1' then
v.state := malfunction;
end if;
-- Without readahead
if orv(r.rdop) = '1' then
if (sample and v.dodma) = '1' then
-- Case is a little tricky. Master may have sampled bad
-- data but we detect the DMA operation as completed.
v.state := malfunction;
end if;
if (r.rdop(0) and change) = '1' then
v.dodma := '1';
v.rdop := "10";
end if;
if (r.dodma and not v.dodma) = '1' then
v.miso := hrdata(31);
v.rdop := (others => '0');
end if;
end if;
when wr =>
if r.brec = '1' then
v.bcnt := r.bcnt + 1;
if v.dodma = '0' then
if r.bcnt = "00" then v.hdata(31 downto 24) := r.sreg; end if;
if r.bcnt(1) = '0' then v.hdata(23 downto 16) := r.sreg; end if;
if r.bcnt(0) = '0' then v.hdata(15 downto 8) := r.sreg; end if;
v.hdata(7 downto 0) := r.sreg;
if lb = '1' then v.dodma := '1'; v.hwrite := '1'; v.malf := '0'; end if;
else
v.state := malfunction;
end if;
end if;
when idle =>
if r.sel(1) = '0' then
v.state := decode;
v.misooen := OE;
v.cnt := (others => '0');
v.bcnt := (others => '0');
end if;
when malfunction =>
v.malf := '1';
end case;
if r.state /= rd then v.rdop := (others => '0'); end if;
if spi2ahbi.hmask /= zero32 then
if v.dodma = '1' then
if ((spi2ahbi.haddr xor r.haddr) and spi2ahbi.hmask) /= zero32 then
v.dodma := '0';
v.prot := '1';
v.state := idle;
else
v.prot := '0';
end if;
end if;
else
v.prot := '0';
end if;
if spi2ahbi.en = '1' then
if r.sel(1) = '1' then
v.state := idle;
v.misooen := HIZ;
end if;
else
v.state := idle;
v.misooen := HIZ;
end if;
----------------------------------------------------------------------------
-- Reset
----------------------------------------------------------------------------
if rstn = '0' then
v.state := idle;
v.haddr := (others => '0');
v.hdata := (others => '0');
v.hsize := HSIZE_WORD(1 downto 0);
v.rahead := '1';
v.mexc := '0';
v.dodma := '0';
v.prot := '0';
v.malf := '0';
v.psck := conv_std_logic(cpol = 1);
v.miso := '1';
v.misooen := HIZ;
end if;
if spi2ahbi.hmask = zero32 then v.prot := '0'; end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB master control
ami.address <= r.haddr;
ami.wdata <= ahbdrivedata(r.hdata);
ami.start <= ahbreq;
ami.burst <= '0';
ami.write <= r.hwrite;
ami.busy <= '0';
ami.irq <= '0';
ami.size <= '0' & r.hsize;
-- Update outputs
spi2ahbo.dma <= r.dodma;
spi2ahbo.wr <= r.hwrite;
spi2ahbo.prot <= r.prot;
-- Several unused here..
spio.miso <= r.miso;
spio.misooen <= r.misooen;
spio.mosi <= '0';
spio.mosioen <= HIZ;
spio.sck <= '0';
spio.sckoen <= HIZ;
spio.ssn <= (others => '0');
spio.enable <= spi2ahbi.en;
spio.astart <= '0';
end process comb;
reg: process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map ("spi2ahb" & tost(hindex) & ": SPI to AHB bridge");
-- pragma translate_on
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNXGQJH2DS is
function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate;
constant cPERIOD : time := 7.499999999999999 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNXGQJH2DS is
function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate;
constant cPERIOD : time := 7.499999999999999 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNXGQJH2DS is
function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate;
constant cPERIOD : time := 7.499999999999999 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNXGQJH2DS is
function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate;
constant cPERIOD : time := 7.499999999999999 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNXGQJH2DS is
function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate;
constant cPERIOD : time := 7.499999999999999 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNXGQJH2DS is
function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate;
constant cPERIOD : time := 7.499999999999999 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNXGQJH2DS is
function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate;
constant cPERIOD : time := 7.499999999999999 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNXGQJH2DS is
function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate;
constant cPERIOD : time := 7.499999999999999 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNXGQJH2DS is
function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate;
constant cPERIOD : time := 7.499999999999999 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNXGQJH2DS is
function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate;
constant cPERIOD : time := 7.499999999999999 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture; |
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 21.11.2013 14:22:20
-- Design Name: rx_path_lookup_memory.vhd
-- Module Name: rx_path_lookup_memory - structural
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: this module contains the lookup memory
-- for details on the lookup memory and search process see switch_port_rxpath_lookup_memory.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rx_path_lookup_memory is
Generic (
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer
);
Port (
--Port A -> Processor
mem_in_wenable : in std_logic_vector;
mem_in_addr : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_in_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
mem_in_clk : in std_logic;
--Port B -> Lookup module
mem_out_enable : in std_logic;
mem_out_addr : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_out_data : out std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
mem_out_clk : in std_logic
);
end rx_path_lookup_memory;
architecture structural of rx_path_lookup_memory is
component blk_mem_gen_0 is
Port (
--Port A -> Processor
wea : in std_logic_vector;
addra : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
dina : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
clka : in std_logic;
--Port B -> Lookup module
enb : in std_logic; --opt port
addrb : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
doutb : out std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
clkb : in std_logic
);
end component;
begin
lookup_mem_ip : blk_mem_gen_0
PORT MAP (
--Port A
wea => mem_in_wenable,
addra => mem_in_addr,
dina => mem_in_data,
clka => mem_in_clk,
--Port B
enb => mem_out_enable,
addrb => mem_out_addr,
doutb => mem_out_data,
clkb => mem_out_clk
);
end structural;
|
-- ledblinker.vhd
--
-- Created on: 12 May 2017
-- Author: Fabian Meyer
--
-- LED blinker with configurable frequency.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LED blinking module
entity ledblinker is
port (clk: in std_logic; -- clock, rising edge
led: out std_logic); -- LED status, active high
end entity ledblinker;
architecture behavioral of ledblinker is
-- define length of counter
constant CNTLEN: natural := 24;
signal cnt: std_logic_vector(CNTLEN-1 downto 0) := (others => '0');
signal led_int: std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if unsigned(cnt) = 12000000 then
cnt <= (others => '0');
led_int <= not led_int;
else
cnt <= std_logic_vector(unsigned(cnt) + 1);
end if;
end if;
end process;
led <= led_int;
end architecture behavioral;
|
--
-- UART for ZPUINO - Majority voting filter
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity zpuino_uart_mv_filter is
generic (
bits: natural;
threshold: natural
);
port (
clk: in std_logic;
rst: in std_logic;
sin: in std_logic;
sout: out std_logic;
clear: in std_logic;
enable: in std_logic
);
end entity zpuino_uart_mv_filter;
architecture behave of zpuino_uart_mv_filter is
signal count_q: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
count_q <= (others => '0');
sout <= '0';
else
if clear='1' then
count_q <= (others => '0');
sout <= '0';
else
if enable='1' then
if sin='1' then
count_q <= count_q + 1;
end if;
end if;
if (count_q >= threshold) then
sout<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
-- Revision history:
-- 07.08.2015 Carlos Minamisava Faria created
-- 07.08.2015 Carlos Minamisava Faria entity
-- 07.08.2015 Carlos Minamisava Faria moore state machine states definition
-- 10.08.2015 Carlos Minamisava Faria & Patrick Appenheimer Instructions added
-- 10.08.2015 Patrick Appenheimer bugfixes
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library WORK;
use WORK.all;
-- -------------------------------------- --
-- FSM-Moore State Machine: --
-- -------------------------------------- --
-- current state
-- when 0 => -- Instruction fetch
-- when 1 => -- Instruction Decode / Register fetch
-- when 2 => -- Memory address computation
-- when 3 => -- Execution
-- when 4 => -- Branch completion
-- when 5 => -- Jump Completion
-- when 6 => -- Memory access read
-- when 7 => -- Memory access write
-- when 8 => -- Writeback
-- when 9 => -- R-Type completion
-- when 10 => -- R-Type completion - Overflow
-- when 11 => -- Others
-- -------------------------------------- --
-- FSM-signal-Howto: --
-- -------------------------------------- --
-- -------- Datapath -----------------
-- pc_mux:
-- 1: Branch logic
-- 0: old PC +4
-- -------- Instr. Decode -----------------
-- regdest_mux:
-- 00: if instruction is of R-type
-- 01: if regdest must be set to 31 (JAL?)
-- 10: if instruction is of I-type
-- 11: NEVER EVER EVER!!!
--
-- regshift_mux:
-- 00: if instruction is of R-type
-- 01: if shift must be 16 (No idea, which instruction uses that...)
-- 10: if you like non-deterministic behaviour
-- 11: if you love non-deterministic behaviour
--
-- enable_regs:
-- 1: if the writeback-stage just finished an R-type- or I-type-instruction (except for JR)
-- 0: if the writeback-stage just finished a J-type-instruction or JR
--
-- -------- Execution -----------------
-- in_mux1 chooses the input of register A for the ALU
-- 00: Zero extend
-- 01: outputs x"0000_0004"
-- 10: in A from Decode
-- 11: others => 'X'
--
-- in_mux2 chooses the input of register B for the ALU:
-- 00: in_b
-- 01: immediate 16
-- 10: Instruction Pointer (IP)
-- 11: others => 'X'
-- in_alu_instruction:
-- 000000:
--
-- -------- Memory Stage -----------------
-- FSS decision for writeback output. ALU results or memory data can be forwarded to writeback
-- mux_decisions:
-- 0: to forward aluResult
-- 1: to forward memory data
--
-- -- stage_control: --
-- to activate registers, set signal stage_control as follows:
-- stage0->stage1: xxxx1
-- stage1->stage2: xxx1x
-- stage2->stage3: xx1xx
-- stage3->stage4: x1xxx
-- stage4->stage5: 1xxxx
-- stage0: PC
-- stage1: Instruction Fetch
-- stage2: Instr. Decode
-- stage3: Execution
-- stage4: Memory Stage
-- stage5: Writeback
-- -------------------------------------- --
-- Instruction: --
-- -------------------------------------- --
-- The reference program needs the following assembly commands:
-- lui -- Load upper immediate: 0011 11
-- addiu -- Add immediate unsigned 0010 01
-- j -- Jumps 0000 10
-- lw -- Load word 1000 11
-- nop -- Performs no operation. 0000 00
-- sb -- Store byte 1010 00
-- sw -- Store word 1010 11
-- slti -- Set on less than immediate (signed) 0010 10
-- beqz -- Branch on equal 0001 00
-- bnez -- Branch on greater than or equal to zero 0001 01
-- lbu -- Load byte unsigned 1001 00
-- andi -- And Immediate 0011 00
-- jalx -- Jump and Link Exchange 0111 01
entity FSM is
port (
-- General Signals
clk : in std_logic;
rst : in std_logic;
-- output_buffer is a register with all control outputs of the state machine:
-- output_buffer (29 downto 29): pc_mux: out std_logic;
-- output_buffer (28 downto 27): regdest_mux,
-- output_buffer (26 downto 25): regshift_mux: out std_logic_vector (1 downto 0);
-- output_buffer (24 downto 24): enable_regs: out std_logic;
-- output_buffer (23 downto 22): in_mux1 : out std_logic_vector(1 downto 0);
-- output_buffer (21 downto 20): in_mux2 : out std_logic_vector(1 downto 0);
-- output_buffer (19 downto 14): in_alu_instruction : out std_logic_vector(5 downto 0);
-- output_buffer (13 downto 13): mux_decision: out std_logic;
-- output_buffer (12 downto 9): rd_mask : out std_logic_vector(3 downto 0);
-- output_buffer (8 downto 5): wr_mask : out std_logic_vector(3 downto 0);
-- output_buffer (4 downto 0): stage_control : out std_logic_vector(4 downto 0);
fsm_busy: out std_logic;
nextfsm_busy: in std_logic;
nextfsm_state: in std_logic_vector(4 downto 0);
output_buffer : out std_logic_vector(29 downto 0);
-- Datapath -----------------
--pc_mux : out std_logic;
-- Instr. Fetch -----------------
instr : in std_logic_vector(31 downto 0);
-- Instr. Decode -----------------
--regdest_mux, regshift_mux : out std_logic_vector (1 downto 0);
--enable_regs : out std_logic;
-- Execution -----------------
--in_mux1 : out std_logic_vector(1 downto 0);
--in_mux2 : out std_logic_vector(1 downto 0);
--in_alu_instruction : out std_logic_vector(5 downto 0);
--ex_alu_zero : in std_logic_vector(0 downto 0);
-- Memory Stage -----------------
--mux_decision : out std_logic;
-- Write Back -----------------
-- Memory -----------------
--rd_mask : out std_logic_vector(3 downto 0);
--wr_mask : out std_logic_vector(3 downto 0);
instr_stall : in std_logic;
data_stall : in std_logic
-- Pipeline -----------------
--stage_control : out std_logic_vector(4 downto 0) next step in pipeline
);
end entity FSM;
architecture behavioral of FSM is
-- State Machine --
constant s0 : std_logic_vector(4 downto 0) := b"00000";
constant s1 : std_logic_vector(4 downto 0) := b"00001";
constant s2 : std_logic_vector(4 downto 0) := b"00010";
constant s3 : std_logic_vector(4 downto 0) := b"00011";
constant s4 : std_logic_vector(4 downto 0) := b"00100";
constant s5 : std_logic_vector(4 downto 0) := b"00101";
constant s6 : std_logic_vector(4 downto 0) := b"00110";
constant s7 : std_logic_vector(4 downto 0) := b"00111";
constant s8 : std_logic_vector(4 downto 0) := b"01000";
constant s9 : std_logic_vector(4 downto 0) := b"01001";
constant s10 : std_logic_vector(4 downto 0) := b"01010";
constant s11 : std_logic_vector(4 downto 0) := b"01011";
-- Arithmetic --
constant addiu : std_logic_vector(5 downto 0) := b"0010_01"; -- Type I
-- Data Transfer --
constant lui : std_logic_vector(5 downto 0) := b"0011_11"; -- Type I -Register access
constant lbu : std_logic_vector(5 downto 0) := b"1001_00"; -- Type I -Memory access
constant lw : std_logic_vector(5 downto 0) := b"1000_11"; -- Type I -Memory access
constant sb : std_logic_vector(5 downto 0) := b"101000"; -- Type I -Memory access
constant sw : std_logic_vector(5 downto 0) := b"101011"; -- Type I -Memory access
-- Logical --
constant slti : std_logic_vector(5 downto 0) := b"001010"; -- Type I
constant andi : std_logic_vector(5 downto 0) := b"0011_00"; -- Type I
constant shift : std_logic_vector(5 downto 0) := b"0000_00"; -- Type R -NOP is read as sll $0,$0,0
-- Bitwise Shift --
-- Conditional branch --
constant beqz : std_logic_vector(5 downto 0) := b"000100"; -- Type I
constant bnez : std_logic_vector(5 downto 0) := b"000101"; -- Type I
-- Unconditional jump --
constant j : std_logic_vector(5 downto 0) := b"0000_10"; -- Type J
constant jalx : std_logic_vector(5 downto 0) := b"0011_01"; -- Type J
constant r_type : std_logic_vector(5 downto 0) := b"0000_00"; -- Type R
signal opcode : std_logic_vector(5 downto 0);
signal currentstate : std_logic_vector(4 downto 0) := (others => '0');
signal nextstate : std_logic_vector(4 downto 0) := (others => '0');
signal instruction : std_logic_vector(31 downto 0) := (others => '0');
begin
-- purpose: set output buffer on instruction input
-- type : combinational
-- inputs : instr
-- outputs: output
output : process (instr, currentstate, instr_stall, data_stall)
begin
if (rst = '1') then -- if no reset
case currentstate is
when s0 => -- Instruction fetch
output_buffer <= (others => '0'); -- reinitialize all to zero
if (instr_stall = '0') then -- check if a instruction stall is required. Stall if 1.
opcode <= instr (31 downto 26);
case instr (31 downto 26) is
when lui => output_buffer <= b"0_10_01_1_00_01_000100_0_0000_0000_11111";
when addiu => output_buffer <= b"0_10_00_1_10_01_100000_0_0000_0000_11111";
when lbu => output_buffer <= b"0_10_00_1_10_01_100000_1_0001_0000_11111";
when lw => output_buffer <= b"0_10_00_1_10_01_100000_1_1111_0000_11111";
when sb => output_buffer <= b"0_10_00_0_10_01_100000_0_0001_0000_11111";
when sw => output_buffer <= b"0_10_00_0_10_01_100000_0_1111_0000_11111";
when slti => output_buffer <= b"0_10_00_1_10_01_001000_0_0000_0000_11111";
when andi => output_buffer <= b"0_10_01_1_00_01_100100_0_0000_0000_11111";
when shift => output_buffer <= b"0_00_00_1_00_00_001000_0_0000_0000_11111";
when beqz => output_buffer <= b"0_10_00_0_00_00_000000_0_0000_0000_11111";
when bnez => output_buffer <= b"0_10_00_0_00_00_000000_0_0000_0000_11111";
when j => output_buffer <= b"1_10_00_1_00_00_000000_0_0000_0000_11000";
when jalx => output_buffer <= b"1_10_00_1_00_00_000000_0_0000_0000_11000";
--when r_type => output_buffer <= b"0_00_00_0_00_00_000000_0_0000_0000_11111";
when others => output_buffer <= b"0_00_00_0_00_00_000000_0_0000_0000_11111";
end case;
if (nextfsm_busy = '0') and (nextfsm_state > currentstate) then
nextstate <= s1; -- nextstate is the Instruction decode
end if;
else -- instruction stall is required
nextstate <= s0; -- stay on this stage if stall is required
end if;
when s1 => -- Instruction Decode / Register fetch
if (nextfsm_busy = '0') and (nextfsm_state > currentstate) then
nextstate <= s1;
else
nextstate <= s2;
end if;
when s2 => -- Execution
nextstate <= s3;
when s3 => -- Memory
nextstate <= s4;
when others => nextstate <= s0;
end case;
else -- if a reset was activated, all outputs and internal registers are reseted
output_buffer <= (others => '0'); -- reinitialize all to zero
currentstate <= b"00000";
nextstate <= b"00000";
end if;
end process output;
-- purpose: this is a timed output for the state machine
-- type : sequential
-- inputs : clk, rst, nextstate
-- outputs: pc_mux, regdest_mux, regshift_mux, enable_regs, in_mux1, in_mux2, in_alu_instruction, mux_decision, rd_mask, wr_mask, stage_control, currentstate
reset : process (clk, rst) is
begin -- process ouput
if rst = '0' then -- asynchronous reset (active low)
currentstate <= s0; -- reset to first state - Instruction fetch
elsif clk'event and clk = '1' then -- rising clock edge
-- output_buffer is outputed
--pc_mux <= output_buffer (29);
--regdest_mux <= output_buffer (28 downto 27);
--regshift_mux <= output_buffer (26 downto 25);
--enable_regs <= output_buffer (24);
--in_mux1 <= output_buffer (23 downto 22);
--in_mux2 <= output_buffer (21 downto 20);
--in_alu_instruction <= output_buffer (19 downto 14);
--mux_decision <= output_buffer (13);
--rd_mask <= output_buffer (12 downto 9);
--wr_mask <= output_buffer (8 downto 5);
--stage_control <= output_buffer (4 downto 0);
currentstate <= nextstate;
end if;
end process reset;
end architecture behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc526.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00526ent IS
END c03s03b00x00p03n04i00526ent;
ARCHITECTURE c03s03b00x00p03n04i00526arch OF c03s03b00x00p03n04i00526ent IS
BEGIN
TESTING : PROCESS
type beta is range 1000 downto 0
units
b1;
b2 = 5 b1;
b3 = 7 b2;
b4 = 1 b3;
end units;
type phys_ptr is access beta;
variable v_phys_ptr1: phys_ptr := new beta'(6 b1);
variable v_phys_ptr2: phys_ptr;
variable v_phys_ptr3: phys_ptr := v_phys_ptr1;
variable v_phys_ptr4: phys_ptr := new beta'(1 b3);
variable v_phys_ptr5: phys_ptr := v_phys_ptr4;
variable OKtest : integer := 0;
BEGIN
assert v_phys_ptr1.all = 6 b1;
if (v_phys_ptr1.all = 6 b1) then
OKtest := Oktest + 1;
end if;
assert v_phys_ptr2 = null;
if (v_phys_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_phys_ptr3.all = 6 b1;
if (v_phys_ptr3.all = 6 b1) then
OKtest := Oktest + 1;
end if;
assert v_phys_ptr4.all = 1 b3;
if (v_phys_ptr4.all = 1 b3) then
OKtest := Oktest + 1;
end if;
assert v_phys_ptr5.all = b4;
if (v_phys_ptr5.all = b4) then
OKtest := Oktest + 1;
end if;
v_phys_ptr2 := new beta'(7 b2);
assert v_phys_ptr2.all = b3;
if (v_phys_ptr2.all = b3) then
OKtest := Oktest + 1;
end if;
assert (40 * v_phys_ptr3.all / 6 = 1 b2 + 1 b4);
if (40 * v_phys_ptr3.all / 6 = 1 b2 + 1 b4) then
OKtest := Oktest + 1;
end if;
assert (v_phys_ptr5.all = 1 b2 + 6 b2);
if (v_phys_ptr5.all = 1 b2 + 6 b2) then
OKtest := Oktest + 1;
end if;
assert (v_phys_ptr5.all = v_phys_ptr2.all - 5 * 7 b1 + 1 b4);
if (v_phys_ptr5.all = v_phys_ptr2.all - 5 * 7 b1 + 1 b4) then
OKtest := Oktest + 1;
end if;
assert (v_phys_ptr5.all > v_phys_ptr1.all) = true;
if ((v_phys_ptr5.all > v_phys_ptr1.all) = true) then
OKtest := Oktest + 1;
end if;
deallocate(v_phys_ptr1);
deallocate(v_phys_ptr2);
deallocate(v_phys_ptr4);
assert NOT(OKtest = 10)
report "***PASSED TEST: c03s03b00x00p03n04i00526"
severity NOTE;
assert (OKtest = 10)
report "***FAILED TEST: c03s03b00x00p03n04i00526 - Physical type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00526arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc526.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00526ent IS
END c03s03b00x00p03n04i00526ent;
ARCHITECTURE c03s03b00x00p03n04i00526arch OF c03s03b00x00p03n04i00526ent IS
BEGIN
TESTING : PROCESS
type beta is range 1000 downto 0
units
b1;
b2 = 5 b1;
b3 = 7 b2;
b4 = 1 b3;
end units;
type phys_ptr is access beta;
variable v_phys_ptr1: phys_ptr := new beta'(6 b1);
variable v_phys_ptr2: phys_ptr;
variable v_phys_ptr3: phys_ptr := v_phys_ptr1;
variable v_phys_ptr4: phys_ptr := new beta'(1 b3);
variable v_phys_ptr5: phys_ptr := v_phys_ptr4;
variable OKtest : integer := 0;
BEGIN
assert v_phys_ptr1.all = 6 b1;
if (v_phys_ptr1.all = 6 b1) then
OKtest := Oktest + 1;
end if;
assert v_phys_ptr2 = null;
if (v_phys_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_phys_ptr3.all = 6 b1;
if (v_phys_ptr3.all = 6 b1) then
OKtest := Oktest + 1;
end if;
assert v_phys_ptr4.all = 1 b3;
if (v_phys_ptr4.all = 1 b3) then
OKtest := Oktest + 1;
end if;
assert v_phys_ptr5.all = b4;
if (v_phys_ptr5.all = b4) then
OKtest := Oktest + 1;
end if;
v_phys_ptr2 := new beta'(7 b2);
assert v_phys_ptr2.all = b3;
if (v_phys_ptr2.all = b3) then
OKtest := Oktest + 1;
end if;
assert (40 * v_phys_ptr3.all / 6 = 1 b2 + 1 b4);
if (40 * v_phys_ptr3.all / 6 = 1 b2 + 1 b4) then
OKtest := Oktest + 1;
end if;
assert (v_phys_ptr5.all = 1 b2 + 6 b2);
if (v_phys_ptr5.all = 1 b2 + 6 b2) then
OKtest := Oktest + 1;
end if;
assert (v_phys_ptr5.all = v_phys_ptr2.all - 5 * 7 b1 + 1 b4);
if (v_phys_ptr5.all = v_phys_ptr2.all - 5 * 7 b1 + 1 b4) then
OKtest := Oktest + 1;
end if;
assert (v_phys_ptr5.all > v_phys_ptr1.all) = true;
if ((v_phys_ptr5.all > v_phys_ptr1.all) = true) then
OKtest := Oktest + 1;
end if;
deallocate(v_phys_ptr1);
deallocate(v_phys_ptr2);
deallocate(v_phys_ptr4);
assert NOT(OKtest = 10)
report "***PASSED TEST: c03s03b00x00p03n04i00526"
severity NOTE;
assert (OKtest = 10)
report "***FAILED TEST: c03s03b00x00p03n04i00526 - Physical type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00526arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc526.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00526ent IS
END c03s03b00x00p03n04i00526ent;
ARCHITECTURE c03s03b00x00p03n04i00526arch OF c03s03b00x00p03n04i00526ent IS
BEGIN
TESTING : PROCESS
type beta is range 1000 downto 0
units
b1;
b2 = 5 b1;
b3 = 7 b2;
b4 = 1 b3;
end units;
type phys_ptr is access beta;
variable v_phys_ptr1: phys_ptr := new beta'(6 b1);
variable v_phys_ptr2: phys_ptr;
variable v_phys_ptr3: phys_ptr := v_phys_ptr1;
variable v_phys_ptr4: phys_ptr := new beta'(1 b3);
variable v_phys_ptr5: phys_ptr := v_phys_ptr4;
variable OKtest : integer := 0;
BEGIN
assert v_phys_ptr1.all = 6 b1;
if (v_phys_ptr1.all = 6 b1) then
OKtest := Oktest + 1;
end if;
assert v_phys_ptr2 = null;
if (v_phys_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_phys_ptr3.all = 6 b1;
if (v_phys_ptr3.all = 6 b1) then
OKtest := Oktest + 1;
end if;
assert v_phys_ptr4.all = 1 b3;
if (v_phys_ptr4.all = 1 b3) then
OKtest := Oktest + 1;
end if;
assert v_phys_ptr5.all = b4;
if (v_phys_ptr5.all = b4) then
OKtest := Oktest + 1;
end if;
v_phys_ptr2 := new beta'(7 b2);
assert v_phys_ptr2.all = b3;
if (v_phys_ptr2.all = b3) then
OKtest := Oktest + 1;
end if;
assert (40 * v_phys_ptr3.all / 6 = 1 b2 + 1 b4);
if (40 * v_phys_ptr3.all / 6 = 1 b2 + 1 b4) then
OKtest := Oktest + 1;
end if;
assert (v_phys_ptr5.all = 1 b2 + 6 b2);
if (v_phys_ptr5.all = 1 b2 + 6 b2) then
OKtest := Oktest + 1;
end if;
assert (v_phys_ptr5.all = v_phys_ptr2.all - 5 * 7 b1 + 1 b4);
if (v_phys_ptr5.all = v_phys_ptr2.all - 5 * 7 b1 + 1 b4) then
OKtest := Oktest + 1;
end if;
assert (v_phys_ptr5.all > v_phys_ptr1.all) = true;
if ((v_phys_ptr5.all > v_phys_ptr1.all) = true) then
OKtest := Oktest + 1;
end if;
deallocate(v_phys_ptr1);
deallocate(v_phys_ptr2);
deallocate(v_phys_ptr4);
assert NOT(OKtest = 10)
report "***PASSED TEST: c03s03b00x00p03n04i00526"
severity NOTE;
assert (OKtest = 10)
report "***FAILED TEST: c03s03b00x00p03n04i00526 - Physical type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00526arch;
|
--------------------------------------------------------------------------------
-- ion_wishbone_bridge.vhdl -- Connects an ION bus master to a Wishbone bus.
--------------------------------------------------------------------------------
-- ION_WISHBONE_BRIDGE
-- This bridge converts ION-bus signals to Wishbone signals ans vice-versa.
-- For the Wb-slaves, the bridge appears as the Wb-bus master.
--
-- REFERENCES
--
--------------------------------------------------------------------------------
--
--
--------------------------------------------------------------------------------
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_WISHBONE_BRIDGE is
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
ION_MOSI_I : in t_cpumem_mosi;
ION_MISO_O : out t_cpumem_miso;
WISHBONE_MOSI_O : out t_wishbone_mosi;
WISHBONE_MISO_I : in t_wishbone_miso
);
end;
architecture ION_WISHBONE_BRIDGE_arc of ION_WISHBONE_BRIDGE is
-- Signal to register the value of Wb-signal STALL_I
signal stall_i_reg : std_logic;
begin
--WISHBONE_MOSI_O <= ION_MOSI_I;
--ION_MISO_O <= WISHBONE_MISO_I;
--process (CLK_I, RESET_I, ION_MOSI_I.rd_en, ION_MOSI_I.wr_be,
-- WISHBONE_MISO_I.ack)
process (CLK_I, RESET_I, ION_MOSI_I, WISHBONE_MISO_I)
-- variable cyc_var : boolean := false;
begin
-----------------------------------------------------------------
-- Generate ION-bus o/p signals
-----------------------------------------------------------------
ION_MISO_O.rd_data <= WISHBONE_MISO_I.dat;
ION_MISO_O.mwait <= WISHBONE_MISO_I.stall;
-----------------------------------------------------------------
-- Generate Wishbone o/p signals
-----------------------------------------------------------------
WISHBONE_MOSI_O.adr <= ION_MOSI_I.addr;
WISHBONE_MOSI_O.dat <= ION_MOSI_I.wr_data;
WISHBONE_MOSI_O.tga <= ION_MOSI_I.wr_be;
WISHBONE_MOSI_O.we <= not(ION_MOSI_I.rd_en);
-----------------------------------------------------------------
-- Generate the Wb STROBE signal from valid read or write cycles
-----------------------------------------------------------------
if ((ION_MOSI_I.rd_en = '1' and ION_MOSI_I.wr_be /= "1111") or
(ION_MOSI_I.rd_en = '0' and ION_MOSI_I.wr_be = "1111")) then
WISHBONE_MOSI_O.stb <= '1';
else
WISHBONE_MOSI_O.stb <= '0';
end if;
-- Register the value of Wb signal STALL_I
if (RESET_I = '0') then
stall_i_reg <= '0';
else
if (CLK_I='1' and CLK_I'event) then
stall_i_reg <= WISHBONE_MISO_I.stall;
end if;
end if;
-----------------------------------------------------------------
-- Generate the Wb CYCLIC signal from valid read/write cycles
-----------------------------------------------------------------
if ((ION_MOSI_I.rd_en = '1' and ION_MOSI_I.wr_be /= "1111") or
(ION_MOSI_I.rd_en = '0' and ION_MOSI_I.wr_be = "1111")) then
WISHBONE_MOSI_O.cyc <= '1';
-- Check the STALL & ACK inputs in case of invalid read/write
else
-- If STALL was LOW in the previous clk cycle
if (stall_i_reg = '0') then
-- CYC is de-asserted only if ACK is de-asserted
if (WISHBONE_MISO_I.ack = '0') then
WISHBONE_MOSI_O.cyc <= '0';
-- CYC remains asserted
else
WISHBONE_MOSI_O.cyc <= '1';
end if;
-- If STALL was HIGH in previous clk cycle
else
WISHBONE_MOSI_O.cyc <= '1';
end if;
end if;
end process;
end architecture ION_WISHBONE_BRIDGE_arc;
|
library ieee;
use ieee.numeric_bit.all;
entity View2 is
port(
Rb, Reset, CLK: in bit;
Win, Lose:out bit;
hex0,hex1:out unsigned(7 downto 0)
);
end entity View2;
architecture Sys of View2 is
component Segment7Decoder
port (bcd : in unsigned(3 downto 0); --BCD input
segment7 : out unsigned(6 downto 0) -- 7 bit decoded output.
);
end component;
component Roll_Sum
port(Rb,CLK,Reset:in bit;
hex0,hex1:out integer range 6 downto 1;
Sum:out integer range 12 downto 2
);
end component;
component PointerRegister
port(
Sum:in integer range 2 to 12;
Sp:in bit;
LockedSum:out integer range 2 to 12
);
end component;
component Compartor
port(
Sum,LockedSum:in integer range 2 to 12;
Eq,D7,D711,D2312:out bit
);
end component;
component Controller
port(
Rb,Reset, Eq,D7,D711,D2312,CLK:in bit;
Sp,Roll,Win,Lose,Clear:out bit);
end component;
signal mid_hex0,mid_hex1:integer range 6 downto 1;
signal mid_hex0_unsigned,mid_hex1_unsigned:unsigned(3 downto 0);
signal mid_Sum,mid_LockedSum:integer range 12 downto 2;
signal mid_Roll,mid_Clear,mEq,mD7,mD711,mD2312,mid_Sp:bit;
begin
label_Controller:Controller port map(Rb,Reset, mEq,mD7,mD711,mD2312,CLK, mid_Sp,mid_Roll,Win,Lose,mid_Clear);
label_Roll_sum:Roll_Sum port map(mid_Roll,CLK,mid_Clear,mid_hex0,mid_hex1,mid_Sum);
label_Pointer:PointerRegister port map(mid_Sum,mid_Sp,mid_LockedSum);
label_Compartoe:Compartor port map(mid_Sum,mid_LockedSum,mEq,mD7,mD711,mD2312);
Dispaly_hex0:Segment7Decoder port map(mid_hex0_unsigned,hex0(7 downto 1));
Dispaly_hex1:Segment7Decoder port map(mid_hex1_unsigned,hex1(7 downto 1));
mid_hex0_unsigned<=to_unsigned(mid_hex0,4);
mid_hex1_unsigned<=to_unsigned(mid_hex1,4);
hex0(0)<='1';--shutdown Dot..
hex1(0)<='1';
end architecture Sys; |
-- ps2_rx_tb.vhd - TB modulu pro prijem signalu z portu PS2
-- Autori: Jakub Cabal
-- Posledni zmena: 04.10.2014 21:24
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY TB_PS2_RX IS
END TB_PS2_RX;
ARCHITECTURE behavior OF TB_PS2_RX IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PS2_RX
PORT(
CLK : IN std_logic;
RST : IN std_logic;
PS2C : IN std_logic;
PS2D : IN std_logic;
PS2RX_DATA : OUT std_logic_vector(7 downto 0);
PS2RX_VALID : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal ps2c : std_logic := '0';
signal ps2d : std_logic := '0';
--Outputs
signal PS2RX_DATA : std_logic_vector(7 downto 0);
signal PS2RX_VALID : std_logic;
-- Clock period definitions
constant CLK2_period : time := 10 ns;
constant clk_period : time := 90 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PS2_RX PORT MAP (
CLK => CLK,
RST => RST,
PS2C => ps2c,
PS2D => ps2d,
PS2RX_DATA => PS2RX_DATA,
PS2RX_VALID => PS2RX_VALID
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK2_period/2;
CLK <= '1';
wait for CLK2_period/2;
end process;
-- Stimulus process - generate scan codes
p_keyboard: process
variable data : std_logic_vector(7 downto 0);
variable parity : std_logic;
begin
ps2d <= '1';
ps2c <= '1';
RST <= '1';
wait for 100 ns;
RST <= '0';
wait for clk_period*10;
----------------------------------------------------------------------------------
-- key A - make code
data := X"1C";
parity := data(7) xor data(6) xor data(5) xor data(4) xor data(3) xor data(2) xor data(1) xor data(0) xor '1';
ps2d <= '0'; -- start bit
wait for clk_period*0.1;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
for i in 0 to 7 loop
ps2d <= data(0); -- LSB first
data := '0' & data(7 downto 1); -- shift right
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
end loop;
ps2d <= parity; -- parity bit
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
ps2d <= '1'; -- stop bit
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
wait for clk_period*50;
----------------------------------------------------------------------------------
-- break code
data := X"F0";
parity := data(7) xor data(6) xor data(5) xor data(4) xor data(3) xor data(2) xor data(1) xor data(0) xor '1';
ps2d <= '0'; -- start bit
wait for clk_period*0.1;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
for i in 0 to 7 loop
ps2d <= data(0); -- LSB first
data := '0' & data(7 downto 1); -- shift right
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
end loop;
ps2d <= parity; -- parity bit
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
ps2d <= '1'; -- stop bit
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
wait for clk_period*50;
----------------------------------------------------------------------------------
-- break code of key A
data := X"1C";
parity := data(7) xor data(6) xor data(5) xor data(4) xor data(3) xor data(2) xor data(1) xor data(0) xor '1';
ps2d <= '0'; -- start bit
wait for clk_period*0.1;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
for i in 0 to 7 loop
ps2d <= data(0); -- LSB first
data := '0' & data(7 downto 1); -- shift right
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
end loop;
ps2d <= parity; -- parity bit
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
ps2d <= '1'; -- stop bit
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
wait for clk_period*50;
----------------------------------------------------------------------------------
-- end of simulation
wait;
end process p_keyboard;
END; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
clkperiod : integer := 10 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal rstn : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(26 downto 0):=(others =>'0');
signal data : std_logic_vector(31 downto 0);
signal RamCE : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Output signals for LEDs
signal led : std_logic_vector(15 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 100 ns;
rstn <= not rst;
dsubre <= '0';
urxd <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech)
port map (
clk => clk,
btnCpuResetn => rstn,
-- PROM
address => address(22 downto 0),
data => data(31 downto 16),
RamOE => oen,
RamWE => writen,
RamCE => RamCE,
-- AHB Uart
RsRx => dsurx,
RsTx => dsutx,
-- Output signals for LEDs
led => led
);
sram0 : sram
generic map (index => 4, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(31 downto 24), RamCE, writen, oen);
sram1 : sram
generic map (index => 5, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(23 downto 16), RamCE, writen, oen);
led(3) <= 'L'; -- ERROR pull-down
error <= not led(3);
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
data <= buskeep(data) after 5 ns;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity anod_enabler_decoder_tb is
end;
architecture anod_enabler_decoder_tb_func of anod_enabler_decoder_tb is
signal data_in: std_logic_vector(1 downto 0) := (others => '0');
signal data_out: std_logic_vector(3 downto 0) := (others => '0');
component anod_enabler_decoder is
port(
binary_in: in std_logic_vector(1 downto 0); --"2 bit vector to switch between the 4 possible anod values"
code_out: out std_logic_vector(3 downto 0) --4 bit output to switch between anod
);
end component;
begin
data_in(0) <= not(data_in(0)) after 20 ns;
data_in(1) <= not(data_in(1)) after 40 ns;
anodEnablerMap: anod_enabler_decoder
port map(
binary_in => data_in,
code_out => data_out
);
end architecture;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY fifo_generator_input_buffer IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END fifo_generator_input_buffer;
ARCHITECTURE fifo_generator_input_buffer_arch OF fifo_generator_input_buffer IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_input_buffer_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_generator_input_buffer_arch: ARCHITECTURE IS "fifo_generator_v13_0_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_input_buffer_arch : ARCHITECTURE IS "fifo_generator_input_buffer,fifo_generator_v13_0_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_input_buffer_arch: ARCHITECTURE IS "fifo_generator_input_buffer,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=12,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx9,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=4093,C_PROG_FULL_THRESH_NEGATE_VAL=4092,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=12,C_WR_DEPTH=4096,C_WR_FREQ=1,C_WR_PNTR_WIDTH=12,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 12,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx9",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 4093,
C_PROG_FULL_THRESH_NEGATE_VAL => 4092,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 12,
C_WR_DEPTH => 4096,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 12,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_input_buffer_arch;
|
architecture RTL of FIFO is begin end architecture RTL;
architecture RTL of FIFO is
begin end architecture RTL;
-- This should fail
architecture RTL of FIFO is
begin
end architecture RTL;
|
-------------------------------------------------------------------------------
-- Design : Instruction Fetch Queue i_fetch_q
-- Project : Tomasulo Processor
-- Author : Gandhi Puvvada
-- Company : University of Southern California
-- Date : 07/25/2008 , 7/15/2009, 6/29/2010
-- This file is same as the file dated 4/27/2010 except for a few spelling errors!
-- File : i_fetch_q_efficient_r2.vhd
-------------------------------------------------------------------------------
-- Description : This is the revised design where we eliminated all
-- barrel shifters. We read an entire cache line of 4 words
-- into the Instruction Fetch Queue.
-----------------------------------------------------------------------------
-- Solution version of the design:
-- ==============================
-- Here we fixed the following two inefficiencies and one restriction
-- which existed in the exercise version of the design (i.e. in i_fetch_q_inefficient_r2.vhd).
-- Inefficiency #1: Delay in conveying branch/jump target address to cache
-- Inefficiency #2: Delay in conveying the target instruction to the dispatch unit:
-- Restriction #1: All branch and jump target addresses shall be aligned to 4-word boundary.
-- Along with removing the inefficiency #2, we will use our forwarding (FWFT)
-- circuitry to forward the first instruction after the IFQ runs dry (becomes empty).
-- FWFT = First Word Fall Through
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all; -- use of this package is discouraged. So, without this, we need to write "unsigned(wp) - unsigned(rp)" inplace of simple "wp - rp".
-- use work.tmslopkg.all ;
entity i_fetch_q is
port (
Clk : in std_logic;
Resetb : in std_logic;
-- interface with the dispatch unit
Ifetch_Instruction : out std_logic_vector(31 downto 0);
Ifetch_PcPlusFour : out std_logic_vector(31 downto 0);
Ifetch_EmptyFlag : out std_logic;
Dis_Ren : in std_logic; -- may be active even if ifq is empty.
Dis_JmpBrAddr : in std_logic_vector(31 downto 0);
Dis_JmpBr : in std_logic;
Dis_JmpBrAddrValid : in std_logic;
-- interface with the cache unit
Ifetch_WpPcIn : out std_logic_vector(31 downto 0);
Ifetch_ReadCache : out std_logic;
-- synopsys translate_off
wp_report, rp_report, depth_report : out std_logic_vector(4 downto 0);
-- synopsys translate_on
Ifetch_AbortPrevRead : out std_logic;
Cache_Cd0 : in std_logic_vector (31 downto 0);
Cache_Cd1 : in std_logic_vector (31 downto 0);
Cache_Cd2 : in std_logic_vector (31 downto 0);
Cache_Cd3 : in std_logic_vector (31 downto 0);
Cache_ReadHit : in std_logic
);
end entity i_fetch_q;
-----------------------------------------------------------------------------
architecture i_fetch_q_arc of i_fetch_q is
-- Component declaration
component i_fetch_fifo_ram_reg_array
generic (N: integer := 2; M: integer := 32);
port (
Clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(N-1 downto 0);
dia : in std_logic_vector(M-1 downto 0);
addrb : in std_logic_vector(N-1 downto 0);
dob : out std_logic_vector(M-1 downto 0)
);
end component i_fetch_fifo_ram_reg_array;
-- local signal declarations
-- Note: The suffix "_int" means an internal local signal. Most outputs
-- may be first generated as an internal signals and then assigned to
-- their output ports.
signal wp, rp : std_logic_vector(4 downto 0);
-- Note: We are using 5-bit pointers for a 16-location fifo. It is not absolutely
-- necessary to use 5-bit pointers as it is a single clock fifo. It is possible to use
-- 4-bit pointer. However, it makes it easy to produce the full and empty flags.
-- We actually use only upper 3-bits of the 5-bit wp and 5-bit rp to compute EMPTY and FULL.
-- This solves a lot of problems we solved earlier using a 2-state state machine!
signal wp_2bit, rp_2bit : std_logic_vector(1 downto 0);
-- the 2-bit pointers (3 downto 2) that go to the four 4x32 register arrays
signal full, nearly_full, empty_int : std_logic; -- internal full and empty flags
signal wp_upper_equals_rp_upper : std_logic; -- to derive empty flag
signal wenq, renq : std_logic; -- write-eable and read-enable, q = qualified
-- synopsys translate_off
signal depth : std_logic_vector(4 downto 0); -- ----------------------------???? Try to avaoid
-- synopsys translate_on
-- instructions read from the i_fetch_q
signal instr0 : std_logic_vector(31 downto 0);
signal instr1 : std_logic_vector(31 downto 0);
signal instr2 : std_logic_vector(31 downto 0);
signal instr3 : std_logic_vector(31 downto 0);
signal bypass_fifo : std_logic; -- forwarding logic signal
signal wp_pc_int, wp_pc_int_next : std_logic_vector(31 downto 0);
-- pc associated with wp
signal rp_pc_plus_four_int : std_logic_vector(31 downto 0);
-- pc associated with rp
signal ValidJump : std_logic; -- Jump only when J, Jal or JR$31. Do not Jump when JR $RS.
begin
-- Component instantiations
ram_dp0: i_fetch_fifo_ram_reg_array
generic map (N => 2, M => 32)
port map(
Clka => Clk, wea => wenq, addra => wp_2bit,
dia => Cache_Cd0, addrb => rp_2bit, dob => instr0);
ram_dp1: i_fetch_fifo_ram_reg_array
generic map (N => 2, M => 32)
port map(
Clka => Clk, wea => wenq, addra => wp_2bit,
dia => Cache_Cd1, addrb => rp_2bit, dob => instr1);
ram_dp2: i_fetch_fifo_ram_reg_array
generic map (N => 2, M => 32)
port map(
Clka => Clk, wea => wenq, addra => wp_2bit,
dia => Cache_Cd2, addrb => rp_2bit, dob => instr2);
ram_dp3: i_fetch_fifo_ram_reg_array
generic map (N => 2, M => 32)
port map(
Clka => Clk, wea => wenq, addra => wp_2bit,
dia => Cache_Cd3, addrb => rp_2bit, dob => instr3);
-- =========================
-- synopsys translate_off
wp_report <= wp; rp_report <= rp; depth_report <= depth;
-- synopsys translate_on
-- =========================
-- Two bits (3 downto 2) of the 5-bit wp counter are sent to all the dual port RAMs.
wp_2bit <= wp(3 downto 2);
rp_2bit <= rp(3 downto 2);
-- The 4 RAMs (register arrays) are organized in a lower-order interleaved fashion.
-- The lower 2 bits of the rp are used to select one instruction from the 4 instructions
-- coming out of the 4 RAMs or the four instructions given out by the instruction cache
-- in the forwarding situation.
-- =========================
-- instruction forwarding
-- =========================
bypass_fifo <= wp_upper_equals_rp_upper AND Cache_ReadHit;-- if fifo was empty, let us forward
Ifetch_Instruction_forwarding_process: process
(bypass_fifo, rp, instr0, instr1, instr2, instr3, Cache_Cd0, Cache_Cd1, Cache_Cd2, Cache_Cd3)
begin
if bypass_fifo = '1' then -- forward the instruction from the cache
case (rp(1 downto 0)) is
when "00" =>
Ifetch_Instruction <= Cache_Cd0;
when "01" =>
Ifetch_Instruction <= Cache_Cd1;
when "10" =>
Ifetch_Instruction <= Cache_Cd2;
when others =>
Ifetch_Instruction <= Cache_Cd3;
end case;
else -- use the instruction previously deposited in the fifo
case (rp(1 downto 0)) is
when "00" =>
Ifetch_Instruction <= instr0;
when "01" =>
Ifetch_Instruction <= instr1;
when "10" =>
Ifetch_Instruction <= instr2;
when others =>
Ifetch_Instruction <= instr3;
end case;
end if;
end process Ifetch_Instruction_forwarding_process;
-- =========================
-- depth, empty, full, ...etc.
-- =========================
-- synopsys translate_off
-- depth calculation and flags generation
depth <= unsigned(wp) - unsigned(rp); ---- avoid producing depth for synthesis ***********************
-- synopsys translate_on
wp_upper_equals_rp_upper <= ( -- only upper three bits!
( wp(4) XNOR rp(4) ) AND
( wp(3) XNOR rp(3) ) AND
( wp(2) XNOR rp(2) )
);
empty_int <= wp_upper_equals_rp_upper AND (NOT(Cache_ReadHit));
Ifetch_EmptyFlag <= empty_int;
-- the dispatch unit shall not consume an instruction during the
-- clock when it asserts "ValidJump" due to a successful branch
-- though the empty_flag will be inactive in that clock.
-- The empty_flag will be inactive in that clock so that the jump instruction
-- is decoded and executed by the dispatch unit.
-- Generating Signal for Valid Jump. When Instruction is Jump type and Jump Addr is valid, Jump.
ValidJump <= Dis_JmpBr AND Dis_JmpBrAddrValid;
---
full <= (
( wp(4) XOR rp(4) ) AND
( wp(3) XNOR rp(3) ) AND
( wp(2) XNOR rp(2) )
);
nearly_full <= '1' when (unsigned(wp(4 downto 2)) - unsigned(rp(4 downto 2)) = unsigned'("011") ) else '0'; -- 3 of the four rows full
Ifetch_ReadCache <= (NOT (full OR (nearly_full AND Cache_ReadHit))) OR (ValidJump);
-- =========================
-- concurrent statements to produce wenq and renq (q = qualified)
wenq <= Cache_ReadHit AND (NOT(full));
-- In the above expression for wenq, "not(full)" is
-- unnecessary as we will not activate read-cache unless we have
-- atleast a row of space_left
renq <= Dis_Ren AND (NOT(empty_int));
-- =========================
wp_pc_int_next_combinational_process: process
(wp_pc_int, wenq, ValidJump, Dis_JmpBrAddr)
begin
if ValidJump = '1' then
wp_pc_int_next <= Dis_JmpBrAddr (31 downto 4) & "0000"; -- aligned address
elsif wenq = '1' then
wp_pc_int_next <= unsigned(wp_pc_int) + 16; -- increment by 16
else
wp_pc_int_next <= wp_pc_int; -- recirculate the current value
end if;
end process wp_pc_int_next_combinational_process;
-- =========================
Clk_registers : process (Clk, Resetb)
begin
if (Resetb = '0') then
wp <= "00000";
rp <= "00000";
wp_pc_int <= X"0000_0000";
rp_pc_plus_four_int <= X"0000_0004";
elsif (Clk'event AND Clk = '1') then
wp_pc_int <= wp_pc_int_next; -- wp_pc_int_next was combinationally derived separately
if (ValidJump = '1') then -- flush the fifo
wp <= "000" & Dis_JmpBrAddr (3 downto 2); rp <= "000" & Dis_JmpBrAddr (3 downto 2);
-- Dis_JmpBrAddr (3 downto 2) is 00 or 01 or 10 or 11
-- depending on the 4-word alignment of the Dis_JmpBrAddr
-- Note: we are not using wp (1 downto 0) anywhere except for producing depth information during simulation.
-- So, wp (1 downto 0) will not be implemented anyway and it does not matter if we initiate it to "00"
-- or to Dis_JmpBrAddr (3 downto 2).
rp_pc_plus_four_int <= unsigned(Dis_JmpBrAddr) + 4;
else
if (wenq = '1') then
wp(4 downto 2) <= unsigned(wp(4 downto 2)) + 1;
end if;
if renq = '1' then
rp <= unsigned(rp) + 1;
rp_pc_plus_four_int <= unsigned(rp_pc_plus_four_int) + 4;
end if;
end if;
end if;
end process Clk_registers;
Ifetch_WpPcIn <= wp_pc_int_next;
-- send it out to the instruction cache
Ifetch_PcPlusFour <= rp_pc_plus_four_int;
-- send it out to the dispatch unit.
Ifetch_AbortPrevRead <= ValidJump;
end architecture i_fetch_q_arc;
-----------------------------------------------------------------------------
|
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_COMPLEX
--
-- Purpose: VHDL declarations for mathematical package MATH_COMPLEX
-- which contains common complex constants and basic complex
-- functions and operations.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body uses package IEEE.MATH_REAL
--
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.1 (Strawman) Jose A. Torres 6/22/92
-- Version 0.2 Jose A. Torres 1/15/93
-- Version 0.3 Jose A. Torres 4/13/93
-- Version 0.4 Jose A. Torres 4/19/93
-- Version 0.5 Jose A. Torres 4/20/93
-- Version 0.6 Jose A. Torres 4/23/93 Added unary minus
-- and CONJ for polar
-- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility
-- with package body.
-------------------------------------------------------------
Library IEEE;
Package MATH_COMPLEX is
type COMPLEX is record RE, IM: real; end record;
type COMPLEX_VECTOR is array (integer range <>) of COMPLEX;
type COMPLEX_POLAR is record MAG: real; ARG: real; end record;
constant CBASE_1: complex := COMPLEX'(1.0, 0.0);
constant CBASE_j: complex := COMPLEX'(0.0, 1.0);
constant CZERO: complex := COMPLEX'(0.0, 0.0);
function CABS(Z: in complex ) return real;
-- returns absolute value (magnitude) of Z
function CARG(Z: in complex ) return real;
-- returns argument (angle) in radians of a complex number
function CMPLX(X: in real; Y: in real:= 0.0 ) return complex;
-- returns complex number X + iY
function "-" (Z: in complex ) return complex;
-- unary minus
function "-" (Z: in complex_polar ) return complex_polar;
-- unary minus
function CONJ (Z: in complex) return complex;
-- returns complex conjugate
function CONJ (Z: in complex_polar) return complex_polar;
-- returns complex conjugate
function CSQRT(Z: in complex ) return complex_vector;
-- returns square root of Z; 2 values
function CEXP(Z: in complex ) return complex;
-- returns e**Z
function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar;
-- converts complex to complex_polar
function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex;
-- converts complex_polar to complex
-- arithmetic operators
function "+" ( L: in complex; R: in complex ) return complex;
function "+" ( L: in complex_polar; R: in complex_polar) return complex;
function "+" ( L: in complex_polar; R: in complex ) return complex;
function "+" ( L: in complex; R: in complex_polar) return complex;
function "+" ( L: in real; R: in complex ) return complex;
function "+" ( L: in complex; R: in real ) return complex;
function "+" ( L: in real; R: in complex_polar) return complex;
function "+" ( L: in complex_polar; R: in real) return complex;
function "-" ( L: in complex; R: in complex ) return complex;
function "-" ( L: in complex_polar; R: in complex_polar) return complex;
function "-" ( L: in complex_polar; R: in complex ) return complex;
function "-" ( L: in complex; R: in complex_polar) return complex;
function "-" ( L: in real; R: in complex ) return complex;
function "-" ( L: in complex; R: in real ) return complex;
function "-" ( L: in real; R: in complex_polar) return complex;
function "-" ( L: in complex_polar; R: in real) return complex;
function "*" ( L: in complex; R: in complex ) return complex;
function "*" ( L: in complex_polar; R: in complex_polar) return complex;
function "*" ( L: in complex_polar; R: in complex ) return complex;
function "*" ( L: in complex; R: in complex_polar) return complex;
function "*" ( L: in real; R: in complex ) return complex;
function "*" ( L: in complex; R: in real ) return complex;
function "*" ( L: in real; R: in complex_polar) return complex;
function "*" ( L: in complex_polar; R: in real) return complex;
function "/" ( L: in complex; R: in complex ) return complex;
function "/" ( L: in complex_polar; R: in complex_polar) return complex;
function "/" ( L: in complex_polar; R: in complex ) return complex;
function "/" ( L: in complex; R: in complex_polar) return complex;
function "/" ( L: in real; R: in complex ) return complex;
function "/" ( L: in complex; R: in real ) return complex;
function "/" ( L: in real; R: in complex_polar) return complex;
function "/" ( L: in complex_polar; R: in real) return complex;
end MATH_COMPLEX;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:09:00 01/06/2016
-- Design Name:
-- Module Name: my_alu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity my_alu is
generic(NUMBITS : natural := 8);
Port ( A : in STD_LOGIC_VECTOR(NUMBITS-1 downto 0);
B : in STD_LOGIC_VECTOR(NUMBITS-1 downto 0);
opcode : in STD_LOGIC_VECTOR(2 downto 0);
result : out STD_LOGIC_VECTOR(NUMBITS-1 downto 0);
carryout : out STD_LOGIC;
overflow : out STD_LOGIC;
zero : out STD_LOGIC);
end my_alu;
architecture Behavioral of my_alu is
signal stuff: std_logic_vector(NUMBITS downto 0);
begin
process (A, B, opcode, stuff)
begin
--UNSIGNED ADD
if opcode = "000" then
stuff <= std_logic_vector( ('0' & unsigned(A) ) + ( '0' & unsigned(B)));
result <= stuff(NUMBITS-1 downto 0);
--carryout <= '1';
carryout <= stuff(NUMBITS);
overflow <= stuff(NUMBITS);
if stuff(NUMBITS downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--SIGNED ADD
elsif opcode = "001" then
stuff <= std_logic_vector( signed('0' & A) + signed('0' & B) );
result <= stuff(NUMBITS-1 downto 0);
if (A(NUMBITS-1) = '0') and (B(NUMBITS-1) = '0') and (stuff(NUMBITS-1) = '1') then
overflow <= '1';
elsif (A(NUMBITS-1) = '1') and (B(NUMBITS-1) = '1') and (stuff(NUMBITS-1) = '0') then
overflow <= '1';
else
overflow <= '0';
end if;
carryout <= stuff(NUMBITS);
if stuff(NUMBITS - 1 downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--UNSIGNED SUB
elsif opcode = "010" then
stuff <= std_logic_vector( ('0' & unsigned(A) ) + ( '0' & ((not unsigned(B)) + 1)));
result <= stuff(NUMBITS-1 downto 0);
overflow <= stuff(NUMBITS - 1);
if stuff(NUMBITS - 1) = '0' then
carryout <= '1';
else
carryout <= '0';
end if;
if stuff(NUMBITS - 1 downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--SIGNED SUB
elsif opcode = "011" then
stuff <= std_logic_vector( ('0' & signed(A) ) + ( '0' & ((not signed(B)) + 1)));
result <= stuff(NUMBITS-1 downto 0);
if (A(NUMBITS-1) = '0') and (B(NUMBITS-1) = '1') and (stuff(NUMBITS-2) = '1') then
overflow <= '1';
elsif (A(NUMBITS-1) = '1') and (B(NUMBITS-1) = '0') and (stuff(NUMBITS-2) = '0') then
overflow <= '1';
else
overflow <= '0';
end if;
carryout <= stuff(NUMBITS);
if stuff(NUMBITS - 1 downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--BITWISE AND
elsif opcode = "100" then
stuff <= std_logic_vector(('0' & A) AND ('0' & B));
result <= stuff(NUMBITS-1 downto 0);
overflow <= '0';
carryout <= '0';
if stuff(NUMBITS downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--BITWISE OR
elsif opcode = "101" then
stuff <= std_logic_vector(('0' & A) OR ('0' & B));
result <= stuff(NUMBITS-1 downto 0);
overflow <= '0';
carryout <= '0';
if stuff(NUMBITS downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--BITWUS XOR
elsif opcode = "110" then
stuff <= std_logic_vector(('0' & A) XOR ('0' & B));
result <= stuff(NUMBITS-1 downto 0);
overflow <= '0';
carryout <= '0';
if stuff(NUMBITS downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
else
--Divide A by 2
stuff <= std_logic_vector( ('0' & unsigned(A)) / 2 );
result <= stuff(NUMBITS-1 downto 0);
overflow <= '0';
carryout <= '0';
if stuff(NUMBITS downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
end if;
end process;
end Behavioral;
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pokey_keyboard_scanner is
port
(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic; -- typically hsync or equiv timing
keyboard_response : in std_logic_vector(1 downto 0);
debounce_disable : in std_logic;
scan_enable : in std_logic;
keyboard_scan : out std_logic_vector(5 downto 0);
shift_pressed : out std_logic;
control_pressed : out std_logic;
break_pressed : out std_logic;
key_held : out std_logic;
keycode : out std_logic_vector(5 downto 0);
other_key_irq : out std_logic
);
end pokey_keyboard_scanner;
architecture vhdl of pokey_keyboard_scanner is
signal bincnt_next : std_logic_vector(5 downto 0);
signal bincnt_reg : std_logic_vector(5 downto 0);
signal break_pressed_next : std_logic;
signal break_pressed_reg : std_logic;
signal shift_pressed_next : std_logic;
signal shift_pressed_reg : std_logic;
signal control_pressed_next : std_logic;
signal control_pressed_reg : std_logic;
signal compare_latch_next : std_logic_vector(5 downto 0);
signal compare_latch_reg : std_logic_vector(5 downto 0);
signal keycode_latch_next : std_logic_vector(5 downto 0);
signal keycode_latch_reg : std_logic_vector(5 downto 0);
signal irq_next : std_logic;
signal irq_reg : std_logic;
signal key_held_next : std_logic;
signal key_held_reg : std_logic;
signal my_key : std_logic;
signal state_next : std_logic_vector(1 downto 0);
signal state_reg : std_logic_vector(1 downto 0);
constant state_wait_key : std_logic_vector(1 downto 0) := "00";
constant state_key_bounce : std_logic_vector(1 downto 0) := "01";
constant state_valid_key : std_logic_vector(1 downto 0) := "10";
constant state_key_debounce : std_logic_vector(1 downto 0) := "11";
begin
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
bincnt_reg <= (others=>'0');
break_pressed_reg <= '0';
shift_pressed_reg <= '0';
control_pressed_reg <= '0';
compare_latch_reg <= (others=>'0');
keycode_latch_reg <= (others=>'1');
key_held_reg <= '0';
state_reg <= state_wait_key;
irq_reg <= '0';
elsif (clk'event and clk = '1') then
bincnt_reg <= bincnt_next;
state_reg <= state_next;
break_pressed_reg <= break_pressed_next;
shift_pressed_reg <= shift_pressed_next;
control_pressed_reg <= control_pressed_next;
compare_latch_reg <= compare_latch_next;
keycode_latch_reg <= keycode_latch_next;
key_held_reg <= key_held_next;
state_reg <= state_next;
irq_reg <= irq_next;
end if;
end process;
process (enable, keyboard_response, scan_enable, key_held_reg, my_key, state_reg,bincnt_reg, compare_latch_reg, break_pressed_reg, shift_pressed_reg, control_pressed_reg, keycode_latch_reg, debounce_disable)
begin
bincnt_next <= bincnt_reg;
state_next <= state_reg;
compare_latch_next <= compare_latch_reg;
irq_next <= '0';
break_pressed_next <= break_pressed_reg;
shift_pressed_next <= shift_pressed_reg;
control_pressed_next <= control_pressed_reg;
keycode_latch_next <= keycode_latch_reg;
key_held_next <= key_held_reg;
my_key <= '0';
if (bincnt_reg = compare_latch_reg or debounce_disable='1') then
my_key <= '1';
end if;
if (enable = '1' and scan_enable='1') then
bincnt_next <= std_logic_vector(unsigned(bincnt_reg) + 1); -- check another key
key_held_next<= '0';
case state_reg is
when state_wait_key =>
if (keyboard_response(0) = '0') then -- detected key press
state_next <= state_key_bounce;
compare_latch_next <= bincnt_reg;
end if;
when state_key_bounce =>
if (keyboard_response(0) = '0') then -- detected key press
if (my_key = '1') then -- same key
keycode_latch_next <= compare_latch_reg;
irq_next <= '1';
key_held_next<= '1';
state_next <= state_valid_key;
else -- different key (multiple keys pressed)
state_next <= state_wait_key;
end if;
else -- key not pressed
if (my_key = '1') then -- same key, no longer pressed
state_next <= state_wait_key;
end if;
end if;
when state_valid_key =>
key_held_next<= '1';
if (my_key = '1') then -- only response to my key
if (keyboard_response(0) = '1') then -- no longer pressed
state_next <= state_key_debounce;
end if;
end if;
when state_key_debounce =>
if (my_key = '1') then
state_next <= state_wait_key;
end if;
when others=>
state_next <= state_wait_key;
end case;
if (bincnt_reg(3 downto 0) = "0000") then
case bincnt_reg(5 downto 4) is
when "11" =>
break_pressed_next <= not(keyboard_response(1)); --0x30
when "01" =>
shift_pressed_next <= not(keyboard_response(1)); --0x10
when "00" =>
control_pressed_next <= not(keyboard_response(1)); -- 0x00
when others =>
--
end case;
end if;
end if;
end process;
-- outputs
keyboard_scan <= not(bincnt_reg);
key_held <= key_held_reg;
keycode <= keycode_latch_reg;
break_pressed <= break_pressed_reg;
shift_pressed <= shift_pressed_reg;
control_pressed <= control_pressed_reg;
other_key_irq <= irq_reg;
end vhdl;
|
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLAH8bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
SomaResult:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END CLAH8bits;
ARCHITECTURE strc_CLAH8bits of CLAH8bits is
SIGNAL Cin_sig, Cout_sig, P0_sig, P1_sig, G0_sig, G1_sig: STD_LOGIC;
SIGNAL Cout_temp_sig: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SomaT1,SomaT2:STD_LOGIC_VECTOR(3 DOWNTO 0);
Component CLA4bits
PORT (
val1,val2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
end component;
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg8Bit
PORT (
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end component;
Component CLGB
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
end component;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>Cin_sig
);
Reg_A: Reg8Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg8Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cout_sig,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg8Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
Som1: CLA4bits PORT MAP(
val1(3 DOWNTO 0) => A_sig(3 DOWNTO 0),
val2(3 DOWNTO 0) => B_sig(3 DOWNTO 0),
CarryIn=>Cin_sig,
P=>P0_sig,
G=>G0_sig,
SomaResult=>SomaT1
);
CLGB1: CLGB PORT MAP(
P0=>P0_sig,
G0=>G0_sig,
P1=>P1_sig,
G1=>G1_sig,
Cin=>Cin_sig,
Cout1=>Cout_temp_sig,
Cout2=>Cout_sig
);
Som2: CLA4bits PORT MAP(
val1(3 DOWNTO 0) => A_sig(7 DOWNTO 4),
val2(3 DOWNTO 0) => B_sig(7 DOWNTO 4),
CarryIn=>Cout_temp_sig,
P=>P1_sig,
G=>G1_sig,
SomaResult=>SomaT2
);
Out_sig <= SomaT2 & SomaT1;
END strc_CLAH8bits; |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator is
generic (
g_divider : integer := 5 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
h_sync : in std_logic;
v_sync : in std_logic;
pixel_active : out std_logic;
pixel_data : out std_logic;
sync_out_n : out std_logic );
end entity;
architecture structural of char_generator is
signal clock_en : std_logic;
signal control : t_chargen_control;
signal screen_addr : unsigned(10 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
begin
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
control => control );
i_timing: entity work.char_generator_timing
generic map (
g_divider => g_divider )
port map (
clock => clock,
reset => reset,
h_sync => h_sync,
v_sync => v_sync,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_data => pixel_data,
clock_en => clock_en,
sync_n => sync_out_n );
i_rom: entity work.char_generator_rom
port map (
clock => clock,
enable => clock_en,
address => char_addr,
data => char_data );
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
screen_data <= std_logic_vector(screen_addr(7 downto 0));
end if;
end if;
end process;
-- i_ram: entity work.char_generator_rom
-- port map (
-- clock => clock,
-- enable => clock_en,
-- address => screen_addr,
-- data => screen_data );
end structural;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator is
generic (
g_divider : integer := 5 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
h_sync : in std_logic;
v_sync : in std_logic;
pixel_active : out std_logic;
pixel_data : out std_logic;
sync_out_n : out std_logic );
end entity;
architecture structural of char_generator is
signal clock_en : std_logic;
signal control : t_chargen_control;
signal screen_addr : unsigned(10 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
begin
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
control => control );
i_timing: entity work.char_generator_timing
generic map (
g_divider => g_divider )
port map (
clock => clock,
reset => reset,
h_sync => h_sync,
v_sync => v_sync,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_data => pixel_data,
clock_en => clock_en,
sync_n => sync_out_n );
i_rom: entity work.char_generator_rom
port map (
clock => clock,
enable => clock_en,
address => char_addr,
data => char_data );
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
screen_data <= std_logic_vector(screen_addr(7 downto 0));
end if;
end if;
end process;
-- i_ram: entity work.char_generator_rom
-- port map (
-- clock => clock,
-- enable => clock_en,
-- address => screen_addr,
-- data => screen_data );
end structural;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator is
generic (
g_divider : integer := 5 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
h_sync : in std_logic;
v_sync : in std_logic;
pixel_active : out std_logic;
pixel_data : out std_logic;
sync_out_n : out std_logic );
end entity;
architecture structural of char_generator is
signal clock_en : std_logic;
signal control : t_chargen_control;
signal screen_addr : unsigned(10 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
begin
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
control => control );
i_timing: entity work.char_generator_timing
generic map (
g_divider => g_divider )
port map (
clock => clock,
reset => reset,
h_sync => h_sync,
v_sync => v_sync,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_data => pixel_data,
clock_en => clock_en,
sync_n => sync_out_n );
i_rom: entity work.char_generator_rom
port map (
clock => clock,
enable => clock_en,
address => char_addr,
data => char_data );
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
screen_data <= std_logic_vector(screen_addr(7 downto 0));
end if;
end if;
end process;
-- i_ram: entity work.char_generator_rom
-- port map (
-- clock => clock,
-- enable => clock_en,
-- address => screen_addr,
-- data => screen_data );
end structural;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator is
generic (
g_divider : integer := 5 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
h_sync : in std_logic;
v_sync : in std_logic;
pixel_active : out std_logic;
pixel_data : out std_logic;
sync_out_n : out std_logic );
end entity;
architecture structural of char_generator is
signal clock_en : std_logic;
signal control : t_chargen_control;
signal screen_addr : unsigned(10 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
begin
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
control => control );
i_timing: entity work.char_generator_timing
generic map (
g_divider => g_divider )
port map (
clock => clock,
reset => reset,
h_sync => h_sync,
v_sync => v_sync,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_data => pixel_data,
clock_en => clock_en,
sync_n => sync_out_n );
i_rom: entity work.char_generator_rom
port map (
clock => clock,
enable => clock_en,
address => char_addr,
data => char_data );
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
screen_data <= std_logic_vector(screen_addr(7 downto 0));
end if;
end if;
end process;
-- i_ram: entity work.char_generator_rom
-- port map (
-- clock => clock,
-- enable => clock_en,
-- address => screen_addr,
-- data => screen_data );
end structural;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator is
generic (
g_divider : integer := 5 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
h_sync : in std_logic;
v_sync : in std_logic;
pixel_active : out std_logic;
pixel_data : out std_logic;
sync_out_n : out std_logic );
end entity;
architecture structural of char_generator is
signal clock_en : std_logic;
signal control : t_chargen_control;
signal screen_addr : unsigned(10 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
begin
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
control => control );
i_timing: entity work.char_generator_timing
generic map (
g_divider => g_divider )
port map (
clock => clock,
reset => reset,
h_sync => h_sync,
v_sync => v_sync,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_data => pixel_data,
clock_en => clock_en,
sync_n => sync_out_n );
i_rom: entity work.char_generator_rom
port map (
clock => clock,
enable => clock_en,
address => char_addr,
data => char_data );
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
screen_data <= std_logic_vector(screen_addr(7 downto 0));
end if;
end if;
end process;
-- i_ram: entity work.char_generator_rom
-- port map (
-- clock => clock,
-- enable => clock_en,
-- address => screen_addr,
-- data => screen_data );
end structural;
|
package error2 is
subtype char128 is character range (NUL to DEL); -- Error
-- Crash here
constant k : string := IfElse(false, "Status: " & IfElse(true, "PASSED", "FAILED") & LF, "");
end package;
|
--
-- synthesis test 3:
-- * with clock enable
-- * fast
--
--
-- Altera EP2C-8, Quartus 8.0: 286 LEs,0 bits mem, fmax = 295 MHz (320 requested)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw3_grain128 is
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of hw3_grain128 is
begin
top: entity work.grain128
generic map (
DEBUG => false,
FAST => true
)
port map (
CLK_I => CLK_I,
CLKEN_I => CLKEN_I,
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INIT_I=> INIT_I,
KEYSTREAM_O => KEYSTREAM_O,
KEYSTREAM_VALID_O => KEYSTREAM_VALID_O
);
end behav;
|
-------------------------------------------------------------------------------
-- my_core_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_scheduler_tb_v1_00_a;
use plb_scheduler_tb_v1_00_a.all;
entity my_core_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end my_core_wrapper;
architecture STRUCTURE of my_core_wrapper is
component plb_scheduler_tb is
generic (
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_AWIDTH : integer;
C_SPLB_DWIDTH : integer;
C_SPLB_NUM_MASTERS : integer;
C_SPLB_MID_WIDTH : integer;
C_SPLB_NATIVE_DWIDTH : integer;
C_SPLB_P2P : integer;
C_SPLB_SUPPORT_BURSTS : integer;
C_SPLB_SMALLEST_MASTER : integer;
C_SPLB_CLK_PERIOD_PS : integer;
C_INCLUDE_DPHASE_TIMER : integer;
C_FAMILY : string;
C_MPLB_AWIDTH : integer;
C_MPLB_DWIDTH : integer;
C_MPLB_NATIVE_DWIDTH : integer;
C_MPLB_P2P : integer;
C_MPLB_SMALLEST_SLAVE : integer;
C_MPLB_CLK_PERIOD_PS : integer
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to (31));
PLB_UABus : in std_logic_vector(0 to (31));
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8-1));
PLB_MSize : in std_logic_vector(0 to (1));
PLB_size : in std_logic_vector(0 to (3));
PLB_type : in std_logic_vector(0 to (2));
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to (1));
PLB_rdPendPri : in std_logic_vector(0 to (1));
PLB_reqPri : in std_logic_vector(0 to (1));
PLB_TAttribute : in std_logic_vector(0 to (15));
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to (1));
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to (3));
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to (1));
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to (C_MPLB_DWIDTH/8-1));
M_MSize : out std_logic_vector(0 to (1));
M_size : out std_logic_vector(0 to (3));
M_type : out std_logic_vector(0 to (2));
M_TAttribute : out std_logic_vector(0 to (15));
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to (31));
M_ABus : out std_logic_vector(0 to (31));
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to (1));
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to ((C_MPLB_DWIDTH-1)));
PLB_MRdWdAddr : in std_logic_vector(0 to (3));
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
begin
my_core : plb_scheduler_tb
generic map (
C_BASEADDR => X"30000000",
C_HIGHADDR => X"3000ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 128,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_SUPPORT_BURSTS => 0,
C_SPLB_SMALLEST_MASTER => 32,
C_SPLB_CLK_PERIOD_PS => 10000,
C_INCLUDE_DPHASE_TIMER => 0,
C_FAMILY => "virtex5",
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 128,
C_MPLB_NATIVE_DWIDTH => 32,
C_MPLB_P2P => 0,
C_MPLB_SMALLEST_SLAVE => 32,
C_MPLB_CLK_PERIOD_PS => 10000
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
SYNCH_IN => SYNCH_IN,
SYNCH_OUT => SYNCH_OUT
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- my_core_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_scheduler_tb_v1_00_a;
use plb_scheduler_tb_v1_00_a.all;
entity my_core_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end my_core_wrapper;
architecture STRUCTURE of my_core_wrapper is
component plb_scheduler_tb is
generic (
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_AWIDTH : integer;
C_SPLB_DWIDTH : integer;
C_SPLB_NUM_MASTERS : integer;
C_SPLB_MID_WIDTH : integer;
C_SPLB_NATIVE_DWIDTH : integer;
C_SPLB_P2P : integer;
C_SPLB_SUPPORT_BURSTS : integer;
C_SPLB_SMALLEST_MASTER : integer;
C_SPLB_CLK_PERIOD_PS : integer;
C_INCLUDE_DPHASE_TIMER : integer;
C_FAMILY : string;
C_MPLB_AWIDTH : integer;
C_MPLB_DWIDTH : integer;
C_MPLB_NATIVE_DWIDTH : integer;
C_MPLB_P2P : integer;
C_MPLB_SMALLEST_SLAVE : integer;
C_MPLB_CLK_PERIOD_PS : integer
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to (31));
PLB_UABus : in std_logic_vector(0 to (31));
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8-1));
PLB_MSize : in std_logic_vector(0 to (1));
PLB_size : in std_logic_vector(0 to (3));
PLB_type : in std_logic_vector(0 to (2));
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to (1));
PLB_rdPendPri : in std_logic_vector(0 to (1));
PLB_reqPri : in std_logic_vector(0 to (1));
PLB_TAttribute : in std_logic_vector(0 to (15));
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to (1));
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to (3));
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to (1));
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to (C_MPLB_DWIDTH/8-1));
M_MSize : out std_logic_vector(0 to (1));
M_size : out std_logic_vector(0 to (3));
M_type : out std_logic_vector(0 to (2));
M_TAttribute : out std_logic_vector(0 to (15));
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to (31));
M_ABus : out std_logic_vector(0 to (31));
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to (1));
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to ((C_MPLB_DWIDTH-1)));
PLB_MRdWdAddr : in std_logic_vector(0 to (3));
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
begin
my_core : plb_scheduler_tb
generic map (
C_BASEADDR => X"30000000",
C_HIGHADDR => X"3000ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 128,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_SUPPORT_BURSTS => 0,
C_SPLB_SMALLEST_MASTER => 32,
C_SPLB_CLK_PERIOD_PS => 10000,
C_INCLUDE_DPHASE_TIMER => 0,
C_FAMILY => "virtex5",
C_MPLB_AWIDTH => 32,
C_MPLB_DWIDTH => 128,
C_MPLB_NATIVE_DWIDTH => 32,
C_MPLB_P2P => 0,
C_MPLB_SMALLEST_SLAVE => 32,
C_MPLB_CLK_PERIOD_PS => 10000
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
SYNCH_IN => SYNCH_IN,
SYNCH_OUT => SYNCH_OUT
);
end architecture STRUCTURE;
|
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 01/11/2018 04:18:22 PM
-- Module Name: writeback - Behavioral
-- Description: Writeback shift register
--
-- Additional Comments:
-- This is an output buffer for the ALU stage for the control unit. This is included
-- to allow a simple two-bit control of writeback data.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
entity writeback is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- System reset
halt: in std_logic; -- Do nothing when high
ready_input: in std_logic; -- Control has data to be written back
ready_output: in std_logic; -- MMU is ready to accept data
output_OK: out std_logic; -- Write data and address are valid
input_OK: out std_logic; -- Read data and address recorded
input_data: in doubleword; -- Data from previous stage
input_address: in word; -- MMU Destination for input data
output_data: out doubleword; -- Data to be written to MMU
output_address: out word -- MMU destination for output data
);
end writeback;
architecture Behavioral of writeback is
-- Two states represent waiting or not waiting to dump the registers
-- Moore machine with inputs read, write, and halt, synchronous reset
type state is (state_idle, state_writing);
signal curr_state: state;
signal next_state: state;
signal last_data: doubleword;
signal last_addr: word;
signal s_output_ack: std_logic;
signal s_input_ack: std_logic;
begin
-- Advance State
process(clk, rst)
begin
if(rising_edge(clk)) then
if('1' = rst) then
curr_state <= state_idle;
else
curr_state <= next_state;
end if;
end if;
end process;
-- Compute outputs
-- Needs to be sensitive to clock in case MMU stalls, we
-- want to check for updates at each rising edge
process(clk, rst, curr_state)
begin
if(rising_edge(clk)) then
input_OK <= '0';
output_OK <= '0';
output_data <= last_data;
output_address <= last_addr;
next_state <= curr_state;
if('1' = rst) then
last_data <= (others => '0');
last_addr <= (others => '0');
output_data <= (others => '0');
output_address <= (others => '0');
next_state <= state_idle;
elsif('0' = halt) then -- Do nothing unless halt is low
case curr_state is
when state_writing => -- Case pending write
output_OK <= '1'; -- signal MMU data is valid
if('1' = ready_output) then -- Case MMU ready for data
next_state <= state_idle; -- Transition to idle state to get more input
end if;
when state_idle => -- Case no pending write
if('1' = ready_input) then -- Case control has new data
last_addr <= input_address; -- Update latches
last_data <= input_data;
input_OK <= '1'; -- signal control that data is accepted
next_state <= state_writing; -- Transition to write pending state
end if;
end case;
end if; -- rst/halt
end if; -- rising edge
end process;
end Behavioral;
|
--*****************************************************************************
-- @Copyright 2013 by SIAT_HFUS_TEAM, All rights reserved.
-- Module name : ADS58C48
-- Call by :
-- Description : this module is the top module of ADS58C48.
-- IC : 5CGXFC7D7F31C8N
-- Version : A
-- Note: :
-- Author : Peitian Mu
-- Date : 2013.12.02
-- Update :
--*****************************************************************************
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity ADS58C48 is
port
(
O_adca_sen : out std_logic;
I_adca_sd : in std_logic;
O_adca_sdata : out std_logic;
O_adca_sclk : out std_logic;
O_adca_rst : out std_logic;
O_adca_pdn : out std_logic;
O_adca_snrb0 : out std_logic;
O_adca_snrb1 : out std_logic;
I_adca_oclk : in std_logic;
I_adca_d : in std_logic_vector(5 downto 0);
I_adcb_d : in std_logic_vector(5 downto 0);
I_adcc_d : in std_logic_vector(5 downto 0);
I_adcd_d : in std_logic_vector(5 downto 0);
O_adca_data : out std_logic_vector(11 downto 0);
O_adcb_data : out std_logic_vector(11 downto 0);
O_adcc_data : out std_logic_vector(11 downto 0);
O_adcd_data : out std_logic_vector(11 downto 0)
);
end ADS58C48;
architecture rtl of ADS58C48 is
component ADC_DDIO
port(
datain : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
inclock : IN STD_LOGIC ;
dataout_h : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component;
signal S_adca_ad_12 : std_logic_vector(11 downto 0);
signal S_adcb_ad_12 : std_logic_vector(11 downto 0);
signal S_adcc_ad_12 : std_logic_vector(11 downto 0);
signal S_adcd_ad_12 : std_logic_vector(11 downto 0);
begin
U0_ddio_in_a: ADC_DDIO
port map(
datain => I_adca_d,
inclock => I_adca_oclk,
dataout_h => S_adca_ad_12(11 downto 6),
dataout_l => S_adca_ad_12(5 downto 0)
);
O_adca_data(11) <= S_adca_ad_12(11);
O_adca_data(10) <= S_adca_ad_12(5);
O_adca_data(9) <= S_adca_ad_12(10);
O_adca_data(8) <= S_adca_ad_12(4);
O_adca_data(7) <= S_adca_ad_12(9);
O_adca_data(6) <= S_adca_ad_12(3);
O_adca_data(5) <= S_adca_ad_12(8);
O_adca_data(4) <= S_adca_ad_12(2);
O_adca_data(3) <= S_adca_ad_12(7);
O_adca_data(2) <= S_adca_ad_12(1);
O_adca_data(1) <= S_adca_ad_12(6);
O_adca_data(0) <= S_adca_ad_12(0);
U1_ddio_in_b: ADC_DDIO
port map(
datain => I_adcb_d,
inclock => I_adca_oclk,
dataout_h => S_adcb_ad_12(11 downto 6),
dataout_l => S_adcb_ad_12(5 downto 0)
);
O_adcb_data(11) <= S_adcb_ad_12(11);
O_adcb_data(10) <= S_adcb_ad_12(5);
O_adcb_data(9) <= S_adcb_ad_12(10);
O_adcb_data(8) <= S_adcb_ad_12(4);
O_adcb_data(7) <= S_adcb_ad_12(9);
O_adcb_data(6) <= S_adcb_ad_12(3);
O_adcb_data(5) <= S_adcb_ad_12(8);
O_adcb_data(4) <= S_adcb_ad_12(2);
O_adcb_data(3) <= S_adcb_ad_12(7);
O_adcb_data(2) <= S_adcb_ad_12(1);
O_adcb_data(1) <= S_adcb_ad_12(6);
O_adcb_data(0) <= S_adcb_ad_12(0);
U2_ddio_in_c: ADC_DDIO
port map(
datain => I_adcc_d,
inclock => I_adca_oclk,
dataout_h => S_adcc_ad_12(11 downto 6),
dataout_l => S_adcc_ad_12(5 downto 0)
);
O_adcc_data(11) <= S_adcc_ad_12(11);
O_adcc_data(10) <= S_adcc_ad_12(5);
O_adcc_data(9) <= S_adcc_ad_12(10);
O_adcc_data(8) <= S_adcc_ad_12(4);
O_adcc_data(7) <= S_adcc_ad_12(9);
O_adcc_data(6) <= S_adcc_ad_12(3);
O_adcc_data(5) <= S_adcc_ad_12(8);
O_adcc_data(4) <= S_adcc_ad_12(2);
O_adcc_data(3) <= S_adcc_ad_12(7);
O_adcc_data(2) <= S_adcc_ad_12(1);
O_adcc_data(1) <= S_adcc_ad_12(6);
O_adcc_data(0) <= S_adcc_ad_12(0);
U3_ddio_in_d: ADC_DDIO
port map(
datain => I_adcd_d,
inclock => I_adca_oclk,
dataout_h => S_adcd_ad_12(11 downto 6),
dataout_l => S_adcd_ad_12(5 downto 0)
);
O_adcd_data(11) <= S_adcd_ad_12(11);
O_adcd_data(10) <= S_adcd_ad_12(5);
O_adcd_data(9) <= S_adcd_ad_12(10);
O_adcd_data(8) <= S_adcd_ad_12(4);
O_adcd_data(7) <= S_adcd_ad_12(9);
O_adcd_data(6) <= S_adcd_ad_12(3);
O_adcd_data(5) <= S_adcd_ad_12(8);
O_adcd_data(4) <= S_adcd_ad_12(2);
O_adcd_data(3) <= S_adcd_ad_12(7);
O_adcd_data(2) <= S_adcd_ad_12(1);
O_adcd_data(1) <= S_adcd_ad_12(6);
O_adcd_data(0) <= S_adcd_ad_12(0);
end rtl;
|
--ovo su komentari
--trebali bi biti zanemareni
ENTITY Adder_4_bit IS PORT(
x: in std_logic_vector(3 downto 0); --prvi broj
y: in std_logic_vector(3 downto 0); -- drugi broj
cin: in std_logic;
sum: out std_logic_vector(3 downto 0);
cout: out std_logic
);
END Adder_4_bit;
architecture arch OF Adder_4_bit IS
signal carry: std_logic_vector(2 downto 0);
BEGIN
a_1: ENTITY work.Adder_1_bit port map (x(0), y(0), cin, sum(0), carry(0));
a_2: ENTITY work.Adder_1_bit port map (x(1), y(1), carry(0), sum(1), carry(1));
a_3: ENTITY work.Adder_1_bit port map (x(2), y(2), carry(1), sum(2), carry(2));
a_4: ENTITY work.Adder_1_bit port map (x(3), y(3), carry(2), sum(3), cout);
END arch;
--kraj |
-------------------------------------------------------------------------------
-- Title : Strobe generator
-- Project :
-------------------------------------------------------------------------------
-- File : strobe_gen.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-11
-- Last update: 2014-06-20
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Generates strobes at decimation rate for CIC filter
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-11 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.dsp_cores_pkg.all;
-------------------------------------------------------------------------------
entity strobe_gen is
generic (
g_maxrate : natural := 2048;
g_bus_width : natural := 11
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
ratio_i : in std_logic_vector(g_bus_width-1 downto 0);
strobe_o : out std_logic
);
end entity strobe_gen;
-------------------------------------------------------------------------------
architecture str of strobe_gen is
--signal zeroed : std_logic := '0';
begin -- architecture str
cmp_xlclockdriver : xlclockdriver
generic map (
period => g_maxrate,
log_2_period => g_bus_width
)
port map (
sysclk => clk_i,
sysclr => rst_i,
sysce => ce_i,
clk => open,
clr => open,
ce => strobe_o,
ce_logic => open
);
--counting : process(clk_i )
-- variable count : natural := 0;
--begin
-- if rising_edge(clk_i ) then
-- if rst_i = '1' then
-- count := to_integer(unsigned(ratio_i))-1;
-- else
-- if ce_i = '1' then
-- if count = 0 then
-- count := to_integer(unsigned(ratio_i))-1;
-- zeroed <= '1';
-- else
-- count := count - 1;
-- zeroed <= '0';
-- end if; --count = 0
-- end if; -- ce
-- end if; -- reset
-- end if; -- rising_edge
--end process counting;
--strobe_o <= zeroed;
end architecture str;
-------------------------------------------------------------------------------
|
architecture RTL of FIFO is
attribute coordinate of OTHERS : component is (0.0, 17.5);
attribute coordinate of OTHERS :component is (0.0, 17.5);
begin
end architecture RTL;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
LIBRARY RS232_test;
USE RS232_test.RS232_test.all;
entity PICtop_tb is
end PICtop_tb;
architecture TestBench of PICtop_tb is
component PICtop
port (
Reset : in std_logic;
Clk : in std_logic;
RS232_RX : in std_logic;
RS232_TX : out std_logic;
switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0));
end component;
-----------------------------------------------------------------------------
-- Internal signals
-----------------------------------------------------------------------------
signal Reset : std_logic;
signal Clk : std_logic;
signal RS232_RX : std_logic;
signal RS232_TX : std_logic;
signal switches : std_logic_vector(7 downto 0);
signal Temp_L : std_logic_vector(6 downto 0);
signal Temp_H : std_logic_vector(6 downto 0);
begin -- TestBench
UUT: PICtop
port map (
Reset => Reset,
Clk => Clk,
RS232_RX => RS232_RX,
RS232_TX => RS232_TX,
switches => switches,
Temp_L => Temp_L,
Temp_H => Temp_H);
-----------------------------------------------------------------------------
-- Reset & clock generator
-----------------------------------------------------------------------------
Reset <= '0', '1' after 75 ns;
p_clk : PROCESS
BEGIN
clk <= '1', '0' after 25 ns;
wait for 50 ns;
END PROCESS;
-------------------------------------------------------------------------------
-- Sending some stuff through RS232 port
-------------------------------------------------------------------------------
SEND_STUFF : process
begin
RS232_RX <= '1';
wait for 40 us;
Transmit(RS232_RX, X"49");
wait for 40 us;
Transmit(RS232_RX, X"34");
wait for 40 us;
Transmit(RS232_RX, X"31");
wait;
end process SEND_STUFF;
end TestBench;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1283.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01283ent IS
END c08s04b00x00p04n01i01283ent;
ARCHITECTURE c08s04b00x00p04n01i01283arch OF c08s04b00x00p04n01i01283ent IS
type INIT_1 is (ONE, TWO, THREE);
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
INIT_1'(S1) <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01283 - Qualified expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01283arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1283.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01283ent IS
END c08s04b00x00p04n01i01283ent;
ARCHITECTURE c08s04b00x00p04n01i01283arch OF c08s04b00x00p04n01i01283ent IS
type INIT_1 is (ONE, TWO, THREE);
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
INIT_1'(S1) <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01283 - Qualified expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01283arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1283.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01283ent IS
END c08s04b00x00p04n01i01283ent;
ARCHITECTURE c08s04b00x00p04n01i01283arch OF c08s04b00x00p04n01i01283ent IS
type INIT_1 is (ONE, TWO, THREE);
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
INIT_1'(S1) <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01283 - Qualified expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01283arch;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
);
end;
architecture behavior of Arbiter is
-- next
-- Arbiter router or NI
-- --- ---------------------------- ---- ----
-- from LBDR ---> |Req(s) RTS | -----> |DRTS
-- To FIFO <--- |Grant(s) DCTS| <----- |CTS
-- to XBAR <--- |Xbar_sel | |
-- --- ---------------------------- ---- ----
--------------------------------------------------------------------------------------------
-- an example of a request/grant + handshake process with next router or NI
--CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__
-- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________
-- _________ ___________________ _______ _______ _______ ____
-- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____
-- Grant _________________________|'''|___|'''|___|'''|____________
-- RTS _________|'''''''''''''''''''|___|'''''''|___|'''''''|____
-- DCTS _________________________|'''|_______|'''|_______|'''|____ (CTS (DCTS) is always maximum 1 clock cycle!)
-- |<---------clear----------->|
-- | to send |
--------------------------------------------------------------------------------------------
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
begin
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in;
RTS_FF <= RTS_FF_in;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin
Grant_N <= '0';
Grant_E <= '0';
Grant_W <= '0';
Grant_S <= '0';
Grant_L <= '0';
Xbar_sel<= "00000";
case(state) is
when IDLE =>
Xbar_sel<= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N <= DCTS and RTS_FF ;
Xbar_sel<= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E <= DCTS and RTS_FF;
Xbar_sel<= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W <= DCTS and RTS_FF;
Xbar_sel<= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S <= DCTS and RTS_FF;
Xbar_sel<= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L <= DCTS and RTS_FF;
Xbar_sel<= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
|
-------------------------------------------------------------------------------
-- Entity: mcu
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Top-level description of a simple von-Neumann MCU.
-- All top-level component are instantiated here. Also, tri-state buffers for
-- bi-directional GPIO pins are described here.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity mcu is
generic(CLK_FRQ : natural := CF
);
port(rst : in std_logic;
clk : in std_logic;
-- LED(8:0) on S3E-Board (demonstrate tri-state buffers)
LED : inout std_logic_vector(7 downto 0);
-- SW(3:0) on S3E-Board
Switch : in std_logic_vector(3 downto 0);
-- 3 pins per FMC channels
fmc_enable : out std_logic_vector(FMC_NUM_CHN-1 downto 0);
fmc_direct : out std_logic_vector(FMC_NUM_CHN-1 downto 0);
fmc_step : out std_logic_vector(FMC_NUM_CHN-1 downto 0)
);
end mcu;
architecture rtl of mcu is
-- CPU signals
signal cpu2bus : t_cpu2bus;
signal bus2cpu : t_bus2cpu;
-- ROM signals
signal bus2rom : t_bus2ros;
signal rom2bus : t_ros2bus;
-- ROM signals
signal bus2ram : t_bus2rws;
signal ram2bus : t_rws2bus;
-- GPIO signals
signal bus2gpio : t_bus2rws;
signal gpio2bus : t_rws2bus;
signal gpio_in : std_logic_vector(DW-1 downto 0);
signal gpio_out : std_logic_vector(DW-1 downto 0);
signal gpio_out_enb : std_logic_vector(DW-1 downto 0);
-- FMC signals
signal bus2fmc : t_bus2rws;
signal fmc2bus : t_rws2bus;
begin
-----------------------------------------------------------------------------
-- Connect GPIO(7:0) to LED(7:0)
-- Demonstrates the usage of tri-state buffers although this not required for
-- LED functionality.
-----------------------------------------------------------------------------
gpio_in(7 downto 0) <= LED;
gen_led_3state: for k in 0 to 7 generate
LED(k) <= gpio_out(k) when gpio_out_enb(k) = '1' else 'Z';
end generate;
-----------------------------------------------------------------------------
-- Connect SW(3:0) to GPIO(11:8)
-- NOTE: GPIO(11:8) is only connected as input, since the SITE TYPE of the 4
-- Switch pins is IBUF, which prevents the usage of tri-state IOBs.
-- Furthermore, even if IOBs were available, it would be dangerous to
-- use them here, since a wrong SW configuration could then cause
-- driver conflicts on these pins!!
-----------------------------------------------------------------------------
gpio_in(11 downto 8) <= Switch;
-- gen_sw_3state: for k in 8 to 11 generate
-- SW(k-8) <= gpio_out(k) when gpio_out_enb(k) = '1' else 'Z';
-- end generate;
-----------------------------------------------------------------------------
-- Instantiation of top-level components (assumed to be in library work)
-----------------------------------------------------------------------------
-- CPU ----------------------------------------------------------------------
i_cpu: entity work.cpu
port map(
rst => rst,
clk => clk,
bus_in => bus2cpu,
bus_out => cpu2bus
);
-- BUS ----------------------------------------------------------------------
i_bus: entity work.buss
port map(
rst => rst,
clk => clk,
cpu_in => cpu2bus,
cpu_out => bus2cpu,
rom_in => rom2bus,
rom_out => bus2rom,
ram_in => ram2bus,
ram_out => bus2ram,
gpio_in => gpio2bus,
gpio_out => bus2gpio,
fmc_in => fmc2bus,
fmc_out => bus2fmc
);
-- ROM ----------------------------------------------------------------------
i_rom: entity work.rom
port map(
clk => clk,
bus_in => bus2rom,
bus_out => rom2bus
);
-- RAM ----------------------------------------------------------------------
i_ram: entity work.ram
port map(
clk => clk,
bus_in => bus2ram,
bus_out => ram2bus
);
-- GPIO ---------------------------------------------------------------------
i_gpio: entity work.gpio
port map(
rst => rst,
clk => clk,
bus_in => bus2gpio,
bus_out => gpio2bus,
gpio_in => gpio_in,
gpio_out => gpio_out,
gpio_out_enb => gpio_out_enb
);
-- FMC ----------------------------------------------------------------------
i_fmc: entity work.fmc_top
generic map(CLK_FRQ => CLK_FRQ)
port map(
rst => rst,
clk => clk,
bus_in => bus2fmc,
bus_out => fmc2bus,
fmc_enable => fmc_enable,
fmc_direct => fmc_direct,
fmc_step => fmc_step
);
end rtl;
|
--
---- SPI Module - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_mode_0_module.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg;
use lib_pkg_v1_0.lib_pkg.log2;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------:
-- C_SCK_RATIO -- 2, 4, 16, 32, , , , 1024, 2048 SPI
-- clock ratio (16*N), where N=1,2,3...
-- C_SPI_NUM_BITS_REG -- Width of SPI Control register
-- in this module
-- C_NUM_SS_BITS -- Total number of SS-bits
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- OTHER INTERFACE
-- Slave_MODF_strobe -- Slave mode fault strobe
-- MODF_strobe -- Mode fault strobe
-- SR_3_MODF -- Mode fault error flag
-- SR_5_Tx_Empty -- Transmit Empty
-- Control_Reg -- Control Register
-- Slave_Select_Reg -- Slave Select Register
-- Transmit_Data -- Data Transmit Register Interface
-- Receive_Data -- Data Receive Register Interface
-- SPIXfer_done -- SPI transfer done flag
-- DTR_underrun -- DTR underrun generation signal
-- SPI INTERFACE
-- SCK_I -- SPI Bus Clock Input
-- SCK_O_reg -- SPI Bus Clock Output
-- SCK_T -- SPI Bus Clock 3-state Enable
-- (3-state when high)
-- MISO_I -- Master out,Slave in Input
-- MISO_O -- Master out,Slave in Output
-- MISO_T -- Master out,Slave in 3-state Enable
-- MOSI_I -- Master in,Slave out Input
-- MOSI_O -- Master in,Slave out Output
-- MOSI_T -- Master in,Slave out 3-state Enable
-- SPISEL -- Local SPI slave select active low input
-- has to be initialzed to VCC
-- SS_I -- Input of slave select vector
-- of length N input where there are
-- N SPI devices,but not connected
-- SS_O -- One-hot encoded,active low slave select
-- vector of length N ouput
-- SS_T -- Single 3-state control signal for
-- slave select vector of length N
-- (3-state when high)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_mode_0_module is
generic
(
--C_SPI_MODE : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_USE_STARTUP : integer;
C_SPICR_REG_WIDTH : integer;
C_SUB_FAMILY : string;
C_FIFO_EXIST : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
----------------------
-- Control Reg is 10-bit wide
SPICR_0_LOOP : in std_logic;
SPICR_1_SPE : in std_logic;
SPICR_2_MASTER_N_SLV : in std_logic;
SPICR_3_CPOL : in std_logic;
SPICR_4_CPHA : in std_logic;
SPICR_5_TXFIFO_RST : in std_logic;
SPICR_6_RXFIFO_RST : in std_logic;
SPICR_7_SS : in std_logic;
SPICR_8_TR_INHIBIT : in std_logic;
SPICR_9_LSB : in std_logic;
----------------------
SR_3_MODF : in std_logic;
SR_5_Tx_Empty : in std_logic;
Slave_MODF_strobe : out std_logic;
MODF_strobe : out std_logic;
SPIXfer_done_rd_tx_en: out std_logic;
Slave_Select_Reg : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Receive_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
SPIXfer_done : out std_logic;
DTR_underrun : out std_logic;
SPISEL_pulse_op : out std_logic;
SPISEL_d1_reg : out std_logic;
--SPI Interface
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
MISO_I : in std_logic;
MISO_O : out std_logic;
MISO_T : out std_logic;
MOSI_I : in std_logic;
MOSI_O : out std_logic;
MOSI_T : out std_logic;
SPISEL : in std_logic;
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
control_bit_7_8 : in std_logic_vector(0 to 1);
Mst_N_Slv_mode : out std_logic;
Rx_FIFO_Full : in std_logic;
reset_RcFIFO_ptr_to_spi : in std_logic;
DRR_Overrun_reg : out std_logic;
tx_cntr_xfer_done : out std_logic
);
end qspi_mode_0_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of qspi_mode_0_module is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function Declarations
---------------------------------------------------------------------
------------------------
-- spcl_log2 : Performs log2(x) function for value of C_SCK_RATIO > 2
------------------------
function spcl_log2(x : natural) return integer is
variable j : integer := 0;
variable k : integer := 0;
begin
if(C_SCK_RATIO /= 2) then
for i in 0 to 11 loop
if(2**i >= x) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
else
-- coverage off
return 2;
-- coverage on
end if;
end spcl_log2;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal Ratio_Count : std_logic_vector
(0 to (spcl_log2(C_SCK_RATIO))-2);
signal Count : std_logic_vector
(COUNT_WIDTH downto 0)
:= (others => '0');
signal LSB_first : std_logic;
signal Mst_Trans_inhibit : std_logic;
signal Manual_SS_mode : std_logic;
signal CPHA : std_logic;
signal CPOL : std_logic;
signal Mst_N_Slv : std_logic;
signal SPI_En : std_logic;
signal Loop_mode : std_logic;
signal transfer_start : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
signal sck_o_int : std_logic;
signal sck_o_in : std_logic;
signal Count_trigger : std_logic;
signal Count_trigger_d1 : std_logic;
signal Count_trigger_pulse : std_logic;
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal Serial_Dout : std_logic;
signal Serial_Din : std_logic;
signal Shift_Reg : std_logic_vector
(0 to C_NUM_TRANSFER_BITS-1);
signal SS_Asserted : std_logic;
signal SS_Asserted_1dly : std_logic;
signal Allow_Slave_MODF_Strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal Loading_SR_Reg_int : std_logic;
signal sck_i_d1 : std_logic;
signal spisel_d1 : std_logic;
signal spisel_pulse : std_logic;
signal rising_edge_sck_i : std_logic;
signal falling_edge_sck_i : std_logic;
signal edge_sck_i : std_logic;
signal MODF_strobe_int : std_logic;
signal master_tri_state_en_control: std_logic;
signal slave_tri_state_en_control: std_logic;
-- following signals are added for use in variouos clock ratio modes.
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal rx_shft_reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
-- added synchronization signals for SPISEL and SCK_I
signal SPISEL_sync : std_logic;
signal SCK_I_sync : std_logic;
-- following register are declared for making data path clear in different modes
signal rx_shft_reg_s : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0110 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal sck_fe1 : std_logic;
signal sck_d21 : std_logic:='0';
signal sck_d11 : std_logic:='0';
signal SCK_O_1 : std_logic:='0';
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal mosi_i_sync : std_logic;
signal miso_i_sync : std_logic;
signal serial_dout_int : std_logic;
--
attribute IOB : string;
--attribute IOB of SPI_TRISTATE_CONTROL_II : label is "true";
attribute IOB of SPI_TRISTATE_CONTROL_III : label is "false";
--attribute IOB of SPI_TRISTATE_CONTROL_IV : label is "true";
attribute IOB of SPI_TRISTATE_CONTROL_V : label is "false";
--attribute IOB of OTHER_RATIO_GENERATE : label is "true";
--attribute IOB of SCK_I_REG : label is "true";
--attribute IOB of SPISEL_REG : label is "true";
signal Mst_Trans_inhibit_d1, Mst_Trans_inhibit_pulse : std_logic;
signal no_slave_selected : std_logic;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
TRANSFER_OKAY,
TEMP_TRANSFER_OKAY
);
signal spi_cntrl_ps: STATE_TYPE;
signal spi_cntrl_ns: STATE_TYPE;
signal stop_clock_reg : std_logic;
signal stop_clock : std_logic;
signal Rx_FIFO_Full_reg, DRR_Overrun_reg_int : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal SR_5_Tx_Empty_d1 : std_logic;
signal SR_5_Tx_Empty_pulse: std_logic;
signal SR_5_Tx_comeplete_Empty : std_logic;
signal falling_edge_sck_i_d1, rising_edge_sck_i_d1 : std_logic;
signal spisel_d2 : std_logic;
signal xfer_done_fifo_0 : std_logic;
signal rst_xfer_done_fifo_0 : std_logic;
-------------------------------------------------------------------------------
-- Architecture Starts
-------------------------------------------------------------------------------
begin
--------------------------------------------------
LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----------------------------------------
TX_EMPTY_MODE_0_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) or
(transfer_start_pulse = '1') or
(rst_xfer_done_fifo_0 = '1')then
xfer_done_fifo_0 <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
xfer_done_fifo_0 <= '1';
end if;
end if;
end process TX_EMPTY_MODE_0_P;
------------------------------
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
-----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv,
stop_clock_reg,
spi_cntrl_ps,
no_slave_selected,
SR_5_Tx_Empty,
SPIXfer_done_int_pulse,
transfer_start_pulse,
xfer_done_fifo_0
)
begin
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
stop_clock <= '0';
spi_cntrl_ns <= TRANSFER_OKAY;
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
if(no_slave_selected = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
stop_clock <= xfer_done_fifo_0;
if (no_slave_selected = '1')then
spi_cntrl_ns <= IDLE;
--code coverage -- elsif(SPIXfer_done_int_pulse='1')then
--code coverage -- stop_clock <= SR_5_Tx_Empty;
--code coverage -- spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
-----------------------------------------------
end generate LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN;
-------------------------------------------------------------------------------
LOCAL_TX_EMPTY_FIFO_12_GEN: if C_FIFO_EXIST /= 0 generate
-----
begin
-----
xfer_done_fifo_0 <= '0';
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
----------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Rx_FIFO_Full_reg <= '0';
elsif(reset_RcFIFO_ptr_to_spi = '1') or (DRR_Overrun_reg_int = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(SPIXfer_done_int_pulse = '1')and (Rx_FIFO_Full = '1') then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv ,
stop_clock_reg ,
spi_cntrl_ps ,
no_slave_selected ,
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse ,
transfer_start_pulse ,
SPIXfer_done_int_pulse_d2,
SR_5_Tx_comeplete_Empty,
Loop_mode
)is
-----
begin
-----
stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
spi_cntrl_ns <= TRANSFER_OKAY;
stop_clock <= '0';
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
--if(no_slave_selected = '1')then
if(SR_5_Tx_comeplete_Empty = '1' and
SPIXfer_done_int_pulse_d2 = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if(SR_5_Tx_comeplete_Empty='1')then
-- stop_clock <= xfer_done_fifo_0;
if (Loop_mode = '1' and
SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
elsif(no_slave_selected = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
--stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
----------------------------------------
----------------------------------------
end generate LOCAL_TX_EMPTY_FIFO_12_GEN;
-----------------------------------------
SR_5_TX_EMPTY_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SR_5_Tx_Empty_d1 <= '0';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
end if;
end if;
end process SR_5_TX_EMPTY_PROCESS;
----------------------------------
SR_5_Tx_Empty_pulse <= SR_5_Tx_Empty_d1 and not (SR_5_Tx_Empty);
----------------------------------
-------------------------------------------------------------------------------
-- Combinatorial operations
-------------------------------------------------------------------------------
-----------------------------------------------------------
LSB_first <= SPICR_9_LSB; -- Control_Reg(0);
Mst_Trans_inhibit <= SPICR_8_TR_INHIBIT; -- Control_Reg(1);
Manual_SS_mode <= SPICR_7_SS; -- Control_Reg(2);
CPHA <= SPICR_4_CPHA; -- Control_Reg(5);
CPOL <= SPICR_3_CPOL; -- Control_Reg(6);
Mst_N_Slv <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
SPI_En <= SPICR_1_SPE; -- Control_Reg(8);
Loop_mode <= SPICR_0_LOOP; -- Control_Reg(9);
Mst_N_Slv_mode <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
-----------------------------------------------------------
MOSI_O <= Serial_Dout;
MISO_O <= Serial_Dout;
Receive_Data <= receive_Data_int;
DRR_Overrun_reg <= DRR_Overrun_reg_int;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full_reg and
SPIXfer_done_int_pulse; --_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
MST_TRANS_INHIBIT_D1_I: component FD
generic map
(
INIT => '1'
)
port map
(
Q => Mst_Trans_inhibit_d1,
C => Bus2IP_Clk,
D => Mst_Trans_inhibit
);
Mst_Trans_inhibit_pulse <= Mst_Trans_inhibit and (not Mst_Trans_inhibit_d1);
-------------------------------------------------------------------------------
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
master_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0') and --no mode fault
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_II : Tri-state register for SCK_T, ideal state-deactive
SPI_TRISTATE_CONTROL_II: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_III: tri-state register for MOSI, ideal state-deactive
SPI_TRISTATE_CONTROL_III: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MOSI_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_IV: tri-state register for SS,ideal state-deactive
SPI_TRISTATE_CONTROL_IV: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--* -------------------------------------------------------------------------------
--* -- SLAVE_TRIST_EN_PROCESS : If slave mode, then make tristate enabled
--* ---------------------------
slave_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='0') and -- decides master/slave
(control_bit_7_8(1)='1') and -- decide the spi_en
(SPISEL_sync = '0') and
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_V: tri-state register for MISO, ideal state-deactive
SPI_TRISTATE_CONTROL_V: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MISO_T,
C => Bus2IP_Clk,
D => slave_tri_state_en_control
);
-------------------------------------------------------------------------------
DTR_COMPLETE_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if(SR_5_Tx_Empty = '1' and SPIXfer_done_int_pulse = '1')then
SR_5_Tx_comeplete_Empty <= '1';
elsif(SR_5_Tx_Empty = '0')then
SR_5_Tx_comeplete_Empty <= '0';
end if;
end if;
end process DTR_COMPLETE_EMPTY_P;
---------------------------------
DTR_UNDERRUN_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
--if(SPIXfer_done_int_pulse_d2 = '1') then
DTR_underrun <= '1';
--end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_0_GEN;
DTR_UNDERRUN_FIFO_EXIST_GEN: if C_FIFO_EXIST /= 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
if(SPIXfer_done_int_pulse = '1') then
DTR_underrun <= '1';
end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_EXIST_GEN;
-------------------------------------------------------------------------------
-- SPISEL_SYNC: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
SPISEL_REG: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => Bus2IP_Clk,
D => SPISEL
);
---- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-------------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spisel_d1 <= '1';
spisel_d2 <= '1';
else
spisel_d1 <= SPISEL_sync;
spisel_d2 <= spisel_d1;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
--SPISEL_DELAY_1CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d1,
-- C => Bus2IP_Clk,
-- D => SPISEL_sync
-- );
--SPISEL_DELAY_2CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d2,
-- C => Bus2IP_Clk,
-- D => spisel_d1
-- );
---- spisel pulse generating logic
---- this one clock cycle pulse will be available for data loading into
---- shift register
--spisel_pulse <= (not SPISEL_sync) and spisel_d1;
------------------------------------------------
-- spisel pulse generating logic
-- this one clock cycle pulse will be available for data loading into
-- shift register
spisel_pulse <= (not spisel_d1) and spisel_d2;
-- --------|__________ -- SPISEL
-- ----------|________ -- SPISEL_sync
-- -------------|_____ -- spisel_d1
-- ----------------|___-- spisel_d2
-- _____________|--|__ -- SPISEL_pulse_op
SPISEL_pulse_op <= spisel_pulse;
SPISEL_d1_reg <= spisel_d2;
-------------------------------------------------------------------------------
--SCK_I_SYNC: first synchronize incomming signal
-------------
SCK_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => SCK_I_sync,
C => Bus2IP_Clk,
D => SCK_I
);
------------------------------------------------------------------
-- SCK_I_DELAY_1CLK_PROCESS : Detect active SCK edge in slave mode on +ve edge
SCK_I_DELAY_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
sck_i_d1 <= '0';
else
sck_i_d1 <= SCK_I_sync;
end if;
end if;
end process SCK_I_DELAY_1CLK_PROCESS;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_4_GEN: to synchronise the incoming clock signal in
-- slave mode in SCK ratio = 4
RISING_EDGE_CLK_RATIO_4_GEN : if C_SCK_RATIO = 4 generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I and (not(SCK_I_sync)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I) and SCK_I_sync) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_4_GEN;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_OTHERS_GEN: Due to timing crunch, in SCK> 4 mode,
-- the incoming clock signal cant be synchro
-- -nized with internal AXI clock.
-- slave mode operation on SCK_RATIO=2 isn't
-- supported in the core.
RISING_EDGE_CLK_RATIO_OTHERS_GEN: if ((C_SCK_RATIO /= 2) and (C_SCK_RATIO /= 4))
generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I_sync and (not(sck_i_d1)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I_sync) and sck_i_d1) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_OTHERS_GEN;
-------------------------------------------------------------------------------
-- combine rising edge as well as falling edge as a single signal
edge_sck_i <= rising_edge_sck_i or falling_edge_sck_i;
no_slave_selected <= and_reduce(Slave_Select_Reg(0 to (C_NUM_SS_BITS-1)));
-------------------------------------------------------------------------------
-- TRANSFER_START_PROCESS : Generate transfer start signal. When the transfer
-- gets completed, SPI Transfer done strobe pulls
-- transfer_start back to zero.
---------------------------
TRANSFER_START_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
(
Mst_N_Slv = '1' and -- If Master Mode
(
SPI_En = '0' or -- enable not asserted or
(SPIXfer_done_int = '1' and SR_5_Tx_Empty = '1') or -- no data in Tx reg/FIFO or
SR_3_MODF = '1' or -- mode fault error
Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
stop_clock = '1'
)
) or
(
Mst_N_Slv = '0' and -- If Slave Mode
(
SPI_En = '0' -- enable not asserted or
)
)
)then
transfer_start <= '0';
else
-- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
-- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
--if((SPIXfer_done_int_pulse = '1') or
-- (SPIXfer_done_int_pulse_d1 = '1') or
-- (SPIXfer_done_int_pulse_d2='1')) then-- this is added to remove
-- -- glitch at the end of
-- -- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
end if;
end if;
end process TRANSFER_START_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
-- transfer start pulse generating logic
transfer_start_pulse <= transfer_start and (not(transfer_start_d1));
---------------------------------------------------------------------------------
---- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
----------------------------
--TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- --elsif (transfer_start_pulse = '1') then
-- -- SPIXfer_done_int <= '0';
-- elsif(and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) = '1') then --(Count(COUNT_WIDTH) = '1') then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
--end process TRANSFER_DONE_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
begin
-----
TRANSFER_DONE_8: if C_NUM_TRANSFER_BITS = 8 generate
TRANSFER_DONE_PROCESS_8: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_8;
end generate TRANSFER_DONE_8;
TRANSFER_DONE_16: if C_NUM_TRANSFER_BITS = 16 generate
TRANSFER_DONE_PROCESS_16: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '1' and
Count(COUNT_WIDTH-5) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_16;
end generate TRANSFER_DONE_16;
TRANSFER_DONE_32: if C_NUM_TRANSFER_BITS = 32 generate
TRANSFER_DONE_PROCESS_32: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '1' and
Count(COUNT_WIDTH-5) = '1' and
Count(COUNT_WIDTH-6) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_32;
end generate TRANSFER_DONE_32;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
rx_shft_reg <= rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
RECEIVE_DATA_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= Shift_Reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= Shift_Reg;
end if;
end if;
else
if(SPIXfer_done_int_pulse_d2 = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-- Done strobe delayed to match receive data
SPIXfer_done <= SPIXfer_done_int_pulse_d3;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d3; -- SPIXfer_done_int_pulse_d1;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d3;
-------------------------------------------------
end generate RX_DATA_SCK_RATIO_2_GEN1;
-------------------------------------------------------------------------------
-- RX_DATA_GEN_OTHER_RATIOS: This logic is for other SCK ratios than
---------------------------- C_SCK_RATIO =2
RX_DATA_GEN_OTHER_SCK_RATIOS : if C_SCK_RATIO /= 2 generate
begin
FIFO_PRESENT_GEN: if C_FIFO_EXIST = 1 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and ((CPOL xor CPHA) = '1') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((and_reduce(Count((COUNT_WIDTH-1) downto 0)) = '1') and (or_reduce(ratio_count) = '0'))
then
SPIXfer_done_int <= '1';
elsif(Mst_N_Slv = '1') and ((CPOL xor CPHA) = '0') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((and_reduce(Count((COUNT_WIDTH-1) downto 0)) = '1') and (or_reduce(ratio_count) = '0'))
-- ((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or
-- transfer_start_pulse = '1' or
-- SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- elsif(Mst_N_Slv = '1') and
-- --and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
-- ((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
-- and
-- Count_trigger = '1'
-- then
-- SPIXfer_done_int <= '1';
-- elsif--(Mst_N_Slv = '0') and
-- and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
-- if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
-- SPIXfer_done_int <= '1';
-- elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
-- end if;
-- end process TRANSFER_DONE_PROCESS;
end generate FIFO_PRESENT_GEN;
--------------------------------------------------------------
FIFO_ABSENT_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and
((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
end generate FIFO_ABSENT_GEN;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
-- the below mux is applicable only for Master mode of SPI.
rx_shft_reg <=
rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else
rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: the below process if for other
-------------------------------------------- SPI ratios of C_SCK_RATIO >2
-- -- It multiplexes the data stored
-- -- in internal registers in LSB and
-- -- non-LSB modes, in master as well as
-- -- in slave mode.
RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (Mst_N_Slv = '1') then -- in master mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
elsif(Mst_N_Slv = '0') then -- in slave mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg_s
(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg_s;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO;
SPIXfer_done <= SPIXfer_done_int_pulse_d2;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or
SPIXfer_done_int_pulse_d2 or
spisel_pulse;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
--------------------------------------------
end generate RX_DATA_GEN_OTHER_SCK_RATIOS;
-------------------------------------------------------------------------------
-- OTHER_RATIO_GENERATE : Logic to be used when C_SCK_RATIO is not equal to 2
-------------------------
OTHER_RATIO_GENERATE: if(C_SCK_RATIO /= 2) generate
--attribute IOB : string;
--attribute IOB of MOSI_I_REG : label is "true";
begin
-----
-------------------------------------------------------------------------------
-- OTHER_RATIO_MISO_I_REG_IOB_GEN: Push the IO1_I register in IOB
-- --------------
-- Only when the targeted family is 7-series or spartan 6
-- ir-respective of C_USE_STARTUP parameter
-- OTHER_RATIO_MISO_I_REG_IOB_GEN: if(C_SUB_FAMILY = "virtex7"
-- or
-- C_SUB_FAMILY = "kintex7"
-- or
-- C_SUB_FAMILY = "artix7"
-- --or
-- --C_SUB_FAMILY = "spartan6"
-- )
-- -- or
-- -- (
-- -- C_USE_STARTUP = 0
-- -- and
-- -- C_SUB_FAMILY = "virtex6"
-- -- )
-- generate
-- -- attribute IOB : string;
-- --attribute IOB of MISO_I_REG : label is "true";
-- -----
-- begin
-----
-- MISO_I_REG: component FD
-- generic map
-- (
-- INIT => '0'
-- )
-- port map
-- (
-- Q => miso_i_sync,
-- C => Bus2IP_Clk,
-- D => MISO_I
-- );
miso_i_sync <= MISO_I;
--end generate OTHER_RATIO_MISO_I_REG_IOB_GEN;
-----------------------------------------------------------------
-- OTHER_RATIO_MISO_I_REG_NO_IOB_GEN: If C_USE_STARTUP is used and family is virtex6, then
-- IO1_I is registered only, but it is not pushed in IOB.
-- this is due to STARTUP block in V6 is having DINSPI interface available for IO1_I.
-- OTHER_RATIO_MISO_I_REG_NO_IOB_GEN: if(C_USE_STARTUP = 1
-- and
-- C_SUB_FAMILY = "virtex6"
-- ) generate
-------
--begin
-------
--MISO_I_REG: component FD
--generic map
-- (
-- INIT => '0'
-- )
--port map
-- (
-- Q => miso_i_sync,
-- C => Bus2IP_Clk,
-- D => MISO_I
-- );
--end generate OTHER_RATIO_MISO_I_REG_NO_IOB_GEN;
-----------------------------------------------------------------
-- MOSI_I_REG: component FD
-- generic map
-- (
-- INIT => '0'
-- )
-- port map
-- (
-- Q => mosi_i_sync,
-- C => Bus2IP_Clk,
-- D => MOSI_I
-- );
mosi_i_sync <= MOSI_I;
------------------------------
LOOP_BACK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '0' or Soft_Reset_op = RESET_ACTIVE) then
serial_dout_int <= '0';
elsif(Loop_mode = '1') then
serial_dout_int <= Serial_Dout;
end if;
end if;
end process LOOP_BACK_PROCESS;
------------------------------
-- EXTERNAL_INPUT_OR_LOOP_PROCESS: The logic below provides MUXed input to
-- serial_din input.
EXTERNAL_INPUT_OR_LOOP_PROCESS: process(Loop_mode,
Mst_N_Slv,
mosi_i_sync,
miso_i_sync,
serial_dout_int
)is
-----
begin
-----
if(Mst_N_Slv = '1' )then
if(Loop_mode = '1')then
Serial_Din <= serial_dout_int;
else
Serial_Din <= miso_i_sync;
end if;
else
Serial_Din <= mosi_i_sync;
end if;
end process EXTERNAL_INPUT_OR_LOOP_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
RATIO_COUNT_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
else
Ratio_Count <= Ratio_Count - 1;
if (Ratio_Count = 0) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
end if;
end if;
end if;
end process RATIO_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
COUNT_TRIGGER_GEN_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger <= '0';
elsif(Ratio_Count = 0) then
Count_trigger <= not Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_GEN_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
COUNT_TRIGGER_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_1CLK_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Count <= (others => '0');
elsif (Mst_N_Slv = '1') then
if (SPIXfer_done_int = '1')or
(transfer_start = '0') or
(xfer_done_fifo_0 = '1') then
Count <= (others => '0');
elsif((Count_trigger_pulse = '1') and (Count(COUNT_WIDTH) = '0')) then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
elsif (Mst_N_Slv = '0') then
if ((transfer_start = '0') or (SPISEL_sync = '1')or
(spixfer_done_int = '1')) then
Count <= (others => '0');
elsif (edge_sck_i = '1') then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(Sync_Reset = '1') or
(Mst_N_Slv='0')
)then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= sck_o_int xor Count_trigger_pulse;
end if;
end if;
end process SCK_SET_RESET_PROCESS;
------------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
DELAY_CLK: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process DELAY_CLK;
------------------------------------
-- Rising egde pulse for CPHA-CPOL = 00/11 mode
sck_rising_edge <= not(sck_d2) and sck_d1;
-- CAPT_RX_FE_MODE_00_11: The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 00 and 11.
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_rising_edge = '1') and (transfer_start='1')) then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
--
sck_fe1 <= (not sck_d1) and sck_d2;
-- CAPT_RX_FE_MODE_01_10 : The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 01 and 10.
CAPT_RX_FE_MODE_01_10 : process(Bus2IP_Clk)
begin
--if rising_edge(Bus2IP_Clk) then
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0110 <= (others => '0');
elsif ((sck_fe1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data
------------------------------
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif((Mst_N_Slv = '1')) then -- and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
-- Capture Data on even Count
elsif(--(transfer_start = '1') and
(Count(0) = '0') ) then
Serial_Dout <= Shift_Reg(0);
-- Shift Data on odd Count
elsif(--(transfer_start = '1') and
(Count(0) = '1') and
(Count_trigger_pulse = '1')) then
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & Serial_Din;
end if;
-- below mode is slave mode logic for SPI
elsif(Mst_N_Slv = '0') then
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
--if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(SR_5_Tx_Empty_pulse = '1' or SPIXfer_done_int = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif (transfer_start = '1') then
if((CPOL = '0' and CPHA = '0') or
(CPOL = '1' and CPHA = '1')) then
if(rising_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(falling_edge_sck_i = '1') then
--elsif(rising_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
elsif((CPOL = '0' and CPHA = '1') or
(CPOL = '1' and CPHA = '0')) then
--Serial_Dout <= Shift_Reg(0);
if(falling_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(rising_edge_sck_i = '1') then
--elsif(falling_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
end if;
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate OTHER_RATIO_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(transfer_start = '0') or
(SPIXfer_done_int = '1') or
(Mst_N_Slv = '0')) then
Count <= (others => '0');
--elsif (Count(COUNT_WIDTH) = '0') then
-- Count <= Count + 1;
elsif(Count(COUNT_WIDTH) = '0')then
if(CPHA = '0')then
if(CPOL = '0' and transfer_start_d1 = '1')then -- cpol = cpha = 00
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then -- cpol = cpha = 10
Count <= Count + 1;
end if;
else
if(CPOL = '1' and transfer_start_d1 = '1')then -- cpol = cpha = 11
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then-- cpol = cpha = 10
Count <= Count + 1;
end if;
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (Sync_Reset = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);-- xor Count(COUNT_WIDTH);
end if;
end if;
end process SCK_SET_RESET_PROCESS;
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
-- CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '0') then
-- sck_d1 <= sck_o_int;
-- sck_d2 <= sck_d1;
-- -- if (sck_rising_edge = '1') then
-- if (sck_d1 = '1') then
-- rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
-- (1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
-- end if;
-- end if;
-- end process CAPT_RX_FE_MODE_00_11;
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
-- sck_d3 <= sck_d2;
-- if (sck_rising_edge = '1') then
if (sck_d2 = '0') then
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
-- Falling egde pulse
sck_rising_edge <= sck_d2 and not sck_d1;
--
-- CAPT_RX_FE_MODE_01_10: the below logic captures data in SPI 01 or 10 mode.
---------------------------
CAPT_RX_FE_MODE_01_10: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d11 <= sck_o_in;
sck_d21 <= sck_d11;
if(CPOL = '1' and CPHA = '0') then
if ((sck_d1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
elsif((CPOL = '0') and (CPHA = '1')) then
if ((sck_fe1 = '0') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
sck_fe1 <= (not sck_d11) and sck_d21;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif(Mst_N_Slv = '1') then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif(--(transfer_start = '1') and
(Count(0) = '0') -- and
--(Count(COUNT_WIDTH) = '0')
) then -- Shift Data on even
Serial_Dout <= Shift_Reg(0);
elsif(--(transfer_start = '1') and
(Count(0) = '1')-- and
--(Count(COUNT_WIDTH) = '0')
) then -- Capture Data on odd
if(Loop_mode = '1') then -- Loop mode
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Dout;
else
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & MISO_I;
end if;
end if;
elsif(Mst_N_Slv = '0') then
-- Added to have consistent default value after reset
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
if(spisel_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= (others => '0');
Serial_Dout <= '0';
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate RATIO_OF_2_GENERATE;
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL,CPHA,transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse
)
begin
-- if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Set <= (CPOL xor CPHA);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL,
CPHA,
transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse)
begin
--if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Reset <= not(CPOL xor CPHA);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_NOT_EQUAL_4_GENERATE : Logic to be used when C_SCK_RATIO is not equal
-- to 4
-------------------------------
RATIO_NOT_EQUAL_4_GENERATE: if(C_SCK_RATIO /= 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_NOT_EQUAL_4_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_4_GENERATE : Logic to be used when C_SCK_RATIO is equal to 4
------------------------
RATIO_OF_4_GENERATE: if(C_SCK_RATIO = 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
------------------------
-- A work around to reduce one clock cycle for sck_o generation. This would
-- allow for proper shifting of data bits into the slave device.
-- Removing the final stage F/F. Disadvantage of not registering final output
-------------------------------------------------------------------------------
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv,
sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
-----
begin
-----
if((Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
SCK_O_EQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_EQ_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_EQ_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => SCK_O_1 -- Data input
);
end generate SCK_O_EQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_EQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
----------------------------------------------------------------------------
-- SCK_RATIO_4_REG_PROCESS : The SCK is registered in SCK RATIO = 4 mode
----------------------------------------------------------------------------
SCK_O_EQ_4_REG_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- If Soft_Reset_op or slave Mode. Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= SCK_O_1;
end if;
end if;
end process SCK_O_EQ_4_REG_PROCESS;
-----------------------------------
end generate SCK_O_EQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_OF_4_GENERATE;
-------------------------------------------------------------------------------
-- LOADING_FIRST_ELEMENT_PROCESS : Combinatorial process to generate flag
-- when loading first data element in shift
-- register from transmit register/fifo
----------------------------------
LOADING_FIRST_ELEMENT_PROCESS: process(Soft_Reset_op,
SPI_En,Mst_N_Slv,
SS_Asserted,
SS_Asserted_1dly,
SR_3_MODF,
transfer_start_pulse)is
begin
if(Soft_Reset_op = RESET_ACTIVE) then
Loading_SR_Reg_int <= '0'; --Clear flag
elsif(SPI_En = '1' and --Enabled
(
((Mst_N_Slv = '1') and --Master configuration
(SS_Asserted = '1') and
(SS_Asserted_1dly = '0') and
(SR_3_MODF = '0')
) or
((Mst_N_Slv = '0') and --Slave configuration
((transfer_start_pulse = '1'))
)
)
)then
Loading_SR_Reg_int <= '1'; --Set flag
else
Loading_SR_Reg_int <= '0'; --Clear flag
end if;
end process LOADING_FIRST_ELEMENT_PROCESS;
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SS_O <= (others => '1');
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
elsif(transfer_start = '0') or (xfer_done_fifo_0 = '1') then -- Tranfer not in progress
if(Manual_SS_mode = '0') then -- Auto SS assert
SS_O <= (others => '1');
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
end if;
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '1';
SS_Asserted_1dly <= SS_Asserted;
end if;
end if;
end process SELECT_OUT_PROCESS;
-------------------------------------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif((Mst_N_Slv = '1') and --In Master mode
(SPISEL_sync = '0') and (Allow_MODF_Strobe = '1')) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
-------------------------------------------------------------------------------
-- SLAVE_MODF_STROBE_PROCESS : Strobe MODF signal when slave is addressed
-- but not enabled.
------------------------------
SLAVE_MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
Slave_MODF_strobe <= '0';
Allow_Slave_MODF_Strobe<= '1';
elsif((Mst_N_Slv = '0') and --In Slave mode
(SPI_En = '0') and --but not enabled
(SPISEL_sync = '0') and
(Allow_Slave_MODF_Strobe = '1')
) then
Slave_MODF_strobe <= '1';
Allow_Slave_MODF_Strobe <= '0';
else
Slave_MODF_strobe <= '0';
end if;
end if;
end process SLAVE_MODF_STROBE_PROCESS;
---------------------xxx------------------------------------------------------
end imp;
|
entity ieee8 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all;
use ieee.fixed_pkg.all;
architecture test of ieee8 is
procedure check(value : in float32; expect : in real) is
variable r : real;
begin
r := to_real(value);
assert value > expect - 0.00001;
assert value < expect + 0.00001;
end procedure;
begin
main: process is
subtype ufixed7 is ufixed (3 downto -3); -- 7 bit
variable a, b, c : float32;
variable checknum : float32;
variable check7uf1, check7uf : ufixed7;
begin
a := to_float(2.0);
b := to_float(3.0);
c := a + b;
report to_string(to_real(c));
check(c, 5.0);
c := a * b;
check(c, 6.0);
checknum := "00000000000000000000000000000000"; -- 0
check7uf1 := to_ufixed (checknum, check7uf1'high, check7uf1'low);
check7uf := "0000000";
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END blk_mem_gen_v7_3_exdes;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_v7_3 IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : blk_mem_gen_v7_3
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY Instructions IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(799 DOWNTO 0)
);
END Instructions;
ARCHITECTURE Instructions_arch OF Instructions IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Instructions_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(799 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(799 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(799 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(799 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(799 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(799 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Instructions_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Instructions_arch : ARCHITECTURE IS "Instructions,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Instructions_arch: ARCHITECTURE IS "Instructions,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=Instructions.mif,C_INIT_FILE=Instructions.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=800,C_READ_WIDTH_A=800,C_WRITE_DEPTH_A=600,C_READ_DEPTH_A=600,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=800,C_READ_WIDTH_B=800,C_WRITE_DEPTH_B=600,C_READ_DEPTH_B=600,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=22,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 60.4532 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "Instructions.mif",
C_INIT_FILE => "Instructions.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 800,
C_READ_WIDTH_A => 800,
C_WRITE_DEPTH_A => 600,
C_READ_DEPTH_A => 600,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 800,
C_READ_WIDTH_B => 800,
C_WRITE_DEPTH_B => 600,
C_READ_DEPTH_B => 600,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "22",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 60.4532 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 800)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 800)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 800)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END Instructions_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vactcapdashofkplusone is
port (
clock : in std_logic;
Vsigactofkofzero : in std_logic_vector(31 downto 0);
Vsigactofkofone : in std_logic_vector(31 downto 0);
Vsigactofkoftwo : in std_logic_vector(31 downto 0);
Wofmofzero : in std_logic_vector(31 downto 0);
Wofmofone : in std_logic_vector(31 downto 0);
Wofmoftwo : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : out std_logic_vector(31 downto 0)
);
end k_ukf_Vactcapdashofkplusone;
architecture struct of k_ukf_Vactcapdashofkplusone is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2,Z3,Z4 : std_logic_vector(31 downto 0);
begin
M1 : k_ukf_mult port map
( clock => clock,
dataa => Wofmofzero,
datab => Vsigactofkofzero,
result => Z1);
M2 : k_ukf_mult port map
( clock => clock,
dataa => Wofmofone,
datab => Vsigactofkofone,
result => Z2);
M3 : k_ukf_mult port map
( clock => clock,
dataa => Wofmoftwo,
datab => Vsigactofkoftwo,
result => Z3);
M4 : k_ukf_add port map
( clock => clock,
dataa => Z1,
datab => Z2,
result => Z4);
M5 : k_ukf_add port map
( clock => clock,
dataa => Z3,
datab => Z4,
result => Vactcapdashofkplusone);
end struct;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.async_fifo_fg;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_dma_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_dma_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_dma_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read_cdc_tig : std_logic := '0';
Signal first_read1 : std_logic := '0';
Signal first_read2 : std_logic := '0';
signal AFIFO_Ainit_d1_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
--ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true";
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity proc_common_v4_0.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_d2 or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_SYNC_FLOP : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => AFIFO_Ainit,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => AFIFO_Ainit_d2,
scndry_vect_out => open
);
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk)
begin
if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
IMP_SYNC_FLOP1 : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => first_write,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => first_read1,
scndry_vect_out => open
);
process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (AFIFO_Ainit_d2 = '0') then
first_read2 <= '0';
elsif (sig_afifo_empty = '0') then
first_read2 <= first_read1;
end if;
end if;
end process;
autoread <= first_read1 xor first_read2;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: generic_ddr_phy
-- File: ddr_phy_inferred.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Modified: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR PHY (simulation only)
------------------------------------------------------------------------------
--###################################################################################
-- Generic DDR1 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb: in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic -- Mobile DDR enable
);
end;
architecture rtl of generic_ddr_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
signal ckl: std_logic_vector(nclk-1 downto 0);
signal ckel: std_logic_vector(ncs-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl, rst)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' or rst='0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
-- For mobile SDRAM, force Cke high during reset and reset-delay,
-- For regular SDRAM, force Cke low
-- also disable outgoing clock until we have achieved PLL lock
mobgen: if mobile > 1 generate
ckel <= cke or (cke'range => not locked);
end generate;
nmobgen: if mobile < 2 generate
ckel <= cke and (cke'range => locked);
end generate;
ckl <= ck and (ck'range => lockl);
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2, ncs => ncs, nclk => nclk,
resync => 2 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => open,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba,
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => ckel,
odt => (others => '0'),
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ckl
);
end;
--###################################################################################
-- Generic DDR2 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
eightbanks: integer := 0; abits: integer := 14;
cben: integer := 0; chkbits: integer := 8;
nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic; -- system clock returned
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0); -- ddr odt
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector (2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(2 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of generic_ddr2_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr2 without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2+EIGHTBANKS, ncs => ncs, nclk => nclk,
resync => 0 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => ddr_odt,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba(1+eightbanks downto 0),
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => cke,
odt => odt,
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ck(nclk-1 downto 0)
);
end;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:41:03 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter is
port (
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : out STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast_i0 : out STD_LOGIC;
\m_axi_arqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
ADDRESS_HIT_0 : out STD_LOGIC;
match : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : out STD_LOGIC;
p_39_in : out STD_LOGIC;
p_57_in : out STD_LOGIC;
p_75_in : out STD_LOGIC;
\gen_master_slots[4].r_issuing_cnt_reg[32]\ : out STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_arready_4 : in STD_LOGIC;
p_23_in : in STD_LOGIC;
\read_cs__0\ : in STD_LOGIC;
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
\r_cmd_pop_0__1\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
\r_cmd_pop_1__1\ : in STD_LOGIC;
\r_cmd_pop_3__1\ : in STD_LOGIC;
\r_cmd_pop_2__1\ : in STD_LOGIC;
m_valid_i : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
\s_axi_araddr[24]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter is
signal \^address_hit_0\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^aa_mi_arvalid\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_3_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \^m_axi_arqos[15]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^match\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
signal st_aa_artarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_rid_i[11]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[10]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[18]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[19]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[19]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[26]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair2";
begin
ADDRESS_HIT_0 <= \^address_hit_0\;
D(2 downto 0) <= \^d\(2 downto 0);
Q(0) <= \^q\(0);
aa_mi_arvalid <= \^aa_mi_arvalid\;
\m_axi_arqos[15]\(68 downto 0) <= \^m_axi_arqos[15]\(68 downto 0);
match <= \^match\;
\gen_axi.s_axi_rid_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
I2 => mi_arready_4,
I3 => p_23_in,
O => \gen_axi.s_axi_rid_i_reg[11]\(0)
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55035500"
)
port map (
I0 => \read_cs__0\,
I1 => \^m_axi_arqos[15]\(45),
I2 => \^m_axi_arqos[15]\(44),
I3 => p_23_in,
I4 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
O => s_axi_rlast_i0
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \^m_axi_arqos[15]\(46),
I1 => \^m_axi_arqos[15]\(47),
I2 => \^m_axi_arqos[15]\(48),
I3 => \^m_axi_arqos[15]\(49),
I4 => \^m_axi_arqos[15]\(51),
I5 => \^m_axi_arqos[15]\(50),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \r_cmd_pop_0__1\,
I2 => m_axi_arready(0),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(0),
I5 => r_issuing_cnt(1),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I1 => r_issuing_cnt(1),
I2 => r_issuing_cnt(2),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(1),
I1 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I2 => r_issuing_cnt(3),
I3 => r_issuing_cnt(2),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(0),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(0),
O => p_93_in
);
\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \r_cmd_pop_0__1\,
I2 => m_axi_arready(0),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(0),
I5 => r_issuing_cnt(1),
O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I1 => r_issuing_cnt(5),
I2 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(5),
I1 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I2 => r_issuing_cnt(7),
I3 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(1),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(1),
O => p_75_in
);
\gen_master_slots[1].r_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \r_cmd_pop_1__1\,
I2 => m_axi_arready(1),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(1),
I5 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \r_cmd_pop_1__1\,
I2 => m_axi_arready(1),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(1),
I5 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0)
);
\gen_master_slots[2].r_issuing_cnt[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(8),
I1 => \r_cmd_pop_2__1\,
I2 => m_axi_arready(2),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(2),
I5 => r_issuing_cnt(9),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0)
);
\gen_master_slots[2].r_issuing_cnt[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\,
I1 => r_issuing_cnt(9),
I2 => r_issuing_cnt(10),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(9),
I1 => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\,
I2 => r_issuing_cnt(11),
I3 => r_issuing_cnt(10),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(2),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(2),
O => p_57_in
);
\gen_master_slots[2].r_issuing_cnt[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(8),
I1 => \r_cmd_pop_2__1\,
I2 => m_axi_arready(2),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(2),
I5 => r_issuing_cnt(9),
O => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\
);
\gen_master_slots[3].r_issuing_cnt[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(12),
I1 => \r_cmd_pop_3__1\,
I2 => m_axi_arready(3),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(3),
I5 => r_issuing_cnt(13),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0)
);
\gen_master_slots[3].r_issuing_cnt[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\,
I1 => r_issuing_cnt(13),
I2 => r_issuing_cnt(14),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(13),
I1 => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\,
I2 => r_issuing_cnt(15),
I3 => r_issuing_cnt(14),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(3),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(3),
O => p_39_in
);
\gen_master_slots[3].r_issuing_cnt[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(12),
I1 => \r_cmd_pop_3__1\,
I2 => m_axi_arready(3),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(3),
I5 => r_issuing_cnt(13),
O => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\
);
\gen_master_slots[4].r_issuing_cnt[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"807F0080"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
I2 => mi_arready_4,
I3 => \r_cmd_pop_4__1\,
I4 => r_issuing_cnt(16),
O => \gen_master_slots[4].r_issuing_cnt_reg[32]\
);
\gen_no_arbiter.m_mesg_i[11]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_mi_arvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(0),
Q => \^m_axi_arqos[15]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(10),
Q => \^m_axi_arqos[15]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(11),
Q => \^m_axi_arqos[15]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(12),
Q => \^m_axi_arqos[15]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(13),
Q => \^m_axi_arqos[15]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(14),
Q => \^m_axi_arqos[15]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(15),
Q => \^m_axi_arqos[15]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(16),
Q => \^m_axi_arqos[15]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(17),
Q => \^m_axi_arqos[15]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(18),
Q => \^m_axi_arqos[15]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(19),
Q => \^m_axi_arqos[15]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(1),
Q => \^m_axi_arqos[15]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(20),
Q => \^m_axi_arqos[15]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(21),
Q => \^m_axi_arqos[15]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(22),
Q => \^m_axi_arqos[15]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(23),
Q => \^m_axi_arqos[15]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(24),
Q => \^m_axi_arqos[15]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(25),
Q => \^m_axi_arqos[15]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(26),
Q => \^m_axi_arqos[15]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(27),
Q => \^m_axi_arqos[15]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(28),
Q => \^m_axi_arqos[15]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(29),
Q => \^m_axi_arqos[15]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(2),
Q => \^m_axi_arqos[15]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(30),
Q => \^m_axi_arqos[15]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(31),
Q => \^m_axi_arqos[15]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(32),
Q => \^m_axi_arqos[15]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(33),
Q => \^m_axi_arqos[15]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(34),
Q => \^m_axi_arqos[15]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(35),
Q => \^m_axi_arqos[15]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(36),
Q => \^m_axi_arqos[15]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(37),
Q => \^m_axi_arqos[15]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(38),
Q => \^m_axi_arqos[15]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(39),
Q => \^m_axi_arqos[15]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(3),
Q => \^m_axi_arqos[15]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(40),
Q => \^m_axi_arqos[15]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(41),
Q => \^m_axi_arqos[15]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(42),
Q => \^m_axi_arqos[15]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(43),
Q => \^m_axi_arqos[15]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(44),
Q => \^m_axi_arqos[15]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(45),
Q => \^m_axi_arqos[15]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(46),
Q => \^m_axi_arqos[15]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(47),
Q => \^m_axi_arqos[15]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(48),
Q => \^m_axi_arqos[15]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(49),
Q => \^m_axi_arqos[15]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(4),
Q => \^m_axi_arqos[15]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(50),
Q => \^m_axi_arqos[15]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(51),
Q => \^m_axi_arqos[15]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(52),
Q => \^m_axi_arqos[15]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(53),
Q => \^m_axi_arqos[15]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(54),
Q => \^m_axi_arqos[15]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(55),
Q => \^m_axi_arqos[15]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(56),
Q => \^m_axi_arqos[15]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(57),
Q => \^m_axi_arqos[15]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(58),
Q => \^m_axi_arqos[15]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(5),
Q => \^m_axi_arqos[15]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(59),
Q => \^m_axi_arqos[15]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(60),
Q => \^m_axi_arqos[15]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(61),
Q => \^m_axi_arqos[15]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(62),
Q => \^m_axi_arqos[15]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(63),
Q => \^m_axi_arqos[15]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(64),
Q => \^m_axi_arqos[15]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(6),
Q => \^m_axi_arqos[15]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(65),
Q => \^m_axi_arqos[15]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(66),
Q => \^m_axi_arqos[15]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(67),
Q => \^m_axi_arqos[15]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(68),
Q => \^m_axi_arqos[15]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(7),
Q => \^m_axi_arqos[15]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(8),
Q => \^m_axi_arqos[15]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(9),
Q => \^m_axi_arqos[15]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^address_hit_0\,
I1 => \^match\,
O => st_aa_artarget_hot(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
I4 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^address_hit_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I1 => \s_axi_arqos[3]\(29),
I2 => \s_axi_arqos[3]\(28),
I3 => \s_axi_arqos[3]\(31),
I4 => \s_axi_arqos[3]\(30),
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \s_axi_arqos[3]\(34),
I1 => \s_axi_arqos[3]\(35),
I2 => \s_axi_arqos[3]\(33),
I3 => \s_axi_arqos[3]\(32),
I4 => \s_axi_arqos[3]\(37),
I5 => \s_axi_arqos[3]\(36),
O => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
\gen_no_arbiter.m_target_hot_i[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
I4 => \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(1)
);
\gen_no_arbiter.m_target_hot_i[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => \s_axi_arqos[3]\(35),
I1 => \s_axi_arqos[3]\(34),
I2 => \s_axi_arqos[3]\(32),
I3 => \s_axi_arqos[3]\(33),
I4 => \s_axi_arqos[3]\(36),
I5 => \s_axi_arqos[3]\(37),
O => \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\,
I1 => \s_axi_arqos[3]\(25),
I2 => \s_axi_arqos[3]\(26),
I3 => \s_axi_arqos[3]\(27),
I4 => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(2)
);
\gen_no_arbiter.m_target_hot_i[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \s_axi_arqos[3]\(32),
I1 => \s_axi_arqos[3]\(33),
I2 => \s_axi_arqos[3]\(34),
I3 => \s_axi_arqos[3]\(35),
I4 => \s_axi_arqos[3]\(37),
I5 => \s_axi_arqos[3]\(36),
O => \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \s_axi_arqos[3]\(31),
I1 => \s_axi_arqos[3]\(30),
I2 => \s_axi_arqos[3]\(29),
I3 => \s_axi_arqos[3]\(28),
O => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_arqos[3]\(40),
I1 => \s_axi_arqos[3]\(41),
I2 => \s_axi_arqos[3]\(38),
I3 => \s_axi_arqos[3]\(39),
I4 => \s_axi_arqos[3]\(43),
I5 => \s_axi_arqos[3]\(42),
O => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
\gen_no_arbiter.m_target_hot_i[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^d\(1),
I1 => \^d\(2),
I2 => \^d\(0),
I3 => \^address_hit_0\,
O => \^match\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_artarget_hot(0),
Q => aa_mi_artarget_hot(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(0),
Q => aa_mi_artarget_hot(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(1),
Q => aa_mi_artarget_hot(2),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(2),
Q => aa_mi_artarget_hot(3),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \s_axi_araddr[24]\(0),
Q => \^q\(0),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"DC"
)
port map (
I0 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
I1 => m_valid_i,
I2 => \^aa_mi_arvalid\,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF88800000000"
)
port map (
I0 => m_axi_arready(2),
I1 => aa_mi_artarget_hot(2),
I2 => m_axi_arready(1),
I3 => aa_mi_artarget_hot(1),
I4 => \gen_no_arbiter.m_valid_i_i_3_n_0\,
I5 => \^aa_mi_arvalid\,
O => \gen_no_arbiter.m_valid_i_i_2_n_0\
);
\gen_no_arbiter.m_valid_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => m_axi_arready(0),
I2 => \^q\(0),
I3 => mi_arready_4,
I4 => m_axi_arready(3),
I5 => aa_mi_artarget_hot(3),
O => \gen_no_arbiter.m_valid_i_i_3_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^aa_mi_arvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => E(0),
Q => S_AXI_ARREADY(0),
R => '0'
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(1),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(2),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(2)
);
\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(3),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 is
port (
ss_aa_awready : out STD_LOGIC;
aa_sa_awvalid : out STD_LOGIC;
\mi_awready_mux__3\ : out STD_LOGIC;
\s_ready_i0__1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_84_in : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
p_66_in : out STD_LOGIC;
p_48_in : out STD_LOGIC;
p_101_in : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
write_cs01_out : out STD_LOGIC;
ADDRESS_HIT_0 : out STD_LOGIC;
match : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
\sa_wm_awready_mux__3\ : out STD_LOGIC;
\gen_master_slots[4].w_issuing_cnt_reg[32]\ : out STD_LOGIC;
\m_axi_awqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
mi_awready_4 : in STD_LOGIC;
\s_axi_awqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[24]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 is
signal \^address_hit_0\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^aa_sa_awvalid\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC;
signal \^match\ : STD_LOGIC;
signal \^mi_awready_mux__3\ : STD_LOGIC;
signal \^s_ready_i0__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal s_ready_i2 : STD_LOGIC;
signal \^ss_aa_awready\ : STD_LOGIC;
signal st_aa_awtarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^write_cs01_out\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_4\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_4\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[4]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair14";
begin
ADDRESS_HIT_0 <= \^address_hit_0\;
D(2 downto 0) <= \^d\(2 downto 0);
Q(4 downto 0) <= \^q\(4 downto 0);
aa_sa_awvalid <= \^aa_sa_awvalid\;
match <= \^match\;
\mi_awready_mux__3\ <= \^mi_awready_mux__3\;
\s_ready_i0__1\(0) <= \^s_ready_i0__1\(0);
ss_aa_awready <= \^ss_aa_awready\;
write_cs01_out <= \^write_cs01_out\;
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => mi_awready_4,
I1 => \^q\(4),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => \^write_cs01_out\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(0),
I1 => \^q\(0),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_101_in
);
\gen_master_slots[1].w_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(1),
I1 => \^q\(1),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_84_in
);
\gen_master_slots[2].w_issuing_cnt[19]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(2),
I1 => \^q\(2),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_66_in
);
\gen_master_slots[3].w_issuing_cnt[27]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(3),
I1 => \^q\(3),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_48_in
);
\gen_master_slots[4].w_issuing_cnt[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"95552AAA"
)
port map (
I0 => \^write_cs01_out\,
I1 => s_axi_bready(0),
I2 => p_46_out,
I3 => \chosen_reg[4]\(0),
I4 => w_issuing_cnt(0),
O => \gen_master_slots[4].w_issuing_cnt_reg[32]\
);
\gen_no_arbiter.m_mesg_i[11]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_sa_awvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(0),
Q => \m_axi_awqos[15]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(10),
Q => \m_axi_awqos[15]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(11),
Q => \m_axi_awqos[15]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(12),
Q => \m_axi_awqos[15]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(13),
Q => \m_axi_awqos[15]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(14),
Q => \m_axi_awqos[15]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(15),
Q => \m_axi_awqos[15]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(16),
Q => \m_axi_awqos[15]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(17),
Q => \m_axi_awqos[15]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(18),
Q => \m_axi_awqos[15]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(19),
Q => \m_axi_awqos[15]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(1),
Q => \m_axi_awqos[15]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(20),
Q => \m_axi_awqos[15]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(21),
Q => \m_axi_awqos[15]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(22),
Q => \m_axi_awqos[15]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(23),
Q => \m_axi_awqos[15]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(24),
Q => \m_axi_awqos[15]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(25),
Q => \m_axi_awqos[15]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(26),
Q => \m_axi_awqos[15]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(27),
Q => \m_axi_awqos[15]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(28),
Q => \m_axi_awqos[15]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(29),
Q => \m_axi_awqos[15]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(2),
Q => \m_axi_awqos[15]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(30),
Q => \m_axi_awqos[15]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(31),
Q => \m_axi_awqos[15]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(32),
Q => \m_axi_awqos[15]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(33),
Q => \m_axi_awqos[15]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(34),
Q => \m_axi_awqos[15]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(35),
Q => \m_axi_awqos[15]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(36),
Q => \m_axi_awqos[15]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(37),
Q => \m_axi_awqos[15]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(38),
Q => \m_axi_awqos[15]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(39),
Q => \m_axi_awqos[15]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(3),
Q => \m_axi_awqos[15]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(40),
Q => \m_axi_awqos[15]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(41),
Q => \m_axi_awqos[15]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(42),
Q => \m_axi_awqos[15]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(43),
Q => \m_axi_awqos[15]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(44),
Q => \m_axi_awqos[15]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(45),
Q => \m_axi_awqos[15]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(46),
Q => \m_axi_awqos[15]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(47),
Q => \m_axi_awqos[15]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(48),
Q => \m_axi_awqos[15]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(49),
Q => \m_axi_awqos[15]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(4),
Q => \m_axi_awqos[15]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(50),
Q => \m_axi_awqos[15]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(51),
Q => \m_axi_awqos[15]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(52),
Q => \m_axi_awqos[15]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(53),
Q => \m_axi_awqos[15]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(54),
Q => \m_axi_awqos[15]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(55),
Q => \m_axi_awqos[15]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(56),
Q => \m_axi_awqos[15]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(57),
Q => \m_axi_awqos[15]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(58),
Q => \m_axi_awqos[15]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(5),
Q => \m_axi_awqos[15]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(59),
Q => \m_axi_awqos[15]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(60),
Q => \m_axi_awqos[15]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(61),
Q => \m_axi_awqos[15]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(62),
Q => \m_axi_awqos[15]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(63),
Q => \m_axi_awqos[15]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(64),
Q => \m_axi_awqos[15]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(6),
Q => \m_axi_awqos[15]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(65),
Q => \m_axi_awqos[15]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(66),
Q => \m_axi_awqos[15]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(67),
Q => \m_axi_awqos[15]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(68),
Q => \m_axi_awqos[15]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(7),
Q => \m_axi_awqos[15]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(8),
Q => \m_axi_awqos[15]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(9),
Q => \m_axi_awqos[15]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^address_hit_0\,
I1 => \^match\,
O => st_aa_awtarget_hot(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_awqos[3]\(29),
I1 => \s_axi_awqos[3]\(28),
I2 => \s_axi_awqos[3]\(31),
I3 => \s_axi_awqos[3]\(30),
I4 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^address_hit_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I1 => \s_axi_awqos[3]\(29),
I2 => \s_axi_awqos[3]\(28),
I3 => \s_axi_awqos[3]\(31),
I4 => \s_axi_awqos[3]\(30),
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \s_axi_awqos[3]\(34),
I1 => \s_axi_awqos[3]\(35),
I2 => \s_axi_awqos[3]\(33),
I3 => \s_axi_awqos[3]\(32),
I4 => \s_axi_awqos[3]\(37),
I5 => \s_axi_awqos[3]\(36),
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
\gen_no_arbiter.m_target_hot_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_awqos[3]\(29),
I1 => \s_axi_awqos[3]\(28),
I2 => \s_axi_awqos[3]\(31),
I3 => \s_axi_awqos[3]\(30),
I4 => \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(1)
);
\gen_no_arbiter.m_target_hot_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => \s_axi_awqos[3]\(35),
I1 => \s_axi_awqos[3]\(34),
I2 => \s_axi_awqos[3]\(32),
I3 => \s_axi_awqos[3]\(33),
I4 => \s_axi_awqos[3]\(36),
I5 => \s_axi_awqos[3]\(37),
O => \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\,
I1 => \s_axi_awqos[3]\(25),
I2 => \s_axi_awqos[3]\(26),
I3 => \s_axi_awqos[3]\(27),
I4 => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(2)
);
\gen_no_arbiter.m_target_hot_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \s_axi_awqos[3]\(32),
I1 => \s_axi_awqos[3]\(33),
I2 => \s_axi_awqos[3]\(34),
I3 => \s_axi_awqos[3]\(35),
I4 => \s_axi_awqos[3]\(37),
I5 => \s_axi_awqos[3]\(36),
O => \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \s_axi_awqos[3]\(31),
I1 => \s_axi_awqos[3]\(30),
I2 => \s_axi_awqos[3]\(29),
I3 => \s_axi_awqos[3]\(28),
O => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_awqos[3]\(40),
I1 => \s_axi_awqos[3]\(41),
I2 => \s_axi_awqos[3]\(38),
I3 => \s_axi_awqos[3]\(39),
I4 => \s_axi_awqos[3]\(43),
I5 => \s_axi_awqos[3]\(42),
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
\gen_no_arbiter.m_target_hot_i[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^d\(1),
I1 => \^d\(2),
I2 => \^d\(0),
I3 => \^address_hit_0\,
O => \^match\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_awtarget_hot(0),
Q => \^q\(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(0),
Q => \^q\(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(1),
Q => \^q\(2),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(2),
Q => \^q\(3),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \s_axi_awaddr[24]\(0),
Q => \^q\(4),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1F00"
)
port map (
I0 => m_ready_d(1),
I1 => \^mi_awready_mux__3\,
I2 => \^s_ready_i0__1\(0),
I3 => \^aa_sa_awvalid\,
I4 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1__0_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1__0_n_0\,
Q => \^aa_sa_awvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^ss_aa_awready\,
I1 => s_axi_awvalid(0),
I2 => m_ready_d_0(0),
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => E(0),
Q => \^ss_aa_awready\,
R => '0'
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(0),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(2),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(2)
);
\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(3),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(3)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(4),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(2),
I4 => \^q\(3),
O => \sa_wm_awready_mux__3\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \m_ready_d[1]_i_4_n_0\,
I1 => \^q\(1),
I2 => m_axi_awready(1),
I3 => \^q\(2),
I4 => m_axi_awready(2),
O => \^mi_awready_mux__3\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => m_ready_d(0),
I1 => \^q\(3),
I2 => \^q\(2),
I3 => \^q\(1),
I4 => \^q\(0),
I5 => \^q\(4),
O => \^s_ready_i0__1\(0)
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^q\(0),
I1 => m_axi_awready(0),
I2 => \^q\(4),
I3 => mi_awready_4,
I4 => m_axi_awready(3),
I5 => \^q\(3),
O => \m_ready_d[1]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].w_issuing_cnt_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
\s_axi_bvalid[0]\ : out STD_LOGIC;
resp_select : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
f_mux4_return : out STD_LOGIC_VECTOR ( 13 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
p_84_in : in STD_LOGIC;
p_66_in : in STD_LOGIC;
p_48_in : in STD_LOGIC;
p_101_in : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
match : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
p_0_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
st_mr_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
st_mr_bmesg : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_68_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_24_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_25_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_26_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_36_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_37_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_38_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_39_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6_n_0\ : STD_LOGIC;
signal last_rr_hot : STD_LOGIC;
signal \last_rr_hot[0]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_4__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_5__0_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_5_in6_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in9_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal \^resp_select\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \resp_select__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_bvalid[0]\ : STD_LOGIC;
signal \^s_ready_i_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \w_cmd_pop_0__0\ : STD_LOGIC;
signal \w_cmd_pop_1__0\ : STD_LOGIC;
signal \w_cmd_pop_2__0\ : STD_LOGIC;
signal \w_cmd_pop_3__0\ : STD_LOGIC;
signal \w_cmd_pop_4__0\ : STD_LOGIC;
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[3]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_3\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_3\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_3\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_2__0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_3__0\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \last_rr_hot[1]_i_2__0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_3__0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_2__0\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_3__0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_1\ : label is "soft_lutpair156";
begin
SR(0) <= \^sr\(0);
m_valid_i <= \^m_valid_i\;
resp_select(0) <= \^resp_select\(0);
\s_axi_bvalid[0]\ <= \^s_axi_bvalid[0]\;
s_ready_i_reg(4 downto 0) <= \^s_ready_i_reg\(4 downto 0);
\chosen[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBB8"
)
port map (
I0 => s_axi_bready(0),
I1 => \^s_axi_bvalid[0]\,
I2 => p_46_out,
I3 => p_128_out,
I4 => p_108_out,
I5 => m_valid_i_reg,
O => need_arbitration
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(0),
Q => \^s_ready_i_reg\(0),
R => \^sr\(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(1),
Q => \^s_ready_i_reg\(1),
R => \^sr\(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(2),
Q => \^s_ready_i_reg\(2),
R => \^sr\(0)
);
\chosen_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(3),
Q => \^s_ready_i_reg\(3),
R => \^sr\(0)
);
\chosen_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(4),
Q => \^s_ready_i_reg\(4),
R => \^sr\(0)
);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(36),
I1 => st_mr_bid(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(24),
I5 => st_mr_bid(12),
O => f_mux4_return(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(46),
I1 => st_mr_bid(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(34),
I5 => st_mr_bid(22),
O => f_mux4_return(10)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_ready_i_reg\(4),
I1 => p_46_out,
O => \^resp_select\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(47),
I1 => st_mr_bid(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(35),
I5 => st_mr_bid(23),
O => f_mux4_return(11)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_68_out,
I1 => \^s_ready_i_reg\(3),
I2 => p_108_out,
I3 => \^s_ready_i_reg\(1),
O => \resp_select__0\(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bmesg(6),
I1 => st_mr_bmesg(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bmesg(4),
I5 => st_mr_bmesg(2),
O => f_mux4_return(12)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bmesg(7),
I1 => st_mr_bmesg(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bmesg(5),
I5 => st_mr_bmesg(3),
O => f_mux4_return(13)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(37),
I1 => st_mr_bid(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(25),
I5 => st_mr_bid(13),
O => f_mux4_return(1)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(38),
I1 => st_mr_bid(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(26),
I5 => st_mr_bid(14),
O => f_mux4_return(2)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(39),
I1 => st_mr_bid(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(27),
I5 => st_mr_bid(15),
O => f_mux4_return(3)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(40),
I1 => st_mr_bid(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(28),
I5 => st_mr_bid(16),
O => f_mux4_return(4)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(41),
I1 => st_mr_bid(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(29),
I5 => st_mr_bid(17),
O => f_mux4_return(5)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(42),
I1 => st_mr_bid(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(30),
I5 => st_mr_bid(18),
O => f_mux4_return(6)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(43),
I1 => st_mr_bid(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(31),
I5 => st_mr_bid(19),
O => f_mux4_return(7)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(44),
I1 => st_mr_bid(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(32),
I5 => st_mr_bid(20),
O => f_mux4_return(8)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(45),
I1 => st_mr_bid(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(33),
I5 => st_mr_bid(21),
O => f_mux4_return(9)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(1),
I1 => w_issuing_cnt(2),
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(3),
I4 => \w_cmd_pop_0__0\,
I5 => p_101_in,
O => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(0),
I1 => p_128_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_0__0\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(5),
I1 => w_issuing_cnt(6),
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(7),
I4 => \w_cmd_pop_1__0\,
I5 => p_84_in,
O => E(0)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(1),
I1 => p_108_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_1__0\
);
\gen_master_slots[2].w_issuing_cnt[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(9),
I1 => w_issuing_cnt(10),
I2 => w_issuing_cnt(8),
I3 => w_issuing_cnt(11),
I4 => \w_cmd_pop_2__0\,
I5 => p_66_in,
O => \gen_master_slots[2].w_issuing_cnt_reg[16]\(0)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(2),
I1 => p_88_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_2__0\
);
\gen_master_slots[3].w_issuing_cnt[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(13),
I1 => w_issuing_cnt(14),
I2 => w_issuing_cnt(12),
I3 => w_issuing_cnt(15),
I4 => \w_cmd_pop_3__0\,
I5 => p_48_in,
O => \gen_master_slots[3].w_issuing_cnt_reg[24]\(0)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(3),
I1 => p_68_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_3__0\
);
\gen_no_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\,
I5 => aa_sa_awvalid,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8888888AAAAAAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
I1 => \gen_multi_thread.accept_cnt_reg[0]\,
I2 => \^s_axi_bvalid[0]\,
I3 => p_0_out,
I4 => s_axi_bready(0),
I5 => Q(0),
O => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_36_n_0\,
I1 => \s_axi_awaddr[30]\(0),
I2 => ADDRESS_HIT_0,
I3 => \gen_no_arbiter.s_ready_i[0]_i_37_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"ECA0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_38_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_39_n_0\,
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_26_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(4),
I1 => p_46_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_36\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_1__0\,
I1 => w_issuing_cnt(4),
I2 => w_issuing_cnt(7),
I3 => w_issuing_cnt(5),
I4 => w_issuing_cnt(6),
O => \gen_no_arbiter.s_ready_i[0]_i_36_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_37\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_0__0\,
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(3),
I3 => w_issuing_cnt(1),
I4 => w_issuing_cnt(2),
O => \gen_no_arbiter.s_ready_i[0]_i_37_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_38\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_2__0\,
I1 => w_issuing_cnt(8),
I2 => w_issuing_cnt(11),
I3 => w_issuing_cnt(9),
I4 => w_issuing_cnt(10),
O => \gen_no_arbiter.s_ready_i[0]_i_38_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_39\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_3__0\,
I1 => w_issuing_cnt(12),
I2 => w_issuing_cnt(15),
I3 => w_issuing_cnt(13),
I4 => w_issuing_cnt(14),
O => \gen_no_arbiter.s_ready_i[0]_i_39_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8AAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_26_n_0\,
I3 => \w_cmd_pop_4__0\,
I4 => match,
I5 => w_issuing_cnt(16),
O => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\
);
\last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_128_out,
I1 => p_68_out,
I2 => p_46_out,
I3 => \last_rr_hot[0]_i_2__0_n_0\,
I4 => \last_rr_hot[0]_i_3__0_n_0\,
I5 => p_6_in,
O => next_rr_hot(0)
);
\last_rr_hot[0]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_5_in6_in,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_108_out,
I3 => p_88_out,
O => \last_rr_hot[0]_i_2__0_n_0\
);
\last_rr_hot[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_46_out,
I1 => p_7_in9_in,
I2 => p_8_in,
O => \last_rr_hot[0]_i_3__0_n_0\
);
\last_rr_hot[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_108_out,
I1 => p_128_out,
I2 => p_46_out,
I3 => \last_rr_hot[1]_i_2__0_n_0\,
I4 => \last_rr_hot[4]_i_4__0_n_0\,
I5 => p_7_in9_in,
O => next_rr_hot(1)
);
\last_rr_hot[1]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_6_in,
I1 => p_5_in6_in,
I2 => p_88_out,
I3 => p_68_out,
O => \last_rr_hot[1]_i_2__0_n_0\
);
\last_rr_hot[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_88_out,
I1 => m_valid_i_reg_0,
I2 => \last_rr_hot[4]_i_5__0_n_0\,
I3 => p_46_out,
I4 => \last_rr_hot[2]_i_3__0_n_0\,
I5 => p_8_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_108_out,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_5_in6_in,
O => \last_rr_hot[2]_i_3__0_n_0\
);
\last_rr_hot[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_68_out,
I1 => p_108_out,
I2 => p_88_out,
I3 => \last_rr_hot[3]_i_2__0_n_0\,
I4 => \last_rr_hot[3]_i_3__0_n_0\,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(3)
);
\last_rr_hot[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_8_in,
I1 => p_7_in9_in,
I2 => p_46_out,
I3 => p_128_out,
O => \last_rr_hot[3]_i_2__0_n_0\
);
\last_rr_hot[3]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_88_out,
I1 => p_5_in6_in,
I2 => p_6_in,
O => \last_rr_hot[3]_i_3__0_n_0\
);
\last_rr_hot[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(3),
I2 => next_rr_hot(2),
I3 => next_rr_hot(1),
I4 => next_rr_hot(0),
I5 => next_rr_hot(4),
O => last_rr_hot
);
\last_rr_hot[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_46_out,
I1 => m_valid_i_reg,
I2 => \last_rr_hot[4]_i_4__0_n_0\,
I3 => p_108_out,
I4 => \last_rr_hot[4]_i_5__0_n_0\,
I5 => p_5_in6_in,
O => next_rr_hot(4)
);
\last_rr_hot[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_128_out,
I1 => p_8_in,
I2 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[4]_i_4__0_n_0\
);
\last_rr_hot[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_68_out,
I1 => p_6_in,
I2 => p_7_in9_in,
O => \last_rr_hot[4]_i_5__0_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(0),
Q => \last_rr_hot_reg_n_0_[0]\,
R => \^sr\(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(1),
Q => p_5_in6_in,
R => \^sr\(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(2),
Q => p_6_in,
R => \^sr\(0)
);
\last_rr_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(3),
Q => p_7_in9_in,
R => \^sr\(0)
);
\last_rr_hot_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(4),
Q => p_8_in,
S => \^sr\(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \^resp_select\(0),
I1 => p_128_out,
I2 => \^s_ready_i_reg\(0),
I3 => p_108_out,
I4 => \^s_ready_i_reg\(1),
I5 => \resp_select__0\(1),
O => \^s_axi_bvalid[0]\
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_68_out,
I1 => \^s_ready_i_reg\(3),
I2 => p_88_out,
I3 => \^s_ready_i_reg\(2),
O => \resp_select__0\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8 is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
f_mux4_return : out STD_LOGIC_VECTOR ( 46 downto 0 );
\s_axi_rvalid[0]\ : out STD_LOGIC;
resp_select : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
match : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : in STD_LOGIC;
st_mr_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
st_mr_rmesg : in STD_LOGIC_VECTOR ( 135 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_62_out : in STD_LOGIC;
p_102_out : in STD_LOGIC;
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[34]_4\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_40_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8 : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8 is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\ : STD_LOGIC;
signal last_rr_hot : STD_LOGIC;
signal \last_rr_hot[0]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_4_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_5_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_in1_in : STD_LOGIC_VECTOR ( 3 downto 1 );
signal p_5_in6_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in9_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal \^resp_select\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \resp_select__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rvalid[0]\ : STD_LOGIC;
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[3]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_2\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \last_rr_hot[1]_i_2\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_3\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_2\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_3\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_4\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_5\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__3\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_3\ : label is "soft_lutpair123";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
m_valid_i <= \^m_valid_i\;
resp_select(0) <= \^resp_select\(0);
\s_axi_rvalid[0]\ <= \^s_axi_rvalid[0]\;
\chosen[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBB8"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rvalid[0]\,
I2 => p_40_out,
I3 => p_122_out,
I4 => p_102_out,
I5 => m_valid_i_reg,
O => need_arbitration
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(0),
Q => \^q\(0),
R => SR(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(1),
Q => \^q\(1),
R => SR(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(2),
Q => \^q\(2),
R => SR(0)
);
\chosen_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(3),
Q => \^q\(3),
R => SR(0)
);
\chosen_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(4),
Q => \^q\(4),
R => SR(0)
);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(36),
I1 => st_mr_rid(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(24),
I5 => st_mr_rid(12),
O => f_mux4_return(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(46),
I1 => st_mr_rid(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(34),
I5 => st_mr_rid(22),
O => f_mux4_return(10)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(4),
I1 => p_40_out,
O => \^resp_select\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(47),
I1 => st_mr_rid(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(35),
I5 => st_mr_rid(23),
O => f_mux4_return(11)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_62_out,
I1 => \^q\(3),
I2 => p_102_out,
I3 => \^q\(1),
O => \resp_select__0\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_62_out,
I1 => \^q\(3),
I2 => p_82_out,
I3 => \^q\(2),
O => \resp_select__0\(1)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(102),
I1 => st_mr_rmesg(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(68),
I5 => st_mr_rmesg(34),
O => f_mux4_return(12)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(103),
I1 => st_mr_rmesg(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(69),
I5 => st_mr_rmesg(35),
O => f_mux4_return(13)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(104),
I1 => st_mr_rmesg(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(70),
I5 => st_mr_rmesg(36),
O => f_mux4_return(14)
);
\gen_fpga.gen_mux_5_8[16].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(105),
I1 => st_mr_rmesg(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(71),
I5 => st_mr_rmesg(37),
O => f_mux4_return(15)
);
\gen_fpga.gen_mux_5_8[17].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(106),
I1 => st_mr_rmesg(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(72),
I5 => st_mr_rmesg(38),
O => f_mux4_return(16)
);
\gen_fpga.gen_mux_5_8[18].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(107),
I1 => st_mr_rmesg(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(73),
I5 => st_mr_rmesg(39),
O => f_mux4_return(17)
);
\gen_fpga.gen_mux_5_8[19].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(108),
I1 => st_mr_rmesg(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(74),
I5 => st_mr_rmesg(40),
O => f_mux4_return(18)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(37),
I1 => st_mr_rid(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(25),
I5 => st_mr_rid(13),
O => f_mux4_return(1)
);
\gen_fpga.gen_mux_5_8[20].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(109),
I1 => st_mr_rmesg(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(75),
I5 => st_mr_rmesg(41),
O => f_mux4_return(19)
);
\gen_fpga.gen_mux_5_8[21].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(110),
I1 => st_mr_rmesg(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(76),
I5 => st_mr_rmesg(42),
O => f_mux4_return(20)
);
\gen_fpga.gen_mux_5_8[22].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(111),
I1 => st_mr_rmesg(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(77),
I5 => st_mr_rmesg(43),
O => f_mux4_return(21)
);
\gen_fpga.gen_mux_5_8[23].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(112),
I1 => st_mr_rmesg(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(78),
I5 => st_mr_rmesg(44),
O => f_mux4_return(22)
);
\gen_fpga.gen_mux_5_8[24].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(113),
I1 => st_mr_rmesg(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(79),
I5 => st_mr_rmesg(45),
O => f_mux4_return(23)
);
\gen_fpga.gen_mux_5_8[25].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(114),
I1 => st_mr_rmesg(12),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(80),
I5 => st_mr_rmesg(46),
O => f_mux4_return(24)
);
\gen_fpga.gen_mux_5_8[26].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(115),
I1 => st_mr_rmesg(13),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(81),
I5 => st_mr_rmesg(47),
O => f_mux4_return(25)
);
\gen_fpga.gen_mux_5_8[27].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(116),
I1 => st_mr_rmesg(14),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(82),
I5 => st_mr_rmesg(48),
O => f_mux4_return(26)
);
\gen_fpga.gen_mux_5_8[28].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(117),
I1 => st_mr_rmesg(15),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(83),
I5 => st_mr_rmesg(49),
O => f_mux4_return(27)
);
\gen_fpga.gen_mux_5_8[29].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(118),
I1 => st_mr_rmesg(16),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(84),
I5 => st_mr_rmesg(50),
O => f_mux4_return(28)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(38),
I1 => st_mr_rid(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(26),
I5 => st_mr_rid(14),
O => f_mux4_return(2)
);
\gen_fpga.gen_mux_5_8[30].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(119),
I1 => st_mr_rmesg(17),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(85),
I5 => st_mr_rmesg(51),
O => f_mux4_return(29)
);
\gen_fpga.gen_mux_5_8[31].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(120),
I1 => st_mr_rmesg(18),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(86),
I5 => st_mr_rmesg(52),
O => f_mux4_return(30)
);
\gen_fpga.gen_mux_5_8[32].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(121),
I1 => st_mr_rmesg(19),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(87),
I5 => st_mr_rmesg(53),
O => f_mux4_return(31)
);
\gen_fpga.gen_mux_5_8[33].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(122),
I1 => st_mr_rmesg(20),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(88),
I5 => st_mr_rmesg(54),
O => f_mux4_return(32)
);
\gen_fpga.gen_mux_5_8[34].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(123),
I1 => st_mr_rmesg(21),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(89),
I5 => st_mr_rmesg(55),
O => f_mux4_return(33)
);
\gen_fpga.gen_mux_5_8[35].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(124),
I1 => st_mr_rmesg(22),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(90),
I5 => st_mr_rmesg(56),
O => f_mux4_return(34)
);
\gen_fpga.gen_mux_5_8[36].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(125),
I1 => st_mr_rmesg(23),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(91),
I5 => st_mr_rmesg(57),
O => f_mux4_return(35)
);
\gen_fpga.gen_mux_5_8[37].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(126),
I1 => st_mr_rmesg(24),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(92),
I5 => st_mr_rmesg(58),
O => f_mux4_return(36)
);
\gen_fpga.gen_mux_5_8[38].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(127),
I1 => st_mr_rmesg(25),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(93),
I5 => st_mr_rmesg(59),
O => f_mux4_return(37)
);
\gen_fpga.gen_mux_5_8[39].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(128),
I1 => st_mr_rmesg(26),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(94),
I5 => st_mr_rmesg(60),
O => f_mux4_return(38)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(39),
I1 => st_mr_rid(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(27),
I5 => st_mr_rid(15),
O => f_mux4_return(3)
);
\gen_fpga.gen_mux_5_8[40].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(129),
I1 => st_mr_rmesg(27),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(95),
I5 => st_mr_rmesg(61),
O => f_mux4_return(39)
);
\gen_fpga.gen_mux_5_8[41].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(130),
I1 => st_mr_rmesg(28),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(96),
I5 => st_mr_rmesg(62),
O => f_mux4_return(40)
);
\gen_fpga.gen_mux_5_8[42].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(131),
I1 => st_mr_rmesg(29),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(97),
I5 => st_mr_rmesg(63),
O => f_mux4_return(41)
);
\gen_fpga.gen_mux_5_8[43].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(132),
I1 => st_mr_rmesg(30),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(98),
I5 => st_mr_rmesg(64),
O => f_mux4_return(42)
);
\gen_fpga.gen_mux_5_8[44].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(133),
I1 => st_mr_rmesg(31),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(99),
I5 => st_mr_rmesg(65),
O => f_mux4_return(43)
);
\gen_fpga.gen_mux_5_8[45].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(134),
I1 => st_mr_rmesg(32),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(100),
I5 => st_mr_rmesg(66),
O => f_mux4_return(44)
);
\gen_fpga.gen_mux_5_8[46].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(135),
I1 => st_mr_rmesg(33),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(101),
I5 => st_mr_rmesg(67),
O => f_mux4_return(45)
);
\gen_fpga.gen_mux_5_8[47].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => \m_payload_i_reg[34]_0\(0),
I1 => \m_payload_i_reg[34]_1\(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => \m_payload_i_reg[34]_2\(0),
I5 => \m_payload_i_reg[34]_3\(0),
O => f_mux4_return(46)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(40),
I1 => st_mr_rid(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(28),
I5 => st_mr_rid(16),
O => f_mux4_return(4)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(41),
I1 => st_mr_rid(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(29),
I5 => st_mr_rid(17),
O => f_mux4_return(5)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(42),
I1 => st_mr_rid(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(30),
I5 => st_mr_rid(18),
O => f_mux4_return(6)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(43),
I1 => st_mr_rid(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(31),
I5 => st_mr_rid(19),
O => f_mux4_return(7)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(44),
I1 => st_mr_rid(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(32),
I5 => st_mr_rid(20),
O => f_mux4_return(8)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(45),
I1 => st_mr_rid(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(33),
I5 => st_mr_rid(21),
O => f_mux4_return(9)
);
\gen_no_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => E(0)
);
\gen_no_arbiter.s_ready_i[0]_i_24__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044444444"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => s_axi_arvalid(0),
I2 => \gen_multi_thread.accept_cnt_reg[0]\,
I3 => \^s_axi_rvalid[0]\,
I4 => \m_payload_i_reg[34]_4\,
I5 => \gen_multi_thread.accept_cnt_reg[3]\(0),
O => \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\,
I5 => aa_mi_arvalid,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8AAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\,
I1 => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
I2 => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
I3 => \r_cmd_pop_4__1\,
I4 => match,
I5 => r_issuing_cnt(0),
O => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\
);
\last_rr_hot[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_122_out,
I1 => p_62_out,
I2 => p_40_out,
I3 => \last_rr_hot[0]_i_2_n_0\,
I4 => \last_rr_hot[0]_i_3_n_0\,
I5 => p_6_in,
O => next_rr_hot(0)
);
\last_rr_hot[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_5_in6_in,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_102_out,
I3 => p_82_out,
O => \last_rr_hot[0]_i_2_n_0\
);
\last_rr_hot[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_40_out,
I1 => p_7_in9_in,
I2 => p_8_in,
O => \last_rr_hot[0]_i_3_n_0\
);
\last_rr_hot[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_102_out,
I1 => p_40_out,
I2 => p_122_out,
I3 => \last_rr_hot[1]_i_2_n_0\,
I4 => \last_rr_hot[4]_i_4_n_0\,
I5 => p_7_in9_in,
O => next_rr_hot(1)
);
\last_rr_hot[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_6_in,
I1 => p_5_in6_in,
I2 => p_82_out,
I3 => p_62_out,
O => \last_rr_hot[1]_i_2_n_0\
);
\last_rr_hot[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_82_out,
I1 => m_valid_i_reg_0,
I2 => \last_rr_hot[4]_i_5_n_0\,
I3 => p_40_out,
I4 => \last_rr_hot[2]_i_3_n_0\,
I5 => p_8_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_102_out,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_5_in6_in,
O => \last_rr_hot[2]_i_3_n_0\
);
\last_rr_hot[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_62_out,
I1 => p_102_out,
I2 => p_82_out,
I3 => \last_rr_hot[3]_i_2_n_0\,
I4 => \last_rr_hot[3]_i_3_n_0\,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(3)
);
\last_rr_hot[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_8_in,
I1 => p_7_in9_in,
I2 => p_40_out,
I3 => p_122_out,
O => \last_rr_hot[3]_i_2_n_0\
);
\last_rr_hot[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_82_out,
I1 => p_5_in6_in,
I2 => p_6_in,
O => \last_rr_hot[3]_i_3_n_0\
);
\last_rr_hot[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(3),
I2 => next_rr_hot(2),
I3 => next_rr_hot(1),
I4 => next_rr_hot(0),
I5 => next_rr_hot(4),
O => last_rr_hot
);
\last_rr_hot[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_40_out,
I1 => m_valid_i_reg,
I2 => \last_rr_hot[4]_i_4_n_0\,
I3 => p_102_out,
I4 => \last_rr_hot[4]_i_5_n_0\,
I5 => p_5_in6_in,
O => next_rr_hot(4)
);
\last_rr_hot[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_122_out,
I1 => p_8_in,
I2 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[4]_i_4_n_0\
);
\last_rr_hot[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_62_out,
I1 => p_6_in,
I2 => p_7_in9_in,
O => \last_rr_hot[4]_i_5_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(0),
Q => \last_rr_hot_reg_n_0_[0]\,
R => SR(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(1),
Q => p_5_in6_in,
R => SR(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(2),
Q => p_6_in,
R => SR(0)
);
\last_rr_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(3),
Q => p_7_in9_in,
R => SR(0)
);
\last_rr_hot_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(4),
Q => p_8_in,
S => SR(0)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(0),
I1 => s_axi_rready(0),
I2 => p_122_out,
O => \m_payload_i_reg[0]\(0)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(1),
I1 => s_axi_rready(0),
I2 => p_102_out,
O => \m_payload_i_reg[0]_0\(0)
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(4),
I1 => s_axi_rready(0),
I2 => p_40_out,
O => \m_payload_i_reg[34]\(0)
);
\m_payload_i[46]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(3),
I1 => s_axi_rready(0),
I2 => p_62_out,
O => \m_payload_i_reg[0]_1\(0)
);
\m_payload_i[46]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(2),
I1 => s_axi_rready(0),
I2 => p_82_out,
O => \m_payload_i_reg[0]_2\(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF8"
)
port map (
I0 => \^q\(0),
I1 => p_122_out,
I2 => p_0_in1_in(2),
I3 => p_0_in1_in(1),
I4 => p_0_in1_in(3),
I5 => \^resp_select\(0),
O => \^s_axi_rvalid[0]\
);
\s_axi_rvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(2),
I1 => p_82_out,
O => p_0_in1_in(2)
);
\s_axi_rvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(1),
I1 => p_102_out,
O => p_0_in1_in(1)
);
\s_axi_rvalid[0]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(3),
I1 => p_62_out,
O => p_0_in1_in(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_awready_4 : out STD_LOGIC;
p_22_in : out STD_LOGIC;
p_29_in : out STD_LOGIC;
p_23_in : out STD_LOGIC;
p_25_in : out STD_LOGIC;
\read_cs__0\ : out STD_LOGIC;
mi_arready_4 : out STD_LOGIC;
\m_payload_i_reg[13]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_rready_4 : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
mi_bready_4 : in STD_LOGIC;
\write_cs0__0\ : in STD_LOGIC;
write_cs01_out : in STD_LOGIC;
s_axi_rlast_i0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aresetn_d : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bid_i[11]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^mi_arready_4\ : STD_LOGIC;
signal \^mi_awready_4\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_22_in\ : STD_LOGIC;
signal \^p_23_in\ : STD_LOGIC;
signal \^p_25_in\ : STD_LOGIC;
signal \^p_29_in\ : STD_LOGIC;
signal \^read_cs__0\ : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_3\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair16";
begin
mi_arready_4 <= \^mi_arready_4\;
mi_awready_4 <= \^mi_awready_4\;
p_22_in <= \^p_22_in\;
p_23_in <= \^p_23_in\;
p_25_in <= \^p_25_in\;
p_29_in <= \^p_29_in\;
\read_cs__0\ <= \^read_cs__0\;
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(0),
I1 => \^p_23_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(12),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E22E"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(13),
I1 => \^p_23_in\,
I2 => \gen_axi.read_cnt_reg__0\(0),
I3 => \gen_axi.read_cnt_reg\(1),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(14),
I1 => \gen_axi.read_cnt_reg\(1),
I2 => \gen_axi.read_cnt_reg__0\(0),
I3 => \^p_23_in\,
I4 => \gen_axi.read_cnt_reg\(2),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCAAAA0003AAAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(15),
I1 => \gen_axi.read_cnt_reg__0\(0),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg\(2),
I4 => \^p_23_in\,
I5 => \gen_axi.read_cnt_reg\(3),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCAAAA0003AAAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(16),
I1 => \gen_axi.read_cnt_reg\(2),
I2 => \gen_axi.read_cnt[4]_i_2_n_0\,
I3 => \gen_axi.read_cnt_reg\(3),
I4 => \^p_23_in\,
I5 => \gen_axi.read_cnt_reg\(4),
O => p_0_in(4)
);
\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \gen_axi.read_cnt_reg\(1),
I1 => \gen_axi.read_cnt_reg__0\(0),
O => \gen_axi.read_cnt[4]_i_2_n_0\
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CA3A"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(17),
I1 => \gen_axi.read_cnt[5]_i_2_n_0\,
I2 => \^p_23_in\,
I3 => \gen_axi.read_cnt_reg\(5),
O => p_0_in(5)
);
\gen_axi.read_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg\(3),
I1 => \gen_axi.read_cnt_reg__0\(0),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg\(2),
I4 => \gen_axi.read_cnt_reg\(4),
O => \gen_axi.read_cnt[5]_i_2_n_0\
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CA3A"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(18),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \^p_23_in\,
I3 => \gen_axi.read_cnt_reg\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F40404040404040"
)
port map (
I0 => \^read_cs__0\,
I1 => mi_rready_4,
I2 => \^p_23_in\,
I3 => \^mi_arready_4\,
I4 => aa_mi_arvalid,
I5 => \gen_no_arbiter.m_target_hot_i_reg[4]\(0),
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(19),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg\(6),
I3 => \^p_23_in\,
I4 => \gen_axi.read_cnt_reg\(7),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(2),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg__0\(0),
I4 => \gen_axi.read_cnt_reg\(3),
I5 => \gen_axi.read_cnt_reg\(5),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg__0\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F70707070707070"
)
port map (
I0 => \^read_cs__0\,
I1 => mi_rready_4,
I2 => \^p_23_in\,
I3 => \^mi_arready_4\,
I4 => aa_mi_arvalid,
I5 => \gen_no_arbiter.m_target_hot_i_reg[4]\(0),
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^p_23_in\,
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FBBB0000"
)
port map (
I0 => \^mi_arready_4\,
I1 => \^p_23_in\,
I2 => \^read_cs__0\,
I3 => mi_rready_4,
I4 => aresetn_d,
I5 => E(0),
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_axi.read_cnt[4]_i_2_n_0\,
I1 => \gen_axi.read_cnt_reg\(6),
I2 => \gen_axi.read_cnt_reg\(7),
I3 => \gen_axi.s_axi_arready_i_i_3_n_0\,
I4 => \gen_axi.read_cnt_reg\(2),
I5 => \gen_axi.read_cnt_reg\(3),
O => \^read_cs__0\
);
\gen_axi.s_axi_arready_i_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(5),
O => \gen_axi.s_axi_arready_i_i_3_n_0\
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready_4\,
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFBB0000F0FF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => Q(0),
I2 => mi_bready_4,
I3 => write_cs(1),
I4 => write_cs(0),
I5 => \^mi_awready_4\,
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready_4\,
R => SR(0)
);
\gen_axi.s_axi_bid_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => write_cs(1),
I1 => write_cs(0),
I2 => m_ready_d(0),
I3 => aa_sa_awvalid,
I4 => Q(0),
I5 => \^mi_awready_4\,
O => \gen_axi.s_axi_bid_i[11]_i_1_n_0\
);
\gen_axi.s_axi_bid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(0),
Q => \m_payload_i_reg[13]\(0),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(10),
Q => \m_payload_i_reg[13]\(10),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(11),
Q => \m_payload_i_reg[13]\(11),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(1),
Q => \m_payload_i_reg[13]\(1),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(2),
Q => \m_payload_i_reg[13]\(2),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(3),
Q => \m_payload_i_reg[13]\(3),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(4),
Q => \m_payload_i_reg[13]\(4),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(5),
Q => \m_payload_i_reg[13]\(5),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(6),
Q => \m_payload_i_reg[13]\(6),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(7),
Q => \m_payload_i_reg[13]\(7),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(8),
Q => \m_payload_i_reg[13]\(8),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(9),
Q => \m_payload_i_reg[13]\(9),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFF00C0"
)
port map (
I0 => mi_bready_4,
I1 => write_cs(0),
I2 => \write_cs0__0\,
I3 => write_cs(1),
I4 => \^p_29_in\,
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => \^p_29_in\,
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(0),
Q => \skid_buffer_reg[46]\(0),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(10),
Q => \skid_buffer_reg[46]\(10),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(11),
Q => \skid_buffer_reg[46]\(11),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(1),
Q => \skid_buffer_reg[46]\(1),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(2),
Q => \skid_buffer_reg[46]\(2),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(3),
Q => \skid_buffer_reg[46]\(3),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(4),
Q => \skid_buffer_reg[46]\(4),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(5),
Q => \skid_buffer_reg[46]\(5),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(6),
Q => \skid_buffer_reg[46]\(6),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(7),
Q => \skid_buffer_reg[46]\(7),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(8),
Q => \skid_buffer_reg[46]\(8),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(9),
Q => \skid_buffer_reg[46]\(9),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFBFFAAAA0800"
)
port map (
I0 => s_axi_rlast_i0,
I1 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I4 => E(0),
I5 => \^p_25_in\,
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_axi.read_cnt_reg\(2),
I1 => \gen_axi.read_cnt_reg\(3),
O => \gen_axi.s_axi_rlast_i_i_3_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(5),
I2 => \gen_axi.read_cnt_reg\(6),
I3 => \gen_axi.read_cnt_reg\(7),
I4 => mi_rready_4,
I5 => \^p_23_in\,
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => \^p_25_in\,
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF5F000C"
)
port map (
I0 => \write_cs0__0\,
I1 => write_cs01_out,
I2 => write_cs(0),
I3 => write_cs(1),
I4 => \^p_22_in\,
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => \^p_22_in\,
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4522"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => write_cs(1),
I2 => \write_cs0__0\,
I3 => write_cs(0),
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE00FE44"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => write_cs(1),
I2 => \write_cs0__0\,
I3 => write_cs(0),
I4 => mi_bready_4,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => write_cs(1),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter is
port (
\s_axi_awready[0]\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
ss_wr_awvalid : out STD_LOGIC;
ss_wr_awready : in STD_LOGIC;
ss_aa_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_valid_i_i_2__0\ : label is "soft_lutpair190";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair190";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready,
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000C8C0"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready,
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_valid_i_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
O => ss_wr_awvalid
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => \^m_ready_d\(1),
I1 => ss_wr_awready,
I2 => \^m_ready_d\(0),
I3 => ss_aa_awready,
O => \s_axi_awready[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5 is
port (
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_axi.s_axi_awready_i_reg\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[19]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[3].w_issuing_cnt_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 15 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_108_out : in STD_LOGIC;
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_88_out : in STD_LOGIC;
p_68_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\mi_awready_mux__3\ : in STD_LOGIC;
\s_ready_i0__1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\sa_wm_awready_mux__3\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5 : entity is "axi_crossbar_v2_1_14_splitter";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5 is
signal \^gen_axi.s_axi_awready_i_reg\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\ : STD_LOGIC;
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_awready_i_i_2\ : label is "soft_lutpair194";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[10]_i_1\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_2\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[18]_i_1\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_2\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[26]_i_1\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_2\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_1\ : label is "soft_lutpair194";
begin
\gen_axi.s_axi_awready_i_reg\ <= \^gen_axi.s_axi_awready_i_reg\;
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\gen_axi.s_axi_awready_i_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_ready_d\(1),
I1 => aa_sa_awvalid,
O => \^gen_axi.s_axi_awready_i_reg\
);
\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(1),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(1),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(3),
I4 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(0),
I2 => m_axi_awready(0),
I3 => s_axi_bready(0),
I4 => p_128_out,
I5 => \chosen_reg[3]\(0),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I1 => w_issuing_cnt(4),
I2 => w_issuing_cnt(5),
I3 => w_issuing_cnt(6),
O => D(1)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(5),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(7),
I4 => w_issuing_cnt(6),
O => D(2)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(1),
I2 => m_axi_awready(1),
I3 => s_axi_bready(0),
I4 => p_108_out,
I5 => \chosen_reg[3]\(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(5),
O => D(0)
);
\gen_master_slots[2].w_issuing_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(8),
I1 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I2 => w_issuing_cnt(9),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(0)
);
\gen_master_slots[2].w_issuing_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I1 => w_issuing_cnt(8),
I2 => w_issuing_cnt(9),
I3 => w_issuing_cnt(10),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(1)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(9),
I1 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I2 => w_issuing_cnt(8),
I3 => w_issuing_cnt(11),
I4 => w_issuing_cnt(10),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(2)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(2),
I2 => m_axi_awready(2),
I3 => s_axi_bready(0),
I4 => p_88_out,
I5 => \chosen_reg[3]\(2),
O => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\
);
\gen_master_slots[3].w_issuing_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(12),
I1 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I2 => w_issuing_cnt(13),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(0)
);
\gen_master_slots[3].w_issuing_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I1 => w_issuing_cnt(12),
I2 => w_issuing_cnt(13),
I3 => w_issuing_cnt(14),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(1)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(13),
I1 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I2 => w_issuing_cnt(12),
I3 => w_issuing_cnt(15),
I4 => w_issuing_cnt(14),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(2)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(3),
I2 => m_axi_awready(3),
I3 => s_axi_bready(0),
I4 => p_68_out,
I5 => \chosen_reg[3]\(3),
O => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => aa_sa_awvalid,
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => \mi_awready_mux__3\,
I4 => \^m_ready_d\(0),
I5 => \sa_wm_awready_mux__3\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000C8C0"
)
port map (
I0 => aa_sa_awvalid,
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => \mi_awready_mux__3\,
I4 => \s_ready_i0__1\(0),
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
push : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
out0 : in STD_LOGIC_VECTOR ( 0 to 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
signal \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => D(0),
Q => \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0EEFFFFF0EE0000"
)
port map (
I0 => \s_axi_awaddr[30]\(1),
I1 => \s_axi_awaddr[30]\(0),
I2 => \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\,
I3 => out0(0),
I4 => load_s1,
I5 => m_select_enc(0),
O => \storage_data1_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ is
port (
\storage_data1_reg[1]\ : out STD_LOGIC;
push : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
out0 : in STD_LOGIC_VECTOR ( 0 to 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ is
signal p_2_out : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => D(0),
Q => p_2_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0EEFFFFF0EE0000"
)
port map (
I0 => \s_axi_awaddr[30]\(1),
I1 => \s_axi_awaddr[30]\(0),
I2 => p_2_out,
I3 => out0(0),
I4 => load_s1,
I5 => m_select_enc(0),
O => \storage_data1_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ is
port (
push : out STD_LOGIC;
\storage_data1_reg[2]\ : out STD_LOGIC;
\m_aready__1\ : out STD_LOGIC;
\m_aready0__3\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
match : in STD_LOGIC;
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
ss_wr_awready : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ is
signal \^m_aready0__3\ : STD_LOGIC;
signal \^m_aready__1\ : STD_LOGIC;
signal p_3_out : STD_LOGIC;
signal \^push\ : STD_LOGIC;
signal \s_axi_wready[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\m_aready0__3\ <= \^m_aready0__3\;
\m_aready__1\ <= \^m_aready__1\;
push <= \^push\;
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => \^push\,
CLK => aclk,
D => D(0),
Q => p_3_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0088000000F80000"
)
port map (
I0 => ss_wr_awready,
I1 => out0(0),
I2 => out0(1),
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => \^m_aready__1\,
O => \^push\
);
\m_valid_i_i_1__8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => s_axi_wlast(0),
I1 => m_avalid,
I2 => s_axi_wvalid(0),
I3 => \^m_aready0__3\,
O => \^m_aready__1\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAFEAAAAAAAEA"
)
port map (
I0 => \s_axi_wready[0]_INST_0_i_2_n_0\,
I1 => m_axi_wready(1),
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
I5 => m_axi_wready(2),
O => \^m_aready0__3\
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0000CA000000CA"
)
port map (
I0 => m_axi_wready(0),
I1 => p_22_in,
I2 => m_select_enc(2),
I3 => m_select_enc(1),
I4 => m_select_enc(0),
I5 => m_axi_wready(3),
O => \s_axi_wready[0]_INST_0_i_2_n_0\
);
\storage_data1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"C5FFC500"
)
port map (
I0 => match,
I1 => p_3_out,
I2 => out0(0),
I3 => load_s1,
I4 => m_select_enc(2),
O => \storage_data1_reg[2]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
\m_payload_i_reg[2]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
mi_bready_4 : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_29_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^mi_bready_4\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
begin
\m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
mi_bready_4 <= \^mi_bready_4\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => '0'
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => p_29_in,
I1 => \^mi_bready_4\,
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[2]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__0_n_0\
);
\m_valid_i_i_1__9\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg_0\,
O => \^m_valid_i_reg_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^m_payload_i_reg[2]_0\,
R => \^m_valid_i_reg_0\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
I1 => p_29_in,
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^mi_bready_4\,
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
\m_axi_bid[35]\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal \s_ready_i_i_1__3_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__3_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__3_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
\m_axi_bid[23]\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__1_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__1_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__1_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
p_108_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__0_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\last_rr_hot[2]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_108_out,
O => \chosen_reg[2]\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_2_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__0_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__0_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
\chosen_reg[4]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
p_88_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^p_1_in\ : STD_LOGIC;
signal s_ready_i_i_2_n_0 : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
p_1_in <= \^p_1_in\;
\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(1),
I1 => aresetn,
O => \aresetn_d_reg[1]\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => p_0_in(1),
R => '0'
);
\last_rr_hot[4]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_88_out,
O => \chosen_reg[4]\
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]_0\
);
s_ready_i_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => \^p_1_in\
);
s_ready_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_1\,
O => s_ready_i_i_2_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i_i_2_n_0,
Q => \^m_axi_bready\(0),
R => \^p_1_in\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\skid_buffer_reg[34]_0\ : out STD_LOGIC;
\r_cmd_pop_4__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_23_in : in STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_25_in : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \s_ready_i_i_1__6_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 34 );
signal \^skid_buffer_reg[34]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__3\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__3\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__3\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__3\ : label is "soft_lutpair114";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0);
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\skid_buffer_reg[34]_0\ <= \^skid_buffer_reg[34]_0\;
\gen_master_slots[4].r_issuing_cnt[32]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I1 => \chosen_reg[4]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \r_cmd_pop_4__1\
);
\m_payload_i[34]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_25_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(0),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(1),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(2),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(3),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(4),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[40]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(5),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(6),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(7),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(8),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(9),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(10),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(11),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_valid_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^skid_buffer_reg[34]_0\,
I1 => p_23_in,
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[4]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[4]\(0),
I3 => \^skid_buffer_reg[34]_0\,
I4 => p_23_in,
O => \s_ready_i_i_1__6_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__6_n_0\,
Q => \^skid_buffer_reg[34]_0\,
R => p_1_in
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => p_25_in,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[3]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_3__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[4]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_39_in : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_3__1\ : STD_LOGIC;
signal \s_ready_i_i_1__7_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_3\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_3\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__7\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__2\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__2\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__2\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__2\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__2\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__2\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair110";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[3]\ <= \^m_axi_rready[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_3__1\ <= \^r_cmd_pop_3__1\;
\gen_master_slots[3].r_issuing_cnt[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1),
I1 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2),
I2 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0),
I3 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3),
I4 => \^r_cmd_pop_3__1\,
I5 => p_39_in,
O => E(0)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[3]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_3__1\
);
\gen_no_arbiter.s_ready_i[0]_i_38__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_3__1\,
I1 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0),
I2 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3),
I3 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1),
I4 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\last_rr_hot[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => p_82_out,
O => \chosen_reg[4]\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[3]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[3]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[3]\(0),
I3 => \^m_axi_rready[3]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__7_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__7_n_0\,
Q => \^m_axi_rready[3]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_2__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_57_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[24]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\chosen_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\ : STD_LOGIC;
signal \^m_axi_rready[2]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_2__1\ : STD_LOGIC;
signal \s_ready_i_i_1__8_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__6\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair85";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[2]\ <= \^m_axi_rready[2]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_2__1\ <= \^r_cmd_pop_2__1\;
\gen_master_slots[2].r_issuing_cnt[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1),
I1 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2),
I2 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0),
I3 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3),
I4 => \^r_cmd_pop_2__1\,
I5 => p_57_in,
O => E(0)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[2]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_2__1\
);
\gen_no_arbiter.s_ready_i[0]_i_26__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ECA0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\,
I1 => \gen_master_slots[3].r_issuing_cnt_reg[24]\,
I2 => D(0),
I3 => D(1),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_37__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_2__1\,
I1 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0),
I2 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3),
I3 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1),
I4 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\
);
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[2]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[2]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__8\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[2]\(0),
I3 => \^m_axi_rready[2]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__8_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__8_n_0\,
Q => \^m_axi_rready[2]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_1__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_75_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\chosen_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\ : STD_LOGIC;
signal \^m_axi_rready[1]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_1__1\ : STD_LOGIC;
signal \s_ready_i_i_1__5_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__5\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair62";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[1]\ <= \^m_axi_rready[1]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_1__1\ <= \^r_cmd_pop_1__1\;
\gen_master_slots[1].r_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1),
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3),
I4 => \^r_cmd_pop_1__1\,
I5 => p_75_in,
O => E(0)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_1__1\
);
\gen_no_arbiter.s_ready_i[0]_i_25__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\,
I1 => D(0),
I2 => ADDRESS_HIT_0,
I3 => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_35__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_1__1\,
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1),
I4 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[1]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[1]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[1]\(0),
I3 => \^m_axi_rready[1]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__5_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__5_n_0\,
Q => \^m_axi_rready[1]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_0__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : in STD_LOGIC;
p_102_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[0]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_0__1\ : STD_LOGIC;
signal \s_ready_i_i_1__4_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__4\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair40";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[0]\ <= \^m_axi_rready[0]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_0__1\ <= \^r_cmd_pop_0__1\;
\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I4 => \^r_cmd_pop_0__1\,
I5 => p_93_in,
O => E(0)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[0]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_0__1\
);
\gen_no_arbiter.s_ready_i[0]_i_36__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_0__1\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I4 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\last_rr_hot[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => p_102_out,
O => \chosen_reg[2]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[0]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[0]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[0]\(0),
I3 => \^m_axi_rready[0]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__4_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__4_n_0\,
Q => \^m_axi_rready[0]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc is
port (
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
resp_select : in STD_LOGIC_VECTOR ( 0 to 0 );
f_mux4_return : in STD_LOGIC_VECTOR ( 46 downto 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\thread_valid_0__2\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\thread_valid_3__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_4 : in STD_LOGIC;
\thread_valid_4__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_7 : in STD_LOGIC;
\thread_valid_7__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_6 : in STD_LOGIC;
\thread_valid_6__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_5 : in STD_LOGIC;
\thread_valid_5__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_2 : in STD_LOGIC;
\thread_valid_2__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_1 : in STD_LOGIC;
\thread_valid_1__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc is
signal \any_pop__1\ : STD_LOGIC;
signal \^s_axi_rid[0]\ : STD_LOGIC;
signal \^s_axi_rid[10]\ : STD_LOGIC;
signal \^s_axi_rid[11]\ : STD_LOGIC;
signal \^s_axi_rid[1]\ : STD_LOGIC;
signal \^s_axi_rid[2]\ : STD_LOGIC;
signal \^s_axi_rid[3]\ : STD_LOGIC;
signal \^s_axi_rid[4]\ : STD_LOGIC;
signal \^s_axi_rid[5]\ : STD_LOGIC;
signal \^s_axi_rid[6]\ : STD_LOGIC;
signal \^s_axi_rid[7]\ : STD_LOGIC;
signal \^s_axi_rid[8]\ : STD_LOGIC;
signal \^s_axi_rid[9]\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[0].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[10].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[11].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[12].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[13].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[15].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[16].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[17].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[18].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[19].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[1].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[20].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[21].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[22].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[23].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[24].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[25].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[26].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[27].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[28].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[29].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[2].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[30].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[31].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[32].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[33].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[34].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[35].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[36].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[37].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[38].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[39].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[3].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[40].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[41].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[42].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[43].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[44].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[45].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[46].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[47].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[4].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[5].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[6].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[7].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[8].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[9].mux_s2_inst\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_34__0\ : label is "soft_lutpair128";
begin
\s_axi_rid[0]\ <= \^s_axi_rid[0]\;
\s_axi_rid[10]\ <= \^s_axi_rid[10]\;
\s_axi_rid[11]\ <= \^s_axi_rid[11]\;
\s_axi_rid[1]\ <= \^s_axi_rid[1]\;
\s_axi_rid[2]\ <= \^s_axi_rid[2]\;
\s_axi_rid[3]\ <= \^s_axi_rid[3]\;
\s_axi_rid[4]\ <= \^s_axi_rid[4]\;
\s_axi_rid[5]\ <= \^s_axi_rid[5]\;
\s_axi_rid[6]\ <= \^s_axi_rid[6]\;
\s_axi_rid[7]\ <= \^s_axi_rid[7]\;
\s_axi_rid[8]\ <= \^s_axi_rid[8]\;
\s_axi_rid[9]\ <= \^s_axi_rid[9]\;
s_axi_rlast(0) <= \^s_axi_rlast\(0);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(0),
I1 => st_mr_rid(0),
O => \^s_axi_rid[0]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(10),
I1 => st_mr_rid(10),
O => \^s_axi_rid[10]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(11),
I1 => st_mr_rid(11),
O => \^s_axi_rid[11]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(12),
I1 => '1',
O => s_axi_rresp(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(13),
I1 => '1',
O => s_axi_rresp(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(14),
I1 => '0',
O => s_axi_rdata(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[16].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(15),
I1 => '0',
O => s_axi_rdata(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[17].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(16),
I1 => '0',
O => s_axi_rdata(2),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[18].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(17),
I1 => '0',
O => s_axi_rdata(3),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[19].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(18),
I1 => '0',
O => s_axi_rdata(4),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(1),
I1 => st_mr_rid(1),
O => \^s_axi_rid[1]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[20].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(19),
I1 => '0',
O => s_axi_rdata(5),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[21].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(20),
I1 => '0',
O => s_axi_rdata(6),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[22].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(21),
I1 => '0',
O => s_axi_rdata(7),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[23].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(22),
I1 => '0',
O => s_axi_rdata(8),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[24].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(23),
I1 => '0',
O => s_axi_rdata(9),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[25].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(24),
I1 => '0',
O => s_axi_rdata(10),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[26].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(25),
I1 => '0',
O => s_axi_rdata(11),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[27].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(26),
I1 => '0',
O => s_axi_rdata(12),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[28].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(27),
I1 => '0',
O => s_axi_rdata(13),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[29].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(28),
I1 => '0',
O => s_axi_rdata(14),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(2),
I1 => st_mr_rid(2),
O => \^s_axi_rid[2]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[30].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(29),
I1 => '0',
O => s_axi_rdata(15),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[31].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(30),
I1 => '0',
O => s_axi_rdata(16),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[32].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(31),
I1 => '0',
O => s_axi_rdata(17),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[33].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(32),
I1 => '0',
O => s_axi_rdata(18),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[34].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(33),
I1 => '0',
O => s_axi_rdata(19),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[35].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(34),
I1 => '0',
O => s_axi_rdata(20),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[36].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(35),
I1 => '0',
O => s_axi_rdata(21),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[37].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(36),
I1 => '0',
O => s_axi_rdata(22),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[38].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(37),
I1 => '0',
O => s_axi_rdata(23),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[39].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(38),
I1 => '0',
O => s_axi_rdata(24),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(3),
I1 => st_mr_rid(3),
O => \^s_axi_rid[3]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[40].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(39),
I1 => '0',
O => s_axi_rdata(25),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[41].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(40),
I1 => '0',
O => s_axi_rdata(26),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[42].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(41),
I1 => '0',
O => s_axi_rdata(27),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[43].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(42),
I1 => '0',
O => s_axi_rdata(28),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[44].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(43),
I1 => '0',
O => s_axi_rdata(29),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[45].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(44),
I1 => '0',
O => s_axi_rdata(30),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[46].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(45),
I1 => '0',
O => s_axi_rdata(31),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[47].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(46),
I1 => \m_payload_i_reg[34]\(0),
O => \^s_axi_rlast\(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(4),
I1 => st_mr_rid(4),
O => \^s_axi_rid[4]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(5),
I1 => st_mr_rid(5),
O => \^s_axi_rid[5]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(6),
I1 => st_mr_rid(6),
O => \^s_axi_rid[6]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(7),
I1 => st_mr_rid(7),
O => \^s_axi_rid[7]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(8),
I1 => st_mr_rid(8),
O => \^s_axi_rid[8]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(9),
I1 => st_mr_rid(9),
O => \^s_axi_rid[9]\,
S => resp_select(0)
);
\gen_multi_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A65"
)
port map (
I0 => Q(0),
I1 => \any_pop__1\,
I2 => S_AXI_ARREADY(0),
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFF2200D"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => \any_pop__1\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => \any_pop__1\,
I5 => S_AXI_ARREADY(0),
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800FFAE0051"
)
port map (
I0 => Q(1),
I1 => S_AXI_ARREADY(0),
I2 => \any_pop__1\,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_0,
I1 => \any_pop__1\,
I2 => \thread_valid_0__2\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_1,
I1 => \any_pop__1\,
I2 => \thread_valid_1__2\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_2,
I1 => \any_pop__1\,
I2 => \thread_valid_2__2\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_3,
I1 => \any_pop__1\,
I2 => \thread_valid_3__2\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_4,
I1 => \any_pop__1\,
I2 => \thread_valid_4__2\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_5,
I1 => \any_pop__1\,
I2 => \thread_valid_5__2\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_6,
I1 => \any_pop__1\,
I2 => \thread_valid_6__2\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_7,
I1 => \any_pop__1\,
I2 => \thread_valid_7__2\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rlast\(0),
I2 => \chosen_reg[0]\,
O => \any_pop__1\
);
\gen_no_arbiter.s_ready_i[0]_i_34__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_rlast\(0),
I1 => s_axi_rready(0),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\i__carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \^s_axi_rid[11]\,
O => S(3)
);
\i__carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \^s_axi_rid[8]\,
O => S(2)
);
\i__carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \^s_axi_rid[5]\,
O => S(1)
);
\i__carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \^s_axi_rid[2]\,
O => S(0)
);
p_10_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
p_10_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
p_10_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
p_10_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
p_12_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
p_12_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
p_12_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
p_12_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
p_14_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3)
);
p_14_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2)
);
p_14_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1)
);
p_14_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
p_2_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
p_2_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
p_2_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
p_2_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
p_4_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
p_4_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
p_4_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
p_4_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
p_6_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
p_6_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
p_6_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
p_6_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
p_8_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3)
);
p_8_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2)
);
p_8_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1)
);
p_8_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ is
port (
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
p_0_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
resp_select : in STD_LOGIC_VECTOR ( 0 to 0 );
f_mux4_return : in STD_LOGIC_VECTOR ( 13 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
cmd_push_0 : in STD_LOGIC;
\thread_valid_0__2\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\thread_valid_3__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_4 : in STD_LOGIC;
\thread_valid_4__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_7 : in STD_LOGIC;
\thread_valid_7__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_6 : in STD_LOGIC;
\thread_valid_6__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_5 : in STD_LOGIC;
\thread_valid_5__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_2 : in STD_LOGIC;
\thread_valid_2__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_1 : in STD_LOGIC;
\thread_valid_1__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ : entity is "generic_baseblocks_v2_1_0_mux_enc";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ is
signal \any_pop__1\ : STD_LOGIC;
signal \^p_0_out\ : STD_LOGIC;
signal \^s_axi_bid[0]\ : STD_LOGIC;
signal \^s_axi_bid[10]\ : STD_LOGIC;
signal \^s_axi_bid[11]\ : STD_LOGIC;
signal \^s_axi_bid[1]\ : STD_LOGIC;
signal \^s_axi_bid[2]\ : STD_LOGIC;
signal \^s_axi_bid[3]\ : STD_LOGIC;
signal \^s_axi_bid[4]\ : STD_LOGIC;
signal \^s_axi_bid[5]\ : STD_LOGIC;
signal \^s_axi_bid[6]\ : STD_LOGIC;
signal \^s_axi_bid[7]\ : STD_LOGIC;
signal \^s_axi_bid[8]\ : STD_LOGIC;
signal \^s_axi_bid[9]\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[0].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[10].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[11].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[12].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[13].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[15].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[1].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[2].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[3].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[4].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[5].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[6].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[7].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[8].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[9].mux_s2_inst\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1\ : label is "soft_lutpair162";
begin
p_0_out <= \^p_0_out\;
\s_axi_bid[0]\ <= \^s_axi_bid[0]\;
\s_axi_bid[10]\ <= \^s_axi_bid[10]\;
\s_axi_bid[11]\ <= \^s_axi_bid[11]\;
\s_axi_bid[1]\ <= \^s_axi_bid[1]\;
\s_axi_bid[2]\ <= \^s_axi_bid[2]\;
\s_axi_bid[3]\ <= \^s_axi_bid[3]\;
\s_axi_bid[4]\ <= \^s_axi_bid[4]\;
\s_axi_bid[5]\ <= \^s_axi_bid[5]\;
\s_axi_bid[6]\ <= \^s_axi_bid[6]\;
\s_axi_bid[7]\ <= \^s_axi_bid[7]\;
\s_axi_bid[8]\ <= \^s_axi_bid[8]\;
\s_axi_bid[9]\ <= \^s_axi_bid[9]\;
\gen_fpga.gen_mux_5_8[0].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(0),
I1 => st_mr_bid(0),
O => \^s_axi_bid[0]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(10),
I1 => st_mr_bid(10),
O => \^s_axi_bid[10]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(11),
I1 => st_mr_bid(11),
O => \^s_axi_bid[11]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(12),
I1 => '1',
O => s_axi_bresp(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(13),
I1 => '1',
O => s_axi_bresp(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => '1',
I1 => '1',
O => \^p_0_out\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(1),
I1 => st_mr_bid(1),
O => \^s_axi_bid[1]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(2),
I1 => st_mr_bid(2),
O => \^s_axi_bid[2]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(3),
I1 => st_mr_bid(3),
O => \^s_axi_bid[3]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(4),
I1 => st_mr_bid(4),
O => \^s_axi_bid[4]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(5),
I1 => st_mr_bid(5),
O => \^s_axi_bid[5]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(6),
I1 => st_mr_bid(6),
O => \^s_axi_bid[6]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(7),
I1 => st_mr_bid(7),
O => \^s_axi_bid[7]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(8),
I1 => st_mr_bid(8),
O => \^s_axi_bid[8]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(9),
I1 => st_mr_bid(9),
O => \^s_axi_bid[9]\,
S => resp_select(0)
);
\gen_multi_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A65"
)
port map (
I0 => Q(0),
I1 => \any_pop__1\,
I2 => \m_ready_d_reg[1]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFF2200D"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \any_pop__1\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => \any_pop__1\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800FFAE0051"
)
port map (
I0 => Q(1),
I1 => \m_ready_d_reg[1]\,
I2 => \any_pop__1\,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_0,
I1 => \any_pop__1\,
I2 => \thread_valid_0__2\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_1,
I1 => \any_pop__1\,
I2 => \thread_valid_1__2\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_2,
I1 => \any_pop__1\,
I2 => \thread_valid_2__2\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_3,
I1 => \any_pop__1\,
I2 => \thread_valid_3__2\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_4,
I1 => \any_pop__1\,
I2 => \thread_valid_4__2\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_5,
I1 => \any_pop__1\,
I2 => \thread_valid_5__2\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_6,
I1 => \any_pop__1\,
I2 => \thread_valid_6__2\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_7,
I1 => \any_pop__1\,
I2 => \thread_valid_7__2\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_bready(0),
I1 => \^p_0_out\,
I2 => m_valid_i_reg,
O => \any_pop__1\
);
\i__carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \^s_axi_bid[11]\,
O => S(3)
);
\i__carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \^s_axi_bid[8]\,
O => S(2)
);
\i__carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \^s_axi_bid[5]\,
O => S(1)
);
\i__carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \^s_axi_bid[2]\,
O => S(0)
);
\p_10_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
\p_10_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
\p_10_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
\p_10_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
\p_12_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
\p_12_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
\p_12_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
\p_12_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
\p_14_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3)
);
\p_14_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2)
);
\p_14_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1)
);
\p_14_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\p_2_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
\p_2_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
\p_2_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
\p_2_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
\p_4_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
\p_4_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
\p_4_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
\p_4_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
\p_6_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
\p_6_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
\p_6_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
\p_6_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
\p_8_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3)
);
\p_8_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2)
);
\p_8_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1)
);
\p_8_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor is
port (
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\s_axi_rvalid[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 59 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
match : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\s_axi_araddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : in STD_LOGIC;
st_mr_rmesg : in STD_LOGIC_VECTOR ( 135 downto 0 );
\m_payload_i_reg[34]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_62_out : in STD_LOGIC;
p_102_out : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
p_40_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_arid[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \accum_push_5__0\ : STD_LOGIC;
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 58 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal aid_match_00_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal \aid_match_0__0\ : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal aid_match_10_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal \aid_match_1__0\ : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal aid_match_20_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal \aid_match_2__0\ : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal aid_match_30_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal \aid_match_3__0\ : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal aid_match_40_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal \aid_match_4__0\ : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal aid_match_50_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal \aid_match_5__0\ : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal aid_match_60_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal \aid_match_6__0\ : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal aid_match_70_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal \aid_match_7__0\ : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal f_mux4_return : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \gen_multi_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_47\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_48\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_49\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_50\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_51\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_52\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_53\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_54\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_55\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_56\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_57\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_58\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_59\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_60\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_61\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_62\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_63\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_64\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_65\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_66\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_67\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_68\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_69\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_70\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_71\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_72\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_73\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_74\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_75\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_76\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_77\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_78\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_79\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_80\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_81\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_82\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_83\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_84\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_85\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_86\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_87\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_88\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_89\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_90\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_91\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_31_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal resp_select : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^s_axi_rvalid[0]\ : STD_LOGIC;
signal \thread_valid_0__2\ : STD_LOGIC;
signal \thread_valid_1__2\ : STD_LOGIC;
signal \thread_valid_2__2\ : STD_LOGIC;
signal \thread_valid_3__2\ : STD_LOGIC;
signal \thread_valid_4__2\ : STD_LOGIC;
signal \thread_valid_5__2\ : STD_LOGIC;
signal \thread_valid_6__2\ : STD_LOGIC;
signal \thread_valid_7__2\ : STD_LOGIC;
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_10__0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13__0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_16__0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_19__0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_20__0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_27__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_29__0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_32__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_33__0\ : label is "soft_lutpair155";
begin
D(0) <= \^d\(0);
\s_axi_rvalid[0]\ <= \^s_axi_rvalid[0]\;
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_00_carry_i_1_n_0,
S(2) => aid_match_00_carry_i_2_n_0,
S(1) => aid_match_00_carry_i_3_n_0,
S(0) => aid_match_00_carry_i_4_n_0
);
aid_match_00_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
O => aid_match_00_carry_i_1_n_0
);
aid_match_00_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
O => aid_match_00_carry_i_2_n_0
);
aid_match_00_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
O => aid_match_00_carry_i_3_n_0
);
aid_match_00_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
O => aid_match_00_carry_i_4_n_0
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_10_carry_i_1_n_0,
S(2) => aid_match_10_carry_i_2_n_0,
S(1) => aid_match_10_carry_i_3_n_0,
S(0) => aid_match_10_carry_i_4_n_0
);
aid_match_10_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
I5 => \s_axi_arid[11]\(11),
O => aid_match_10_carry_i_1_n_0
);
aid_match_10_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
I5 => \s_axi_arid[11]\(8),
O => aid_match_10_carry_i_2_n_0
);
aid_match_10_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
I5 => \s_axi_arid[11]\(5),
O => aid_match_10_carry_i_3_n_0
);
aid_match_10_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
I5 => \s_axi_arid[11]\(2),
O => aid_match_10_carry_i_4_n_0
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_20_carry_i_1_n_0,
S(2) => aid_match_20_carry_i_2_n_0,
S(1) => aid_match_20_carry_i_3_n_0,
S(0) => aid_match_20_carry_i_4_n_0
);
aid_match_20_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
O => aid_match_20_carry_i_1_n_0
);
aid_match_20_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
O => aid_match_20_carry_i_2_n_0
);
aid_match_20_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
O => aid_match_20_carry_i_3_n_0
);
aid_match_20_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
O => aid_match_20_carry_i_4_n_0
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_30_carry_i_1_n_0,
S(2) => aid_match_30_carry_i_2_n_0,
S(1) => aid_match_30_carry_i_3_n_0,
S(0) => aid_match_30_carry_i_4_n_0
);
aid_match_30_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
O => aid_match_30_carry_i_1_n_0
);
aid_match_30_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
O => aid_match_30_carry_i_2_n_0
);
aid_match_30_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
O => aid_match_30_carry_i_3_n_0
);
aid_match_30_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
O => aid_match_30_carry_i_4_n_0
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_40_carry_i_1_n_0,
S(2) => aid_match_40_carry_i_2_n_0,
S(1) => aid_match_40_carry_i_3_n_0,
S(0) => aid_match_40_carry_i_4_n_0
);
aid_match_40_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
O => aid_match_40_carry_i_1_n_0
);
aid_match_40_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
O => aid_match_40_carry_i_2_n_0
);
aid_match_40_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
O => aid_match_40_carry_i_3_n_0
);
aid_match_40_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
O => aid_match_40_carry_i_4_n_0
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_50_carry_i_1_n_0,
S(2) => aid_match_50_carry_i_2_n_0,
S(1) => aid_match_50_carry_i_3_n_0,
S(0) => aid_match_50_carry_i_4_n_0
);
aid_match_50_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
O => aid_match_50_carry_i_1_n_0
);
aid_match_50_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
O => aid_match_50_carry_i_2_n_0
);
aid_match_50_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
O => aid_match_50_carry_i_3_n_0
);
aid_match_50_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
O => aid_match_50_carry_i_4_n_0
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_60_carry_i_1_n_0,
S(2) => aid_match_60_carry_i_2_n_0,
S(1) => aid_match_60_carry_i_3_n_0,
S(0) => aid_match_60_carry_i_4_n_0
);
aid_match_60_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
O => aid_match_60_carry_i_1_n_0
);
aid_match_60_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
O => aid_match_60_carry_i_2_n_0
);
aid_match_60_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
O => aid_match_60_carry_i_3_n_0
);
aid_match_60_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
O => aid_match_60_carry_i_4_n_0
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_70_carry_i_1_n_0,
S(2) => aid_match_70_carry_i_2_n_0,
S(1) => aid_match_70_carry_i_3_n_0,
S(0) => aid_match_70_carry_i_4_n_0
);
aid_match_70_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
O => aid_match_70_carry_i_1_n_0
);
aid_match_70_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
O => aid_match_70_carry_i_2_n_0
);
aid_match_70_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
O => aid_match_70_carry_i_3_n_0
);
aid_match_70_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
O => aid_match_70_carry_i_4_n_0
);
\gen_multi_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.accept_cnt[0]_i_1_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_58\,
Q => \gen_multi_thread.accept_cnt_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_57\,
Q => \gen_multi_thread.accept_cnt_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_56\,
Q => \gen_multi_thread.accept_cnt_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8
port map (
E(0) => E(0),
Q(4 downto 0) => Q(4 downto 0),
SR(0) => SR(0),
S_AXI_ARREADY(0) => S_AXI_ARREADY(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
f_mux4_return(46 downto 14) => f_mux4_return(47 downto 15),
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.accept_cnt_reg__0\(3),
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ => \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\,
\m_payload_i_reg[0]\(0) => \m_payload_i_reg[0]\(0),
\m_payload_i_reg[0]_0\(0) => \m_payload_i_reg[0]_0\(0),
\m_payload_i_reg[0]_1\(0) => \m_payload_i_reg[0]_1\(0),
\m_payload_i_reg[0]_2\(0) => \m_payload_i_reg[0]_2\(0),
\m_payload_i_reg[34]\(0) => \m_payload_i_reg[34]\(0),
\m_payload_i_reg[34]_0\(0) => \m_payload_i_reg[34]_1\(0),
\m_payload_i_reg[34]_1\(0) => \m_payload_i_reg[34]_2\(0),
\m_payload_i_reg[34]_2\(0) => \m_payload_i_reg[34]_3\(0),
\m_payload_i_reg[34]_3\(0) => \m_payload_i_reg[34]_4\(0),
\m_payload_i_reg[34]_4\ => \gen_multi_thread.mux_resp_multi_thread_n_59\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
match => match,
p_102_out => p_102_out,
p_122_out => p_122_out,
p_40_out => p_40_out,
p_62_out => p_62_out,
p_82_out => p_82_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(0) => r_issuing_cnt(0),
resp_select(0) => resp_select(2),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rready(0) => s_axi_rready(0),
\s_axi_rvalid[0]\ => \^s_axi_rvalid[0]\,
st_mr_rid(47 downto 0) => st_mr_rid(47 downto 0),
st_mr_rmesg(135 downto 0) => st_mr_rmesg(135 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(0),
I1 => cmd_push_0,
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(2),
I3 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(1),
I1 => cmd_push_0,
I2 => active_cnt(0),
I3 => active_cnt(3),
I4 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\,
Q => active_cnt(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\,
Q => active_cnt(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\,
Q => active_cnt(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\,
Q => active_cnt(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E222"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => aid_match_00,
I3 => S_AXI_ARREADY(0),
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_1,
I1 => active_cnt(8),
I2 => active_cnt(10),
I3 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(9),
I1 => cmd_push_1,
I2 => active_cnt(8),
I3 => active_cnt(11),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(8),
I1 => cmd_push_1,
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\,
Q => active_cnt(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\,
Q => active_cnt(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\,
Q => active_cnt(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\,
Q => active_cnt(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => aid_match_10,
I4 => S_AXI_ARREADY(0),
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(16),
I1 => cmd_push_2,
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_2,
I1 => active_cnt(16),
I2 => active_cnt(18),
I3 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(17),
I1 => cmd_push_2,
I2 => active_cnt(16),
I3 => active_cnt(19),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\,
Q => active_cnt(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\,
Q => active_cnt(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\,
Q => active_cnt(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\,
Q => active_cnt(19),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80008000800080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => \thread_valid_2__2\,
I4 => aid_match_20,
I5 => S_AXI_ARREADY(0),
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
O => \thread_valid_0__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
O => \thread_valid_1__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
O => \thread_valid_2__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(24),
I1 => cmd_push_3,
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(26),
I3 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(25),
I1 => cmd_push_3,
I2 => active_cnt(24),
I3 => active_cnt(27),
I4 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\,
Q => active_cnt(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\,
Q => active_cnt(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\,
Q => active_cnt(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\,
Q => active_cnt(27),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I2 => \thread_valid_3__2\,
I3 => aid_match_30,
I4 => S_AXI_ARREADY(0),
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(32),
I1 => cmd_push_4,
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_4,
I1 => active_cnt(32),
I2 => active_cnt(34),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(33),
I1 => cmd_push_4,
I2 => active_cnt(32),
I3 => active_cnt(35),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\,
Q => active_cnt(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\,
Q => active_cnt(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\,
Q => active_cnt(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\,
Q => active_cnt(35),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
I1 => \thread_valid_3__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \thread_valid_4__2\,
I4 => aid_match_40,
I5 => S_AXI_ARREADY(0),
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555557FFFFFFFF"
)
port map (
I0 => \thread_valid_0__2\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
I5 => \thread_valid_2__2\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
O => \thread_valid_3__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
O => \thread_valid_4__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(40),
I1 => cmd_push_5,
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_5,
I1 => active_cnt(40),
I2 => active_cnt(42),
I3 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(41),
I1 => cmd_push_5,
I2 => active_cnt(40),
I3 => active_cnt(43),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\,
Q => active_cnt(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\,
Q => active_cnt(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\,
Q => active_cnt(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\,
Q => active_cnt(43),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I2 => \thread_valid_5__2\,
I3 => aid_match_50,
I4 => S_AXI_ARREADY(0),
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(48),
I1 => cmd_push_6,
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_6,
I1 => active_cnt(48),
I2 => active_cnt(50),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(49),
I1 => cmd_push_6,
I2 => active_cnt(48),
I3 => active_cnt(51),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\,
Q => active_cnt(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\,
Q => active_cnt(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\,
Q => active_cnt(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\,
Q => active_cnt(51),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \thread_valid_5__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \thread_valid_6__2\,
I4 => aid_match_60,
I5 => S_AXI_ARREADY(0),
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
O => \thread_valid_5__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(51),
I2 => active_cnt(49),
I3 => active_cnt(48),
O => \thread_valid_6__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(56),
I1 => cmd_push_7,
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_7,
I1 => active_cnt(56),
I2 => active_cnt(58),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(57),
I1 => cmd_push_7,
I2 => active_cnt(56),
I3 => active_cnt(59),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
O => \thread_valid_7__2\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\,
Q => active_cnt(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\,
Q => active_cnt(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\,
Q => active_cnt(58),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\,
Q => active_cnt(59),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_araddr[30]\(2),
I1 => \s_axi_araddr[30]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_araddr[30]\(2),
I1 => \s_axi_araddr[30]\(1),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \aid_match_7__0\,
I4 => S_AXI_ARREADY(0),
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55555557"
)
port map (
I0 => \thread_valid_3__2\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
O => \accum_push_5__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => \thread_valid_6__2\,
I5 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\,
I4 => \aid_match_6__0\,
I5 => \aid_match_7__0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
O => \aid_match_7__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_00,
I1 => \thread_valid_0__2\,
I2 => aid_match_10,
I3 => \thread_valid_1__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_20,
I1 => \thread_valid_2__2\,
I2 => aid_match_30,
I3 => \thread_valid_3__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_40,
I1 => \thread_valid_4__2\,
I2 => aid_match_50,
I3 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(48),
I1 => active_cnt(49),
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => aid_match_60,
O => \aid_match_6__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(58),
R => SR(0)
);
\gen_multi_thread.mux_resp_multi_thread\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc
port map (
CO(0) => p_14_out,
D(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
D(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
D(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\,
E(0) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg__0\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_60\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_61\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_62\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_63\,
S_AXI_ARREADY(0) => S_AXI_ARREADY(0),
\chosen_reg[0]\ => \^s_axi_rvalid[0]\,
cmd_push_0 => cmd_push_0,
cmd_push_1 => cmd_push_1,
cmd_push_2 => cmd_push_2,
cmd_push_3 => cmd_push_3,
cmd_push_4 => cmd_push_4,
cmd_push_5 => cmd_push_5,
cmd_push_6 => cmd_push_6,
cmd_push_7 => cmd_push_7,
f_mux4_return(46 downto 14) => f_mux4_return(47 downto 15),
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3) => \gen_multi_thread.mux_resp_multi_thread_n_88\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2) => \gen_multi_thread.mux_resp_multi_thread_n_89\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1) => \gen_multi_thread.mux_resp_multi_thread_n_90\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_91\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_84\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_85\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_86\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_87\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_80\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_81\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_82\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_83\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_76\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_77\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_78\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_79\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_72\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_73\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_74\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_75\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_68\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_69\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_70\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_71\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_64\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_65\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_66\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_67\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_multi_thread.mux_resp_multi_thread_n_59\,
\m_payload_i_reg[34]\(0) => \m_payload_i_reg[34]_0\(0),
resp_select(0) => resp_select(2),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => \s_axi_rid[0]\,
\s_axi_rid[10]\ => \s_axi_rid[10]\,
\s_axi_rid[11]\ => \s_axi_rid[11]\,
\s_axi_rid[1]\ => \s_axi_rid[1]\,
\s_axi_rid[2]\ => \s_axi_rid[2]\,
\s_axi_rid[3]\ => \s_axi_rid[3]\,
\s_axi_rid[4]\ => \s_axi_rid[4]\,
\s_axi_rid[5]\ => \s_axi_rid[5]\,
\s_axi_rid[6]\ => \s_axi_rid[6]\,
\s_axi_rid[7]\ => \s_axi_rid[7]\,
\s_axi_rid[8]\ => \s_axi_rid[8]\,
\s_axi_rid[9]\ => \s_axi_rid[9]\,
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
st_mr_rid(11 downto 0) => st_mr_rid(59 downto 48),
\thread_valid_0__2\ => \thread_valid_0__2\,
\thread_valid_1__2\ => \thread_valid_1__2\,
\thread_valid_2__2\ => \thread_valid_2__2\,
\thread_valid_3__2\ => \thread_valid_3__2\,
\thread_valid_4__2\ => \thread_valid_4__2\,
\thread_valid_5__2\ => \thread_valid_5__2\,
\thread_valid_6__2\ => \thread_valid_6__2\,
\thread_valid_7__2\ => \thread_valid_7__2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => match,
O => \^d\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
I4 => aid_match_30,
O => \aid_match_3__0\
);
\gen_no_arbiter.s_ready_i[0]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(17),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(18),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
I4 => aid_match_20,
O => \aid_match_2__0\
);
\gen_no_arbiter.s_ready_i[0]_i_14__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(9),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(10),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
I4 => aid_match_10,
O => \aid_match_1__0\
);
\gen_no_arbiter.s_ready_i[0]_i_17__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(1),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(2),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
I4 => aid_match_00,
O => \aid_match_0__0\
);
\gen_no_arbiter.s_ready_i[0]_i_20__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(49),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(50),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(57),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(58),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_27__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(41),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(42),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_29__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
I4 => aid_match_50,
O => \aid_match_5__0\
);
\gen_no_arbiter.s_ready_i[0]_i_30__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(33),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(34),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_31_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_32__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
O => \aid_match_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_33__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
I1 => \gen_multi_thread.accept_cnt_reg__0\(2),
I2 => \gen_multi_thread.accept_cnt_reg__0\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\,
I2 => \aid_match_3__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\,
I5 => \aid_match_2__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\,
I2 => \aid_match_1__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\,
I5 => \aid_match_0__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\,
I2 => \aid_match_6__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\,
I5 => \aid_match_7__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\,
I2 => \aid_match_5__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_31_n_0\,
I5 => \aid_match_4__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(25),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(26),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_60\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_61\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_62\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_63\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_80\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_81\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_82\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_83\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_84\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_85\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_86\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_87\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_88\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_89\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_90\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_91\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_64\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_65\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_66\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_67\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_68\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_69\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_70\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_71\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_72\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_73\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_74\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_75\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_76\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_77\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_78\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_79\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
port (
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].w_issuing_cnt_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\s_axi_bvalid[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 59 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
p_84_in : in STD_LOGIC;
p_66_in : in STD_LOGIC;
p_48_in : in STD_LOGIC;
p_101_in : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
match : in STD_LOGIC;
ADDRESS_HIT_0 : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
st_mr_bmesg : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_68_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_awid[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_14_si_transactor";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \accum_push_5__0\ : STD_LOGIC;
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 58 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal \aid_match_00_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal \aid_match_0__0\ : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal \aid_match_10_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal \aid_match_1__0\ : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal \aid_match_20_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal \aid_match_2__0\ : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal \aid_match_30_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal \aid_match_3__0\ : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal \aid_match_40_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal \aid_match_4__0\ : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal \aid_match_50_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal \aid_match_5__0\ : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal \aid_match_60_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal \aid_match_6__0\ : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal \aid_match_70_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal \aid_match_7__0\ : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal f_mux4_return : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_15\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_16\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_17\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_18\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_19\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_20\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_21\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_22\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_23\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_24\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_25\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_26\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_27\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_28\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_29\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_30\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_31\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_32\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_33\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_34\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_35\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_36\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_37\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_38\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_39\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_40\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_41\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_42\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_43\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_44\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_45\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_46\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_47\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_48\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_49\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_50\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_51\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_52\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_53\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_54\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_55\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_56\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_57\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_58\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_29_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_32_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_35_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal resp_select : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^s_axi_bvalid[0]\ : STD_LOGIC;
signal \thread_valid_0__2\ : STD_LOGIC;
signal \thread_valid_1__2\ : STD_LOGIC;
signal \thread_valid_2__2\ : STD_LOGIC;
signal \thread_valid_3__2\ : STD_LOGIC;
signal \thread_valid_4__2\ : STD_LOGIC;
signal \thread_valid_5__2\ : STD_LOGIC;
signal \thread_valid_6__2\ : STD_LOGIC;
signal \thread_valid_7__2\ : STD_LOGIC;
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair189";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_10\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_16\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_19\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_20\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_28__0\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_30\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_33\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_35\ : label is "soft_lutpair189";
begin
D(2 downto 0) <= \^d\(2 downto 0);
SR(0) <= \^sr\(0);
\s_axi_bvalid[0]\ <= \^s_axi_bvalid[0]\;
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_00_carry_i_1__0_n_0\,
S(2) => \aid_match_00_carry_i_2__0_n_0\,
S(1) => \aid_match_00_carry_i_3__0_n_0\,
S(0) => \aid_match_00_carry_i_4__0_n_0\
);
\aid_match_00_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
O => \aid_match_00_carry_i_1__0_n_0\
);
\aid_match_00_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8),
O => \aid_match_00_carry_i_2__0_n_0\
);
\aid_match_00_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
O => \aid_match_00_carry_i_3__0_n_0\
);
\aid_match_00_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
O => \aid_match_00_carry_i_4__0_n_0\
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_10_carry_i_1__0_n_0\,
S(2) => \aid_match_10_carry_i_2__0_n_0\,
S(1) => \aid_match_10_carry_i_3__0_n_0\,
S(0) => \aid_match_10_carry_i_4__0_n_0\
);
\aid_match_10_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \s_axi_awid[11]\(11),
O => \aid_match_10_carry_i_1__0_n_0\
);
\aid_match_10_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8),
I5 => \s_axi_awid[11]\(8),
O => \aid_match_10_carry_i_2__0_n_0\
);
\aid_match_10_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \s_axi_awid[11]\(5),
O => \aid_match_10_carry_i_3__0_n_0\
);
\aid_match_10_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I5 => \s_axi_awid[11]\(2),
O => \aid_match_10_carry_i_4__0_n_0\
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_20_carry_i_1__0_n_0\,
S(2) => \aid_match_20_carry_i_2__0_n_0\,
S(1) => \aid_match_20_carry_i_3__0_n_0\,
S(0) => \aid_match_20_carry_i_4__0_n_0\
);
\aid_match_20_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
O => \aid_match_20_carry_i_1__0_n_0\
);
\aid_match_20_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8),
O => \aid_match_20_carry_i_2__0_n_0\
);
\aid_match_20_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
O => \aid_match_20_carry_i_3__0_n_0\
);
\aid_match_20_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
O => \aid_match_20_carry_i_4__0_n_0\
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_30_carry_i_1__0_n_0\,
S(2) => \aid_match_30_carry_i_2__0_n_0\,
S(1) => \aid_match_30_carry_i_3__0_n_0\,
S(0) => \aid_match_30_carry_i_4__0_n_0\
);
\aid_match_30_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
O => \aid_match_30_carry_i_1__0_n_0\
);
\aid_match_30_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8),
O => \aid_match_30_carry_i_2__0_n_0\
);
\aid_match_30_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
O => \aid_match_30_carry_i_3__0_n_0\
);
\aid_match_30_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
O => \aid_match_30_carry_i_4__0_n_0\
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_40_carry_i_1__0_n_0\,
S(2) => \aid_match_40_carry_i_2__0_n_0\,
S(1) => \aid_match_40_carry_i_3__0_n_0\,
S(0) => \aid_match_40_carry_i_4__0_n_0\
);
\aid_match_40_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
O => \aid_match_40_carry_i_1__0_n_0\
);
\aid_match_40_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8),
O => \aid_match_40_carry_i_2__0_n_0\
);
\aid_match_40_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
O => \aid_match_40_carry_i_3__0_n_0\
);
\aid_match_40_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
O => \aid_match_40_carry_i_4__0_n_0\
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_50_carry_i_1__0_n_0\,
S(2) => \aid_match_50_carry_i_2__0_n_0\,
S(1) => \aid_match_50_carry_i_3__0_n_0\,
S(0) => \aid_match_50_carry_i_4__0_n_0\
);
\aid_match_50_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
O => \aid_match_50_carry_i_1__0_n_0\
);
\aid_match_50_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8),
O => \aid_match_50_carry_i_2__0_n_0\
);
\aid_match_50_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
O => \aid_match_50_carry_i_3__0_n_0\
);
\aid_match_50_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
O => \aid_match_50_carry_i_4__0_n_0\
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_60_carry_i_1__0_n_0\,
S(2) => \aid_match_60_carry_i_2__0_n_0\,
S(1) => \aid_match_60_carry_i_3__0_n_0\,
S(0) => \aid_match_60_carry_i_4__0_n_0\
);
\aid_match_60_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
O => \aid_match_60_carry_i_1__0_n_0\
);
\aid_match_60_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8),
O => \aid_match_60_carry_i_2__0_n_0\
);
\aid_match_60_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
O => \aid_match_60_carry_i_3__0_n_0\
);
\aid_match_60_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
O => \aid_match_60_carry_i_4__0_n_0\
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_70_carry_i_1__0_n_0\,
S(2) => \aid_match_70_carry_i_2__0_n_0\,
S(1) => \aid_match_70_carry_i_3__0_n_0\,
S(0) => \aid_match_70_carry_i_4__0_n_0\
);
\aid_match_70_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
O => \aid_match_70_carry_i_1__0_n_0\
);
\aid_match_70_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8),
O => \aid_match_70_carry_i_2__0_n_0\
);
\aid_match_70_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
O => \aid_match_70_carry_i_3__0_n_0\
);
\aid_match_70_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
O => \aid_match_70_carry_i_4__0_n_0\
);
\gen_multi_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\,
Q => \gen_multi_thread.accept_cnt_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_26\,
Q => \gen_multi_thread.accept_cnt_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_25\,
Q => \gen_multi_thread.accept_cnt_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_24\,
Q => \gen_multi_thread.accept_cnt_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp
port map (
ADDRESS_HIT_0 => ADDRESS_HIT_0,
E(0) => E(0),
Q(0) => \gen_multi_thread.accept_cnt_reg\(3),
SR(0) => \^sr\(0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0),
\gen_master_slots[2].w_issuing_cnt_reg[16]\(0) => \gen_master_slots[2].w_issuing_cnt_reg[16]\(0),
\gen_master_slots[3].w_issuing_cnt_reg[24]\(0) => \gen_master_slots[3].w_issuing_cnt_reg[24]\(0),
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_35_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]\(0) => \gen_no_arbiter.s_ready_i_reg[0]\(0),
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_no_arbiter.s_ready_i_reg[0]_0\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
match => match,
p_0_out => p_0_out_0,
p_101_in => p_101_in,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_68_out => p_68_out,
p_84_in => p_84_in,
p_88_out => p_88_out,
resp_select(0) => resp_select(2),
\s_axi_awaddr[30]\(2 downto 0) => \s_axi_awaddr[30]\(2 downto 0),
s_axi_bready(0) => s_axi_bready(0),
\s_axi_bvalid[0]\ => \^s_axi_bvalid[0]\,
s_ready_i_reg(4 downto 0) => Q(4 downto 0),
st_mr_bid(47 downto 0) => st_mr_bid(47 downto 0),
st_mr_bmesg(7 downto 0) => st_mr_bmesg(7 downto 0),
w_issuing_cnt(16 downto 0) => w_issuing_cnt(16 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(0),
I1 => cmd_push_0,
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(2),
I3 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(1),
I1 => cmd_push_0,
I2 => active_cnt(0),
I3 => active_cnt(3),
I4 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\,
Q => active_cnt(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\,
Q => active_cnt(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\,
Q => active_cnt(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\,
Q => active_cnt(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E222"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => aid_match_00,
I3 => \m_ready_d_reg[1]\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(1),
Q => active_target(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(2),
Q => active_target(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_1,
I1 => active_cnt(8),
I2 => active_cnt(10),
I3 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(9),
I1 => cmd_push_1,
I2 => active_cnt(8),
I3 => active_cnt(11),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(8),
I1 => cmd_push_1,
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\,
Q => active_cnt(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\,
Q => active_cnt(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\,
Q => active_cnt(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\,
Q => active_cnt(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => aid_match_10,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(2),
Q => active_target(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(1),
Q => active_target(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(16),
I1 => cmd_push_2,
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_2,
I1 => active_cnt(16),
I2 => active_cnt(18),
I3 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(17),
I1 => cmd_push_2,
I2 => active_cnt(16),
I3 => active_cnt(19),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\,
Q => active_cnt(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\,
Q => active_cnt(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\,
Q => active_cnt(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\,
Q => active_cnt(19),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80008000800080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => \thread_valid_2__2\,
I4 => aid_match_20,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
O => \thread_valid_0__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
O => \thread_valid_1__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
O => \thread_valid_2__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(1),
Q => active_target(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(2),
Q => active_target(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(24),
I1 => cmd_push_3,
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(26),
I3 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(25),
I1 => cmd_push_3,
I2 => active_cnt(24),
I3 => active_cnt(27),
I4 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\,
Q => active_cnt(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\,
Q => active_cnt(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\,
Q => active_cnt(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\,
Q => active_cnt(27),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I2 => \thread_valid_3__2\,
I3 => aid_match_30,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(1),
Q => active_target(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(2),
Q => active_target(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(32),
I1 => cmd_push_4,
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_4,
I1 => active_cnt(32),
I2 => active_cnt(34),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(33),
I1 => cmd_push_4,
I2 => active_cnt(32),
I3 => active_cnt(35),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\,
Q => active_cnt(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\,
Q => active_cnt(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\,
Q => active_cnt(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\,
Q => active_cnt(35),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
I1 => \thread_valid_3__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \thread_valid_4__2\,
I4 => aid_match_40,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555557FFFFFFFF"
)
port map (
I0 => \thread_valid_0__2\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
I5 => \thread_valid_2__2\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
O => \thread_valid_3__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
O => \thread_valid_4__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(1),
Q => active_target(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(2),
Q => active_target(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(40),
I1 => cmd_push_5,
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_5,
I1 => active_cnt(40),
I2 => active_cnt(42),
I3 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(41),
I1 => cmd_push_5,
I2 => active_cnt(40),
I3 => active_cnt(43),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\,
Q => active_cnt(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\,
Q => active_cnt(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\,
Q => active_cnt(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\,
Q => active_cnt(43),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I2 => \thread_valid_5__2\,
I3 => aid_match_50,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(1),
Q => active_target(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(2),
Q => active_target(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(48),
I1 => cmd_push_6,
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_6,
I1 => active_cnt(48),
I2 => active_cnt(50),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(49),
I1 => cmd_push_6,
I2 => active_cnt(48),
I3 => active_cnt(51),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\,
Q => active_cnt(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\,
Q => active_cnt(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\,
Q => active_cnt(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\,
Q => active_cnt(51),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \thread_valid_5__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \thread_valid_6__2\,
I4 => aid_match_60,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
O => \thread_valid_5__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(51),
I2 => active_cnt(49),
I3 => active_cnt(48),
O => \thread_valid_6__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(1),
Q => active_target(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(2),
Q => active_target(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(56),
I1 => cmd_push_7,
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_7,
I1 => active_cnt(56),
I2 => active_cnt(58),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(57),
I1 => cmd_push_7,
I2 => active_cnt(56),
I3 => active_cnt(59),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
O => \thread_valid_7__2\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\,
Q => active_cnt(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\,
Q => active_cnt(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\,
Q => active_cnt(58),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\,
Q => active_cnt(59),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_awaddr[30]\(2),
I1 => \s_axi_awaddr[30]\(0),
O => \^d\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_awaddr[30]\(2),
I1 => \s_axi_awaddr[30]\(1),
O => \^d\(1)
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \aid_match_7__0\,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55555557"
)
port map (
I0 => \thread_valid_3__2\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
O => \accum_push_5__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => \thread_valid_6__2\,
I5 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\,
I4 => \aid_match_6__0\,
I5 => \aid_match_7__0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
O => \aid_match_7__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_00,
I1 => \thread_valid_0__2\,
I2 => aid_match_10,
I3 => \thread_valid_1__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_20,
I1 => \thread_valid_2__2\,
I2 => aid_match_30,
I3 => \thread_valid_3__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_40,
I1 => \thread_valid_4__2\,
I2 => aid_match_50,
I3 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(48),
I1 => active_cnt(49),
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => aid_match_60,
O => \aid_match_6__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(1),
Q => active_target(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(2),
Q => active_target(58),
R => \^sr\(0)
);
\gen_multi_thread.mux_resp_multi_thread\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\
port map (
CO(0) => p_14_out,
D(2) => \gen_multi_thread.mux_resp_multi_thread_n_24\,
D(1) => \gen_multi_thread.mux_resp_multi_thread_n_25\,
D(0) => \gen_multi_thread.mux_resp_multi_thread_n_26\,
E(0) => \gen_multi_thread.mux_resp_multi_thread_n_15\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_27\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_28\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_29\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_30\,
cmd_push_0 => cmd_push_0,
cmd_push_1 => cmd_push_1,
cmd_push_2 => cmd_push_2,
cmd_push_3 => cmd_push_3,
cmd_push_4 => cmd_push_4,
cmd_push_5 => cmd_push_5,
cmd_push_6 => cmd_push_6,
cmd_push_7 => cmd_push_7,
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_23\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_22\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_21\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_16\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_43\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_44\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_45\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_46\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_17\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_39\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_40\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_41\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_42\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_20\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_35\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_36\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_37\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_38\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_19\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_31\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_32\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_33\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_34\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_18\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11 downto 0),
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
m_valid_i_reg => \^s_axi_bvalid[0]\,
p_0_out => p_0_out_0,
resp_select(0) => resp_select(2),
\s_axi_bid[0]\ => \s_axi_bid[0]\,
\s_axi_bid[10]\ => \s_axi_bid[10]\,
\s_axi_bid[11]\ => \s_axi_bid[11]\,
\s_axi_bid[1]\ => \s_axi_bid[1]\,
\s_axi_bid[2]\ => \s_axi_bid[2]\,
\s_axi_bid[3]\ => \s_axi_bid[3]\,
\s_axi_bid[4]\ => \s_axi_bid[4]\,
\s_axi_bid[5]\ => \s_axi_bid[5]\,
\s_axi_bid[6]\ => \s_axi_bid[6]\,
\s_axi_bid[7]\ => \s_axi_bid[7]\,
\s_axi_bid[8]\ => \s_axi_bid[8]\,
\s_axi_bid[9]\ => \s_axi_bid[9]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
st_mr_bid(11 downto 0) => st_mr_bid(59 downto 48),
\thread_valid_0__2\ => \thread_valid_0__2\,
\thread_valid_1__2\ => \thread_valid_1__2\,
\thread_valid_2__2\ => \thread_valid_2__2\,
\thread_valid_3__2\ => \thread_valid_3__2\,
\thread_valid_4__2\ => \thread_valid_4__2\,
\thread_valid_5__2\ => \thread_valid_5__2\,
\thread_valid_6__2\ => \thread_valid_6__2\,
\thread_valid_7__2\ => \thread_valid_7__2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => match,
O => \^d\(2)
);
\gen_no_arbiter.s_ready_i[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
I4 => aid_match_30,
O => \aid_match_3__0\
);
\gen_no_arbiter.s_ready_i[0]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(17),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(18),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
I4 => aid_match_20,
O => \aid_match_2__0\
);
\gen_no_arbiter.s_ready_i[0]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(9),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(10),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
I4 => aid_match_10,
O => \aid_match_1__0\
);
\gen_no_arbiter.s_ready_i[0]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(1),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(2),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
I4 => aid_match_00,
O => \aid_match_0__0\
);
\gen_no_arbiter.s_ready_i[0]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(49),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(50),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(57),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(58),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(41),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_29\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(42),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_29_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\,
I2 => \aid_match_3__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\,
I5 => \aid_match_2__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_30\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
I4 => aid_match_50,
O => \aid_match_5__0\
);
\gen_no_arbiter.s_ready_i[0]_i_31__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(33),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(34),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_32_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
O => \aid_match_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
I1 => \gen_multi_thread.accept_cnt_reg\(2),
I2 => \gen_multi_thread.accept_cnt_reg\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_35_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\,
I2 => \aid_match_1__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\,
I5 => \aid_match_0__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\,
I2 => \aid_match_6__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\,
I5 => \aid_match_7__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_29_n_0\,
I2 => \aid_match_5__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_32_n_0\,
I5 => \aid_match_4__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(25),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(26),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_27\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_28\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_29\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_30\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_31\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_32\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_33\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_34\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_35\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_36\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_37\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_38\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_39\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_40\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_41\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_42\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_43\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_44\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_45\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_46\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\write_cs0__0\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
match : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
signal \/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal areset_d1 : STD_LOGIC;
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[2].srl_nx1_n_1\ : STD_LOGIC;
signal load_s1 : STD_LOGIC;
signal \m_aready0__3\ : STD_LOGIC;
signal \m_aready__1\ : STD_LOGIC;
signal m_avalid : STD_LOGIC;
signal m_select_enc : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_valid_i__0\ : STD_LOGIC;
signal m_valid_i_n_0 : STD_LOGIC;
signal p_0_in5_out : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal \s_ready_i1__4\ : STD_LOGIC;
signal \s_ready_i_i_1__9_n_0\ : STD_LOGIC;
signal \^ss_wr_awready\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \m_axi_wvalid[2]_INST_0\ : label is "soft_lutpair192";
attribute SOFT_HLUTNM of \m_axi_wvalid[3]_INST_0\ : label is "soft_lutpair192";
begin
ss_wr_awready <= \^ss_wr_awready\;
\/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20202F20"
)
port map (
I0 => s_axi_awvalid(0),
I1 => m_ready_d(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[1]_i_1_n_0\
);
\/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0B0B0BF"
)
port map (
I0 => m_ready_d(0),
I1 => s_axi_awvalid(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"008A0000"
)
port map (
I0 => \m_aready__1\,
I1 => m_ready_d(0),
I2 => s_axi_awvalid(0),
I3 => p_9_in,
I4 => p_0_in8_in,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF488F488F488"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => \m_valid_i__0\
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00007500"
)
port map (
I0 => \m_aready__1\,
I1 => m_ready_d(0),
I2 => s_axi_awvalid(0),
I3 => p_0_in8_in,
I4 => p_9_in,
O => \FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => areset_d1
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \/FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => areset_d1
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \/FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => areset_d1
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => areset_d1
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => SR(0),
Q => areset_d1,
R => '0'
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000800000"
)
port map (
I0 => s_axi_wlast(0),
I1 => m_avalid,
I2 => s_axi_wvalid(0),
I3 => m_select_enc(0),
I4 => m_select_enc(2),
I5 => m_select_enc(1),
O => \write_cs0__0\
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => push,
I3 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FF77008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(0),
I3 => push,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8FFFFFF770000008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(0),
I3 => fifoaddr(1),
I4 => push,
I5 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\
port map (
D(0) => D(0),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
m_select_enc(0) => m_select_enc(0),
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
\s_axi_awaddr[30]\(1) => \s_axi_awaddr[30]\(2),
\s_axi_awaddr[30]\(0) => \s_axi_awaddr[30]\(0),
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[1].srl_nx1\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\
port map (
D(0) => D(1),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
m_select_enc(0) => m_select_enc(1),
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
\s_axi_awaddr[30]\(1 downto 0) => \s_axi_awaddr[30]\(2 downto 1),
\storage_data1_reg[1]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[2].srl_nx1\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\
port map (
D(0) => D(2),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
\m_aready0__3\ => \m_aready0__3\,
\m_aready__1\ => \m_aready__1\,
m_avalid => m_avalid,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_ready_d(0) => m_ready_d(0),
m_select_enc(2 downto 0) => m_select_enc(2 downto 0),
match => match,
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
p_22_in => p_22_in,
push => push,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => \^ss_wr_awready\,
\storage_data1_reg[2]\ => \gen_srls[0].gen_rep[2].srl_nx1_n_1\
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(2)
);
\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(3)
);
m_valid_i: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF400F400F400"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i_n_0
);
m_valid_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(1),
I3 => fifoaddr(0),
I4 => fifoaddr(2),
I5 => push,
O => p_0_in5_out
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => m_valid_i_n_0,
Q => m_avalid,
R => areset_d1
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => m_avalid,
I1 => \m_aready0__3\,
O => s_axi_wready(0)
);
\s_ready_i_i_1__9\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0FFF0F8"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => areset_d1,
I3 => \s_ready_i1__4\,
I4 => \^ss_wr_awready\,
O => \s_ready_i_i_1__9_n_0\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000700000000000"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(2),
I3 => fifoaddr(1),
I4 => fifoaddr(0),
I5 => push,
O => \s_ready_i1__4\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__9_n_0\,
Q => \^ss_wr_awready\,
R => SR(0)
);
\storage_data1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0FCA0A0A0ECA0A0"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => p_9_in,
I2 => \m_aready__1\,
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => p_0_in8_in,
O => load_s1
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
Q => m_select_enc(0),
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[1].srl_nx1_n_0\,
Q => m_select_enc(1),
R => '0'
);
\storage_data1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[2].srl_nx1_n_1\,
Q => m_select_enc(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
port (
p_128_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_0__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\chosen_reg[2]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : in STD_LOGIC;
p_102_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
begin
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\chosen_reg[2]\ => \chosen_reg[2]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_128_out,
p_108_out => p_108_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[0]\(0) => \chosen_reg[0]\(0),
\chosen_reg[0]_0\(0) => \chosen_reg[0]_0\(0),
\chosen_reg[2]\ => \chosen_reg[2]\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_122_out,
p_102_out => p_102_out,
p_1_in => p_1_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 is
port (
p_108_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_102_out : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_1__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_75_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\m_axi_bid[23]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 is
begin
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\
port map (
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
\m_axi_bid[23]\(13 downto 0) => \m_axi_bid[23]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_108_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\
port map (
ADDRESS_HIT_0 => ADDRESS_HIT_0,
D(0) => D(0),
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[1]\(0) => \chosen_reg[1]\(0),
\chosen_reg[1]_0\(0) => \chosen_reg[1]_0\(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0) => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[1]\ => \m_axi_rready[1]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_102_out,
p_1_in => p_1_in,
p_75_in => p_75_in,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 is
port (
p_88_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_82_out : out STD_LOGIC;
\m_axi_rready[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_2__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_57_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[24]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_axi_bid[35]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 is
begin
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\
port map (
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
\m_axi_bid[35]\(13 downto 0) => \m_axi_bid[35]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_88_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\
port map (
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[2]\(0) => \chosen_reg[2]\(0),
\chosen_reg[2]_0\(0) => \chosen_reg[2]_0\(0),
\gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0) => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0),
\gen_master_slots[3].r_issuing_cnt_reg[24]\ => \gen_master_slots[3].r_issuing_cnt_reg[24]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[2]\ => \m_axi_rready[2]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_82_out,
p_1_in => p_1_in,
p_57_in => p_57_in,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3 is
port (
p_68_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
p_62_out : out STD_LOGIC;
\m_axi_rready[3]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_3__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[4]\ : out STD_LOGIC;
\chosen_reg[4]_0\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_39_in : in STD_LOGIC;
p_82_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3 is
signal \^p_1_in\ : STD_LOGIC;
begin
p_1_in <= \^p_1_in\;
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\aresetn_d_reg[1]_1\ => \aresetn_d_reg[1]_1\,
\chosen_reg[4]\ => \chosen_reg[4]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_68_out,
p_1_in => \^p_1_in\,
p_88_out => p_88_out,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]_0\,
\chosen_reg[3]\(0) => \chosen_reg[3]\(0),
\chosen_reg[3]_0\(0) => \chosen_reg[3]_0\(0),
\chosen_reg[4]\ => \chosen_reg[4]\,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0) => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[3]\ => \m_axi_rready[3]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_62_out,
p_1_in => \^p_1_in\,
p_39_in => p_39_in,
p_82_out => p_82_out,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4 is
port (
p_46_out : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
mi_bready_4 : out STD_LOGIC;
p_40_out : out STD_LOGIC;
mi_rready_4 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
\r_cmd_pop_4__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_29_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_23_in : in STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_25_in : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4 is
signal \^m_valid_i_reg\ : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
D(11 downto 0) => D(11 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(11 downto 0),
\m_payload_i_reg[2]_0\ => p_46_out,
m_valid_i_reg_0 => \^m_valid_i_reg\,
mi_bready_4 => mi_bready_4,
p_1_in => p_1_in,
p_29_in => p_29_in,
s_axi_bready(0) => s_axi_bready(0),
s_ready_i_reg_0 => s_ready_i_reg
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \^m_valid_i_reg\,
\chosen_reg[4]\(0) => \chosen_reg[4]\(0),
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0),
m_valid_i_reg_0 => p_40_out,
p_1_in => p_1_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
s_axi_rready(0) => s_axi_rready(0),
\skid_buffer_reg[34]_0\ => mi_rready_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\write_cs0__0\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
match : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router is
begin
wrouter_aw_fifo: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
port map (
D(2 downto 0) => D(2 downto 0),
SR(0) => SR(0),
aclk => aclk,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(0) => m_ready_d(0),
match => match,
p_22_in => p_22_in,
\s_axi_awaddr[30]\(2 downto 0) => \s_axi_awaddr[30]\(2 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
\write_cs0__0\ => \write_cs0__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar is
port (
M_AXI_RREADY : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
\m_axi_arqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_axi_awready[0]\ : out STD_LOGIC;
\s_axi_bvalid[0]\ : out STD_LOGIC;
\s_axi_rvalid[0]\ : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 68 downto 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
aresetn : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar is
signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 4 to 4 );
signal aa_mi_arvalid : STD_LOGIC;
signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal aa_sa_awvalid : STD_LOGIC;
signal addr_arbiter_ar_n_79 : STD_LOGIC;
signal addr_arbiter_ar_n_80 : STD_LOGIC;
signal addr_arbiter_ar_n_81 : STD_LOGIC;
signal addr_arbiter_ar_n_82 : STD_LOGIC;
signal addr_arbiter_ar_n_83 : STD_LOGIC;
signal addr_arbiter_ar_n_84 : STD_LOGIC;
signal addr_arbiter_ar_n_85 : STD_LOGIC;
signal addr_arbiter_ar_n_86 : STD_LOGIC;
signal addr_arbiter_ar_n_87 : STD_LOGIC;
signal addr_arbiter_ar_n_88 : STD_LOGIC;
signal addr_arbiter_ar_n_89 : STD_LOGIC;
signal addr_arbiter_ar_n_90 : STD_LOGIC;
signal addr_arbiter_ar_n_99 : STD_LOGIC;
signal addr_arbiter_aw_n_23 : STD_LOGIC;
signal addr_arbiter_aw_n_25 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_54\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_55\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_53\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_53\ : STD_LOGIC;
signal \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_55\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_56\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_57\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_7\ : STD_LOGIC;
signal \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[4].reg_slice_mi_n_1\ : STD_LOGIC;
signal \gen_master_slots[4].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst/chosen\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst/chosen_9\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\ : STD_LOGIC;
signal \^m_axi_arqos[15]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_12 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_valid_i : STD_LOGIC;
signal m_valid_i_10 : STD_LOGIC;
signal match : STD_LOGIC;
signal match_3 : STD_LOGIC;
signal mi_arready_4 : STD_LOGIC;
signal mi_awready_4 : STD_LOGIC;
signal \mi_awready_mux__3\ : STD_LOGIC;
signal mi_bready_4 : STD_LOGIC;
signal mi_rready_4 : STD_LOGIC;
signal p_101_in : STD_LOGIC;
signal p_102_out : STD_LOGIC;
signal p_104_out : STD_LOGIC;
signal p_108_out : STD_LOGIC;
signal p_122_out : STD_LOGIC;
signal p_124_out : STD_LOGIC;
signal p_128_out : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_22_in : STD_LOGIC;
signal p_23_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_28_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_29_in : STD_LOGIC;
signal p_32_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_39_in : STD_LOGIC;
signal p_40_out : STD_LOGIC;
signal p_42_out : STD_LOGIC;
signal p_46_out : STD_LOGIC;
signal p_48_in : STD_LOGIC;
signal p_57_in : STD_LOGIC;
signal p_62_out : STD_LOGIC;
signal p_64_out : STD_LOGIC;
signal p_66_in : STD_LOGIC;
signal p_68_out : STD_LOGIC;
signal p_75_in : STD_LOGIC;
signal p_82_out : STD_LOGIC;
signal p_84_in : STD_LOGIC;
signal p_84_out : STD_LOGIC;
signal p_88_out : STD_LOGIC;
signal p_93_in : STD_LOGIC;
signal \r_cmd_pop_0__1\ : STD_LOGIC;
signal \r_cmd_pop_1__1\ : STD_LOGIC;
signal \r_cmd_pop_2__1\ : STD_LOGIC;
signal \r_cmd_pop_3__1\ : STD_LOGIC;
signal \r_cmd_pop_4__1\ : STD_LOGIC;
signal r_issuing_cnt : STD_LOGIC_VECTOR ( 32 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal \r_pipe/p_1_in_5\ : STD_LOGIC;
signal \r_pipe/p_1_in_6\ : STD_LOGIC;
signal \r_pipe/p_1_in_7\ : STD_LOGIC;
signal \r_pipe/p_1_in_8\ : STD_LOGIC;
signal \read_cs__0\ : STD_LOGIC;
signal reset : STD_LOGIC;
signal \^s_axi_awready[0]\ : STD_LOGIC;
signal s_axi_rlast_i0 : STD_LOGIC;
signal s_axi_rvalid_i : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal s_ready_i0_11 : STD_LOGIC;
signal \s_ready_i0__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \sa_wm_awready_mux__3\ : STD_LOGIC;
signal splitter_aw_mi_n_0 : STD_LOGIC;
signal splitter_aw_mi_n_1 : STD_LOGIC;
signal splitter_aw_mi_n_10 : STD_LOGIC;
signal splitter_aw_mi_n_11 : STD_LOGIC;
signal splitter_aw_mi_n_12 : STD_LOGIC;
signal splitter_aw_mi_n_2 : STD_LOGIC;
signal splitter_aw_mi_n_3 : STD_LOGIC;
signal splitter_aw_mi_n_4 : STD_LOGIC;
signal splitter_aw_mi_n_5 : STD_LOGIC;
signal splitter_aw_mi_n_6 : STD_LOGIC;
signal splitter_aw_mi_n_7 : STD_LOGIC;
signal splitter_aw_mi_n_8 : STD_LOGIC;
signal splitter_aw_mi_n_9 : STD_LOGIC;
signal ss_aa_awready : STD_LOGIC;
signal ss_wr_awready : STD_LOGIC;
signal ss_wr_awvalid : STD_LOGIC;
signal st_aa_awtarget_enc : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_bid : STD_LOGIC_VECTOR ( 59 downto 0 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 10 downto 0 );
signal st_mr_rid : STD_LOGIC_VECTOR ( 59 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 139 downto 0 );
signal w_issuing_cnt : STD_LOGIC_VECTOR ( 32 downto 0 );
signal write_cs01_out : STD_LOGIC;
signal \write_cs0__0\ : STD_LOGIC;
begin
Q(68 downto 0) <= \^q\(68 downto 0);
S_AXI_ARREADY(0) <= \^s_axi_arready\(0);
\m_axi_arqos[15]\(68 downto 0) <= \^m_axi_arqos[15]\(68 downto 0);
\s_axi_awready[0]\ <= \^s_axi_awready[0]\;
addr_arbiter_ar: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
E(0) => s_ready_i0,
Q(0) => aa_mi_artarget_hot(4),
SR(0) => reset,
S_AXI_ARREADY(0) => \^s_axi_arready\(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
\gen_axi.s_axi_rid_i_reg[11]\(0) => s_axi_rvalid_i,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(2) => addr_arbiter_ar_n_79,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(1) => addr_arbiter_ar_n_80,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(0) => addr_arbiter_ar_n_81,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(2) => addr_arbiter_ar_n_82,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(1) => addr_arbiter_ar_n_83,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(0) => addr_arbiter_ar_n_84,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(2) => addr_arbiter_ar_n_88,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(1) => addr_arbiter_ar_n_89,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(0) => addr_arbiter_ar_n_90,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(2) => addr_arbiter_ar_n_85,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(1) => addr_arbiter_ar_n_86,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(0) => addr_arbiter_ar_n_87,
\gen_master_slots[4].r_issuing_cnt_reg[32]\ => addr_arbiter_ar_n_99,
\m_axi_arqos[15]\(68 downto 0) => \^m_axi_arqos[15]\(68 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_valid_i => m_valid_i,
match => match,
mi_arready_4 => mi_arready_4,
p_23_in => p_23_in,
p_39_in => p_39_in,
p_57_in => p_57_in,
p_75_in => p_75_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(16) => r_issuing_cnt(32),
r_issuing_cnt(15 downto 12) => r_issuing_cnt(27 downto 24),
r_issuing_cnt(11 downto 8) => r_issuing_cnt(19 downto 16),
r_issuing_cnt(7 downto 4) => r_issuing_cnt(11 downto 8),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0),
\read_cs__0\ => \read_cs__0\,
\s_axi_araddr[24]\(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\,
\s_axi_arqos[3]\(68 downto 0) => \s_axi_arqos[3]\(68 downto 0),
s_axi_rlast_i0 => s_axi_rlast_i0
);
addr_arbiter_aw: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\,
D(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
E(0) => s_ready_i0_11,
Q(4 downto 0) => aa_mi_awtarget_hot(4 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
\chosen_reg[4]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4),
\gen_master_slots[4].w_issuing_cnt_reg[32]\ => addr_arbiter_aw_n_25,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_23,
\m_axi_awqos[15]\(68 downto 0) => \^q\(68 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d_12(1 downto 0),
m_ready_d_0(0) => m_ready_d(0),
m_valid_i => m_valid_i_10,
match => match_3,
mi_awready_4 => mi_awready_4,
\mi_awready_mux__3\ => \mi_awready_mux__3\,
p_101_in => p_101_in,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_84_in => p_84_in,
\s_axi_awaddr[24]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
\s_axi_awqos[3]\(68 downto 0) => D(68 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
\s_ready_i0__1\(0) => \s_ready_i0__1\(0),
\sa_wm_awready_mux__3\ => \sa_wm_awready_mux__3\,
ss_aa_awready => ss_aa_awready,
w_issuing_cnt(0) => w_issuing_cnt(32),
write_cs01_out => write_cs01_out
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr_slave.decerr_slave_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave
port map (
E(0) => s_axi_rvalid_i,
Q(0) => aa_mi_awtarget_hot(4),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_no_arbiter.m_mesg_i_reg[11]\(11 downto 0) => \^q\(11 downto 0),
\gen_no_arbiter.m_mesg_i_reg[51]\(19 downto 12) => \^m_axi_arqos[15]\(51 downto 44),
\gen_no_arbiter.m_mesg_i_reg[51]\(11 downto 0) => \^m_axi_arqos[15]\(11 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[4]\(0) => aa_mi_artarget_hot(4),
\m_payload_i_reg[13]\(11 downto 0) => p_32_in(11 downto 0),
m_ready_d(0) => m_ready_d_12(1),
\m_ready_d_reg[1]\ => splitter_aw_mi_n_3,
mi_arready_4 => mi_arready_4,
mi_awready_4 => mi_awready_4,
mi_bready_4 => mi_bready_4,
mi_rready_4 => mi_rready_4,
p_22_in => p_22_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
p_29_in => p_29_in,
\read_cs__0\ => \read_cs__0\,
s_axi_rlast_i0 => s_axi_rlast_i0,
\skid_buffer_reg[46]\(11 downto 0) => p_28_in(11 downto 0),
write_cs01_out => write_cs01_out,
\write_cs0__0\ => \write_cs0__0\
);
\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(0),
O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\,
Q => r_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_81,
Q => r_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_80,
Q => r_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_79,
Q => r_issuing_cnt(3),
R => reset
);
\gen_master_slots[0].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
port map (
D(13 downto 2) => m_axi_bid(11 downto 0),
D(1 downto 0) => m_axi_bresp(1 downto 0),
E(0) => \gen_master_slots[0].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[0]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(0),
\chosen_reg[0]_0\(0) => \r_pipe/p_1_in_8\,
\chosen_reg[2]\ => \gen_master_slots[0].reg_slice_mi_n_54\,
\chosen_reg[2]_0\ => \gen_master_slots[0].reg_slice_mi_n_55\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => r_issuing_cnt(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_124_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(34 downto 3),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(1 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_6\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => M_AXI_RREADY(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
p_102_out => p_102_out,
p_108_out => p_108_out,
p_122_out => p_122_out,
p_128_out => p_128_out,
p_1_in => p_1_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(0),
O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\,
Q => w_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_12,
Q => w_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_11,
Q => w_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_10,
Q => w_issuing_cnt(3),
R => reset
);
\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(8),
O => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].r_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_83,
Q => r_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_82,
Q => r_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\,
Q => r_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_84,
Q => r_issuing_cnt(9),
R => reset
);
\gen_master_slots[1].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
E(0) => \gen_master_slots[1].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(1),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[1]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(1),
\chosen_reg[1]_0\(0) => \r_pipe/p_1_in_7\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_6\,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0) => r_issuing_cnt(11 downto 8),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_104_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(36 downto 35),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(69 downto 38),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(4 downto 3),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_53\,
\m_axi_bid[23]\(13 downto 2) => m_axi_bid(23 downto 12),
\m_axi_bid[23]\(1 downto 0) => m_axi_bresp(3 downto 2),
m_axi_bready(0) => m_axi_bready(1),
m_axi_bvalid(0) => m_axi_bvalid(1),
m_axi_rdata(31 downto 0) => m_axi_rdata(63 downto 32),
m_axi_rid(11 downto 0) => m_axi_rid(23 downto 12),
m_axi_rlast(0) => m_axi_rlast(1),
\m_axi_rready[1]\ => M_AXI_RREADY(1),
m_axi_rresp(1 downto 0) => m_axi_rresp(3 downto 2),
m_axi_rvalid(0) => m_axi_rvalid(1),
p_102_out => p_102_out,
p_108_out => p_108_out,
p_1_in => p_1_in,
p_75_in => p_75_in,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(8),
O => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].w_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_1,
Q => w_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_0,
Q => w_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\,
Q => w_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_2,
Q => w_issuing_cnt(9),
R => reset
);
\gen_master_slots[2].r_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(16),
O => \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\
);
\gen_master_slots[2].r_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\,
Q => r_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_90,
Q => r_issuing_cnt(17),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_89,
Q => r_issuing_cnt(18),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_88,
Q => r_issuing_cnt(19),
R => reset
);
\gen_master_slots[2].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2
port map (
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
E(0) => \gen_master_slots[2].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(2),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2),
\chosen_reg[2]_0\(0) => \r_pipe/p_1_in\,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0) => r_issuing_cnt(19 downto 16),
\gen_master_slots[3].r_issuing_cnt_reg[24]\ => \gen_master_slots[3].reg_slice_mi_n_7\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_84_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(71 downto 70),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(104 downto 73),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(7 downto 6),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[2].reg_slice_mi_n_53\,
\m_axi_bid[35]\(13 downto 2) => m_axi_bid(35 downto 24),
\m_axi_bid[35]\(1 downto 0) => m_axi_bresp(5 downto 4),
m_axi_bready(0) => m_axi_bready(2),
m_axi_bvalid(0) => m_axi_bvalid(2),
m_axi_rdata(31 downto 0) => m_axi_rdata(95 downto 64),
m_axi_rid(11 downto 0) => m_axi_rid(35 downto 24),
m_axi_rlast(0) => m_axi_rlast(2),
\m_axi_rready[2]\ => M_AXI_RREADY(2),
m_axi_rresp(1 downto 0) => m_axi_rresp(5 downto 4),
m_axi_rvalid(0) => m_axi_rvalid(2),
p_1_in => p_1_in,
p_57_in => p_57_in,
p_82_out => p_82_out,
p_88_out => p_88_out,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[2].w_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(16),
O => \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\
);
\gen_master_slots[2].w_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\,
Q => w_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_6,
Q => w_issuing_cnt(17),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_5,
Q => w_issuing_cnt(18),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_4,
Q => w_issuing_cnt(19),
R => reset
);
\gen_master_slots[3].r_issuing_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(24),
O => \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\
);
\gen_master_slots[3].r_issuing_cnt_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\,
Q => r_issuing_cnt(24),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_87,
Q => r_issuing_cnt(25),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_86,
Q => r_issuing_cnt(26),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_85,
Q => r_issuing_cnt(27),
R => reset
);
\gen_master_slots[3].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3
port map (
D(13 downto 2) => m_axi_bid(47 downto 36),
D(1 downto 0) => m_axi_bresp(7 downto 6),
E(0) => \gen_master_slots[3].reg_slice_mi_n_5\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(3),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \gen_master_slots[3].reg_slice_mi_n_57\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_1\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(3),
\chosen_reg[3]_0\(0) => \r_pipe/p_1_in_5\,
\chosen_reg[4]\ => \gen_master_slots[3].reg_slice_mi_n_55\,
\chosen_reg[4]_0\ => \gen_master_slots[3].reg_slice_mi_n_56\,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0) => r_issuing_cnt(27 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(47 downto 36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_64_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(106 downto 105),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(139 downto 108),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(47 downto 36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(10 downto 9),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[3].reg_slice_mi_n_7\,
m_axi_bready(0) => m_axi_bready(3),
m_axi_bvalid(0) => m_axi_bvalid(3),
m_axi_rdata(31 downto 0) => m_axi_rdata(127 downto 96),
m_axi_rid(11 downto 0) => m_axi_rid(47 downto 36),
m_axi_rlast(0) => m_axi_rlast(3),
\m_axi_rready[3]\ => M_AXI_RREADY(3),
m_axi_rresp(1 downto 0) => m_axi_rresp(7 downto 6),
m_axi_rvalid(0) => m_axi_rvalid(3),
p_1_in => p_1_in,
p_39_in => p_39_in,
p_62_out => p_62_out,
p_68_out => p_68_out,
p_82_out => p_82_out,
p_88_out => p_88_out,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[3].w_issuing_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(24),
O => \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\
);
\gen_master_slots[3].w_issuing_cnt_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\,
Q => w_issuing_cnt(24),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_9,
Q => w_issuing_cnt(25),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_8,
Q => w_issuing_cnt(26),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_7,
Q => w_issuing_cnt(27),
R => reset
);
\gen_master_slots[4].r_issuing_cnt_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_ar_n_99,
Q => r_issuing_cnt(32),
R => reset
);
\gen_master_slots[4].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4
port map (
D(11 downto 0) => p_32_in(11 downto 0),
E(0) => \r_pipe/p_1_in_6\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4),
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_master_slots[3].reg_slice_mi_n_57\,
\chosen_reg[4]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(4),
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => p_28_in(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 1) => st_mr_rid(59 downto 48),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => p_42_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(11 downto 0) => st_mr_bid(59 downto 48),
m_valid_i_reg => \gen_master_slots[4].reg_slice_mi_n_1\,
mi_bready_4 => mi_bready_4,
mi_rready_4 => mi_rready_4,
p_1_in => p_1_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
p_29_in => p_29_in,
p_40_out => p_40_out,
p_46_out => p_46_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0),
s_ready_i_reg => \gen_master_slots[4].reg_slice_mi_n_5\
);
\gen_master_slots[4].w_issuing_cnt_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_aw_n_25,
Q => w_issuing_cnt(32),
R => reset
);
\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\,
E(0) => s_ready_i0,
Q(4 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(4 downto 0),
SR(0) => reset,
S_AXI_ARREADY(0) => \^s_axi_arready\(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_53\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_53\,
\m_payload_i_reg[0]\(0) => \r_pipe/p_1_in_8\,
\m_payload_i_reg[0]_0\(0) => \r_pipe/p_1_in_7\,
\m_payload_i_reg[0]_1\(0) => \r_pipe/p_1_in_5\,
\m_payload_i_reg[0]_2\(0) => \r_pipe/p_1_in\,
\m_payload_i_reg[34]\(0) => \r_pipe/p_1_in_6\,
\m_payload_i_reg[34]_0\(0) => p_42_out,
\m_payload_i_reg[34]_1\(0) => p_64_out,
\m_payload_i_reg[34]_2\(0) => p_124_out,
\m_payload_i_reg[34]_3\(0) => p_84_out,
\m_payload_i_reg[34]_4\(0) => p_104_out,
m_valid_i => m_valid_i,
m_valid_i_reg => \gen_master_slots[3].reg_slice_mi_n_55\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_54\,
match => match,
p_102_out => p_102_out,
p_122_out => p_122_out,
p_40_out => p_40_out,
p_62_out => p_62_out,
p_82_out => p_82_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(0) => r_issuing_cnt(32),
\s_axi_araddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
\s_axi_araddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
\s_axi_araddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
\s_axi_arid[11]\(11 downto 0) => \s_axi_arqos[3]\(11 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => \s_axi_rid[0]\,
\s_axi_rid[10]\ => \s_axi_rid[10]\,
\s_axi_rid[11]\ => \s_axi_rid[11]\,
\s_axi_rid[1]\ => \s_axi_rid[1]\,
\s_axi_rid[2]\ => \s_axi_rid[2]\,
\s_axi_rid[3]\ => \s_axi_rid[3]\,
\s_axi_rid[4]\ => \s_axi_rid[4]\,
\s_axi_rid[5]\ => \s_axi_rid[5]\,
\s_axi_rid[6]\ => \s_axi_rid[6]\,
\s_axi_rid[7]\ => \s_axi_rid[7]\,
\s_axi_rid[8]\ => \s_axi_rid[8]\,
\s_axi_rid[9]\ => \s_axi_rid[9]\,
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
\s_axi_rvalid[0]\ => \s_axi_rvalid[0]\,
st_mr_rid(59 downto 0) => st_mr_rid(59 downto 0),
st_mr_rmesg(135 downto 104) => st_mr_rmesg(139 downto 108),
st_mr_rmesg(103 downto 70) => st_mr_rmesg(106 downto 73),
st_mr_rmesg(69 downto 36) => st_mr_rmesg(71 downto 38),
st_mr_rmesg(35 downto 2) => st_mr_rmesg(36 downto 3),
st_mr_rmesg(1 downto 0) => st_mr_rmesg(1 downto 0)
);
\gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\,
D(2) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
D(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
E(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
Q(4 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
\gen_master_slots[3].w_issuing_cnt_reg[24]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
\gen_no_arbiter.s_ready_i_reg[0]\(0) => s_ready_i0_11,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_23,
\m_ready_d_reg[1]\ => \^s_axi_awready[0]\,
m_valid_i => m_valid_i_10,
m_valid_i_reg => \gen_master_slots[3].reg_slice_mi_n_56\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_55\,
match => match_3,
p_101_in => p_101_in,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_68_out => p_68_out,
p_84_in => p_84_in,
p_88_out => p_88_out,
\s_axi_awaddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
\s_axi_awaddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
\s_axi_awaddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
\s_axi_awid[11]\(11 downto 0) => D(11 downto 0),
\s_axi_bid[0]\ => \s_axi_bid[0]\,
\s_axi_bid[10]\ => \s_axi_bid[10]\,
\s_axi_bid[11]\ => \s_axi_bid[11]\,
\s_axi_bid[1]\ => \s_axi_bid[1]\,
\s_axi_bid[2]\ => \s_axi_bid[2]\,
\s_axi_bid[3]\ => \s_axi_bid[3]\,
\s_axi_bid[4]\ => \s_axi_bid[4]\,
\s_axi_bid[5]\ => \s_axi_bid[5]\,
\s_axi_bid[6]\ => \s_axi_bid[6]\,
\s_axi_bid[7]\ => \s_axi_bid[7]\,
\s_axi_bid[8]\ => \s_axi_bid[8]\,
\s_axi_bid[9]\ => \s_axi_bid[9]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
\s_axi_bvalid[0]\ => \s_axi_bvalid[0]\,
st_mr_bid(59 downto 0) => st_mr_bid(59 downto 0),
st_mr_bmesg(7 downto 6) => st_mr_bmesg(10 downto 9),
st_mr_bmesg(5 downto 4) => st_mr_bmesg(7 downto 6),
st_mr_bmesg(3 downto 2) => st_mr_bmesg(4 downto 3),
st_mr_bmesg(1 downto 0) => st_mr_bmesg(1 downto 0),
w_issuing_cnt(16) => w_issuing_cnt(32),
w_issuing_cnt(15 downto 12) => w_issuing_cnt(27 downto 24),
w_issuing_cnt(11 downto 8) => w_issuing_cnt(19 downto 16),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
\gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
\s_axi_awready[0]\ => \^s_axi_awready[0]\,
s_axi_awvalid(0) => s_axi_awvalid(0),
ss_aa_awready => ss_aa_awready,
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid
);
\gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router
port map (
D(2) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
D(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
SR(0) => reset,
aclk => aclk,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(0) => m_ready_d(1),
match => match_3,
p_22_in => p_22_in,
\s_axi_awaddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
\s_axi_awaddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
\s_axi_awaddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
\write_cs0__0\ => \write_cs0__0\
);
splitter_aw_mi: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5
port map (
D(2) => splitter_aw_mi_n_0,
D(1) => splitter_aw_mi_n_1,
D(0) => splitter_aw_mi_n_2,
Q(3 downto 0) => aa_mi_awtarget_hot(3 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\chosen_reg[3]\(3 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(3 downto 0),
\gen_axi.s_axi_awready_i_reg\ => splitter_aw_mi_n_3,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(2) => splitter_aw_mi_n_10,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(1) => splitter_aw_mi_n_11,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(0) => splitter_aw_mi_n_12,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(2) => splitter_aw_mi_n_4,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(1) => splitter_aw_mi_n_5,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(0) => splitter_aw_mi_n_6,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(2) => splitter_aw_mi_n_7,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(1) => splitter_aw_mi_n_8,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(0) => splitter_aw_mi_n_9,
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d_12(1 downto 0),
\mi_awready_mux__3\ => \mi_awready_mux__3\,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_68_out => p_68_out,
p_88_out => p_88_out,
s_axi_bready(0) => s_axi_bready(0),
\s_ready_i0__1\(0) => \s_ready_i0__1\(0),
\sa_wm_awready_mux__3\ => \sa_wm_awready_mux__3\,
w_issuing_cnt(15 downto 12) => w_issuing_cnt(27 downto 24),
w_issuing_cnt(11 downto 8) => w_issuing_cnt(19 downto 16),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001101000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 127 downto 96 );
signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 127 downto 96 );
signal \^m_axi_awburst\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \^m_axi_awcache\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 31 downto 24 );
signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^m_axi_awprot\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_awqos\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\(0) <= s_axi_wlast(0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(127 downto 96) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(95 downto 64) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(63 downto 32) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(127 downto 96);
m_axi_arburst(7 downto 6) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(5 downto 4) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(7 downto 6);
m_axi_arcache(15 downto 12) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(11 downto 8) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(15 downto 12);
m_axi_arid(47 downto 36) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(35 downto 24) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_arlen(31 downto 24) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(23 downto 16) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(15 downto 8) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlock(3) <= \^m_axi_arlock\(3);
m_axi_arlock(2) <= \^m_axi_arlock\(3);
m_axi_arlock(1) <= \^m_axi_arlock\(3);
m_axi_arlock(0) <= \^m_axi_arlock\(3);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(11 downto 9);
m_axi_arqos(15 downto 12) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(11 downto 8) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(15 downto 12);
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
m_axi_arregion(12) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(11 downto 9) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(8 downto 6) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(11 downto 9);
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(127 downto 96) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(95 downto 64) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(63 downto 32) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awburst(7 downto 6) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(5 downto 4) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(3 downto 2) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(1 downto 0) <= \^m_axi_awburst\(7 downto 6);
m_axi_awcache(15 downto 12) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(11 downto 8) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(7 downto 4) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(3 downto 0) <= \^m_axi_awcache\(15 downto 12);
m_axi_awid(47 downto 36) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(35 downto 24) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(23 downto 12) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(11 downto 0) <= \^m_axi_awid\(11 downto 0);
m_axi_awlen(31 downto 24) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(23 downto 16) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlock(3) <= \^m_axi_awlock\(3);
m_axi_awlock(2) <= \^m_axi_awlock\(3);
m_axi_awlock(1) <= \^m_axi_awlock\(3);
m_axi_awlock(0) <= \^m_axi_awlock\(3);
m_axi_awprot(11 downto 9) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(8 downto 6) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(5 downto 3) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(2 downto 0) <= \^m_axi_awprot\(11 downto 9);
m_axi_awqos(15 downto 12) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(11 downto 8) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(7 downto 4) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(3 downto 0) <= \^m_axi_awqos\(15 downto 12);
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
m_axi_awregion(12) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(11 downto 9) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(8 downto 6) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(5 downto 3) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(2 downto 0) <= \^m_axi_awsize\(11 downto 9);
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(47) <= \<const0>\;
m_axi_wid(46) <= \<const0>\;
m_axi_wid(45) <= \<const0>\;
m_axi_wid(44) <= \<const0>\;
m_axi_wid(43) <= \<const0>\;
m_axi_wid(42) <= \<const0>\;
m_axi_wid(41) <= \<const0>\;
m_axi_wid(40) <= \<const0>\;
m_axi_wid(39) <= \<const0>\;
m_axi_wid(38) <= \<const0>\;
m_axi_wid(37) <= \<const0>\;
m_axi_wid(36) <= \<const0>\;
m_axi_wid(35) <= \<const0>\;
m_axi_wid(34) <= \<const0>\;
m_axi_wid(33) <= \<const0>\;
m_axi_wid(32) <= \<const0>\;
m_axi_wid(31) <= \<const0>\;
m_axi_wid(30) <= \<const0>\;
m_axi_wid(29) <= \<const0>\;
m_axi_wid(28) <= \<const0>\;
m_axi_wid(27) <= \<const0>\;
m_axi_wid(26) <= \<const0>\;
m_axi_wid(25) <= \<const0>\;
m_axi_wid(24) <= \<const0>\;
m_axi_wid(23) <= \<const0>\;
m_axi_wid(22) <= \<const0>\;
m_axi_wid(21) <= \<const0>\;
m_axi_wid(20) <= \<const0>\;
m_axi_wid(19) <= \<const0>\;
m_axi_wid(18) <= \<const0>\;
m_axi_wid(17) <= \<const0>\;
m_axi_wid(16) <= \<const0>\;
m_axi_wid(15) <= \<const0>\;
m_axi_wid(14) <= \<const0>\;
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(3) <= \^s_axi_wlast\(0);
m_axi_wlast(2) <= \^s_axi_wlast\(0);
m_axi_wlast(1) <= \^s_axi_wlast\(0);
m_axi_wlast(0) <= \^s_axi_wlast\(0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_samd.crossbar_samd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar
port map (
D(68 downto 65) => s_axi_awqos(3 downto 0),
D(64 downto 61) => s_axi_awcache(3 downto 0),
D(60 downto 59) => s_axi_awburst(1 downto 0),
D(58 downto 56) => s_axi_awprot(2 downto 0),
D(55) => s_axi_awlock(0),
D(54 downto 52) => s_axi_awsize(2 downto 0),
D(51 downto 44) => s_axi_awlen(7 downto 0),
D(43 downto 12) => s_axi_awaddr(31 downto 0),
D(11 downto 0) => s_axi_awid(11 downto 0),
M_AXI_RREADY(3 downto 0) => m_axi_rready(3 downto 0),
Q(68 downto 65) => \^m_axi_awqos\(15 downto 12),
Q(64 downto 61) => \^m_axi_awcache\(15 downto 12),
Q(60 downto 59) => \^m_axi_awburst\(7 downto 6),
Q(58 downto 56) => \^m_axi_awprot\(11 downto 9),
Q(55) => \^m_axi_awlock\(3),
Q(54 downto 52) => \^m_axi_awsize\(11 downto 9),
Q(51 downto 44) => \^m_axi_awlen\(31 downto 24),
Q(43 downto 12) => \^m_axi_awaddr\(127 downto 96),
Q(11 downto 0) => \^m_axi_awid\(11 downto 0),
S_AXI_ARREADY(0) => s_axi_arready(0),
aclk => aclk,
aresetn => aresetn,
\m_axi_arqos[15]\(68 downto 65) => \^m_axi_arqos\(15 downto 12),
\m_axi_arqos[15]\(64 downto 61) => \^m_axi_arcache\(15 downto 12),
\m_axi_arqos[15]\(60 downto 59) => \^m_axi_arburst\(7 downto 6),
\m_axi_arqos[15]\(58 downto 56) => \^m_axi_arprot\(11 downto 9),
\m_axi_arqos[15]\(55) => \^m_axi_arlock\(3),
\m_axi_arqos[15]\(54 downto 52) => \^m_axi_arsize\(11 downto 9),
\m_axi_arqos[15]\(51 downto 44) => \^m_axi_arlen\(7 downto 0),
\m_axi_arqos[15]\(43 downto 12) => \^m_axi_araddr\(127 downto 96),
\m_axi_arqos[15]\(11 downto 0) => \^m_axi_arid\(11 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => m_axi_bid(47 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => m_axi_rid(47 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
\s_axi_arqos[3]\(68 downto 65) => s_axi_arqos(3 downto 0),
\s_axi_arqos[3]\(64 downto 61) => s_axi_arcache(3 downto 0),
\s_axi_arqos[3]\(60 downto 59) => s_axi_arburst(1 downto 0),
\s_axi_arqos[3]\(58 downto 56) => s_axi_arprot(2 downto 0),
\s_axi_arqos[3]\(55) => s_axi_arlock(0),
\s_axi_arqos[3]\(54 downto 52) => s_axi_arsize(2 downto 0),
\s_axi_arqos[3]\(51 downto 44) => s_axi_arlen(7 downto 0),
\s_axi_arqos[3]\(43 downto 12) => s_axi_araddr(31 downto 0),
\s_axi_arqos[3]\(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
\s_axi_awready[0]\ => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
\s_axi_bid[0]\ => s_axi_bid(0),
\s_axi_bid[10]\ => s_axi_bid(10),
\s_axi_bid[11]\ => s_axi_bid(11),
\s_axi_bid[1]\ => s_axi_bid(1),
\s_axi_bid[2]\ => s_axi_bid(2),
\s_axi_bid[3]\ => s_axi_bid(3),
\s_axi_bid[4]\ => s_axi_bid(4),
\s_axi_bid[5]\ => s_axi_bid(5),
\s_axi_bid[6]\ => s_axi_bid(6),
\s_axi_bid[7]\ => s_axi_bid(7),
\s_axi_bid[8]\ => s_axi_bid(8),
\s_axi_bid[9]\ => s_axi_bid(9),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
\s_axi_bvalid[0]\ => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => s_axi_rid(0),
\s_axi_rid[10]\ => s_axi_rid(10),
\s_axi_rid[11]\ => s_axi_rid(11),
\s_axi_rid[1]\ => s_axi_rid(1),
\s_axi_rid[2]\ => s_axi_rid(2),
\s_axi_rid[3]\ => s_axi_rid(3),
\s_axi_rid[4]\ => s_axi_rid(4),
\s_axi_rid[5]\ => s_axi_rid(5),
\s_axi_rid[6]\ => s_axi_rid(6),
\s_axi_rid[7]\ => s_axi_rid(7),
\s_axi_rid[8]\ => s_axi_rid(8),
\s_axi_rid[9]\ => s_axi_rid(9),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
\s_axi_rvalid[0]\ => s_axi_rvalid(0),
s_axi_wlast(0) => \^s_axi_wlast\(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "128'b00000000000000000000000000001101000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 8;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(127 downto 0) => m_axi_araddr(127 downto 0),
m_axi_arburst(7 downto 0) => m_axi_arburst(7 downto 0),
m_axi_arcache(15 downto 0) => m_axi_arcache(15 downto 0),
m_axi_arid(47 downto 0) => m_axi_arid(47 downto 0),
m_axi_arlen(31 downto 0) => m_axi_arlen(31 downto 0),
m_axi_arlock(3 downto 0) => m_axi_arlock(3 downto 0),
m_axi_arprot(11 downto 0) => m_axi_arprot(11 downto 0),
m_axi_arqos(15 downto 0) => m_axi_arqos(15 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arregion(15 downto 0) => m_axi_arregion(15 downto 0),
m_axi_arsize(11 downto 0) => m_axi_arsize(11 downto 0),
m_axi_aruser(3 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awaddr(127 downto 0) => m_axi_awaddr(127 downto 0),
m_axi_awburst(7 downto 0) => m_axi_awburst(7 downto 0),
m_axi_awcache(15 downto 0) => m_axi_awcache(15 downto 0),
m_axi_awid(47 downto 0) => m_axi_awid(47 downto 0),
m_axi_awlen(31 downto 0) => m_axi_awlen(31 downto 0),
m_axi_awlock(3 downto 0) => m_axi_awlock(3 downto 0),
m_axi_awprot(11 downto 0) => m_axi_awprot(11 downto 0),
m_axi_awqos(15 downto 0) => m_axi_awqos(15 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awregion(15 downto 0) => m_axi_awregion(15 downto 0),
m_axi_awsize(11 downto 0) => m_axi_awsize(11 downto 0),
m_axi_awuser(3 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => m_axi_bid(47 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_buser(3 downto 0) => B"0000",
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => m_axi_rid(47 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rready(3 downto 0) => m_axi_rready(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_ruser(3 downto 0) => B"0000",
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(47 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(47 downto 0),
m_axi_wlast(3 downto 0) => m_axi_wlast(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(3 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE ieee.math_real.ceil;
USE ieee.math_real.log2;
-- TODO - review this whole scheme
-- Massively overcomplex and turbo doesn't even work with it right now!
ENTITY shared_enable IS
GENERIC
(
cycle_length : integer := 16 -- or 32...
);
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ANTIC_REFRESH : IN STD_LOGIC;
MEMORY_READY_CPU : IN STD_LOGIC; -- during memory wait states keep CPU awake
MEMORY_READY_ANTIC : IN STD_LOGIC; -- during memory wait states keep CPU awake
PAUSE_6502 : in std_logic;
THROTTLE_COUNT_6502 : in std_logic_vector(5 downto 0);
ANTIC_ENABLE_179 : OUT STD_LOGIC; -- always about 1.79MHz to keep sound the same - 1 cycle early
oldcpu_enable : OUT STD_LOGIC; -- always about 1.79MHz to keep sound the same - 1 cycle only, when memory is ready...
CPU_ENABLE_OUT : OUT STD_LOGIC -- for compatibility run at 1.79MHz, for speed run as fast as we can
-- antic DMA runs 1 cycle after 'enable', so ANTIC_ENABLE is delayed by cycle_length-1 cycles vs CPU_ENABLE (when in 1.79MHz mode)
);
END shared_enable;
ARCHITECTURE vhdl OF shared_enable IS
component enable_divider IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE_IN : IN STD_LOGIC;
ENABLE_OUT : OUT STD_LOGIC
);
END component;
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
signal enable_179 : std_logic;
signal enable_179_early : std_logic;
signal cpu_enable : std_logic;
signal cpu_extra_enable_next : std_logic;
signal cpu_extra_enable_reg : std_logic;
signal speed_shift_next : std_logic_vector(cycle_length-1 downto 0);
signal speed_shift_reg : std_logic_vector(cycle_length-1 downto 0);
-- TODO - clean up
signal oldcpu_pending_next : std_logic;
signal oldcpu_pending_reg : std_logic;
signal oldcpu_go : std_logic;
signal memory_ready : std_logic;
constant cycle_length_bits: integer := integer(ceil(log2(real(cycle_length))));
begin
-- instantiate some clock calcs
enable_179_clock_div : enable_divider
generic map (COUNT=>cycle_length)
port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
process(THROTTLE_COUNT_6502, speed_shift_reg, enable_179)
variable speed_shift : std_logic;
variable speed_shift_temp : std_logic_vector(cycle_length-1 downto 0);
begin
if (enable_179 = '1') then -- synchronize
speed_shift_temp(cycle_length-1 downto 1) := (others=>'0');
speed_shift_temp(0) := '1';
else
speed_shift_temp := speed_shift_reg;
end if;
speed_shift_next(cycle_length-1 downto 1) <= speed_shift_temp(cycle_length-2 downto 0);
speed_shift := '0';
for i in 0 to cycle_length_bits loop
speed_shift := speed_shift or (speed_shift_temp(cycle_length/(2**i)-1) and throttle_count_6502(i));
end loop;
speed_shift_next(0) <= speed_shift;
end process;
delay_line_phase : delay_line
generic map (COUNT=>cycle_length-1)
port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);
-- registers
process(clk,reset_n)
begin
if (reset_n = '0') then
cpu_extra_enable_reg <= '0';
oldcpu_pending_reg <= '0';
speed_shift_reg <= (others=>'0');
elsif (clk'event and clk='1') then
cpu_extra_enable_reg <= cpu_extra_enable_next;
oldcpu_pending_reg <= oldcpu_pending_next;
speed_shift_reg <= speed_shift_next;
end if;
end process;
-- next state
memory_ready <= memORY_READY_CPU or memORY_READY_ANTIC;
cpu_enable <= (speed_shift_reg(0) or cpu_extra_enable_reg or enable_179) and not(pause_6502 or antic_refresh);
cpu_extra_enable_next <= cpu_enable and not(memory_ready);
oldcpu_pending_next <= (oldcpu_pending_reg or enable_179) and not(memory_ready or antic_refresh);
oldcpu_go <= (oldcpu_pending_reg or enable_179) and (memory_ready or antic_refresh);
-- output
oldcpu_enable <= oldcpu_go;
ANTIC_ENABLE_179 <= enable_179_early;
CPU_ENABLE_OUT <= cpu_enable; -- run at 25MHz
end vhdl;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01200_bad.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of process label: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_01200_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_01200_bad;
architecture Behavioral of CNE_01200_bad is
signal Q : std_logic; -- D Flip-Flop output
begin
--CODE
-- D FlipFlop process
FlipFlop:process(i_Clock, i_Reset_n)
begin
if (i_Reset_n='0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
Q <= i_D;
end if;
end process;
--CODE
o_Q <= Q;
end Behavioral; |
-- $Id: pdp11_ounit.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_ounit - syn
-- Description: pdp11: arithmetic unit for addresses (ounit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-09-18 300 1.1 renamed from abox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_ounit is -- offset adder for addresses (ounit)
port (
DSRC : in slv16; -- 'src' data for port A
DDST : in slv16; -- 'dst' data for port A
DTMP : in slv16; -- 'tmp' data for port A
PC : in slv16; -- PC data for port A
ASEL : in slv2; -- selector for port A
AZERO : in slbit; -- force zero for port A
IREG8 : in slv8; -- 'ireg' data for port B
VMDOUT : in slv16; -- virt. memory data for port B
CONST : in slv9; -- sequencer const data for port B
BSEL : in slv2; -- selector for port B
OPSUB : in slbit; -- operation: 0 add, 1 sub
DOUT : out slv16; -- data output
NZOUT : out slv2 -- NZ condition codes out
);
end pdp11_ounit;
architecture syn of pdp11_ounit is
-- --------------------------------------
begin
process (DSRC, DDST, DTMP, PC, ASEL, AZERO,
IREG8, VMDOUT, CONST, BSEL, OPSUB)
variable ma : slv16 := (others=>'0'); -- effective port a data
variable mb : slv16 := (others=>'0'); -- effective port b data
variable sum : slv16 := (others=>'0'); -- sum
variable nzo : slbit := '0';
begin
if AZERO = '0' then
case ASEL is
when c_ounit_asel_dsrc => ma := DSRC;
when c_ounit_asel_ddst => ma := DDST;
when c_ounit_asel_dtmp => ma := DTMP;
when c_ounit_asel_pc => ma := PC;
when others => null;
end case;
else
ma := (others=>'0');
end if;
case BSEL is
when c_ounit_bsel_ireg6 => mb := "000000000" & IREG8(5 downto 0) & "0";
when c_ounit_bsel_ireg8 => mb := IREG8(7) & IREG8(7) & IREG8(7) &
IREG8(7) & IREG8(7) & IREG8(7) &
IREG8(7) & IREG8 & "0";
when c_ounit_bsel_vmdout => mb := VMDOUT;
when c_ounit_bsel_const => mb := "0000000" & CONST;
when others => null;
end case;
if OPSUB = '0' then
sum := slv(unsigned(ma) + unsigned(mb));
else
sum := slv(unsigned(ma) - unsigned(mb));
end if;
nzo := '0';
if unsigned(sum) = 0 then
nzo := '1';
else
nzo := '0';
end if;
DOUT <= sum;
NZOUT(1) <= sum(15);
NZOUT(0) <= nzo;
end process;
end syn;
|
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