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-- *****************************************************************************************
-- Standard libraries
-- Version 0.2
-- Modified 02.12.2006
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package std_library is
type log2array_type is array(0 to 1024) of integer;
constant fn_log2 : log2array_type := (
0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
others => 10);
constant fn_log2x : log2array_type := (
0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
others => 10);
-- *********************************************************************************
function fn_det_x(d : std_logic_vector) return boolean;
function fn_det_x(d : std_logic) return boolean;
function fn_xor_vect(vect : std_logic_vector) return std_logic;
function fn_or_vect(vect : std_logic_vector) return std_logic;
function fn_and_vect(vect : std_logic_vector) return std_logic;
function fn_to_integer(vect : std_logic_vector) return integer;
function fn_to_integer(d : std_logic) return integer;
function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector;
function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector;
function fn_to_std_logic(b : boolean) return std_logic;
function fn_dcd(vect : std_logic_vector) return std_logic_vector;
function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic;
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector;
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector;
function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector;
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector;
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector;
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector;
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector;
end std_library;
package body std_library is
function fn_det_x(d : std_logic_vector) return boolean is
variable result : boolean;
begin
result := FALSE;
-- pragma translate_off
result := is_x(d);
-- pragma translate_on
return (result);
end fn_det_x;
function fn_det_x(d : std_logic) return boolean is
variable result : boolean;
begin
result := FALSE;
-- pragma translate_off
result := is_x(d);
-- pragma translate_on
return (result);
end fn_det_x;
function fn_xor_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '0';
for i in vect'range loop
temp := temp xor vect(i);
end loop;
return(temp);
end fn_xor_vect;
function fn_or_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '0';
for i in vect'range loop
temp := temp or vect(i);
end loop;
return(temp);
end fn_or_vect;
function fn_and_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '1';
for i in vect'range loop
temp := temp and vect(i);
end loop;
return(temp);
end fn_and_vect;
function fn_to_integer(vect : std_logic_vector) return integer is
begin
if (not fn_det_x(vect)) then
return(to_integer(unsigned(vect)));
else
return(0);
end if;
end fn_to_integer;
function fn_to_integer(d : std_logic) return integer is
begin
if (not fn_det_x(d)) then
if (d = '1') then
return(1);
else
return(0);
end if;
else
return(0);
end if;
end fn_to_integer;
function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
begin
temp := std_logic_vector(to_unsigned(int, width));
return(temp);
end fn_to_std_logic_vector;
function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
begin
temp := std_logic_vector(to_signed(int, width));
return(temp);
end fn_to_std_logic_vector_signed;
function fn_to_std_logic(b : boolean) return std_logic is
begin
if (b) then
return('1');
else
return('0');
end if;
end fn_to_std_logic;
function fn_dcd(vect : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector((2**vect'length)-1 downto 0);
variable i : integer range result'range;
begin
result := (others => '0');
i := 0;
if (not fn_det_x(vect)) then
i := to_integer(unsigned(vect));
end if;
result(i) := '1';
return(result);
end fn_dcd;
function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic is
variable result : std_logic_vector(vect'length-1 downto 0);
variable i : integer range result'range;
begin
result := vect;
i := 0;
if (not fn_det_x(sel)) then
i := to_integer(unsigned(sel));
end if;
return(result(i));
end fn_mux;
-- >>>>
function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect_a) or fn_det_x(vect_b)) then
tmp_a := (others =>'X');
tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect_a) + unsigned(vect_b)));
end "+";
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) + int));
end "+";
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
-- pragma translate_off
if (fn_det_x(vect) or fn_det_x(d)) then
tmp_b := (others =>'X');
return(tmp_b);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) + unsigned(tmp_b)));
end "+";
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect_a) or fn_det_x(vect_b)) then
tmp_a := (others =>'X'); tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect_a) - unsigned(vect_b)));
end "-";
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) - int));
end "-";
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(int - unsigned(vect)));
end "-";
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
-- pragma translate_off
if (fn_det_x(vect) or fn_det_x(d)) then
tmp_a := (others =>'X');
return(tmp_a);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) - unsigned(tmp_b)));
end "-";
end std_library;
|
-- *****************************************************************************************
-- Standard libraries
-- Version 0.2
-- Modified 02.12.2006
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package std_library is
type log2array_type is array(0 to 1024) of integer;
constant fn_log2 : log2array_type := (
0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
others => 10);
constant fn_log2x : log2array_type := (
0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
others => 10);
-- *********************************************************************************
function fn_det_x(d : std_logic_vector) return boolean;
function fn_det_x(d : std_logic) return boolean;
function fn_xor_vect(vect : std_logic_vector) return std_logic;
function fn_or_vect(vect : std_logic_vector) return std_logic;
function fn_and_vect(vect : std_logic_vector) return std_logic;
function fn_to_integer(vect : std_logic_vector) return integer;
function fn_to_integer(d : std_logic) return integer;
function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector;
function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector;
function fn_to_std_logic(b : boolean) return std_logic;
function fn_dcd(vect : std_logic_vector) return std_logic_vector;
function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic;
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector;
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector;
function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector;
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector;
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector;
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector;
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector;
end std_library;
package body std_library is
function fn_det_x(d : std_logic_vector) return boolean is
variable result : boolean;
begin
result := FALSE;
-- pragma translate_off
result := is_x(d);
-- pragma translate_on
return (result);
end fn_det_x;
function fn_det_x(d : std_logic) return boolean is
variable result : boolean;
begin
result := FALSE;
-- pragma translate_off
result := is_x(d);
-- pragma translate_on
return (result);
end fn_det_x;
function fn_xor_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '0';
for i in vect'range loop
temp := temp xor vect(i);
end loop;
return(temp);
end fn_xor_vect;
function fn_or_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '0';
for i in vect'range loop
temp := temp or vect(i);
end loop;
return(temp);
end fn_or_vect;
function fn_and_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '1';
for i in vect'range loop
temp := temp and vect(i);
end loop;
return(temp);
end fn_and_vect;
function fn_to_integer(vect : std_logic_vector) return integer is
begin
if (not fn_det_x(vect)) then
return(to_integer(unsigned(vect)));
else
return(0);
end if;
end fn_to_integer;
function fn_to_integer(d : std_logic) return integer is
begin
if (not fn_det_x(d)) then
if (d = '1') then
return(1);
else
return(0);
end if;
else
return(0);
end if;
end fn_to_integer;
function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
begin
temp := std_logic_vector(to_unsigned(int, width));
return(temp);
end fn_to_std_logic_vector;
function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
begin
temp := std_logic_vector(to_signed(int, width));
return(temp);
end fn_to_std_logic_vector_signed;
function fn_to_std_logic(b : boolean) return std_logic is
begin
if (b) then
return('1');
else
return('0');
end if;
end fn_to_std_logic;
function fn_dcd(vect : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector((2**vect'length)-1 downto 0);
variable i : integer range result'range;
begin
result := (others => '0');
i := 0;
if (not fn_det_x(vect)) then
i := to_integer(unsigned(vect));
end if;
result(i) := '1';
return(result);
end fn_dcd;
function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic is
variable result : std_logic_vector(vect'length-1 downto 0);
variable i : integer range result'range;
begin
result := vect;
i := 0;
if (not fn_det_x(sel)) then
i := to_integer(unsigned(sel));
end if;
return(result(i));
end fn_mux;
-- >>>>
function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect_a) or fn_det_x(vect_b)) then
tmp_a := (others =>'X');
tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect_a) + unsigned(vect_b)));
end "+";
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) + int));
end "+";
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
-- pragma translate_off
if (fn_det_x(vect) or fn_det_x(d)) then
tmp_b := (others =>'X');
return(tmp_b);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) + unsigned(tmp_b)));
end "+";
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect_a) or fn_det_x(vect_b)) then
tmp_a := (others =>'X'); tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect_a) - unsigned(vect_b)));
end "-";
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) - int));
end "-";
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(int - unsigned(vect)));
end "-";
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
-- pragma translate_off
if (fn_det_x(vect) or fn_det_x(d)) then
tmp_a := (others =>'X');
return(tmp_a);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) - unsigned(tmp_b)));
end "-";
end std_library;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:05:49 10/31/2011
-- Design Name:
-- Module Name: preEscalador - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity preEscalador is
Port (clk : in STD_LOGIC;
reset : in STD_LOGIC;
caidaBolitaOut : out STD_LOGIC;
multiplexorOut : out STD_LOGIC
);
end preEscalador;
architecture Behavioral of preEscalador is
signal contCaidaBolita : integer range 0 to 1100000;--***
signal contMultiplexor : integer range 0 to 33000;--***
signal caidaBolita : STD_LOGIC;
signal multiplexor : STD_LOGIC;
begin
process(reset,clk,contCaidaBolita,contMultiplexor,caidaBolita,multiplexor)
begin
if reset = '1' then
caidaBolita <= '0';
multiplexor <= '0';
contCaidaBolita <= 1100000;--***
contMultiplexor <= 33000;--***
elsif clk'event and clk = '1' then
if contCaidaBolita = 0 then
contCaidaBolita <= 1100000;--***
if caidaBolita = '1' then
caidaBolita <= '0';
else
caidaBolita <= '1';
end if;
else
contCaidaBolita <= contCaidaBolita - 1;
end if;
if contMultiplexor = 0 then
contMultiplexor <= 33000; --***
if multiplexor = '1' then
multiplexor <= '0';
else
multiplexor <= '1';
end if;
else
contMultiplexor <= contMultiplexor - 1;
end if;
end if;
end process;
process(clk,reset,multiplexor,caidaBolita)
begin
if reset = '1' then
caidaBolitaOut <= '0';
multiplexorOut <= '0';
elsif clk'event and clk = '1' then
multiplexorOut <= multiplexor;
caidaBolitaOut <= caidaBolita;
end if;
end process;
end Behavioral;
|
architecture RTL of ENTITY1 is
signal sig1, sig2 : std_logic;
signal sig9 : std_logic;
signal sig3 : std_logic;
signal sig4 : std_logic;
signal sig5 : std_logic;
signal sig6 : std_logic;
signal sig7 : std_logic;
component COMP1 is
port (
SIG1 : in std_logic;
SIG2 : out std_logic;
SIG3 : in std_logic
);
end component COMP1;
begin
PROC_NAME : process (siG2) is
begin
siG1 <= '0';
if (SIG2 = '0') then
sIg1 <= '1';
elsif (SiG2 = '1') then
SIg1 <= '0';
end if;
end process PROC_NAME;
-- This is a component that is brought in by a component declaration in the same file
U_COMP1 : COMP1
port map (
SIG1 => Sig1,
SIG2 => SIg2,
SIG3 => sig3
);
-- This is a component that is brought in by a package
U_COMP2 : COMP2
port map (
SIG3 => Sig3,
SIG4 => sig4,
SIG5 => siG5
);
-- This is a component that is directly instantiated
U_COMP3 : entity library.COMP3
port map (
SIG6 => siG6,
SIG7 => sig7
);
Sig1 <= '0';
sig1 <= sig2 and sig3;
sig1 <= Sig2 and sig3;
sig1 <= sig2 and
Sig3;
SIG1 <= SIG2 and SIG3;
SIG1 <= SIG1 or SIG1;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
entity hello is
generic (constant l : natural := 8);
port (a : in std_logic_vector (l - 1 downto 0));
end hello;
architecture behav of hello is
` signal clk : std_logic;
signal q : std_logic_vector (lrocess
begin
& clk <= '0';
wait for 1 ns;
clk <= '1'for 1 ns;
end processy
process (clk)
begin
if rhsing_edge(clk) then
q <= a;
end if;
end process;
assert false repSrrolt "Hello world" severity note;
end behav;
|
-------------------------------------------------------------------------------
-- wrap_brst.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wrap_brst.vhd
--
-- Description: Create sub module for logic to generate WRAP burst
-- address for rd_chnl and wr_chnl.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 2/7/2011 v1.03a
-- ~~~~~~
-- Remove axi_bram_ctrl_funcs package use.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, wrap_burst_total_cmb,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 3/24/2011 v1.03a
-- ~~~~~~
-- Add specific generate blocks based on C_AXI_DATA_WIDTH to calculate
-- total WRAP burst size for improved FPGA resource utilization.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Clean up code.
-- Re-code wrap_burst_total_cmb process blocks for each data width
-- to improve and catch all false conditions in code coverage analysis.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wrap_brst is
generic (
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_AXI_DATA_WIDTH : integer := 32
-- Width of AXI data bus (in bits)
);
port (
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
curr_axlen : in std_logic_vector(7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector(2 downto 0) := (others => '0');
curr_narrow_burst : in std_logic;
narrow_bram_addr_inc_re : in std_logic;
bram_addr_ld_en : in std_logic;
bram_addr_ld : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_int : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_ld_wrap : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
max_wrap_burst_mod : out std_logic := '0'
);
end entity wrap_brst;
-------------------------------------------------------------------------------
architecture implementation of wrap_brst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Constants for WRAP size decoding to simplify integer represenation.
constant C_WRAP_SIZE_2 : std_logic_vector (2 downto 0) := "001";
constant C_WRAP_SIZE_4 : std_logic_vector (2 downto 0) := "010";
constant C_WRAP_SIZE_8 : std_logic_vector (2 downto 0) := "011";
constant C_WRAP_SIZE_16 : std_logic_vector (2 downto 0) := "100";
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal max_wrap_burst : std_logic := '0';
signal save_init_bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1)
:= (others => '0');
-- signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
-- signal curr_axsize_int : integer := 0;
-- signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
-- Holds burst length/size total (based on width of BRAM width)
-- Max size = max length of burst (256 beats)
-- signal wrap_burst_total_cmb : integer range 0 to 256 := 1; -- Max 256 (= 32768d / 128 bytes)
-- signal wrap_burst_total : integer range 0 to 256 := 1;
signal wrap_burst_total_cmb : std_logic_vector (2 downto 0) := (others => '0');
signal wrap_burst_total : std_logic_vector (2 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1 : unsigned (7 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Modify counter size based on size of current write burst operation
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Based on AxSIZE and AxLEN
-- To minimize muxing on initial load of counter value
-- Detect on WRAP burst types, when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value.
-- Save initial load address value.
REG_INIT_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
save_init_bram_addr_ld <= (others => '0');
elsif (bram_addr_ld_en = '1') then
save_init_bram_addr_ld <= bram_addr_ld(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
else
save_init_bram_addr_ld <= save_init_bram_addr_ld;
end if;
end if;
end process REG_INIT_BRAM_ADDR;
---------------------------------------------------------------------------
-- v1.03a
-- Calculate AXI size (integer)
-- curr_axsize_unsigned <= unsigned (curr_axsize);
-- curr_axsize_int <= to_integer (curr_axsize_unsigned);
-- Calculate AXI length (integer)
-- curr_axlen_unsigned <= unsigned (curr_axlen);
-- curr_axlen_unsigned_plus1 <= curr_axlen_unsigned + "00000001";
-- WRAP = size * length (based on BRAM data width in bytes)
--
-- Original multiply function:
-- wrap_burst_total_cmb <= (size_bytes_int * len_int) / C_AXI_DATA_WIDTH_BYTES;
-- For XST, modify integer multiply function to improve timing.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
-- LEN_LSHIFT: process (curr_axlen_unsigned_plus1, curr_axsize_int)
-- begin
--
-- for i in C_MAX_LSHIFT_SIZE downto 0 loop
--
-- if (i >= curr_axsize_int + 8) then
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- elsif (i >= curr_axsize_int) then
-- curr_axlen_unsigned_plus1_lshift (i) <= curr_axlen_unsigned_plus1 (i - curr_axsize_int);
-- else
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- end if;
--
-- end loop;
--
-- end process LEN_LSHIFT;
-- Final signal assignment for XST & timing improvements.
-- wrap_burst_total_cmb <= to_integer (curr_axlen_unsigned_plus1_lshift) / C_AXI_DATA_WIDTH_BYTES;
---------------------------------------------------------------------------
-- v1.03a
-- For best FPGA resource implementation, hard code the generation of
-- WRAP burst size based on each C_AXI_DATA_WIDTH possibility.
---------------------------------------------------------------------------
-- Generate: GEN_32_WRAP_SIZE
-- Purpose: These wrap size values only apply to 32-bit BRAM.
---------------------------------------------------------------------------
GEN_32_WRAP_SIZE: if C_AXI_DATA_WIDTH = 32 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 4 bytes (full AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/2 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/4 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_32_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_64_WRAP_SIZE
-- Purpose: These wrap size values only apply to 64-bit BRAM.
---------------------------------------------------------------------------
GEN_64_WRAP_SIZE: if C_AXI_DATA_WIDTH = 64 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 8 bytes (full AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/2 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/4 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/8 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_64_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_128_WRAP_SIZE
-- Purpose: These wrap size values only apply to 128-bit BRAM.
---------------------------------------------------------------------------
GEN_128_WRAP_SIZE: if C_AXI_DATA_WIDTH = 128 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 16 bytes (full AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/2 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/4 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/8 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_128_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_256_WRAP_SIZE
-- Purpose: These wrap size values only apply to 256-bit BRAM.
---------------------------------------------------------------------------
GEN_256_WRAP_SIZE: if C_AXI_DATA_WIDTH = 256 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 32 bytes (full AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/2 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/4 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/8 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_256_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_512_WRAP_SIZE
-- Purpose: These wrap size values only apply to 512-bit BRAM.
---------------------------------------------------------------------------
GEN_512_WRAP_SIZE: if C_AXI_DATA_WIDTH = 512 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 64 bytes (full AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/2 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/4 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/8 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_512_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_1024_WRAP_SIZE
-- Purpose: These wrap size values only apply to 1024-bit BRAM.
---------------------------------------------------------------------------
GEN_1024_WRAP_SIZE: if C_AXI_DATA_WIDTH = 1024 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 128 bytes (full AXI size)
when C_AXI_SIZE_128BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 64 bytes (1/2 AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/4 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/8 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_1024_WRAP_SIZE;
---------------------------------------------------------------------------
-- Early decode to determine size of WRAP transfer
-- Goal to break up long timing path to generate max_wrap_burst signal.
REG_WRAP_TOTAL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wrap_burst_total <= (others => '0');
elsif (bram_addr_ld_en = '1') then
wrap_burst_total <= wrap_burst_total_cmb;
else
wrap_burst_total <= wrap_burst_total;
end if;
end if;
end process REG_WRAP_TOTAL;
---------------------------------------------------------------------------
CHECK_WRAP_MAX : process ( wrap_burst_total,
bram_addr_int,
save_init_bram_addr_ld )
begin
-- Check BRAM address value if max value is reached.
-- Max value is based on burst size/length for operation.
-- Address bits to check vary based on C_S_AXI_DATA_WIDTH and burst size/length.
-- (use signal, wrap_burst_total, based on current WRAP burst size/length/data width).
case wrap_burst_total is
when C_WRAP_SIZE_2 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR) = '1') then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
when C_WRAP_SIZE_4 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR) = "11") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "00";
when C_WRAP_SIZE_8 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR) = "111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "000";
when C_WRAP_SIZE_16 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR) = "1111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "0000";
when others =>
max_wrap_burst <= '0';
bram_addr_ld_wrap(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld;
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
end case;
end process CHECK_WRAP_MAX;
---------------------------------------------------------------------------
-- Move outside of CHECK_WRAP_MAX process.
-- Account for narrow burst operations.
--
-- Currently max_wrap_burst is getting asserted at the first address beat to BRAM
-- that indicates the maximum WRAP burst boundary. Must wait for the completion of the
-- narrow wrap burst counter to assert max_wrap_burst.
--
-- Indicates when narrow burst address counter hits max (all zeros value)
-- narrow_bram_addr_inc_re
max_wrap_burst_mod <= max_wrap_burst when (curr_narrow_burst = '0') else
(max_wrap_burst and narrow_bram_addr_inc_re);
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- wrap_brst.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wrap_brst.vhd
--
-- Description: Create sub module for logic to generate WRAP burst
-- address for rd_chnl and wr_chnl.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 2/7/2011 v1.03a
-- ~~~~~~
-- Remove axi_bram_ctrl_funcs package use.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, wrap_burst_total_cmb,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 3/24/2011 v1.03a
-- ~~~~~~
-- Add specific generate blocks based on C_AXI_DATA_WIDTH to calculate
-- total WRAP burst size for improved FPGA resource utilization.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Clean up code.
-- Re-code wrap_burst_total_cmb process blocks for each data width
-- to improve and catch all false conditions in code coverage analysis.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wrap_brst is
generic (
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_AXI_DATA_WIDTH : integer := 32
-- Width of AXI data bus (in bits)
);
port (
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
curr_axlen : in std_logic_vector(7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector(2 downto 0) := (others => '0');
curr_narrow_burst : in std_logic;
narrow_bram_addr_inc_re : in std_logic;
bram_addr_ld_en : in std_logic;
bram_addr_ld : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_int : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_ld_wrap : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
max_wrap_burst_mod : out std_logic := '0'
);
end entity wrap_brst;
-------------------------------------------------------------------------------
architecture implementation of wrap_brst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Constants for WRAP size decoding to simplify integer represenation.
constant C_WRAP_SIZE_2 : std_logic_vector (2 downto 0) := "001";
constant C_WRAP_SIZE_4 : std_logic_vector (2 downto 0) := "010";
constant C_WRAP_SIZE_8 : std_logic_vector (2 downto 0) := "011";
constant C_WRAP_SIZE_16 : std_logic_vector (2 downto 0) := "100";
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal max_wrap_burst : std_logic := '0';
signal save_init_bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1)
:= (others => '0');
-- signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
-- signal curr_axsize_int : integer := 0;
-- signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
-- Holds burst length/size total (based on width of BRAM width)
-- Max size = max length of burst (256 beats)
-- signal wrap_burst_total_cmb : integer range 0 to 256 := 1; -- Max 256 (= 32768d / 128 bytes)
-- signal wrap_burst_total : integer range 0 to 256 := 1;
signal wrap_burst_total_cmb : std_logic_vector (2 downto 0) := (others => '0');
signal wrap_burst_total : std_logic_vector (2 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1 : unsigned (7 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Modify counter size based on size of current write burst operation
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Based on AxSIZE and AxLEN
-- To minimize muxing on initial load of counter value
-- Detect on WRAP burst types, when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value.
-- Save initial load address value.
REG_INIT_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
save_init_bram_addr_ld <= (others => '0');
elsif (bram_addr_ld_en = '1') then
save_init_bram_addr_ld <= bram_addr_ld(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
else
save_init_bram_addr_ld <= save_init_bram_addr_ld;
end if;
end if;
end process REG_INIT_BRAM_ADDR;
---------------------------------------------------------------------------
-- v1.03a
-- Calculate AXI size (integer)
-- curr_axsize_unsigned <= unsigned (curr_axsize);
-- curr_axsize_int <= to_integer (curr_axsize_unsigned);
-- Calculate AXI length (integer)
-- curr_axlen_unsigned <= unsigned (curr_axlen);
-- curr_axlen_unsigned_plus1 <= curr_axlen_unsigned + "00000001";
-- WRAP = size * length (based on BRAM data width in bytes)
--
-- Original multiply function:
-- wrap_burst_total_cmb <= (size_bytes_int * len_int) / C_AXI_DATA_WIDTH_BYTES;
-- For XST, modify integer multiply function to improve timing.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
-- LEN_LSHIFT: process (curr_axlen_unsigned_plus1, curr_axsize_int)
-- begin
--
-- for i in C_MAX_LSHIFT_SIZE downto 0 loop
--
-- if (i >= curr_axsize_int + 8) then
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- elsif (i >= curr_axsize_int) then
-- curr_axlen_unsigned_plus1_lshift (i) <= curr_axlen_unsigned_plus1 (i - curr_axsize_int);
-- else
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- end if;
--
-- end loop;
--
-- end process LEN_LSHIFT;
-- Final signal assignment for XST & timing improvements.
-- wrap_burst_total_cmb <= to_integer (curr_axlen_unsigned_plus1_lshift) / C_AXI_DATA_WIDTH_BYTES;
---------------------------------------------------------------------------
-- v1.03a
-- For best FPGA resource implementation, hard code the generation of
-- WRAP burst size based on each C_AXI_DATA_WIDTH possibility.
---------------------------------------------------------------------------
-- Generate: GEN_32_WRAP_SIZE
-- Purpose: These wrap size values only apply to 32-bit BRAM.
---------------------------------------------------------------------------
GEN_32_WRAP_SIZE: if C_AXI_DATA_WIDTH = 32 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 4 bytes (full AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/2 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/4 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_32_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_64_WRAP_SIZE
-- Purpose: These wrap size values only apply to 64-bit BRAM.
---------------------------------------------------------------------------
GEN_64_WRAP_SIZE: if C_AXI_DATA_WIDTH = 64 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 8 bytes (full AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/2 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/4 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/8 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_64_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_128_WRAP_SIZE
-- Purpose: These wrap size values only apply to 128-bit BRAM.
---------------------------------------------------------------------------
GEN_128_WRAP_SIZE: if C_AXI_DATA_WIDTH = 128 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 16 bytes (full AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/2 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/4 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/8 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_128_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_256_WRAP_SIZE
-- Purpose: These wrap size values only apply to 256-bit BRAM.
---------------------------------------------------------------------------
GEN_256_WRAP_SIZE: if C_AXI_DATA_WIDTH = 256 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 32 bytes (full AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/2 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/4 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/8 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_256_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_512_WRAP_SIZE
-- Purpose: These wrap size values only apply to 512-bit BRAM.
---------------------------------------------------------------------------
GEN_512_WRAP_SIZE: if C_AXI_DATA_WIDTH = 512 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 64 bytes (full AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/2 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/4 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/8 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_512_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_1024_WRAP_SIZE
-- Purpose: These wrap size values only apply to 1024-bit BRAM.
---------------------------------------------------------------------------
GEN_1024_WRAP_SIZE: if C_AXI_DATA_WIDTH = 1024 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 128 bytes (full AXI size)
when C_AXI_SIZE_128BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 64 bytes (1/2 AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/4 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/8 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_1024_WRAP_SIZE;
---------------------------------------------------------------------------
-- Early decode to determine size of WRAP transfer
-- Goal to break up long timing path to generate max_wrap_burst signal.
REG_WRAP_TOTAL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wrap_burst_total <= (others => '0');
elsif (bram_addr_ld_en = '1') then
wrap_burst_total <= wrap_burst_total_cmb;
else
wrap_burst_total <= wrap_burst_total;
end if;
end if;
end process REG_WRAP_TOTAL;
---------------------------------------------------------------------------
CHECK_WRAP_MAX : process ( wrap_burst_total,
bram_addr_int,
save_init_bram_addr_ld )
begin
-- Check BRAM address value if max value is reached.
-- Max value is based on burst size/length for operation.
-- Address bits to check vary based on C_S_AXI_DATA_WIDTH and burst size/length.
-- (use signal, wrap_burst_total, based on current WRAP burst size/length/data width).
case wrap_burst_total is
when C_WRAP_SIZE_2 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR) = '1') then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
when C_WRAP_SIZE_4 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR) = "11") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "00";
when C_WRAP_SIZE_8 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR) = "111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "000";
when C_WRAP_SIZE_16 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR) = "1111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "0000";
when others =>
max_wrap_burst <= '0';
bram_addr_ld_wrap(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld;
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
end case;
end process CHECK_WRAP_MAX;
---------------------------------------------------------------------------
-- Move outside of CHECK_WRAP_MAX process.
-- Account for narrow burst operations.
--
-- Currently max_wrap_burst is getting asserted at the first address beat to BRAM
-- that indicates the maximum WRAP burst boundary. Must wait for the completion of the
-- narrow wrap burst counter to assert max_wrap_burst.
--
-- Indicates when narrow burst address counter hits max (all zeros value)
-- narrow_bram_addr_inc_re
max_wrap_burst_mod <= max_wrap_burst when (curr_narrow_burst = '0') else
(max_wrap_burst and narrow_bram_addr_inc_re);
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- wrap_brst.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wrap_brst.vhd
--
-- Description: Create sub module for logic to generate WRAP burst
-- address for rd_chnl and wr_chnl.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 2/7/2011 v1.03a
-- ~~~~~~
-- Remove axi_bram_ctrl_funcs package use.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, wrap_burst_total_cmb,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 3/24/2011 v1.03a
-- ~~~~~~
-- Add specific generate blocks based on C_AXI_DATA_WIDTH to calculate
-- total WRAP burst size for improved FPGA resource utilization.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Clean up code.
-- Re-code wrap_burst_total_cmb process blocks for each data width
-- to improve and catch all false conditions in code coverage analysis.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wrap_brst is
generic (
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_AXI_DATA_WIDTH : integer := 32
-- Width of AXI data bus (in bits)
);
port (
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
curr_axlen : in std_logic_vector(7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector(2 downto 0) := (others => '0');
curr_narrow_burst : in std_logic;
narrow_bram_addr_inc_re : in std_logic;
bram_addr_ld_en : in std_logic;
bram_addr_ld : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_int : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_ld_wrap : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
max_wrap_burst_mod : out std_logic := '0'
);
end entity wrap_brst;
-------------------------------------------------------------------------------
architecture implementation of wrap_brst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Constants for WRAP size decoding to simplify integer represenation.
constant C_WRAP_SIZE_2 : std_logic_vector (2 downto 0) := "001";
constant C_WRAP_SIZE_4 : std_logic_vector (2 downto 0) := "010";
constant C_WRAP_SIZE_8 : std_logic_vector (2 downto 0) := "011";
constant C_WRAP_SIZE_16 : std_logic_vector (2 downto 0) := "100";
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal max_wrap_burst : std_logic := '0';
signal save_init_bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1)
:= (others => '0');
-- signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
-- signal curr_axsize_int : integer := 0;
-- signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
-- Holds burst length/size total (based on width of BRAM width)
-- Max size = max length of burst (256 beats)
-- signal wrap_burst_total_cmb : integer range 0 to 256 := 1; -- Max 256 (= 32768d / 128 bytes)
-- signal wrap_burst_total : integer range 0 to 256 := 1;
signal wrap_burst_total_cmb : std_logic_vector (2 downto 0) := (others => '0');
signal wrap_burst_total : std_logic_vector (2 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1 : unsigned (7 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Modify counter size based on size of current write burst operation
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Based on AxSIZE and AxLEN
-- To minimize muxing on initial load of counter value
-- Detect on WRAP burst types, when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value.
-- Save initial load address value.
REG_INIT_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
save_init_bram_addr_ld <= (others => '0');
elsif (bram_addr_ld_en = '1') then
save_init_bram_addr_ld <= bram_addr_ld(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
else
save_init_bram_addr_ld <= save_init_bram_addr_ld;
end if;
end if;
end process REG_INIT_BRAM_ADDR;
---------------------------------------------------------------------------
-- v1.03a
-- Calculate AXI size (integer)
-- curr_axsize_unsigned <= unsigned (curr_axsize);
-- curr_axsize_int <= to_integer (curr_axsize_unsigned);
-- Calculate AXI length (integer)
-- curr_axlen_unsigned <= unsigned (curr_axlen);
-- curr_axlen_unsigned_plus1 <= curr_axlen_unsigned + "00000001";
-- WRAP = size * length (based on BRAM data width in bytes)
--
-- Original multiply function:
-- wrap_burst_total_cmb <= (size_bytes_int * len_int) / C_AXI_DATA_WIDTH_BYTES;
-- For XST, modify integer multiply function to improve timing.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
-- LEN_LSHIFT: process (curr_axlen_unsigned_plus1, curr_axsize_int)
-- begin
--
-- for i in C_MAX_LSHIFT_SIZE downto 0 loop
--
-- if (i >= curr_axsize_int + 8) then
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- elsif (i >= curr_axsize_int) then
-- curr_axlen_unsigned_plus1_lshift (i) <= curr_axlen_unsigned_plus1 (i - curr_axsize_int);
-- else
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- end if;
--
-- end loop;
--
-- end process LEN_LSHIFT;
-- Final signal assignment for XST & timing improvements.
-- wrap_burst_total_cmb <= to_integer (curr_axlen_unsigned_plus1_lshift) / C_AXI_DATA_WIDTH_BYTES;
---------------------------------------------------------------------------
-- v1.03a
-- For best FPGA resource implementation, hard code the generation of
-- WRAP burst size based on each C_AXI_DATA_WIDTH possibility.
---------------------------------------------------------------------------
-- Generate: GEN_32_WRAP_SIZE
-- Purpose: These wrap size values only apply to 32-bit BRAM.
---------------------------------------------------------------------------
GEN_32_WRAP_SIZE: if C_AXI_DATA_WIDTH = 32 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 4 bytes (full AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/2 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/4 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_32_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_64_WRAP_SIZE
-- Purpose: These wrap size values only apply to 64-bit BRAM.
---------------------------------------------------------------------------
GEN_64_WRAP_SIZE: if C_AXI_DATA_WIDTH = 64 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 8 bytes (full AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/2 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/4 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/8 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_64_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_128_WRAP_SIZE
-- Purpose: These wrap size values only apply to 128-bit BRAM.
---------------------------------------------------------------------------
GEN_128_WRAP_SIZE: if C_AXI_DATA_WIDTH = 128 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 16 bytes (full AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/2 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/4 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/8 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_128_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_256_WRAP_SIZE
-- Purpose: These wrap size values only apply to 256-bit BRAM.
---------------------------------------------------------------------------
GEN_256_WRAP_SIZE: if C_AXI_DATA_WIDTH = 256 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 32 bytes (full AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/2 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/4 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/8 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_256_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_512_WRAP_SIZE
-- Purpose: These wrap size values only apply to 512-bit BRAM.
---------------------------------------------------------------------------
GEN_512_WRAP_SIZE: if C_AXI_DATA_WIDTH = 512 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 64 bytes (full AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/2 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/4 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/8 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_512_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_1024_WRAP_SIZE
-- Purpose: These wrap size values only apply to 1024-bit BRAM.
---------------------------------------------------------------------------
GEN_1024_WRAP_SIZE: if C_AXI_DATA_WIDTH = 1024 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 128 bytes (full AXI size)
when C_AXI_SIZE_128BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 64 bytes (1/2 AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/4 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/8 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_1024_WRAP_SIZE;
---------------------------------------------------------------------------
-- Early decode to determine size of WRAP transfer
-- Goal to break up long timing path to generate max_wrap_burst signal.
REG_WRAP_TOTAL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wrap_burst_total <= (others => '0');
elsif (bram_addr_ld_en = '1') then
wrap_burst_total <= wrap_burst_total_cmb;
else
wrap_burst_total <= wrap_burst_total;
end if;
end if;
end process REG_WRAP_TOTAL;
---------------------------------------------------------------------------
CHECK_WRAP_MAX : process ( wrap_burst_total,
bram_addr_int,
save_init_bram_addr_ld )
begin
-- Check BRAM address value if max value is reached.
-- Max value is based on burst size/length for operation.
-- Address bits to check vary based on C_S_AXI_DATA_WIDTH and burst size/length.
-- (use signal, wrap_burst_total, based on current WRAP burst size/length/data width).
case wrap_burst_total is
when C_WRAP_SIZE_2 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR) = '1') then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
when C_WRAP_SIZE_4 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR) = "11") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "00";
when C_WRAP_SIZE_8 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR) = "111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "000";
when C_WRAP_SIZE_16 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR) = "1111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "0000";
when others =>
max_wrap_burst <= '0';
bram_addr_ld_wrap(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld;
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
end case;
end process CHECK_WRAP_MAX;
---------------------------------------------------------------------------
-- Move outside of CHECK_WRAP_MAX process.
-- Account for narrow burst operations.
--
-- Currently max_wrap_burst is getting asserted at the first address beat to BRAM
-- that indicates the maximum WRAP burst boundary. Must wait for the completion of the
-- narrow wrap burst counter to assert max_wrap_burst.
--
-- Indicates when narrow burst address counter hits max (all zeros value)
-- narrow_bram_addr_inc_re
max_wrap_burst_mod <= max_wrap_burst when (curr_narrow_burst = '0') else
(max_wrap_burst and narrow_bram_addr_inc_re);
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- wrap_brst.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wrap_brst.vhd
--
-- Description: Create sub module for logic to generate WRAP burst
-- address for rd_chnl and wr_chnl.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 2/7/2011 v1.03a
-- ~~~~~~
-- Remove axi_bram_ctrl_funcs package use.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, wrap_burst_total_cmb,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 3/24/2011 v1.03a
-- ~~~~~~
-- Add specific generate blocks based on C_AXI_DATA_WIDTH to calculate
-- total WRAP burst size for improved FPGA resource utilization.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Clean up code.
-- Re-code wrap_burst_total_cmb process blocks for each data width
-- to improve and catch all false conditions in code coverage analysis.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wrap_brst is
generic (
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_AXI_DATA_WIDTH : integer := 32
-- Width of AXI data bus (in bits)
);
port (
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
curr_axlen : in std_logic_vector(7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector(2 downto 0) := (others => '0');
curr_narrow_burst : in std_logic;
narrow_bram_addr_inc_re : in std_logic;
bram_addr_ld_en : in std_logic;
bram_addr_ld : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_int : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_ld_wrap : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
max_wrap_burst_mod : out std_logic := '0'
);
end entity wrap_brst;
-------------------------------------------------------------------------------
architecture implementation of wrap_brst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Constants for WRAP size decoding to simplify integer represenation.
constant C_WRAP_SIZE_2 : std_logic_vector (2 downto 0) := "001";
constant C_WRAP_SIZE_4 : std_logic_vector (2 downto 0) := "010";
constant C_WRAP_SIZE_8 : std_logic_vector (2 downto 0) := "011";
constant C_WRAP_SIZE_16 : std_logic_vector (2 downto 0) := "100";
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal max_wrap_burst : std_logic := '0';
signal save_init_bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1)
:= (others => '0');
-- signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
-- signal curr_axsize_int : integer := 0;
-- signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
-- Holds burst length/size total (based on width of BRAM width)
-- Max size = max length of burst (256 beats)
-- signal wrap_burst_total_cmb : integer range 0 to 256 := 1; -- Max 256 (= 32768d / 128 bytes)
-- signal wrap_burst_total : integer range 0 to 256 := 1;
signal wrap_burst_total_cmb : std_logic_vector (2 downto 0) := (others => '0');
signal wrap_burst_total : std_logic_vector (2 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1 : unsigned (7 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Modify counter size based on size of current write burst operation
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Based on AxSIZE and AxLEN
-- To minimize muxing on initial load of counter value
-- Detect on WRAP burst types, when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value.
-- Save initial load address value.
REG_INIT_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
save_init_bram_addr_ld <= (others => '0');
elsif (bram_addr_ld_en = '1') then
save_init_bram_addr_ld <= bram_addr_ld(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
else
save_init_bram_addr_ld <= save_init_bram_addr_ld;
end if;
end if;
end process REG_INIT_BRAM_ADDR;
---------------------------------------------------------------------------
-- v1.03a
-- Calculate AXI size (integer)
-- curr_axsize_unsigned <= unsigned (curr_axsize);
-- curr_axsize_int <= to_integer (curr_axsize_unsigned);
-- Calculate AXI length (integer)
-- curr_axlen_unsigned <= unsigned (curr_axlen);
-- curr_axlen_unsigned_plus1 <= curr_axlen_unsigned + "00000001";
-- WRAP = size * length (based on BRAM data width in bytes)
--
-- Original multiply function:
-- wrap_burst_total_cmb <= (size_bytes_int * len_int) / C_AXI_DATA_WIDTH_BYTES;
-- For XST, modify integer multiply function to improve timing.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
-- LEN_LSHIFT: process (curr_axlen_unsigned_plus1, curr_axsize_int)
-- begin
--
-- for i in C_MAX_LSHIFT_SIZE downto 0 loop
--
-- if (i >= curr_axsize_int + 8) then
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- elsif (i >= curr_axsize_int) then
-- curr_axlen_unsigned_plus1_lshift (i) <= curr_axlen_unsigned_plus1 (i - curr_axsize_int);
-- else
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- end if;
--
-- end loop;
--
-- end process LEN_LSHIFT;
-- Final signal assignment for XST & timing improvements.
-- wrap_burst_total_cmb <= to_integer (curr_axlen_unsigned_plus1_lshift) / C_AXI_DATA_WIDTH_BYTES;
---------------------------------------------------------------------------
-- v1.03a
-- For best FPGA resource implementation, hard code the generation of
-- WRAP burst size based on each C_AXI_DATA_WIDTH possibility.
---------------------------------------------------------------------------
-- Generate: GEN_32_WRAP_SIZE
-- Purpose: These wrap size values only apply to 32-bit BRAM.
---------------------------------------------------------------------------
GEN_32_WRAP_SIZE: if C_AXI_DATA_WIDTH = 32 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 4 bytes (full AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/2 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/4 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_32_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_64_WRAP_SIZE
-- Purpose: These wrap size values only apply to 64-bit BRAM.
---------------------------------------------------------------------------
GEN_64_WRAP_SIZE: if C_AXI_DATA_WIDTH = 64 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 8 bytes (full AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/2 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/4 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/8 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_64_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_128_WRAP_SIZE
-- Purpose: These wrap size values only apply to 128-bit BRAM.
---------------------------------------------------------------------------
GEN_128_WRAP_SIZE: if C_AXI_DATA_WIDTH = 128 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 16 bytes (full AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/2 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/4 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/8 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_128_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_256_WRAP_SIZE
-- Purpose: These wrap size values only apply to 256-bit BRAM.
---------------------------------------------------------------------------
GEN_256_WRAP_SIZE: if C_AXI_DATA_WIDTH = 256 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 32 bytes (full AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/2 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/4 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/8 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_256_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_512_WRAP_SIZE
-- Purpose: These wrap size values only apply to 512-bit BRAM.
---------------------------------------------------------------------------
GEN_512_WRAP_SIZE: if C_AXI_DATA_WIDTH = 512 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 64 bytes (full AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/2 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/4 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/8 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_512_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_1024_WRAP_SIZE
-- Purpose: These wrap size values only apply to 1024-bit BRAM.
---------------------------------------------------------------------------
GEN_1024_WRAP_SIZE: if C_AXI_DATA_WIDTH = 1024 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 128 bytes (full AXI size)
when C_AXI_SIZE_128BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 64 bytes (1/2 AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/4 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/8 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_1024_WRAP_SIZE;
---------------------------------------------------------------------------
-- Early decode to determine size of WRAP transfer
-- Goal to break up long timing path to generate max_wrap_burst signal.
REG_WRAP_TOTAL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wrap_burst_total <= (others => '0');
elsif (bram_addr_ld_en = '1') then
wrap_burst_total <= wrap_burst_total_cmb;
else
wrap_burst_total <= wrap_burst_total;
end if;
end if;
end process REG_WRAP_TOTAL;
---------------------------------------------------------------------------
CHECK_WRAP_MAX : process ( wrap_burst_total,
bram_addr_int,
save_init_bram_addr_ld )
begin
-- Check BRAM address value if max value is reached.
-- Max value is based on burst size/length for operation.
-- Address bits to check vary based on C_S_AXI_DATA_WIDTH and burst size/length.
-- (use signal, wrap_burst_total, based on current WRAP burst size/length/data width).
case wrap_burst_total is
when C_WRAP_SIZE_2 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR) = '1') then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
when C_WRAP_SIZE_4 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR) = "11") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "00";
when C_WRAP_SIZE_8 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR) = "111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "000";
when C_WRAP_SIZE_16 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR) = "1111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "0000";
when others =>
max_wrap_burst <= '0';
bram_addr_ld_wrap(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld;
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
end case;
end process CHECK_WRAP_MAX;
---------------------------------------------------------------------------
-- Move outside of CHECK_WRAP_MAX process.
-- Account for narrow burst operations.
--
-- Currently max_wrap_burst is getting asserted at the first address beat to BRAM
-- that indicates the maximum WRAP burst boundary. Must wait for the completion of the
-- narrow wrap burst counter to assert max_wrap_burst.
--
-- Indicates when narrow burst address counter hits max (all zeros value)
-- narrow_bram_addr_inc_re
max_wrap_burst_mod <= max_wrap_burst when (curr_narrow_burst = '0') else
(max_wrap_burst and narrow_bram_addr_inc_re);
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- wrap_brst.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wrap_brst.vhd
--
-- Description: Create sub module for logic to generate WRAP burst
-- address for rd_chnl and wr_chnl.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 2/7/2011 v1.03a
-- ~~~~~~
-- Remove axi_bram_ctrl_funcs package use.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, wrap_burst_total_cmb,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 3/24/2011 v1.03a
-- ~~~~~~
-- Add specific generate blocks based on C_AXI_DATA_WIDTH to calculate
-- total WRAP burst size for improved FPGA resource utilization.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Clean up code.
-- Re-code wrap_burst_total_cmb process blocks for each data width
-- to improve and catch all false conditions in code coverage analysis.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wrap_brst is
generic (
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_AXI_DATA_WIDTH : integer := 32
-- Width of AXI data bus (in bits)
);
port (
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
curr_axlen : in std_logic_vector(7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector(2 downto 0) := (others => '0');
curr_narrow_burst : in std_logic;
narrow_bram_addr_inc_re : in std_logic;
bram_addr_ld_en : in std_logic;
bram_addr_ld : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_int : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_ld_wrap : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
max_wrap_burst_mod : out std_logic := '0'
);
end entity wrap_brst;
-------------------------------------------------------------------------------
architecture implementation of wrap_brst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Constants for WRAP size decoding to simplify integer represenation.
constant C_WRAP_SIZE_2 : std_logic_vector (2 downto 0) := "001";
constant C_WRAP_SIZE_4 : std_logic_vector (2 downto 0) := "010";
constant C_WRAP_SIZE_8 : std_logic_vector (2 downto 0) := "011";
constant C_WRAP_SIZE_16 : std_logic_vector (2 downto 0) := "100";
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal max_wrap_burst : std_logic := '0';
signal save_init_bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1)
:= (others => '0');
-- signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
-- signal curr_axsize_int : integer := 0;
-- signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
-- Holds burst length/size total (based on width of BRAM width)
-- Max size = max length of burst (256 beats)
-- signal wrap_burst_total_cmb : integer range 0 to 256 := 1; -- Max 256 (= 32768d / 128 bytes)
-- signal wrap_burst_total : integer range 0 to 256 := 1;
signal wrap_burst_total_cmb : std_logic_vector (2 downto 0) := (others => '0');
signal wrap_burst_total : std_logic_vector (2 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1 : unsigned (7 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Modify counter size based on size of current write burst operation
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Based on AxSIZE and AxLEN
-- To minimize muxing on initial load of counter value
-- Detect on WRAP burst types, when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value.
-- Save initial load address value.
REG_INIT_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
save_init_bram_addr_ld <= (others => '0');
elsif (bram_addr_ld_en = '1') then
save_init_bram_addr_ld <= bram_addr_ld(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
else
save_init_bram_addr_ld <= save_init_bram_addr_ld;
end if;
end if;
end process REG_INIT_BRAM_ADDR;
---------------------------------------------------------------------------
-- v1.03a
-- Calculate AXI size (integer)
-- curr_axsize_unsigned <= unsigned (curr_axsize);
-- curr_axsize_int <= to_integer (curr_axsize_unsigned);
-- Calculate AXI length (integer)
-- curr_axlen_unsigned <= unsigned (curr_axlen);
-- curr_axlen_unsigned_plus1 <= curr_axlen_unsigned + "00000001";
-- WRAP = size * length (based on BRAM data width in bytes)
--
-- Original multiply function:
-- wrap_burst_total_cmb <= (size_bytes_int * len_int) / C_AXI_DATA_WIDTH_BYTES;
-- For XST, modify integer multiply function to improve timing.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
-- LEN_LSHIFT: process (curr_axlen_unsigned_plus1, curr_axsize_int)
-- begin
--
-- for i in C_MAX_LSHIFT_SIZE downto 0 loop
--
-- if (i >= curr_axsize_int + 8) then
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- elsif (i >= curr_axsize_int) then
-- curr_axlen_unsigned_plus1_lshift (i) <= curr_axlen_unsigned_plus1 (i - curr_axsize_int);
-- else
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- end if;
--
-- end loop;
--
-- end process LEN_LSHIFT;
-- Final signal assignment for XST & timing improvements.
-- wrap_burst_total_cmb <= to_integer (curr_axlen_unsigned_plus1_lshift) / C_AXI_DATA_WIDTH_BYTES;
---------------------------------------------------------------------------
-- v1.03a
-- For best FPGA resource implementation, hard code the generation of
-- WRAP burst size based on each C_AXI_DATA_WIDTH possibility.
---------------------------------------------------------------------------
-- Generate: GEN_32_WRAP_SIZE
-- Purpose: These wrap size values only apply to 32-bit BRAM.
---------------------------------------------------------------------------
GEN_32_WRAP_SIZE: if C_AXI_DATA_WIDTH = 32 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 4 bytes (full AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/2 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/4 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_32_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_64_WRAP_SIZE
-- Purpose: These wrap size values only apply to 64-bit BRAM.
---------------------------------------------------------------------------
GEN_64_WRAP_SIZE: if C_AXI_DATA_WIDTH = 64 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 8 bytes (full AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/2 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/4 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/8 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_64_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_128_WRAP_SIZE
-- Purpose: These wrap size values only apply to 128-bit BRAM.
---------------------------------------------------------------------------
GEN_128_WRAP_SIZE: if C_AXI_DATA_WIDTH = 128 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 16 bytes (full AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/2 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/4 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/8 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_128_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_256_WRAP_SIZE
-- Purpose: These wrap size values only apply to 256-bit BRAM.
---------------------------------------------------------------------------
GEN_256_WRAP_SIZE: if C_AXI_DATA_WIDTH = 256 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 32 bytes (full AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/2 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/4 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/8 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_256_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_512_WRAP_SIZE
-- Purpose: These wrap size values only apply to 512-bit BRAM.
---------------------------------------------------------------------------
GEN_512_WRAP_SIZE: if C_AXI_DATA_WIDTH = 512 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 64 bytes (full AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/2 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/4 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/8 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_512_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_1024_WRAP_SIZE
-- Purpose: These wrap size values only apply to 1024-bit BRAM.
---------------------------------------------------------------------------
GEN_1024_WRAP_SIZE: if C_AXI_DATA_WIDTH = 1024 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 128 bytes (full AXI size)
when C_AXI_SIZE_128BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 64 bytes (1/2 AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/4 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/8 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_1024_WRAP_SIZE;
---------------------------------------------------------------------------
-- Early decode to determine size of WRAP transfer
-- Goal to break up long timing path to generate max_wrap_burst signal.
REG_WRAP_TOTAL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wrap_burst_total <= (others => '0');
elsif (bram_addr_ld_en = '1') then
wrap_burst_total <= wrap_burst_total_cmb;
else
wrap_burst_total <= wrap_burst_total;
end if;
end if;
end process REG_WRAP_TOTAL;
---------------------------------------------------------------------------
CHECK_WRAP_MAX : process ( wrap_burst_total,
bram_addr_int,
save_init_bram_addr_ld )
begin
-- Check BRAM address value if max value is reached.
-- Max value is based on burst size/length for operation.
-- Address bits to check vary based on C_S_AXI_DATA_WIDTH and burst size/length.
-- (use signal, wrap_burst_total, based on current WRAP burst size/length/data width).
case wrap_burst_total is
when C_WRAP_SIZE_2 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR) = '1') then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
when C_WRAP_SIZE_4 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR) = "11") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "00";
when C_WRAP_SIZE_8 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR) = "111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "000";
when C_WRAP_SIZE_16 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR) = "1111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "0000";
when others =>
max_wrap_burst <= '0';
bram_addr_ld_wrap(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld;
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
end case;
end process CHECK_WRAP_MAX;
---------------------------------------------------------------------------
-- Move outside of CHECK_WRAP_MAX process.
-- Account for narrow burst operations.
--
-- Currently max_wrap_burst is getting asserted at the first address beat to BRAM
-- that indicates the maximum WRAP burst boundary. Must wait for the completion of the
-- narrow wrap burst counter to assert max_wrap_burst.
--
-- Indicates when narrow burst address counter hits max (all zeros value)
-- narrow_bram_addr_inc_re
max_wrap_burst_mod <= max_wrap_burst when (curr_narrow_burst = '0') else
(max_wrap_burst and narrow_bram_addr_inc_re);
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- wrap_brst.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wrap_brst.vhd
--
-- Description: Create sub module for logic to generate WRAP burst
-- address for rd_chnl and wr_chnl.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 2/7/2011 v1.03a
-- ~~~~~~
-- Remove axi_bram_ctrl_funcs package use.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, wrap_burst_total_cmb,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 3/24/2011 v1.03a
-- ~~~~~~
-- Add specific generate blocks based on C_AXI_DATA_WIDTH to calculate
-- total WRAP burst size for improved FPGA resource utilization.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Clean up code.
-- Re-code wrap_burst_total_cmb process blocks for each data width
-- to improve and catch all false conditions in code coverage analysis.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wrap_brst is
generic (
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_AXI_DATA_WIDTH : integer := 32
-- Width of AXI data bus (in bits)
);
port (
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
curr_axlen : in std_logic_vector(7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector(2 downto 0) := (others => '0');
curr_narrow_burst : in std_logic;
narrow_bram_addr_inc_re : in std_logic;
bram_addr_ld_en : in std_logic;
bram_addr_ld : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_int : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_ld_wrap : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
max_wrap_burst_mod : out std_logic := '0'
);
end entity wrap_brst;
-------------------------------------------------------------------------------
architecture implementation of wrap_brst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Constants for WRAP size decoding to simplify integer represenation.
constant C_WRAP_SIZE_2 : std_logic_vector (2 downto 0) := "001";
constant C_WRAP_SIZE_4 : std_logic_vector (2 downto 0) := "010";
constant C_WRAP_SIZE_8 : std_logic_vector (2 downto 0) := "011";
constant C_WRAP_SIZE_16 : std_logic_vector (2 downto 0) := "100";
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal max_wrap_burst : std_logic := '0';
signal save_init_bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1)
:= (others => '0');
-- signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
-- signal curr_axsize_int : integer := 0;
-- signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
-- Holds burst length/size total (based on width of BRAM width)
-- Max size = max length of burst (256 beats)
-- signal wrap_burst_total_cmb : integer range 0 to 256 := 1; -- Max 256 (= 32768d / 128 bytes)
-- signal wrap_burst_total : integer range 0 to 256 := 1;
signal wrap_burst_total_cmb : std_logic_vector (2 downto 0) := (others => '0');
signal wrap_burst_total : std_logic_vector (2 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1 : unsigned (7 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Modify counter size based on size of current write burst operation
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Based on AxSIZE and AxLEN
-- To minimize muxing on initial load of counter value
-- Detect on WRAP burst types, when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value.
-- Save initial load address value.
REG_INIT_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
save_init_bram_addr_ld <= (others => '0');
elsif (bram_addr_ld_en = '1') then
save_init_bram_addr_ld <= bram_addr_ld(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
else
save_init_bram_addr_ld <= save_init_bram_addr_ld;
end if;
end if;
end process REG_INIT_BRAM_ADDR;
---------------------------------------------------------------------------
-- v1.03a
-- Calculate AXI size (integer)
-- curr_axsize_unsigned <= unsigned (curr_axsize);
-- curr_axsize_int <= to_integer (curr_axsize_unsigned);
-- Calculate AXI length (integer)
-- curr_axlen_unsigned <= unsigned (curr_axlen);
-- curr_axlen_unsigned_plus1 <= curr_axlen_unsigned + "00000001";
-- WRAP = size * length (based on BRAM data width in bytes)
--
-- Original multiply function:
-- wrap_burst_total_cmb <= (size_bytes_int * len_int) / C_AXI_DATA_WIDTH_BYTES;
-- For XST, modify integer multiply function to improve timing.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
-- LEN_LSHIFT: process (curr_axlen_unsigned_plus1, curr_axsize_int)
-- begin
--
-- for i in C_MAX_LSHIFT_SIZE downto 0 loop
--
-- if (i >= curr_axsize_int + 8) then
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- elsif (i >= curr_axsize_int) then
-- curr_axlen_unsigned_plus1_lshift (i) <= curr_axlen_unsigned_plus1 (i - curr_axsize_int);
-- else
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- end if;
--
-- end loop;
--
-- end process LEN_LSHIFT;
-- Final signal assignment for XST & timing improvements.
-- wrap_burst_total_cmb <= to_integer (curr_axlen_unsigned_plus1_lshift) / C_AXI_DATA_WIDTH_BYTES;
---------------------------------------------------------------------------
-- v1.03a
-- For best FPGA resource implementation, hard code the generation of
-- WRAP burst size based on each C_AXI_DATA_WIDTH possibility.
---------------------------------------------------------------------------
-- Generate: GEN_32_WRAP_SIZE
-- Purpose: These wrap size values only apply to 32-bit BRAM.
---------------------------------------------------------------------------
GEN_32_WRAP_SIZE: if C_AXI_DATA_WIDTH = 32 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 4 bytes (full AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/2 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/4 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_32_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_64_WRAP_SIZE
-- Purpose: These wrap size values only apply to 64-bit BRAM.
---------------------------------------------------------------------------
GEN_64_WRAP_SIZE: if C_AXI_DATA_WIDTH = 64 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 8 bytes (full AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/2 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/4 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/8 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_64_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_128_WRAP_SIZE
-- Purpose: These wrap size values only apply to 128-bit BRAM.
---------------------------------------------------------------------------
GEN_128_WRAP_SIZE: if C_AXI_DATA_WIDTH = 128 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 16 bytes (full AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/2 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/4 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/8 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_128_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_256_WRAP_SIZE
-- Purpose: These wrap size values only apply to 256-bit BRAM.
---------------------------------------------------------------------------
GEN_256_WRAP_SIZE: if C_AXI_DATA_WIDTH = 256 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 32 bytes (full AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/2 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/4 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/8 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_256_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_512_WRAP_SIZE
-- Purpose: These wrap size values only apply to 512-bit BRAM.
---------------------------------------------------------------------------
GEN_512_WRAP_SIZE: if C_AXI_DATA_WIDTH = 512 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 64 bytes (full AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/2 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/4 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/8 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_512_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_1024_WRAP_SIZE
-- Purpose: These wrap size values only apply to 1024-bit BRAM.
---------------------------------------------------------------------------
GEN_1024_WRAP_SIZE: if C_AXI_DATA_WIDTH = 1024 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 128 bytes (full AXI size)
when C_AXI_SIZE_128BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 64 bytes (1/2 AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/4 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/8 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_1024_WRAP_SIZE;
---------------------------------------------------------------------------
-- Early decode to determine size of WRAP transfer
-- Goal to break up long timing path to generate max_wrap_burst signal.
REG_WRAP_TOTAL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wrap_burst_total <= (others => '0');
elsif (bram_addr_ld_en = '1') then
wrap_burst_total <= wrap_burst_total_cmb;
else
wrap_burst_total <= wrap_burst_total;
end if;
end if;
end process REG_WRAP_TOTAL;
---------------------------------------------------------------------------
CHECK_WRAP_MAX : process ( wrap_burst_total,
bram_addr_int,
save_init_bram_addr_ld )
begin
-- Check BRAM address value if max value is reached.
-- Max value is based on burst size/length for operation.
-- Address bits to check vary based on C_S_AXI_DATA_WIDTH and burst size/length.
-- (use signal, wrap_burst_total, based on current WRAP burst size/length/data width).
case wrap_burst_total is
when C_WRAP_SIZE_2 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR) = '1') then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
when C_WRAP_SIZE_4 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR) = "11") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "00";
when C_WRAP_SIZE_8 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR) = "111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "000";
when C_WRAP_SIZE_16 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR) = "1111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "0000";
when others =>
max_wrap_burst <= '0';
bram_addr_ld_wrap(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld;
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
end case;
end process CHECK_WRAP_MAX;
---------------------------------------------------------------------------
-- Move outside of CHECK_WRAP_MAX process.
-- Account for narrow burst operations.
--
-- Currently max_wrap_burst is getting asserted at the first address beat to BRAM
-- that indicates the maximum WRAP burst boundary. Must wait for the completion of the
-- narrow wrap burst counter to assert max_wrap_burst.
--
-- Indicates when narrow burst address counter hits max (all zeros value)
-- narrow_bram_addr_inc_re
max_wrap_burst_mod <= max_wrap_burst when (curr_narrow_burst = '0') else
(max_wrap_burst and narrow_bram_addr_inc_re);
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- wrap_brst.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wrap_brst.vhd
--
-- Description: Create sub module for logic to generate WRAP burst
-- address for rd_chnl and wr_chnl.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 2/7/2011 v1.03a
-- ~~~~~~
-- Remove axi_bram_ctrl_funcs package use.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, wrap_burst_total_cmb,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 3/24/2011 v1.03a
-- ~~~~~~
-- Add specific generate blocks based on C_AXI_DATA_WIDTH to calculate
-- total WRAP burst size for improved FPGA resource utilization.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Clean up code.
-- Re-code wrap_burst_total_cmb process blocks for each data width
-- to improve and catch all false conditions in code coverage analysis.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wrap_brst is
generic (
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_AXI_DATA_WIDTH : integer := 32
-- Width of AXI data bus (in bits)
);
port (
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
curr_axlen : in std_logic_vector(7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector(2 downto 0) := (others => '0');
curr_narrow_burst : in std_logic;
narrow_bram_addr_inc_re : in std_logic;
bram_addr_ld_en : in std_logic;
bram_addr_ld : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_int : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_ld_wrap : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
max_wrap_burst_mod : out std_logic := '0'
);
end entity wrap_brst;
-------------------------------------------------------------------------------
architecture implementation of wrap_brst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Constants for WRAP size decoding to simplify integer represenation.
constant C_WRAP_SIZE_2 : std_logic_vector (2 downto 0) := "001";
constant C_WRAP_SIZE_4 : std_logic_vector (2 downto 0) := "010";
constant C_WRAP_SIZE_8 : std_logic_vector (2 downto 0) := "011";
constant C_WRAP_SIZE_16 : std_logic_vector (2 downto 0) := "100";
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal max_wrap_burst : std_logic := '0';
signal save_init_bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1)
:= (others => '0');
-- signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
-- signal curr_axsize_int : integer := 0;
-- signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
-- Holds burst length/size total (based on width of BRAM width)
-- Max size = max length of burst (256 beats)
-- signal wrap_burst_total_cmb : integer range 0 to 256 := 1; -- Max 256 (= 32768d / 128 bytes)
-- signal wrap_burst_total : integer range 0 to 256 := 1;
signal wrap_burst_total_cmb : std_logic_vector (2 downto 0) := (others => '0');
signal wrap_burst_total : std_logic_vector (2 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1 : unsigned (7 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Modify counter size based on size of current write burst operation
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Based on AxSIZE and AxLEN
-- To minimize muxing on initial load of counter value
-- Detect on WRAP burst types, when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value.
-- Save initial load address value.
REG_INIT_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
save_init_bram_addr_ld <= (others => '0');
elsif (bram_addr_ld_en = '1') then
save_init_bram_addr_ld <= bram_addr_ld(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
else
save_init_bram_addr_ld <= save_init_bram_addr_ld;
end if;
end if;
end process REG_INIT_BRAM_ADDR;
---------------------------------------------------------------------------
-- v1.03a
-- Calculate AXI size (integer)
-- curr_axsize_unsigned <= unsigned (curr_axsize);
-- curr_axsize_int <= to_integer (curr_axsize_unsigned);
-- Calculate AXI length (integer)
-- curr_axlen_unsigned <= unsigned (curr_axlen);
-- curr_axlen_unsigned_plus1 <= curr_axlen_unsigned + "00000001";
-- WRAP = size * length (based on BRAM data width in bytes)
--
-- Original multiply function:
-- wrap_burst_total_cmb <= (size_bytes_int * len_int) / C_AXI_DATA_WIDTH_BYTES;
-- For XST, modify integer multiply function to improve timing.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
-- LEN_LSHIFT: process (curr_axlen_unsigned_plus1, curr_axsize_int)
-- begin
--
-- for i in C_MAX_LSHIFT_SIZE downto 0 loop
--
-- if (i >= curr_axsize_int + 8) then
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- elsif (i >= curr_axsize_int) then
-- curr_axlen_unsigned_plus1_lshift (i) <= curr_axlen_unsigned_plus1 (i - curr_axsize_int);
-- else
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- end if;
--
-- end loop;
--
-- end process LEN_LSHIFT;
-- Final signal assignment for XST & timing improvements.
-- wrap_burst_total_cmb <= to_integer (curr_axlen_unsigned_plus1_lshift) / C_AXI_DATA_WIDTH_BYTES;
---------------------------------------------------------------------------
-- v1.03a
-- For best FPGA resource implementation, hard code the generation of
-- WRAP burst size based on each C_AXI_DATA_WIDTH possibility.
---------------------------------------------------------------------------
-- Generate: GEN_32_WRAP_SIZE
-- Purpose: These wrap size values only apply to 32-bit BRAM.
---------------------------------------------------------------------------
GEN_32_WRAP_SIZE: if C_AXI_DATA_WIDTH = 32 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 4 bytes (full AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/2 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/4 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_32_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_64_WRAP_SIZE
-- Purpose: These wrap size values only apply to 64-bit BRAM.
---------------------------------------------------------------------------
GEN_64_WRAP_SIZE: if C_AXI_DATA_WIDTH = 64 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 8 bytes (full AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/2 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/4 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/8 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_64_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_128_WRAP_SIZE
-- Purpose: These wrap size values only apply to 128-bit BRAM.
---------------------------------------------------------------------------
GEN_128_WRAP_SIZE: if C_AXI_DATA_WIDTH = 128 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 16 bytes (full AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/2 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/4 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/8 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_128_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_256_WRAP_SIZE
-- Purpose: These wrap size values only apply to 256-bit BRAM.
---------------------------------------------------------------------------
GEN_256_WRAP_SIZE: if C_AXI_DATA_WIDTH = 256 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 32 bytes (full AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/2 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/4 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/8 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_256_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_512_WRAP_SIZE
-- Purpose: These wrap size values only apply to 512-bit BRAM.
---------------------------------------------------------------------------
GEN_512_WRAP_SIZE: if C_AXI_DATA_WIDTH = 512 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 64 bytes (full AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/2 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/4 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/8 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_512_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_1024_WRAP_SIZE
-- Purpose: These wrap size values only apply to 1024-bit BRAM.
---------------------------------------------------------------------------
GEN_1024_WRAP_SIZE: if C_AXI_DATA_WIDTH = 1024 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 128 bytes (full AXI size)
when C_AXI_SIZE_128BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 64 bytes (1/2 AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/4 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/8 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_1024_WRAP_SIZE;
---------------------------------------------------------------------------
-- Early decode to determine size of WRAP transfer
-- Goal to break up long timing path to generate max_wrap_burst signal.
REG_WRAP_TOTAL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wrap_burst_total <= (others => '0');
elsif (bram_addr_ld_en = '1') then
wrap_burst_total <= wrap_burst_total_cmb;
else
wrap_burst_total <= wrap_burst_total;
end if;
end if;
end process REG_WRAP_TOTAL;
---------------------------------------------------------------------------
CHECK_WRAP_MAX : process ( wrap_burst_total,
bram_addr_int,
save_init_bram_addr_ld )
begin
-- Check BRAM address value if max value is reached.
-- Max value is based on burst size/length for operation.
-- Address bits to check vary based on C_S_AXI_DATA_WIDTH and burst size/length.
-- (use signal, wrap_burst_total, based on current WRAP burst size/length/data width).
case wrap_burst_total is
when C_WRAP_SIZE_2 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR) = '1') then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
when C_WRAP_SIZE_4 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR) = "11") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "00";
when C_WRAP_SIZE_8 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR) = "111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "000";
when C_WRAP_SIZE_16 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR) = "1111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "0000";
when others =>
max_wrap_burst <= '0';
bram_addr_ld_wrap(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld;
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
end case;
end process CHECK_WRAP_MAX;
---------------------------------------------------------------------------
-- Move outside of CHECK_WRAP_MAX process.
-- Account for narrow burst operations.
--
-- Currently max_wrap_burst is getting asserted at the first address beat to BRAM
-- that indicates the maximum WRAP burst boundary. Must wait for the completion of the
-- narrow wrap burst counter to assert max_wrap_burst.
--
-- Indicates when narrow burst address counter hits max (all zeros value)
-- narrow_bram_addr_inc_re
max_wrap_burst_mod <= max_wrap_burst when (curr_narrow_burst = '0') else
(max_wrap_burst and narrow_bram_addr_inc_re);
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
--
-- File: tb_TestDataPath_all.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench is used to test the DataPath & ADC_Calibration modules
-- with static/dynamic calibration and in normal operation/test mode
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_TestDataPath_all is
-- Port ( );
end tb_TestDataPath_all;
architecture Behavioral of tb_TestDataPath_all is
constant kADC_Width : integer range 10 to 16 := 14;
constant kCh1LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010110010";
constant kCh1LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101";
constant kCh1HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010100010";
constant kCh1HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111000101";
constant kCh2LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010010010";
constant kCh2LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101101010101";
constant kCh2HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101000110010";
constant kCh2HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010001";
begin
-- Test the DataPath & ADC_Calibration modules with static calibration and in normal operation.
InstDataPathStaticCalib: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => false,
kSimTestMode => '0',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
-- Test the DataPath & ADC_Calibration modules with dynamic calibration and in normal operation.
InstDataPathExtCalib: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => true,
kSimTestMode => '0',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
-- Test the DataPath & ADC_Calibration modules with static calibration and in test mode.
InstDataPathStaticCalibTestMode: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => false,
kSimTestMode => '1',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
-- Test the DataPath & ADC_Calibration modules with dynamic calibration and in test mode.
InstDataPathExtCalibTestMode: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => true,
kSimTestMode => '1',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: tb_TestDataPath_all.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench is used to test the DataPath & ADC_Calibration modules
-- with static/dynamic calibration and in normal operation/test mode
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_TestDataPath_all is
-- Port ( );
end tb_TestDataPath_all;
architecture Behavioral of tb_TestDataPath_all is
constant kADC_Width : integer range 10 to 16 := 14;
constant kCh1LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010110010";
constant kCh1LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101";
constant kCh1HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010100010";
constant kCh1HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111000101";
constant kCh2LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010010010";
constant kCh2LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101101010101";
constant kCh2HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101000110010";
constant kCh2HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010001";
begin
-- Test the DataPath & ADC_Calibration modules with static calibration and in normal operation.
InstDataPathStaticCalib: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => false,
kSimTestMode => '0',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
-- Test the DataPath & ADC_Calibration modules with dynamic calibration and in normal operation.
InstDataPathExtCalib: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => true,
kSimTestMode => '0',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
-- Test the DataPath & ADC_Calibration modules with static calibration and in test mode.
InstDataPathStaticCalibTestMode: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => false,
kSimTestMode => '1',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
-- Test the DataPath & ADC_Calibration modules with dynamic calibration and in test mode.
InstDataPathExtCalibTestMode: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => true,
kSimTestMode => '1',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
end Behavioral;
|
-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2010 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_fifo_tb.vhd
--
-- -----------------------------------------------------------------------
--
-- Testbench for gen_fifo
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_fifo_tb is
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_fifo_tb is
signal clk : std_logic := '0';
signal stop : std_logic := '0';
signal d_ena : std_logic := '0';
signal d : unsigned(7 downto 0) := (others => '0');
signal q_ena : std_logic := '0';
signal q : unsigned(7 downto 0);
signal empty : std_logic;
signal full : std_logic;
function tohex(value : in unsigned) return string is
constant hex_digit : string(1 to 16) := "0123456789ABCDEF";
variable input : unsigned(value'high downto value'low);
variable rlen : integer;
variable output : string(1 to 16) := (others => '0');
begin
input := value;
rlen := value'length / 4;
for i in output'range loop
if i <= rlen then
output(i) := hex_digit(to_integer(input(input'high-(i-1)*4 downto input'high-(i*4-1))) + 1);
end if;
end loop;
return output(1 to rlen);
end function;
procedure waitRisingEdge is
begin
wait until clk = '0';
wait until clk = '1';
wait for 0.5 ns;
end procedure;
procedure waitCheck(
expected_empty:std_logic;
expected_full:std_logic) is
begin
waitRisingEdge;
assert(expected_empty = empty) report "q output " & tohex("000" & empty) & " expected " & tohex("000" & expected_empty);
assert(expected_full = full) report "q output " & tohex("000" & full) & " expected " & tohex("000" & expected_full);
end procedure;
procedure waitCheck(
expected_q:unsigned(7 downto 0);
expected_empty:std_logic;
expected_full:std_logic) is
begin
waitRisingEdge;
assert(expected_q = q) report "q output " & tohex(q) & " expected " & tohex(expected_q);
assert(expected_empty = empty) report "q output " & tohex("000" & empty) & " expected " & tohex("000" & expected_empty);
assert(expected_full = full) report "q output " & tohex("000" & full) & " expected " & tohex("000" & expected_full);
end procedure;
begin
gen_fifo_inst : entity work.gen_fifo
generic map (
width => 8,
depth => 4
)
port map (
clk => clk,
d_ena => d_ena,
d => d,
q_ena => q_ena,
q => q,
empty => empty,
full => full
);
clk <= (not stop) and (not clk) after 5 ns;
process
begin
waitCheck(X"00", '1', '0');
d_ena <= '1';
d <= X"55";
waitCheck(X"55", '0', '0');
d_ena <= '1';
d <= X"66";
waitCheck(X"55", '0', '0');
d_ena <= '1';
d <= X"77";
waitCheck(X"55", '0', '0');
d_ena <= '1';
d <= X"88";
waitCheck(X"55", '0', '1');
d_ena <= '0';
q_ena <= '1';
waitCheck(X"66", '0', '0');
waitCheck(X"77", '0', '0');
waitCheck(X"88", '0', '0');
waitCheck('1', '0');
stop <= '1';
wait;
end process;
end architecture;
|
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg8Bit is
port(
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end Reg8Bit;
architecture strc_Reg8Bit of Reg8Bit is
signal Temp: std_logic_vector(7 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "00000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg8Bit; |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg8Bit is
port(
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end Reg8Bit;
architecture strc_Reg8Bit of Reg8Bit is
signal Temp: std_logic_vector(7 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "00000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg8Bit; |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg8Bit is
port(
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end Reg8Bit;
architecture strc_Reg8Bit of Reg8Bit is
signal Temp: std_logic_vector(7 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "00000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg8Bit; |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg8Bit is
port(
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end Reg8Bit;
architecture strc_Reg8Bit of Reg8Bit is
signal Temp: std_logic_vector(7 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "00000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg8Bit; |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg8Bit is
port(
valIn: in std_logic_vector(7 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(7 downto 0)
);
end Reg8Bit;
architecture strc_Reg8Bit of Reg8Bit is
signal Temp: std_logic_vector(7 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "00000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg8Bit; |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Jun 05 08:32:55 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
clk_100 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
enable_nm : in STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync : in STD_LOGIC;
pclk : in STD_LOGIC;
ready : out STD_LOGIC;
reset : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
ready : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC;
reset : in STD_LOGIC;
pclk : in STD_LOGIC;
clk_100 : in STD_LOGIC;
enable_nm : in STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
clk_100 => clk_100,
data(7 downto 0) => data(7 downto 0),
enable_nm => enable_nm,
hdmi_clk => hdmi_clk,
hdmi_d(15 downto 0) => hdmi_d(15 downto 0),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
pclk => pclk,
ready => ready,
reset => reset,
sioc => sioc,
siod => siod,
vsync => vsync,
xclk => xclk
);
end STRUCTURE;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- character 0 causes Quartus to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0);
type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : STRING) return T_IPSTYLE;
-- to_char
function to_char(value : STD_LOGIC) return CHARACTER;
function to_char(value : NATURAL) return CHARACTER;
function to_char(rawchar : T_RAWCHAR) return CHARACTER;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(value : BOOLEAN) return STRING;
function raw_format_bool_chr(value : BOOLEAN) return STRING;
function raw_format_bool_str(value : BOOLEAN) return STRING;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_nat_bin(value : NATURAL) return STRING;
function raw_format_nat_oct(value : NATURAL) return STRING;
function raw_format_nat_dec(value : NATURAL) return STRING;
function raw_format_nat_hex(value : NATURAL) return STRING;
-- str_format_* functions
function str_format(value : REAL; precision : NATURAL := 3) return STRING;
-- to_string
function to_string(value : BOOLEAN) return STRING;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING;
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING;
function to_string(rawstring : T_RAWSTRING) return STRING;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR;
-- to_digit*
function to_digit_bin(chr : character) return integer;
function to_digit_oct(chr : character) return integer;
function to_digit_dec(chr : character) return integer;
function to_digit_hex(chr : character) return integer;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : STRING) return INTEGER;
function to_natural_oct(str : STRING) return INTEGER;
function to_natural_dec(str : STRING) return INTEGER;
function to_natural_hex(str : STRING) return INTEGER;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : STRING) return NATURAL;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_find(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_find(str : STRING; pattern : STRING) return BOOLEAN;
function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_ifind(str : STRING; pattern : STRING) return BOOLEAN;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_trim(str : STRING) return STRING;
function str_toLower(str : STRING) return STRING;
function str_toUpper(str : STRING) return STRING;
end package;
package body strings is
--
function to_IPStyle(str : STRING) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(I))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
end function;
-- to_char
-- ===========================================================================
function to_char(value : STD_LOGIC) return CHARACTER is
begin
case value IS
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- TODO: rename to to_HexDigit(..) ?
function to_char(value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(value < 16, HEX(value+1), 'X');
end function;
function to_char(rawchar : T_RAWCHAR) return CHARACTER is
begin
return CHARACTER'val(to_integer(unsigned(rawchar)));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(value : BOOLEAN) return STRING is
begin
return ite(value, "1", "0");
end function;
function raw_format_bool_chr(value : BOOLEAN) return STRING is
begin
return ite(value, "T", "F");
end function;
function raw_format_bool_str(value : BOOLEAN) return STRING is
begin
return str_toUpper(boolean'image(value));
end function;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to slv'length);
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
J := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(2 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
subtype TT_BCD is INTEGER range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : NATURAL;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_char(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(3 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 4));
variable j : NATURAL;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(value : NATURAL) return STRING is
begin
return raw_format_slv_bin(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_oct(value : NATURAL) return STRING is
begin
return raw_format_slv_oct(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_dec(value : NATURAL) return STRING is
begin
return INTEGER'image(value);
end function;
function raw_format_nat_hex(value : NATURAL) return STRING is
begin
return raw_format_slv_hex(to_slv(value, log2ceilnz(value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(value : REAL; precision : NATURAL := 3) return STRING is
constant s : REAL := sign(value);
constant val : REAL := value * s;
constant int : INTEGER := integer(floor(val));
constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision));
constant frac_str : STRING := INTEGER'image(frac);
constant res : STRING := INTEGER'image(int) & "." & (1 to (precision - frac_str'length) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(value : boolean) return string is
begin
return raw_format_bool_str(value);
end function;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING is
constant absValue : NATURAL := abs(value);
constant len : POSITIVE := log10ceilnz(absValue);
variable power : POSITIVE;
variable Result : STRING(1 TO len);
begin
power := 1;
if (base = 10) then
return INTEGER'image(value);
else
for i in len downto 1 loop
Result(i) := to_char(absValue / power MOD base);
power := power * base;
end loop;
if (value < 0) then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- TODO: rename to slv_format(..) ?
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING is
constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : STRING := INTEGER'image(int);
constant bin_len : POSITIVE := slv'length;
constant dec_len : POSITIVE := str'length;--log10ceilnz(int);
constant hex_len : POSITIVE := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : NATURAL := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : NATURAL;
variable Result : STRING(1 to ite((length = 0), len, imax(len, length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_char(to_integer(unsigned(slv((j * 4) + 3 downto (j * 4)))));
j := j + 1;
end loop;
else
report "unknown format" severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return STRING is
variable str : STRING(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
str(I - rawstring'low + 1) := to_char(rawstring(I));
end loop;
return str;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return result;
end function;
-- to_*
-- ===========================================================================
function to_digit_bin(chr : character) return integer is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
function to_digit_oct(chr : character) return integer is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
function to_digit_dec(chr : character) return integer is
begin
if chr_isDigit(chr) then
return character'pos(chr) - character'pos('0');
else
return -1;
end if;
end function;
function to_digit_hex(chr : character) return integer is
begin
if chr_isDigit(chr) then return character'pos(chr) - character'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - character'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - character'pos('A') + 10;
else return -1;
end if;
end function;
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function to_natural_bin(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_bin(str(I));
if (Digit /= -1) then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_oct(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_oct(str(I));
if (Digit /= -1) then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_dec(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_dec(str(I));
if (Digit /= -1) then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result;
-- return INTEGER'value(str); -- 'value(...) is not supported by Vivado Synth 2014.1
end function;
function to_natural_hex(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_hex(str(I));
if (Digit /= -1) then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "unknown base" severity ERROR;
end case;
end function;
-- to_raw*
-- ===========================================================================
function to_RawChar(char : character) return t_rawchar is
begin
return std_logic_vector(to_unsigned(character'pos(char), t_rawchar'length));
end function;
function to_RawString(str : STRING) return T_RAWSTRING is
variable rawstr : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
rawstr(i - str'low) := to_RawChar(str(i));
end loop;
return rawstr;
end function;
-- resize
-- ===========================================================================
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to size);
begin
Result := (others => FillChar);
if (str'length > 0) then
Result(1 to imin(size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if (str(i) = chr) then
return i;
end if;
end loop;
return -1;
end function;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
function str_find(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
function str_find(str : STRING; pattern : STRING) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
function str_ifind(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
function str_ifind(str : STRING; pattern : STRING) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is
variable pos : INTEGER;
begin
pos := str_pos(str, pattern);
if (pos > 0) then
if (pos = 1) then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- examples:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if (start < 0) then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif (start = 0) then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + length;
elsif (length = 0) then -- length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- length is positive -> end substring at StartOfString + length
EndOfString := StartOfString + length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
return str(StartOfString to EndOfString);
end function;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'range loop
if (str(i) /= char) then
return str(i to str'high);
end if;
end loop;
return "";
end function;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'reverse_range loop
if (str(i) /= char) then
return str(str'low to i);
end if;
end loop;
return "";
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_toLower(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toLower(str(I));
end loop;
return temp;
end function;
function str_toUpper(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toUpper(str(I));
end loop;
return temp;
end function;
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- character 0 causes Quartus to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0);
type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : STRING) return T_IPSTYLE;
-- to_char
function to_char(value : STD_LOGIC) return CHARACTER;
function to_char(value : NATURAL) return CHARACTER;
function to_char(rawchar : T_RAWCHAR) return CHARACTER;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(value : BOOLEAN) return STRING;
function raw_format_bool_chr(value : BOOLEAN) return STRING;
function raw_format_bool_str(value : BOOLEAN) return STRING;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_nat_bin(value : NATURAL) return STRING;
function raw_format_nat_oct(value : NATURAL) return STRING;
function raw_format_nat_dec(value : NATURAL) return STRING;
function raw_format_nat_hex(value : NATURAL) return STRING;
-- str_format_* functions
function str_format(value : REAL; precision : NATURAL := 3) return STRING;
-- to_string
function to_string(value : BOOLEAN) return STRING;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING;
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING;
function to_string(rawstring : T_RAWSTRING) return STRING;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR;
-- to_digit*
function to_digit_bin(chr : character) return integer;
function to_digit_oct(chr : character) return integer;
function to_digit_dec(chr : character) return integer;
function to_digit_hex(chr : character) return integer;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : STRING) return INTEGER;
function to_natural_oct(str : STRING) return INTEGER;
function to_natural_dec(str : STRING) return INTEGER;
function to_natural_hex(str : STRING) return INTEGER;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : STRING) return NATURAL;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_find(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_find(str : STRING; pattern : STRING) return BOOLEAN;
function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_ifind(str : STRING; pattern : STRING) return BOOLEAN;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_trim(str : STRING) return STRING;
function str_toLower(str : STRING) return STRING;
function str_toUpper(str : STRING) return STRING;
end package;
package body strings is
--
function to_IPStyle(str : STRING) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(I))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
end function;
-- to_char
-- ===========================================================================
function to_char(value : STD_LOGIC) return CHARACTER is
begin
case value IS
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- TODO: rename to to_HexDigit(..) ?
function to_char(value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(value < 16, HEX(value+1), 'X');
end function;
function to_char(rawchar : T_RAWCHAR) return CHARACTER is
begin
return CHARACTER'val(to_integer(unsigned(rawchar)));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(value : BOOLEAN) return STRING is
begin
return ite(value, "1", "0");
end function;
function raw_format_bool_chr(value : BOOLEAN) return STRING is
begin
return ite(value, "T", "F");
end function;
function raw_format_bool_str(value : BOOLEAN) return STRING is
begin
return str_toUpper(boolean'image(value));
end function;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to slv'length);
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
J := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(2 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
subtype TT_BCD is INTEGER range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : NATURAL;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_char(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(3 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 4));
variable j : NATURAL;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(value : NATURAL) return STRING is
begin
return raw_format_slv_bin(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_oct(value : NATURAL) return STRING is
begin
return raw_format_slv_oct(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_dec(value : NATURAL) return STRING is
begin
return INTEGER'image(value);
end function;
function raw_format_nat_hex(value : NATURAL) return STRING is
begin
return raw_format_slv_hex(to_slv(value, log2ceilnz(value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(value : REAL; precision : NATURAL := 3) return STRING is
constant s : REAL := sign(value);
constant val : REAL := value * s;
constant int : INTEGER := integer(floor(val));
constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision));
constant frac_str : STRING := INTEGER'image(frac);
constant res : STRING := INTEGER'image(int) & "." & (1 to (precision - frac_str'length) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(value : boolean) return string is
begin
return raw_format_bool_str(value);
end function;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING is
constant absValue : NATURAL := abs(value);
constant len : POSITIVE := log10ceilnz(absValue);
variable power : POSITIVE;
variable Result : STRING(1 TO len);
begin
power := 1;
if (base = 10) then
return INTEGER'image(value);
else
for i in len downto 1 loop
Result(i) := to_char(absValue / power MOD base);
power := power * base;
end loop;
if (value < 0) then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- TODO: rename to slv_format(..) ?
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING is
constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : STRING := INTEGER'image(int);
constant bin_len : POSITIVE := slv'length;
constant dec_len : POSITIVE := str'length;--log10ceilnz(int);
constant hex_len : POSITIVE := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : NATURAL := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : NATURAL;
variable Result : STRING(1 to ite((length = 0), len, imax(len, length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_char(to_integer(unsigned(slv((j * 4) + 3 downto (j * 4)))));
j := j + 1;
end loop;
else
report "unknown format" severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return STRING is
variable str : STRING(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
str(I - rawstring'low + 1) := to_char(rawstring(I));
end loop;
return str;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return result;
end function;
-- to_*
-- ===========================================================================
function to_digit_bin(chr : character) return integer is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
function to_digit_oct(chr : character) return integer is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
function to_digit_dec(chr : character) return integer is
begin
if chr_isDigit(chr) then
return character'pos(chr) - character'pos('0');
else
return -1;
end if;
end function;
function to_digit_hex(chr : character) return integer is
begin
if chr_isDigit(chr) then return character'pos(chr) - character'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - character'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - character'pos('A') + 10;
else return -1;
end if;
end function;
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function to_natural_bin(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_bin(str(I));
if (Digit /= -1) then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_oct(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_oct(str(I));
if (Digit /= -1) then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_dec(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_dec(str(I));
if (Digit /= -1) then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result;
-- return INTEGER'value(str); -- 'value(...) is not supported by Vivado Synth 2014.1
end function;
function to_natural_hex(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_hex(str(I));
if (Digit /= -1) then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "unknown base" severity ERROR;
end case;
end function;
-- to_raw*
-- ===========================================================================
function to_RawChar(char : character) return t_rawchar is
begin
return std_logic_vector(to_unsigned(character'pos(char), t_rawchar'length));
end function;
function to_RawString(str : STRING) return T_RAWSTRING is
variable rawstr : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
rawstr(i - str'low) := to_RawChar(str(i));
end loop;
return rawstr;
end function;
-- resize
-- ===========================================================================
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to size);
begin
Result := (others => FillChar);
if (str'length > 0) then
Result(1 to imin(size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if (str(i) = chr) then
return i;
end if;
end loop;
return -1;
end function;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
function str_find(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
function str_find(str : STRING; pattern : STRING) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
function str_ifind(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
function str_ifind(str : STRING; pattern : STRING) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is
variable pos : INTEGER;
begin
pos := str_pos(str, pattern);
if (pos > 0) then
if (pos = 1) then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- examples:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if (start < 0) then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif (start = 0) then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + length;
elsif (length = 0) then -- length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- length is positive -> end substring at StartOfString + length
EndOfString := StartOfString + length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
return str(StartOfString to EndOfString);
end function;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'range loop
if (str(i) /= char) then
return str(i to str'high);
end if;
end loop;
return "";
end function;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'reverse_range loop
if (str(i) /= char) then
return str(str'low to i);
end if;
end loop;
return "";
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_toLower(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toLower(str(I));
end loop;
return temp;
end function;
function str_toUpper(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toUpper(str(I));
end loop;
return temp;
end function;
end package body;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity zpuino_top_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_hyperion;
architecture behave of zpuino_top_hyperion is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic;
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic;
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 0);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 0)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic
);
end component;
component zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wb_rom_ram_hyperion is
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_cti_i: in std_logic_vector(2 downto 0)
);
end component wb_rom_ram_hyperion;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBitBRAM downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits+1 downto 2);
signal stack_a_writeenable, stack_b_writeenable, stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal ram_wb_clk_i: std_logic;
signal ram_wb_rst_i: std_logic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_we_i: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_we_i: std_logic;
signal rom_wb_clk_i: std_logic;
signal rom_wb_rst_i: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_hyperion
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBitBRAM downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
rom_wb_cti_o => rom_wb_cti_i,
rom_wb_stall_i => '0',
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
memory: wb_rom_ram_hyperion
port map (
ram_wb_clk_i => clk,
ram_wb_rst_i => rst,
ram_wb_ack_o => ram_wb_ack_o,
ram_wb_dat_i => ram_wb_dat_i,
ram_wb_dat_o => ram_wb_dat_o,
ram_wb_adr_i => ram_wb_adr_i,
ram_wb_cyc_i => ram_wb_cyc_i,
ram_wb_stb_i => ram_wb_stb_i,
ram_wb_we_i => ram_wb_we_i,
rom_wb_clk_i => clk,
rom_wb_rst_i => rst,
rom_wb_ack_o => rom_wb_ack_o,
rom_wb_dat_o => rom_wb_dat_o,
rom_wb_adr_i => rom_wb_adr_i,
rom_wb_cyc_i => rom_wb_cyc_i,
rom_wb_stb_i => rom_wb_stb_i,
rom_wb_cti_i => rom_wb_cti_i
);
dbg: zpuino_debug_core_hyperion
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => "1111",--wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => open, --ram_wb_sel_i,
s0_wb_cti_o => open, --ram_wb_cti_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i,
m0_wb_sel_i => (others => '1'),
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i,
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_o,
s0_wb_dat_o => ram_wb_dat_i,
s0_wb_adr_o => ram_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_i,
s0_wb_cyc_o => ram_wb_cyc_i,
s0_wb_stb_o => ram_wb_stb_i,
s0_wb_ack_i => ram_wb_ack_o
);
end behave;
|
-------------------------------------------------------------------------------
-- File Name : DC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : DC_ROM
--
-- Content : DC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DC_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
VLI_size : in std_logic_vector(3 downto 0);
VLC_DC_size : out std_logic_vector(3 downto 0);
VLC_DC : out unsigned(8 downto 0)
);
end entity DC_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DC_ROM is
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- DC-ROM
-------------------------------------------------------------------
p_dc_rom : process(CLK, RST)
begin
if RST = '1' then
VLC_DC_size <= X"0";
VLC_DC <= (others => '0');
elsif CLK'event and CLK = '1' then
case VLI_size is
when X"0" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("00", VLC_DC'length);
when X"1" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("010", VLC_DC'length);
when X"2" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("011", VLC_DC'length);
when X"3" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("100", VLC_DC'length);
when X"4" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("101", VLC_DC'length);
when X"5" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("110", VLC_DC'length);
when X"6" =>
VLC_DC_size <= X"4";
VLC_DC <= resize("1110", VLC_DC'length);
when X"7" =>
VLC_DC_size <= X"5";
VLC_DC <= resize("11110", VLC_DC'length);
when X"8" =>
VLC_DC_size <= X"6";
VLC_DC <= resize("111110", VLC_DC'length);
when X"9" =>
VLC_DC_size <= X"7";
VLC_DC <= resize("1111110", VLC_DC'length);
when X"A" =>
VLC_DC_size <= X"8";
VLC_DC <= resize("11111110", VLC_DC'length);
when X"B" =>
VLC_DC_size <= X"9";
VLC_DC <= resize("111111110", VLC_DC'length);
when others =>
VLC_DC_size <= X"0";
VLC_DC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : DC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : DC_ROM
--
-- Content : DC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DC_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
VLI_size : in std_logic_vector(3 downto 0);
VLC_DC_size : out std_logic_vector(3 downto 0);
VLC_DC : out unsigned(8 downto 0)
);
end entity DC_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DC_ROM is
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- DC-ROM
-------------------------------------------------------------------
p_dc_rom : process(CLK, RST)
begin
if RST = '1' then
VLC_DC_size <= X"0";
VLC_DC <= (others => '0');
elsif CLK'event and CLK = '1' then
case VLI_size is
when X"0" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("00", VLC_DC'length);
when X"1" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("010", VLC_DC'length);
when X"2" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("011", VLC_DC'length);
when X"3" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("100", VLC_DC'length);
when X"4" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("101", VLC_DC'length);
when X"5" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("110", VLC_DC'length);
when X"6" =>
VLC_DC_size <= X"4";
VLC_DC <= resize("1110", VLC_DC'length);
when X"7" =>
VLC_DC_size <= X"5";
VLC_DC <= resize("11110", VLC_DC'length);
when X"8" =>
VLC_DC_size <= X"6";
VLC_DC <= resize("111110", VLC_DC'length);
when X"9" =>
VLC_DC_size <= X"7";
VLC_DC <= resize("1111110", VLC_DC'length);
when X"A" =>
VLC_DC_size <= X"8";
VLC_DC <= resize("11111110", VLC_DC'length);
when X"B" =>
VLC_DC_size <= X"9";
VLC_DC <= resize("111111110", VLC_DC'length);
when others =>
VLC_DC_size <= X"0";
VLC_DC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : DC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : DC_ROM
--
-- Content : DC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DC_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
VLI_size : in std_logic_vector(3 downto 0);
VLC_DC_size : out std_logic_vector(3 downto 0);
VLC_DC : out unsigned(8 downto 0)
);
end entity DC_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DC_ROM is
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- DC-ROM
-------------------------------------------------------------------
p_dc_rom : process(CLK, RST)
begin
if RST = '1' then
VLC_DC_size <= X"0";
VLC_DC <= (others => '0');
elsif CLK'event and CLK = '1' then
case VLI_size is
when X"0" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("00", VLC_DC'length);
when X"1" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("010", VLC_DC'length);
when X"2" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("011", VLC_DC'length);
when X"3" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("100", VLC_DC'length);
when X"4" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("101", VLC_DC'length);
when X"5" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("110", VLC_DC'length);
when X"6" =>
VLC_DC_size <= X"4";
VLC_DC <= resize("1110", VLC_DC'length);
when X"7" =>
VLC_DC_size <= X"5";
VLC_DC <= resize("11110", VLC_DC'length);
when X"8" =>
VLC_DC_size <= X"6";
VLC_DC <= resize("111110", VLC_DC'length);
when X"9" =>
VLC_DC_size <= X"7";
VLC_DC <= resize("1111110", VLC_DC'length);
when X"A" =>
VLC_DC_size <= X"8";
VLC_DC <= resize("11111110", VLC_DC'length);
when X"B" =>
VLC_DC_size <= X"9";
VLC_DC <= resize("111111110", VLC_DC'length);
when others =>
VLC_DC_size <= X"0";
VLC_DC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_411 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end cmp_411;
architecture augh of cmp_411 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_411 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end cmp_411;
architecture augh of cmp_411 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_dma_0_wrapper_fifo_generator_v9_3_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:56:33 07/06/2016
-- Design Name:
-- Module Name: RF_fetch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RF_fetch is
Port ( kbclk : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
rf : out STD_LOGIC);
end RF_fetch;
architecture Behavioral of RF_fetch is
signal clk_history: STD_LOGIC_VECTOR(1 downto 0);
begin
clk_history_shift: process(kbclk, clk, reset)
begin
if reset = '1' then
clk_history <= "11";
elsif clk'event and clk = '1' then
clk_history(1) <= clk_history(0);
clk_history(0) <= kbclk;
end if;
end process clk_history_shift;
find_rf: process(clk_history)
begin
if clk_history = "10" then
rf <= '1';
else
rf <= '0';
end if;
end process find_rf;
end Behavioral;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity tb_uart_tx is
end tb_uart_tx;
architecture behavior of tb_uart_tx is
-- Component Declaration for the Unit Under Test (UUT)
component uart_tx
port(
Clk : in std_logic;
Rst : in std_logic;
FreqEn : in std_logic;
Byte : in std_logic_vector(7 downto 0);
Kick : in std_logic;
RsTx : out std_logic;
Busy : out std_logic
);
end component;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '1';
signal FreqEn : std_logic := '0';
signal Byte : std_logic_vector(7 downto 0) := X"AA";
signal Kick : std_logic := '0';
--Outputs
signal RsTx : std_logic;
signal Busy : std_logic;
-- Clock period definitions
constant Clk_period : time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut : uart_tx port map (
Clk => Clk,
Rst => Rst,
FreqEn => FreqEn,
Byte => Byte,
Kick => Kick,
RsTx => RsTx,
Busy => Busy
);
-- Clock process definitions
Clk_process : process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Frequenct enable process
Freq_process : process
begin
FreqEn <= '0';
wait for Clk_period * 2;
FreqEn <= '1';
wait for Clk_period;
end process;
-- Kick process
Kick_process : process
begin
Kick <= '0';
Byte <= X"00";
wait for Clk_period * 25;
Kick <= '1';
Byte <= X"55";
wait for Clk_period;
Byte <= X"00";
wait for Clk_period;
end process;
-- Stimulus process
stim_proc : process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
Rst <= '0';
wait for Clk_period*10;
-- insert stimulus here
wait;
end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram128bw
-- File: syncram128bw.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 128-bit syncronous 1-port ram with 8-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram128bw is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(16*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(16*custombits-1 downto 0));
end;
architecture rtl of syncram128bw is
component unisim_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end component;
component altera_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end component;
component tm65gplus_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000"
);
end component;
component ut90nhbd_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
tdbn : in std_ulogic
);
end component;
signal xenable, xwrite : std_logic_vector(15 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
custominx(custominx'high downto custombits) <= (others => '0');
custominx(custombits-1 downto 0) <= customin(custombits-1 downto 0);
nocust: if syncram_has_customif(tech)=0 or has_sram128bw(tech)=0 generate
customoutx <= (others => '0');
end generate;
s64 : if has_sram128bw(tech) = 1 generate
xc2v : if (is_unisim(tech) = 1) generate
x0 : unisim_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
alt : if (tech = stratix2) or (tech = stratix3) or (tech = stratix4) or
(tech = cyclone3) or (tech = altera) generate
x0 : altera_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
tm65: if tech = tm65gplus generate
x0 : tm65gplus_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin);
end generate;
ut09: if tech = ut90 generate
x0 : ut90nhbd_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin(TESTIN_WIDTH-3));
end generate;
customout(16*custombits-1 downto custombits) <= (others => '0');
customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0);
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram128bw: " & tost(2**abits) & "x128" &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nos64 : if has_sram128bw(tech) = 0 generate
rx : for i in 0 to 15 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i), testin,
customclk, customin((i+1)*custombits-1 downto i*custombits),
customout((i+1)*custombits-1 downto i*custombits));
end generate;
end generate;
end;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 1; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant FADD_DELAY : integer := 11;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 1; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant FADD_DELAY : integer := 11;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FSM_LCD is
port (
Clock, RST, Sign : in std_logic;
Operation : in std_logic_vector(1 downto 0);
Selection : out std_logic_vector(4 downto 0);
RS, EN : out std_logic
);
end FSM_LCD;
architecture FSM_beh of FSM_LCD is
type states0 is (C0, C1, C2);
type states1 is (B0, B1, B2);
type states2 is (S0, CMD1, CMD2, CMD3, ESOMA, EMULT, ESUB, RESULT_U1, RESULT_T1, OP2_T3, RESULT_H1, OP1_H2, OP1_T2, OP1_U2, OP2_H3, EDIV, NEG_OPR, NEG_OP2, NEG_OP1, OP2_U3, LIMPA, EIGUAL, Edois);
signal CA: states0;
signal BA, PB: states1;
signal EA, PE: states2;
signal delay: std_logic_vector(4 downto 0);
signal iniciado, NotSending: std_logic;
component counter
port (
Clock, Reset : in std_logic;
Fim : out std_logic
);
end component;
begin
P0: process(Clock, RST, NotSending)
begin
if RST = '0' then
CA <= C0;
BA <= B2;
elsif NotSending = '1' then
BA <= B2;
elsif Clock'event and Clock = '1' then
case CA is
when C0 =>
delay <= (others => '0');
CA <= C1;
when C1 =>
delay <= delay + 1;
CA <= C2;
when C2 =>
if delay <= "00001" then --59 cycles = 1180ns "11110"
CA <= C1;
else
CA <= C0;
BA <= PB;
end if;
end case;
end if;
end process;
P1: process (RST, BA)
begin
if RST = '0' then
EA <= S0;
else
case BA is
when B0 =>
EN <= '0';
PB <= B1;
when B1 =>
EN <= '1';
PB <= B2;
when B2 =>
EN <= '0';
PB <= B0;
EA <= PE;
end case;
end if;
end process;
P2: process(EA, Sign, Operation, iniciado)
begin
case EA is
when S0 =>
--NotSending = '1';
if iniciado = '0' then
PE <= CMD1;
else
PE <= LIMPA;
end if;
when CMD1 => -- 038H
RS <= '0';
Selection <= "01001";
if iniciado = '0' then
PE <= CMD2;
else
PE <= LIMPA;
end if;
when CMD2 => -- 0FH
RS <= '0';
Selection <= "01010";
PE <= CMD3;
when CMD3 => --06H
RS <= '0';
iniciado <= '1';
Selection <= "01011";
PE <= LIMPA;
when LIMPA => --01H
RS <= '0';
Selection <= "10010";
PE <= NEG_OP1;
when NEG_OP1 => --SINAL NEGATIVO OP1
RS <= '1';
Selection <= "01101";
if Sign = '1' then
PE <= OP1_H2;
end if;
when OP1_H2 => --H2
RS <= '1';
Selection <= "00011";
PE <= OP1_T2;
--OPERANDO 1
when OP1_T2 => --T2
RS <= '1';
Selection <= "00100";
PE <= OP1_U2;
when OP1_U2 => --U2
RS <= '1';
Selection <= "00101";
if Operation = "00" then
PE <= ESOMA;
elsif Operation = "01" then
PE <= ESUB;
end if;
when ESOMA => -- MAIS
RS <= '1';
Selection <= "01100";
if Sign = '1' then
PE <= NEG_OP2;
else
PE <= OP2_H3;
end if;
when ESUB => -- MENOS
RS <= '1';
Selection <= "01101";
if Sign = '1' then
PE <= NEG_OP2;
else
PE <= OP2_H3;
end if;
when EDIV => --BARRA
RS <= '1';
Selection <= "01111";
if Sign = '1' then
PE <= NEG_OP2;
else
PE <= OP2_H3;
end if;
when EMULT => --VEZES
RS <= '1';
Selection <= "01110";
if Sign = '1' then
PE <= NEG_OP2;
else
PE <= OP2_H3;
end if;
when NEG_OP2 => --SINAL NEGATIVO OP2
RS <= '1';
Selection <= "01101";
if Sign = '1' then
PE <= OP2_H3;
end if;
when OP2_H3 => --H3
RS <= '1';
Selection <= "00110";
PE <= OP2_T3;
when OP2_T3 => --T3
RS <= '1'; --OPERANDO 2 E 1(/ e *)
Selection <= "00111";
PE <= OP2_U3;
when OP2_U3 => --U3
RS <= '1';
Selection <= "01000";
if Operation = "00" then
PE <= EIGUAL;
elsif Operation = "01"then
PE <= EIGUAL;
elsif Operation = "10" then
PE <= Edois;
else
PE <= Edois;
end if;
when Edois => --2
RS <= '1';
Selection <= "10001";
PE <= EIGUAL;
when EIGUAL => --IGUAL
RS <= '1';
Selection <= "10000";
if Sign = '1' then
PE <= NEG_OPR;
else
PE <= RESULT_H1;
end if;
when NEG_OPR => --SINAL NEGATIVO RESULTADO
RS <= '1';
Selection <= "01101";
if Sign = '1' then
PE <= RESULT_H1;
end if;
when RESULT_H1 => --H1
RS <= '1';
Selection <= "00000";
when RESULT_T1 => --T1 --RESULTADO
RS <= '1';
Selection <= "00001";
when RESULT_U1 => --U1
RS <= '1';
Selection <= "00010";
end case;
end process;
end FSM_beh; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2903.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x01p02n02i02903ent IS
END c02s01b01x01p02n02i02903ent;
ARCHITECTURE c02s01b01x01p02n02i02903arch OF c02s01b01x01p02n02i02903ent IS
type t1 is (one,two,three);
signal s1 : t1;
constant c1 : integer:=65;
procedure proc1(variable vv1:inout real; signal ss1:inout t1) is
begin
assert (vv1=43.1)
report "Variables of mode inout for procedures are not copied properly"
severity failure;
assert (ss1=two)
report "Signals of mode inout for procedures are not copied properly"
severity failure;
assert NOT( vv1=43.1 and ss1=two )
report "***PASSED TEST: c02s01b01x01p02n02i02903"
severity NOTE;
assert ( vv1=43.1 and ss1=two )
report "***FAILED TEST: c02s01b01x01p02n02i02903 - Values of actual parameters of mode inout are not copied into their associated formal parameter."
severity ERROR;
end proc1;
BEGIN
TESTING: PROCESS
variable v1:real;
BEGIN
s1<=two;
v1:=43.1;
wait for 5 ns;
proc1(v1,s1);
wait;
END PROCESS TESTING;
END c02s01b01x01p02n02i02903arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2903.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x01p02n02i02903ent IS
END c02s01b01x01p02n02i02903ent;
ARCHITECTURE c02s01b01x01p02n02i02903arch OF c02s01b01x01p02n02i02903ent IS
type t1 is (one,two,three);
signal s1 : t1;
constant c1 : integer:=65;
procedure proc1(variable vv1:inout real; signal ss1:inout t1) is
begin
assert (vv1=43.1)
report "Variables of mode inout for procedures are not copied properly"
severity failure;
assert (ss1=two)
report "Signals of mode inout for procedures are not copied properly"
severity failure;
assert NOT( vv1=43.1 and ss1=two )
report "***PASSED TEST: c02s01b01x01p02n02i02903"
severity NOTE;
assert ( vv1=43.1 and ss1=two )
report "***FAILED TEST: c02s01b01x01p02n02i02903 - Values of actual parameters of mode inout are not copied into their associated formal parameter."
severity ERROR;
end proc1;
BEGIN
TESTING: PROCESS
variable v1:real;
BEGIN
s1<=two;
v1:=43.1;
wait for 5 ns;
proc1(v1,s1);
wait;
END PROCESS TESTING;
END c02s01b01x01p02n02i02903arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2903.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x01p02n02i02903ent IS
END c02s01b01x01p02n02i02903ent;
ARCHITECTURE c02s01b01x01p02n02i02903arch OF c02s01b01x01p02n02i02903ent IS
type t1 is (one,two,three);
signal s1 : t1;
constant c1 : integer:=65;
procedure proc1(variable vv1:inout real; signal ss1:inout t1) is
begin
assert (vv1=43.1)
report "Variables of mode inout for procedures are not copied properly"
severity failure;
assert (ss1=two)
report "Signals of mode inout for procedures are not copied properly"
severity failure;
assert NOT( vv1=43.1 and ss1=two )
report "***PASSED TEST: c02s01b01x01p02n02i02903"
severity NOTE;
assert ( vv1=43.1 and ss1=two )
report "***FAILED TEST: c02s01b01x01p02n02i02903 - Values of actual parameters of mode inout are not copied into their associated formal parameter."
severity ERROR;
end proc1;
BEGIN
TESTING: PROCESS
variable v1:real;
BEGIN
s1<=two;
v1:=43.1;
wait for 5 ns;
proc1(v1,s1);
wait;
END PROCESS TESTING;
END c02s01b01x01p02n02i02903arch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_3_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 70
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_3_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 70
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_3_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 70
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
--
-- File: HS_Negotiation.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module handles the USB speed negociatian, reset and suspend protocols
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity HS_Negotiation is
Port (
u_Reset : in STD_LOGIC;
Ulpi_Clk : in STD_LOGIC;
--command signals used to initiate register read/write,
--NOPID frameworks of the ULPI state machine
u_Send_NOPID_CMD : out STD_LOGIC;
u_Send_EXTW_CMD : out STD_LOGIC;
u_Send_REGW_CMD : out STD_LOGIC;
u_Send_EXTR_CMD : out STD_LOGIC;
u_Send_REGR_CMD : out STD_LOGIC;
u_Send_STP_CMD : out STD_LOGIC;
u_Send_Last : out STD_LOGIC;
u_Remote_Wake : in STD_LOGIC;
--NOPID data, register data, register address used for
--attachment signaling and for chirping
u_Tx_Data : out STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Regw_Data : out STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Reg_Addr : out STD_LOGIC_VECTOR (7 downto 0);
--inputs from ULPI state machine
u_Rx_Cmd_Received : in STD_LOGIC;
u_Tx_Cmd_Done : in STD_LOGIC;
--UTMI+ signals
u_LineState : in STD_LOGIC_VECTOR (1 downto 0);
u_Vbus : in STD_LOGIC_VECTOR (1 downto 0);
-- Negotiation outputs
u_USB_Mode : out STD_LOGIC;
u_Not_Connected : OUT std_logic;
u_Set_Mode_HS : OUT std_logic;
u_Set_Mode_FS : OUT std_logic;
u_Wake : OUT std_logic;
u_USBCMD_RS : in std_logic;
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0);
u_Negociation_Done : out STD_LOGIC
);
end HS_Negotiation;
architecture Behavioral of HS_Negotiation is
constant Const_10Ms : STD_LOGIC_VECTOR (10 downto 0) := "00001100100"; --100
constant Const_20Ms : STD_LOGIC_VECTOR (10 downto 0) := "00011001000"; --200
constant Const_50Ms : STD_LOGIC_VECTOR (10 downto 0) := "00111110100"; --500
constant Const_1_2Ms : STD_LOGIC_VECTOR (10 downto 0) := "00000001100"; --12
constant Const_2_5Us : STD_LOGIC_VECTOR (12 downto 0) := "0000010010110"; --150 * Ulpi_Clk_period = 2.5Us
constant Const_2_5Ms : STD_LOGIC_VECTOR (10 downto 0) := "00000011001"; --25Const_3Ms
constant Const_3Ms : STD_LOGIC_VECTOR (10 downto 0) := "00000011110"; --30
constant Const_200Us : STD_LOGIC_VECTOR (10 downto 0) := "00000000010"; --2
type state_type is (IDLE, REGR, EXTR_W, EXTR_R, DISCONNECTED, WAIT_ATTACH, WRITE_FCR, ATTACH, WAIT_RESET, PULL_UP_ID, NORMAL,RST_RES_SUSP, SUSPEND, HS_SUSPEND, FS_SUSPEND, SUSP_RES, RESET, ERROR, SEND_CHIRP_K, WAIT_CHIRP_J, WAIT_CHIRP_K, SEND_CHIRP_K_LAST, WAIT_CHIRP_SE0, SET_FS, SET_HS, SWITCH_FS, FS_WAIT_SE0, FS_WAIT_J, RESUME_REQ_WAIT, WAIT_HSEOP, CLEAR_SUSPEND, SIGNAL_WAKE); -- CLEAR_SUSPEND_COMPLETE
signal u_Negociation_State, u_Negociation_Next_State : state_type;
signal u_RX_J : STD_LOGIC;
signal u_RX_K : STD_LOGIC;
signal u_RX_SE0 : STD_LOGIC;
signal u_RX_Idle : STD_LOGIC;
signal u_Set_Mode_HS_Loc : STD_LOGIC;
signal u_Mode : STD_LOGIC; --1 when the device is in High Speed mode, 0 otherwise
signal u_Negociation_Done_Rst : STD_LOGIC;
signal u_Negociation_Done_Set : STD_LOGIC;
signal u_LineState_q : STD_LOGIC_VECTOR(1 downto 0);
signal u_LineState_Change : STD_LOGIC;
signal u_Cnt1_Us : STD_LOGIC_VECTOR(12 downto 0);
signal u_Cnt1_Ms : STD_LOGIC_VECTOR(10 downto 0);
signal u_Cnt2_Us : STD_LOGIC_VECTOR(12 downto 0);
signal u_Cnt1_Ms_Presc : STD_LOGIC;
signal u_Cnt1_Rst_Ms : STD_LOGIC;-- initial 100ms, chirp_k
signal u_Cnt2_Rst_Ms : STD_LOGIC;
signal u_Cnt_Chirp : STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal u_Cnt_Chirp_CE : STD_LOGIC;
signal u_Cnt_Chirp_Rst : STD_LOGIC;
--degug
signal u_Cnt1_Ms_debug : STD_LOGIC_VECTOR(10 downto 0);
attribute mark_debug : string;
attribute keep : string;
--attribute mark_debug of state_ind_hs_r : signal is "true";
--attribute keep of state_ind_hs_r : signal is "true";
--attribute mark_debug of rst : signal is "true";
--attribute keep of rst : signal is "true";
--attribute mark_debug of u_LineState : signal is "true";
--attribute keep of u_LineState : signal is "true";
--attribute mark_debug of u_Cnt1_Us : signal is "true";
--attribute keep of u_Cnt1_Us : signal is "true";
--attribute mark_debug of u_Cnt1_Ms : signal is "true";
--attribute keep of u_Cnt1_Ms : signal is "true";
--attribute mark_debug of u_RX_Idle : signal is "true";
--attribute keep of u_RX_Idle : signal is "true";
--attribute mark_debug of u_Cnt1_Rst_Ms : signal is "true";
--attribute keep of u_Cnt1_Rst_Ms : signal is "true";
--attribute mark_debug of u_Mode : signal is "true";
--attribute keep of u_Mode : signal is "true";
--attribute mark_debug of u_Cnt1_Ms_debug : signal is "true";
--attribute keep of u_Cnt1_Ms_debug : signal is "true";
begin
u_USB_Mode <= u_Mode;
u_Set_Mode_HS <= u_Set_Mode_HS_Loc;
u_RX_SE0 <= '1' when u_LineState = "00"
else '0';
u_RX_K <= '1' when u_LineState = "10"
else '0';
u_RX_J <= '1' when u_LineState = "01"
else '0';
u_RX_Idle <= u_RX_SE0 when u_Mode = '1'
else u_RX_J;
--debug purposes
delay_cnt: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
u_Cnt1_Ms_debug <= u_Cnt1_Ms;
end if;
end process;
--detect state machine changes
STATE_CHANGE: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
u_LineState_q <= u_LineState;
if (u_LineState_q = u_LineState) then
u_LineState_Change <= '0';
else
u_LineState_Change <= '1';
end if;
end if;
end process;
--u_Mode encodes the negotiated speed
MODEHS : process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Reset = '0') then
u_Mode <= '0';
else
if (u_Set_Mode_HS_Loc = '1') then
u_Mode <= '1';
end if;
end if;
end if;
end process;
NEG_DONE_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Reset = '0' or u_Negociation_Done_Rst = '0') then
u_Negociation_Done <= '0';
else
if (u_Negociation_Done_Set = '1') then
u_Negociation_Done <= '1';
end if;
end if;
end if;
end process;
--Counters/Timers used to monitor Reset, Suspend, Resume, High Speed Negotiation characteristic intervals
US_COUNTER1: process (Ulpi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if ((u_Cnt1_Rst_Ms = '1') or (u_Reset = '0')) then
u_Cnt1_Us <= (others => '0');
u_Cnt1_Ms_Presc <= '0';
else
u_Cnt1_Us <= u_Cnt1_Us + '1';
if (u_Cnt1_Us = 6000) then -- u_Cnt1_Ms_Presc = 100us
u_Cnt1_Ms_Presc <= '1';
u_Cnt1_Us <= (others => '0');
else
u_Cnt1_Ms_Presc <= '0';
end if;
end if;
end if;
end process;
MS_COUNTER1: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Cnt1_Rst_Ms = '1' or (u_Reset = '0')) then
u_Cnt1_Ms <= (others => '0');
else
if (u_Cnt1_Ms_Presc = '1') then
u_Cnt1_Ms <= u_Cnt1_Ms + '1';
end if;
end if;
end if;
end process;
US_COUNTER2: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Cnt2_Rst_Ms = '1' or (u_Reset = '0')) then
u_Cnt2_Us <= (others => '0');
else
u_Cnt2_Us <= u_Cnt2_Us + '1';
if (u_Cnt2_Us = 6000) then
u_Cnt2_Us <= (others => '0');
end if;
end if;
end if;
end process;
CHIRP_COUNTER: process (u_Cnt_Chirp_CE, Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Cnt_Chirp_Rst = '1' or (u_Reset = '0')) then
u_Cnt_Chirp <= (others => '0');
elsif (u_Cnt_Chirp_CE = '1') then
u_Cnt_Chirp <= u_Cnt_Chirp + '1';
end if;
end if;
end process;
--High Speed Negotiation State Machine
SYNC_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Reset = '0') then
u_Negociation_State <= IDLE;
else
u_Negociation_State <= u_Negociation_Next_State;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (u_Negociation_State, u_Vbus, u_Rx_Cmd_Received, u_USBCMD_RS, u_LineState, u_LineState_Change, u_Tx_Cmd_Done, u_RX_J, u_RX_K, u_RX_Idle, u_RX_SE0, u_Cnt_Chirp, u_Remote_Wake, u_Mode)
begin
u_Negociation_Next_State <= u_Negociation_State;
state_ind_hs <= "00000";
u_Tx_Data <= (others => '0');
u_Cnt1_Rst_Ms <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Cnt_Chirp_CE <= '0';
u_Cnt_Chirp_Rst <= '1';
u_Set_Mode_HS_Loc <= '0';
u_Negociation_Done_Rst <= '1';
u_Negociation_Done_Set <= '0';
u_Send_REGW_CMD <= '0';
u_Send_NOPID_CMD <= '0';
u_Send_Last <= '0';
u_Tx_Regw_Data <= (others => '0');
u_Tx_Reg_Addr <= (others => '0');
u_Send_REGR_CMD <= '0';
u_Send_EXTW_CMD <= '0';
u_Send_EXTR_CMD <= '0';
u_Send_STP_CMD <= '0';
u_Not_Connected <= '0';
u_Set_Mode_FS <= '0';
u_Wake <= '0';
case (u_Negociation_State) is
when IDLE =>
if (u_USBCMD_RS = '1') then --Waits for user interaction (USBCMD-> RS bit : Run/Stop) to start negociation
u_Negociation_Next_State <= DISCONNECTED;
end if;
when DISCONNECTED =>
state_ind_hs <= "00001";
u_Negociation_Done_Rst <= '0';
u_Not_Connected <= '1';
if (u_Vbus = "11") then
u_Negociation_Next_State <= WAIT_ATTACH;
end if;
when WAIT_ATTACH =>
state_ind_hs <= "00010";
u_Not_Connected <= '1';
u_Cnt1_Rst_Ms <= '0';
if ( u_Cnt1_Ms = Const_50Ms) then -- Debounce interval. Not required by specifications
if (u_Vbus = "11") then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= PULL_UP_ID;
else
u_Negociation_Next_State <= DISCONNECTED;
end if;
end if;
when PULL_UP_ID =>
state_ind_hs <= "00011";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "001010"; --u_Tx_Data (6 downto 0) = OTG control reg write addr
u_Tx_Regw_Data <= "00000001";
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= WRITE_FCR;
end if;
when WRITE_FCR =>
state_ind_hs <= "00100";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000101"; --Select peripheral Full Speed driver: opmode = 00, xcvrselect = 01, termselect = 1; the pull-up resistor on D+ will be attached
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= ATTACH;
end if;
when ATTACH =>
state_ind_hs <= "00101";
if (u_LineState = "01") then
u_Negociation_Next_State <= WAIT_RESET;
end if;
when WAIT_RESET => --the host should detect the pull-up resistor and should place the bus in SE0 state
state_ind_hs <= "00110";
u_Cnt1_Rst_Ms <= '0';
if (u_LineState = "00") then
u_Negociation_Next_State <= NORMAL;
end if;
when NORMAL => -- this is the state corresponding to normal operation. The state machine monitors SUSPEND(IDLE) and RESET conditions
state_ind_hs <= "11111";
if ( u_LineState_Change = '0') then
if (u_RX_Idle = '1') then -- if the device is in high speed mode it can not distinguish between IDLE and SE0 at this point
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_3Ms) then
u_Negociation_Next_State <= RST_RES_SUSP;
end if;
elsif ((u_RX_SE0 = '1') and (u_Mode = '0')) then --If the device is being reset from a non-suspended full-speed state, then the device begins a high-speed
--detection handshake after the detection of SE0 for no less than 2.5 ?s and no more than 3.0 ms
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Us = Const_2_5Us) then
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
end if;
else
u_Cnt1_Rst_Ms <= '1';
end if;
else
u_Cnt1_Rst_Ms <= '1';
end if;
when RST_RES_SUSP =>
state_ind_hs <= "00111";
if (u_Mode = '0') then
u_Negociation_Next_State <= SUSPEND;
elsif (u_Mode = '1') then
u_Negociation_Next_State <= SWITCH_FS;
end if;
--RESET sequence
when RESET => --Enter High-speed Detection Handshake. Select peripheral chirp by writing to the PHY FCR
state_ind_hs <= "01000";
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01010100"; --opmode = 10, xcvrselect = 00, termselect = 1
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= SEND_CHIRP_K;
end if;
when SEND_CHIRP_K =>
state_ind_hs <= "01001";
u_Cnt1_Rst_Ms <= '0';
u_Send_NOPID_CMD <= '1'; --This will instruct the ULPI state machine to send NOPID_CMD with transmit data which is by default 00h (drive current into D-)
if (u_Cnt1_Ms = Const_1_2Ms) then --The device chirp must last no less than 1.0 ms (TUCH) and must end no more than 7.0 ms (TUCHEND) high-speed Reset time T0.
u_Cnt1_Rst_Ms <= '1';
u_Send_Last <= '1';
u_Negociation_Next_State <= SEND_CHIRP_K_LAST;
end if;
when SEND_CHIRP_K_LAST =>
state_ind_hs <= "01010";
--u_Tx_Data <= (others => '0');
u_Cnt1_Rst_Ms <= '1';
if (u_Rx_Cmd_Received = '1') then
if (u_RX_SE0 = '1') then
u_Negociation_Next_State <= WAIT_CHIRP_SE0;
end if;
end if;
--------------------------------------------------------------
when WAIT_CHIRP_SE0 =>
state_ind_hs <= "01011";
u_Cnt1_Rst_Ms <= '0'; -- monitor JK timeout
if (u_RX_K = '1') then
u_Cnt1_Rst_Ms <= '0';
u_Cnt2_Rst_Ms <= '0'; -- monitor chirp duration
u_Negociation_Next_State <= WAIT_CHIRP_K;
elsif (u_Cnt1_Ms = Const_2_5Ms) then
u_Set_Mode_FS <= '1';
u_Negociation_Next_State <= SET_FS;
end if;
--------------------------------------------------------------
when WAIT_CHIRP_K =>
state_ind_hs <= "01100";
u_Cnt_Chirp_Rst <= '0';
u_Cnt1_Rst_Ms <= '0'; -- monitor JK timeout
if (u_RX_K = '1') then
u_Cnt2_Rst_Ms <= '0'; -- monitor chirp duration
if (u_Cnt2_Us = Const_2_5Us) then
if(u_Cnt_Chirp > 5) then
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Cnt_Chirp_Rst <= '1';
u_Cnt_Chirp_CE <= '0';
u_Negociation_Next_State <= SET_HS;
else
u_Cnt_Chirp_CE <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Negociation_Next_State <= WAIT_CHIRP_J;
end if;
end if;
elsif (u_Cnt1_Ms = Const_2_5Ms or u_RX_SE0 = '1') then
u_Send_REGW_CMD <= '1';
u_Cnt1_Rst_Ms <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Set_Mode_FS <= '1';
u_Negociation_Next_State <= SET_FS;
end if;
when WAIT_CHIRP_J =>
state_ind_hs <= "01101";
u_Cnt1_Rst_Ms <= '0'; -- monitor JK timeout
u_Cnt_Chirp_Rst <= '0';
if (u_RX_J = '1') then
u_Cnt2_Rst_Ms <= '0'; -- monitor chirp duration
if (u_Cnt2_Us = Const_2_5Us) then
if(u_Cnt_Chirp > 5) then
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Cnt_Chirp_Rst <= '1';
u_Cnt_Chirp_CE <= '0';
u_Negociation_Next_State <= SET_HS;
else
u_Cnt2_Rst_Ms <= '1';
u_Cnt_Chirp_CE <= '1';
u_Negociation_Next_State <= WAIT_CHIRP_K;
end if;
end if;
elsif (u_Cnt1_Ms = Const_2_5Ms or u_RX_SE0 = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "00000101"; --opmode = 00, xcvrselect = 00, termselect = 1
u_Set_Mode_FS <= '1';
u_Negociation_Next_State <= SET_FS;
end if;
when SET_FS =>
state_ind_hs <= "01110";
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000101"; --opmode = 00, xcvrselect = 01, termselect = 1
u_Send_REGW_CMD <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Done_Set <= '1';
u_Negociation_Next_State <= NORMAL;
end if;
when SET_HS =>
state_ind_hs <= "01111";
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000000"; --opmode = 00, xcvrselect = 00, termselect = 0
u_Set_Mode_HS_Loc <= '1';
u_Send_REGW_CMD <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Done_Set <= '1';
u_Negociation_Next_State <= NORMAL;
end if;
---SUSPEND/RESUME -- Not Tested!
when SWITCH_FS => -- Select peripherla Full Speed by writing to FCR
u_Negociation_Done_Rst <= '0';
state_ind_hs <= "10000";
u_Cnt1_Rst_Ms <= '0';
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000101"; --opmode = 00, xcvrselect = 01, termselect = 1
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= SUSP_RES;
end if;
when SUSP_RES =>
state_ind_hs <= "10001";
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_200Us) then --The device samples the bus state, and checks for SE0 (reset as opposed to suspend), no less than 100 �s and no more than 875 �s (TWTRSTHS) after starting reversion to full-speed.
if( u_RX_SE0 = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
elsif (u_RX_J = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= SUSPEND;
else
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= DISCONNECTED;
end if;
end if;
when SUSPEND =>
state_ind_hs <= "10010";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg set addr
u_Tx_Regw_Data <= "00010101"; --set suspendM
if (u_Tx_Cmd_Done = '1') then
if (u_Mode = '1') then
u_Negociation_Next_State <= HS_SUSPEND;
else
u_Negociation_Next_State <= FS_SUSPEND;
end if;
end if;
when FS_SUSPEND =>
state_ind_hs <= "10011";
if (u_RX_K = '1') then
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_20Ms) then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= FS_WAIT_SE0;
end if;
elsif (u_RX_SE0 = '1')then
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Us = Const_2_5Us) then
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
end if;
elsif (u_Remote_Wake = '1') then -- 3ms to enter suspend + 2ms
u_Send_STP_CMD <= '1';
u_Negociation_Next_State <= CLEAR_SUSPEND;
else
u_Cnt1_Rst_Ms <= '1';
end if;
when HS_SUSPEND =>
state_ind_hs <= "10100";
if (u_RX_K = '1') then
u_Cnt1_Rst_Ms <= '0';
state_ind_hs <= "11110";
if (u_Cnt1_Ms = Const_20Ms) then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= WAIT_HSEOP;
end if;
elsif (u_RX_SE0 = '1')then
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Us = Const_2_5Us) then
state_ind_hs <= "11101";
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
end if;
elsif (u_Remote_Wake = '1') then -- 3ms to enter suspend + 2ms
u_Send_STP_CMD <= '1';
u_Negociation_Next_State <= CLEAR_SUSPEND;
else
state_ind_hs <= "11100";
u_Cnt1_Rst_Ms <= '1';
end if;
when FS_WAIT_SE0 =>
state_ind_hs <= "10101";
if (u_RX_SE0 = '1') then
u_Negociation_Next_State <= FS_WAIT_J;
end if;
when FS_WAIT_J =>
state_ind_hs <= "10110";
if (u_RX_J = '1') then
u_Send_REGW_CMD <= '1';
u_Set_Mode_FS <= '1';
u_Wake <= '1';
u_Negociation_Next_State <= SET_FS;
else
u_Negociation_Next_State <= ERROR;
end if;
when WAIT_HSEOP =>
state_ind_hs <= "10111";
if (u_RX_SE0 = '1') then
u_Send_REGW_CMD <= '1';
u_Wake <= '1';
u_Negociation_Next_State <= SET_HS;
end if;
when CLEAR_SUSPEND =>
state_ind_hs <= "11001";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100";
u_Tx_Regw_Data <= "01010101";
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= SIGNAL_WAKE;
end if;
when SIGNAL_WAKE =>
state_ind_hs <= "11010";
u_Send_NOPID_CMD <= '1';
u_Tx_Data <= "11111111";
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_10Ms) then
u_Send_Last <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= RESUME_REQ_WAIT;
end if;
end if;
when RESUME_REQ_WAIT =>
state_ind_hs <= "11011";
u_Cnt1_Rst_Ms <= '0';
if (u_RX_K = '1') then
u_Negociation_Next_State <= WAIT_HSEOP;
end if;
when others =>
u_Negociation_Next_State <= DISCONNECTED;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: HS_Negotiation.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module handles the USB speed negociatian, reset and suspend protocols
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity HS_Negotiation is
Port (
u_Reset : in STD_LOGIC;
Ulpi_Clk : in STD_LOGIC;
--command signals used to initiate register read/write,
--NOPID frameworks of the ULPI state machine
u_Send_NOPID_CMD : out STD_LOGIC;
u_Send_EXTW_CMD : out STD_LOGIC;
u_Send_REGW_CMD : out STD_LOGIC;
u_Send_EXTR_CMD : out STD_LOGIC;
u_Send_REGR_CMD : out STD_LOGIC;
u_Send_STP_CMD : out STD_LOGIC;
u_Send_Last : out STD_LOGIC;
u_Remote_Wake : in STD_LOGIC;
--NOPID data, register data, register address used for
--attachment signaling and for chirping
u_Tx_Data : out STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Regw_Data : out STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Reg_Addr : out STD_LOGIC_VECTOR (7 downto 0);
--inputs from ULPI state machine
u_Rx_Cmd_Received : in STD_LOGIC;
u_Tx_Cmd_Done : in STD_LOGIC;
--UTMI+ signals
u_LineState : in STD_LOGIC_VECTOR (1 downto 0);
u_Vbus : in STD_LOGIC_VECTOR (1 downto 0);
-- Negotiation outputs
u_USB_Mode : out STD_LOGIC;
u_Not_Connected : OUT std_logic;
u_Set_Mode_HS : OUT std_logic;
u_Set_Mode_FS : OUT std_logic;
u_Wake : OUT std_logic;
u_USBCMD_RS : in std_logic;
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0);
u_Negociation_Done : out STD_LOGIC
);
end HS_Negotiation;
architecture Behavioral of HS_Negotiation is
constant Const_10Ms : STD_LOGIC_VECTOR (10 downto 0) := "00001100100"; --100
constant Const_20Ms : STD_LOGIC_VECTOR (10 downto 0) := "00011001000"; --200
constant Const_50Ms : STD_LOGIC_VECTOR (10 downto 0) := "00111110100"; --500
constant Const_1_2Ms : STD_LOGIC_VECTOR (10 downto 0) := "00000001100"; --12
constant Const_2_5Us : STD_LOGIC_VECTOR (12 downto 0) := "0000010010110"; --150 * Ulpi_Clk_period = 2.5Us
constant Const_2_5Ms : STD_LOGIC_VECTOR (10 downto 0) := "00000011001"; --25Const_3Ms
constant Const_3Ms : STD_LOGIC_VECTOR (10 downto 0) := "00000011110"; --30
constant Const_200Us : STD_LOGIC_VECTOR (10 downto 0) := "00000000010"; --2
type state_type is (IDLE, REGR, EXTR_W, EXTR_R, DISCONNECTED, WAIT_ATTACH, WRITE_FCR, ATTACH, WAIT_RESET, PULL_UP_ID, NORMAL,RST_RES_SUSP, SUSPEND, HS_SUSPEND, FS_SUSPEND, SUSP_RES, RESET, ERROR, SEND_CHIRP_K, WAIT_CHIRP_J, WAIT_CHIRP_K, SEND_CHIRP_K_LAST, WAIT_CHIRP_SE0, SET_FS, SET_HS, SWITCH_FS, FS_WAIT_SE0, FS_WAIT_J, RESUME_REQ_WAIT, WAIT_HSEOP, CLEAR_SUSPEND, SIGNAL_WAKE); -- CLEAR_SUSPEND_COMPLETE
signal u_Negociation_State, u_Negociation_Next_State : state_type;
signal u_RX_J : STD_LOGIC;
signal u_RX_K : STD_LOGIC;
signal u_RX_SE0 : STD_LOGIC;
signal u_RX_Idle : STD_LOGIC;
signal u_Set_Mode_HS_Loc : STD_LOGIC;
signal u_Mode : STD_LOGIC; --1 when the device is in High Speed mode, 0 otherwise
signal u_Negociation_Done_Rst : STD_LOGIC;
signal u_Negociation_Done_Set : STD_LOGIC;
signal u_LineState_q : STD_LOGIC_VECTOR(1 downto 0);
signal u_LineState_Change : STD_LOGIC;
signal u_Cnt1_Us : STD_LOGIC_VECTOR(12 downto 0);
signal u_Cnt1_Ms : STD_LOGIC_VECTOR(10 downto 0);
signal u_Cnt2_Us : STD_LOGIC_VECTOR(12 downto 0);
signal u_Cnt1_Ms_Presc : STD_LOGIC;
signal u_Cnt1_Rst_Ms : STD_LOGIC;-- initial 100ms, chirp_k
signal u_Cnt2_Rst_Ms : STD_LOGIC;
signal u_Cnt_Chirp : STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal u_Cnt_Chirp_CE : STD_LOGIC;
signal u_Cnt_Chirp_Rst : STD_LOGIC;
--degug
signal u_Cnt1_Ms_debug : STD_LOGIC_VECTOR(10 downto 0);
attribute mark_debug : string;
attribute keep : string;
--attribute mark_debug of state_ind_hs_r : signal is "true";
--attribute keep of state_ind_hs_r : signal is "true";
--attribute mark_debug of rst : signal is "true";
--attribute keep of rst : signal is "true";
--attribute mark_debug of u_LineState : signal is "true";
--attribute keep of u_LineState : signal is "true";
--attribute mark_debug of u_Cnt1_Us : signal is "true";
--attribute keep of u_Cnt1_Us : signal is "true";
--attribute mark_debug of u_Cnt1_Ms : signal is "true";
--attribute keep of u_Cnt1_Ms : signal is "true";
--attribute mark_debug of u_RX_Idle : signal is "true";
--attribute keep of u_RX_Idle : signal is "true";
--attribute mark_debug of u_Cnt1_Rst_Ms : signal is "true";
--attribute keep of u_Cnt1_Rst_Ms : signal is "true";
--attribute mark_debug of u_Mode : signal is "true";
--attribute keep of u_Mode : signal is "true";
--attribute mark_debug of u_Cnt1_Ms_debug : signal is "true";
--attribute keep of u_Cnt1_Ms_debug : signal is "true";
begin
u_USB_Mode <= u_Mode;
u_Set_Mode_HS <= u_Set_Mode_HS_Loc;
u_RX_SE0 <= '1' when u_LineState = "00"
else '0';
u_RX_K <= '1' when u_LineState = "10"
else '0';
u_RX_J <= '1' when u_LineState = "01"
else '0';
u_RX_Idle <= u_RX_SE0 when u_Mode = '1'
else u_RX_J;
--debug purposes
delay_cnt: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
u_Cnt1_Ms_debug <= u_Cnt1_Ms;
end if;
end process;
--detect state machine changes
STATE_CHANGE: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
u_LineState_q <= u_LineState;
if (u_LineState_q = u_LineState) then
u_LineState_Change <= '0';
else
u_LineState_Change <= '1';
end if;
end if;
end process;
--u_Mode encodes the negotiated speed
MODEHS : process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Reset = '0') then
u_Mode <= '0';
else
if (u_Set_Mode_HS_Loc = '1') then
u_Mode <= '1';
end if;
end if;
end if;
end process;
NEG_DONE_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Reset = '0' or u_Negociation_Done_Rst = '0') then
u_Negociation_Done <= '0';
else
if (u_Negociation_Done_Set = '1') then
u_Negociation_Done <= '1';
end if;
end if;
end if;
end process;
--Counters/Timers used to monitor Reset, Suspend, Resume, High Speed Negotiation characteristic intervals
US_COUNTER1: process (Ulpi_Clk) -- Ulpi_Clk = 60MHz => T = 0.01666666 Us
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if ((u_Cnt1_Rst_Ms = '1') or (u_Reset = '0')) then
u_Cnt1_Us <= (others => '0');
u_Cnt1_Ms_Presc <= '0';
else
u_Cnt1_Us <= u_Cnt1_Us + '1';
if (u_Cnt1_Us = 6000) then -- u_Cnt1_Ms_Presc = 100us
u_Cnt1_Ms_Presc <= '1';
u_Cnt1_Us <= (others => '0');
else
u_Cnt1_Ms_Presc <= '0';
end if;
end if;
end if;
end process;
MS_COUNTER1: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Cnt1_Rst_Ms = '1' or (u_Reset = '0')) then
u_Cnt1_Ms <= (others => '0');
else
if (u_Cnt1_Ms_Presc = '1') then
u_Cnt1_Ms <= u_Cnt1_Ms + '1';
end if;
end if;
end if;
end process;
US_COUNTER2: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Cnt2_Rst_Ms = '1' or (u_Reset = '0')) then
u_Cnt2_Us <= (others => '0');
else
u_Cnt2_Us <= u_Cnt2_Us + '1';
if (u_Cnt2_Us = 6000) then
u_Cnt2_Us <= (others => '0');
end if;
end if;
end if;
end process;
CHIRP_COUNTER: process (u_Cnt_Chirp_CE, Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Cnt_Chirp_Rst = '1' or (u_Reset = '0')) then
u_Cnt_Chirp <= (others => '0');
elsif (u_Cnt_Chirp_CE = '1') then
u_Cnt_Chirp <= u_Cnt_Chirp + '1';
end if;
end if;
end process;
--High Speed Negotiation State Machine
SYNC_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (u_Reset = '0') then
u_Negociation_State <= IDLE;
else
u_Negociation_State <= u_Negociation_Next_State;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (u_Negociation_State, u_Vbus, u_Rx_Cmd_Received, u_USBCMD_RS, u_LineState, u_LineState_Change, u_Tx_Cmd_Done, u_RX_J, u_RX_K, u_RX_Idle, u_RX_SE0, u_Cnt_Chirp, u_Remote_Wake, u_Mode)
begin
u_Negociation_Next_State <= u_Negociation_State;
state_ind_hs <= "00000";
u_Tx_Data <= (others => '0');
u_Cnt1_Rst_Ms <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Cnt_Chirp_CE <= '0';
u_Cnt_Chirp_Rst <= '1';
u_Set_Mode_HS_Loc <= '0';
u_Negociation_Done_Rst <= '1';
u_Negociation_Done_Set <= '0';
u_Send_REGW_CMD <= '0';
u_Send_NOPID_CMD <= '0';
u_Send_Last <= '0';
u_Tx_Regw_Data <= (others => '0');
u_Tx_Reg_Addr <= (others => '0');
u_Send_REGR_CMD <= '0';
u_Send_EXTW_CMD <= '0';
u_Send_EXTR_CMD <= '0';
u_Send_STP_CMD <= '0';
u_Not_Connected <= '0';
u_Set_Mode_FS <= '0';
u_Wake <= '0';
case (u_Negociation_State) is
when IDLE =>
if (u_USBCMD_RS = '1') then --Waits for user interaction (USBCMD-> RS bit : Run/Stop) to start negociation
u_Negociation_Next_State <= DISCONNECTED;
end if;
when DISCONNECTED =>
state_ind_hs <= "00001";
u_Negociation_Done_Rst <= '0';
u_Not_Connected <= '1';
if (u_Vbus = "11") then
u_Negociation_Next_State <= WAIT_ATTACH;
end if;
when WAIT_ATTACH =>
state_ind_hs <= "00010";
u_Not_Connected <= '1';
u_Cnt1_Rst_Ms <= '0';
if ( u_Cnt1_Ms = Const_50Ms) then -- Debounce interval. Not required by specifications
if (u_Vbus = "11") then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= PULL_UP_ID;
else
u_Negociation_Next_State <= DISCONNECTED;
end if;
end if;
when PULL_UP_ID =>
state_ind_hs <= "00011";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "001010"; --u_Tx_Data (6 downto 0) = OTG control reg write addr
u_Tx_Regw_Data <= "00000001";
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= WRITE_FCR;
end if;
when WRITE_FCR =>
state_ind_hs <= "00100";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000101"; --Select peripheral Full Speed driver: opmode = 00, xcvrselect = 01, termselect = 1; the pull-up resistor on D+ will be attached
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= ATTACH;
end if;
when ATTACH =>
state_ind_hs <= "00101";
if (u_LineState = "01") then
u_Negociation_Next_State <= WAIT_RESET;
end if;
when WAIT_RESET => --the host should detect the pull-up resistor and should place the bus in SE0 state
state_ind_hs <= "00110";
u_Cnt1_Rst_Ms <= '0';
if (u_LineState = "00") then
u_Negociation_Next_State <= NORMAL;
end if;
when NORMAL => -- this is the state corresponding to normal operation. The state machine monitors SUSPEND(IDLE) and RESET conditions
state_ind_hs <= "11111";
if ( u_LineState_Change = '0') then
if (u_RX_Idle = '1') then -- if the device is in high speed mode it can not distinguish between IDLE and SE0 at this point
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_3Ms) then
u_Negociation_Next_State <= RST_RES_SUSP;
end if;
elsif ((u_RX_SE0 = '1') and (u_Mode = '0')) then --If the device is being reset from a non-suspended full-speed state, then the device begins a high-speed
--detection handshake after the detection of SE0 for no less than 2.5 ?s and no more than 3.0 ms
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Us = Const_2_5Us) then
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
end if;
else
u_Cnt1_Rst_Ms <= '1';
end if;
else
u_Cnt1_Rst_Ms <= '1';
end if;
when RST_RES_SUSP =>
state_ind_hs <= "00111";
if (u_Mode = '0') then
u_Negociation_Next_State <= SUSPEND;
elsif (u_Mode = '1') then
u_Negociation_Next_State <= SWITCH_FS;
end if;
--RESET sequence
when RESET => --Enter High-speed Detection Handshake. Select peripheral chirp by writing to the PHY FCR
state_ind_hs <= "01000";
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01010100"; --opmode = 10, xcvrselect = 00, termselect = 1
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= SEND_CHIRP_K;
end if;
when SEND_CHIRP_K =>
state_ind_hs <= "01001";
u_Cnt1_Rst_Ms <= '0';
u_Send_NOPID_CMD <= '1'; --This will instruct the ULPI state machine to send NOPID_CMD with transmit data which is by default 00h (drive current into D-)
if (u_Cnt1_Ms = Const_1_2Ms) then --The device chirp must last no less than 1.0 ms (TUCH) and must end no more than 7.0 ms (TUCHEND) high-speed Reset time T0.
u_Cnt1_Rst_Ms <= '1';
u_Send_Last <= '1';
u_Negociation_Next_State <= SEND_CHIRP_K_LAST;
end if;
when SEND_CHIRP_K_LAST =>
state_ind_hs <= "01010";
--u_Tx_Data <= (others => '0');
u_Cnt1_Rst_Ms <= '1';
if (u_Rx_Cmd_Received = '1') then
if (u_RX_SE0 = '1') then
u_Negociation_Next_State <= WAIT_CHIRP_SE0;
end if;
end if;
--------------------------------------------------------------
when WAIT_CHIRP_SE0 =>
state_ind_hs <= "01011";
u_Cnt1_Rst_Ms <= '0'; -- monitor JK timeout
if (u_RX_K = '1') then
u_Cnt1_Rst_Ms <= '0';
u_Cnt2_Rst_Ms <= '0'; -- monitor chirp duration
u_Negociation_Next_State <= WAIT_CHIRP_K;
elsif (u_Cnt1_Ms = Const_2_5Ms) then
u_Set_Mode_FS <= '1';
u_Negociation_Next_State <= SET_FS;
end if;
--------------------------------------------------------------
when WAIT_CHIRP_K =>
state_ind_hs <= "01100";
u_Cnt_Chirp_Rst <= '0';
u_Cnt1_Rst_Ms <= '0'; -- monitor JK timeout
if (u_RX_K = '1') then
u_Cnt2_Rst_Ms <= '0'; -- monitor chirp duration
if (u_Cnt2_Us = Const_2_5Us) then
if(u_Cnt_Chirp > 5) then
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Cnt_Chirp_Rst <= '1';
u_Cnt_Chirp_CE <= '0';
u_Negociation_Next_State <= SET_HS;
else
u_Cnt_Chirp_CE <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Negociation_Next_State <= WAIT_CHIRP_J;
end if;
end if;
elsif (u_Cnt1_Ms = Const_2_5Ms or u_RX_SE0 = '1') then
u_Send_REGW_CMD <= '1';
u_Cnt1_Rst_Ms <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Set_Mode_FS <= '1';
u_Negociation_Next_State <= SET_FS;
end if;
when WAIT_CHIRP_J =>
state_ind_hs <= "01101";
u_Cnt1_Rst_Ms <= '0'; -- monitor JK timeout
u_Cnt_Chirp_Rst <= '0';
if (u_RX_J = '1') then
u_Cnt2_Rst_Ms <= '0'; -- monitor chirp duration
if (u_Cnt2_Us = Const_2_5Us) then
if(u_Cnt_Chirp > 5) then
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Cnt_Chirp_Rst <= '1';
u_Cnt_Chirp_CE <= '0';
u_Negociation_Next_State <= SET_HS;
else
u_Cnt2_Rst_Ms <= '1';
u_Cnt_Chirp_CE <= '1';
u_Negociation_Next_State <= WAIT_CHIRP_K;
end if;
end if;
elsif (u_Cnt1_Ms = Const_2_5Ms or u_RX_SE0 = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Cnt2_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "00000101"; --opmode = 00, xcvrselect = 00, termselect = 1
u_Set_Mode_FS <= '1';
u_Negociation_Next_State <= SET_FS;
end if;
when SET_FS =>
state_ind_hs <= "01110";
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000101"; --opmode = 00, xcvrselect = 01, termselect = 1
u_Send_REGW_CMD <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Done_Set <= '1';
u_Negociation_Next_State <= NORMAL;
end if;
when SET_HS =>
state_ind_hs <= "01111";
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000000"; --opmode = 00, xcvrselect = 00, termselect = 0
u_Set_Mode_HS_Loc <= '1';
u_Send_REGW_CMD <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Done_Set <= '1';
u_Negociation_Next_State <= NORMAL;
end if;
---SUSPEND/RESUME -- Not Tested!
when SWITCH_FS => -- Select peripherla Full Speed by writing to FCR
u_Negociation_Done_Rst <= '0';
state_ind_hs <= "10000";
u_Cnt1_Rst_Ms <= '0';
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg write addr
u_Tx_Regw_Data <= "01000101"; --opmode = 00, xcvrselect = 01, termselect = 1
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= SUSP_RES;
end if;
when SUSP_RES =>
state_ind_hs <= "10001";
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_200Us) then --The device samples the bus state, and checks for SE0 (reset as opposed to suspend), no less than 100 �s and no more than 875 �s (TWTRSTHS) after starting reversion to full-speed.
if( u_RX_SE0 = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
elsif (u_RX_J = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= SUSPEND;
else
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= DISCONNECTED;
end if;
end if;
when SUSPEND =>
state_ind_hs <= "10010";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100"; --u_Tx_Data (6 downto 0) = function control reg set addr
u_Tx_Regw_Data <= "00010101"; --set suspendM
if (u_Tx_Cmd_Done = '1') then
if (u_Mode = '1') then
u_Negociation_Next_State <= HS_SUSPEND;
else
u_Negociation_Next_State <= FS_SUSPEND;
end if;
end if;
when FS_SUSPEND =>
state_ind_hs <= "10011";
if (u_RX_K = '1') then
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_20Ms) then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= FS_WAIT_SE0;
end if;
elsif (u_RX_SE0 = '1')then
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Us = Const_2_5Us) then
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
end if;
elsif (u_Remote_Wake = '1') then -- 3ms to enter suspend + 2ms
u_Send_STP_CMD <= '1';
u_Negociation_Next_State <= CLEAR_SUSPEND;
else
u_Cnt1_Rst_Ms <= '1';
end if;
when HS_SUSPEND =>
state_ind_hs <= "10100";
if (u_RX_K = '1') then
u_Cnt1_Rst_Ms <= '0';
state_ind_hs <= "11110";
if (u_Cnt1_Ms = Const_20Ms) then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= WAIT_HSEOP;
end if;
elsif (u_RX_SE0 = '1')then
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Us = Const_2_5Us) then
state_ind_hs <= "11101";
u_Cnt1_Rst_Ms <= '1';
u_Send_REGW_CMD <= '1';
u_Negociation_Next_State <= RESET;
end if;
elsif (u_Remote_Wake = '1') then -- 3ms to enter suspend + 2ms
u_Send_STP_CMD <= '1';
u_Negociation_Next_State <= CLEAR_SUSPEND;
else
state_ind_hs <= "11100";
u_Cnt1_Rst_Ms <= '1';
end if;
when FS_WAIT_SE0 =>
state_ind_hs <= "10101";
if (u_RX_SE0 = '1') then
u_Negociation_Next_State <= FS_WAIT_J;
end if;
when FS_WAIT_J =>
state_ind_hs <= "10110";
if (u_RX_J = '1') then
u_Send_REGW_CMD <= '1';
u_Set_Mode_FS <= '1';
u_Wake <= '1';
u_Negociation_Next_State <= SET_FS;
else
u_Negociation_Next_State <= ERROR;
end if;
when WAIT_HSEOP =>
state_ind_hs <= "10111";
if (u_RX_SE0 = '1') then
u_Send_REGW_CMD <= '1';
u_Wake <= '1';
u_Negociation_Next_State <= SET_HS;
end if;
when CLEAR_SUSPEND =>
state_ind_hs <= "11001";
u_Send_REGW_CMD <= '1';
u_Tx_Reg_Addr(5 downto 0) <= "000100";
u_Tx_Regw_Data <= "01010101";
if (u_Tx_Cmd_Done = '1') then
u_Negociation_Next_State <= SIGNAL_WAKE;
end if;
when SIGNAL_WAKE =>
state_ind_hs <= "11010";
u_Send_NOPID_CMD <= '1';
u_Tx_Data <= "11111111";
u_Cnt1_Rst_Ms <= '0';
if (u_Cnt1_Ms = Const_10Ms) then
u_Send_Last <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Cnt1_Rst_Ms <= '1';
u_Negociation_Next_State <= RESUME_REQ_WAIT;
end if;
end if;
when RESUME_REQ_WAIT =>
state_ind_hs <= "11011";
u_Cnt1_Rst_Ms <= '0';
if (u_RX_K = '1') then
u_Negociation_Next_State <= WAIT_HSEOP;
end if;
when others =>
u_Negociation_Next_State <= DISCONNECTED;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_stbs_set.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set;
architecture implementation of axi_datamover_stbs_set is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" | "00000010" | "00000100" | "00001000" |
"00010000" | "00100000" | "01000000" | "10000000" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" | "00000110" | "00001100" | "00011000" |
"00110000" | "01100000" | "11000000" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" | "00001110" | "00011100" | "00111000" |
"01110000" | "11100000" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" | "00011110" | "00111100" | "01111000" |
"11110000" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" | "00111110" | "01111100" | "11111000" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" | "01111110" | "11111100" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" | "11111110" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_128_STRB;
end implementation;
|
-- THIS FILE WAS GENERATED ON Tue Oct 30 13:46:44 2012 EDT
-- BASED ON THE FILE: bias_vhdl.xml
-- YOU PROBABLY SHOULD NOT EDIT IT
-- This file contains the implementation declarations for worker bias_vhdl
-- Interface definition signal names defined with pattern rule: "%s_"
-- OCP-based Control Interface, based on the WCI profile,
-- used for clk/reset, control and configuration
-- /\
-- /--\
-- +--------------------OCP----||----OCP---------------------------+
-- | \--/ |
-- | \/ |
-- | Entity: <worker> |
-- | |
-- O +------------------------------------------------------+ O
-- C | Entity: <worker>_worker | C
-- P | | P
-- | | This "inner layer" is the code you write, based | |
-- Data Input |\ | on definitions the in <worker>_worker_defs package, | |\ Data Output
-- Port based ==| \ | and the <worker>_worker entity, both in this file, | =| \ Port based
-- on the WSI ==| / | both in the "work" library. | =| / on the WSI
-- OCP Profile |/ | Package and entity declaration is this | |/ OCP Profile
-- O | <worker>_impl.vhd file. Architeture is in your | |
-- O | <worker>.vhd file | O
-- C | | C
-- P +------------------------------------------------------+ P
-- | |
-- | This outer layer is the "worker shell" code which |
-- | is automatically generated. The "worker shell" is |
-- | defined as the <worker> entity using definitions in |
-- | the <worker>_defs package. The worker shell is also |
-- | defined as a VHDL component in the <worker>_defs package, |
-- | as declared in the <worker>_defs.vhd file. |
-- | The worker shell "architecture" is also in this file, |
-- | as well as some subsidiary modules. |
-- +---------------------------------------------------------------+
-- This package defines types needed for the inner worker entity's generics or ports
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ocpi;
use ocpi.all; use ocpi.types.all;
package bias_vhdl_worker_defs is
-- The following record is for the writable properties of worker "bias_vhdl"
type worker_props_write_t is record
biasValue : ULong_t;
biasValue_written : Bool_t;
end record worker_props_write_t;
-- The following two records are for the inner/worker interfaces for port "ctl"
type worker_ctl_in_t is record
clk : std_logic; -- clock for this worker
reset : Bool_t; -- reset for this worker, at least 16 clocks long
control_op : wci.control_op_t; -- control op in progress, or no_op_e
state : wci.state_t; -- wci state: see state_t
is_operating : Bool_t; -- shorthand for state = operating_e
abort_control_op : Bool_t; -- demand that slow control op finish now
is_big_endian : Bool_t; -- for endian-switchable workers
end record worker_ctl_in_t;
type worker_ctl_out_t is record
done : Bool_t; -- is the pending prop access/config op done?
attention : Bool_t; -- worker wants attention
end record worker_ctl_out_t;
-- The following two records are for the inner/worker interfaces for port "in"
type worker_in_in_t is record
reset : Bool_t; -- this port is being reset from the outside peer
ready : Bool_t; -- this port is ready for data to be taken
-- one or more of: som, eom, valid are true
data : std_logic_vector(31 downto 0);
byte_enable : std_logic_vector(3 downto 0);
som, eom, valid : Bool_t; -- valid means data and byte_enable are present
end record worker_in_in_t;
type worker_in_out_t is record
take : Bool_t; -- take data now from this port
-- can be asserted when ready is true
end record worker_in_out_t;
-- The following two records are for the inner/worker interfaces for port "out"
type worker_out_in_t is record
reset : Bool_t; -- this port is being reset from the outside peer
ready : Bool_t; -- this port is ready for data to be given
end record worker_out_in_t;
type worker_out_out_t is record
give : Bool_t; -- give data now to this port
-- can be asserted when ready is true
data : std_logic_vector(31 downto 0);
byte_enable : std_logic_vector(3 downto 0);
som, eom, valid : Bool_t; -- one or more must be true when 'give' is asserted
end record worker_out_out_t;
end package bias_vhdl_worker_defs;
-- This is the entity to be implemented, depending on the above record types.
library ocpi; use ocpi.types.all;
library work; use work.bias_vhdl_worker_defs.all;
entity bias_vhdl_worker is
port(
-- Signals for control and configuration. See record types above.
ctl_in : in worker_ctl_in_t;
ctl_out : out worker_ctl_out_t;
-- Input values and strobes for this worker's writable properties
props_write : in worker_props_write_t;
-- Signals for WSI input port named "in". See record types above.
in_in : in worker_in_in_t;
in_out : out worker_in_out_t;
-- Signals for WSI output port named "out". See record types above.
out_in : in worker_out_in_t;
out_out : out worker_out_out_t);
end entity bias_vhdl_worker;
-- The rest of the file below here is the implementation of the worker shell
-- which surrounds the entity to be implemented, above.
-- Worker-specific definitions that are needed outside entities below
package body bias_vhdl_defs is
constant worker : ocpi.wci.worker_t := (5, "00000100");
constant properties : ocpi.wci.properties_t := (
0 => (32, 0, 3, 0, 1, true, true, false, false)
);
end bias_vhdl_defs;
-- This is the entity declaration that the worker developer will implement
-- The achitecture for this entity will be in the implementation file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ocpi;
use ocpi.all; use ocpi.types.all;
library work;
use work.all;
use work.bias_vhdl_defs.all;
entity bias_vhdl is
port (
-- The WCI interface named "ctl", with "bias_vhdl" acting as OCP slave:
-- WIP attributes for this WCI interface are:
-- Clock: this interface has its own clock, named "ctl_Clk"
-- SizeOfConfigSpace: 4 (0x4)
-- WritableConfigProperties: true
-- ReadableConfigProperties: true
-- Sub32BitConfigProperties: false
-- ControlOperations (in addition to the required "start"):
-- ResetWhileSuspended: true
ctl_Clk : in std_logic;
ctl_MAddr : in std_logic_vector(4 downto 0);
ctl_MAddrSpace : in std_logic_vector(0 downto 0);
ctl_MCmd : in std_logic_vector(2 downto 0);
ctl_MData : in std_logic_vector(31 downto 0);
ctl_MFlag : in std_logic_vector(1 downto 0);
ctl_MReset_n : in std_logic;
ctl_SData : out std_logic_vector(31 downto 0);
ctl_SFlag : out std_logic_vector(1 downto 0);
ctl_SResp : out std_logic_vector(1 downto 0);
ctl_SThreadBusy : out std_logic_vector(0 downto 0);
-- The WSI consumer interface named "in", with "bias_vhdl" acting as OCP slave:
-- WIP attributes for this WSI interface are:
-- Clock: uses the clock from interface named "ctl"
-- Protocol: "stream32"
-- DataValueWidth: 8
-- DataValueGranularity: 1
-- DiverseDataSizes: false
-- MaxMessageValues: 16380
-- NumberOfOpcodes: 256
-- Producer: false
-- VariableMessageLength: true
-- ZeroLengthMessages: true
-- Continuous: false
-- DataWidth: 32
-- ByteWidth: 8
-- ImpreciseBurst: true
-- Preciseburst: true
-- Abortable: false
-- EarlyRequest: false
-- No Clk signal here. The "in" interface uses "ctl_Clk" as clock
in_MBurstLength : in std_logic_vector(11 downto 0);
in_MByteEn : in std_logic_vector(3 downto 0);
in_MCmd : in std_logic_vector(2 downto 0);
in_MData : in std_logic_vector(31 downto 0);
in_MBurstPrecise : in std_logic;
in_MReqInfo : in std_logic_vector(7 downto 0);
in_MReqLast : in std_logic;
in_MReset_n : in std_logic;
in_SReset_n : out std_logic;
in_SThreadBusy : out std_logic_vector(0 downto 0);
-- The WSI producer interface named "out", with "bias_vhdl" acting as OCP master:
-- WIP attributes for this WSI interface are:
-- Clock: uses the clock from interface named "ctl"
-- Protocol: "stream32"
-- DataValueWidth: 8
-- DataValueGranularity: 1
-- DiverseDataSizes: false
-- MaxMessageValues: 16380
-- NumberOfOpcodes: 256
-- Producer: true
-- VariableMessageLength: true
-- ZeroLengthMessages: true
-- Continuous: false
-- DataWidth: 32
-- ByteWidth: 8
-- ImpreciseBurst: true
-- Preciseburst: true
-- Abortable: false
-- EarlyRequest: false
-- No Clk signal here. The "out" interface uses "ctl_Clk" as clock
out_SReset_n : in std_logic;
out_SThreadBusy : in std_logic_vector(0 downto 0);
out_MBurstLength : out std_logic_vector(11 downto 0);
out_MByteEn : out std_logic_vector(3 downto 0);
out_MCmd : out std_logic_vector(2 downto 0);
out_MData : out std_logic_vector(31 downto 0);
out_MBurstPrecise : out std_logic;
out_MReqInfo : out std_logic_vector(7 downto 0);
out_MReqLast : out std_logic;
out_MReset_n : out std_logic
);
-- Aliases for WCI interface "ctl"
alias ctl_Terminate : std_logic is ctl_MFlag(0);
alias ctl_Endian : std_logic is ctl_MFlag(1);
alias ctl_Config : std_logic is ctl_MAddrSpace(0);
alias ctl_Attention : std_logic is ctl_SFlag(0);
-- Constants for bias_vhdl's property addresses
subtype Property_t is std_logic_vector(4 downto 0);
constant biasValue : Property_t := b"00000"; -- 0x00
-- Aliases for interface "in"
subtype in_OpCode_t is std_logic_vector(7 downto 0);
alias in_Opcode: in_OpCode_t is in_MReqInfo(7 downto 0);
-- Opcode/operation value declarations for protocol "stream32" on interface "in"
constant in_data_Op : in_Opcode_t := b"00000000"; -- 0x00
-- Aliases for interface "out"
subtype out_OpCode_t is std_logic_vector(7 downto 0);
alias out_Opcode: out_OpCode_t is out_MReqInfo(7 downto 0);
-- Opcode/operation value declarations for protocol "stream32" on interface "out"
constant out_data_Op : out_Opcode_t := b"00000000"; -- 0x00
signal wci_reset : bool_t;
-- these signals provide the values of writable properties
signal biasValue_value : ULong_t;
signal biasValue_written : Bool_t;
signal wci_attention, wci_is_operating: Bool_t;
signal wci_is_big_endian, wci_abort_control_op, wci_done : Bool_t;
signal wci_control_op : wci.control_op_t;
signal wci_state : wci.state_t;
signal in_take : Bool_t;
signal in_ready : Bool_t;
signal in_reset : Bool_t; -- this port is being reset from the outside
signal in_data : std_logic_vector(31 downto 0);
signal in_byte_enable: std_logic_vector(3 downto 0);
signal in_som : Bool_t; -- valid eom
signal in_eom : Bool_t; -- valid som
signal in_valid : Bool_t; -- valid data
signal out_give : Bool_t;
signal out_ready : Bool_t;
signal out_reset : Bool_t; -- this port is being reset from the outside
signal out_data : std_logic_vector(31 downto 0);
signal out_byte_enable: std_logic_vector(3 downto 0);
signal out_som : Bool_t; -- valid eom
signal out_eom : Bool_t; -- valid som
signal out_valid : Bool_t; -- valid data
end entity bias_vhdl;
-- Here we define and implement the WCI interface module for this worker,
-- which can be used by the worker implementer to avoid all the OCP/WCI issues
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ocpi;
use ocpi.all; use ocpi.types.all;
library work;
use work.all; use work.bias_vhdl_defs.all;
entity bias_vhdl_wci is
port(
inputs : in ctl_in_t; -- signal bundle from wci interface
done : in bool_t := btrue; -- worker uses this to delay completion
attention : in bool_t := bfalse; -- worker indicates an attention condition
outputs : out wci.out_t; -- signal bundle to wci interface
reset : out bool_t; -- wci reset for worker
control_op : out wci.control_op_t; -- control op in progress, or no_op_e
state : out wci.state_t; -- wci state: see state_t
is_operating : out bool_t; -- shorthand for state==operating_e
is_big_endian : out bool_t; -- for endian-switchable workers
abort_control_op : out bool_t; -- forcible abort a control-op when
-- worker uses 'done' to delay it
-- Outputs for this worker's writable properties
biasValue_value : out ULong_t;
biasValue_written : out Bool_t
);
end entity;
architecture rtl of bias_vhdl_wci is
signal my_reset : bool_t; -- internal usage of output
-- signals for property reads and writes
signal offsets : wci.offset_a_t(0 to 0); -- offsets within each property
signal indices : wci.offset_a_t(0 to 0); -- array index for array properties
signal hi32 : bool_t; -- high word of 64 bit value
signal nbytes_1 : types.byte_offset_t; -- # bytes minus one being read/written
-- signals between the decoder and the writable property registers
signal write_enables : bool_array_t(0 to 0);
signal data : wci.data_a_t (0 to 0); -- data being written, right justified
-- signals between the decoder and the readback mux
signal read_enables : bool_array_t(0 to 0);
signal readback_data : wci.data_a_t(bias_vhdl_defs.properties'range);
-- internal signals between property registers and the readback mux
-- for those that are writable, readable, and not volatile
signal my_biasValue_value : ULong_t;
-- temp signal to workaround isim/fuse crash bug
signal wciAddr : std_logic_vector(31 downto 0);
begin
wciAddr(inputs.MAddr'range) <= inputs.MAddr;
wciAddr(31 downto inputs.MAddr'length) <= (others => '0');
outputs.SFlag(0) <= '1' when its(attention) else '0';
outputs.SFlag(1) <= '1'; -- worker is present
outputs.SThreadBusy(0) <= '0' when its(done) else '1';
my_reset <= to_bool(inputs.MReset_n = '0');
reset <= my_reset;
x : component wci.decoder
generic map(worker => bias_vhdl_defs.worker,
properties => bias_vhdl_defs.properties)
port map( ocp_in.Clk => inputs.Clk,
ocp_in.Maddr => wciAddr,
ocp_in.MAddrSpace(0) => inputs.MAddrSpace(0),
ocp_in.MByteEn => "0000",
ocp_in.MCmd => inputs.MCmd,
ocp_in.MData => inputs.MData,
ocp_in.MFlag => inputs.MFlag,
ocp_in.MReset_n => inputs.MReset_n,
done => done,
resp => outputs.SResp,
write_enables => write_enables,
read_enables => read_enables,
offsets => offsets,
indices => indices,
hi32 => hi32,
nbytes_1 => nbytes_1,
data_outputs => data,
control_op => control_op,
state => state,
is_operating => is_operating,
abort_control_op => abort_control_op,
is_big_endian => is_big_endian);
readback : component wci.readback
generic map(bias_vhdl_defs.properties)
port map( read_enables => read_enables,
data_inputs => readback_data,
data_output => outputs.SData);
biasValue : component ocpi.props.ULong_property
generic map(worker => bias_vhdl_defs.worker,
property => bias_vhdl_defs.properties(0))
port map( clk => inputs.Clk,
reset => my_reset,
write_enable => write_enables(0),
data => data(0)(31 downto 0),
value => my_biasValue_value,
written => biasValue_written);
biasValue_value <= my_biasValue_value;
biasValue_readback : component ocpi.props.read_ULong_property
generic map(worker => bias_vhdl_defs.worker,
property => bias_vhdl_defs.properties(0))
port map( value => my_biasValue_value,
data_out => readback_data(0));
end architecture rtl;
library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL;
library ocpi; use ocpi.types.all;
library work; use work.bias_vhdl_defs.all;
entity bias_vhdl_in_wsi is
port (-- Exterior OCP signals
ocp_in : in in_in_t;
ocp_out : out in_out_t;
-- Signals connected from the worker's WCI to this interface;
wci_clk : in std_logic;
wci_reset : in Bool_t;
-- Interior signals used by worker logic
reset : out Bool_t; -- this port is being reset from outside/peer
ready : out Bool_t; -- data can be taken
take : in Bool_t;
data : out std_logic_vector(31 downto 0);
byte_enable : out std_logic_vector(3 downto 0);
som, eom, valid : out Bool_t);
end entity;
architecture rtl of bias_vhdl_in_wsi is
signal fifo_full_n, fifo_empty_n : std_logic;
signal my_take, my_reset_n, my_enq : std_logic;
component FIFO2
generic (width : natural := 1; \guarded\ : natural := 1);
port( CLK : in std_logic;
RST : in std_logic;
D_IN : in std_logic_vector(width - 1 downto 0);
ENQ : in std_logic;
DEQ : in std_logic;
CLR : in std_logic;
FULL_N : out std_logic;
EMPTY_N : out std_logic;
D_OUT : out std_logic_vector(width - 1 downto 0));
end component FIFO2;
begin
my_take <= '1' when its(take) else '0';
my_enq <= '1' when ocp_in.MCmd = ocpi.ocp.MCmd_WRITE else '0';
my_reset_n <= '0' when wci_reset or (ocp_in.MReset_n = '0') else '1';
ready <= btrue when fifo_empty_n = '1' else bfalse;
fifo : FIFO2
generic map(width => 32)
port map( clk => wci_clk,
rst => my_reset_n,
d_in => ocp_in.MData,
enq => my_enq,
full_n => fifo_full_n,
d_out => data,
deq => my_take,
empty_n => fifo_empty_n,
clr => '0');
end architecture rtl;
library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL;
library ocpi; use ocpi.types.all;
library work; use work.bias_vhdl_defs.all;
entity bias_vhdl_out_wsi is
port (-- Exterior OCP signals
ocp_in : in out_in_t;
ocp_out : out out_out_t;
-- Signals connected from the worker's WCI to this interface;
wci_clk : in std_logic;
wci_reset : in Bool_t;
-- Interior signals used by worker logic
reset : out Bool_t; -- this port is being reset from outside/peer
ready : out Bool_t; -- data can be given
give : in Bool_t;
data : in std_logic_vector(31 downto 0);
byte_enable : in std_logic_vector(3 downto 0);
som, eom, valid : in Bool_t);
end entity;
architecture rtl of bias_vhdl_out_wsi is
signal my_reset : Bool_t;
begin
my_reset <= wci_reset or (ocp_in.SReset_n = '0');
reset <= my_reset;
reg: process(wci_clk) is begin
if rising_edge(wci_clk) then
if its(my_reset) then
ready <= bfalse;
else
ready <= not to_bool(ocp_in.SThreadBusy(0));
end if;
end if;
end process;
ocp_out.MCmd <= ocpi.ocp.MCmd_WRITE when its(give) else ocpi.ocp.MCmd_IDLE;
ocp_out.MData <= data;
ocp_out.MReqLast <= '1' when its(eom) else '0';
ocp_out.MBurstLength <=
std_logic_vector(to_unsigned(1,ocp_out.MBurstLength'length)) when its(eom)
else std_logic_vector(to_unsigned(2, ocp_out.MBurstLength'length));
ocp_out.MByteEn <= byte_enable;
end architecture rtl;
library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.types.all; -- remove this to avoid all ocpi name collisions
architecture rtl of bias_vhdl is
signal unused : std_logic_vector(3 downto 0);
begin
-- This instantiates the WCI/Control module/entity generated in the *_impl.vhd file
-- With no user logic at all, this implements writable properties.
wci : entity bias_vhdl_wci
port map(-- These first signals are just for use by the wci module, not the worker
inputs.Clk => ctl_Clk,
inputs.MAddr => ctl_MAddr,
inputs.MAddrSpace => ctl_MAddrSpace,
inputs.MCmd => ctl_MCmd,
inputs.MData => ctl_MData,
inputs.MFlag => ctl_MFlag,
inputs.MReset_n => ctl_MReset_n,
outputs.SData => ctl_SData, outputs.SResp => ctl_SResp,
outputs.SFlag => ctl_SFlag, outputs.SThreadBusy => ctl_SThreadBusy,
-- These are outputs used by the worker logic
reset => wci_reset, -- OCP guarantees 16 clocks of reset
control_op => wci_control_op,
state => wci_state,
is_operating => wci_is_operating,
is_big_endian => wci_is_big_endian,
done => wci_done,
attention => wci_attention,
abort_control_op => wci_abort_control_op, -- use this to know when we are running
-- These are outputs to the worker for writable property values.
biasValue_value => biasValue_value,
biasValue_written => biasValue_written
);
--
-- The WSI interface helper component instance for port "in"
in_port : entity bias_vhdl_in_wsi
port map(-- These signals connect this component to the external OCP interface
ocp_in.MBurstLength => in_MBurstLength,
ocp_in.MBurstPrecise => in_MBurstPrecise,
ocp_in.MByteEn => in_MByteEn,
ocp_in.MCmd => in_MCmd,
ocp_in.MData => in_MData,
ocp_in.MReqInfo => in_MReqInfo,
ocp_in.MReqLast => in_MReqLast,
ocp_in.MReset_n => in_MReset_n,
ocp_out.SReset_n => in_SReset_n,
ocp_out.SThreadBusy => in_SThreadBusy,
-- These signals are just connected to the WCI
wci_clk => ctl_Clk,
wci_reset => wci_reset,
-- This signal is the only input from worker code
take => in_take,
-- Output signals from this component into the worker
reset => in_reset, -- this port is being reset from the outside
ready => in_ready,
data => in_data,
byte_enable => in_byte_enable,
som => in_som, -- valid eom
eom => in_eom, -- valid som
valid => in_valid); -- valid data
--
-- The WSI interface helper component instance for port "out"
out_port : entity bias_vhdl_out_wsi
port map(-- These signals connect this component to the external OCP interface
ocp_in.SReset_n => out_SReset_n,
ocp_in.SThreadBusy => out_SThreadBusy,
ocp_out.MBurstLength => out_MBurstLength,
ocp_out.MBurstPrecise => out_MBurstPrecise,
ocp_out.MByteEn => out_MByteEn,
ocp_out.MCmd => out_MCmd,
ocp_out.MData => out_MData,
ocp_out.MReqInfo => out_MReqInfo,
ocp_out.MReqLast => out_MReqLast,
ocp_out.MReset_n => out_MReset_n,
-- These signals are just connected to the WCI
wci_clk => ctl_Clk,
wci_reset => wci_reset,
-- This signal is the control input from worker code
give => out_give,
-- Output signals from this component into the worker
reset => out_reset, -- this port is being reset from the outside
ready => out_ready,
data => out_data,
byte_enable => out_byte_enable,
som => out_som, -- valid eom
eom => out_eom, -- valid som
valid => out_valid); -- valid data
bias_vhdl : entity bias_vhdl_worker
port map(
ctl_in.clk => ctl_Clk, ctl_in.reset => wci_reset,
ctl_in.control_op => wci_control_op,
ctl_in.state => wci_state,
ctl_in.is_operating => wci_is_operating,
ctl_in.abort_control_op => wci_abort_control_op,
ctl_in.is_big_endian => wci_is_big_endian,
ctl_out.done => wci_done, ctl_out.attention => wci_attention,
in_in.reset => in_reset,
in_in.ready => in_ready,
in_in.data => in_data,
in_in.byte_enable => in_byte_enable,
in_in.som => in_som,
in_in.eom => in_eom,
in_in.valid => in_valid,
in_out.take => in_take,
out_in.reset => out_reset,
out_in.ready => out_ready,
out_out.give => out_give, out_out.data => out_data,
out_out.byte_enable => out_byte_enable,
out_out.som => out_som,
out_out.eom => out_eom,
out_out.valid => out_valid,
props_write.biasValue => biasValue_value,
props_write.biasValue_written => biasValue_written);
end rtl;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in /= '0') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (reconfig_cx_in /= '1') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Cx_reconf_PE)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (Temp_Cx_in /= Cx_reconf_PE) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in /= '0') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (reconfig_cx_in /= '1') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Cx_reconf_PE)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (Temp_Cx_in /= Cx_reconf_PE) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in /= '0') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (reconfig_cx_in /= '1') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Cx_reconf_PE)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (Temp_Cx_in /= Cx_reconf_PE) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in /= '0') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (reconfig_cx_in /= '1') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Cx_reconf_PE)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (Temp_Cx_in /= Cx_reconf_PE) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in /= '0') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (reconfig_cx_in /= '1') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Cx_reconf_PE)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (Temp_Cx_in /= Cx_reconf_PE) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in /= '0') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (reconfig_cx_in /= '1') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Cx_reconf_PE)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (Temp_Cx_in /= Cx_reconf_PE) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in /= '0') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (reconfig_cx_in /= '1') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Cx_reconf_PE)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (Temp_Cx_in /= Cx_reconf_PE) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in /= '0') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (reconfig_cx_in /= '1') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Cx_reconf_PE)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (Temp_Cx_in /= Cx_reconf_PE) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added
Reconfig_command : in std_logic; -- newly added
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in /= '0') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (reconfig_cx_in /= '1') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (not changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Cx_reconf_PE)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '1') and (Temp_Cx_in /= Cx_reconf_PE) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal <= '0';
end if;
end process;
-- Checked (changed)!
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Reconfig_command, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Reconfig_command = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
-- Checked (Added) !
end; |
-------------------------------------------------------------------------------
--
-- File: MIPI_CSI2_RxTop.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mipi_csi2_rx_top is
Generic (
kVersionMajor : natural := 0; -- TCL-propagated from VLNV
kVersionMinor : natural := 0; -- TCL-propagated from VLNV
kTargetDT : string := "RAW10";
kGenerateAXIL : boolean := false;
kDebug : boolean := true;
--PPI
kLaneCount : natural range 1 to 4 := 2; --[1,2,4]
--Video Format
C_M_AXIS_COMPONENT_WIDTH : natural := 10; -- [8,10]
C_M_AXIS_TDATA_WIDTH : natural := 40;
C_M_MAX_SAMPLES_PER_CLOCK : natural := 4;
-- Parameters of Axi Slave Bus Interface S_AXI_LITE
C_S_AXI_LITE_DATA_WIDTH : integer := 32;
C_S_AXI_LITE_ADDR_WIDTH : integer := 4
);
Port (
--PPI
RxByteClkHS : in STD_LOGIC;
aClkStopstate : in std_logic;
aRxClkActiveHS : in std_logic;
RxDataHSD0 : in STD_LOGIC_VECTOR (7 downto 0);
RxSyncHSD0 : in STD_LOGIC;
RxValidHSD0 : in STD_LOGIC;
RxActiveHSD0 : in STD_LOGIC;
aD0Enable : out STD_LOGIC;
RxDataHSD1 : in STD_LOGIC_VECTOR (7 downto 0);
RxSyncHSD1 : in STD_LOGIC;
RxValidHSD1 : in STD_LOGIC;
RxActiveHSD1 : in STD_LOGIC;
aD1Enable : out STD_LOGIC;
RxDataHSD2 : in STD_LOGIC_VECTOR (7 downto 0);
RxSyncHSD2 : in STD_LOGIC;
RxValidHSD2 : in STD_LOGIC;
RxActiveHSD2 : in STD_LOGIC;
aD2Enable : out STD_LOGIC;
RxDataHSD3 : in STD_LOGIC_VECTOR (7 downto 0);
RxSyncHSD3 : in STD_LOGIC;
RxValidHSD3 : in STD_LOGIC;
RxActiveHSD3 : in STD_LOGIC;
aD3Enable : out STD_LOGIC;
aClkEnable : out STD_LOGIC;
--axi stream signals
m_axis_video_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_video_tvalid : out std_logic;
m_axis_video_tready : in std_logic;
m_axis_video_tlast : out std_logic;
m_axis_video_tuser : out std_logic_vector(0 downto 0);
video_aresetn : in std_logic; --available when the AXI-Lite interface is disabled
video_aclk : in std_logic;
-- Ports of Axi Slave Bus Interface S_AXI_LITE
s_axi_lite_aclk : in std_logic;
s_axi_lite_aresetn : in std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_awprot : in std_logic_vector(2 downto 0);
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_wstrb : in std_logic_vector((C_S_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_arprot : in std_logic_vector(2 downto 0);
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic
);
end mipi_csi2_rx_top;
architecture Behavioral of mipi_csi2_rx_top is
constant kMaxLaneCount : natural := 4;
signal rbRxDataHS : STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
signal rbRxSyncHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbRxValidHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbRxActiveHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal aDEnable : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal xSoftEnable, xSoftRst, vSoftEnable, vSoftRst, vRst_n : std_logic;
begin
InputDataGen: for i in 0 to kLaneCount-1 generate
DataLane0: if i = 0 generate
rbRxDataHS(8 * (i + 1) - 1 downto 8 * i) <= RxDataHSD0;
rbRxValidHS(i) <= RxValidHSD0;
rbRxActiveHS(i) <= RxActiveHSD0;
rbRxSyncHS(i) <= RxSyncHSD0;
aD0Enable <= aDEnable(i);
end generate;
DataLane1: if i = 1 generate
rbRxDataHS(8 * (i + 1) - 1 downto 8 * i) <= RxDataHSD1;
rbRxValidHS(i) <= RxValidHSD1;
rbRxActiveHS(i) <= RxActiveHSD1;
rbRxSyncHS(i) <= RxSyncHSD1;
aD1Enable <= aDEnable(i);
end generate;
DataLane2: if i = 2 generate
rbRxDataHS(8 * (i + 1) - 1 downto 8 * i) <= RxDataHSD2;
rbRxValidHS(i) <= RxValidHSD2;
rbRxActiveHS(i) <= RxActiveHSD2;
rbRxSyncHS(i) <= RxSyncHSD2;
aD2Enable <= aDEnable(i);
end generate;
DataLane3: if i = 3 generate
rbRxDataHS(8 * (i + 1) - 1 downto 8 * i) <= RxDataHSD3;
rbRxValidHS(i) <= RxValidHSD3;
rbRxActiveHS(i) <= RxActiveHSD3;
rbRxSyncHS(i) <= RxSyncHSD3;
aD3Enable <= aDEnable(i);
end generate;
end generate InputDataGen;
MIPI_CSI2_Rx_inst: entity work.MIPI_CSI2_Rx
Generic map(
kTargetDT => kTargetDT,
kDebug => kDebug,
--PPI
kLaneCount => kLaneCount, --[1,2,4]
--Video Format
C_M_AXIS_COMPONENT_WIDTH => C_M_AXIS_COMPONENT_WIDTH, -- [8,10]
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_MAX_SAMPLES_PER_CLOCK => C_M_MAX_SAMPLES_PER_CLOCK
)
Port map(
--PPI
RxByteClkHS => RxByteClkHS,
aClkStopstate => aClkStopstate,
aRxClkActiveHS => aRxClkActiveHS,
rbRxDataHS => rbRxDataHS,
rbRxSyncHS => rbRxSyncHS,
rbRxValidHS => rbRxValidHS,
rbRxActiveHS => rbRxActiveHS,
aDEnable => aDEnable,
aClkEnable => aClkEnable,
--axi stream signals
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tlast => m_axis_video_tlast,
m_axis_video_tuser => m_axis_video_tuser,
video_aresetn => vRst_n,
video_aclk => video_aclk,
vEnable => vSoftEnable
);
-------------------------------------------------------------------------------
-- AXI-Lite interface for control and status
-------------------------------------------------------------------------------
YesAXILITE: if kGenerateAXIL generate
AXI_Lite_Control: entity work.MIPI_CSI_2_RX_S_AXI_LITE
generic map (
kVersionMajor => kVersionMajor,
kVersionMinor => kVersionMinor,
C_S_AXI_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH
)
port map (
xEnable => xSoftEnable,
xRst => xSoftRst,
S_AXI_ACLK => s_axi_lite_aclk,
S_AXI_ARESETN => s_axi_lite_aresetn,
S_AXI_AWADDR => s_axi_lite_awaddr,
S_AXI_AWPROT => s_axi_lite_awprot,
S_AXI_AWVALID => s_axi_lite_awvalid,
S_AXI_AWREADY => s_axi_lite_awready,
S_AXI_WDATA => s_axi_lite_wdata,
S_AXI_WSTRB => s_axi_lite_wstrb,
S_AXI_WVALID => s_axi_lite_wvalid,
S_AXI_WREADY => s_axi_lite_wready,
S_AXI_BRESP => s_axi_lite_bresp,
S_AXI_BVALID => s_axi_lite_bvalid,
S_AXI_BREADY => s_axi_lite_bready,
S_AXI_ARADDR => s_axi_lite_araddr,
S_AXI_ARPROT => s_axi_lite_arprot,
S_AXI_ARVALID => s_axi_lite_arvalid,
S_AXI_ARREADY => s_axi_lite_arready,
S_AXI_RDATA => s_axi_lite_rdata,
S_AXI_RRESP => s_axi_lite_rresp,
S_AXI_RVALID => s_axi_lite_rvalid,
S_AXI_RREADY => s_axi_lite_rready
);
CoreSoftReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => xSoftRst,
OutClk => video_aclk,
oRst => vSoftRst);
SyncAsyncClkEnable: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0', --lane-level enable
aIn => xSoftEnable,
OutClk => video_aclk,
oOut => vSoftEnable);
GlitchFreeReset: process(video_aclk)
begin
if Rising_Edge(video_aclk) then
vRst_n <= video_aresetn and not vSoftRst; --combinational logic can produce glitches
end if;
end process;
end generate;
NoAXILITE: if not kGenerateAXIL generate
vSoftEnable <= '1';
vRst_n <= video_aresetn;
end generate;
end Behavioral;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:02 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/RAT_Counter10bit_0_0_stub.vhdl
-- Design : RAT_Counter10bit_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_Counter10bit_0_0 is
Port (
Din : in STD_LOGIC_VECTOR ( 0 to 9 );
LOAD : in STD_LOGIC;
INC : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR ( 0 to 9 )
);
end RAT_Counter10bit_0_0;
architecture stub of RAT_Counter10bit_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Din[0:9],LOAD,INC,RESET,CLK,COUNT[0:9]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "Counter10bit,Vivado 2016.4";
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Data bit connections on display:
--
-- --0--
-- | |
-- 1 2
-- | |
-- --3--
-- | |
-- 4 5
-- | |
-- --6-- [7] (dot)
entity seg7 is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
-- special display modes
error_i : in std_logic;
stop_i : in std_logic;
-- register access
data_i : in std_logic_vector(7 downto 0);
write_mode_i : in std_logic;
write_raw_i : std_logic_vector(3 downto 0);
write_hex_i : std_logic_vector(1 downto 0);
-- display output
cathode_o : out std_logic_vector(7 downto 0);
anode_o : out std_logic_vector(3 downto 0)
);
end seg7;
architecture behavioral of seg7 is
-- registers
signal reg_mode : std_logic_vector(1 downto 0);
signal reg_raw : std_logic_vector(31 downto 0);
signal reg_hex : std_logic_vector(15 downto 0);
-- delay counter
signal delay_counter : std_logic_vector(14 downto 0);
signal delay_counter_done : std_logic;
-- current digit
signal digit_counter : std_logic_vector(1 downto 0);
signal digit_raw : std_logic_vector(7 downto 0);
signal digit_hex : std_logic_vector(3 downto 0);
-- output
signal cathode : std_logic_vector(7 downto 0);
signal anode : std_logic_vector(3 downto 0);
signal cathode_delay1 : std_logic_vector(7 downto 0);
signal anode_delay1 : std_logic_vector(3 downto 0);
begin
-- registers
reg_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_mode <= (others => '0');
reg_raw <= (others => '0');
reg_hex <= (others => '0');
else
reg_mode <= reg_mode;
reg_raw <= reg_raw;
reg_hex <= reg_hex;
if (write_mode_i = '1') then
reg_mode <= data_i(1 downto 0);
end if;
if (write_raw_i(3) = '1') then
reg_raw(31 downto 24) <= data_i;
end if;
if (write_raw_i(2) = '1') then
reg_raw(23 downto 16) <= data_i;
end if;
if (write_raw_i(1) = '1') then
reg_raw(15 downto 8) <= data_i;
end if;
if (write_raw_i(0) = '1') then
reg_raw(7 downto 0) <= data_i;
end if;
if (write_hex_i(1) = '1') then
reg_hex(15 downto 8) <= data_i;
end if;
if (write_hex_i(0) = '1') then
reg_hex(7 downto 0) <= data_i;
end if;
end if;
end if;
end process;
-- delay counter
delay_counter_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
delay_counter <= (others => '0');
else
if (delay_counter = "111111111111111") then
delay_counter <= (others => '0');
else
delay_counter <= delay_counter + 1;
end if;
end if;
end if;
end process;
delay_counter_done_proc : process(delay_counter)
begin
if (delay_counter = "111111111111111") then
delay_counter_done <= '1';
else
delay_counter_done <= '0';
end if;
end process;
-- current digit
digit_counter_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
digit_counter <= (others => '0');
else
if (delay_counter_done = '1') then
digit_counter <= digit_counter + 1;
else
digit_counter <= digit_counter;
end if;
end if;
end if;
end process;
digit_proc : process(digit_counter, reg_raw, reg_hex)
begin
case (digit_counter) is
when "00" =>
digit_raw <= reg_raw(7 downto 0);
digit_hex <= reg_hex(3 downto 0);
when "01" =>
digit_raw <= reg_raw(15 downto 8);
digit_hex <= reg_hex(7 downto 4);
when "10" =>
digit_raw <= reg_raw(23 downto 16);
digit_hex <= reg_hex(11 downto 8);
when "11" =>
digit_raw <= reg_raw(31 downto 24);
digit_hex <= reg_hex(15 downto 12);
when others =>
digit_raw <= (others => '0');
digit_hex <= (others => '0');
end case;
end process;
-- output
cathode_o <= cathode_delay1;
anode_o <= anode_delay1;
delay_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
cathode_delay1 <= (others => '0');
anode_delay1 <= (others => '1');
else
cathode_delay1 <= cathode;
anode_delay1 <= anode;
end if;
end if;
end process;
anode_proc : process(digit_counter)
begin
case (digit_counter) is
when "00" => anode <= "1110";
when "01" => anode <= "1101";
when "10" => anode <= "1011";
when "11" => anode <= "0111";
when others => anode <= (others => '1');
end case;
end process;
cathode_proc : process(error_i, stop_i, digit_counter, reg_mode, digit_raw, digit_hex)
begin
if (error_i = '1') then
case (digit_counter) is
when "00" => cathode <= "11111111"; -- blank
when "01" => cathode <= "11100111"; -- r
when "10" => cathode <= "11100111"; -- r
when "11" => cathode <= "10100100"; -- E
when others => cathode <= (others => '1');
end case;
elsif (stop_i = '1') then
case (digit_counter) is
when "00" => cathode <= "11100000"; -- P
when "01" => cathode <= "10001000"; -- O
when "10" => cathode <= "10100101"; -- t
when "11" => cathode <= "10010100"; -- S
when others => cathode <= (others => '1');
end case;
else
if (reg_mode = "00") then
cathode <= not digit_raw;
else
if ((reg_mode = "01" and (digit_counter = "10" or digit_counter = "11")) or
(reg_mode = "10" and (digit_counter = "00" or digit_counter = "01"))) then
cathode <= not digit_raw;
else
case digit_hex is
when "0000" => cathode <= "10001000";
when "0001" => cathode <= "11011011";
when "0010" => cathode <= "10100010";
when "0011" => cathode <= "10010010";
when "0100" => cathode <= "11010001";
when "0101" => cathode <= "10010100";
when "0110" => cathode <= "10000100";
when "0111" => cathode <= "11011010";
when "1000" => cathode <= "10000000";
when "1001" => cathode <= "10010000";
when "1010" => cathode <= "11000000";
when "1011" => cathode <= "10000101";
when "1100" => cathode <= "10101100";
when "1101" => cathode <= "10000011";
when "1110" => cathode <= "10100100";
when "1111" => cathode <= "11100100";
when others => cathode <= (others => '1');
end case;
end if;
end if;
end if;
end process;
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hardware_interface is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0);
aclMISO : IN std_logic;
aclMOSI : OUT std_logic;
aclSCLK : OUT std_logic;
aclCS : OUT std_logic;
RGB1_Red : OUT std_logic;
RGB1_Green : OUT std_logic;
RGB1_Blue : OUT std_logic
);
end hardware_interface;
architecture Behavioral of hardware_interface is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component spi_accel port (
clk100MHz : in STD_LOGIC;
masterReset : in STD_LOGIC;
CS : out STD_LOGIC;
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
READY : out STD_LOGIC;
X_VAL : out STD_LOGIC_VECTOR(7 downto 0);
Y_VAL : out STD_LOGIC_VECTOR(7 downto 0);
Z_VAL : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component led_bright port(
clk : IN std_logic;
masterReset : IN std_logic;
ready : IN std_logic;
accel_val : IN std_logic_vector(7 downto 0);
pwm_out : OUT std_logic
);
end component;
component bcd_display port (
clk : in std_logic;
masterReset : in std_logic;
byte_in : in STD_LOGIC_VECTOR(7 downto 0);
bcd_val : out STD_LOGIC_VECTOR(11 downto 0)
);
end component;
--Central Button
signal masterReset : std_logic;
signal buttonLeft : std_logic;
signal buttonRight : std_logic;
signal buttonUp : std_logic;
signal buttonDown : std_logic;
signal displayLower : std_logic_vector(15 downto 0);
signal displayUpper : std_logic_vector(15 downto 0);
signal clockScalers : std_logic_vector (26 downto 0);
-- Component Signals
signal CS : std_logic := '1';
signal SCLK : std_logic := '0';
signal MOSI : std_logic := '0';
signal MISO : std_logic := '0';
signal READY : std_logic := '0';
signal X_VAL : std_logic_vector(7 downto 0) := (others => '0');
signal Y_VAL : std_logic_vector(7 downto 0) := (others => '0');
signal Z_VAL : std_logic_vector(7 downto 0) := (others => '0');
signal X_VAL_D : std_logic_vector(11 downto 0) := (others => '0');
signal Y_VAL_D : std_logic_vector(11 downto 0) := (others => '0');
signal Z_VAL_D : std_logic_vector(11 downto 0) := (others => '0');
signal X_PWM : std_logic := '0';
signal Y_PWM : std_logic := '0';
signal Z_PWM : std_logic := '0';
begin
--Central Button
masterReset <= pushButtons(4);
buttonLeft <= pushButtons(3);
buttonRight <= pushButtons(0);
buttonUp <= pushButtons(2);
buttonDown <= pushButtons(1);
LEDs (15 downto 8) <= clockScalers(26 downto 19);
--logic_analyzer (7 downto 0) <= clockScalers(26 downto 19);
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayLower (3 downto 0),
digit2_p => displayLower (7 downto 4),
digit3_p => displayLower (11 downto 8),
digit4_p => displayLower (15 downto 12),
digit5_p => displayUpper (3 downto 0),
digit6_p => displayUpper (7 downto 4),
digit7_p => displayUpper (11 downto 8),
digit8_p => displayUpper (15 downto 12)
);
m1 : spi_accel port map (clk100Mhz, masterReset, CS, SCLK, MOSI, MISO, READY, X_VAL, Y_VAL, Z_VAL);
logic_analyzer(0) <= clk100Mhz;
logic_analyzer(1) <= masterReset;
logic_analyzer(2) <= CS;
logic_analyzer(3) <= SCLK;
logic_analyzer(4) <= MOSI;
logic_analyzer(5) <= MISO;
logic_analyzer(6) <= READY;
--logic_analyzer(7) <= '0';
--Accel Linking
aclCS <= CS;
aclSCLK <= SCLk;
aclMOSI <= MOSI;
MISO <= aclMISO;
-- displayLower(15 downto 8) <= X_VAL;
-- displayLower(7 downto 0) <= Y_VAL;
-- displayUpper(7 downto 0) <= Z_VAL;
D1 : bcd_display port map (Ready, masterReset, X_VAL, X_VAL_D);
D2 : bcd_display port map (Ready, masterReset, Y_VAL, Y_VAL_D);
D3 : bcd_display port map (Ready, masterReset, Z_VAL, Z_VAL_D);
--PWM Linking
P1 : led_bright port map(clk100Mhz, masterReset, ready, X_VAL, X_PWM);
P2 : led_bright port map(clk100Mhz, masterReset, ready, Y_VAL, Y_PWM);
P3 : led_bright port map(clk100Mhz, masterReset, ready, Z_VAL, Z_PWM);
--LEDBAR and PWM Linking
process ( slideSwitches(15 downto 13) ) begin
if ( (slideSwitches(15) = '0') and (slideSwitches(14) = '0') and (slideSwitches(13) = '1')) then
LEDs(7 downto 0) <= Y_VAL;
displayLower(11 downto 0) <= Y_VAL_D;
logic_analyzer(7) <= Y_PWM;
RGB1_Red <= '0';
RGB1_Green <= Y_PWM;
RGB1_Blue <= '0';
elsif ( (slideSwitches(15) = '0') and (slideSwitches(14) = '1') and (slideSwitches(13) = '0')) then
LEDs(7 downto 0) <= X_VAL;
displayLower(11 downto 0) <= X_VAL_D;
logic_analyzer(7) <= X_PWM;
RGB1_Red <= X_PWM;
RGB1_Green <= '0';
RGB1_Blue <= '0';
elsif ( (slideSwitches(15) = '1') and (slideSwitches(14) = '0') and (slideSwitches(13) = '0')) then
LEDs(7 downto 0) <= Z_VAL;
displayLower(11 downto 0) <= Z_VAL_D;
logic_analyzer(7) <= Z_PWM;
RGB1_Red <= '0';
RGB1_Green <= '0';
RGB1_Blue <= Z_PWM;
elsif ( (slideSwitches(15) = '1') and (slideSwitches(14) = '1') and (slideSwitches(13) = '1')) then
LEDs(7 downto 0) <= "10101010";
RGB1_Red <= X_PWM;
RGB1_Green <= Y_PWM;
RGB1_Blue <= Z_PWM;
else
LEDs(7 downto 0) <= (others => '0');
RGB1_Red <= '0';
RGB1_Green <= '0';
RGB1_Blue <= '0';
end if;
end process;
end Behavioral; |
goes: entity e6
|
library ieee;
use ieee.std_logic_1164.all;
entity SyncREGn is
generic (n : integer := 4);
port(
Din : in std_logic_vector(n-1 downto 0);
EN : in std_logic;
C : in std_logic;
Dout : out std_logic_vector(n-1 downto 0)
);
end SyncREGn;
architecture behavior of SyncREGn is
signal reg : std_logic_vector(n-1 downto 0);
begin
main : process(Din, EN , C)
begin
if rising_edge(C) then
if EN='1' then
reg <= Din;
end if;
end if;
end process;
Dout <= reg;
end behavior;
architecture structual of SyncREGn is
component DET
port(D, E, C : in std_logic; Q: out std_logic);
end component DET;
begin
G_1 : for I in 0 to N-1 generate
DET_I :
DET port map
(Din(I), EN, C, Dout(I));
end generate;
end architecture structual;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 05-05-2016
-- Module Name: vending-machine.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity vending_machine is
port(coin_in : in std_logic;
coin_in_1 : in std_logic;
coin_in_10 : in std_logic;
coin_in_100 : in std_logic;
buy_in : in std_logic;
price : in std_logic_vector(7 downto 0);
coin_return : out std_logic;
coin_return_1 : out std_logic_vector(7 downto 0);
coin_return_10 : out std_logic_vector(7 downto 0);
coin_return_100 : out std_logic_vector(7 downto 0);
clk : in std_logic);
end entity;
architecture rtl of vending_machine is
type state is (COIN_IN_S, COIN_RETURN_100_S, COIN_RETURN_10_S, COIN_RETURN_1_S);
signal current_state, next_state : state;
begin
process (clk)
begin
if clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
process (coin_in, buy_in, current_state)
variable coin_return_total : std_logic_vector(7 downto 0);
variable coin_return_100_var : std_logic_vector(7 downto 0);
variable coin_return_10_var : std_logic_vector(7 downto 0);
variable coin_return_1_var : std_logic_vector(7 downto 0);
variable coin_in_total : std_logic_vector(7 downto 0);
begin
case current_state is
when COIN_IN_S =>
if coin_in = '1' then
coin_return <= '0';
next_state <= COIN_IN_S;
if coin_in_1 = '1' and coin_in_10 = '0' and coin_in_100 = '0' then
coin_in_total := coin_in_total + "00000001";
elsif coin_in_1 = '0' and coin_in_10 = '1' and coin_in_100 = '0' then
coin_in_total := coin_in_total + "00001010";
elsif coin_in_1 = '0' and coin_in_10 = '0' and coin_in_100 = '1' then
coin_in_total := coin_in_total + "01100100";
end if;
end if;
if buy_in = '1' then
coin_return_total := coin_in_total - price;
coin_return_100_var := "00000000";
coin_return_10_var := "00000000";
coin_return_1_var := "00000000";
next_state <= COIN_RETURN_100_S;
end if;
when COIN_RETURN_100_S =>
if coin_return_total >= "01100100" then
coin_return_total := coin_return_total - "01100100";
coin_return_100_var := coin_return_100_var + "00000001";
next_state <= COIN_RETURN_100_S;
else
next_state <= COIN_RETURN_10_S;
end if;
when COIN_RETURN_10_S =>
if coin_return_total >= "00001010" then
coin_return_total := coin_return_total - "00001010";
coin_return_10_var := coin_return_10_var + "00000001";
next_state <= COIN_RETURN_10_S;
else
next_state <= COIN_RETURN_1_S;
end if;
when COIN_RETURN_1_S =>
if coin_return_total >= "00000001" then
coin_return_total := coin_return_total - "00000001";
coin_return_1_var := coin_return_1_var + "00000001";
next_state <= COIN_RETURN_1_S;
else
next_state <= COIN_IN_S;
coin_return <= '1';
coin_return_1 <= coin_return_1_var;
coin_return_10 <= coin_return_10_var;
coin_return_100 <= coin_return_100_var;
end if;
end case;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2253.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02253ent IS
END c07s02b06x00p01n01i02253ent;
ARCHITECTURE c07s02b06x00p01n01i02253arch OF c07s02b06x00p01n01i02253ent IS
BEGIN
TESTING: PROCESS
-- file types.
type FileType is file of BIT;
-- Local declarations.
file FILEV : FileType is "input_file";
variable k : integer;
BEGIN
k := FILEV rem FILEV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02253 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02253arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2253.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02253ent IS
END c07s02b06x00p01n01i02253ent;
ARCHITECTURE c07s02b06x00p01n01i02253arch OF c07s02b06x00p01n01i02253ent IS
BEGIN
TESTING: PROCESS
-- file types.
type FileType is file of BIT;
-- Local declarations.
file FILEV : FileType is "input_file";
variable k : integer;
BEGIN
k := FILEV rem FILEV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02253 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02253arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2253.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02253ent IS
END c07s02b06x00p01n01i02253ent;
ARCHITECTURE c07s02b06x00p01n01i02253arch OF c07s02b06x00p01n01i02253ent IS
BEGIN
TESTING: PROCESS
-- file types.
type FileType is file of BIT;
-- Local declarations.
file FILEV : FileType is "input_file";
variable k : integer;
BEGIN
k := FILEV rem FILEV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02253 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02253arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
entity vga_sequencer is
generic (
display_rows : natural := 480;
display_cols : natural := 640
);
port (
clock : in std_logic; -- 100 MHz Clock
output_enable : out std_logic := '0';
-- TODO make this out natural range vga_memory'range;
read_address : out natural range vga_memory'range := 0;
hsync : out std_logic := '1';
vsync : out std_logic := '1'
);
end vga_sequencer;
architecture behavioural of vga_sequencer is
type sync_state is (SRead, SUpdate, SDelay1, SDelay2);
signal state : sync_state := SDelay1; -- Give the system time to get ready
constant H_PULSE_START : natural := display_cols + 16; -- front porch is 16 columns
constant H_PULSE_END: natural := H_PULSE_START + 96; -- Pulse is 96 columns
constant H_LINE_END: natural := H_PULSE_END + 48 - 1; -- back porch is 48 columns
constant V_PULSE_START : natural := display_rows + 10; -- front porch is 10 rows
constant V_PULSE_END: natural := V_PULSE_START + 2; -- Pulse is 2 rows
constant V_LINE_END: natural := V_PULSE_END + 33 - 1; -- back porch is 33 rows
signal h_count : natural range H_LINE_END downto 0 := 0;
signal v_count : natural range V_LINE_END downto 0 := 0;
begin
process(clock)
begin
if rising_edge(clock) then
case state is
when SRead =>
if h_count < display_cols and v_count < display_rows then
output_enable <= '1';
read_address <= v_count * display_cols + h_count;
else
output_enable <= '0';
read_address <= 0;
end if;
state <= SUpdate;
when SUpdate =>
if h_count >= H_PULSE_START and h_count < H_PULSE_END then
hsync <= '0';
else
hsync <= '1';
end if;
if v_count >= V_PULSE_START and v_count < V_PULSE_END then
vsync <= '0';
else
vsync <= '1';
end if;
-- UPDATE COUNTERS
if h_count = H_LINE_END then
h_count <= 0;
if v_count = V_LINE_END then
v_count <= 0;
else
v_count <= v_count + 1;
end if;
else -- not at a row/col border
h_count <= h_count + 1;
end if;
state <= SDelay1;
when SDelay1 =>
state <= SDelay2;
when SDelay2 =>
state <= SRead;
end case;
end if; -- end rising_edge if
end process;
end behavioural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
entity vga_sequencer is
generic (
display_rows : natural := 480;
display_cols : natural := 640
);
port (
clock : in std_logic; -- 100 MHz Clock
output_enable : out std_logic := '0';
-- TODO make this out natural range vga_memory'range;
read_address : out natural range vga_memory'range := 0;
hsync : out std_logic := '1';
vsync : out std_logic := '1'
);
end vga_sequencer;
architecture behavioural of vga_sequencer is
type sync_state is (SRead, SUpdate, SDelay1, SDelay2);
signal state : sync_state := SDelay1; -- Give the system time to get ready
constant H_PULSE_START : natural := display_cols + 16; -- front porch is 16 columns
constant H_PULSE_END: natural := H_PULSE_START + 96; -- Pulse is 96 columns
constant H_LINE_END: natural := H_PULSE_END + 48 - 1; -- back porch is 48 columns
constant V_PULSE_START : natural := display_rows + 10; -- front porch is 10 rows
constant V_PULSE_END: natural := V_PULSE_START + 2; -- Pulse is 2 rows
constant V_LINE_END: natural := V_PULSE_END + 33 - 1; -- back porch is 33 rows
signal h_count : natural range H_LINE_END downto 0 := 0;
signal v_count : natural range V_LINE_END downto 0 := 0;
begin
process(clock)
begin
if rising_edge(clock) then
case state is
when SRead =>
if h_count < display_cols and v_count < display_rows then
output_enable <= '1';
read_address <= v_count * display_cols + h_count;
else
output_enable <= '0';
read_address <= 0;
end if;
state <= SUpdate;
when SUpdate =>
if h_count >= H_PULSE_START and h_count < H_PULSE_END then
hsync <= '0';
else
hsync <= '1';
end if;
if v_count >= V_PULSE_START and v_count < V_PULSE_END then
vsync <= '0';
else
vsync <= '1';
end if;
-- UPDATE COUNTERS
if h_count = H_LINE_END then
h_count <= 0;
if v_count = V_LINE_END then
v_count <= 0;
else
v_count <= v_count + 1;
end if;
else -- not at a row/col border
h_count <= h_count + 1;
end if;
state <= SDelay1;
when SDelay1 =>
state <= SDelay2;
when SDelay2 =>
state <= SRead;
end case;
end if; -- end rising_edge if
end process;
end behavioural;
|
-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2013, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : hp_rc.vhd
-- MODULE NAME : DC Component Remover (High-pass RC filter)
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2013-06-20 Mihaita Nagy Created
-------------------------------------------------------------------------------
-- DESCRIPTION : Based on Xilinx's WP279 this module models a high-pass
-- first order RC filter.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_signed.all;
entity hp_rc is
port(
clk_i : in std_logic; -- 100 MHz
rst_i : in std_logic;
en_i : in std_logic; -- sampling frequency
data_i : in std_logic_vector(15 downto 0);
data_o : out std_logic_vector(15 downto 0)
);
end hp_rc;
architecture Behavioral of hp_rc is
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
constant D : integer range 1 to 32 := 32; -- fc = ~120 Hz, rolls off 24 dB for 40 Hz and lower
constant SHIFT_POS : integer := integer(ceil(log2(real(D))));
--constant MAX_SHIFT_POS : integer := 12; --
constant SIZE : integer := SHIFT_POS+16;
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal int_sub : std_logic_vector(16 downto 0) := (others => '0');
--signal int_sub : std_logic_vector((28-SHIFT_POS) downto 0) := (others => '0');
signal int_mult : std_logic_vector(SIZE downto 0) := (others => '0');
signal int_temp : std_logic_vector(SIZE downto 0) := (others => '0');
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- Subtracting only the integer part and discard the fractional part
-- of int_temp. The subtractor:
int_sub <= (data_i(15) & data_i) - int_temp(SIZE downto (SIZE-16));
-- Multiply by the power of two => right shift with log2 of the power
-- of two. Sign extending:
int_mult(SIZE downto (SIZE-SHIFT_POS)+1) <= (others => int_sub(16));
-- Right shifting:
int_mult((SIZE-SHIFT_POS) downto 0) <= int_sub;
-- Final output:
data_o <= int_sub(15 downto 0);
-- Integral part
Integrate: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
int_temp <= (others => '0');
else
if en_i = '1' then
int_temp <= int_temp + int_mult;
end if;
end if;
end if;
end process Integrate;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity TOP is
port (CLK, RESET: IN STD_LOGIC;
WE,RE,load : in std_logic;--delete after testing. this signals should be from control unit
dout:out std_logic;-- we get the decoded data
decisions:out std_logic_vector (3 downto 0));
end TOP;
----------------------------------------------------------
architecture Behavioralarch of TOP is
component INPUT_MEM is
port (CLK ,reset : in std_logic;
--CLR : in std_logic;
--WE : in std_logic;
--EN : in std_logic;
--INPUT_DI : in std_logic_vector(1 downto 0);
INPUT_DO : out std_logic_vector(1 downto 0));
end component;
-----------------------------------------------------------
component ACSunit is
port(din : IN std_logic_vector(1 downto 0);-- data input
RESET,CLK:IN std_logic;
outPM1,outPM2,outPM3,outPM4:out std_logic_vector (2 downto 0);-- path metric values
--dec1,dec2,dec3,dec4:out std_logic
decisions:out std_logic_vector (3 downto 0));--decisions of 4 ACS
end component;
-------------------------------------------------------------
component compar1 is
PORT(A,B,C,D:in std_logic_vector(2 downto 0);
code : out std_logic_vector(1 downto 0));
END component;
------------------------------------------------------------
component dec_mem is
port (CLK,reset : in std_logic;
WE : in std_logic;
RE : in std_logic;
--ADDR : in std_logic_vector(5 downto 0);
DI : in std_logic_vector(3 downto 0);
DO : out std_logic_vector(3 downto 0));
end component;
------------------------------------------------------------
component predictor is
port (rst,clk,din,load:in bit;
stateValue:in bit_vector(1 downto 0);
outStateValue:out integer range 0 to 3;
dout:out bit);
end component;
signal indata,cmp_op: std_logic_vector(1 downto 0);
signal outPM1,outPM2,outPM3,outPM4:std_logic_vector (2 downto 0);
signal mem_column_value : std_logic_vector (3 downto 0);
signal temp_outstate : integer range 0 to 3;
begin
memory : input_mem port map(clk,reset,indata);
mainacs : acsunit port map(indata,reset,clk,outPM1,outPM2,outPM3,outPM4,decisions);
comp_pm : compar1 port map (outPM1,outPM2,outPM3,outPM4,cmp_op);
decision_memory : dec_mem port map(CLK,RESET,WE,RE,decisions,mem_column_value);
predictor1 : predictor port map(reset,clk,mem_column_value(conv_integer(cmp_op)),load,cmp_op,temp_outstate,dout);
end Behavioralarch;
|
library ieee;
use ieee.std_logic_1164.all;
entity UC_transmissor is
port(liga : in std_logic;
enviar : in std_logic;
reset : in std_logic;
clock : in std_logic;
CTS : in std_logic;
DTR : out std_logic;
RTS : out std_logic;
enable_transmissao : out std_logic;
s_estado : out std_logic_vector(1 downto 0)); -- depuracao
end UC_transmissor;
architecture maq_estados of UC_transmissor is
type tipo_estado is (inicial, ligado, espera, transmissao);
signal estado : tipo_estado;
begin
process (clock, estado, reset, liga, enviar, CTS)
begin
if reset = '1' then
estado <= inicial;
elsif (clock'event and clock = '1') then
case estado is
when inicial =>
if liga = '1' then
estado <= ligado;
end if;
when ligado =>
if liga = '1' then
if enviar = '1' then
estado <= espera;
end if;
else
estado <= inicial;
end if;
when espera =>
if enviar = '1' then
if CTS = '1' then
estado <= transmissao;
end if;
else
estado <= ligado;
end if;
when transmissao =>
if enviar = '0' then
estado <= ligado;
end if;
end case;
end if;
end process;
process (estado)
begin
case estado is
when inicial =>
s_estado <= "00";
DTR <= '0';
RTS <= '0';
enable_transmissao <= '0';
when ligado =>
s_estado <= "01";
DTR <= '1';
RTS <= '0';
enable_transmissao <= '0';
when espera =>
s_estado <= "10";
DTR <= '1';
RTS <= '1';
enable_transmissao <= '0';
when transmissao =>
s_estado <= "10";
DTR <= '1';
RTS <= '1';
enable_transmissao <= '1';
end case;
end process;
end maq_estados;
|
entity slice1 is
end entity;
architecture test of slice1 is
function resolved (x : bit_vector) return bit;
subtype r_bit is resolved bit;
type r_bit_vector is array (natural range <>) of r_bit;
signal x : r_bit_vector(0 to 7);
signal y : r_bit_vector(7 downto 0);
begin
x(0 to 3) <= "1111";
x(4 to 2) <= (others => '0');
x(4 to 5) <= "00";
x(5 to 7) <= "111";
y(3 downto 0) <= "1111";
y(2 downto 4) <= (others => '0');
y(5 downto 4) <= "00";
y(7 downto 5) <= "111";
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CharRam is
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(10 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
clkb : in std_logic;
web : in std_logic;
addrb : in std_logic_vector(10 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end CharRam;
architecture BEHAVIORAL of CharRam is
-- Shared memory
type ram_type is array (0 to 2047) of std_logic_vector (7 downto 0);
shared variable RAM : ram_type := (
x"00", x"00", x"00", x"1c", x"22", x"02", x"1a", x"26", x"26", x"1c", x"00", x"00", x"00", x"1C", x"22", x"02",
x"00", x"00", x"00", x"08", x"14", x"22", x"22", x"3e", x"22", x"22", x"00", x"00", x"1A", x"2A", x"2A", x"1C",
x"00", x"00", x"00", x"3c", x"12", x"12", x"1c", x"12", x"12", x"3c", x"00", x"00", x"00", x"08", x"14", x"22",
x"00", x"00", x"00", x"1c", x"22", x"20", x"20", x"20", x"22", x"1c", x"00", x"00", x"22", x"3E", x"22", x"22",
x"00", x"00", x"00", x"3c", x"12", x"12", x"12", x"12", x"12", x"3c", x"00", x"00", x"00", x"3C", x"12", x"12",
x"00", x"00", x"00", x"3e", x"20", x"20", x"38", x"20", x"20", x"3e", x"00", x"00", x"1C", x"12", x"12", x"3C",
x"00", x"00", x"00", x"3e", x"20", x"20", x"38", x"20", x"20", x"20", x"00", x"00", x"00", x"1C", x"22", x"20",
x"00", x"00", x"00", x"1c", x"22", x"20", x"20", x"26", x"22", x"1c", x"00", x"00", x"20", x"20", x"22", x"1C",
x"00", x"00", x"00", x"22", x"22", x"22", x"3e", x"22", x"22", x"22", x"00", x"00", x"00", x"3C", x"12", x"12",
x"00", x"00", x"00", x"1c", x"08", x"08", x"08", x"08", x"08", x"1c", x"00", x"00", x"12", x"12", x"12", x"3C",
x"00", x"00", x"00", x"02", x"02", x"02", x"02", x"02", x"22", x"1c", x"00", x"00", x"00", x"3E", x"20", x"20",
x"00", x"00", x"00", x"22", x"24", x"28", x"30", x"28", x"24", x"22", x"00", x"00", x"38", x"20", x"20", x"3E",
x"00", x"00", x"00", x"20", x"20", x"20", x"20", x"20", x"20", x"3e", x"00", x"00", x"00", x"3E", x"20", x"20",
x"00", x"00", x"00", x"22", x"36", x"2a", x"2a", x"22", x"22", x"22", x"00", x"00", x"38", x"20", x"20", x"20",
x"00", x"00", x"00", x"22", x"22", x"32", x"2a", x"26", x"22", x"22", x"00", x"00", x"00", x"1E", x"20", x"20",
x"00", x"00", x"00", x"1c", x"22", x"22", x"22", x"22", x"22", x"1c", x"00", x"00", x"26", x"22", x"22", x"1E",
x"00", x"00", x"00", x"3c", x"22", x"22", x"3c", x"20", x"20", x"20", x"00", x"00", x"00", x"22", x"22", x"22",
x"00", x"00", x"00", x"1c", x"22", x"22", x"22", x"2a", x"24", x"1a", x"00", x"00", x"3E", x"22", x"22", x"22",
x"00", x"00", x"00", x"3c", x"22", x"22", x"3c", x"28", x"24", x"22", x"00", x"00", x"00", x"1C", x"08", x"08",
x"00", x"00", x"00", x"1c", x"22", x"20", x"1c", x"02", x"22", x"1c", x"00", x"00", x"08", x"08", x"08", x"1C",
x"00", x"00", x"00", x"3e", x"08", x"08", x"08", x"08", x"08", x"08", x"00", x"00", x"00", x"02", x"02", x"02",
x"00", x"00", x"00", x"22", x"22", x"22", x"22", x"22", x"22", x"1c", x"00", x"00", x"02", x"22", x"22", x"1C",
x"00", x"00", x"00", x"22", x"22", x"22", x"14", x"14", x"08", x"08", x"00", x"00", x"00", x"22", x"24", x"28",
x"00", x"00", x"00", x"22", x"22", x"22", x"22", x"2a", x"36", x"22", x"00", x"00", x"30", x"28", x"24", x"22",
x"00", x"00", x"00", x"22", x"22", x"14", x"08", x"14", x"22", x"22", x"00", x"00", x"00", x"20", x"20", x"20",
x"00", x"00", x"00", x"22", x"22", x"14", x"08", x"08", x"08", x"08", x"00", x"00", x"20", x"20", x"20", x"3E",
x"00", x"00", x"00", x"3e", x"02", x"04", x"08", x"10", x"20", x"3e", x"00", x"00", x"00", x"22", x"36", x"2A",
x"00", x"00", x"00", x"1c", x"10", x"10", x"10", x"10", x"10", x"1c", x"00", x"00", x"2A", x"22", x"22", x"22",
x"00", x"00", x"00", x"00", x"20", x"10", x"08", x"04", x"02", x"00", x"00", x"00", x"00", x"22", x"32", x"2A",
x"00", x"00", x"00", x"1c", x"04", x"04", x"04", x"04", x"04", x"1c", x"00", x"00", x"26", x"22", x"22", x"22",
x"00", x"00", x"00", x"08", x"1c", x"2a", x"08", x"08", x"08", x"08", x"00", x"00", x"00", x"3E", x"22", x"22",
x"00", x"00", x"00", x"00", x"08", x"10", x"3e", x"10", x"08", x"00", x"00", x"00", x"22", x"22", x"22", x"3E",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"3C", x"22", x"22",
x"00", x"00", x"00", x"08", x"08", x"08", x"08", x"08", x"00", x"08", x"00", x"00", x"3C", x"20", x"20", x"20",
x"00", x"00", x"00", x"14", x"14", x"14", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"1C", x"22", x"22",
x"00", x"00", x"00", x"14", x"14", x"3e", x"14", x"3e", x"14", x"14", x"00", x"00", x"22", x"2A", x"24", x"1A",
x"00", x"00", x"00", x"08", x"1e", x"28", x"1c", x"0a", x"3c", x"08", x"00", x"00", x"00", x"3C", x"22", x"22",
x"00", x"00", x"00", x"30", x"32", x"04", x"08", x"10", x"26", x"06", x"00", x"00", x"3C", x"28", x"24", x"22",
x"00", x"00", x"00", x"10", x"28", x"28", x"10", x"2a", x"24", x"1a", x"00", x"00", x"00", x"1C", x"22", x"10",
x"00", x"00", x"00", x"08", x"08", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"04", x"22", x"1C",
x"00", x"00", x"00", x"04", x"08", x"10", x"10", x"10", x"08", x"04", x"00", x"00", x"00", x"3E", x"08", x"08",
x"00", x"00", x"00", x"10", x"08", x"04", x"04", x"04", x"08", x"10", x"00", x"00", x"08", x"08", x"08", x"08",
x"00", x"00", x"00", x"00", x"08", x"2a", x"1c", x"1c", x"2a", x"08", x"00", x"00", x"00", x"22", x"22", x"22",
x"00", x"00", x"00", x"00", x"08", x"08", x"3e", x"08", x"08", x"00", x"00", x"00", x"22", x"22", x"22", x"1C",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"10", x"20", x"00", x"00", x"22", x"22", x"22",
x"00", x"00", x"00", x"00", x"00", x"00", x"3e", x"00", x"00", x"00", x"00", x"00", x"14", x"14", x"08", x"08",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"00", x"00", x"00", x"22", x"22", x"22",
x"00", x"00", x"00", x"00", x"02", x"04", x"08", x"10", x"20", x"00", x"00", x"00", x"2A", x"2A", x"36", x"22",
x"00", x"00", x"00", x"1c", x"22", x"26", x"2a", x"32", x"22", x"1c", x"00", x"00", x"00", x"22", x"22", x"14",
x"00", x"00", x"00", x"08", x"18", x"08", x"08", x"08", x"08", x"1c", x"00", x"00", x"08", x"14", x"22", x"22",
x"00", x"00", x"00", x"1c", x"22", x"02", x"1c", x"20", x"20", x"3e", x"00", x"00", x"00", x"22", x"22", x"14",
x"00", x"00", x"00", x"1c", x"22", x"02", x"04", x"02", x"22", x"1c", x"00", x"00", x"08", x"08", x"08", x"08",
x"00", x"00", x"00", x"04", x"0c", x"14", x"24", x"3e", x"04", x"04", x"00", x"00", x"00", x"3E", x"02", x"04",
x"00", x"00", x"00", x"3e", x"20", x"3c", x"02", x"02", x"22", x"1c", x"00", x"00", x"08", x"10", x"20", x"3E",
x"00", x"00", x"00", x"1c", x"20", x"20", x"3c", x"22", x"22", x"1c", x"00", x"00", x"00", x"38", x"20", x"20",
x"00", x"00", x"00", x"3e", x"02", x"04", x"08", x"10", x"20", x"20", x"00", x"00", x"20", x"20", x"20", x"38",
x"00", x"00", x"00", x"1c", x"22", x"22", x"1c", x"22", x"22", x"1c", x"00", x"00", x"00", x"20", x"20", x"10",
x"00", x"00", x"00", x"1c", x"22", x"22", x"1e", x"02", x"02", x"1c", x"00", x"00", x"08", x"04", x"02", x"02",
x"00", x"00", x"00", x"00", x"00", x"08", x"00", x"00", x"08", x"00", x"00", x"00", x"00", x"0E", x"02", x"02",
x"00", x"00", x"00", x"00", x"00", x"08", x"00", x"00", x"08", x"08", x"10", x"00", x"02", x"02", x"02", x"0E",
x"00", x"00", x"00", x"04", x"08", x"10", x"20", x"10", x"08", x"04", x"00", x"00", x"00", x"08", x"1C", x"2A",
x"00", x"00", x"00", x"00", x"00", x"3e", x"00", x"3e", x"00", x"00", x"00", x"00", x"08", x"08", x"08", x"08",
x"00", x"00", x"00", x"10", x"08", x"04", x"02", x"04", x"08", x"10", x"00", x"00", x"00", x"00", x"08", x"10",
x"00", x"00", x"00", x"1c", x"22", x"02", x"04", x"08", x"00", x"08", x"00", x"00", x"3E", x"10", x"08", x"00",
x"00", x"00", x"00", x"08", x"14", x"22", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"1c", x"02", x"1e", x"22", x"1e", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"20", x"20", x"2c", x"32", x"22", x"32", x"2c", x"00", x"00", x"00", x"08", x"08", x"08",
x"00", x"00", x"00", x"00", x"00", x"1c", x"22", x"20", x"22", x"1c", x"00", x"00", x"08", x"08", x"00", x"08",
x"00", x"00", x"00", x"02", x"02", x"1a", x"26", x"22", x"26", x"1a", x"00", x"00", x"00", x"14", x"14", x"14",
x"00", x"00", x"00", x"00", x"00", x"1c", x"22", x"3e", x"20", x"1c", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"04", x"0a", x"08", x"1c", x"08", x"08", x"08", x"00", x"00", x"00", x"14", x"14", x"36",
x"00", x"00", x"00", x"00", x"00", x"1a", x"26", x"22", x"26", x"1a", x"02", x"1c", x"00", x"36", x"14", x"14",
x"00", x"00", x"00", x"20", x"20", x"2c", x"32", x"22", x"22", x"22", x"00", x"00", x"00", x"08", x"1E", x"20",
x"00", x"00", x"00", x"08", x"00", x"18", x"08", x"08", x"08", x"1c", x"00", x"00", x"1C", x"02", x"3C", x"08",
x"00", x"00", x"00", x"02", x"00", x"02", x"02", x"02", x"02", x"22", x"1c", x"00", x"00", x"32", x"32", x"04",
x"00", x"00", x"00", x"20", x"20", x"24", x"28", x"30", x"28", x"24", x"00", x"00", x"08", x"10", x"26", x"26",
x"00", x"00", x"00", x"18", x"08", x"08", x"08", x"08", x"08", x"1c", x"00", x"00", x"00", x"10", x"28", x"28",
x"00", x"00", x"00", x"00", x"00", x"3c", x"2a", x"2a", x"2a", x"2a", x"00", x"00", x"10", x"2A", x"24", x"1A",
x"00", x"00", x"00", x"00", x"00", x"2c", x"32", x"22", x"22", x"22", x"00", x"00", x"00", x"18", x"18", x"18",
x"00", x"00", x"00", x"00", x"00", x"1c", x"22", x"22", x"22", x"1c", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"3c", x"22", x"22", x"22", x"3c", x"20", x"20", x"00", x"08", x"10", x"20",
x"00", x"00", x"00", x"00", x"00", x"1e", x"22", x"22", x"22", x"1e", x"02", x"02", x"20", x"20", x"10", x"08",
x"00", x"00", x"00", x"00", x"00", x"2c", x"32", x"20", x"20", x"20", x"00", x"00", x"00", x"08", x"04", x"02",
x"00", x"00", x"00", x"00", x"00", x"1e", x"20", x"1c", x"02", x"3c", x"00", x"00", x"02", x"02", x"04", x"08",
x"00", x"00", x"00", x"10", x"10", x"38", x"10", x"10", x"12", x"0c", x"00", x"00", x"00", x"00", x"08", x"1C",
x"00", x"00", x"00", x"00", x"00", x"22", x"22", x"22", x"26", x"1a", x"00", x"00", x"3E", x"1C", x"08", x"00",
x"00", x"00", x"00", x"00", x"00", x"22", x"22", x"22", x"14", x"08", x"00", x"00", x"00", x"00", x"08", x"08",
x"00", x"00", x"00", x"00", x"00", x"22", x"2a", x"2a", x"14", x"14", x"00", x"00", x"3E", x"08", x"08", x"00",
x"00", x"00", x"00", x"00", x"00", x"22", x"14", x"08", x"14", x"22", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"22", x"22", x"22", x"1e", x"02", x"1c", x"00", x"30", x"30", x"10", x"20",
x"00", x"00", x"00", x"00", x"00", x"3e", x"04", x"08", x"10", x"3e", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"04", x"08", x"08", x"10", x"08", x"08", x"04", x"00", x"00", x"3E", x"00", x"00", x"00",
x"00", x"00", x"00", x"08", x"08", x"08", x"00", x"08", x"08", x"08", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"10", x"08", x"08", x"04", x"08", x"08", x"10", x"00", x"00", x"00", x"00", x"30", x"30",
x"00", x"00", x"00", x"10", x"2a", x"04", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"02", x"02", x"04",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"3e", x"00", x"00", x"08", x"10", x"20", x"20",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"18", x"24", x"24",
x"00", x"00", x"00", x"08", x"00", x"08", x"08", x"08", x"08", x"08", x"00", x"00", x"24", x"24", x"24", x"18",
x"00", x"00", x"00", x"00", x"08", x"1c", x"20", x"20", x"20", x"1c", x"08", x"00", x"00", x"08", x"18", x"08",
x"00", x"00", x"00", x"0c", x"12", x"10", x"38", x"10", x"10", x"3e", x"00", x"00", x"08", x"08", x"08", x"1C",
x"00", x"00", x"00", x"00", x"00", x"22", x"1c", x"14", x"1c", x"22", x"00", x"00", x"00", x"1C", x"22", x"02",
x"00", x"00", x"00", x"22", x"14", x"08", x"3e", x"08", x"3e", x"08", x"00", x"00", x"1C", x"20", x"20", x"3E",
x"00", x"00", x"00", x"08", x"08", x"08", x"00", x"08", x"08", x"08", x"00", x"00", x"00", x"1C", x"22", x"02",
x"00", x"00", x"00", x"1c", x"20", x"1c", x"22", x"1c", x"02", x"1c", x"00", x"00", x"04", x"02", x"22", x"1C",
x"14", x"14", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"04", x"0C", x"14",
x"00", x"00", x"3e", x"41", x"5d", x"51", x"51", x"5d", x"41", x"3e", x"00", x"00", x"3E", x"04", x"04", x"04",
x"00", x"00", x"00", x"1c", x"02", x"1e", x"22", x"1e", x"00", x"00", x"00", x"00", x"00", x"3E", x"20", x"3C",
x"00", x"00", x"00", x"00", x"0a", x"14", x"28", x"14", x"0a", x"00", x"00", x"00", x"02", x"02", x"22", x"1C",
x"00", x"00", x"00", x"00", x"00", x"00", x"3e", x"02", x"02", x"00", x"00", x"00", x"00", x"1C", x"20", x"20",
x"00", x"00", x"00", x"00", x"00", x"00", x"3e", x"00", x"00", x"00", x"00", x"00", x"3C", x"22", x"22", x"1C",
x"00", x"00", x"3e", x"41", x"5d", x"55", x"59", x"55", x"41", x"3e", x"00", x"00", x"00", x"3E", x"02", x"04",
x"00", x"00", x"00", x"7e", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"08", x"10", x"20", x"20",
x"00", x"00", x"00", x"10", x"28", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"1C", x"22", x"22",
x"00", x"00", x"08", x"08", x"3e", x"08", x"08", x"00", x"3e", x"00", x"00", x"00", x"1C", x"22", x"22", x"1C",
x"00", x"00", x"00", x"18", x"04", x"08", x"10", x"1c", x"00", x"00", x"00", x"00", x"00", x"1C", x"22", x"22",
x"00", x"00", x"00", x"18", x"04", x"18", x"04", x"18", x"00", x"00", x"00", x"00", x"1E", x"02", x"02", x"1C",
x"04", x"08", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"18", x"18",
x"00", x"00", x"00", x"00", x"00", x"12", x"12", x"12", x"12", x"1c", x"10", x"20", x"00", x"18", x"18", x"00",
x"00", x"00", x"00", x"1a", x"2a", x"2a", x"1a", x"0a", x"0a", x"0a", x"00", x"00", x"00", x"18", x"18", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"18", x"18", x"00", x"00", x"00", x"00", x"18", x"18", x"08", x"10",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"04", x"18", x"00", x"04", x"08", x"10",
x"00", x"00", x"00", x"08", x"18", x"08", x"08", x"1c", x"00", x"00", x"00", x"00", x"20", x"10", x"08", x"04",
x"00", x"00", x"00", x"1c", x"22", x"22", x"22", x"1c", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"3E",
x"00", x"00", x"00", x"00", x"28", x"14", x"0a", x"14", x"28", x"00", x"00", x"00", x"00", x"3E", x"00", x"00",
x"00", x"00", x"00", x"20", x"20", x"20", x"22", x"06", x"0e", x"02", x"00", x"00", x"00", x"10", x"08", x"04",
x"00", x"00", x"00", x"20", x"20", x"20", x"2e", x"02", x"04", x"0e", x"00", x"00", x"02", x"04", x"08", x"10",
x"00", x"00", x"00", x"70", x"10", x"70", x"12", x"76", x"0e", x"02", x"00", x"00", x"00", x"18", x"24", x"04",
x"00", x"00", x"00", x"08", x"00", x"08", x"08", x"10", x"12", x"0c", x"00", x"00", x"08", x"08", x"00", x"08"
);
--attribute RAM_STYLE : string;
--attribute RAM_STYLE of RAM: signal is "BLOCK";
begin
process (clka)
begin
if rising_edge(clka) then
if (wea = '1') then
RAM(conv_integer(addra(10 downto 0))) := dina;
end if;
douta <= RAM(conv_integer(addra(10 downto 0)));
end if;
end process;
process (clkb)
begin
if rising_edge(clkb) then
if (web = '1') then
RAM(conv_integer(addrb(10 downto 0))) := dinb;
end if;
doutb <= RAM(conv_integer(addrb(10 downto 0)));
end if;
end process;
end BEHAVIORAL;
|
----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Rob Taglang <[email protected]>
--
-- Create Date: 06:01:06 01/23/2013
-- Modified: 5/20/2017
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric.
-- Modified to fit modularly with other designs
--
-- Notes:
-- Technically, the ADV7511 supports rgb input formats, and it would
-- be really nice to be able to just drive that straight through.
-- Unfortunately, the pin mapping for hdmi_d maps to the [23-8] input
-- pins on the IC, and there is not rgb format that lies only in that
-- range of pins.
--
-- http://www.analog.com/media/en/technical-documentation/user-guides/ADV7511_Programming_Guide.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zed_hdmi is
port(
clk : in std_logic;
clk_x2 : in std_logic;
clk_100 : in std_logic;
active : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic
);
end zed_hdmi;
architecture Behavioral of zed_hdmi is
component i2c_sender
port(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
end component;
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal edge : std_logic := '0';
signal edge_rb : std_logic := '0';
signal r, g, b : std_logic_vector(7 downto 0);
signal y, cr, cb : std_logic_vector(7 downto 0);
begin
-- there is a 16 bit interface into the HDMI transmitter, although I only use 8 bits
r <= rgb888(23 downto 16);
g <= rgb888(15 downto 8);
b <= rgb888(7 downto 0);
hdmi_d(7 downto 0) <= x"00";
process(clk_x2)
variable y_hold, cr_hold, cb_hold : std_logic_vector(7 downto 0);
begin
---------------------------------------------------------------------------
-- signal generation for the HDMI encoder
--
-- Transfer on rising edge of clock Y
-- on falling edge of clock Either Cr or Cb
----------------------------------------------------------------------------
if rising_edge(clk_x2) then
if edge = '0' then
edge <= '1';
hdmi_clk_bits <= "11";
if edge_rb = '0' then
-- lock in value from conversion
y_hold := y;
cr_hold := cr;
cb_hold := cb;
end if;
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
hdmi_d(15 downto 8) <= y_hold;
hdmi_de <= '1';
end if;
else
edge <= '0';
hdmi_clk_bits <= "00";
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
if edge_rb = '0' then
hdmi_d(15 downto 8) <= cr_hold;
edge_rb <= '1';
else
hdmi_d(15 downto 8) <= cb_hold;
edge_rb <= '0';
end if;
hdmi_de <= '1';
end if;
end if;
hdmi_hsync <= not hsync;
hdmi_vsync <= not vsync;
end if;
end process;
process (clk)
variable r_int, g_int, b_int, y_int, cr_int, cb_int : integer;
begin
if rising_edge(clk) then
-- color space conversion and clamping
r_int := to_integer(unsigned(r));
g_int := to_integer(unsigned(g));
b_int := to_integer(unsigned(b));
y_int := ((r_int * 77) / 256) + ((g_int * 150) / 256) + ((b_int * 29) / 256);
cr_int := ((r_int * 131) / 256) - ((g_int * 110) / 256) - ((b_int * 21) / 256) + 128;
cb_int := -((r_int * 44) / 256) - ((g_int * 87) / 256) + ((b_int * 131) / 256) + 128;
end if;
if falling_edge(clk) then
if y_int > 255 then
y <= (others => '1');
elsif y_int < 0 then
y <= (others => '0');
else
y <= std_logic_vector(to_unsigned(y_int, 8));
end if;
if cr_int > 255 then
cr <= (others => '1');
elsif cr_int < 0 then
cr <= (others => '0');
else
cr <= std_logic_vector(to_unsigned(cr_int, 8));
end if;
if cb_int > 255 then
cb <= (others => '1');
elsif cb_int < 0 then
cb <= (others => '0');
else
cb <= std_logic_vector(to_unsigned(cb_int, 8));
end if;
end if;
end process;
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0',SRTYPE => "SYNC")
port map (
Q => hdmi_clk,
C => clk_x2,
D1 => hdmi_clk_bits(0),
D2 => hdmi_clk_bits(1),
CE => '1', R => '0', S => '0'
);
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk_100,
resend => '0',
sioc => hdmi_scl,
siod => hdmi_sda
);
end Behavioral; |
----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Rob Taglang <[email protected]>
--
-- Create Date: 06:01:06 01/23/2013
-- Modified: 5/20/2017
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric.
-- Modified to fit modularly with other designs
--
-- Notes:
-- Technically, the ADV7511 supports rgb input formats, and it would
-- be really nice to be able to just drive that straight through.
-- Unfortunately, the pin mapping for hdmi_d maps to the [23-8] input
-- pins on the IC, and there is not rgb format that lies only in that
-- range of pins.
--
-- http://www.analog.com/media/en/technical-documentation/user-guides/ADV7511_Programming_Guide.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zed_hdmi is
port(
clk : in std_logic;
clk_x2 : in std_logic;
clk_100 : in std_logic;
active : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic
);
end zed_hdmi;
architecture Behavioral of zed_hdmi is
component i2c_sender
port(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
end component;
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal edge : std_logic := '0';
signal edge_rb : std_logic := '0';
signal r, g, b : std_logic_vector(7 downto 0);
signal y, cr, cb : std_logic_vector(7 downto 0);
begin
-- there is a 16 bit interface into the HDMI transmitter, although I only use 8 bits
r <= rgb888(23 downto 16);
g <= rgb888(15 downto 8);
b <= rgb888(7 downto 0);
hdmi_d(7 downto 0) <= x"00";
process(clk_x2)
variable y_hold, cr_hold, cb_hold : std_logic_vector(7 downto 0);
begin
---------------------------------------------------------------------------
-- signal generation for the HDMI encoder
--
-- Transfer on rising edge of clock Y
-- on falling edge of clock Either Cr or Cb
----------------------------------------------------------------------------
if rising_edge(clk_x2) then
if edge = '0' then
edge <= '1';
hdmi_clk_bits <= "11";
if edge_rb = '0' then
-- lock in value from conversion
y_hold := y;
cr_hold := cr;
cb_hold := cb;
end if;
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
hdmi_d(15 downto 8) <= y_hold;
hdmi_de <= '1';
end if;
else
edge <= '0';
hdmi_clk_bits <= "00";
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
if edge_rb = '0' then
hdmi_d(15 downto 8) <= cr_hold;
edge_rb <= '1';
else
hdmi_d(15 downto 8) <= cb_hold;
edge_rb <= '0';
end if;
hdmi_de <= '1';
end if;
end if;
hdmi_hsync <= not hsync;
hdmi_vsync <= not vsync;
end if;
end process;
process (clk)
variable r_int, g_int, b_int, y_int, cr_int, cb_int : integer;
begin
if rising_edge(clk) then
-- color space conversion and clamping
r_int := to_integer(unsigned(r));
g_int := to_integer(unsigned(g));
b_int := to_integer(unsigned(b));
y_int := ((r_int * 77) / 256) + ((g_int * 150) / 256) + ((b_int * 29) / 256);
cr_int := ((r_int * 131) / 256) - ((g_int * 110) / 256) - ((b_int * 21) / 256) + 128;
cb_int := -((r_int * 44) / 256) - ((g_int * 87) / 256) + ((b_int * 131) / 256) + 128;
end if;
if falling_edge(clk) then
if y_int > 255 then
y <= (others => '1');
elsif y_int < 0 then
y <= (others => '0');
else
y <= std_logic_vector(to_unsigned(y_int, 8));
end if;
if cr_int > 255 then
cr <= (others => '1');
elsif cr_int < 0 then
cr <= (others => '0');
else
cr <= std_logic_vector(to_unsigned(cr_int, 8));
end if;
if cb_int > 255 then
cb <= (others => '1');
elsif cb_int < 0 then
cb <= (others => '0');
else
cb <= std_logic_vector(to_unsigned(cb_int, 8));
end if;
end if;
end process;
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0',SRTYPE => "SYNC")
port map (
Q => hdmi_clk,
C => clk_x2,
D1 => hdmi_clk_bits(0),
D2 => hdmi_clk_bits(1),
CE => '1', R => '0', S => '0'
);
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk_100,
resend => '0',
sioc => hdmi_scl,
siod => hdmi_sda
);
end Behavioral; |
----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Rob Taglang <[email protected]>
--
-- Create Date: 06:01:06 01/23/2013
-- Modified: 5/20/2017
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric.
-- Modified to fit modularly with other designs
--
-- Notes:
-- Technically, the ADV7511 supports rgb input formats, and it would
-- be really nice to be able to just drive that straight through.
-- Unfortunately, the pin mapping for hdmi_d maps to the [23-8] input
-- pins on the IC, and there is not rgb format that lies only in that
-- range of pins.
--
-- http://www.analog.com/media/en/technical-documentation/user-guides/ADV7511_Programming_Guide.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zed_hdmi is
port(
clk : in std_logic;
clk_x2 : in std_logic;
clk_100 : in std_logic;
active : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic
);
end zed_hdmi;
architecture Behavioral of zed_hdmi is
component i2c_sender
port(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
end component;
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal edge : std_logic := '0';
signal edge_rb : std_logic := '0';
signal r, g, b : std_logic_vector(7 downto 0);
signal y, cr, cb : std_logic_vector(7 downto 0);
begin
-- there is a 16 bit interface into the HDMI transmitter, although I only use 8 bits
r <= rgb888(23 downto 16);
g <= rgb888(15 downto 8);
b <= rgb888(7 downto 0);
hdmi_d(7 downto 0) <= x"00";
process(clk_x2)
variable y_hold, cr_hold, cb_hold : std_logic_vector(7 downto 0);
begin
---------------------------------------------------------------------------
-- signal generation for the HDMI encoder
--
-- Transfer on rising edge of clock Y
-- on falling edge of clock Either Cr or Cb
----------------------------------------------------------------------------
if rising_edge(clk_x2) then
if edge = '0' then
edge <= '1';
hdmi_clk_bits <= "11";
if edge_rb = '0' then
-- lock in value from conversion
y_hold := y;
cr_hold := cr;
cb_hold := cb;
end if;
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
hdmi_d(15 downto 8) <= y_hold;
hdmi_de <= '1';
end if;
else
edge <= '0';
hdmi_clk_bits <= "00";
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
if edge_rb = '0' then
hdmi_d(15 downto 8) <= cr_hold;
edge_rb <= '1';
else
hdmi_d(15 downto 8) <= cb_hold;
edge_rb <= '0';
end if;
hdmi_de <= '1';
end if;
end if;
hdmi_hsync <= not hsync;
hdmi_vsync <= not vsync;
end if;
end process;
process (clk)
variable r_int, g_int, b_int, y_int, cr_int, cb_int : integer;
begin
if rising_edge(clk) then
-- color space conversion and clamping
r_int := to_integer(unsigned(r));
g_int := to_integer(unsigned(g));
b_int := to_integer(unsigned(b));
y_int := ((r_int * 77) / 256) + ((g_int * 150) / 256) + ((b_int * 29) / 256);
cr_int := ((r_int * 131) / 256) - ((g_int * 110) / 256) - ((b_int * 21) / 256) + 128;
cb_int := -((r_int * 44) / 256) - ((g_int * 87) / 256) + ((b_int * 131) / 256) + 128;
end if;
if falling_edge(clk) then
if y_int > 255 then
y <= (others => '1');
elsif y_int < 0 then
y <= (others => '0');
else
y <= std_logic_vector(to_unsigned(y_int, 8));
end if;
if cr_int > 255 then
cr <= (others => '1');
elsif cr_int < 0 then
cr <= (others => '0');
else
cr <= std_logic_vector(to_unsigned(cr_int, 8));
end if;
if cb_int > 255 then
cb <= (others => '1');
elsif cb_int < 0 then
cb <= (others => '0');
else
cb <= std_logic_vector(to_unsigned(cb_int, 8));
end if;
end if;
end process;
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0',SRTYPE => "SYNC")
port map (
Q => hdmi_clk,
C => clk_x2,
D1 => hdmi_clk_bits(0),
D2 => hdmi_clk_bits(1),
CE => '1', R => '0', S => '0'
);
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk_100,
resend => '0',
sioc => hdmi_scl,
siod => hdmi_sda
);
end Behavioral; |
----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Rob Taglang <[email protected]>
--
-- Create Date: 06:01:06 01/23/2013
-- Modified: 5/20/2017
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric.
-- Modified to fit modularly with other designs
--
-- Notes:
-- Technically, the ADV7511 supports rgb input formats, and it would
-- be really nice to be able to just drive that straight through.
-- Unfortunately, the pin mapping for hdmi_d maps to the [23-8] input
-- pins on the IC, and there is not rgb format that lies only in that
-- range of pins.
--
-- http://www.analog.com/media/en/technical-documentation/user-guides/ADV7511_Programming_Guide.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zed_hdmi is
port(
clk : in std_logic;
clk_x2 : in std_logic;
clk_100 : in std_logic;
active : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic
);
end zed_hdmi;
architecture Behavioral of zed_hdmi is
component i2c_sender
port(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
end component;
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal edge : std_logic := '0';
signal edge_rb : std_logic := '0';
signal r, g, b : std_logic_vector(7 downto 0);
signal y, cr, cb : std_logic_vector(7 downto 0);
begin
-- there is a 16 bit interface into the HDMI transmitter, although I only use 8 bits
r <= rgb888(23 downto 16);
g <= rgb888(15 downto 8);
b <= rgb888(7 downto 0);
hdmi_d(7 downto 0) <= x"00";
process(clk_x2)
variable y_hold, cr_hold, cb_hold : std_logic_vector(7 downto 0);
begin
---------------------------------------------------------------------------
-- signal generation for the HDMI encoder
--
-- Transfer on rising edge of clock Y
-- on falling edge of clock Either Cr or Cb
----------------------------------------------------------------------------
if rising_edge(clk_x2) then
if edge = '0' then
edge <= '1';
hdmi_clk_bits <= "11";
if edge_rb = '0' then
-- lock in value from conversion
y_hold := y;
cr_hold := cr;
cb_hold := cb;
end if;
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
hdmi_d(15 downto 8) <= y_hold;
hdmi_de <= '1';
end if;
else
edge <= '0';
hdmi_clk_bits <= "00";
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
if edge_rb = '0' then
hdmi_d(15 downto 8) <= cr_hold;
edge_rb <= '1';
else
hdmi_d(15 downto 8) <= cb_hold;
edge_rb <= '0';
end if;
hdmi_de <= '1';
end if;
end if;
hdmi_hsync <= not hsync;
hdmi_vsync <= not vsync;
end if;
end process;
process (clk)
variable r_int, g_int, b_int, y_int, cr_int, cb_int : integer;
begin
if rising_edge(clk) then
-- color space conversion and clamping
r_int := to_integer(unsigned(r));
g_int := to_integer(unsigned(g));
b_int := to_integer(unsigned(b));
y_int := ((r_int * 77) / 256) + ((g_int * 150) / 256) + ((b_int * 29) / 256);
cr_int := ((r_int * 131) / 256) - ((g_int * 110) / 256) - ((b_int * 21) / 256) + 128;
cb_int := -((r_int * 44) / 256) - ((g_int * 87) / 256) + ((b_int * 131) / 256) + 128;
end if;
if falling_edge(clk) then
if y_int > 255 then
y <= (others => '1');
elsif y_int < 0 then
y <= (others => '0');
else
y <= std_logic_vector(to_unsigned(y_int, 8));
end if;
if cr_int > 255 then
cr <= (others => '1');
elsif cr_int < 0 then
cr <= (others => '0');
else
cr <= std_logic_vector(to_unsigned(cr_int, 8));
end if;
if cb_int > 255 then
cb <= (others => '1');
elsif cb_int < 0 then
cb <= (others => '0');
else
cb <= std_logic_vector(to_unsigned(cb_int, 8));
end if;
end if;
end process;
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0',SRTYPE => "SYNC")
port map (
Q => hdmi_clk,
C => clk_x2,
D1 => hdmi_clk_bits(0),
D2 => hdmi_clk_bits(1),
CE => '1', R => '0', S => '0'
);
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk_100,
resend => '0',
sioc => hdmi_scl,
siod => hdmi_sda
);
end Behavioral; |
----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Rob Taglang <[email protected]>
--
-- Create Date: 06:01:06 01/23/2013
-- Modified: 5/20/2017
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric.
-- Modified to fit modularly with other designs
--
-- Notes:
-- Technically, the ADV7511 supports rgb input formats, and it would
-- be really nice to be able to just drive that straight through.
-- Unfortunately, the pin mapping for hdmi_d maps to the [23-8] input
-- pins on the IC, and there is not rgb format that lies only in that
-- range of pins.
--
-- http://www.analog.com/media/en/technical-documentation/user-guides/ADV7511_Programming_Guide.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zed_hdmi is
port(
clk : in std_logic;
clk_x2 : in std_logic;
clk_100 : in std_logic;
active : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic
);
end zed_hdmi;
architecture Behavioral of zed_hdmi is
component i2c_sender
port(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
end component;
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal edge : std_logic := '0';
signal edge_rb : std_logic := '0';
signal r, g, b : std_logic_vector(7 downto 0);
signal y, cr, cb : std_logic_vector(7 downto 0);
begin
-- there is a 16 bit interface into the HDMI transmitter, although I only use 8 bits
r <= rgb888(23 downto 16);
g <= rgb888(15 downto 8);
b <= rgb888(7 downto 0);
hdmi_d(7 downto 0) <= x"00";
process(clk_x2)
variable y_hold, cr_hold, cb_hold : std_logic_vector(7 downto 0);
begin
---------------------------------------------------------------------------
-- signal generation for the HDMI encoder
--
-- Transfer on rising edge of clock Y
-- on falling edge of clock Either Cr or Cb
----------------------------------------------------------------------------
if rising_edge(clk_x2) then
if edge = '0' then
edge <= '1';
hdmi_clk_bits <= "11";
if edge_rb = '0' then
-- lock in value from conversion
y_hold := y;
cr_hold := cr;
cb_hold := cb;
end if;
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
hdmi_d(15 downto 8) <= y_hold;
hdmi_de <= '1';
end if;
else
edge <= '0';
hdmi_clk_bits <= "00";
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
if edge_rb = '0' then
hdmi_d(15 downto 8) <= cr_hold;
edge_rb <= '1';
else
hdmi_d(15 downto 8) <= cb_hold;
edge_rb <= '0';
end if;
hdmi_de <= '1';
end if;
end if;
hdmi_hsync <= not hsync;
hdmi_vsync <= not vsync;
end if;
end process;
process (clk)
variable r_int, g_int, b_int, y_int, cr_int, cb_int : integer;
begin
if rising_edge(clk) then
-- color space conversion and clamping
r_int := to_integer(unsigned(r));
g_int := to_integer(unsigned(g));
b_int := to_integer(unsigned(b));
y_int := ((r_int * 77) / 256) + ((g_int * 150) / 256) + ((b_int * 29) / 256);
cr_int := ((r_int * 131) / 256) - ((g_int * 110) / 256) - ((b_int * 21) / 256) + 128;
cb_int := -((r_int * 44) / 256) - ((g_int * 87) / 256) + ((b_int * 131) / 256) + 128;
end if;
if falling_edge(clk) then
if y_int > 255 then
y <= (others => '1');
elsif y_int < 0 then
y <= (others => '0');
else
y <= std_logic_vector(to_unsigned(y_int, 8));
end if;
if cr_int > 255 then
cr <= (others => '1');
elsif cr_int < 0 then
cr <= (others => '0');
else
cr <= std_logic_vector(to_unsigned(cr_int, 8));
end if;
if cb_int > 255 then
cb <= (others => '1');
elsif cb_int < 0 then
cb <= (others => '0');
else
cb <= std_logic_vector(to_unsigned(cb_int, 8));
end if;
end if;
end process;
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0',SRTYPE => "SYNC")
port map (
Q => hdmi_clk,
C => clk_x2,
D1 => hdmi_clk_bits(0),
D2 => hdmi_clk_bits(1),
CE => '1', R => '0', S => '0'
);
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk_100,
resend => '0',
sioc => hdmi_scl,
siod => hdmi_sda
);
end Behavioral; |
----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Rob Taglang <[email protected]>
--
-- Create Date: 06:01:06 01/23/2013
-- Modified: 5/20/2017
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric.
-- Modified to fit modularly with other designs
--
-- Notes:
-- Technically, the ADV7511 supports rgb input formats, and it would
-- be really nice to be able to just drive that straight through.
-- Unfortunately, the pin mapping for hdmi_d maps to the [23-8] input
-- pins on the IC, and there is not rgb format that lies only in that
-- range of pins.
--
-- http://www.analog.com/media/en/technical-documentation/user-guides/ADV7511_Programming_Guide.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zed_hdmi is
port(
clk : in std_logic;
clk_x2 : in std_logic;
clk_100 : in std_logic;
active : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic
);
end zed_hdmi;
architecture Behavioral of zed_hdmi is
component i2c_sender
port(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
end component;
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal edge : std_logic := '0';
signal edge_rb : std_logic := '0';
signal r, g, b : std_logic_vector(7 downto 0);
signal y, cr, cb : std_logic_vector(7 downto 0);
begin
-- there is a 16 bit interface into the HDMI transmitter, although I only use 8 bits
r <= rgb888(23 downto 16);
g <= rgb888(15 downto 8);
b <= rgb888(7 downto 0);
hdmi_d(7 downto 0) <= x"00";
process(clk_x2)
variable y_hold, cr_hold, cb_hold : std_logic_vector(7 downto 0);
begin
---------------------------------------------------------------------------
-- signal generation for the HDMI encoder
--
-- Transfer on rising edge of clock Y
-- on falling edge of clock Either Cr or Cb
----------------------------------------------------------------------------
if rising_edge(clk_x2) then
if edge = '0' then
edge <= '1';
hdmi_clk_bits <= "11";
if edge_rb = '0' then
-- lock in value from conversion
y_hold := y;
cr_hold := cr;
cb_hold := cb;
end if;
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
hdmi_d(15 downto 8) <= y_hold;
hdmi_de <= '1';
end if;
else
edge <= '0';
hdmi_clk_bits <= "00";
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
if edge_rb = '0' then
hdmi_d(15 downto 8) <= cr_hold;
edge_rb <= '1';
else
hdmi_d(15 downto 8) <= cb_hold;
edge_rb <= '0';
end if;
hdmi_de <= '1';
end if;
end if;
hdmi_hsync <= not hsync;
hdmi_vsync <= not vsync;
end if;
end process;
process (clk)
variable r_int, g_int, b_int, y_int, cr_int, cb_int : integer;
begin
if rising_edge(clk) then
-- color space conversion and clamping
r_int := to_integer(unsigned(r));
g_int := to_integer(unsigned(g));
b_int := to_integer(unsigned(b));
y_int := ((r_int * 77) / 256) + ((g_int * 150) / 256) + ((b_int * 29) / 256);
cr_int := ((r_int * 131) / 256) - ((g_int * 110) / 256) - ((b_int * 21) / 256) + 128;
cb_int := -((r_int * 44) / 256) - ((g_int * 87) / 256) + ((b_int * 131) / 256) + 128;
end if;
if falling_edge(clk) then
if y_int > 255 then
y <= (others => '1');
elsif y_int < 0 then
y <= (others => '0');
else
y <= std_logic_vector(to_unsigned(y_int, 8));
end if;
if cr_int > 255 then
cr <= (others => '1');
elsif cr_int < 0 then
cr <= (others => '0');
else
cr <= std_logic_vector(to_unsigned(cr_int, 8));
end if;
if cb_int > 255 then
cb <= (others => '1');
elsif cb_int < 0 then
cb <= (others => '0');
else
cb <= std_logic_vector(to_unsigned(cb_int, 8));
end if;
end if;
end process;
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0',SRTYPE => "SYNC")
port map (
Q => hdmi_clk,
C => clk_x2,
D1 => hdmi_clk_bits(0),
D2 => hdmi_clk_bits(1),
CE => '1', R => '0', S => '0'
);
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk_100,
resend => '0',
sioc => hdmi_scl,
siod => hdmi_sda
);
end Behavioral; |
----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Rob Taglang <[email protected]>
--
-- Create Date: 06:01:06 01/23/2013
-- Modified: 5/20/2017
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric.
-- Modified to fit modularly with other designs
--
-- Notes:
-- Technically, the ADV7511 supports rgb input formats, and it would
-- be really nice to be able to just drive that straight through.
-- Unfortunately, the pin mapping for hdmi_d maps to the [23-8] input
-- pins on the IC, and there is not rgb format that lies only in that
-- range of pins.
--
-- http://www.analog.com/media/en/technical-documentation/user-guides/ADV7511_Programming_Guide.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zed_hdmi is
port(
clk : in std_logic;
clk_x2 : in std_logic;
clk_100 : in std_logic;
active : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic
);
end zed_hdmi;
architecture Behavioral of zed_hdmi is
component i2c_sender
port(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
end component;
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal edge : std_logic := '0';
signal edge_rb : std_logic := '0';
signal r, g, b : std_logic_vector(7 downto 0);
signal y, cr, cb : std_logic_vector(7 downto 0);
begin
-- there is a 16 bit interface into the HDMI transmitter, although I only use 8 bits
r <= rgb888(23 downto 16);
g <= rgb888(15 downto 8);
b <= rgb888(7 downto 0);
hdmi_d(7 downto 0) <= x"00";
process(clk_x2)
variable y_hold, cr_hold, cb_hold : std_logic_vector(7 downto 0);
begin
---------------------------------------------------------------------------
-- signal generation for the HDMI encoder
--
-- Transfer on rising edge of clock Y
-- on falling edge of clock Either Cr or Cb
----------------------------------------------------------------------------
if rising_edge(clk_x2) then
if edge = '0' then
edge <= '1';
hdmi_clk_bits <= "11";
if edge_rb = '0' then
-- lock in value from conversion
y_hold := y;
cr_hold := cr;
cb_hold := cb;
end if;
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
hdmi_d(15 downto 8) <= y_hold;
hdmi_de <= '1';
end if;
else
edge <= '0';
hdmi_clk_bits <= "00";
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
if edge_rb = '0' then
hdmi_d(15 downto 8) <= cr_hold;
edge_rb <= '1';
else
hdmi_d(15 downto 8) <= cb_hold;
edge_rb <= '0';
end if;
hdmi_de <= '1';
end if;
end if;
hdmi_hsync <= not hsync;
hdmi_vsync <= not vsync;
end if;
end process;
process (clk)
variable r_int, g_int, b_int, y_int, cr_int, cb_int : integer;
begin
if rising_edge(clk) then
-- color space conversion and clamping
r_int := to_integer(unsigned(r));
g_int := to_integer(unsigned(g));
b_int := to_integer(unsigned(b));
y_int := ((r_int * 77) / 256) + ((g_int * 150) / 256) + ((b_int * 29) / 256);
cr_int := ((r_int * 131) / 256) - ((g_int * 110) / 256) - ((b_int * 21) / 256) + 128;
cb_int := -((r_int * 44) / 256) - ((g_int * 87) / 256) + ((b_int * 131) / 256) + 128;
end if;
if falling_edge(clk) then
if y_int > 255 then
y <= (others => '1');
elsif y_int < 0 then
y <= (others => '0');
else
y <= std_logic_vector(to_unsigned(y_int, 8));
end if;
if cr_int > 255 then
cr <= (others => '1');
elsif cr_int < 0 then
cr <= (others => '0');
else
cr <= std_logic_vector(to_unsigned(cr_int, 8));
end if;
if cb_int > 255 then
cb <= (others => '1');
elsif cb_int < 0 then
cb <= (others => '0');
else
cb <= std_logic_vector(to_unsigned(cb_int, 8));
end if;
end if;
end process;
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0',SRTYPE => "SYNC")
port map (
Q => hdmi_clk,
C => clk_x2,
D1 => hdmi_clk_bits(0),
D2 => hdmi_clk_bits(1),
CE => '1', R => '0', S => '0'
);
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk_100,
resend => '0',
sioc => hdmi_scl,
siod => hdmi_sda
);
end Behavioral; |
entity adder is
-- i0, i1 and the carry-in ci are inputs of the adder.
-- s is the sum output, co is the carry-out.
port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
end adder;
architecture rtl of adder is
begin
-- This full-adder architecture contains two concurrent assignment.
-- Compute the sum.
s <= i0 xor i1 xor ci;
-- Compute the carry.
co <= (i0 and i1) or (i0 and ci) or (i1 and ci);
end rtl;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2019 Paul Genssler - Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.math_real.all;
use work.op_codes.all;
ENTITY tb_lockstep IS
END tb_lockstep;
ARCHITECTURE behavior OF tb_lockstep IS
--Inputs
signal clk : std_logic := '0';
signal clk_5ns_delayed : std_logic := '0';
signal clk_5ns_enable : std_logic := '0';
signal reset : std_logic := '0';
signal sleep : std_logic := '0';
signal instruction : std_logic_vector(17 downto 0) := (others => '0');
signal in_port : std_logic_vector(7 downto 0) := (others => '0');
signal in_port_del : std_logic_vector(7 downto 0) := (others => '0');
signal interrupt : std_logic := '0';
--Outputs
signal address : std_logic_vector(11 downto 0);
signal bram_enable : std_logic;
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt_ack : std_logic;
-- PicoBlaze Outputs
signal pico_address : std_logic_vector(11 downto 0);
signal pico_instruction : std_logic_vector(17 downto 0) := (others => '0');
signal pico_bram_enable : std_logic;
signal pico_out_port : std_logic_vector(7 downto 0);
signal pico_port_id : std_logic_vector(7 downto 0);
signal pico_write_strobe : std_logic;
signal pico_k_write_strobe : std_logic;
signal pico_read_strobe : std_logic;
signal pico_interrupt_ack : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
type io_data is array (0 to 4) of unsigned(7 downto 0);
signal data : io_data := (x"00", x"AB", x"CD", x"12", x"00");
signal prog_mem_en : std_logic;
signal done : std_logic;
signal pico_done : std_logic;
signal sleep_en : std_logic := '1';
signal inter_en : std_logic := '1';
signal reset_en : std_logic := '1';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.pauloBlaze
generic map (
debug => true,
interrupt_vector => x"300",
hwbuild => x"41",
scratch_pad_memory_size => 64 )
PORT MAP (
-- clk => clk_5ns_delayed,
clk => clk,
reset => reset,
sleep => sleep,
address => address,
instruction => instruction,
bram_enable => bram_enable,
in_port => in_port,
out_port => out_port,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
read_strobe => read_strobe,
interrupt => interrupt,
interrupt_ack => interrupt_ack );
-- end port map
picoblaze: entity work.kcpsm6
generic map ( hwbuild => X"41",
interrupt_vector => X"300",
scratch_pad_memory_size => 64)
port map( address => pico_address,
instruction => pico_instruction,
bram_enable => pico_bram_enable,
port_id => pico_port_id,
write_strobe => pico_write_strobe,
k_write_strobe => pico_k_write_strobe,
out_port => pico_out_port,
read_strobe => pico_read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => pico_interrupt_ack,
sleep => sleep,
reset => reset,
clk => clk);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
sleeping : process begin
if (sleep_en = '1') then
wait for 1035 ns;
sleep <= '1';
wait for 1 * clk_period;
sleep <= '0';
wait for 5000 ns;
sleep <= '1';
wait for 7 * clk_period;
sleep <= '0';
end if;
wait;
end process sleeping;
inter_static : process
begin
if (inter_en = '1') then
wait for 490 ns;
interrupt <= '1';
wait for 3 * clk_period;
interrupt <= '0';
wait for 875 ns;
interrupt <= '1';
wait until interrupt_ack = '1';
interrupt <= '0';
end if;
wait;
end process inter_static;
prog_mem : entity work.code_loader
Port map (
address => address,
instruction => instruction,
enable => bram_enable,
done => done,
rdl => open,
clk => clk);
prog_mem_pico : entity work.code_loader
Port map (
address => pico_address,
instruction => pico_instruction,
enable => pico_bram_enable,
done => pico_done,
rdl => open,
clk => clk);
reset_proc: process
begin
reset <= '1';
wait until (done = '1' and pico_done = '1');
wait until clk = '0';
reset <= '0';
if (reset_en = '1') then
wait for 465 ns;
reset <= '1';
wait for 86 ns;
reset <= '0';
end if;
wait for 1337 ns;
wait until rising_edge(clk);
if (reset_en = '1') then
wait for 85 ns;
reset <= '1';
wait for 35 ns;
reset <= '0';
end if;
wait;
end process;
process begin
wait for 20 ns;
in_port <= in_port_del;
end process;
data_in_proc : process (port_id) begin
case (port_id) is
when x"05" =>
in_port_del <= x"F3";
when others =>
in_port_del <= port_id;
end case;
end process data_in_proc;
compare_process: process begin
wait until reset = '0';
loop
wait until rising_edge(clk);
wait until rising_edge(clk);
assert pico_address = address report "address is different" severity error;
assert pico_bram_enable = bram_enable report "bram_enable is different" severity error;
assert pico_write_strobe = write_strobe report "write_strobe is different" severity error;
assert pico_k_write_strobe = k_write_strobe report "k_write_strobe is different" severity error;
if (pico_write_strobe = '1' or write_strobe = '1' or
pico_k_write_strobe = '1' or k_write_strobe = '1' ) then
assert pico_out_port = out_port report "out_port is different" severity error;
if (pico_k_write_strobe = '1' or k_write_strobe = '1' ) then
assert pico_port_id(3 downto 0) = port_id(3 downto 0) report "port_id is different" severity error;
else
assert pico_port_id = port_id report "port_id is different" severity error;
end if;
end if;
assert pico_read_strobe = read_strobe report "read_strobe is different" severity error;
assert pico_interrupt_ack = interrupt_ack report "interrupt_ack is different" severity error;
end loop;
end process;
END;
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2019 Paul Genssler - Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.math_real.all;
use work.op_codes.all;
ENTITY tb_lockstep IS
END tb_lockstep;
ARCHITECTURE behavior OF tb_lockstep IS
--Inputs
signal clk : std_logic := '0';
signal clk_5ns_delayed : std_logic := '0';
signal clk_5ns_enable : std_logic := '0';
signal reset : std_logic := '0';
signal sleep : std_logic := '0';
signal instruction : std_logic_vector(17 downto 0) := (others => '0');
signal in_port : std_logic_vector(7 downto 0) := (others => '0');
signal in_port_del : std_logic_vector(7 downto 0) := (others => '0');
signal interrupt : std_logic := '0';
--Outputs
signal address : std_logic_vector(11 downto 0);
signal bram_enable : std_logic;
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt_ack : std_logic;
-- PicoBlaze Outputs
signal pico_address : std_logic_vector(11 downto 0);
signal pico_instruction : std_logic_vector(17 downto 0) := (others => '0');
signal pico_bram_enable : std_logic;
signal pico_out_port : std_logic_vector(7 downto 0);
signal pico_port_id : std_logic_vector(7 downto 0);
signal pico_write_strobe : std_logic;
signal pico_k_write_strobe : std_logic;
signal pico_read_strobe : std_logic;
signal pico_interrupt_ack : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
type io_data is array (0 to 4) of unsigned(7 downto 0);
signal data : io_data := (x"00", x"AB", x"CD", x"12", x"00");
signal prog_mem_en : std_logic;
signal done : std_logic;
signal pico_done : std_logic;
signal sleep_en : std_logic := '1';
signal inter_en : std_logic := '1';
signal reset_en : std_logic := '1';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.pauloBlaze
generic map (
debug => true,
interrupt_vector => x"300",
hwbuild => x"41",
scratch_pad_memory_size => 64 )
PORT MAP (
-- clk => clk_5ns_delayed,
clk => clk,
reset => reset,
sleep => sleep,
address => address,
instruction => instruction,
bram_enable => bram_enable,
in_port => in_port,
out_port => out_port,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
read_strobe => read_strobe,
interrupt => interrupt,
interrupt_ack => interrupt_ack );
-- end port map
picoblaze: entity work.kcpsm6
generic map ( hwbuild => X"41",
interrupt_vector => X"300",
scratch_pad_memory_size => 64)
port map( address => pico_address,
instruction => pico_instruction,
bram_enable => pico_bram_enable,
port_id => pico_port_id,
write_strobe => pico_write_strobe,
k_write_strobe => pico_k_write_strobe,
out_port => pico_out_port,
read_strobe => pico_read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => pico_interrupt_ack,
sleep => sleep,
reset => reset,
clk => clk);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
sleeping : process begin
if (sleep_en = '1') then
wait for 1035 ns;
sleep <= '1';
wait for 1 * clk_period;
sleep <= '0';
wait for 5000 ns;
sleep <= '1';
wait for 7 * clk_period;
sleep <= '0';
end if;
wait;
end process sleeping;
inter_static : process
begin
if (inter_en = '1') then
wait for 490 ns;
interrupt <= '1';
wait for 3 * clk_period;
interrupt <= '0';
wait for 875 ns;
interrupt <= '1';
wait until interrupt_ack = '1';
interrupt <= '0';
end if;
wait;
end process inter_static;
prog_mem : entity work.code_loader
Port map (
address => address,
instruction => instruction,
enable => bram_enable,
done => done,
rdl => open,
clk => clk);
prog_mem_pico : entity work.code_loader
Port map (
address => pico_address,
instruction => pico_instruction,
enable => pico_bram_enable,
done => pico_done,
rdl => open,
clk => clk);
reset_proc: process
begin
reset <= '1';
wait until (done = '1' and pico_done = '1');
wait until clk = '0';
reset <= '0';
if (reset_en = '1') then
wait for 465 ns;
reset <= '1';
wait for 86 ns;
reset <= '0';
end if;
wait for 1337 ns;
wait until rising_edge(clk);
if (reset_en = '1') then
wait for 85 ns;
reset <= '1';
wait for 35 ns;
reset <= '0';
end if;
wait;
end process;
process begin
wait for 20 ns;
in_port <= in_port_del;
end process;
data_in_proc : process (port_id) begin
case (port_id) is
when x"05" =>
in_port_del <= x"F3";
when others =>
in_port_del <= port_id;
end case;
end process data_in_proc;
compare_process: process begin
wait until reset = '0';
loop
wait until rising_edge(clk);
wait until rising_edge(clk);
assert pico_address = address report "address is different" severity error;
assert pico_bram_enable = bram_enable report "bram_enable is different" severity error;
assert pico_write_strobe = write_strobe report "write_strobe is different" severity error;
assert pico_k_write_strobe = k_write_strobe report "k_write_strobe is different" severity error;
if (pico_write_strobe = '1' or write_strobe = '1' or
pico_k_write_strobe = '1' or k_write_strobe = '1' ) then
assert pico_out_port = out_port report "out_port is different" severity error;
if (pico_k_write_strobe = '1' or k_write_strobe = '1' ) then
assert pico_port_id(3 downto 0) = port_id(3 downto 0) report "port_id is different" severity error;
else
assert pico_port_id = port_id report "port_id is different" severity error;
end if;
end if;
assert pico_read_strobe = read_strobe report "read_strobe is different" severity error;
assert pico_interrupt_ack = interrupt_ack report "interrupt_ack is different" severity error;
end loop;
end process;
END;
|
-- file: Interface_Master_BD_clk_wiz_0_0.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1____71.602______0.000______50.0______245.835____242.683
-- CLK_OUT2_____7.202______0.000______50.0______392.994____242.683
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity Interface_Master_BD_clk_wiz_0_0 is
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end Interface_Master_BD_clk_wiz_0_0;
architecture xilinx of Interface_Master_BD_clk_wiz_0_0 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "Interface_Master_BD_clk_wiz_0_0,clk_wiz_v5_1,{component_name=Interface_Master_BD_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component Interface_Master_BD_clk_wiz_0_0_clk_wiz
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end component;
begin
U0: Interface_Master_BD_clk_wiz_0_0_clk_wiz
port map (
-- Clock in ports
clk_in1 => clk_in1,
-- Clock out ports
clk_out1 => clk_out1,
clk_out2 => clk_out2,
-- Status and control signals
resetn => resetn,
locked => locked
);
end xilinx;
|
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