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-- This file has been automatically generated by go-iec61499-vhdl and should not be edited by hand -- Converter written by Hammond Pearce and available at github.com/kiwih/go-iec61499-vhdl -- This file represents the Basic Function Block for RejectArmController library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity RejectArmController is port( --for clock and reset signal clk : in std_logic; reset : in std_logic; enable : in std_logic; sync : in std_logic; --input events RejectCanister : in std_logic; LasersChanged : in std_logic; --output events GoRejectArm : out std_logic; --input variables RejectSiteLaser_I : in std_logic; --type was BOOL --for done signal done : out std_logic ); end entity; architecture rtl of RejectArmController is -- Build an enumerated type for the state machine type state_type is (STATE_Clear, STATE_AwaitCanister, STATE_GoReject); -- Register to hold the current state signal state : state_type := STATE_Clear; -- signals to store variable sampled on enable signal RejectSiteLaser : std_logic := '0'; --register for input -- signals for enabling algorithms -- signal for algorithm completion signal AlgorithmsStart : std_logic := '0'; signal AlgorithmsDone : std_logic; begin -- Registers for data variables (only updated on relevant events) process (clk) begin if rising_edge(clk) then if sync = '1' then if LasersChanged = '1' then RejectSiteLaser <= RejectSiteLaser_I; end if; end if; end if; end process; -- Logic to advance to the next state process (clk, reset) begin if reset = '1' then state <= STATE_Clear; AlgorithmsStart <= '1'; elsif (rising_edge(clk)) then if AlgorithmsStart = '1' then --algorithms should be triggered only once via this pulse signal AlgorithmsStart <= '0'; elsif enable = '1' then --default values state <= state; AlgorithmsStart <= '0'; --next state logic if AlgorithmsStart = '0' and AlgorithmsDone = '1' then case state is when STATE_Clear => if RejectCanister = '1' then state <= STATE_AwaitCanister; AlgorithmsStart <= '1'; end if; when STATE_AwaitCanister => if LasersChanged = '1' and (RejectSiteLaser = '1') then state <= STATE_GoReject; AlgorithmsStart <= '1'; end if; when STATE_GoReject => if RejectCanister = '1' then state <= STATE_AwaitCanister; AlgorithmsStart <= '1'; end if; end case; end if; end if; end if; end process; -- Event outputs and internal algorithm triggers depend solely on the current state process (state) begin --default values --events GoRejectArm <= '0'; case state is when STATE_Clear => when STATE_AwaitCanister => when STATE_GoReject => GoRejectArm <= '1'; end case; end process; --This Basic FB had no algorithms --Done signal AlgorithmsDone <= (not AlgorithmsStart); Done <= AlgorithmsDone; end rtl;
-- This file has been automatically generated by go-iec61499-vhdl and should not be edited by hand -- Converter written by Hammond Pearce and available at github.com/kiwih/go-iec61499-vhdl -- This file represents the Basic Function Block for RejectArmController library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity RejectArmController is port( --for clock and reset signal clk : in std_logic; reset : in std_logic; enable : in std_logic; sync : in std_logic; --input events RejectCanister : in std_logic; LasersChanged : in std_logic; --output events GoRejectArm : out std_logic; --input variables RejectSiteLaser_I : in std_logic; --type was BOOL --for done signal done : out std_logic ); end entity; architecture rtl of RejectArmController is -- Build an enumerated type for the state machine type state_type is (STATE_Clear, STATE_AwaitCanister, STATE_GoReject); -- Register to hold the current state signal state : state_type := STATE_Clear; -- signals to store variable sampled on enable signal RejectSiteLaser : std_logic := '0'; --register for input -- signals for enabling algorithms -- signal for algorithm completion signal AlgorithmsStart : std_logic := '0'; signal AlgorithmsDone : std_logic; begin -- Registers for data variables (only updated on relevant events) process (clk) begin if rising_edge(clk) then if sync = '1' then if LasersChanged = '1' then RejectSiteLaser <= RejectSiteLaser_I; end if; end if; end if; end process; -- Logic to advance to the next state process (clk, reset) begin if reset = '1' then state <= STATE_Clear; AlgorithmsStart <= '1'; elsif (rising_edge(clk)) then if AlgorithmsStart = '1' then --algorithms should be triggered only once via this pulse signal AlgorithmsStart <= '0'; elsif enable = '1' then --default values state <= state; AlgorithmsStart <= '0'; --next state logic if AlgorithmsStart = '0' and AlgorithmsDone = '1' then case state is when STATE_Clear => if RejectCanister = '1' then state <= STATE_AwaitCanister; AlgorithmsStart <= '1'; end if; when STATE_AwaitCanister => if LasersChanged = '1' and (RejectSiteLaser = '1') then state <= STATE_GoReject; AlgorithmsStart <= '1'; end if; when STATE_GoReject => if RejectCanister = '1' then state <= STATE_AwaitCanister; AlgorithmsStart <= '1'; end if; end case; end if; end if; end if; end process; -- Event outputs and internal algorithm triggers depend solely on the current state process (state) begin --default values --events GoRejectArm <= '0'; case state is when STATE_Clear => when STATE_AwaitCanister => when STATE_GoReject => GoRejectArm <= '1'; end case; end process; --This Basic FB had no algorithms --Done signal AlgorithmsDone <= (not AlgorithmsStart); Done <= AlgorithmsDone; end rtl;
-- ------------------------------------------------------------- -- -- Entity Declaration for ent_b -- -- Generated -- by: wig -- on: Tue Sep 27 05:17:18 2005 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../highlow.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: ent_b-e.vhd,v 1.3 2005/10/25 13:31:24 wig Exp $ -- $Date: 2005/10/25 13:31:24 $ -- $Log: ent_b-e.vhd,v $ -- Revision 1.3 2005/10/25 13:31:24 wig -- Testcase result update -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.58 2005/09/14 14:40:06 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.37 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity ent_b -- entity ent_b is -- Generics: -- No Generated Generics for Entity ent_b -- Generated Port Declaration: -- No Generated Port for Entity ent_b end ent_b; -- -- End of Generated Entity ent_b -- -- --!End of Entity/ies -- --------------------------------------------------------------
---------------------------------------------------------------------------------- --! Company: EDAQ WIS. --! Engineer: juna --! --! Create Date: 10/07/2014 --! Module Name: MUX4 --! Project Name: FELIX ---------------------------------------------------------------------------------- --! Use standard library library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; --! MUX 4x1 entity MUX4 is Port ( data0 : in std_logic; data1 : in std_logic; data2 : in std_logic; data3 : in std_logic; sel : in std_logic_vector(1 downto 0); data_out : out std_logic ); end MUX4; --architecture low_level_MUX4 of MUX4 is --begin --lut_inst: LUT6 --generic map (INIT => X"FF00F0F0CCCCAAAA") --port map( -- I0 => data0, -- I1 => data1, -- I2 => data2, -- I3 => data3, -- I4 => sel(0), -- I5 => sel(1), -- O => data_out -- ); --end low_level_MUX4; architecture behavioral of MUX4 is begin process(data0,data1,data2,data3,sel) begin case sel is when "00" => data_out <= data0; when "01" => data_out <= data1; when "10" => data_out <= data2; when "11" => data_out <= data3; when others => end case; end process; end behavioral;
---------------------------------------------------------------------------------- --! Company: EDAQ WIS. --! Engineer: juna --! --! Create Date: 10/07/2014 --! Module Name: MUX4 --! Project Name: FELIX ---------------------------------------------------------------------------------- --! Use standard library library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; --! MUX 4x1 entity MUX4 is Port ( data0 : in std_logic; data1 : in std_logic; data2 : in std_logic; data3 : in std_logic; sel : in std_logic_vector(1 downto 0); data_out : out std_logic ); end MUX4; --architecture low_level_MUX4 of MUX4 is --begin --lut_inst: LUT6 --generic map (INIT => X"FF00F0F0CCCCAAAA") --port map( -- I0 => data0, -- I1 => data1, -- I2 => data2, -- I3 => data3, -- I4 => sel(0), -- I5 => sel(1), -- O => data_out -- ); --end low_level_MUX4; architecture behavioral of MUX4 is begin process(data0,data1,data2,data3,sel) begin case sel is when "00" => data_out <= data0; when "01" => data_out <= data1; when "10" => data_out <= data2; when "11" => data_out <= data3; when others => end case; end process; end behavioral;
---------------------------------------------------------------------------------- --! Company: EDAQ WIS. --! Engineer: juna --! --! Create Date: 10/07/2014 --! Module Name: MUX4 --! Project Name: FELIX ---------------------------------------------------------------------------------- --! Use standard library library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; --! MUX 4x1 entity MUX4 is Port ( data0 : in std_logic; data1 : in std_logic; data2 : in std_logic; data3 : in std_logic; sel : in std_logic_vector(1 downto 0); data_out : out std_logic ); end MUX4; --architecture low_level_MUX4 of MUX4 is --begin --lut_inst: LUT6 --generic map (INIT => X"FF00F0F0CCCCAAAA") --port map( -- I0 => data0, -- I1 => data1, -- I2 => data2, -- I3 => data3, -- I4 => sel(0), -- I5 => sel(1), -- O => data_out -- ); --end low_level_MUX4; architecture behavioral of MUX4 is begin process(data0,data1,data2,data3,sel) begin case sel is when "00" => data_out <= data0; when "01" => data_out <= data1; when "10" => data_out <= data2; when "11" => data_out <= data3; when others => end case; end process; end behavioral;
---------------------------------------------------------------------------------- --! Company: EDAQ WIS. --! Engineer: juna --! --! Create Date: 10/07/2014 --! Module Name: MUX4 --! Project Name: FELIX ---------------------------------------------------------------------------------- --! Use standard library library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; --! MUX 4x1 entity MUX4 is Port ( data0 : in std_logic; data1 : in std_logic; data2 : in std_logic; data3 : in std_logic; sel : in std_logic_vector(1 downto 0); data_out : out std_logic ); end MUX4; --architecture low_level_MUX4 of MUX4 is --begin --lut_inst: LUT6 --generic map (INIT => X"FF00F0F0CCCCAAAA") --port map( -- I0 => data0, -- I1 => data1, -- I2 => data2, -- I3 => data3, -- I4 => sel(0), -- I5 => sel(1), -- O => data_out -- ); --end low_level_MUX4; architecture behavioral of MUX4 is begin process(data0,data1,data2,data3,sel) begin case sel is when "00" => data_out <= data0; when "01" => data_out <= data1; when "10" => data_out <= data2; when "11" => data_out <= data3; when others => end case; end process; end behavioral;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc107.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b02x00p29n06i00107ent IS port ( signal S : out bit) ; END c04s03b02x00p29n06i00107ent; ARCHITECTURE c04s03b02x00p29n06i00107arch OF c04s03b02x00p29n06i00107ent IS BEGIN TESTING: PROCESS variable T : TIME := 10 ns; BEGIN if (S'LAST_ACTIVE = T) then -- Failure_here end if; assert FALSE report "***FAILED TEST: c04s03b02x00p29n06i00107 - The attribute LAST_ACTIVE of a signal of mode out cannot be read." severity ERROR; wait; END PROCESS TESTING; END c04s03b02x00p29n06i00107arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc107.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b02x00p29n06i00107ent IS port ( signal S : out bit) ; END c04s03b02x00p29n06i00107ent; ARCHITECTURE c04s03b02x00p29n06i00107arch OF c04s03b02x00p29n06i00107ent IS BEGIN TESTING: PROCESS variable T : TIME := 10 ns; BEGIN if (S'LAST_ACTIVE = T) then -- Failure_here end if; assert FALSE report "***FAILED TEST: c04s03b02x00p29n06i00107 - The attribute LAST_ACTIVE of a signal of mode out cannot be read." severity ERROR; wait; END PROCESS TESTING; END c04s03b02x00p29n06i00107arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc107.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b02x00p29n06i00107ent IS port ( signal S : out bit) ; END c04s03b02x00p29n06i00107ent; ARCHITECTURE c04s03b02x00p29n06i00107arch OF c04s03b02x00p29n06i00107ent IS BEGIN TESTING: PROCESS variable T : TIME := 10 ns; BEGIN if (S'LAST_ACTIVE = T) then -- Failure_here end if; assert FALSE report "***FAILED TEST: c04s03b02x00p29n06i00107 - The attribute LAST_ACTIVE of a signal of mode out cannot be read." severity ERROR; wait; END PROCESS TESTING; END c04s03b02x00p29n06i00107arch;
package fifo_pkg is end package; library ieee; package fifo_pkg is end package; -- Comment package fifo_pkg is end package;
------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------ entity DECODER is port(OP1,OP2,OP3,OP4,OP5,OP6: in integer range 0 to 255; CLOCK: std_logic; OUTS: out integer range 0 to 2048); end DECODER; ------------------------------------------ architecture behv of DECODER is signal NEXT_OUTS: integer; begin process(CLOCK) begin if(rising_edge(CLOCK)) then OUTS <= NEXT_OUTS; end if; end process; process(OP1,OP2,OP3,OP4,OP5,OP6) begin case OP1 is when 0 => NEXT_OUTS <= 809; -- addb_Eb_Gb SANITY when 1 => case OP2 is when 0 => NEXT_OUTS <= 1579; -- addl_Ed_Gd SANITY when 1 => NEXT_OUTS <= 1598; -- decl_ERX SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 2 => NEXT_OUTS <= 1045; -- addb_Gb_Eb SANITY when 3 => NEXT_OUTS <= 360; -- addl_Gd_Ed SANITY when 4 => NEXT_OUTS <= 1394; -- addb_AL_Ib SANITY when 5 => NEXT_OUTS <= 727; -- addl_EAX_Id SANITY when 6 => NEXT_OUTS <= 77; -- pushl_ES SANITY when 7 => NEXT_OUTS <= 1032; -- popl_ES SANITY when 8 => NEXT_OUTS <= 397; -- orb_Eb_Gb SANITY when 9 => NEXT_OUTS <= 513; -- orl_Ed_Gd SANITY when 10 => NEXT_OUTS <= 1378; -- orb_Gb_Eb SANITY when 11 => NEXT_OUTS <= 263; -- orl_Gd_Ed SANITY when 12 => NEXT_OUTS <= 557; -- orb_AL_Ib SANITY when 13 => NEXT_OUTS <= 93; -- orl_EAX_Id SANITY when 14 => NEXT_OUTS <= 730; -- pushl_CS SANITY when 15 => case OP2 is when 0 => case OP3 is when 0 => NEXT_OUTS <= 1423; -- sldt SANITY when 8 => NEXT_OUTS <= 1289; -- str SANITY when 16 => NEXT_OUTS <= 1312; -- lldt SANITY when 24 => NEXT_OUTS <= 383; -- ltr SANITY when 32 => NEXT_OUTS <= 420; -- verr SANITY when 40 => NEXT_OUTS <= 1447; -- verw SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 1 => case OP3 is when 0 => NEXT_OUTS <= 811; -- sgdt SANITY when 8 => NEXT_OUTS <= 1446; -- sidt SANITY when 16 => NEXT_OUTS <= 1652; -- lgdt SANITY when 24 => NEXT_OUTS <= 1236; -- lidt SANITY when 32 => NEXT_OUTS <= 841; -- smsw_Ew SANITY when 48 => NEXT_OUTS <= 9; -- lmsw_Ew SANITY when 56 => NEXT_OUTS <= 700; -- invlpg SANITY when 193 => NEXT_OUTS <= 1483; -- vmcall SANITY when 194 => NEXT_OUTS <= 553; -- vmlaunch SANITY when 195 => NEXT_OUTS <= 205; -- vmresume SANITY when 196 => NEXT_OUTS <= 939; -- vmxoff SANITY when 200 => NEXT_OUTS <= 1497; -- monitor SANITY when 201 => NEXT_OUTS <= 489; -- mwait SANITY when 208 => NEXT_OUTS <= 1348; -- xgetbv SANITY when 209 => NEXT_OUTS <= 141; -- xsetbv SANITY when 248 => NEXT_OUTS <= 712; -- swapgs SANITY when 249 => NEXT_OUTS <= 262; -- rdtscp SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 2 => case OP3 is when 0 => NEXT_OUTS <= 1586; -- larl_Gd_Ew SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 3 => case OP3 is when 0 => NEXT_OUTS <= 975; -- lsll_Gd_Ew SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 5 => NEXT_OUTS <= 628; -- syscall SANITY when 6 => NEXT_OUTS <= 100; -- clts SANITY when 7 => NEXT_OUTS <= 1049; -- sysret SANITY when 8 => NEXT_OUTS <= 367; -- invd SANITY when 9 => NEXT_OUTS <= 735; -- wbinvd SANITY when 11 => NEXT_OUTS <= 878; -- ud2a SANITY when 16 => NEXT_OUTS <= 155; -- movups_Vps_Wps SANITY when 17 => NEXT_OUTS <= 826; -- movups_Wps_Vps SANITY when 18 => case OP3 is when 0 => NEXT_OUTS <= 1114; -- movlps_Vps_Mq SANITY when 192 => NEXT_OUTS <= 693; -- movhlps_Vps_Udq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 19 => NEXT_OUTS <= 1574; -- movlps_Mq_Vps SANITY when 20 => NEXT_OUTS <= 1511; -- unpcklps_Vps_Wps SANITY when 21 => NEXT_OUTS <= 1028; -- unpckhps_Vps_Wps SANITY when 22 => case OP3 is when 0 => NEXT_OUTS <= 625; -- movhps_Vps_Mq SANITY when 192 => NEXT_OUTS <= 1016; -- movlhps_Vps_Udq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 23 => NEXT_OUTS <= 74; -- movhps_Mq_Vps SANITY when 24 => case OP3 is when 0 => NEXT_OUTS <= 1328; -- prefetchnta SANITY when 8 => NEXT_OUTS <= 886; -- prefetcht0 SANITY when 16 => NEXT_OUTS <= 7; -- prefetcht1 SANITY when 24 => NEXT_OUTS <= 522; -- prefetcht2 SANITY when 32 => NEXT_OUTS <= 412; -- prefetch_hint SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 25 => NEXT_OUTS <= 623; -- multibyte_nop SANITY when 32 => case OP3 is when 0 => NEXT_OUTS <= 881; -- movl_Rd_Cd SANITY when 1 => NEXT_OUTS <= 526; -- movq_Rq_Cq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 33 => case OP3 is when 0 => NEXT_OUTS <= 1178; -- movl_Rd_Dd SANITY when 1 => NEXT_OUTS <= 596; -- movq_Rq_Dq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 34 => case OP3 is when 0 => NEXT_OUTS <= 722; -- movl_Cd_Rd SANITY when 1 => NEXT_OUTS <= 1375; -- movq_Cq_Rq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 35 => case OP3 is when 0 => NEXT_OUTS <= 1354; -- movl_Dd_Rd SANITY when 1 => NEXT_OUTS <= 797; -- movq_Dq_Rq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 36 => case OP3 is when 0 => NEXT_OUTS <= 956; -- movl_Rd_Td SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 38 => NEXT_OUTS <= 919; -- movl_Td_Rd SANITY when 40 => NEXT_OUTS <= 457; -- movaps_Vps_Wps SANITY when 41 => NEXT_OUTS <= 1102; -- movaps_Wps_Vps SANITY when 42 => NEXT_OUTS <= 1098; -- cvtpi2ps_Vps_Qq SANITY when 43 => NEXT_OUTS <= 414; -- movntps_Mps_Vps SANITY when 44 => NEXT_OUTS <= 1105; -- cvttps2pi_Pq_Wps SANITY when 45 => NEXT_OUTS <= 6; -- cvtps2pi_Pq_Wps SANITY when 46 => NEXT_OUTS <= 4; -- ucomiss_Vss_Wss SANITY when 47 => NEXT_OUTS <= 877; -- comiss_Vss_Wss SANITY when 48 => NEXT_OUTS <= 923; -- wrmsr SANITY when 49 => NEXT_OUTS <= 1234; -- rdtsc SANITY when 50 => NEXT_OUTS <= 388; -- rdmsr SANITY when 51 => NEXT_OUTS <= 1416; -- rdpmc SANITY when 52 => NEXT_OUTS <= 1047; -- sysenter SANITY when 53 => NEXT_OUTS <= 45; -- sysexit SANITY when 55 => NEXT_OUTS <= 951; -- getsec SANITY when 56 => case OP3 is when 0 => NEXT_OUTS <= 1435; -- pshufb_Pq_Qq SANITY when 1 => NEXT_OUTS <= 413; -- phaddw_Pq_Qq SANITY when 2 => NEXT_OUTS <= 1564; -- phaddd_Pq_Qq SANITY when 3 => NEXT_OUTS <= 19; -- phaddsw_Pq_Qq SANITY when 4 => NEXT_OUTS <= 245; -- pmaddubsw_Pq_Qq SANITY when 5 => NEXT_OUTS <= 470; -- phsubw_Pq_Qq SANITY when 6 => NEXT_OUTS <= 637; -- phsubd_Pq_Qq SANITY when 7 => NEXT_OUTS <= 11; -- phsubsw_Pq_Qq SANITY when 8 => NEXT_OUTS <= 753; -- psignb_Pq_Qq SANITY when 9 => NEXT_OUTS <= 997; -- psignw_Pq_Qq SANITY when 10 => NEXT_OUTS <= 458; -- psignd_Pq_Qq SANITY when 11 => NEXT_OUTS <= 984; -- pmulhrsw_Pq_Qq SANITY when 28 => NEXT_OUTS <= 1644; -- pabsb_Pq_Qq SANITY when 29 => NEXT_OUTS <= 1103; -- pabsw_Pq_Qq SANITY when 30 => NEXT_OUTS <= 752; -- pabsd_Pq_Qq SANITY when 240 => NEXT_OUTS <= 1090; -- movbe_Gd_Md SANITY when 241 => case OP4 is when 195 => NEXT_OUTS <= 105; -- movbe_Md_Gd SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 58 => case OP3 is when 15 => NEXT_OUTS <= 1304; -- palignr_Pq_Qq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 64 => NEXT_OUTS <= 1544; -- cmovol_Gd_Ed SANITY when 65 => NEXT_OUTS <= 867; -- cmovnol_Gd_Ed SANITY when 66 => NEXT_OUTS <= 1247; -- cmovcl_Gd_Ed SANITY when 67 => NEXT_OUTS <= 403; -- cmovncl_Gd_Ed SANITY when 68 => NEXT_OUTS <= 1638; -- cmovzl_Gd_Ed SANITY when 69 => NEXT_OUTS <= 1132; -- cmovnzl_Gd_Ed SANITY when 70 => NEXT_OUTS <= 766; -- cmovnal_Gd_Ed SANITY when 71 => NEXT_OUTS <= 1566; -- cmoval_Gd_Ed SANITY when 72 => NEXT_OUTS <= 104; -- cmovsl_Gd_Ed SANITY when 73 => NEXT_OUTS <= 139; -- cmovnsl_Gd_Ed SANITY when 74 => NEXT_OUTS <= 486; -- cmovpl_Gd_Ed SANITY when 75 => NEXT_OUTS <= 1365; -- cmovnpl_Gd_Ed SANITY when 76 => NEXT_OUTS <= 902; -- cmovll_Gd_Ed SANITY when 77 => NEXT_OUTS <= 1557; -- cmovnll_Gd_Ed SANITY when 78 => NEXT_OUTS <= 942; -- cmovngl_Gd_Ed SANITY when 79 => NEXT_OUTS <= 1535; -- cmovgl_Gd_Ed SANITY when 80 => NEXT_OUTS <= 988; -- movmskps_Gd_Ups SANITY when 81 => NEXT_OUTS <= 990; -- sqrtps_Vps_Wps SANITY when 82 => NEXT_OUTS <= 502; -- rsqrtps_Vps_Wps SANITY when 83 => NEXT_OUTS <= 493; -- rcpps_Vps_Wps SANITY when 84 => NEXT_OUTS <= 801; -- andps_Vps_Wps SANITY when 85 => NEXT_OUTS <= 1431; -- andnps_Vps_Wps SANITY when 86 => NEXT_OUTS <= 103; -- orps_Vps_Wps SANITY when 87 => NEXT_OUTS <= 1642; -- xorps_Vps_Wps SANITY when 88 => NEXT_OUTS <= 1546; -- addps_Vps_Wps SANITY when 89 => NEXT_OUTS <= 943; -- mulps_Vps_Wps SANITY when 90 => NEXT_OUTS <= 40; -- cvtps2pd_Vpd_Wps SANITY when 91 => NEXT_OUTS <= 341; -- cvtdq2ps_Vps_Wdq SANITY when 92 => NEXT_OUTS <= 1223; -- subps_Vps_Wps SANITY when 93 => NEXT_OUTS <= 828; -- minps_Vps_Wps SANITY when 94 => NEXT_OUTS <= 1141; -- divps_Vps_Wps SANITY when 95 => NEXT_OUTS <= 1376; -- maxps_Vps_Wps SANITY when 96 => NEXT_OUTS <= 1571; -- punpcklbw_Pq_Qd SANITY when 97 => NEXT_OUTS <= 322; -- punpcklwd_Pq_Qd SANITY when 98 => NEXT_OUTS <= 1384; -- punpckldq_Pq_Qd SANITY when 99 => NEXT_OUTS <= 714; -- packsswb_Pq_Qq SANITY when 100 => NEXT_OUTS <= 352; -- pcmpgtb_Pq_Qq SANITY when 101 => NEXT_OUTS <= 789; -- pcmpgtw_Pq_Qq SANITY when 102 => NEXT_OUTS <= 439; -- pcmpgtd_Pq_Qq SANITY when 103 => NEXT_OUTS <= 657; -- packuswb_Pq_Qq SANITY when 104 => NEXT_OUTS <= 1241; -- punpckhbw_Pq_Qq SANITY when 105 => NEXT_OUTS <= 1285; -- punpckhwd_Pq_Qq SANITY when 106 => NEXT_OUTS <= 1367; -- punpckhdq_Pq_Qq SANITY when 107 => NEXT_OUTS <= 167; -- packssdw_Pq_Qq SANITY when 110 => NEXT_OUTS <= 1379; -- movd_Pq_Ed SANITY when 111 => NEXT_OUTS <= 948; -- movq_Pq_Qq SANITY when 112 => NEXT_OUTS <= 65; -- pshufw_Pq_Qq_Ib SANITY when 113 => case OP3 is when 16 => NEXT_OUTS <= 537; -- psrlw_Nq_Ib SANITY when 32 => NEXT_OUTS <= 1044; -- psraw_Nq_Ib SANITY when 48 => NEXT_OUTS <= 1388; -- psllw_Nq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 114 => case OP3 is when 16 => NEXT_OUTS <= 516; -- psrld_Nq_Ib SANITY when 32 => NEXT_OUTS <= 187; -- psrad_Nq_Ib SANITY when 48 => NEXT_OUTS <= 615; -- pslld_Nq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 115 => case OP3 is when 16 => NEXT_OUTS <= 1317; -- psrlq_Nq_Ib SANITY when 48 => NEXT_OUTS <= 849; -- psllq_Nq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 116 => NEXT_OUTS <= 434; -- pcmpeqb_Pq_Qq SANITY when 117 => NEXT_OUTS <= 981; -- pcmpeqw_Pq_Qq SANITY when 118 => NEXT_OUTS <= 295; -- pcmpeqd_Pq_Qq SANITY when 119 => NEXT_OUTS <= 663; -- emms SANITY when 126 => case OP3 is when 0 => NEXT_OUTS <= 1166; -- movd_Ed_Pq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 127 => NEXT_OUTS <= 1029; -- movq_Qq_Pq SANITY when 128 => NEXT_OUTS <= 1081; -- jo_Jd SANITY when 129 => NEXT_OUTS <= 291; -- jno_Jd SANITY when 130 => NEXT_OUTS <= 950; -- jb_Jd SANITY when 131 => NEXT_OUTS <= 1601; -- jnb_Jd SANITY when 132 => NEXT_OUTS <= 364; -- jz_Jd SANITY when 133 => NEXT_OUTS <= 1655; -- jnz_Jd SANITY when 134 => NEXT_OUTS <= 1179; -- jbe_Jd SANITY when 135 => NEXT_OUTS <= 1588; -- jnbe_Jd SANITY when 136 => NEXT_OUTS <= 1073; -- js_Jd SANITY when 137 => NEXT_OUTS <= 257; -- jns_Jd SANITY when 138 => NEXT_OUTS <= 256; -- jp_Jd SANITY when 139 => NEXT_OUTS <= 1538; -- jnp_Jd SANITY when 140 => NEXT_OUTS <= 759; -- jl_Jd SANITY when 141 => NEXT_OUTS <= 58; -- jnl_Jd SANITY when 142 => NEXT_OUTS <= 983; -- jle_Jd SANITY when 143 => NEXT_OUTS <= 821; -- jnle_Jd SANITY when 144 => NEXT_OUTS <= 349; -- seto_Eb SANITY when 145 => NEXT_OUTS <= 455; -- setno_Eb SANITY when 146 => NEXT_OUTS <= 565; -- setb_Eb SANITY when 147 => NEXT_OUTS <= 1211; -- setnb_Eb SANITY when 148 => NEXT_OUTS <= 337; -- setz_Eb SANITY when 149 => NEXT_OUTS <= 231; -- setnz_Eb SANITY when 150 => NEXT_OUTS <= 1612; -- setbe_Eb SANITY when 151 => NEXT_OUTS <= 192; -- setnbe_Eb SANITY when 152 => NEXT_OUTS <= 239; -- sets_Eb SANITY when 153 => NEXT_OUTS <= 1235; -- setns_Eb SANITY when 154 => NEXT_OUTS <= 1640; -- setp_Eb SANITY when 155 => NEXT_OUTS <= 1116; -- setnp_Eb SANITY when 156 => NEXT_OUTS <= 445; -- setl_Eb SANITY when 157 => NEXT_OUTS <= 1474; -- setnl_Eb SANITY when 158 => NEXT_OUTS <= 332; -- setle_Eb SANITY when 159 => NEXT_OUTS <= 776; -- setnle_Eb SANITY when 160 => case OP3 is when 0 => NEXT_OUTS <= 133; -- pushl_FS SANITY when 1 => NEXT_OUTS <= 822; -- pushq_FS SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 161 => case OP3 is when 0 => NEXT_OUTS <= 1463; -- popl_FS SANITY when 1 => NEXT_OUTS <= 1515; -- popq_FS SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 162 => NEXT_OUTS <= 354; -- cpuid SANITY when 163 => NEXT_OUTS <= 1433; -- btl_Ed_Gd SANITY when 164 => NEXT_OUTS <= 1504; -- shldl_Ed_Gd_Ib SANITY when 165 => NEXT_OUTS <= 118; -- shldl_Ed_Gd_CL SANITY when 168 => case OP3 is when 0 => NEXT_OUTS <= 1065; -- pushl_GS SANITY when 1 => NEXT_OUTS <= 1634; -- pushq_GS SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 169 => case OP3 is when 0 => NEXT_OUTS <= 292; -- popl_GS SANITY when 1 => NEXT_OUTS <= 1437; -- popq_GS SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 170 => NEXT_OUTS <= 499; -- rsm SANITY when 171 => NEXT_OUTS <= 1554; -- btsl_Ed_Gd SANITY when 172 => NEXT_OUTS <= 961; -- shrdl_Ed_Gd_Ib SANITY when 173 => NEXT_OUTS <= 889; -- shrdl_Ed_Gd_CL SANITY when 174 => case OP3 is when 0 => NEXT_OUTS <= 416; -- fxsave SANITY when 8 => NEXT_OUTS <= 895; -- fxrstor SANITY when 16 => NEXT_OUTS <= 175; -- ldmxcsr SANITY when 24 => NEXT_OUTS <= 123; -- stmxcsr SANITY when 48 => NEXT_OUTS <= 1281; -- xsaveopt SANITY when 56 => NEXT_OUTS <= 87; -- cflush SANITY when 232 => NEXT_OUTS <= 195; -- lfence SANITY when 240 => NEXT_OUTS <= 582; -- mfence SANITY when 248 => NEXT_OUTS <= 370; -- sfence SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 175 => NEXT_OUTS <= 508; -- imull_Gd_Ed SANITY when 176 => NEXT_OUTS <= 400; -- cmpxchgb_Eb_Gb SANITY when 177 => NEXT_OUTS <= 467; -- cmpxchgl_Ed_Gd SANITY when 178 => NEXT_OUTS <= 504; -- lssl_Gd_Mp SANITY when 179 => NEXT_OUTS <= 1273; -- btrl_Ed_Gd SANITY when 180 => NEXT_OUTS <= 191; -- lfsl_Gd_Mp SANITY when 181 => NEXT_OUTS <= 122; -- lgsl_Gd_Mp SANITY when 182 => NEXT_OUTS <= 1140; -- movzbl_Gd_Eb SANITY when 183 => NEXT_OUTS <= 851; -- movzwl_Gd_Ew SANITY when 185 => case OP3 is when 0 => NEXT_OUTS <= 1358; -- ud2b SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 186 => case OP3 is when 32 => NEXT_OUTS <= 401; -- btl_Ed_Ib SANITY when 40 => NEXT_OUTS <= 1562; -- btsl_Ed_Ib SANITY when 48 => NEXT_OUTS <= 430; -- btrl_Ed_Ib SANITY when 56 => NEXT_OUTS <= 674; -- btcl_Ed_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 187 => NEXT_OUTS <= 771; -- btcl_Ed_Gd SANITY when 188 => NEXT_OUTS <= 540; -- bsfl_Gd_Ed SANITY when 189 => NEXT_OUTS <= 1399; -- bsrl_Gd_Ed SANITY when 190 => NEXT_OUTS <= 1150; -- movsbl_Gd_Eb SANITY when 191 => NEXT_OUTS <= 1413; -- movswl_Gd_Ew SANITY when 192 => NEXT_OUTS <= 524; -- xaddb_Eb_Gb SANITY when 193 => NEXT_OUTS <= 717; -- xaddl_Ed_Gd SANITY when 194 => case OP3 is when 0 => case OP4 is when 0 => NEXT_OUTS <= 447; -- cmpps_Vps_Wps_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 195 => NEXT_OUTS <= 243; -- movnti_Md_Gd SANITY when 196 => case OP3 is when 0 => NEXT_OUTS <= 21; -- pinsrw_Pq_Ew_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 197 => NEXT_OUTS <= 769; -- pextrw_Gd_Nq_Ib SANITY when 198 => NEXT_OUTS <= 246; -- shufps_Vps_Wps_Ib SANITY when 199 => case OP3 is when 8 => NEXT_OUTS <= 41; -- cmpxchg8b_Mq SANITY when 48 => NEXT_OUTS <= 884; -- vmptrld_Mq SANITY when 56 => NEXT_OUTS <= 407; -- vmptrst_Mq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 200 => NEXT_OUTS <= 1417; -- bswapl_ERX SANITY when 209 => NEXT_OUTS <= 1545; -- psrlw_Pq_Qq SANITY when 210 => NEXT_OUTS <= 311; -- psrld_Pq_Qq SANITY when 211 => NEXT_OUTS <= 810; -- psrlq_Pq_Qq SANITY when 212 => NEXT_OUTS <= 1118; -- paddq_Pq_Qq SANITY when 213 => NEXT_OUTS <= 699; -- pmullw_Pq_Qq SANITY when 215 => NEXT_OUTS <= 1126; -- pmovmskb_Gd_Nq SANITY when 216 => NEXT_OUTS <= 169; -- psubusb_Pq_Qq SANITY when 217 => NEXT_OUTS <= 151; -- psubusw_Pq_Qq SANITY when 218 => NEXT_OUTS <= 150; -- pminub_Pq_Qq SANITY when 219 => NEXT_OUTS <= 974; -- pand_Pq_Qq SANITY when 220 => NEXT_OUTS <= 831; -- paddusb_Pq_Qq SANITY when 221 => NEXT_OUTS <= 1430; -- paddusw_Pq_Qq SANITY when 222 => NEXT_OUTS <= 496; -- pmaxub_Pq_Qq SANITY when 223 => NEXT_OUTS <= 1660; -- pandn_Pq_Qq SANITY when 224 => NEXT_OUTS <= 258; -- pavgb_Pq_Qq SANITY when 225 => NEXT_OUTS <= 1266; -- psraw_Pq_Qq SANITY when 226 => NEXT_OUTS <= 1560; -- psrad_Pq_Qq SANITY when 227 => NEXT_OUTS <= 1659; -- pavgw_Pq_Qq SANITY when 228 => NEXT_OUTS <= 1019; -- pmulhuw_Pq_Qq SANITY when 229 => NEXT_OUTS <= 448; -- pmulhw_Pq_Qq SANITY when 231 => NEXT_OUTS <= 186; -- movntq_Mq_Pq SANITY when 232 => NEXT_OUTS <= 16; -- psubsb_Pq_Qq SANITY when 233 => NEXT_OUTS <= 1080; -- psubsw_Pq_Qq SANITY when 234 => NEXT_OUTS <= 588; -- pminsw_Pq_Qq SANITY when 235 => NEXT_OUTS <= 638; -- por_Pq_Qq SANITY when 236 => NEXT_OUTS <= 738; -- paddsb_Pq_Qq SANITY when 237 => NEXT_OUTS <= 531; -- paddsw_Pq_Qq SANITY when 238 => NEXT_OUTS <= 1480; -- pmaxsw_Pq_Qq SANITY when 239 => NEXT_OUTS <= 91; -- pxor_Pq_Qq SANITY when 241 => NEXT_OUTS <= 1615; -- psllw_Pq_Qq SANITY when 242 => NEXT_OUTS <= 1482; -- pslld_Pq_Qq SANITY when 243 => NEXT_OUTS <= 1532; -- psllq_Pq_Qq SANITY when 244 => NEXT_OUTS <= 228; -- pmuludq_Pq_Qq SANITY when 245 => NEXT_OUTS <= 1593; -- pmaddwd_Pq_Qq SANITY when 246 => NEXT_OUTS <= 957; -- psadbw_Pq_Qq SANITY when 247 => NEXT_OUTS <= 269; -- maskmovq_Pq_Nq SANITY when 248 => NEXT_OUTS <= 1085; -- psubb_Pq_Qq SANITY when 249 => NEXT_OUTS <= 1189; -- psubw_Pq_Qq SANITY when 250 => NEXT_OUTS <= 211; -- psubd_Pq_Qq SANITY when 251 => NEXT_OUTS <= 535; -- psubq_Pq_Qq SANITY when 252 => NEXT_OUTS <= 428; -- paddb_Pq_Qq SANITY when 253 => NEXT_OUTS <= 554; -- paddw_Pq_Qq SANITY when 254 => NEXT_OUTS <= 617; -- paddd_Pq_Qq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 16 => NEXT_OUTS <= 546; -- adcb_Eb_Gb SANITY when 17 => NEXT_OUTS <= 611; -- adcl_Ed_Gd SANITY when 18 => NEXT_OUTS <= 384; -- adcb_Gb_Eb SANITY when 19 => NEXT_OUTS <= 1484; -- adcl_Gd_Ed SANITY when 20 => NEXT_OUTS <= 541; -- adcb_AL_Ib SANITY when 21 => NEXT_OUTS <= 1256; -- adcl_EAX_Id SANITY when 22 => NEXT_OUTS <= 115; -- pushl_SS SANITY when 23 => NEXT_OUTS <= 1563; -- popl_SS SANITY when 24 => NEXT_OUTS <= 1345; -- sbbb_Eb_Gb SANITY when 25 => NEXT_OUTS <= 1530; -- sbbl_Ed_Gd SANITY when 26 => NEXT_OUTS <= 1200; -- sbbb_Gb_Eb SANITY when 27 => NEXT_OUTS <= 61; -- sbbl_Gd_Ed SANITY when 28 => NEXT_OUTS <= 684; -- sbbb_AL_Ib SANITY when 29 => NEXT_OUTS <= 340; -- sbbl_EAX_Id SANITY when 30 => NEXT_OUTS <= 1663; -- pushl_DS SANITY when 31 => NEXT_OUTS <= 1385; -- popl_DS SANITY when 32 => NEXT_OUTS <= 1274; -- andb_Eb_Gb SANITY when 33 => NEXT_OUTS <= 1454; -- andl_Ed_Gd SANITY when 34 => NEXT_OUTS <= 1503; -- andb_Gb_Eb SANITY when 35 => NEXT_OUTS <= 1260; -- andl_Gd_Ed SANITY when 36 => NEXT_OUTS <= 982; -- andb_AL_Ib SANITY when 37 => NEXT_OUTS <= 527; -- andl_EAX_Id SANITY when 39 => NEXT_OUTS <= 345; -- daa SANITY when 40 => NEXT_OUTS <= 1186; -- subb_Eb_Gb SANITY when 41 => NEXT_OUTS <= 399; -- subl_Ed_Gd SANITY when 42 => NEXT_OUTS <= 835; -- subb_Gb_Eb SANITY when 43 => NEXT_OUTS <= 98; -- subl_Gd_Ed SANITY when 44 => NEXT_OUTS <= 834; -- subb_AL_Ib SANITY when 45 => NEXT_OUTS <= 394; -- subl_EAX_Id SANITY when 47 => NEXT_OUTS <= 1169; -- das SANITY when 48 => NEXT_OUTS <= 1027; -- xorb_Eb_Gb SANITY when 49 => NEXT_OUTS <= 630; -- xorl_Ed_Gd SANITY when 50 => NEXT_OUTS <= 817; -- xorb_Gb_Eb SANITY when 51 => NEXT_OUTS <= 1297; -- xorl_Gd_Ed SANITY when 52 => NEXT_OUTS <= 408; -- xorb_AL_Ib SANITY when 53 => NEXT_OUTS <= 1306; -- xorl_EAX_Id SANITY when 55 => NEXT_OUTS <= 377; -- aaa SANITY when 56 => NEXT_OUTS <= 1227; -- cmpb_Eb_Gb SANITY when 57 => NEXT_OUTS <= 179; -- cmpl_Ed_Gd SANITY when 58 => NEXT_OUTS <= 946; -- cmpb_Gb_Eb SANITY when 59 => NEXT_OUTS <= 242; -- cmpl_Gd_Ed SANITY when 60 => NEXT_OUTS <= 81; -- cmpb_AL_Ib SANITY when 61 => NEXT_OUTS <= 507; -- cmpl_EAX_Id SANITY when 63 => NEXT_OUTS <= 1005; -- aas SANITY when 64 => NEXT_OUTS <= 758; -- incl_ERX SANITY when 72 => case OP2 is when 1 => NEXT_OUTS <= 459; -- addq_Eq_Gq SANITY when 3 => NEXT_OUTS <= 249; -- addq_Gq_Eq SANITY when 5 => NEXT_OUTS <= 166; -- addq_RAX_sId SANITY when 9 => NEXT_OUTS <= 1442; -- orq_Eq_Gq SANITY when 11 => NEXT_OUTS <= 307; -- orq_Gq_Eq SANITY when 13 => NEXT_OUTS <= 805; -- orq_RAX_sId SANITY when 15 => case OP3 is when 2 => case OP4 is when 0 => NEXT_OUTS <= 276; -- larq_Gq_Ew SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 3 => case OP4 is when 0 => NEXT_OUTS <= 784; -- lslq_Gq_Ew SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 56 => case OP4 is when 240 => NEXT_OUTS <= 1389; -- movbe_Gq_Mq SANITY when 241 => case OP5 is when 195 => NEXT_OUTS <= 381; -- movbe_Mq_Gq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 64 => NEXT_OUTS <= 1314; -- cmovoq_Gq_Eq SANITY when 65 => NEXT_OUTS <= 765; -- cmovnoq_Gq_Eq SANITY when 66 => NEXT_OUTS <= 900; -- cmovcq_Gq_Eq SANITY when 67 => NEXT_OUTS <= 658; -- cmovncq_Gq_Eq SANITY when 68 => NEXT_OUTS <= 1002; -- cmovzq_Gq_Eq SANITY when 69 => NEXT_OUTS <= 1380; -- cmovnzq_Gq_Eq SANITY when 70 => NEXT_OUTS <= 1343; -- cmovnaq_Gq_Eq SANITY when 71 => NEXT_OUTS <= 1138; -- cmovaq_Gq_Eq SANITY when 72 => NEXT_OUTS <= 1404; -- cmovsq_Gq_Eq SANITY when 73 => NEXT_OUTS <= 1292; -- cmovnsq_Gq_Eq SANITY when 74 => NEXT_OUTS <= 742; -- cmovpq_Gq_Eq SANITY when 75 => NEXT_OUTS <= 335; -- cmovnpq_Gq_Eq SANITY when 76 => NEXT_OUTS <= 1344; -- cmovlq_Gq_Eq SANITY when 77 => NEXT_OUTS <= 1522; -- cmovnlq_Gq_Eq SANITY when 78 => NEXT_OUTS <= 358; -- cmovngq_Gq_Eq SANITY when 79 => NEXT_OUTS <= 995; -- cmovgq_Gq_Eq SANITY when 110 => NEXT_OUTS <= 1228; -- movq_Pq_Eq SANITY when 126 => case OP4 is when 0 => NEXT_OUTS <= 168; -- movq_Eq_Pq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 163 => NEXT_OUTS <= 548; -- btq_Eq_Gq SANITY when 164 => NEXT_OUTS <= 780; -- shldq_Eq_Gq_Ib SANITY when 165 => NEXT_OUTS <= 819; -- shldq_Eq_Gq_CL SANITY when 171 => NEXT_OUTS <= 597; -- btsq_Eq_Gq SANITY when 172 => NEXT_OUTS <= 813; -- shrdq_Eq_Gq_Ib SANITY when 173 => NEXT_OUTS <= 1371; -- shrdq_Eq_Gq_CL SANITY when 175 => NEXT_OUTS <= 1024; -- imulq_Gq_Eq SANITY when 177 => NEXT_OUTS <= 1415; -- cmpxchgq_Eq_Gq SANITY when 178 => NEXT_OUTS <= 806; -- lssq_Gq_Mp SANITY when 179 => NEXT_OUTS <= 1205; -- btrq_Eq_Gq SANITY when 180 => NEXT_OUTS <= 474; -- lfsq_Gq_Mp SANITY when 181 => NEXT_OUTS <= 281; -- lgsq_Gq_Mp SANITY when 182 => NEXT_OUTS <= 453; -- movzbq_Gq_Eb SANITY when 183 => NEXT_OUTS <= 386; -- movzwq_Gq_Ew SANITY when 186 => case OP4 is when 32 => NEXT_OUTS <= 740; -- btq_Eq_Ib SANITY when 40 => NEXT_OUTS <= 171; -- btsq_Eq_Ib SANITY when 48 => NEXT_OUTS <= 301; -- btrq_Eq_Ib SANITY when 56 => NEXT_OUTS <= 1207; -- btcq_Eq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 187 => NEXT_OUTS <= 96; -- btcq_Eq_Gq SANITY when 188 => NEXT_OUTS <= 334; -- bsfq_Gq_Eq SANITY when 189 => NEXT_OUTS <= 1386; -- bsrq_Gq_Eq SANITY when 190 => NEXT_OUTS <= 1035; -- movsbq_Gq_Eb SANITY when 191 => NEXT_OUTS <= 711; -- movswq_Gq_Ew SANITY when 193 => NEXT_OUTS <= 1396; -- xaddq_Eq_Gq SANITY when 195 => NEXT_OUTS <= 1059; -- movntiq_Mq_Gq SANITY when 199 => case OP4 is when 8 => NEXT_OUTS <= 665; -- cmpxchg16b_Mdq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 200 => NEXT_OUTS <= 1584; -- bswapq_RRX SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 17 => NEXT_OUTS <= 1133; -- adcq_Eq_Gq SANITY when 19 => NEXT_OUTS <= 1068; -- adcq_Gq_Eq SANITY when 21 => NEXT_OUTS <= 479; -- adcq_RAX_sId SANITY when 25 => NEXT_OUTS <= 503; -- sbbq_Eq_Gq SANITY when 27 => NEXT_OUTS <= 226; -- sbbq_Gq_Eq SANITY when 29 => NEXT_OUTS <= 1624; -- sbbq_RAX_sId SANITY when 33 => NEXT_OUTS <= 1397; -- andq_Eq_Gq SANITY when 35 => NEXT_OUTS <= 1267; -- andq_Gq_Eq SANITY when 37 => NEXT_OUTS <= 1323; -- andq_RAX_sId SANITY when 41 => NEXT_OUTS <= 1518; -- subq_Eq_Gq SANITY when 43 => NEXT_OUTS <= 1100; -- subq_Gq_Eq SANITY when 45 => NEXT_OUTS <= 224; -- subq_RAX_sId SANITY when 49 => NEXT_OUTS <= 929; -- xorq_Eq_Gq SANITY when 51 => NEXT_OUTS <= 1494; -- xorq_Gq_Eq SANITY when 53 => NEXT_OUTS <= 994; -- xorq_RAX_sId SANITY when 57 => NEXT_OUTS <= 1231; -- cmpq_Eq_Gq SANITY when 59 => NEXT_OUTS <= 59; -- cmpq_Gq_Eq SANITY when 61 => NEXT_OUTS <= 687; -- cmpq_RAX_sId SANITY when 99 => NEXT_OUTS <= 1136; -- movslq_Gq_Ed SANITY when 105 => NEXT_OUTS <= 1409; -- imulq_Gq_Eq_sId SANITY when 107 => NEXT_OUTS <= 409; -- imulq_Gq_Eq_sIb SANITY when 129 => case OP3 is when 0 => NEXT_OUTS <= 1270; -- addq_Eq_sId SANITY when 8 => NEXT_OUTS <= 645; -- orq_Eq_sId SANITY when 16 => NEXT_OUTS <= 248; -- adcq_Eq_sId SANITY when 24 => NEXT_OUTS <= 512; -- sbbq_Eq_sId SANITY when 32 => NEXT_OUTS <= 1296; -- andq_Eq_sId SANITY when 40 => NEXT_OUTS <= 1630; -- subq_Eq_sId SANITY when 48 => NEXT_OUTS <= 288; -- xorq_Eq_sId SANITY when 56 => NEXT_OUTS <= 1020; -- cmpq_Eq_sId SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 131 => case OP3 is when 0 => NEXT_OUTS <= 484; -- addq_Eq_sIb SANITY when 8 => NEXT_OUTS <= 794; -- orq_Eq_sIb SANITY when 16 => NEXT_OUTS <= 1664; -- adcq_Eq_sIb SANITY when 24 => NEXT_OUTS <= 737; -- sbbq_Eq_sIb SANITY when 32 => NEXT_OUTS <= 1581; -- andq_Eq_sIb SANITY when 40 => NEXT_OUTS <= 183; -- subq_Eq_sIb SANITY when 48 => NEXT_OUTS <= 278; -- xorq_Eq_sIb SANITY when 56 => NEXT_OUTS <= 1594; -- cmpq_Eq_sIb SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 133 => NEXT_OUTS <= 472; -- testq_Eq_Gq SANITY when 135 => NEXT_OUTS <= 595; -- xchgq_Eq_Gq SANITY when 137 => NEXT_OUTS <= 102; -- movq_Eq_Gq SANITY when 139 => NEXT_OUTS <= 1632; -- movq_Gq_Eq SANITY when 141 => NEXT_OUTS <= 181; -- leaq_Gq_Mq SANITY when 145 => NEXT_OUTS <= 906; -- xchgq_RRX_RAX SANITY when 152 => NEXT_OUTS <= 47; -- cdqe SANITY when 153 => NEXT_OUTS <= 147; -- cqo SANITY when 161 => NEXT_OUTS <= 888; -- movq_RAX_Oq SANITY when 163 => NEXT_OUTS <= 1578; -- movq_Oq_RAX SANITY when 165 => NEXT_OUTS <= 1046; -- movsq_Yq_Xq SANITY when 167 => NEXT_OUTS <= 154; -- cmpsq_Yq_Xq SANITY when 169 => NEXT_OUTS <= 931; -- testq_RAX_sId SANITY when 171 => NEXT_OUTS <= 610; -- stosq_Yq_RAX SANITY when 173 => NEXT_OUTS <= 1613; -- lodsq_RAX_Xq SANITY when 175 => NEXT_OUTS <= 539; -- scasq_Yq_RAX SANITY when 184 => NEXT_OUTS <= 1255; -- movq_RRX_Iq SANITY when 193 => case OP3 is when 0 => NEXT_OUTS <= 327; -- rolq_Eq_Ib SANITY when 8 => NEXT_OUTS <= 816; -- rorq_Eq_Ib SANITY when 16 => NEXT_OUTS <= 402; -- rclq_Eq_Ib SANITY when 24 => NEXT_OUTS <= 261; -- rcrq_Eq_Ib SANITY when 32 => NEXT_OUTS <= 346; -- shlq_Eq_Ib SANITY when 40 => NEXT_OUTS <= 1147; -- shrq_Eq_Ib SANITY when 56 => NEXT_OUTS <= 463; -- sarq_Eq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 199 => case OP3 is when 0 => NEXT_OUTS <= 446; -- movq_Eq_sId SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 207 => NEXT_OUTS <= 799; -- iretq SANITY when 209 => case OP3 is when 0 => NEXT_OUTS <= 1075; -- rolq_Eq_I1 SANITY when 8 => NEXT_OUTS <= 783; -- rorq_Eq_I1 SANITY when 16 => NEXT_OUTS <= 273; -- rclq_Eq_I1 SANITY when 24 => NEXT_OUTS <= 649; -- rcrq_Eq_I1 SANITY when 32 => NEXT_OUTS <= 1582; -- shlq_Eq_I1 SANITY when 40 => NEXT_OUTS <= 236; -- shrq_Eq_I1 SANITY when 56 => NEXT_OUTS <= 406; -- sarq_Eq_I1 SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 211 => case OP3 is when 0 => NEXT_OUTS <= 1137; -- rolq_Eq_CL SANITY when 8 => NEXT_OUTS <= 308; -- rorq_Eq_CL SANITY when 16 => NEXT_OUTS <= 55; -- rclq_Eq_CL SANITY when 24 => NEXT_OUTS <= 1123; -- rcrq_Eq_CL SANITY when 32 => NEXT_OUTS <= 355; -- shlq_Eq_CL SANITY when 40 => NEXT_OUTS <= 1359; -- shrq_Eq_CL SANITY when 56 => NEXT_OUTS <= 1194; -- sarq_Eq_CL SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 247 => case OP3 is when 0 => NEXT_OUTS <= 1453; -- testq_Eq_sId SANITY when 16 => NEXT_OUTS <= 635; -- notq_Eq SANITY when 24 => NEXT_OUTS <= 27; -- negq_Eq SANITY when 32 => NEXT_OUTS <= 1326; -- mulq_RAX_Eq SANITY when 40 => NEXT_OUTS <= 221; -- imulq_RAX_Eq SANITY when 48 => NEXT_OUTS <= 418; -- divq_RAX_Eq SANITY when 56 => NEXT_OUTS <= 1067; -- idivq_RAX_Eq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 255 => case OP3 is when 0 => NEXT_OUTS <= 731; -- incq_Eq SANITY when 8 => NEXT_OUTS <= 1164; -- decq_Eq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 80 => case OP2 is when 0 => NEXT_OUTS <= 879; -- pushl_ERX SANITY when 1 => NEXT_OUTS <= 798; -- pushq_RRX SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 88 => case OP2 is when 0 => NEXT_OUTS <= 937; -- popl_ERX SANITY when 1 => NEXT_OUTS <= 128; -- popq_RRX SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 96 => NEXT_OUTS <= 1512; -- pushal SANITY when 97 => NEXT_OUTS <= 76; -- popal SANITY when 98 => NEXT_OUTS <= 897; -- boundl_Gd_Ma SANITY when 99 => NEXT_OUTS <= 36; -- arpl_Ew_Gw SANITY when 102 => case OP2 is when 1 => case OP3 is when 0 => NEXT_OUTS <= 356; -- addw_Ew_Gw SANITY when 1 => NEXT_OUTS <= 581; -- decw_RX SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 3 => NEXT_OUTS <= 777; -- addw_Gw_Ew SANITY when 5 => NEXT_OUTS <= 444; -- addw_AX_Iw SANITY when 6 => NEXT_OUTS <= 197; -- pushw_ES SANITY when 7 => NEXT_OUTS <= 1364; -- popw_ES SANITY when 9 => NEXT_OUTS <= 587; -- orw_Ew_Gw SANITY when 11 => NEXT_OUTS <= 315; -- orw_Gw_Ew SANITY when 13 => NEXT_OUTS <= 1293; -- orw_AX_Iw SANITY when 14 => NEXT_OUTS <= 1224; -- pushw_CS SANITY when 15 => case OP3 is when 2 => case OP4 is when 0 => NEXT_OUTS <= 142; -- larw_Gw_Ew SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 3 => case OP4 is when 0 => NEXT_OUTS <= 174; -- lslw_Gw_Ew SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 16 => NEXT_OUTS <= 490; -- movupd_Vpd_Wpd SANITY when 17 => NEXT_OUTS <= 124; -- movupd_Wpd_Vpd SANITY when 18 => NEXT_OUTS <= 788; -- movlpd_Vpd_Mq SANITY when 19 => NEXT_OUTS <= 86; -- movlpd_Mq_Vpd SANITY when 20 => NEXT_OUTS <= 120; -- unpcklpd_Vpd_Wpd SANITY when 21 => NEXT_OUTS <= 585; -- unpckhpd_Vpd_Wpd SANITY when 22 => NEXT_OUTS <= 854; -- movhpd_Vpd_Mq SANITY when 23 => NEXT_OUTS <= 8; -- movhpd_Mq_Vpd SANITY when 40 => NEXT_OUTS <= 622; -- movapd_Vpd_Wpd SANITY when 41 => NEXT_OUTS <= 662; -- movapd_Wpd_Vpd SANITY when 42 => NEXT_OUTS <= 624; -- cvtpi2pd_Vpd_Qq SANITY when 44 => NEXT_OUTS <= 146; -- cvttpd2pi_Pq_Wpd SANITY when 45 => NEXT_OUTS <= 1124; -- cvtpd2pi_Pq_Wpd SANITY when 46 => NEXT_OUTS <= 1606; -- ucomisd_Vsd_Wsd SANITY when 47 => NEXT_OUTS <= 339; -- comisd_Vsd_Wsd SANITY when 56 => case OP4 is when 0 => NEXT_OUTS <= 739; -- pshufb_Vdq_Wdq SANITY when 1 => NEXT_OUTS <= 1160; -- phaddw_Vdq_Wdq SANITY when 2 => NEXT_OUTS <= 485; -- phaddd_Vdq_Wdq SANITY when 3 => NEXT_OUTS <= 330; -- phaddsw_Vdq_Wdq SANITY when 4 => NEXT_OUTS <= 1042; -- pmaddubsw_Vdq_Wdq SANITY when 5 => NEXT_OUTS <= 909; -- phsubw_Vdq_Wdq SANITY when 6 => NEXT_OUTS <= 578; -- phsubd_Vdq_Wdq SANITY when 7 => NEXT_OUTS <= 677; -- phsubsw_Vdq_Wdq SANITY when 8 => NEXT_OUTS <= 574; -- psignb_Vdq_Wdq SANITY when 9 => NEXT_OUTS <= 1190; -- psignw_Vdq_Wdq SANITY when 10 => NEXT_OUTS <= 971; -- psignd_Vdq_Wdq SANITY when 11 => NEXT_OUTS <= 1144; -- pmulhrsw_Vdq_Wdq SANITY when 16 => NEXT_OUTS <= 223; -- pblendvb_Vdq_Wdq SANITY when 20 => NEXT_OUTS <= 395; -- blendvps_Vps_Wps SANITY when 21 => NEXT_OUTS <= 1239; -- blendvpd_Vpd_Wpd SANITY when 23 => NEXT_OUTS <= 1641; -- ptest_Vdq_Wdq SANITY when 28 => NEXT_OUTS <= 836; -- pabsb_Vdq_Wdq SANITY when 29 => NEXT_OUTS <= 60; -- pabsw_Vdq_Wdq SANITY when 30 => NEXT_OUTS <= 696; -- pabsd_Vdq_Wdq SANITY when 32 => case OP5 is when 1 => NEXT_OUTS <= 1496; -- pmovsxbw_Vdq_Wq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 33 => NEXT_OUTS <= 1004; -- pmovsxbd_Vdq_Wd SANITY when 34 => NEXT_OUTS <= 721; -- pmovsxbq_Vdq_Ww SANITY when 35 => NEXT_OUTS <= 1514; -- pmovsxwd_Vdq_Wq SANITY when 36 => NEXT_OUTS <= 49; -- pmovsxwq_Vdq_Wd SANITY when 37 => NEXT_OUTS <= 134; -- pmovsxdq_Vdq_Wq SANITY when 40 => NEXT_OUTS <= 1555; -- pmuldq_Vdq_Wdq SANITY when 41 => NEXT_OUTS <= 451; -- pcmpeqq_Vdq_Wdq SANITY when 42 => NEXT_OUTS <= 848; -- movntdqa_Vdq_Mdq SANITY when 43 => NEXT_OUTS <= 564; -- packusdw_Vdq_Wdq SANITY when 48 => NEXT_OUTS <= 697; -- pmovzxbw_Vdq_Wq SANITY when 49 => NEXT_OUTS <= 353; -- pmovzxbd_Vdq_Wd SANITY when 50 => NEXT_OUTS <= 1524; -- pmovzxbq_Vdq_Ww SANITY when 51 => NEXT_OUTS <= 491; -- pmovzxwd_Vdq_Wq SANITY when 52 => NEXT_OUTS <= 1307; -- pmovzxwq_Vdq_Wd SANITY when 53 => NEXT_OUTS <= 389; -- pmovzxdq_Vdq_Wq SANITY when 55 => NEXT_OUTS <= 144; -- pcmpgtq_Vdq_Wdq SANITY when 56 => NEXT_OUTS <= 189; -- pminsb_Vdq_Wdq SANITY when 57 => NEXT_OUTS <= 452; -- pminsd_Vdq_Wdq SANITY when 58 => NEXT_OUTS <= 907; -- pminuw_Vdq_Wdq SANITY when 59 => NEXT_OUTS <= 1115; -- pminud_Vdq_Wdq SANITY when 60 => NEXT_OUTS <= 551; -- pmaxsb_Vdq_Wdq SANITY when 61 => NEXT_OUTS <= 1471; -- pmaxsd_Vdq_Wdq SANITY when 62 => NEXT_OUTS <= 1499; -- pmaxuw_Vdq_Wdq SANITY when 63 => NEXT_OUTS <= 991; -- pmaxud_Vdq_Wdq SANITY when 64 => NEXT_OUTS <= 20; -- pmulld_Vdq_Wdq SANITY when 65 => NEXT_OUTS <= 914; -- phminposuw_Vdq_Wdq SANITY when 130 => NEXT_OUTS <= 1418; -- invpcid_Gy_Mdq SANITY when 219 => NEXT_OUTS <= 935; -- aesimc_Vdq_Wdq SANITY when 220 => NEXT_OUTS <= 1639; -- aesenc_Vdq_Wdq SANITY when 221 => NEXT_OUTS <= 807; -- aesenclast_Vdq_Wdq SANITY when 222 => NEXT_OUTS <= 1438; -- aesdec_Vdq_Wdq SANITY when 223 => NEXT_OUTS <= 534; -- aesdeclast_Vdq_Wdq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 58 => case OP4 is when 8 => NEXT_OUTS <= 1347; -- roundps_Vps_Wps_Ib SANITY when 9 => NEXT_OUTS <= 1268; -- roundpd_Vpd_Wpd_Ib SANITY when 10 => NEXT_OUTS <= 655; -- roundss_Vss_Wss_Ib SANITY when 11 => NEXT_OUTS <= 56; -- roundsd_Vsd_Wsd_Ib SANITY when 12 => NEXT_OUTS <= 90; -- blendps_Vps_Wps_Ib SANITY when 13 => NEXT_OUTS <= 1182; -- blendpd_Vpd_Wpd_Ib SANITY when 14 => NEXT_OUTS <= 1324; -- pblendw_Vdq_Wdq_Ib SANITY when 15 => NEXT_OUTS <= 1349; -- palignr_Vdq_Wdq_Ib SANITY when 20 => case OP5 is when 0 => NEXT_OUTS <= 424; -- pextrb_Ebd_Vdq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 21 => case OP5 is when 0 => NEXT_OUTS <= 561; -- pextrw_Ewd_Vdq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 22 => NEXT_OUTS <= 1620; -- pextrd_Ed_Vdq_Ib SANITY when 23 => NEXT_OUTS <= 220; -- extractps_Ed_Vdq_Ib SANITY when 32 => NEXT_OUTS <= 300; -- pinsrb_Vdq_Ed_Ib SANITY when 33 => NEXT_OUTS <= 482; -- insertps_Vps_Wss_Ib SANITY when 34 => NEXT_OUTS <= 1391; -- pinsrd_Vdq_Ed_Ib SANITY when 64 => NEXT_OUTS <= 992; -- dpps_Vps_Wps_Ib SANITY when 65 => NEXT_OUTS <= 1142; -- dppd_Vpd_Wpd_Ib SANITY when 66 => NEXT_OUTS <= 1526; -- mpsadbw_Vdq_Wdq_Ib SANITY when 68 => NEXT_OUTS <= 1608; -- pclmulqdq_Vdq_Wdq_Ib SANITY when 96 => NEXT_OUTS <= 755; -- pcmpestrm_Vdq_Wdq_Ib SANITY when 97 => NEXT_OUTS <= 609; -- pcmpestri_Vdq_Wdq_Ib SANITY when 98 => NEXT_OUTS <= 1148; -- pcmpistrm_Vdq_Wdq_Ib SANITY when 99 => NEXT_OUTS <= 589; -- pcmpistri_Vdq_Wdq_Ib SANITY when 223 => NEXT_OUTS <= 473; -- aeskeygenassist_Vdq_Wdq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 64 => NEXT_OUTS <= 1012; -- cmovow_Gw_Ew SANITY when 65 => NEXT_OUTS <= 1074; -- cmovnow_Gw_Ew SANITY when 66 => NEXT_OUTS <= 1643; -- cmovcw_Gw_Ew SANITY when 67 => NEXT_OUTS <= 1095; -- cmovncw_Gw_Ew SANITY when 68 => NEXT_OUTS <= 264; -- cmovzw_Gw_Ew SANITY when 69 => NEXT_OUTS <= 1548; -- cmovnzw_Gw_Ew SANITY when 70 => NEXT_OUTS <= 558; -- cmovnaw_Gw_Ew SANITY when 71 => NEXT_OUTS <= 511; -- cmovaw_Gw_Ew SANITY when 72 => NEXT_OUTS <= 823; -- cmovsw_Gw_Ew SANITY when 73 => NEXT_OUTS <= 350; -- cmovnsw_Gw_Ew SANITY when 74 => NEXT_OUTS <= 918; -- cmovpw_Gw_Ew SANITY when 75 => NEXT_OUTS <= 698; -- cmovnpw_Gw_Ew SANITY when 76 => NEXT_OUTS <= 1125; -- cmovlw_Gw_Ew SANITY when 77 => NEXT_OUTS <= 1305; -- cmovnlw_Gw_Ew SANITY when 78 => NEXT_OUTS <= 1071; -- cmovngw_Gw_Ew SANITY when 79 => NEXT_OUTS <= 342; -- cmovgw_Gw_Ew SANITY when 80 => NEXT_OUTS <= 235; -- movmskpd_Gd_Upd SANITY when 81 => NEXT_OUTS <= 1651; -- sqrtpd_Vpd_Wpd SANITY when 84 => NEXT_OUTS <= 17; -- andpd_Vpd_Wpd SANITY when 85 => NEXT_OUTS <= 492; -- andnpd_Vpd_Wpd SANITY when 86 => NEXT_OUTS <= 646; -- orpd_Vpd_Wpd SANITY when 87 => NEXT_OUTS <= 1206; -- xorpd_Vpd_Wpd SANITY when 88 => NEXT_OUTS <= 460; -- addpd_Vpd_Wpd SANITY when 89 => NEXT_OUTS <= 1264; -- mulpd_Vpd_Wpd SANITY when 90 => NEXT_OUTS <= 1243; -- cvtpd2ps_Vps_Wpd SANITY when 91 => NEXT_OUTS <= 348; -- cvtps2dq_Vdq_Wps SANITY when 92 => NEXT_OUTS <= 1218; -- subpd_Vpd_Wpd SANITY when 93 => NEXT_OUTS <= 691; -- minpd_Vpd_Wpd SANITY when 94 => NEXT_OUTS <= 284; -- divpd_Vpd_Wpd SANITY when 95 => NEXT_OUTS <= 688; -- maxpd_Vpd_Wpd SANITY when 96 => NEXT_OUTS <= 10; -- punpcklbw_Vdq_Wdq SANITY when 97 => NEXT_OUTS <= 285; -- punpcklwd_Vdq_Wdq SANITY when 98 => NEXT_OUTS <= 1238; -- punpckldq_Vdq_Wdq SANITY when 99 => NEXT_OUTS <= 68; -- packsswb_Vdq_Wdq SANITY when 100 => NEXT_OUTS <= 1040; -- pcmpgtb_Vdq_Wdq SANITY when 101 => NEXT_OUTS <= 659; -- pcmpgtw_Vdq_Wdq SANITY when 102 => NEXT_OUTS <= 22; -- pcmpgtd_Vdq_Wdq SANITY when 103 => NEXT_OUTS <= 1440; -- packuswb_Vdq_Wdq SANITY when 104 => NEXT_OUTS <= 973; -- punpckhbw_Vdq_Wdq SANITY when 105 => NEXT_OUTS <= 433; -- punpckhwd_Vdq_Wdq SANITY when 106 => NEXT_OUTS <= 435; -- punpckhdq_Vdq_Wdq SANITY when 107 => NEXT_OUTS <= 1331; -- packssdw_Vdq_Wdq SANITY when 108 => NEXT_OUTS <= 1291; -- punpcklqdq_Vdq_Wdq SANITY when 109 => NEXT_OUTS <= 125; -- punpckhqdq_Vdq_Wdq SANITY when 110 => NEXT_OUTS <= 1428; -- movd_Vdq_Ed SANITY when 111 => NEXT_OUTS <= 80; -- movdqa_Vdq_Wdq SANITY when 112 => NEXT_OUTS <= 1097; -- pshufd_Vdq_Wdq_Ib SANITY when 113 => case OP4 is when 16 => NEXT_OUTS <= 1491; -- psrlw_Udq_Ib SANITY when 32 => NEXT_OUTS <= 1485; -- psraw_Udq_Ib SANITY when 48 => NEXT_OUTS <= 483; -- psllw_Udq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 114 => case OP4 is when 16 => NEXT_OUTS <= 989; -- psrld_Udq_Ib SANITY when 32 => NEXT_OUTS <= 1106; -- psrad_Udq_Ib SANITY when 48 => NEXT_OUTS <= 1311; -- pslld_Udq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 115 => case OP4 is when 16 => NEXT_OUTS <= 1202; -- psrlq_Udq_Ib SANITY when 24 => NEXT_OUTS <= 456; -- psrldq_Udq_Ib SANITY when 48 => NEXT_OUTS <= 1572; -- psllq_Udq_Ib SANITY when 56 => NEXT_OUTS <= 832; -- pslldq_Udq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 116 => NEXT_OUTS <= 305; -- pcmpeqb_Vdq_Wdq SANITY when 117 => NEXT_OUTS <= 319; -- pcmpeqw_Vdq_Wdq SANITY when 118 => NEXT_OUTS <= 542; -- pcmpeqd_Vdq_Wdq SANITY when 124 => NEXT_OUTS <= 1271; -- haddpd_Vpd_Wpd SANITY when 125 => NEXT_OUTS <= 838; -- hsubpd_Vpd_Wpd SANITY when 126 => case OP4 is when 0 => NEXT_OUTS <= 694; -- movd_Ed_Vd SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 127 => NEXT_OUTS <= 1023; -- movdqa_Wdq_Vdq SANITY when 128 => NEXT_OUTS <= 847; -- jo_Jw SANITY when 129 => NEXT_OUTS <= 1308; -- jno_Jw SANITY when 130 => NEXT_OUTS <= 1284; -- jb_Jw SANITY when 131 => NEXT_OUTS <= 952; -- jnb_Jw SANITY when 132 => NEXT_OUTS <= 12; -- jz_Jw SANITY when 133 => NEXT_OUTS <= 1066; -- jnz_Jw SANITY when 134 => NEXT_OUTS <= 679; -- jbe_Jw SANITY when 135 => NEXT_OUTS <= 1498; -- jnbe_Jw SANITY when 136 => NEXT_OUTS <= 1048; -- js_Jw SANITY when 137 => NEXT_OUTS <= 1226; -- jns_Jw SANITY when 138 => NEXT_OUTS <= 1403; -- jp_Jw SANITY when 139 => NEXT_OUTS <= 1534; -- jnp_Jw SANITY when 140 => NEXT_OUTS <= 1445; -- jl_Jw SANITY when 141 => NEXT_OUTS <= 1531; -- jnl_Jw SANITY when 142 => NEXT_OUTS <= 333; -- jle_Jw SANITY when 143 => NEXT_OUTS <= 678; -- jnle_Jw SANITY when 160 => NEXT_OUTS <= 1605; -- pushw_FS SANITY when 161 => NEXT_OUTS <= 1151; -- popw_FS SANITY when 163 => NEXT_OUTS <= 855; -- btw_Ew_Gw SANITY when 164 => NEXT_OUTS <= 443; -- shldw_Ew_Gw_Ib SANITY when 165 => NEXT_OUTS <= 1018; -- shldw_Ew_Gw_CL SANITY when 168 => NEXT_OUTS <= 1061; -- pushw_GS SANITY when 169 => NEXT_OUTS <= 1551; -- popw_GS SANITY when 171 => NEXT_OUTS <= 1187; -- btsw_Ew_Gw SANITY when 172 => NEXT_OUTS <= 1222; -- shrdw_Ew_Gw_Ib SANITY when 173 => NEXT_OUTS <= 268; -- shrdw_Ew_Gw_CL SANITY when 175 => NEXT_OUTS <= 306; -- imulw_Gw_Ew SANITY when 177 => NEXT_OUTS <= 874; -- cmpxchgw_Ew_Gw SANITY when 178 => NEXT_OUTS <= 1215; -- lssw_Gw_Mp SANITY when 179 => NEXT_OUTS <= 1070; -- btrw_Ew_Gw SANITY when 180 => NEXT_OUTS <= 1461; -- lfsw_Gw_Mp SANITY when 181 => NEXT_OUTS <= 1139; -- lgsw_Gw_Mp SANITY when 182 => NEXT_OUTS <= 153; -- movzbw_Gw_Eb SANITY when 186 => case OP4 is when 32 => NEXT_OUTS <= 497; -- btw_Ew_Ib SANITY when 40 => NEXT_OUTS <= 796; -- btsw_Ew_Ib SANITY when 48 => NEXT_OUTS <= 872; -- btrw_Ew_Ib SANITY when 56 => NEXT_OUTS <= 157; -- btcw_Ew_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 187 => NEXT_OUTS <= 232; -- btcw_Ew_Gw SANITY when 188 => NEXT_OUTS <= 575; -- bsfw_Gw_Ew SANITY when 189 => NEXT_OUTS <= 1341; -- bsrw_Gw_Ew SANITY when 190 => NEXT_OUTS <= 1577; -- movsbw_Gw_Eb SANITY when 193 => NEXT_OUTS <= 1568; -- xaddw_Ew_Gw SANITY when 194 => case OP4 is when 0 => case OP5 is when 0 => NEXT_OUTS <= 550; -- cmppd_Vpd_Wpd_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 196 => case OP4 is when 0 => NEXT_OUTS <= 1470; -- pinsrw_Vdq_Ew_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 197 => NEXT_OUTS <= 1585; -- pextrw_Gd_Udq_Ib SANITY when 198 => NEXT_OUTS <= 79; -- shufpd_Vpd_Wpd_Ib SANITY when 199 => case OP4 is when 48 => NEXT_OUTS <= 647; -- vmclear_Mq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 208 => NEXT_OUTS <= 510; -- addsubpd_Vpd_Wpd SANITY when 209 => NEXT_OUTS <= 633; -- psrlw_Vdq_Wdq SANITY when 210 => NEXT_OUTS <= 567; -- psrld_Vdq_Wdq SANITY when 211 => NEXT_OUTS <= 666; -- psrlq_Vdq_Wdq SANITY when 212 => NEXT_OUTS <= 627; -- paddq_Vdq_Wdq SANITY when 213 => NEXT_OUTS <= 136; -- pmullw_Vdq_Wdq SANITY when 214 => NEXT_OUTS <= 532; -- movq_Wq_Vq SANITY when 215 => NEXT_OUTS <= 559; -- pmovmskb_Gd_Udq SANITY when 216 => NEXT_OUTS <= 1422; -- psubusb_Vdq_Wdq SANITY when 217 => NEXT_OUTS <= 724; -- psubusw_Vdq_Wdq SANITY when 218 => NEXT_OUTS <= 1370; -- pminub_Vdq_Wdq SANITY when 219 => NEXT_OUTS <= 110; -- pand_Vdq_Wdq SANITY when 220 => NEXT_OUTS <= 385; -- paddusb_Vdq_Wdq SANITY when 221 => NEXT_OUTS <= 967; -- paddusw_Vdq_Wdq SANITY when 222 => NEXT_OUTS <= 964; -- pmaxub_Vdq_Wdq SANITY when 223 => NEXT_OUTS <= 50; -- pandn_Vdq_Wdq SANITY when 224 => NEXT_OUTS <= 786; -- pavgb_Vdq_Wdq SANITY when 225 => NEXT_OUTS <= 1310; -- psraw_Vdq_Wdq SANITY when 226 => NEXT_OUTS <= 1580; -- psrad_Vdq_Wdq SANITY when 227 => NEXT_OUTS <= 216; -- pavgw_Vdq_Wdq SANITY when 228 => NEXT_OUTS <= 790; -- pmulhuw_Vdq_Wdq SANITY when 229 => NEXT_OUTS <= 26; -- pmulhw_Vdq_Wdq SANITY when 230 => NEXT_OUTS <= 101; -- cvttpd2dq_Vq_Wpd SANITY when 231 => NEXT_OUTS <= 1519; -- movntdq_Mdq_Vdq SANITY when 232 => NEXT_OUTS <= 117; -- psubsb_Vdq_Wdq SANITY when 233 => NEXT_OUTS <= 1279; -- psubsw_Vdq_Wdq SANITY when 234 => NEXT_OUTS <= 941; -- pminsw_Vdq_Wdq SANITY when 235 => NEXT_OUTS <= 573; -- por_Vdq_Wdq SANITY when 236 => NEXT_OUTS <= 880; -- paddsb_Vdq_Wdq SANITY when 237 => NEXT_OUTS <= 1569; -- paddsw_Vdq_Wdq SANITY when 238 => NEXT_OUTS <= 1038; -- pmaxsw_Vdq_Wdq SANITY when 239 => NEXT_OUTS <= 1313; -- pxor_Vdq_Wdq SANITY when 241 => NEXT_OUTS <= 270; -- psllw_Vdq_Wdq SANITY when 242 => NEXT_OUTS <= 190; -- pslld_Vdq_Wdq SANITY when 243 => NEXT_OUTS <= 910; -- psllq_Vdq_Wdq SANITY when 244 => NEXT_OUTS <= 673; -- pmuludq_Vdq_Wdq SANITY when 245 => NEXT_OUTS <= 145; -- pmaddwd_Vdq_Wdq SANITY when 246 => NEXT_OUTS <= 1254; -- psadbw_Vdq_Wdq SANITY when 247 => NEXT_OUTS <= 1175; -- maskmovdqu_Vdq_Udq SANITY when 248 => NEXT_OUTS <= 199; -- psubb_Vdq_Wdq SANITY when 249 => NEXT_OUTS <= 1469; -- psubw_Vdq_Wdq SANITY when 250 => NEXT_OUTS <= 481; -- psubd_Vdq_Wdq SANITY when 251 => NEXT_OUTS <= 682; -- psubq_Vdq_Wdq SANITY when 252 => NEXT_OUTS <= 1393; -- paddb_Vdq_Wdq SANITY when 253 => NEXT_OUTS <= 1007; -- paddw_Vdq_Wdq SANITY when 254 => NEXT_OUTS <= 505; -- paddd_Vdq_Wdq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 17 => NEXT_OUTS <= 1556; -- adcw_Ew_Gw SANITY when 19 => NEXT_OUTS <= 741; -- adcw_Gw_Ew SANITY when 21 => NEXT_OUTS <= 896; -- adcw_AX_Iw SANITY when 22 => NEXT_OUTS <= 876; -- pushw_SS SANITY when 23 => NEXT_OUTS <= 1214; -- popw_SS SANITY when 25 => NEXT_OUTS <= 1330; -- sbbw_Ew_Gw SANITY when 27 => NEXT_OUTS <= 1014; -- sbbw_Gw_Ew SANITY when 29 => NEXT_OUTS <= 92; -- sbbw_AX_Iw SANITY when 30 => NEXT_OUTS <= 1352; -- pushw_DS SANITY when 31 => NEXT_OUTS <= 760; -- popw_DS SANITY when 33 => NEXT_OUTS <= 1650; -- andw_Ew_Gw SANITY when 35 => NEXT_OUTS <= 375; -- andw_Gw_Ew SANITY when 37 => NEXT_OUTS <= 1055; -- andw_AX_Iw SANITY when 41 => NEXT_OUTS <= 781; -- subw_Ew_Gw SANITY when 43 => NEXT_OUTS <= 225; -- subw_Gw_Ew SANITY when 45 => NEXT_OUTS <= 556; -- subw_AX_Iw SANITY when 49 => NEXT_OUTS <= 518; -- xorw_Ew_Gw SANITY when 51 => NEXT_OUTS <= 845; -- xorw_Gw_Ew SANITY when 53 => NEXT_OUTS <= 1265; -- xorw_AX_Iw SANITY when 57 => NEXT_OUTS <= 1539; -- cmpw_Ew_Gw SANITY when 59 => NEXT_OUTS <= 1487; -- cmpw_Gw_Ew SANITY when 61 => NEXT_OUTS <= 303; -- cmpw_AX_Iw SANITY when 64 => NEXT_OUTS <= 1278; -- incw_RX SANITY when 72 => case OP3 is when 15 => case OP4 is when 58 => case OP5 is when 22 => NEXT_OUTS <= 680; -- pextrq_Eq_Vdq_Ib SANITY when 34 => NEXT_OUTS <= 475; -- pinsrq_Vdq_Eq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 110 => NEXT_OUTS <= 751; -- movq_Vdq_Eq SANITY when 126 => case OP5 is when 0 => NEXT_OUTS <= 382; -- movq_Eq_Vq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 80 => NEXT_OUTS <= 138; -- pushw_RX SANITY when 88 => NEXT_OUTS <= 1654; -- popw_RX SANITY when 96 => NEXT_OUTS <= 1441; -- pushaw SANITY when 97 => NEXT_OUTS <= 336; -- popaw SANITY when 98 => NEXT_OUTS <= 1252; -- boundw_Gw_Ma SANITY when 104 => NEXT_OUTS <= 1172; -- pushw_Iw SANITY when 105 => NEXT_OUTS <= 770; -- imulw_Gw_Ew_Iw SANITY when 106 => NEXT_OUTS <= 1050; -- pushw_sIb SANITY when 107 => NEXT_OUTS <= 440; -- imulw_Gw_Ew_sIb SANITY when 109 => NEXT_OUTS <= 338; -- insw_Yw_DX SANITY when 111 => NEXT_OUTS <= 745; -- outsw_DX_Xw SANITY when 129 => case OP3 is when 0 => NEXT_OUTS <= 203; -- addw_Ew_Iw SANITY when 8 => NEXT_OUTS <= 1618; -- orw_Ew_Iw SANITY when 16 => NEXT_OUTS <= 1025; -- adcw_Ew_Iw SANITY when 24 => NEXT_OUTS <= 48; -- sbbw_Ew_Iw SANITY when 32 => NEXT_OUTS <= 371; -- andw_Ew_Iw SANITY when 40 => NEXT_OUTS <= 422; -- subw_Ew_Iw SANITY when 48 => NEXT_OUTS <= 1395; -- xorw_Ew_Iw SANITY when 56 => NEXT_OUTS <= 215; -- cmpw_Ew_Iw SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 131 => case OP3 is when 0 => NEXT_OUTS <= 1477; -- addw_Ew_sIb SANITY when 8 => NEXT_OUTS <= 1244; -- orw_Ew_sIb SANITY when 16 => NEXT_OUTS <= 1021; -- adcw_Ew_sIb SANITY when 24 => NEXT_OUTS <= 1083; -- sbbw_Ew_sIb SANITY when 32 => NEXT_OUTS <= 450; -- andw_Ew_sIb SANITY when 40 => NEXT_OUTS <= 1277; -- subw_Ew_sIb SANITY when 48 => NEXT_OUTS <= 672; -- xorw_Ew_sIb SANITY when 56 => NEXT_OUTS <= 1479; -- cmpw_Ew_sIb SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 133 => NEXT_OUTS <= 1184; -- testw_Ew_Gw SANITY when 135 => NEXT_OUTS <= 1030; -- xchgw_Ew_Gw SANITY when 137 => NEXT_OUTS <= 1299; -- movw_Ew_Gw SANITY when 139 => NEXT_OUTS <= 1537; -- movw_Gw_Ew SANITY when 141 => NEXT_OUTS <= 1561; -- leaw_Gw_Mw SANITY when 143 => case OP3 is when 0 => NEXT_OUTS <= 312; -- popw_Ew SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 145 => NEXT_OUTS <= 1468; -- xchgw_RX_AX SANITY when 152 => NEXT_OUTS <= 71; -- cbw SANITY when 153 => NEXT_OUTS <= 1204; -- cwd SANITY when 154 => NEXT_OUTS <= 1107; -- lcall_Apw SANITY when 156 => NEXT_OUTS <= 172; -- pushfw SANITY when 157 => NEXT_OUTS <= 129; -- popfw SANITY when 161 => NEXT_OUTS <= 1649; -- movw_AX_Ow SANITY when 163 => NEXT_OUTS <= 1495; -- movw_Ow_AX SANITY when 165 => NEXT_OUTS <= 1346; -- movsw_Yw_Xw SANITY when 167 => NEXT_OUTS <= 1661; -- cmpsw_Yw_Xw SANITY when 169 => NEXT_OUTS <= 359; -- testw_AX_Iw SANITY when 171 => NEXT_OUTS <= 294; -- stosw_Yw_AX SANITY when 173 => NEXT_OUTS <= 1451; -- lodsw_AX_Xw SANITY when 175 => NEXT_OUTS <= 114; -- scasw_Yw_AX SANITY when 184 => NEXT_OUTS <= 868; -- movw_RX_Iw SANITY when 193 => case OP3 is when 0 => NEXT_OUTS <= 208; -- rolw_Ew_Ib SANITY when 8 => NEXT_OUTS <= 1590; -- rorw_Ew_Ib SANITY when 16 => NEXT_OUTS <= 361; -- rclw_Ew_Ib SANITY when 24 => NEXT_OUTS <= 1121; -- rcrw_Ew_Ib SANITY when 32 => NEXT_OUTS <= 689; -- shlw_Ew_Ib SANITY when 40 => NEXT_OUTS <= 1489; -- shrw_Ew_Ib SANITY when 56 => NEXT_OUTS <= 636; -- sarw_Ew_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 196 => NEXT_OUTS <= 728; -- lesw_Gw_Mp SANITY when 197 => NEXT_OUTS <= 1249; -- ldsw_Gw_Mp SANITY when 199 => case OP3 is when 0 => NEXT_OUTS <= 915; -- movw_Ew_Iw SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 207 => NEXT_OUTS <= 1619; -- iretw SANITY when 209 => case OP3 is when 0 => NEXT_OUTS <= 1188; -- rolw_Ew_I1 SANITY when 8 => NEXT_OUTS <= 1406; -- rorw_Ew_I1 SANITY when 16 => NEXT_OUTS <= 890; -- rclw_Ew_I1 SANITY when 24 => NEXT_OUTS <= 1529; -- rcrw_Ew_I1 SANITY when 32 => NEXT_OUTS <= 1464; -- shlw_Ew_I1 SANITY when 40 => NEXT_OUTS <= 648; -- shrw_Ew_I1 SANITY when 56 => NEXT_OUTS <= 2; -- sarw_Ew_I1 SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 211 => case OP3 is when 0 => NEXT_OUTS <= 1390; -- rolw_Ew_CL SANITY when 8 => NEXT_OUTS <= 857; -- rorw_Ew_CL SANITY when 16 => NEXT_OUTS <= 1163; -- rclw_Ew_CL SANITY when 24 => NEXT_OUTS <= 471; -- rcrw_Ew_CL SANITY when 32 => NEXT_OUTS <= 323; -- shlw_Ew_CL SANITY when 40 => NEXT_OUTS <= 865; -- shrw_Ew_CL SANITY when 56 => NEXT_OUTS <= 514; -- sarw_Ew_CL SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 229 => NEXT_OUTS <= 927; -- inw_AX_Ib SANITY when 231 => NEXT_OUTS <= 148; -- outw_Ib_AX SANITY when 232 => NEXT_OUTS <= 1467; -- call_Jw SANITY when 233 => NEXT_OUTS <= 1053; -- jmp_Jw SANITY when 234 => NEXT_OUTS <= 1633; -- ljmp_Apw SANITY when 237 => NEXT_OUTS <= 920; -- inw_AX_DX SANITY when 239 => NEXT_OUTS <= 1626; -- outw_DX_AX SANITY when 242 => case OP3 is when 15 => case OP4 is when 56 => case OP5 is when 241 => case OP6 is when 195 => NEXT_OUTS <= 1146; -- crc32_Gd_Ew SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 243 => case OP3 is when 15 => case OP4 is when 184 => NEXT_OUTS <= 95; -- popcnt_Gw_Ew SANITY when 188 => NEXT_OUTS <= 536; -- tzcntw_Gw_Ew SANITY when 189 => NEXT_OUTS <= 140; -- lzcntw_Gw_Ew SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 247 => case OP3 is when 0 => NEXT_OUTS <= 1427; -- testw_Ew_Iw SANITY when 16 => NEXT_OUTS <= 380; -- notw_Ew SANITY when 24 => NEXT_OUTS <= 1230; -- negw_Ew SANITY when 32 => NEXT_OUTS <= 1033; -- mulw_AX_Ew SANITY when 40 => NEXT_OUTS <= 1043; -- imulw_AX_Ew SANITY when 48 => NEXT_OUTS <= 814; -- divw_AX_Ew SANITY when 56 => NEXT_OUTS <= 1173; -- idivw_AX_Ew SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 255 => case OP3 is when 0 => NEXT_OUTS <= 1282; -- incw_Ew SANITY when 8 => NEXT_OUTS <= 462; -- decw_Ew SANITY when 16 => NEXT_OUTS <= 1609; -- call_Ew SANITY when 32 => NEXT_OUTS <= 1300; -- jmp_Ew SANITY when 48 => NEXT_OUTS <= 1490; -- pushw_Ew SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 103 => case OP2 is when 227 => NEXT_OUTS <= 465; -- jcxz_Jb SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 104 => case OP2 is when 0 => NEXT_OUTS <= 591; -- pushl_Id SANITY when 1 => NEXT_OUTS <= 1658; -- pushq_sId SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 105 => NEXT_OUTS <= 438; -- imull_Gd_Ed_Id SANITY when 106 => case OP2 is when 0 => NEXT_OUTS <= 392; -- pushl_sIb SANITY when 1 => NEXT_OUTS <= 314; -- pushq_sIb SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 107 => NEXT_OUTS <= 579; -- imull_Gd_Ed_sIb SANITY when 108 => NEXT_OUTS <= 1177; -- insb_Yb_DX SANITY when 109 => NEXT_OUTS <= 709; -- insl_Yd_DX SANITY when 110 => NEXT_OUTS <= 1225; -- outsb_DX_Xb SANITY when 111 => NEXT_OUTS <= 461; -- outsl_DX_Xd SANITY when 112 => NEXT_OUTS <= 921; -- jo_Jb SANITY when 113 => NEXT_OUTS <= 229; -- jno_Jb SANITY when 114 => NEXT_OUTS <= 82; -- jb_Jb SANITY when 115 => NEXT_OUTS <= 241; -- jnb_Jb SANITY when 116 => NEXT_OUTS <= 1506; -- jz_Jb SANITY when 117 => NEXT_OUTS <= 621; -- jnz_Jb SANITY when 118 => NEXT_OUTS <= 1143; -- jbe_Jb SANITY when 119 => NEXT_OUTS <= 642; -- jnbe_Jb SANITY when 120 => NEXT_OUTS <= 787; -- js_Jb SANITY when 121 => NEXT_OUTS <= 668; -- jns_Jb SANITY when 122 => NEXT_OUTS <= 108; -- jp_Jb SANITY when 123 => NEXT_OUTS <= 1104; -- jnp_Jb SANITY when 124 => NEXT_OUTS <= 1336; -- jl_Jb SANITY when 125 => NEXT_OUTS <= 875; -- jnl_Jb SANITY when 126 => NEXT_OUTS <= 976; -- jle_Jb SANITY when 127 => NEXT_OUTS <= 1149; -- jnle_Jb SANITY when 128 => case OP2 is when 0 => NEXT_OUTS <= 237; -- addb_Eb_Ib SANITY when 8 => NEXT_OUTS <= 1665; -- orb_Eb_Ib SANITY when 16 => NEXT_OUTS <= 652; -- adcb_Eb_Ib SANITY when 24 => NEXT_OUTS <= 32; -- sbbb_Eb_Ib SANITY when 32 => NEXT_OUTS <= 654; -- andb_Eb_Ib SANITY when 40 => NEXT_OUTS <= 1135; -- subb_Eb_Ib SANITY when 48 => NEXT_OUTS <= 917; -- xorb_Eb_Ib SANITY when 56 => NEXT_OUTS <= 1315; -- cmpb_Eb_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 129 => case OP2 is when 0 => NEXT_OUTS <= 825; -- addl_Ed_Id SANITY when 8 => NEXT_OUTS <= 1656; -- orl_Ed_Id SANITY when 16 => NEXT_OUTS <= 644; -- adcl_Ed_Id SANITY when 24 => NEXT_OUTS <= 164; -- sbbl_Ed_Id SANITY when 32 => NEXT_OUTS <= 1316; -- andl_Ed_Id SANITY when 40 => NEXT_OUTS <= 634; -- subl_Ed_Id SANITY when 48 => NEXT_OUTS <= 107; -- xorl_Ed_Id SANITY when 56 => NEXT_OUTS <= 421; -- cmpl_Ed_Id SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 131 => case OP2 is when 0 => NEXT_OUTS <= 1552; -- addl_Ed_sIb SANITY when 8 => NEXT_OUTS <= 1363; -- orl_Ed_sIb SANITY when 16 => NEXT_OUTS <= 1062; -- adcl_Ed_sIb SANITY when 24 => NEXT_OUTS <= 193; -- sbbl_Ed_sIb SANITY when 32 => NEXT_OUTS <= 521; -- andl_Ed_sIb SANITY when 40 => NEXT_OUTS <= 544; -- subl_Ed_sIb SANITY when 48 => NEXT_OUTS <= 85; -- xorl_Ed_sIb SANITY when 56 => NEXT_OUTS <= 1096; -- cmpl_Ed_sIb SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 132 => NEXT_OUTS <= 686; -- testb_Eb_Gb SANITY when 133 => NEXT_OUTS <= 23; -- testl_Ed_Gd SANITY when 134 => NEXT_OUTS <= 500; -- xchgb_Eb_Gb SANITY when 135 => NEXT_OUTS <= 1501; -- xchgl_Ed_Gd SANITY when 136 => NEXT_OUTS <= 373; -- movb_Eb_Gb SANITY when 137 => NEXT_OUTS <= 1092; -- movl_Ed_Gd SANITY when 138 => NEXT_OUTS <= 213; -- movb_Gb_Eb SANITY when 139 => NEXT_OUTS <= 160; -- movl_Gd_Ed SANITY when 140 => NEXT_OUTS <= 1113; -- movw_Ew_Sw SANITY when 141 => NEXT_OUTS <= 53; -- leal_Gd_Md SANITY when 142 => NEXT_OUTS <= 159; -- movw_Sw_Ew SANITY when 143 => case OP2 is when 0 => case OP3 is when 0 => NEXT_OUTS <= 1475; -- popl_Ed SANITY when 1 => NEXT_OUTS <= 351; -- popq_Eq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 144 => NEXT_OUTS <= 607; -- nop SANITY when 145 => NEXT_OUTS <= 608; -- xchgl_ERX_EAX SANITY when 152 => NEXT_OUTS <= 1573; -- cwde SANITY when 153 => NEXT_OUTS <= 1060; -- cdq SANITY when 154 => NEXT_OUTS <= 112; -- lcall_Apd SANITY when 155 => NEXT_OUTS <= 63; -- fwait SANITY when 156 => case OP2 is when 0 => NEXT_OUTS <= 280; -- pushfl SANITY when 1 => NEXT_OUTS <= 1117; -- pushfq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 157 => case OP2 is when 0 => NEXT_OUTS <= 42; -- popfl SANITY when 1 => NEXT_OUTS <= 692; -- popfq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 158 => NEXT_OUTS <= 1625; -- sahf SANITY when 159 => NEXT_OUTS <= 344; -- lahf SANITY when 160 => NEXT_OUTS <= 1301; -- movb_AL_Ob SANITY when 161 => NEXT_OUTS <= 432; -- movl_EAX_Od SANITY when 162 => NEXT_OUTS <= 1181; -- movb_Ob_AL SANITY when 163 => NEXT_OUTS <= 121; -- movl_Od_EAX SANITY when 164 => NEXT_OUTS <= 113; -- movsb_Yb_Xb SANITY when 165 => NEXT_OUTS <= 1196; -- movsl_Yd_Xd SANITY when 166 => NEXT_OUTS <= 260; -- cmpsb_Yb_Xb SANITY when 167 => NEXT_OUTS <= 1493; -- cmpsl_Yd_Xd SANITY when 168 => NEXT_OUTS <= 1250; -- testb_AL_Ib SANITY when 169 => NEXT_OUTS <= 1069; -- testl_EAX_Id SANITY when 170 => NEXT_OUTS <= 695; -- stosb_Yb_AL SANITY when 171 => NEXT_OUTS <= 196; -- stosl_Yd_EAX SANITY when 172 => NEXT_OUTS <= 1513; -- lodsb_AL_Xb SANITY when 173 => NEXT_OUTS <= 1246; -- lodsl_EAX_Xd SANITY when 174 => NEXT_OUTS <= 374; -- scasb_Yb_AL SANITY when 175 => NEXT_OUTS <= 1421; -- scasl_Yd_EAX SANITY when 176 => NEXT_OUTS <= 130; -- movb_R8_Ib SANITY when 184 => NEXT_OUTS <= 576; -- movl_ERX_Id SANITY when 192 => case OP2 is when 0 => NEXT_OUTS <= 702; -- rolb_Eb_Ib SANITY when 8 => NEXT_OUTS <= 639; -- rorb_Eb_Ib SANITY when 16 => NEXT_OUTS <= 1039; -- rclb_Eb_Ib SANITY when 24 => NEXT_OUTS <= 1000; -- rcrb_Eb_Ib SANITY when 32 => NEXT_OUTS <= 43; -- shlb_Eb_Ib SANITY when 40 => NEXT_OUTS <= 729; -- shrb_Eb_Ib SANITY when 56 => NEXT_OUTS <= 1076; -- sarb_Eb_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 193 => case OP2 is when 0 => NEXT_OUTS <= 1195; -- roll_Ed_Ib SANITY when 8 => NEXT_OUTS <= 366; -- rorl_Ed_Ib SANITY when 16 => NEXT_OUTS <= 899; -- rcll_Ed_Ib SANITY when 24 => NEXT_OUTS <= 1500; -- rcrl_Ed_Ib SANITY when 32 => NEXT_OUTS <= 369; -- shll_Ed_Ib SANITY when 40 => NEXT_OUTS <= 1540; -- shrl_Ed_Ib SANITY when 56 => NEXT_OUTS <= 547; -- sarl_Ed_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 194 => NEXT_OUTS <= 109; -- ret_Iw SANITY when 195 => NEXT_OUTS <= 198; -- ret SANITY when 196 => case OP2 is when 0 => NEXT_OUTS <= 791; -- lesl_Gd_Mp SANITY when 225 => case OP3 is when 249 => case OP4 is when 110 => NEXT_OUTS <= 987; -- vmovq_Vdq_Eq SANITY when 126 => case OP5 is when 0 => NEXT_OUTS <= 1110; -- vmovq_Eq_Vq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 226 => case OP3 is when 80 => case OP4 is when 242 => NEXT_OUTS <= 67; -- andn_Gy_By_Ey SANITY when 243 => case OP5 is when 8 => NEXT_OUTS <= 1356; -- blsr_By_Ey SANITY when 16 => NEXT_OUTS <= 1082; -- blsmsk_By_Ey SANITY when 24 => NEXT_OUTS <= 715; -- blsi_By_Ey SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 245 => NEXT_OUTS <= 1439; -- bzhi_Gy_Ey_By SANITY when 247 => NEXT_OUTS <= 31; -- bextr_Gy_Ey_By SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 81 => case OP4 is when 0 => NEXT_OUTS <= 3; -- vpshufb_Vdq_Hdq_Wdq SANITY when 1 => NEXT_OUTS <= 552; -- vphaddw_Vdq_Hdq_Wdq SANITY when 2 => NEXT_OUTS <= 13; -- vphaddd_Vdq_Hdq_Wdq SANITY when 3 => NEXT_OUTS <= 613; -- vphaddsw_Vdq_Hdq_Wdq SANITY when 4 => NEXT_OUTS <= 309; -- vpmaddubsw_Vdq_Hdq_Wdq SANITY when 5 => NEXT_OUTS <= 764; -- vphsubw_Vdq_Hdq_Wdq SANITY when 6 => NEXT_OUTS <= 1015; -- vphsubd_Vdq_Hdq_Wdq SANITY when 7 => NEXT_OUTS <= 266; -- vphsubsw_Vdq_Hdq_Wdq SANITY when 8 => NEXT_OUTS <= 774; -- vpsignb_Vdq_Hdq_Wdq SANITY when 9 => NEXT_OUTS <= 1342; -- vpsignw_Vdq_Hdq_Wdq SANITY when 10 => NEXT_OUTS <= 1156; -- vpsignd_Vdq_Hdq_Wdq SANITY when 11 => NEXT_OUTS <= 15; -- vpmulhrsw_Vdq_Hdq_Wdq SANITY when 12 => NEXT_OUTS <= 538; -- vpermilps_Vps_Hps_Wps SANITY when 13 => NEXT_OUTS <= 650; -- vpermilpd_Vpd_Hpd_Wpd SANITY when 22 => NEXT_OUTS <= 1237; -- vpermps_Vps_Hps_Wps SANITY when 40 => NEXT_OUTS <= 419; -- vpmuldq_Vdq_Hdq_Wdq SANITY when 41 => NEXT_OUTS <= 1414; -- vpcmpeqq_Vdq_Hdq_Wdq SANITY when 43 => NEXT_OUTS <= 1472; -- vpackusdw_Vdq_Hdq_Wdq SANITY when 44 => NEXT_OUTS <= 376; -- vmaskmovps_Vps_Hps_Mps SANITY when 45 => NEXT_OUTS <= 704; -- vmaskmovpd_Vpd_Hpd_Mpd SANITY when 46 => NEXT_OUTS <= 706; -- vmaskmovps_Mps_Hps_Vps SANITY when 47 => NEXT_OUTS <= 568; -- vmaskmovpd_Mpd_Hpd_Vpd SANITY when 54 => NEXT_OUTS <= 944; -- vpermd_Vdq_Hdq_Wdq SANITY when 55 => NEXT_OUTS <= 632; -- vpcmpgtq_Vdq_Hdq_Wdq SANITY when 56 => NEXT_OUTS <= 1507; -- vpminsb_Vdq_Hdq_Wdq SANITY when 57 => NEXT_OUTS <= 763; -- vpminsd_Vdq_Hdq_Wdq SANITY when 58 => NEXT_OUTS <= 1209; -- vpminuw_Vdq_Hdq_Wdq SANITY when 59 => NEXT_OUTS <= 545; -- vpminud_Vdq_Hdq_Wdq SANITY when 60 => NEXT_OUTS <= 379; -- vpmaxsb_Vdq_Hdq_Wdq SANITY when 61 => NEXT_OUTS <= 1221; -- vpmaxsd_Vdq_Hdq_Wdq SANITY when 62 => NEXT_OUTS <= 149; -- vpmaxuw_Vdq_Hdq_Wdq SANITY when 63 => NEXT_OUTS <= 1176; -- vpmaxud_Vdq_Hdq_Wdq SANITY when 64 => NEXT_OUTS <= 274; -- vpmulld_Vdq_Hdq_Wdq SANITY when 69 => NEXT_OUTS <= 861; -- vpsrlvd_Vdq_Hdq_Wdq SANITY when 70 => NEXT_OUTS <= 176; -- vpsravd_Vdq_Hdq_Wdq SANITY when 71 => NEXT_OUTS <= 1486; -- vpsllvd_Vdq_Hdq_Wdq SANITY when 140 => NEXT_OUTS <= 713; -- vmaskmovd_Vdq_Hdq_Mdq SANITY when 142 => NEXT_OUTS <= 1517; -- vmaskmovq_Mdq_Hdq_Vdq SANITY when 144 => NEXT_OUTS <= 1647; -- vgatherdd_Vdq_VSib_Hdq SANITY when 145 => NEXT_OUTS <= 1212; -- vgatherqd_Vdq_VSib_Hdq SANITY when 146 => NEXT_OUTS <= 1283; -- vgatherdps_Vps_VSib_Hps SANITY when 147 => NEXT_OUTS <= 1168; -- vgatherqps_Vps_VSib_Hps SANITY when 150 => NEXT_OUTS <= 222; -- vfmaddsub132ps_Vps_Hps_Wps SANITY when 151 => NEXT_OUTS <= 830; -- vfmsubadd132ps_Vps_Hps_Wps SANITY when 152 => NEXT_OUTS <= 954; -- vfmadd132ps_Vps_Hps_Wps SANITY when 153 => NEXT_OUTS <= 924; -- vfmadd132ss_Vps_Hss_Wss SANITY when 154 => NEXT_OUTS <= 1516; -- vfmsub132ps_Vps_Hps_Wps SANITY when 155 => NEXT_OUTS <= 795; -- vfmsub132ss_Vps_Hss_Wss SANITY when 156 => NEXT_OUTS <= 1455; -- vfnmadd132ps_Vps_Hps_Wps SANITY when 157 => NEXT_OUTS <= 1084; -- vfnmadd132ss_Vps_Hss_Wss SANITY when 158 => NEXT_OUTS <= 1351; -- vfnmsub132ps_Vps_Hps_Wps SANITY when 159 => NEXT_OUTS <= 1635; -- vfnmsub132ss_Vps_Hss_Wss SANITY when 166 => NEXT_OUTS <= 853; -- vfmaddsub213ps_Vps_Hps_Wps SANITY when 167 => NEXT_OUTS <= 779; -- vfmsubadd213ps_Vps_Hps_Wps SANITY when 168 => NEXT_OUTS <= 963; -- vfmadd213ps_Vps_Hps_Wps SANITY when 169 => NEXT_OUTS <= 643; -- vfmadd213ss_Vps_Hss_Wss SANITY when 170 => NEXT_OUTS <= 842; -- vfmsub213ps_Vps_Hps_Wps SANITY when 171 => NEXT_OUTS <= 761; -- vfmsub213ss_Vps_Hss_Wss SANITY when 172 => NEXT_OUTS <= 1600; -- vfnmadd213ps_Vps_Hps_Wps SANITY when 173 => NEXT_OUTS <= 846; -- vfnmadd213ss_Vps_Hss_Wss SANITY when 174 => NEXT_OUTS <= 116; -- vfnmsub213ps_Vps_Hps_Wps SANITY when 175 => NEXT_OUTS <= 977; -- vfnmsub213ss_Vps_Hss_Wss SANITY when 182 => NEXT_OUTS <= 204; -- vfmaddsub231ps_Vps_Hps_Wps SANITY when 183 => NEXT_OUTS <= 1629; -- vfmsubadd231ps_Vps_Hps_Wps SANITY when 184 => NEXT_OUTS <= 298; -- vfmadd231ps_Vps_Hps_Wps SANITY when 185 => NEXT_OUTS <= 945; -- vfmadd231ss_Vps_Hss_Wss SANITY when 186 => NEXT_OUTS <= 844; -- vfmsub231ps_Vps_Hps_Wps SANITY when 187 => NEXT_OUTS <= 782; -- vfmsub231ss_Vps_Hss_Wss SANITY when 188 => NEXT_OUTS <= 619; -- vfnmadd231ps_Vps_Hps_Wps SANITY when 189 => NEXT_OUTS <= 1340; -- vfnmadd231ss_Vps_Hss_Wss SANITY when 190 => NEXT_OUTS <= 562; -- vfnmsub231ps_Vps_Hps_Wps SANITY when 191 => NEXT_OUTS <= 720; -- vfnmsub231ss_Vps_Hss_Wss SANITY when 219 => NEXT_OUTS <= 302; -- vaesimc_Vdq_Wdq SANITY when 220 => NEXT_OUTS <= 477; -- vaesenc_Vdq_Hdq_Wdq SANITY when 221 => NEXT_OUTS <= 1167; -- vaesenclast_Vdq_Hdq_Wdq SANITY when 222 => NEXT_OUTS <= 1575; -- vaesdec_Vdq_Hdq_Wdq SANITY when 223 => NEXT_OUTS <= 170; -- vaesdeclast_Vdq_Hdq_Wdq SANITY when 247 => NEXT_OUTS <= 1327; -- shlx_Gy_Ey_By SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 82 => case OP4 is when 245 => NEXT_OUTS <= 1622; -- pext_Gy_By_Ey SANITY when 247 => NEXT_OUTS <= 1217; -- sarx_Gy_Ey_By SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 83 => case OP4 is when 245 => NEXT_OUTS <= 1372; -- pdep_Gy_By_Ey SANITY when 247 => NEXT_OUTS <= 1368; -- shrx_Gy_Ey_By SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 121 => case OP4 is when 14 => NEXT_OUTS <= 802; -- vtestps_Vps_Wps SANITY when 15 => NEXT_OUTS <= 744; -- vtestpd_Vpd_Wpd SANITY when 19 => NEXT_OUTS <= 1481; -- vcvtph2ps_Vps_Wq SANITY when 23 => NEXT_OUTS <= 1201; -- vptest_Vdq_Wdq SANITY when 24 => NEXT_OUTS <= 1565; -- vbroadcastss_Vps_Wss SANITY when 25 => NEXT_OUTS <= 1637; -- vbroadcastsd_Vpd_Wsd SANITY when 26 => NEXT_OUTS <= 44; -- vbroadcastf128_Vdq_Mdq SANITY when 28 => NEXT_OUTS <= 656; -- vpabsb_Vdq_Hdq_Wdq SANITY when 29 => NEXT_OUTS <= 1191; -- vpabsw_Vdq_Hdq_Wdq SANITY when 30 => NEXT_OUTS <= 1350; -- vpabsd_Vdq_Hdq_Wdq SANITY when 32 => case OP5 is when 1 => NEXT_OUTS <= 387; -- vpmovsxbw_Vdq_Wq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 33 => NEXT_OUTS <= 1091; -- vpmovsxbd_Vdq_Wd SANITY when 34 => NEXT_OUTS <= 586; -- vpmovsxbq_Vdq_Ww SANITY when 35 => NEXT_OUTS <= 238; -- vpmovsxwd_Vdq_Wq SANITY when 36 => NEXT_OUTS <= 600; -- vpmovsxwq_Vdq_Wd SANITY when 37 => NEXT_OUTS <= 119; -- vpmovsxdq_Vdq_Wq SANITY when 42 => NEXT_OUTS <= 898; -- vmovntdqa_Vdq_Mdq SANITY when 48 => NEXT_OUTS <= 749; -- vpmovzxbw_Vdq_Wq SANITY when 49 => NEXT_OUTS <= 593; -- vpmovzxbd_Vdq_Wd SANITY when 50 => NEXT_OUTS <= 716; -- vpmovzxbq_Vdq_Ww SANITY when 51 => NEXT_OUTS <= 1322; -- vpmovzxwd_Vdq_Wq SANITY when 52 => NEXT_OUTS <= 882; -- vpmovzxwq_Vdq_Wd SANITY when 53 => NEXT_OUTS <= 247; -- vpmovzxdq_Vdq_Wq SANITY when 65 => NEXT_OUTS <= 34; -- vphminposuw_Vdq_Wdq SANITY when 88 => NEXT_OUTS <= 1318; -- vpbroadcastd_Vdq_Wd SANITY when 89 => NEXT_OUTS <= 723; -- vpbroadcastq_Vdq_Wq SANITY when 90 => NEXT_OUTS <= 1377; -- vbroadcasti128_Vdq_Mdq SANITY when 120 => NEXT_OUTS <= 670; -- vpbroadcastb_Vdq_Wb SANITY when 121 => NEXT_OUTS <= 1420; -- vpbroadcastw_Vdq_Ww SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 209 => case OP4 is when 69 => NEXT_OUTS <= 454; -- vpsrlvq_Vdq_Hdq_Wdq SANITY when 71 => NEXT_OUTS <= 1155; -- vpsllvq_Vdq_Hdq_Wdq SANITY when 140 => NEXT_OUTS <= 173; -- vmaskmovq_Vdq_Hdq_Mdq SANITY when 144 => NEXT_OUTS <= 577; -- vgatherdq_Vdq_VSib_Hdq SANITY when 145 => NEXT_OUTS <= 1158; -- vgatherqq_Vdq_VSib_Hdq SANITY when 146 => NEXT_OUTS <= 411; -- vgatherdpd_Vpd_VSib_Hpd SANITY when 147 => NEXT_OUTS <= 1570; -- vgatherqpd_Vpd_VSib_Hpd SANITY when 150 => NEXT_OUTS <= 343; -- vfmaddsub132pd_Vpd_Hpd_Wpd SANITY when 151 => NEXT_OUTS <= 1198; -- vfmsubadd132pd_Vpd_Hpd_Wpd SANITY when 152 => NEXT_OUTS <= 885; -- vfmadd132pd_Vpd_Hpd_Wpd SANITY when 153 => NEXT_OUTS <= 671; -- vfmadd132sd_Vpd_Hsd_Wsd SANITY when 154 => NEXT_OUTS <= 476; -- vfmsub132pd_Vpd_Hpd_Wpd SANITY when 155 => NEXT_OUTS <= 88; -- vfmsub132sd_Vpd_Hsd_Wsd SANITY when 156 => NEXT_OUTS <= 62; -- vfnmadd132pd_Vpd_Hpd_Wpd SANITY when 157 => NEXT_OUTS <= 324; -- vfnmadd132sd_Vpd_Hsd_Wsd SANITY when 158 => NEXT_OUTS <= 244; -- vfnmsub132pd_Vpd_Hpd_Wpd SANITY when 159 => NEXT_OUTS <= 405; -- vfnmsub132sd_Vpd_Hsd_Wsd SANITY when 166 => NEXT_OUTS <= 1429; -- vfmaddsub213pd_Vpd_Hpd_Wpd SANITY when 167 => NEXT_OUTS <= 1154; -- vfmsubadd213pd_Vpd_Hpd_Wpd SANITY when 168 => NEXT_OUTS <= 1591; -- vfmadd213pd_Vpd_Hpd_Wpd SANITY when 169 => NEXT_OUTS <= 425; -- vfmadd213sd_Vpd_Hsd_Wsd SANITY when 170 => NEXT_OUTS <= 1458; -- vfmsub213pd_Vpd_Hpd_Wpd SANITY when 171 => NEXT_OUTS <= 972; -- vfmsub213sd_Vpd_Hsd_Wsd SANITY when 172 => NEXT_OUTS <= 1369; -- vfnmadd213pd_Vpd_Hpd_Wpd SANITY when 173 => NEXT_OUTS <= 601; -- vfnmadd213sd_Vpd_Hsd_Wsd SANITY when 174 => NEXT_OUTS <= 1596; -- vfnmsub213pd_Vpd_Hpd_Wpd SANITY when 175 => NEXT_OUTS <= 1197; -- vfnmsub213sd_Vpd_Hsd_Wsd SANITY when 182 => NEXT_OUTS <= 1041; -- vfmaddsub231pd_Vpd_Hpd_Wpd SANITY when 183 => NEXT_OUTS <= 660; -- vfmsubadd231pd_Vpd_Hpd_Wpd SANITY when 184 => NEXT_OUTS <= 495; -- vfmadd231pd_Vpd_Hpd_Wpd SANITY when 185 => NEXT_OUTS <= 1607; -- vfmadd231sd_Vpd_Hsd_Wsd SANITY when 186 => NEXT_OUTS <= 111; -- vfmsub231pd_Vpd_Hpd_Wpd SANITY when 187 => NEXT_OUTS <= 1261; -- vfmsub231sd_Vpd_Hsd_Wsd SANITY when 188 => NEXT_OUTS <= 1120; -- vfnmadd231pd_Vpd_Hpd_Wpd SANITY when 189 => NEXT_OUTS <= 1157; -- vfnmadd231sd_Vpd_Hsd_Wsd SANITY when 190 => NEXT_OUTS <= 1646; -- vfnmsub231pd_Vpd_Hpd_Wpd SANITY when 191 => NEXT_OUTS <= 1171; -- vfnmsub231sd_Vpd_Hsd_Wsd SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 227 => case OP3 is when 81 => case OP4 is when 2 => NEXT_OUTS <= 1269; -- vpblendd_Vdq_Hdq_Wdq_Ib SANITY when 6 => NEXT_OUTS <= 158; -- vperm2f128_Vdq_Hdq_Wdq_Ib SANITY when 10 => NEXT_OUTS <= 773; -- vroundss_Vss_Hps_Wss_Ib SANITY when 11 => NEXT_OUTS <= 932; -- vroundsd_Vsd_Hpd_Wsd_Ib SANITY when 12 => NEXT_OUTS <= 953; -- vblendps_Vps_Hps_Wps_Ib SANITY when 13 => NEXT_OUTS <= 1152; -- vblendpd_Vpd_Hpd_Wpd_Ib SANITY when 14 => NEXT_OUTS <= 54; -- vpblendw_Vdq_Hdq_Wdq_Ib SANITY when 15 => NEXT_OUTS <= 33; -- vpalignr_Vdq_Hdq_Wdq_Ib SANITY when 24 => NEXT_OUTS <= 426; -- vinsertf128_Vdq_Hdq_Wdq_Ib SANITY when 32 => NEXT_OUTS <= 1419; -- vpinsrb_Vdq_Hdq_Ed_Ib SANITY when 33 => NEXT_OUTS <= 1332; -- vinsertps_Vps_Hps_Wss_Ib SANITY when 34 => NEXT_OUTS <= 640; -- vpinsrd_Vdq_Hdq_Ed_Ib SANITY when 56 => NEXT_OUTS <= 1401; -- vinserti128_Vdq_Hdq_Wdq_Ib SANITY when 64 => NEXT_OUTS <= 436; -- vdpps_Vps_Hps_Wps_Ib SANITY when 65 => NEXT_OUTS <= 940; -- vdppd_Vpd_Hpd_Wpd_Ib SANITY when 66 => NEXT_OUTS <= 1093; -- vmpsadbw_Vdq_Hdq_Wdq_Ib SANITY when 68 => NEXT_OUTS <= 965; -- vpclmulqdq_Vdq_Hdq_Wdq_Ib SANITY when 70 => NEXT_OUTS <= 519; -- vperm2i128_Vdq_Hdq_Wdq_Ib SANITY when 74 => NEXT_OUTS <= 1063; -- vblendvps_Vps_Hps_Wps_Ib SANITY when 75 => NEXT_OUTS <= 277; -- vblendvpd_Vpd_Hpd_Wpd_Ib SANITY when 76 => NEXT_OUTS <= 960; -- vpblendvb_Vdq_Hdq_Wdq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 120 => case OP4 is when 240 => NEXT_OUTS <= 200; -- rorx_Gy_Ey_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 121 => case OP4 is when 4 => NEXT_OUTS <= 676; -- vpermilps_Vps_Wps_Ib SANITY when 5 => NEXT_OUTS <= 1449; -- vpermilpd_Vpd_Wpd_Ib SANITY when 8 => NEXT_OUTS <= 83; -- vroundps_Vps_Wps_Ib SANITY when 9 => NEXT_OUTS <= 1589; -- vroundpd_Vpd_Wpd_Ib SANITY when 20 => case OP5 is when 0 => NEXT_OUTS <= 1193; -- vpextrb_Ebd_Vdq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 21 => case OP5 is when 0 => NEXT_OUTS <= 529; -- vpextrw_Ewd_Vdq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 22 => NEXT_OUTS <= 603; -- vpextrd_Ed_Vdq_Ib SANITY when 23 => NEXT_OUTS <= 1543; -- vextractps_Ed_Vdq_Ib SANITY when 25 => NEXT_OUTS <= 887; -- vextractf128_Wdq_Vdq_Ib SANITY when 29 => NEXT_OUTS <= 410; -- vcvtps2ph_Wq_Vps_Ib SANITY when 57 => NEXT_OUTS <= 705; -- vextracti128_Wdq_Vdq_Ib SANITY when 96 => NEXT_OUTS <= 768; -- vpcmpestrm_Vdq_Wdq_Ib SANITY when 97 => NEXT_OUTS <= 856; -- vpcmpestri_Vdq_Wdq_Ib SANITY when 98 => NEXT_OUTS <= 1465; -- vpcmpistrm_Vdq_Wdq_Ib SANITY when 99 => NEXT_OUTS <= 1444; -- vpcmpistri_Vdq_Wdq_Ib SANITY when 223 => NEXT_OUTS <= 653; -- vaeskeygenassist_Vdq_Wdq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 209 => case OP4 is when 34 => NEXT_OUTS <= 326; -- vpinsrq_Vdq_Hdq_Eq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 249 => case OP4 is when 0 => NEXT_OUTS <= 959; -- vpermq_Vdq_Wdq_Ib SANITY when 1 => NEXT_OUTS <= 132; -- vpermpd_Vpd_Wpd_Ib SANITY when 22 => NEXT_OUTS <= 135; -- vpextrq_Eq_Vdq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 197 => case OP2 is when 0 => NEXT_OUTS <= 52; -- ldsl_Gd_Mp SANITY when 208 => case OP3 is when 18 => case OP4 is when 0 => NEXT_OUTS <= 1174; -- vmovlps_Vps_Hdq_Mq SANITY when 192 => NEXT_OUTS <= 57; -- vmovhlps_Vps_Hdq_Udq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 20 => NEXT_OUTS <= 824; -- vunpcklps_Vps_Hps_Wps SANITY when 21 => NEXT_OUTS <= 1295; -- vunpckhps_Vps_Hps_Wps SANITY when 22 => case OP4 is when 0 => NEXT_OUTS <= 1130; -- vmovhps_Vps_Hdq_Mq SANITY when 192 => NEXT_OUTS <= 1627; -- vmovlhps_Vps_Hdq_Udq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 84 => NEXT_OUTS <= 864; -- vandps_Vps_Hps_Wps SANITY when 85 => NEXT_OUTS <= 661; -- vandnps_Vps_Hps_Wps SANITY when 86 => NEXT_OUTS <= 926; -- vorps_Vps_Hps_Wps SANITY when 87 => NEXT_OUTS <= 515; -- vxorps_Vps_Hps_Wps SANITY when 88 => NEXT_OUTS <= 1064; -- vaddps_Vps_Hps_Wps SANITY when 89 => NEXT_OUTS <= 829; -- vmulps_Vps_Hps_Wps SANITY when 92 => NEXT_OUTS <= 772; -- vsubps_Vps_Hps_Wps SANITY when 93 => NEXT_OUTS <= 1242; -- vminps_Vps_Hps_Wps SANITY when 94 => NEXT_OUTS <= 618; -- vdivps_Vps_Hps_Wps SANITY when 95 => NEXT_OUTS <= 934; -- vmaxps_Vps_Hps_Wps SANITY when 194 => case OP4 is when 0 => case OP5 is when 0 => NEXT_OUTS <= 1398; -- vcmpps_Vps_Hps_Wps_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 198 => NEXT_OUTS <= 488; -- vshufps_Vps_Hps_Wps_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 209 => case OP3 is when 18 => NEXT_OUTS <= 1129; -- vmovlpd_Vpd_Hdq_Mq SANITY when 20 => NEXT_OUTS <= 980; -- vunpcklpd_Vpd_Hpd_Wpd SANITY when 21 => NEXT_OUTS <= 70; -- vunpckhpd_Vpd_Hpd_Wpd SANITY when 22 => NEXT_OUTS <= 1199; -- vmovhpd_Vpd_Hdq_Mq SANITY when 84 => NEXT_OUTS <= 185; -- vandpd_Vpd_Hpd_Wpd SANITY when 85 => NEXT_OUTS <= 265; -- vandnpd_Vpd_Hpd_Wpd SANITY when 86 => NEXT_OUTS <= 1248; -- vorpd_Vpd_Hpd_Wpd SANITY when 87 => NEXT_OUTS <= 938; -- vxorpd_Vpd_Hpd_Wpd SANITY when 88 => NEXT_OUTS <= 37; -- vaddpd_Vpd_Hpd_Wpd SANITY when 89 => NEXT_OUTS <= 862; -- vmulpd_Vpd_Hpd_Wpd SANITY when 92 => NEXT_OUTS <= 1426; -- vsubpd_Vpd_Hpd_Wpd SANITY when 93 => NEXT_OUTS <= 127; -- vminpd_Vpd_Hpd_Wpd SANITY when 94 => NEXT_OUTS <= 707; -- vdivpd_Vpd_Hpd_Wpd SANITY when 95 => NEXT_OUTS <= 733; -- vmaxpd_Vpd_Hpd_Wpd SANITY when 96 => NEXT_OUTS <= 1302; -- vpunpcklbw_Vdq_Hdq_Wdq SANITY when 97 => NEXT_OUTS <= 583; -- vpunpcklwd_Vdq_Hdq_Wdq SANITY when 98 => NEXT_OUTS <= 282; -- vpunpckldq_Vdq_Hdq_Wdq SANITY when 99 => NEXT_OUTS <= 1320; -- vpacksswb_Vdq_Hdq_Wdq SANITY when 100 => NEXT_OUTS <= 1011; -- vpcmpgtb_Vdq_Hdq_Wdq SANITY when 101 => NEXT_OUTS <= 1374; -- vpcmpgtw_Vdq_Hdq_Wdq SANITY when 102 => NEXT_OUTS <= 1536; -- vpcmpgtd_Vdq_Hdq_Wdq SANITY when 103 => NEXT_OUTS <= 1450; -- vpackuswb_Vdq_Hdq_Wdq SANITY when 104 => NEXT_OUTS <= 606; -- vpunpckhbw_Vdq_Hdq_Wdq SANITY when 105 => NEXT_OUTS <= 286; -- vpunpckhwd_Vdq_Hdq_Wdq SANITY when 106 => NEXT_OUTS <= 137; -- vpunpckhdq_Vdq_Hdq_Wdq SANITY when 107 => NEXT_OUTS <= 1232; -- vpackssdw_Vdq_Hdq_Wdq SANITY when 108 => NEXT_OUTS <= 1112; -- vpunpcklqdq_Vdq_Hdq_Wdq SANITY when 109 => NEXT_OUTS <= 1333; -- vpunpckhqdq_Vdq_Hdq_Wdq SANITY when 113 => case OP4 is when 16 => NEXT_OUTS <= 1462; -- vpsrlw_Hdq_Udq_Ib SANITY when 32 => NEXT_OUTS <= 970; -- vpsraw_Hdq_Udq_Ib SANITY when 48 => NEXT_OUTS <= 480; -- vpsllw_Hdq_Udq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 114 => case OP4 is when 16 => NEXT_OUTS <= 903; -- vpsrld_Hdq_Udq_Ib SANITY when 32 => NEXT_OUTS <= 1008; -- vpsrad_Hdq_Udq_Ib SANITY when 48 => NEXT_OUTS <= 1183; -- vpslld_Hdq_Udq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 115 => case OP4 is when 16 => NEXT_OUTS <= 894; -- vpsrlq_Hdq_Udq_Ib SANITY when 24 => NEXT_OUTS <= 201; -- vpsrldq_Hdq_Udq_Ib SANITY when 48 => NEXT_OUTS <= 398; -- vpsllq_Hdq_Udq_Ib SANITY when 56 => NEXT_OUTS <= 599; -- vpslldq_Hdq_Udq_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 116 => NEXT_OUTS <= 732; -- vpcmpeqb_Vdq_Hdq_Wdq SANITY when 117 => NEXT_OUTS <= 1488; -- vpcmpeqw_Vdq_Hdq_Wdq SANITY when 118 => NEXT_OUTS <= 703; -- vpcmpeqd_Vdq_Hdq_Wdq SANITY when 124 => NEXT_OUTS <= 1366; -- vhaddpd_Vpd_Hpd_Wpd SANITY when 125 => NEXT_OUTS <= 966; -- vhsubpd_Vpd_Hpd_Wpd SANITY when 194 => case OP4 is when 0 => case OP5 is when 0 => NEXT_OUTS <= 996; -- vcmppd_Vpd_Hpd_Wpd_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 196 => case OP4 is when 0 => NEXT_OUTS <= 212; -- vpinsrw_Vdq_Hdq_Ew_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 198 => NEXT_OUTS <= 254; -- vshufpd_Vpd_Hpd_Wpd_Ib SANITY when 208 => NEXT_OUTS <= 1457; -- vaddsubpd_Vpd_Hpd_Wpd SANITY when 209 => NEXT_OUTS <= 1131; -- vpsrlw_Vdq_Hdq_Wdq SANITY when 210 => NEXT_OUTS <= 1287; -- vpsrld_Vdq_Hdq_Wdq SANITY when 211 => NEXT_OUTS <= 1353; -- vpsrlq_Vdq_Hdq_Wdq SANITY when 212 => NEXT_OUTS <= 1233; -- vpaddq_Vdq_Hdq_Wdq SANITY when 213 => NEXT_OUTS <= 1119; -- vpmullw_Vdq_Hdq_Wdq SANITY when 216 => NEXT_OUTS <= 669; -- vpsubusb_Vdq_Hdq_Wdq SANITY when 217 => NEXT_OUTS <= 94; -- vpsubusw_Vdq_Hdq_Wdq SANITY when 218 => NEXT_OUTS <= 64; -- vpminub_Vdq_Hdq_Wdq SANITY when 219 => NEXT_OUTS <= 1329; -- vpand_Vdq_Hdq_Wdq SANITY when 220 => NEXT_OUTS <= 1411; -- vpaddusb_Vdq_Hdq_Wdq SANITY when 221 => NEXT_OUTS <= 469; -- vpaddusw_Vdq_Hdq_Wdq SANITY when 222 => NEXT_OUTS <= 1476; -- vpmaxub_Vdq_Hdq_Wdq SANITY when 223 => NEXT_OUTS <= 1180; -- vpandn_Vdq_Hdq_Wdq SANITY when 224 => NEXT_OUTS <= 1010; -- vpavgb_Vdq_Hdq_Wdq SANITY when 225 => NEXT_OUTS <= 743; -- vpsraw_Vdq_Hdq_Wdq SANITY when 226 => NEXT_OUTS <= 210; -- vpsrad_Vdq_Hdq_Wdq SANITY when 227 => NEXT_OUTS <= 427; -- vpavgw_Vdq_Hdq_Wdq SANITY when 228 => NEXT_OUTS <= 1134; -- vpmulhuw_Vdq_Hdq_Wdq SANITY when 229 => NEXT_OUTS <= 1587; -- vpmulhw_Vdq_Hdq_Wdq SANITY when 232 => NEXT_OUTS <= 194; -- vpsubsb_Vdq_Hdq_Wdq SANITY when 233 => NEXT_OUTS <= 1410; -- vpsubsw_Vdq_Hdq_Wdq SANITY when 234 => NEXT_OUTS <= 1339; -- vpminsw_Vdq_Hdq_Wdq SANITY when 235 => NEXT_OUTS <= 1623; -- vpor_Vdq_Hdq_Wdq SANITY when 236 => NEXT_OUTS <= 762; -- vpaddsb_Vdq_Hdq_Wdq SANITY when 237 => NEXT_OUTS <= 417; -- vpaddsw_Vdq_Hdq_Wdq SANITY when 238 => NEXT_OUTS <= 1003; -- vpmaxsw_Vdq_Hdq_Wdq SANITY when 239 => NEXT_OUTS <= 1361; -- vpxor_Vdq_Hdq_Wdq SANITY when 241 => NEXT_OUTS <= 1022; -- vpsllw_Vdq_Hdq_Wdq SANITY when 242 => NEXT_OUTS <= 163; -- vpslld_Vdq_Hdq_Wdq SANITY when 243 => NEXT_OUTS <= 916; -- vpsllq_Vdq_Hdq_Wdq SANITY when 244 => NEXT_OUTS <= 468; -- vpmuludq_Vdq_Hdq_Wdq SANITY when 245 => NEXT_OUTS <= 866; -- vpmaddwd_Vdq_Hdq_Wdq SANITY when 246 => NEXT_OUTS <= 1528; -- vpsadbw_Vdq_Hdq_Wdq SANITY when 248 => NEXT_OUTS <= 891; -- vpsubb_Vdq_Hdq_Wdq SANITY when 249 => NEXT_OUTS <= 275; -- vpsubw_Vdq_Hdq_Wdq SANITY when 250 => NEXT_OUTS <= 631; -- vpsubd_Vdq_Hdq_Wdq SANITY when 251 => NEXT_OUTS <= 152; -- vpsubq_Vdq_Hdq_Wdq SANITY when 252 => NEXT_OUTS <= 5; -- vpaddb_Vdq_Hdq_Wdq SANITY when 253 => NEXT_OUTS <= 1109; -- vpaddw_Vdq_Hdq_Wdq SANITY when 254 => NEXT_OUTS <= 66; -- vpaddd_Vdq_Hdq_Wdq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 210 => case OP3 is when 18 => NEXT_OUTS <= 602; -- vmovsldup_Vdq_Wdq SANITY when 22 => NEXT_OUTS <= 928; -- vmovshdup_Vdq_Wdq SANITY when 42 => NEXT_OUTS <= 1360; -- vcvtsi2ss_Vss_Hps_Ey SANITY when 88 => NEXT_OUTS <= 1258; -- vaddss_Vss_Hps_Wss SANITY when 89 => NEXT_OUTS <= 1072; -- vmulss_Vss_Hps_Wss SANITY when 92 => NEXT_OUTS <= 1657; -- vsubss_Vss_Hps_Wss SANITY when 93 => NEXT_OUTS <= 870; -- vminss_Vss_Hps_Wss SANITY when 94 => NEXT_OUTS <= 1550; -- vdivss_Vss_Hps_Wss SANITY when 95 => NEXT_OUTS <= 1402; -- vmaxss_Vss_Hps_Wss SANITY when 194 => case OP4 is when 0 => case OP5 is when 0 => NEXT_OUTS <= 1412; -- vcmpss_Vss_Hps_Wss_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 211 => case OP3 is when 18 => NEXT_OUTS <= 908; -- vmovddup_Vdq_Wq SANITY when 42 => NEXT_OUTS <= 1257; -- vcvtsi2sd_Vsd_Hpd_Ey SANITY when 88 => NEXT_OUTS <= 1210; -- vaddsd_Vsd_Hpd_Wsd SANITY when 89 => NEXT_OUTS <= 1355; -- vmulsd_Vsd_Hpd_Wsd SANITY when 92 => NEXT_OUTS <= 317; -- vsubsd_Vsd_Hpd_Wsd SANITY when 93 => NEXT_OUTS <= 901; -- vminsd_Vsd_Hpd_Wsd SANITY when 94 => NEXT_OUTS <= 1597; -- vdivsd_Vsd_Hpd_Wsd SANITY when 95 => NEXT_OUTS <= 131; -- vmaxsd_Vsd_Hpd_Wsd SANITY when 124 => NEXT_OUTS <= 442; -- vhaddps_Vps_Hps_Wps SANITY when 125 => NEXT_OUTS <= 240; -- vhsubps_Vps_Hps_Wps SANITY when 194 => case OP4 is when 0 => case OP5 is when 0 => NEXT_OUTS <= 1473; -- vcmpsd_Vsd_Hpd_Wsd_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 208 => NEXT_OUTS <= 1263; -- vaddsubps_Vps_Hps_Wps SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 248 => case OP3 is when 16 => NEXT_OUTS <= 1219; -- vmovups_Vps_Wps SANITY when 17 => NEXT_OUTS <= 28; -- vmovups_Wps_Vps SANITY when 19 => NEXT_OUTS <= 757; -- vmovlps_Mq_Vps SANITY when 23 => NEXT_OUTS <= 1459; -- vmovhps_Mq_Vps SANITY when 40 => NEXT_OUTS <= 710; -- vmovaps_Vps_Wps SANITY when 41 => NEXT_OUTS <= 1335; -- vmovaps_Wps_Vps SANITY when 43 => NEXT_OUTS <= 99; -- vmovntps_Mps_Vps SANITY when 46 => NEXT_OUTS <= 528; -- vucomiss_Vss_Wss SANITY when 47 => NEXT_OUTS <= 509; -- vcomiss_Vss_Wss SANITY when 80 => NEXT_OUTS <= 523; -- vmovmskps_Gd_Vps SANITY when 81 => NEXT_OUTS <= 1185; -- vsqrtps_Vps_Wps SANITY when 82 => NEXT_OUTS <= 316; -- vrsqrtps_Vps_Wps SANITY when 83 => NEXT_OUTS <= 850; -- vrcpps_Vps_Wps SANITY when 90 => NEXT_OUTS <= 1443; -- vcvtps2pd_Vpd_Wps SANITY when 91 => NEXT_OUTS <= 1280; -- vcvtdq2ps_Vps_Wdq SANITY when 119 => NEXT_OUTS <= 1031; -- vzeroupper SANITY when 174 => case OP4 is when 16 => NEXT_OUTS <= 38; -- vldmxcsr SANITY when 24 => NEXT_OUTS <= 818; -- vstmxcsr SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 249 => case OP3 is when 16 => NEXT_OUTS <= 1408; -- vmovupd_Vpd_Wpd SANITY when 17 => NEXT_OUTS <= 1432; -- vmovupd_Wpd_Vpd SANITY when 19 => NEXT_OUTS <= 217; -- vmovlpd_Mq_Vpd SANITY when 23 => NEXT_OUTS <= 1309; -- vmovhpd_Mq_Vpd SANITY when 40 => NEXT_OUTS <= 598; -- vmovapd_Vpd_Wpd SANITY when 41 => NEXT_OUTS <= 393; -- vmovapd_Wpd_Vpd SANITY when 43 => NEXT_OUTS <= 97; -- vmovntpd_Mpd_Vpd SANITY when 46 => NEXT_OUTS <= 1272; -- vucomisd_Vsd_Wsd SANITY when 47 => NEXT_OUTS <= 1290; -- vcomisd_Vsd_Wsd SANITY when 80 => NEXT_OUTS <= 580; -- vmovmskpd_Gd_Vpd SANITY when 81 => NEXT_OUTS <= 404; -- vsqrtpd_Vpd_Wpd SANITY when 90 => NEXT_OUTS <= 955; -- vcvtpd2ps_Vps_Wpd SANITY when 91 => NEXT_OUTS <= 29; -- vcvtps2dq_Vdq_Wps SANITY when 110 => NEXT_OUTS <= 391; -- vmovd_Vdq_Ed SANITY when 111 => NEXT_OUTS <= 1521; -- vmovdqa_Vdq_Wdq SANITY when 112 => NEXT_OUTS <= 283; -- vpshufd_Vdq_Hdq_Wdq_Ib SANITY when 126 => case OP4 is when 0 => NEXT_OUTS <= 827; -- vmovd_Ed_Vd SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 127 => NEXT_OUTS <= 478; -- vmovdqa_Wdq_Vdq SANITY when 197 => NEXT_OUTS <= 962; -- vpextrw_Gd_Udq_Ib SANITY when 214 => case OP4 is when 0 => NEXT_OUTS <= 1549; -- vmovq_Wq_Vq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 215 => NEXT_OUTS <= 30; -- vpmovmskb_Gd_Udq SANITY when 230 => NEXT_OUTS <= 754; -- vcvttpd2dq_Vq_Wpd SANITY when 231 => NEXT_OUTS <= 1592; -- vmovntdq_Mdq_Vdq SANITY when 247 => NEXT_OUTS <= 180; -- vmaskmovdqu_Vdq_Udq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 250 => case OP3 is when 16 => NEXT_OUTS <= 594; -- vmovss_Vss_Wss SANITY when 17 => NEXT_OUTS <= 331; -- vmovss_Wss_Vss SANITY when 44 => NEXT_OUTS <= 1382; -- vcvttss2si_Gy_Wss SANITY when 45 => NEXT_OUTS <= 612; -- vcvtss2si_Gy_Wss SANITY when 81 => NEXT_OUTS <= 683; -- vsqrtss_Vss_Hps_Wss SANITY when 82 => NEXT_OUTS <= 641; -- vrsqrtss_Vss_Hps_Wss SANITY when 83 => NEXT_OUTS <= 681; -- vrcpss_Vss_Hps_Wss SANITY when 90 => NEXT_OUTS <= 162; -- vcvtss2sd_Vsd_Hpd_Wss SANITY when 91 => NEXT_OUTS <= 1541; -- vcvttps2dq_Vdq_Wps SANITY when 111 => NEXT_OUTS <= 1108; -- vmovdqu_Vdq_Wdq SANITY when 112 => NEXT_OUTS <= 251; -- vpshufhw_Vdq_Hdq_Wdq_Ib SANITY when 126 => case OP4 is when 0 => NEXT_OUTS <= 572; -- vmovq_Vq_Wq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 127 => NEXT_OUTS <= 202; -- vmovdqu_Wdq_Vdq SANITY when 230 => NEXT_OUTS <= 1162; -- vcvtdq2pd_Vpd_Wq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 251 => case OP3 is when 16 => NEXT_OUTS <= 1567; -- vmovsd_Vsd_Wsd SANITY when 17 => NEXT_OUTS <= 390; -- vmovsd_Wsd_Vsd SANITY when 44 => NEXT_OUTS <= 1275; -- vcvttsd2si_Gy_Wsd SANITY when 45 => NEXT_OUTS <= 570; -- vcvtsd2si_Gy_Wsd SANITY when 81 => NEXT_OUTS <= 1337; -- vsqrtsd_Vsd_Hpd_Wsd SANITY when 90 => NEXT_OUTS <= 863; -- vcvtsd2ss_Vss_Hps_Wsd SANITY when 112 => NEXT_OUTS <= 207; -- vpshuflw_Vdq_Hdq_Wdq_Ib SANITY when 230 => NEXT_OUTS <= 1127; -- vcvtpd2dq_Vq_Wpd SANITY when 240 => NEXT_OUTS <= 1262; -- vlddqu_Vdq_Mdq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 198 => case OP2 is when 0 => NEXT_OUTS <= 1392; -- movb_Eb_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 199 => case OP2 is when 0 => NEXT_OUTS <= 1599; -- movl_Ed_Id SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 200 => NEXT_OUTS <= 555; -- enter SANITY when 201 => NEXT_OUTS <= 517; -- leave SANITY when 202 => NEXT_OUTS <= 35; -- lret_Iw SANITY when 203 => NEXT_OUTS <= 1460; -- lret SANITY when 204 => NEXT_OUTS <= 1086; -- int3 SANITY when 205 => NEXT_OUTS <= 72; -- int_Ib SANITY when 206 => NEXT_OUTS <= 287; -- into SANITY when 207 => NEXT_OUTS <= 498; -- iretl SANITY when 208 => case OP2 is when 0 => NEXT_OUTS <= 1452; -- rolb_Eb_I1 SANITY when 8 => NEXT_OUTS <= 106; -- rorb_Eb_I1 SANITY when 16 => NEXT_OUTS <= 1520; -- rclb_Eb_I1 SANITY when 24 => NEXT_OUTS <= 626; -- rcrb_Eb_I1 SANITY when 32 => NEXT_OUTS <= 1362; -- shlb_Eb_I1 SANITY when 40 => NEXT_OUTS <= 1523; -- shrb_Eb_I1 SANITY when 56 => NEXT_OUTS <= 873; -- sarb_Eb_I1 SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 209 => case OP2 is when 0 => NEXT_OUTS <= 1213; -- roll_Ed_I1 SANITY when 8 => NEXT_OUTS <= 1251; -- rorl_Ed_I1 SANITY when 16 => NEXT_OUTS <= 1648; -- rcll_Ed_I1 SANITY when 24 => NEXT_OUTS <= 1387; -- rcrl_Ed_I1 SANITY when 32 => NEXT_OUTS <= 1089; -- shll_Ed_I1 SANITY when 40 => NEXT_OUTS <= 685; -- shrl_Ed_I1 SANITY when 56 => NEXT_OUTS <= 1165; -- sarl_Ed_I1 SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 210 => case OP2 is when 0 => NEXT_OUTS <= 1298; -- rolb_Eb_CL SANITY when 8 => NEXT_OUTS <= 206; -- rorb_Eb_CL SANITY when 16 => NEXT_OUTS <= 1088; -- rclb_Eb_CL SANITY when 24 => NEXT_OUTS <= 750; -- rcrb_Eb_CL SANITY when 32 => NEXT_OUTS <= 820; -- shlb_Eb_CL SANITY when 40 => NEXT_OUTS <= 675; -- shrb_Eb_CL SANITY when 56 => NEXT_OUTS <= 800; -- sarb_Eb_CL SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 211 => case OP2 is when 0 => NEXT_OUTS <= 859; -- roll_Ed_CL SANITY when 8 => NEXT_OUTS <= 734; -- rorl_Ed_CL SANITY when 16 => NEXT_OUTS <= 1604; -- rcll_Ed_CL SANITY when 24 => NEXT_OUTS <= 321; -- rcrl_Ed_CL SANITY when 32 => NEXT_OUTS <= 1628; -- shll_Ed_CL SANITY when 40 => NEXT_OUTS <= 560; -- shrl_Ed_CL SANITY when 56 => NEXT_OUTS <= 161; -- sarl_Ed_CL SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 212 => NEXT_OUTS <= 1603; -- aam SANITY when 213 => NEXT_OUTS <= 1407; -- aad SANITY when 214 => NEXT_OUTS <= 156; -- salc SANITY when 215 => NEXT_OUTS <= 719; -- xlat SANITY when 216 => case OP2 is when 0 => NEXT_OUTS <= 51; -- fadds_Md SANITY when 8 => NEXT_OUTS <= 785; -- fmuls_Md SANITY when 16 => NEXT_OUTS <= 604; -- fcoms_Md SANITY when 24 => NEXT_OUTS <= 690; -- fcomps_Md SANITY when 32 => NEXT_OUTS <= 1525; -- fsubs_Md SANITY when 40 => NEXT_OUTS <= 778; -- fsubrs_Md SANITY when 48 => NEXT_OUTS <= 843; -- fdivs_Md SANITY when 56 => NEXT_OUTS <= 431; -- fdivrs_Md SANITY when 192 => NEXT_OUTS <= 584; -- fadd_ST0_STi SANITY when 200 => NEXT_OUTS <= 143; -- fmul_ST0_STi SANITY when 208 => NEXT_OUTS <= 1338; -- fcom_STi SANITY when 216 => NEXT_OUTS <= 299; -- fcomp_STi SANITY when 224 => NEXT_OUTS <= 869; -- fsub_ST0_STi SANITY when 232 => NEXT_OUTS <= 840; -- fsubr_ST0_STi SANITY when 240 => NEXT_OUTS <= 69; -- fdiv_ST0_STi SANITY when 248 => NEXT_OUTS <= 78; -- fdivr_ST0_STi SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 217 => case OP2 is when 0 => NEXT_OUTS <= 73; -- flds_Md SANITY when 16 => NEXT_OUTS <= 804; -- fsts_Md SANITY when 24 => NEXT_OUTS <= 1436; -- fstps_Md SANITY when 32 => NEXT_OUTS <= 1621; -- fldenv SANITY when 40 => NEXT_OUTS <= 1036; -- fldcw SANITY when 48 => NEXT_OUTS <= 913; -- fnstenv SANITY when 56 => NEXT_OUTS <= 1614; -- fnstcw SANITY when 192 => NEXT_OUTS <= 252; -- fld_STi SANITY when 200 => NEXT_OUTS <= 949; -- fxch SANITY when 208 => NEXT_OUTS <= 667; -- fnop SANITY when 224 => NEXT_OUTS <= 1259; -- fchs SANITY when 225 => NEXT_OUTS <= 233; -- fabs SANITY when 228 => NEXT_OUTS <= 1616; -- ftst SANITY when 229 => NEXT_OUTS <= 182; -- fxam SANITY when 232 => NEXT_OUTS <= 1502; -- fld1 SANITY when 233 => NEXT_OUTS <= 289; -- fldl2t SANITY when 234 => NEXT_OUTS <= 39; -- fldl2e SANITY when 235 => NEXT_OUTS <= 1400; -- fldpi SANITY when 236 => NEXT_OUTS <= 979; -- fldlg2 SANITY when 237 => NEXT_OUTS <= 218; -- fldln2 SANITY when 238 => NEXT_OUTS <= 839; -- fldz SANITY when 240 => NEXT_OUTS <= 1602; -- f2xm1 SANITY when 241 => NEXT_OUTS <= 1161; -- fyl2x SANITY when 242 => NEXT_OUTS <= 415; -- fptan SANITY when 243 => NEXT_OUTS <= 520; -- fpatan SANITY when 244 => NEXT_OUTS <= 925; -- fxtract SANITY when 245 => NEXT_OUTS <= 75; -- fprem1 SANITY when 246 => NEXT_OUTS <= 1128; -- fdecstp SANITY when 247 => NEXT_OUTS <= 279; -- fincstp SANITY when 248 => NEXT_OUTS <= 1245; -- fprem SANITY when 249 => NEXT_OUTS <= 178; -- fyl2xp1 SANITY when 250 => NEXT_OUTS <= 815; -- fsqrt SANITY when 251 => NEXT_OUTS <= 234; -- fsincos SANITY when 252 => NEXT_OUTS <= 253; -- frndint SANITY when 253 => NEXT_OUTS <= 1026; -- fscale SANITY when 254 => NEXT_OUTS <= 255; -- fsin SANITY when 255 => NEXT_OUTS <= 775; -- fcos SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 218 => case OP2 is when 0 => NEXT_OUTS <= 84; -- fiaddl_Md SANITY when 8 => NEXT_OUTS <= 188; -- fimull_Md SANITY when 16 => NEXT_OUTS <= 756; -- ficoml_Md SANITY when 24 => NEXT_OUTS <= 464; -- ficompl_Md SANITY when 32 => NEXT_OUTS <= 290; -- fisubl_Md SANITY when 40 => NEXT_OUTS <= 1079; -- fisubrl_Md SANITY when 48 => NEXT_OUTS <= 423; -- fidivl_Md SANITY when 56 => NEXT_OUTS <= 357; -- fidivrl_Md SANITY when 192 => NEXT_OUTS <= 318; -- fcmovb_ST0_STi SANITY when 200 => NEXT_OUTS <= 1170; -- fcmove_ST0_STi SANITY when 208 => NEXT_OUTS <= 297; -- fcmovbe_ST0_STi SANITY when 216 => NEXT_OUTS <= 1576; -- fcmovu_ST0_STi SANITY when 233 => NEXT_OUTS <= 24; -- fucompp SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 219 => case OP2 is when 0 => NEXT_OUTS <= 968; -- fildl_Md SANITY when 8 => NEXT_OUTS <= 372; -- fisttpl_Md SANITY when 16 => NEXT_OUTS <= 1425; -- fistl_Md SANITY when 24 => NEXT_OUTS <= 1509; -- fistpl_Md SANITY when 40 => NEXT_OUTS <= 592; -- fldt_Mt SANITY when 56 => NEXT_OUTS <= 219; -- fstpt_Mt SANITY when 192 => NEXT_OUTS <= 1448; -- fcmovnb_ST0_STi SANITY when 200 => NEXT_OUTS <= 543; -- fcmovne_ST0_STi SANITY when 208 => NEXT_OUTS <= 1122; -- fcmovnbe_ST0_STi SANITY when 216 => NEXT_OUTS <= 89; -- fcmovnu_ST0_STi SANITY when 226 => NEXT_OUTS <= 1334; -- fnclex SANITY when 227 => NEXT_OUTS <= 304; -- fninit SANITY when 232 => NEXT_OUTS <= 998; -- fucomi_ST0_STi SANITY when 240 => NEXT_OUTS <= 793; -- fcomi_ST0_STi SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 220 => case OP2 is when 0 => NEXT_OUTS <= 701; -- faddl_Mq SANITY when 8 => NEXT_OUTS <= 1253; -- fmull_Mq SANITY when 16 => NEXT_OUTS <= 1610; -- fcoml_Mq SANITY when 24 => NEXT_OUTS <= 871; -- fcompl_Mq SANITY when 32 => NEXT_OUTS <= 1492; -- fsubl_Mq SANITY when 40 => NEXT_OUTS <= 812; -- fsubrl_Mq SANITY when 48 => NEXT_OUTS <= 1220; -- fdivl_Mq SANITY when 56 => NEXT_OUTS <= 1052; -- fdivrl_Mq SANITY when 192 => NEXT_OUTS <= 852; -- fadd_STi_ST0 SANITY when 200 => NEXT_OUTS <= 320; -- fmul_STi_ST0 SANITY when 224 => NEXT_OUTS <= 1037; -- fsubr_STi_ST0 SANITY when 232 => NEXT_OUTS <= 227; -- fsub_STi_ST0 SANITY when 240 => NEXT_OUTS <= 368; -- fdivr_STi_ST0 SANITY when 248 => NEXT_OUTS <= 328; -- fdiv_STi_ST0 SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 221 => case OP2 is when 0 => NEXT_OUTS <= 651; -- fldl_Mq SANITY when 8 => NEXT_OUTS <= 296; -- fisttpq_Mq SANITY when 16 => NEXT_OUTS <= 230; -- fstl_Mq SANITY when 24 => NEXT_OUTS <= 1583; -- fstpl_Mq SANITY when 32 => NEXT_OUTS <= 272; -- frstor SANITY when 48 => NEXT_OUTS <= 1636; -- fnsave SANITY when 56 => NEXT_OUTS <= 858; -- fnstsw SANITY when 192 => NEXT_OUTS <= 912; -- ffree_STi SANITY when 208 => NEXT_OUTS <= 1405; -- fst_STi SANITY when 216 => NEXT_OUTS <= 860; -- fstp_STi SANITY when 224 => NEXT_OUTS <= 833; -- fucom_STi SANITY when 232 => NEXT_OUTS <= 566; -- fucomp_STi SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 222 => case OP2 is when 0 => NEXT_OUTS <= 1288; -- fiadds_Mw SANITY when 8 => NEXT_OUTS <= 1662; -- fimuls_Mw SANITY when 16 => NEXT_OUTS <= 310; -- ficoms_Mw SANITY when 24 => NEXT_OUTS <= 363; -- ficomps_Mw SANITY when 32 => NEXT_OUTS <= 1229; -- fisubs_Mw SANITY when 40 => NEXT_OUTS <= 1645; -- fisubrs_Mw SANITY when 48 => NEXT_OUTS <= 487; -- fidivs_Mw SANITY when 56 => NEXT_OUTS <= 1357; -- fidivrs_Mw SANITY when 192 => NEXT_OUTS <= 569; -- faddp_STi_ST0 SANITY when 200 => NEXT_OUTS <= 725; -- fmulp_STi_ST0 SANITY when 217 => NEXT_OUTS <= 441; -- fcompp SANITY when 224 => NEXT_OUTS <= 14; -- fsubrp_STi_ST0 SANITY when 232 => NEXT_OUTS <= 549; -- fsubp_STi_ST0 SANITY when 240 => NEXT_OUTS <= 905; -- fdivrp_STi_ST0 SANITY when 248 => NEXT_OUTS <= 563; -- fdivp_STi_ST0 SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 223 => case OP2 is when 0 => NEXT_OUTS <= 506; -- filds_Mw SANITY when 8 => NEXT_OUTS <= 259; -- fisttps_Mw SANITY when 16 => NEXT_OUTS <= 893; -- fists_Mw SANITY when 24 => NEXT_OUTS <= 936; -- fistps_Mw SANITY when 32 => NEXT_OUTS <= 1527; -- fbldt_Mt SANITY when 40 => NEXT_OUTS <= 293; -- fildq_Mq SANITY when 48 => NEXT_OUTS <= 986; -- fbstpt_Mt SANITY when 56 => NEXT_OUTS <= 1558; -- fistpq_Mq SANITY when 224 => NEXT_OUTS <= 1553; -- fnstsw_AX SANITY when 232 => NEXT_OUTS <= 1456; -- fucomip_ST0_STi SANITY when 240 => NEXT_OUTS <= 325; -- fcomip_ST0_STi SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 224 => NEXT_OUTS <= 177; -- loopne_Jb SANITY when 225 => NEXT_OUTS <= 209; -- loope_Jb SANITY when 226 => NEXT_OUTS <= 616; -- loop_Jb SANITY when 227 => case OP2 is when 0 => NEXT_OUTS <= 1077; -- jecxz_Jb SANITY when 1 => NEXT_OUTS <= 803; -- jrcxz_Jb SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 228 => NEXT_OUTS <= 347; -- inb_AL_Ib SANITY when 229 => NEXT_OUTS <= 1510; -- inl_EAX_Ib SANITY when 230 => NEXT_OUTS <= 571; -- outb_Ib_AL SANITY when 231 => NEXT_OUTS <= 1611; -- outl_Ib_EAX SANITY when 232 => NEXT_OUTS <= 1542; -- call_Jd SANITY when 233 => NEXT_OUTS <= 1424; -- jmp_Jd SANITY when 234 => NEXT_OUTS <= 1631; -- ljmp_Apd SANITY when 235 => NEXT_OUTS <= 605; -- jmp_Jb SANITY when 236 => NEXT_OUTS <= 365; -- inb_AL_DX SANITY when 237 => NEXT_OUTS <= 184; -- inl_EAX_DX SANITY when 238 => NEXT_OUTS <= 718; -- outb_DX_AL SANITY when 239 => NEXT_OUTS <= 1547; -- outl_DX_EAX SANITY when 241 => NEXT_OUTS <= 1595; -- int1 SANITY when 242 => case OP2 is when 15 => case OP3 is when 16 => NEXT_OUTS <= 18; -- movsd_Vsd_Wsd SANITY when 17 => NEXT_OUTS <= 437; -- movsd_Wsd_Vsd SANITY when 18 => NEXT_OUTS <= 1034; -- movddup_Vdq_Wq SANITY when 42 => NEXT_OUTS <= 1325; -- cvtsi2sd_Vsd_Ey SANITY when 44 => NEXT_OUTS <= 892; -- cvttsd2si_Gy_Wsd SANITY when 45 => NEXT_OUTS <= 590; -- cvtsd2si_Gy_Wsd SANITY when 56 => case OP4 is when 240 => NEXT_OUTS <= 1006; -- crc32_Gd_Eb SANITY when 241 => case OP5 is when 195 => NEXT_OUTS <= 1653; -- crc32_Gd_Ed SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 81 => NEXT_OUTS <= 1058; -- sqrtsd_Vsd_Wsd SANITY when 88 => NEXT_OUTS <= 1087; -- addsd_Vsd_Wsd SANITY when 89 => NEXT_OUTS <= 792; -- mulsd_Vsd_Wsd SANITY when 90 => NEXT_OUTS <= 1303; -- cvtsd2ss_Vss_Wsd SANITY when 92 => NEXT_OUTS <= 329; -- subsd_Vsd_Wsd SANITY when 93 => NEXT_OUTS <= 533; -- minsd_Vsd_Wsd SANITY when 94 => NEXT_OUTS <= 1054; -- divsd_Vsd_Wsd SANITY when 95 => NEXT_OUTS <= 214; -- maxsd_Vsd_Wsd SANITY when 112 => NEXT_OUTS <= 396; -- pshuflw_Vdq_Wdq_Ib SANITY when 124 => NEXT_OUTS <= 271; -- haddps_Vps_Wps SANITY when 125 => NEXT_OUTS <= 969; -- hsubps_Vps_Wps SANITY when 194 => case OP4 is when 0 => case OP5 is when 0 => NEXT_OUTS <= 165; -- cmpsd_Vsd_Wsd_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 208 => NEXT_OUTS <= 1319; -- addsubps_Vps_Wps SANITY when 214 => NEXT_OUTS <= 501; -- movdq2q_Pq_Udq SANITY when 230 => NEXT_OUTS <= 1145; -- cvtpd2dq_Vq_Wpd SANITY when 240 => NEXT_OUTS <= 46; -- lddqu_Vdq_Mdq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 72 => case OP3 is when 15 => case OP4 is when 56 => case OP5 is when 241 => case OP6 is when 195 => NEXT_OUTS <= 904; -- crc32_Gd_Eq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 243 => case OP2 is when 15 => case OP3 is when 16 => NEXT_OUTS <= 837; -- movss_Vss_Wss SANITY when 17 => NEXT_OUTS <= 726; -- movss_Wss_Vss SANITY when 18 => NEXT_OUTS <= 999; -- movsldup_Vdq_Wdq SANITY when 22 => NEXT_OUTS <= 1478; -- movshdup_Vdq_Wdq SANITY when 42 => NEXT_OUTS <= 620; -- cvtsi2ss_Vss_Ey SANITY when 44 => NEXT_OUTS <= 1276; -- cvttss2si_Gy_Wss SANITY when 45 => NEXT_OUTS <= 614; -- cvtss2si_Gy_Wss SANITY when 81 => NEXT_OUTS <= 1216; -- sqrtss_Vss_Wss SANITY when 82 => NEXT_OUTS <= 1153; -- rsqrtss_Vss_Wss SANITY when 83 => NEXT_OUTS <= 1559; -- rcpss_Vss_Wss SANITY when 88 => NEXT_OUTS <= 1208; -- addss_Vss_Wss SANITY when 89 => NEXT_OUTS <= 808; -- mulss_Vss_Wss SANITY when 90 => NEXT_OUTS <= 1009; -- cvtss2sd_Vsd_Wss SANITY when 91 => NEXT_OUTS <= 1321; -- cvttps2dq_Vdq_Wps SANITY when 92 => NEXT_OUTS <= 466; -- subss_Vss_Wss SANITY when 93 => NEXT_OUTS <= 494; -- minss_Vss_Wss SANITY when 94 => NEXT_OUTS <= 1383; -- divss_Vss_Wss SANITY when 95 => NEXT_OUTS <= 736; -- maxss_Vss_Wss SANITY when 111 => NEXT_OUTS <= 429; -- movdqu_Vdq_Wdq SANITY when 112 => NEXT_OUTS <= 1373; -- pshufhw_Vdq_Wdq_Ib SANITY when 126 => case OP4 is when 0 => NEXT_OUTS <= 449; -- movq_Vq_Wq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 127 => NEXT_OUTS <= 1013; -- movdqu_Wdq_Vdq SANITY when 174 => case OP4 is when 192 => NEXT_OUTS <= 1111; -- rdfsbase_Ry SANITY when 200 => NEXT_OUTS <= 1159; -- rdgsbase_Ry SANITY when 208 => NEXT_OUTS <= 126; -- wrfsbase_Ry SANITY when 216 => NEXT_OUTS <= 525; -- wrgsbase_Ry SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 184 => NEXT_OUTS <= 911; -- popcnt_Gd_Ed SANITY when 188 => NEXT_OUTS <= 747; -- tzcntl_Gd_Ed SANITY when 189 => NEXT_OUTS <= 1078; -- lzcntl_Gd_Ed SANITY when 194 => case OP4 is when 0 => case OP5 is when 0 => NEXT_OUTS <= 1508; -- cmpss_Vss_Wss_Ib SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 199 => case OP4 is when 48 => NEXT_OUTS <= 1101; -- vmxon_Mq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 214 => NEXT_OUTS <= 1294; -- movq2dq_Vdq_Qq SANITY when 230 => NEXT_OUTS <= 767; -- cvtdq2pd_Vpd_Wq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 72 => case OP3 is when 15 => case OP4 is when 184 => NEXT_OUTS <= 1017; -- popcnt_Gq_Eq SANITY when 188 => NEXT_OUTS <= 1192; -- tzcntq_Gq_Eq SANITY when 189 => NEXT_OUTS <= 708; -- lzcntq_Gq_Eq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when 144 => NEXT_OUTS <= 933; -- pause SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 244 => NEXT_OUTS <= 1286; -- hlt SANITY when 245 => NEXT_OUTS <= 25; -- cmc SANITY when 246 => case OP2 is when 0 => NEXT_OUTS <= 378; -- testb_Eb_Ib SANITY when 16 => NEXT_OUTS <= 1505; -- notb_Eb SANITY when 24 => NEXT_OUTS <= 664; -- negb_Eb SANITY when 32 => NEXT_OUTS <= 993; -- mulb_AL_Eb SANITY when 40 => NEXT_OUTS <= 1001; -- imulb_AL_Eb SANITY when 48 => NEXT_OUTS <= 629; -- divb_AL_Eb SANITY when 56 => NEXT_OUTS <= 267; -- idivb_AL_Eb SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 247 => case OP2 is when 0 => NEXT_OUTS <= 530; -- testl_Ed_Id SANITY when 16 => NEXT_OUTS <= 978; -- notl_Ed SANITY when 24 => NEXT_OUTS <= 1617; -- negl_Ed SANITY when 32 => NEXT_OUTS <= 250; -- mull_EAX_Ed SANITY when 40 => NEXT_OUTS <= 1381; -- imull_EAX_Ed SANITY when 48 => NEXT_OUTS <= 1051; -- divl_EAX_Ed SANITY when 56 => NEXT_OUTS <= 1056; -- idivl_EAX_Ed SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 248 => NEXT_OUTS <= 1094; -- clc SANITY when 249 => NEXT_OUTS <= 1203; -- stc SANITY when 250 => NEXT_OUTS <= 1466; -- cli SANITY when 251 => NEXT_OUTS <= 1057; -- sti SANITY when 252 => NEXT_OUTS <= 883; -- cld SANITY when 253 => NEXT_OUTS <= 947; -- std SANITY when 254 => case OP2 is when 0 => NEXT_OUTS <= 958; -- incb_Eb SANITY when 8 => NEXT_OUTS <= 930; -- decb_Eb SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 255 => case OP2 is when 0 => NEXT_OUTS <= 1240; -- incl_Ed SANITY when 8 => NEXT_OUTS <= 985; -- decl_Ed SANITY when 16 => case OP3 is when 0 => NEXT_OUTS <= 1099; -- call_Ed SANITY when 1 => NEXT_OUTS <= 746; -- call_Eq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 24 => NEXT_OUTS <= 1533; -- lcall_Mp SANITY when 32 => case OP3 is when 0 => NEXT_OUTS <= 748; -- jmp_Ed SANITY when 1 => NEXT_OUTS <= 1434; -- jmp_Eq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when 40 => NEXT_OUTS <= 362; -- ljmp_Mp SANITY when 48 => case OP3 is when 0 => NEXT_OUTS <= 922; -- pushl_Ed SANITY when 1 => NEXT_OUTS <= 313; -- pushq_Eq SANITY when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; when others => NEXT_OUTS <= 0; -- invalid end case; end process; end behv;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1374.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p03n01i01374ent IS END c08s05b00x00p03n01i01374ent; ARCHITECTURE c08s05b00x00p03n01i01374arch OF c08s05b00x00p03n01i01374ent IS BEGIN TESTING: PROCESS -- -- Define constants for package -- constant lowb : integer := 1 ; constant highb : integer := 5 ; constant lowb_i2 : integer := 0 ; constant highb_i2 : integer := 1000 ; constant lowb_p : integer := -100 ; constant highb_p : integer := 1000 ; constant lowb_r : real := 0.0 ; constant highb_r : real := 1000.0 ; constant lowb_r2 : real := 8.0 ; constant highb_r2 : real := 80.0 ; constant c_boolean_1 : boolean := false ; constant c_boolean_2 : boolean := true ; -- -- bit constant c_bit_1 : bit := '0' ; constant c_bit_2 : bit := '1' ; -- severity_level constant c_severity_level_1 : severity_level := NOTE ; constant c_severity_level_2 : severity_level := WARNING ; -- -- character constant c_character_1 : character := 'A' ; constant c_character_2 : character := 'a' ; -- integer types -- predefined constant c_integer_1 : integer := lowb ; constant c_integer_2 : integer := highb ; -- -- user defined integer type type t_int1 is range 0 to 100 ; constant c_t_int1_1 : t_int1 := 0 ; constant c_t_int1_2 : t_int1 := 10 ; subtype st_int1 is t_int1 range 8 to 60 ; constant c_st_int1_1 : st_int1 := 8 ; constant c_st_int1_2 : st_int1 := 9 ; -- -- physical types -- predefined constant c_time_1 : time := 1 ns ; constant c_time_2 : time := 2 ns ; -- -- -- floating point types -- predefined constant c_real_1 : real := 0.0 ; constant c_real_2 : real := 1.0 ; -- -- simple record type t_rec1 is record f1 : integer range lowb_i2 to highb_i2 ; f2 : time ; f3 : boolean ; f4 : real ; end record ; constant c_t_rec1_1 : t_rec1 := (c_integer_1, c_time_1, c_boolean_1, c_real_1) ; constant c_t_rec1_2 : t_rec1 := (c_integer_2, c_time_2, c_boolean_2, c_real_2) ; subtype st_rec1 is t_rec1 ; constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ; constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ; -- -- more complex record type t_rec2 is record f1 : boolean ; f2 : st_rec1 ; f3 : time ; end record ; constant c_t_rec2_1 : t_rec2 := (c_boolean_1, c_st_rec1_1, c_time_1) ; constant c_t_rec2_2 : t_rec2 := (c_boolean_2, c_st_rec1_2, c_time_2) ; subtype st_rec2 is t_rec2 ; constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ; constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ; -- -- simple array type t_arr1 is array (integer range <>) of st_int1 ; subtype t_arr1_range1 is integer range lowb to highb ; subtype st_arr1 is t_arr1 (t_arr1_range1) ; constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ; constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ; constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ; constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ; -- -- more complex array type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ; subtype t_arr2_range1 is integer range lowb to highb ; subtype t_arr2_range2 is boolean range false to true ; subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2); constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ; constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ; constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ; constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ; -- -- most complex record type t_rec3 is record f1 : boolean ; f2 : st_rec2 ; f3 : st_arr2 ; end record ; constant c_t_rec3_1 : t_rec3 := (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ; constant c_t_rec3_2 : t_rec3 := (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ; subtype st_rec3 is t_rec3 ; constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ; constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ; -- -- most complex array type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ; subtype t_arr3_range1 is integer range lowb to highb ; subtype t_arr3_range2 is boolean range true downto false ; subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ; constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ; constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ; constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ; constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ; -- variable v_st_arr3 : st_arr3 :=c_st_arr3_1 ; -- BEGIN v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) := c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ; assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2) report "***PASSED TEST: c08s05b00x00p03n01i01374" severity NOTE; assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2) report "***FAILED TEST: c08s05b00x00p03n01i01374 - The types of the variable and the assigned variable must match." severity ERROR; wait; END PROCESS TESTING; END c08s05b00x00p03n01i01374arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1374.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p03n01i01374ent IS END c08s05b00x00p03n01i01374ent; ARCHITECTURE c08s05b00x00p03n01i01374arch OF c08s05b00x00p03n01i01374ent IS BEGIN TESTING: PROCESS -- -- Define constants for package -- constant lowb : integer := 1 ; constant highb : integer := 5 ; constant lowb_i2 : integer := 0 ; constant highb_i2 : integer := 1000 ; constant lowb_p : integer := -100 ; constant highb_p : integer := 1000 ; constant lowb_r : real := 0.0 ; constant highb_r : real := 1000.0 ; constant lowb_r2 : real := 8.0 ; constant highb_r2 : real := 80.0 ; constant c_boolean_1 : boolean := false ; constant c_boolean_2 : boolean := true ; -- -- bit constant c_bit_1 : bit := '0' ; constant c_bit_2 : bit := '1' ; -- severity_level constant c_severity_level_1 : severity_level := NOTE ; constant c_severity_level_2 : severity_level := WARNING ; -- -- character constant c_character_1 : character := 'A' ; constant c_character_2 : character := 'a' ; -- integer types -- predefined constant c_integer_1 : integer := lowb ; constant c_integer_2 : integer := highb ; -- -- user defined integer type type t_int1 is range 0 to 100 ; constant c_t_int1_1 : t_int1 := 0 ; constant c_t_int1_2 : t_int1 := 10 ; subtype st_int1 is t_int1 range 8 to 60 ; constant c_st_int1_1 : st_int1 := 8 ; constant c_st_int1_2 : st_int1 := 9 ; -- -- physical types -- predefined constant c_time_1 : time := 1 ns ; constant c_time_2 : time := 2 ns ; -- -- -- floating point types -- predefined constant c_real_1 : real := 0.0 ; constant c_real_2 : real := 1.0 ; -- -- simple record type t_rec1 is record f1 : integer range lowb_i2 to highb_i2 ; f2 : time ; f3 : boolean ; f4 : real ; end record ; constant c_t_rec1_1 : t_rec1 := (c_integer_1, c_time_1, c_boolean_1, c_real_1) ; constant c_t_rec1_2 : t_rec1 := (c_integer_2, c_time_2, c_boolean_2, c_real_2) ; subtype st_rec1 is t_rec1 ; constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ; constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ; -- -- more complex record type t_rec2 is record f1 : boolean ; f2 : st_rec1 ; f3 : time ; end record ; constant c_t_rec2_1 : t_rec2 := (c_boolean_1, c_st_rec1_1, c_time_1) ; constant c_t_rec2_2 : t_rec2 := (c_boolean_2, c_st_rec1_2, c_time_2) ; subtype st_rec2 is t_rec2 ; constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ; constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ; -- -- simple array type t_arr1 is array (integer range <>) of st_int1 ; subtype t_arr1_range1 is integer range lowb to highb ; subtype st_arr1 is t_arr1 (t_arr1_range1) ; constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ; constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ; constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ; constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ; -- -- more complex array type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ; subtype t_arr2_range1 is integer range lowb to highb ; subtype t_arr2_range2 is boolean range false to true ; subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2); constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ; constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ; constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ; constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ; -- -- most complex record type t_rec3 is record f1 : boolean ; f2 : st_rec2 ; f3 : st_arr2 ; end record ; constant c_t_rec3_1 : t_rec3 := (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ; constant c_t_rec3_2 : t_rec3 := (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ; subtype st_rec3 is t_rec3 ; constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ; constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ; -- -- most complex array type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ; subtype t_arr3_range1 is integer range lowb to highb ; subtype t_arr3_range2 is boolean range true downto false ; subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ; constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ; constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ; constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ; constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ; -- variable v_st_arr3 : st_arr3 :=c_st_arr3_1 ; -- BEGIN v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) := c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ; assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2) report "***PASSED TEST: c08s05b00x00p03n01i01374" severity NOTE; assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2) report "***FAILED TEST: c08s05b00x00p03n01i01374 - The types of the variable and the assigned variable must match." severity ERROR; wait; END PROCESS TESTING; END c08s05b00x00p03n01i01374arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1374.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p03n01i01374ent IS END c08s05b00x00p03n01i01374ent; ARCHITECTURE c08s05b00x00p03n01i01374arch OF c08s05b00x00p03n01i01374ent IS BEGIN TESTING: PROCESS -- -- Define constants for package -- constant lowb : integer := 1 ; constant highb : integer := 5 ; constant lowb_i2 : integer := 0 ; constant highb_i2 : integer := 1000 ; constant lowb_p : integer := -100 ; constant highb_p : integer := 1000 ; constant lowb_r : real := 0.0 ; constant highb_r : real := 1000.0 ; constant lowb_r2 : real := 8.0 ; constant highb_r2 : real := 80.0 ; constant c_boolean_1 : boolean := false ; constant c_boolean_2 : boolean := true ; -- -- bit constant c_bit_1 : bit := '0' ; constant c_bit_2 : bit := '1' ; -- severity_level constant c_severity_level_1 : severity_level := NOTE ; constant c_severity_level_2 : severity_level := WARNING ; -- -- character constant c_character_1 : character := 'A' ; constant c_character_2 : character := 'a' ; -- integer types -- predefined constant c_integer_1 : integer := lowb ; constant c_integer_2 : integer := highb ; -- -- user defined integer type type t_int1 is range 0 to 100 ; constant c_t_int1_1 : t_int1 := 0 ; constant c_t_int1_2 : t_int1 := 10 ; subtype st_int1 is t_int1 range 8 to 60 ; constant c_st_int1_1 : st_int1 := 8 ; constant c_st_int1_2 : st_int1 := 9 ; -- -- physical types -- predefined constant c_time_1 : time := 1 ns ; constant c_time_2 : time := 2 ns ; -- -- -- floating point types -- predefined constant c_real_1 : real := 0.0 ; constant c_real_2 : real := 1.0 ; -- -- simple record type t_rec1 is record f1 : integer range lowb_i2 to highb_i2 ; f2 : time ; f3 : boolean ; f4 : real ; end record ; constant c_t_rec1_1 : t_rec1 := (c_integer_1, c_time_1, c_boolean_1, c_real_1) ; constant c_t_rec1_2 : t_rec1 := (c_integer_2, c_time_2, c_boolean_2, c_real_2) ; subtype st_rec1 is t_rec1 ; constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ; constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ; -- -- more complex record type t_rec2 is record f1 : boolean ; f2 : st_rec1 ; f3 : time ; end record ; constant c_t_rec2_1 : t_rec2 := (c_boolean_1, c_st_rec1_1, c_time_1) ; constant c_t_rec2_2 : t_rec2 := (c_boolean_2, c_st_rec1_2, c_time_2) ; subtype st_rec2 is t_rec2 ; constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ; constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ; -- -- simple array type t_arr1 is array (integer range <>) of st_int1 ; subtype t_arr1_range1 is integer range lowb to highb ; subtype st_arr1 is t_arr1 (t_arr1_range1) ; constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ; constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ; constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ; constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ; -- -- more complex array type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ; subtype t_arr2_range1 is integer range lowb to highb ; subtype t_arr2_range2 is boolean range false to true ; subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2); constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ; constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ; constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ; constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ; -- -- most complex record type t_rec3 is record f1 : boolean ; f2 : st_rec2 ; f3 : st_arr2 ; end record ; constant c_t_rec3_1 : t_rec3 := (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ; constant c_t_rec3_2 : t_rec3 := (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ; subtype st_rec3 is t_rec3 ; constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ; constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ; -- -- most complex array type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ; subtype t_arr3_range1 is integer range lowb to highb ; subtype t_arr3_range2 is boolean range true downto false ; subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ; constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ; constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ; constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ; constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ; -- variable v_st_arr3 : st_arr3 :=c_st_arr3_1 ; -- BEGIN v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) := c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ; assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2) report "***PASSED TEST: c08s05b00x00p03n01i01374" severity NOTE; assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2) report "***FAILED TEST: c08s05b00x00p03n01i01374 - The types of the variable and the assigned variable must match." severity ERROR; wait; END PROCESS TESTING; END c08s05b00x00p03n01i01374arch;
LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE ieee.math_real.all; USE work.FIR_constants.all; USE STD.textio.all; ENTITY tb_FIR_filter_direct IS GENERIC( N_sample: integer := 202 ); END ENTITY; ARCHITECTURE test OF tb_FIR_filter_direct IS TYPE vector_test IS ARRAY (N_sample-1 DOWNTO 0) OF INTEGER; TYPE coeffs_array IS ARRAY (Ord DOWNTO 0) OF INTEGER; TYPE sig_array IS ARRAY (Ord DOWNTO 0) OF SIGNED(Nb-1 DOWNTO 0); FILE inputs: text; FILE coeff_file: text; FILE c_outs_file: text; SHARED VARIABLE input_samples, c_outputs: vector_test; SIGNAL tot_pipe_stages: INTEGER; SIGNAL CLK, RST_n: STD_LOGIC; SIGNAL VIN, VOUT: STD_LOGIC; SIGNAL VIN_array: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL sample: SIGNED(Nb-1 DOWNTO 0); SIGNAL DINconverted: STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); SIGNAL filter_out: STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); SIGNAL coeffs_std: std_logic_vector ((Ord+1)*Nb - 1 DOWNTO 0); SIGNAL visual_coeffs_integer: coeffs_array; SIGNAL regToDIN: STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); SIGNAL DOUTtoReg: STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); COMPONENT FIR_filter IS PORT( CLK, RST_n: IN STD_LOGIC; VIN: IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); Coeffs: IN STD_LOGIC_VECTOR(((Ord+1)*Nb)-1 DOWNTO 0); --# of coeffs IS Ord+1 VOUT: OUT STD_LOGIC; DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0) ); END COMPONENT; COMPONENT Reg_n IS GENERIC(Nb: INTEGER :=9); PORT( CLK, RST_n, EN: IN STD_LOGIC; DIN: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0) ); END COMPONENT; BEGIN Tot_latency: PROCESS BEGIN IF IO_buffers = TRUE THEN tot_pipe_stages <= 2; ELSE tot_pipe_stages <= 0; END IF; WAIT; END PROCESS; DINconverted <= std_logic_vector(sample); DUT: FIR_filter PORT MAP (CLK => CLK, RST_n => RST_n, VIN => VIN_array(2), DIN => regToDIN, Coeffs => coeffs_std, VOUT => VOUT, DOUT => DOUTtoReg); VIN_array(0) <= VIN; VIN_REGS: FOR i IN 0 TO 1 GENERATE REGS_VIN: Reg_n GENERIC MAP (Nb => 1) PORT MAP(CLK => CLK, RST_n => RST_n, EN => '1', DIN => VIN_array(i DOWNTO i), DOUT => VIN_array(i+1 DOWNTO i+1)); END GENERATE; REG_IN: Reg_n GENERIC MAP (Nb => Nb) PORT MAP (CLK => CLK, RST_n => RST_n, EN => VIN_array(1), DIN => DINconverted, DOUT => regToDIN ); REG_OUT: Reg_n GENERIC MAP (Nb => Nb) PORT MAP (CLK => CLK, RST_n => RST_n, EN => VOUT, DIN => DOUTtoReg, DOUT => filter_out ); CLK_gen: PROCESS BEGIN CLK <= '0'; WAIT FOR 10 ns; CLK <= '1'; WAIT FOR 10 ns; END PROCESS; VIN_RST_gen: PROCESS BEGIN VIN <= '0'; RST_n <= '0'; WAIT FOR 10 ns; RST_n <= '1'; WAIT FOR 5 ns; VIN <= '1'; WAIT FOR 745 ns; VIN <= '0'; WAIT FOR 60 ns; VIN <= '1'; WAIT FOR 3280 ns; VIN <= '0'; WAIT; END PROCESS; test_input_read: PROCESS VARIABLE iLine,cLine, coutLine: LINE; VARIABLE i,j,k: INTEGER := 0; VARIABLE coeffs_integer: coeffs_array; BEGIN file_open(inputs, "samples.txt", READ_MODE); WHILE (NOT ENDFILE(inputs)) LOOP READLINE(inputs, iLine); READ(iLine, input_samples(i)); i := i+1; END LOOP; file_close(inputs); file_open(coeff_file, "coeffs.txt", READ_MODE); WHILE (NOT ENDFILE(coeff_file)) LOOP READLINE(coeff_file, cLine); READ(cLine, coeffs_integer(j)); j := j+1; END LOOP; file_close(coeff_file); visual_coeffs_integer <= coeffs_integer; file_open(c_outs_file, "c_outputvectors.txt", READ_MODE); WHILE (NOT ENDFILE(c_outs_file)) LOOP READLINE(c_outs_file, coutLine); READ(coutLine, c_outputs(k)); k := k+1; END LOOP; file_close(c_outs_file); FOR i IN 0 TO Ord LOOP coeffs_std((i+1)*Nb-1 DOWNTO i*Nb)<= std_logic_vector(to_signed(coeffs_integer(i),Nb)); END LOOP; WAIT; END PROCESS; test_results_write: PROCESS(CLK) VARIABLE oLine: LINE; VARIABLE i, j: INTEGER := 0; VARIABLE diff: INTEGER := 0; FILE results: text is out "output_vectors_direct.txt"; FILE output_diffs: text is out "output_diffs.txt"; BEGIN IF CLK'EVENT AND CLK = '1' THEN IF VIN = '1' THEN sample <= to_signed(input_samples(i),sample'LENGTH); i:= i+1; END IF; END IF; IF CLK'EVENT AND CLK = '1' THEN IF VOUT = '1' THEN WRITE(oLine, to_integer(signed(DOUTtoReg))); WRITELINE(results, oLine); diff := (to_integer(signed(DOUTtoReg)) - c_outputs(j)); IF(diff /= 0) THEN WRITE(oLine, diff); WRITE(oLine, string'(" Sample: ")); WRITE(oLine, (j+1)); WRITELINE(output_diffs, oLine); END IF; j := j+1; END IF; END IF; END PROCESS; END test;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ent is end ent; architecture sim of ent is signal s_clk : std_logic := '1'; signal s_test : std_logic := '0'; begin s_clk <= not s_clk after 5 ns; s_test <= '1' after 30 ns, '0' after 40 ns; process is begin wait until rising_edge(s_clk); -- This works if s_test'stable(10 ns) then report "s_test stable"; else report "s_test changed"; end if; end process; -- This works -- psl assert always (s_test'stable)@rising_edge(s_clk); -- This leads to an compile error -- psl assert always (s_test'stable(10 ns))@rising_edge(s_clk); end architecture sim;
---------------------------------------------------------------------------------- -- Company: University of Cyprus, Department of Computer Science -- Engineer: Dr. Petros Panayi -- -- Create Date: 15:28:22 03/23/2007 -- Design Name: -- Module Name: DataRAM - Behavioral -- Project Name: MIPS32 -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity DataRAM is Port ( DataAddress : in STD_LOGIC_VECTOR (9 downto 0); clk : in STD_LOGIC; readData : in STD_LOGIC; writeData : in STD_LOGIC; DataIn : in STD_LOGIC_VECTOR (31 downto 0); DataOut : out STD_LOGIC_VECTOR (31 downto 0)); end DataRAM; architecture Behavioral of DataRAM is -- Define a new type with the name RAM_Array of 8 bits type RAM_Array is array (0 to 1023) of std_logic_vector(7 downto 0); -- Set some initial values in RAM for Testing signal RAMContent: RAM_Array := ( 0 => X"00", 1 => X"01", 2 => X"02", 3 => X"03", 4 => X"04", 5 => X"05", 6 => X"06", 7 => X"07", 8 => X"08", 9 => X"09", 10 => X"0A", 11 => X"0B", 12 => X"0C", 13 => X"0D", 14 => X"0E", 15 => X"0F", others => X"00"); begin -- This process is called when we READ from RAM p1: process (readData, DataAddress) begin if readData = '1' then DataOut(7 downto 0) <= RAMContent(conv_integer(DataAddress)); DataOut(15 downto 8) <= RAMContent(conv_integer(DataAddress+1)); DataOut(23 downto 16) <= RAMContent(conv_integer(DataAddress+2)); DataOut(31 downto 24) <= RAMContent(conv_integer(DataAddress+3)); else DataOut <= (DataOut'range => 'Z'); end if; end process; -- This process is called when we WRITE into RAM p2: process (clk, writeData) begin if (clk'event and clk = '1') then if writeData ='1' then RAMContent(conv_integer(DataAddress)) <= DataIn(7 downto 0); RAMContent(conv_integer(DataAddress+1)) <= DataIn(15 downto 8); RAMContent(conv_integer(DataAddress+2)) <= DataIn(23 downto 16); RAMContent(conv_integer(DataAddress+3)) <= DataIn(31 downto 24); end if; end if; end process; end Behavioral;
-- modem_recepcao.vhd -- -- componente que modela a recepcao de dados do modem -- => usar para os testes de simulacao do projeto final -- -- Labdig (3o quadrimestre de 2017) library IEEE; use IEEE.std_logic_1164.all; entity modem_recepcao is port ( clock, reset, DTR, RC: in STD_LOGIC; CD, RD: out STD_LOGIC ); end; architecture modem_recepcao of modem_recepcao is type estados_rx is (inicial_rx, em_recepcao); signal Eatual, Eprox: estados_rx; begin -- estado process (RESET, CLOCK) begin if RESET = '1' then Eatual <= inicial_rx; elsif CLOCK'event and CLOCK = '1' then Eatual <= Eprox; end if; end process; -- proximo estado process (DTR, Eatual) begin case Eatual is when inicial_rx => if DTR='0' then Eprox <= em_recepcao; else Eprox <= inicial_rx; end if; when em_recepcao => if DTR='1' then Eprox <= inicial_rx; else Eprox <= em_recepcao; end if; when others => Eprox <= inicial_rx; end case; end process; -- saidas with Eatual select CD <= '0' when em_recepcao, '1' when others; with Eatual select RD <= RC when em_recepcao, '0' when others; end modem_recepcao;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library board; use board.zpu_config.all; entity wbmux2 is generic ( select_line: integer; address_high: integer:=31; address_low: integer:=2 ); port ( wb_clk_i: in std_logic; wb_rst_i: in std_logic; -- Master m_wb_dat_o: out std_logic_vector(31 downto 0); m_wb_dat_i: in std_logic_vector(31 downto 0); m_wb_adr_i: in std_logic_vector(address_high downto address_low); m_wb_sel_i: in std_logic_vector(3 downto 0); m_wb_cti_i: in std_logic_vector(2 downto 0); m_wb_we_i: in std_logic; m_wb_cyc_i: in std_logic; m_wb_stb_i: in std_logic; m_wb_ack_o: out std_logic; -- Slave 0 signals s0_wb_dat_i: in std_logic_vector(31 downto 0); s0_wb_dat_o: out std_logic_vector(31 downto 0); s0_wb_adr_o: out std_logic_vector(address_high downto address_low); s0_wb_sel_o: out std_logic_vector(3 downto 0); s0_wb_cti_o: out std_logic_vector(2 downto 0); s0_wb_we_o: out std_logic; s0_wb_cyc_o: out std_logic; s0_wb_stb_o: out std_logic; s0_wb_ack_i: in std_logic; -- Slave 1 signals s1_wb_dat_i: in std_logic_vector(31 downto 0); s1_wb_dat_o: out std_logic_vector(31 downto 0); s1_wb_adr_o: out std_logic_vector(address_high downto address_low); s1_wb_sel_o: out std_logic_vector(3 downto 0); s1_wb_cti_o: out std_logic_vector(2 downto 0); s1_wb_we_o: out std_logic; s1_wb_cyc_o: out std_logic; s1_wb_stb_o: out std_logic; s1_wb_ack_i: in std_logic ); end entity wbmux2; architecture behave of wbmux2 is signal select_zero: std_logic; begin select_zero<='1' when m_wb_adr_i(select_line)='0' else '0'; s0_wb_dat_o <= m_wb_dat_i; s0_wb_adr_o <= m_wb_adr_i; s0_wb_stb_o <= m_wb_stb_i; s0_wb_we_o <= m_wb_we_i; s0_wb_cti_o <= m_wb_cti_i; s0_wb_sel_o <= m_wb_sel_i; s1_wb_dat_o <= m_wb_dat_i; s1_wb_adr_o <= m_wb_adr_i; s1_wb_stb_o <= m_wb_stb_i; s1_wb_we_o <= m_wb_we_i; s1_wb_cti_o <= m_wb_cti_i; s1_wb_sel_o <= m_wb_sel_i; process(m_wb_cyc_i,select_zero) begin if m_wb_cyc_i='0' then s0_wb_cyc_o<='0'; s1_wb_cyc_o<='0'; else s0_wb_cyc_o<=select_zero; s1_wb_cyc_o<=not select_zero; end if; end process; process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i) begin if select_zero='0' then m_wb_dat_o<=s1_wb_dat_i; m_wb_ack_o<=s1_wb_ack_i; else m_wb_dat_o<=s0_wb_dat_i; m_wb_ack_o<=s0_wb_ack_i; end if; end process; end behave;
-- -- some extensions to the textio package -- USE std.textio.ALL; PACKAGE io_utils IS PROCEDURE write_string(l : INOUT line; value : IN string; justified : IN side := right; field : IN width := 0); TYPE radix IS (binary, octal, decimal, hex); -- read a number from the line -- use this if you have hex numbers that are not in VHDL pound-sign format PROCEDURE read(l : INOUT line; value : OUT integer; radix : IN positive); -- read a number that might be in VHDL pound-sign format PROCEDURE read_based(l : INOUT line; value : OUT integer); PROCEDURE write(l : INOUT line; value : IN bit_vector; justified : IN side := right; field : IN width := 0; base : IN radix; use_pound : boolean := false); PROCEDURE write(l : INOUT line; value : IN integer; justified : IN side := right; field : IN width := 0; base : IN radix; use_pound : boolean := false); END io_utils; PACKAGE BODY io_utils IS PROCEDURE write_string(l : INOUT line; value : IN string; justified : IN side := right; field : IN width := 0) IS BEGIN write(l, value, justified, field); END; PROCEDURE shrink_line(l : INOUT line; pos : integer) IS VARIABLE tmpl : line; BEGIN tmpl := l; l := NEW string'(tmpl(pos TO tmpl'high)); deallocate(tmpl); END; PROCEDURE read(l : INOUT line; value : OUT integer; radix : IN positive) IS CONSTANT not_digit : integer := -999; -- convert a character to a value from 0 to 15 FUNCTION digit_value(c : character) RETURN integer IS BEGIN IF (c >= '0') AND (c <= '9') THEN RETURN (character'pos(c) - character'pos('0')); ELSIF (c >= 'a') AND (c <= 'f') THEN RETURN (character'pos(c) - character'pos('a') + 10); ELSIF (c >= 'A') AND (c <= 'F') THEN RETURN (character'pos(c) - character'pos('A') + 10); ELSE RETURN not_digit; END IF; END; -- skip leading white space in the line PROCEDURE skip_white(VARIABLE l : IN line; pos : OUT integer) IS BEGIN pos := l'low; FOR i IN l'low TO l'high LOOP CASE l(i) IS WHEN ' ' | ht => pos := i + 1; WHEN OTHERS => EXIT; END CASE; END LOOP; END; VARIABLE digit : integer; VARIABLE result : integer := 0; VARIABLE pos : integer; BEGIN -- skip white space skip_white(l, pos); -- calculate the value FOR i IN pos TO l'right LOOP digit := digit_value(l(i)); EXIT WHEN (digit = not_digit) OR (digit >= radix); result := result * radix + digit; pos := i + 1; END LOOP; value := result; -- remove the "used" characters from the line shrink_line(l, pos); END; PROCEDURE read_based(l : INOUT line; value : OUT integer) IS VARIABLE digit : integer; VARIABLE num : integer; VARIABLE base : integer; BEGIN read(l, num, 10); IF (l'length > 1) AND (l(l'left) = '#') THEN shrink_line(l, l'left+1); base := num; read(l, num, base); IF (l'length >= 1) AND (l(l'left) = '#') THEN shrink_line(l, l'left+1); END IF; END IF; value := num; END; PROCEDURE write(l : INOUT line; value : IN bit_vector; justified : IN side := right; field : IN width := 0; base : IN radix; use_pound : boolean := false) IS FUNCTION to_int(bv : bit_vector) RETURN integer IS VARIABLE result : integer := 0; BEGIN FOR i IN bv'RANGE LOOP result := result * 2; IF (bv(i) = '1') THEN result := result + 1; END IF; END LOOP; RETURN result; END; TYPE array_of_widths IS ARRAY(radix) OF natural; CONSTANT nibble_widths : array_of_widths := ( binary => 1, octal => 3, hex => 4, decimal=> 32); CONSTANT hex_digit : string(1 TO 16) := "0123456789ABCDEF"; ALIAS input_val : bit_vector(value'length DOWNTO 1) IS value; CONSTANT nibble_width : natural := nibble_widths(base); CONSTANT result_width : natural := (value'length + nibble_width - 1)/nibble_width; VARIABLE result : string(1 TO result_width); -- longest possible value VARIABLE result_pos : positive := 1; VARIABLE nibble_val : integer; VARIABLE bitcnt : integer; BEGIN IF base = decimal THEN write(l, to_int(value), justified, field, base, use_pound); RETURN; END IF; bitcnt := value'length MOD nibble_width; IF (bitcnt = 0) THEN bitcnt := nibble_width; END IF; FOR i IN input_val'RANGE LOOP nibble_val := nibble_val * 2; IF (input_val(i) = '1') THEN nibble_val := nibble_val + 1; END IF; bitcnt := bitcnt - 1; IF (bitcnt = 0) THEN result(result_pos) := hex_digit(nibble_val + 1); result_pos := result_pos + 1; nibble_val := 0; bitcnt := nibble_width; END IF; END LOOP; write(l, result, justified, field); END; PROCEDURE write(l : INOUT line; value : IN integer; justified : IN side := right; field : IN width := 0; base : IN radix; use_pound : boolean := false) IS FUNCTION to_bv(int : integer) RETURN bit_vector IS VARIABLE bv : bit_vector(32 DOWNTO 1) := (OTHERS => '0'); VARIABLE pos : integer := 0; VARIABLE tmpval : integer := int; BEGIN FOR i IN 1 TO 32 LOOP pos := pos + 1; IF (tmpval MOD 2) = 1 THEN bv(i) := '1'; END IF; tmpval := tmpval / 2; EXIT WHEN tmpval = 0; END LOOP; RETURN bv(pos DOWNTO 1); END; VARIABLE tmp : line; BEGIN IF (base = decimal) THEN IF (use_pound) THEN write_string(tmp, "10#"); END IF; write(tmp, value); IF (use_pound) THEN write_string(tmp, "#"); END IF; write(l, tmp.ALL, justified, field); deallocate(tmp); ELSE write(l, to_bv(value), justified, field, base, use_pound); END IF; END; END io_utils;
-- -- some extensions to the textio package -- USE std.textio.ALL; PACKAGE io_utils IS PROCEDURE write_string(l : INOUT line; value : IN string; justified : IN side := right; field : IN width := 0); TYPE radix IS (binary, octal, decimal, hex); -- read a number from the line -- use this if you have hex numbers that are not in VHDL pound-sign format PROCEDURE read(l : INOUT line; value : OUT integer; radix : IN positive); -- read a number that might be in VHDL pound-sign format PROCEDURE read_based(l : INOUT line; value : OUT integer); PROCEDURE write(l : INOUT line; value : IN bit_vector; justified : IN side := right; field : IN width := 0; base : IN radix; use_pound : boolean := false); PROCEDURE write(l : INOUT line; value : IN integer; justified : IN side := right; field : IN width := 0; base : IN radix; use_pound : boolean := false); END io_utils; PACKAGE BODY io_utils IS PROCEDURE write_string(l : INOUT line; value : IN string; justified : IN side := right; field : IN width := 0) IS BEGIN write(l, value, justified, field); END; PROCEDURE shrink_line(l : INOUT line; pos : integer) IS VARIABLE tmpl : line; BEGIN tmpl := l; l := NEW string'(tmpl(pos TO tmpl'high)); deallocate(tmpl); END; PROCEDURE read(l : INOUT line; value : OUT integer; radix : IN positive) IS CONSTANT not_digit : integer := -999; -- convert a character to a value from 0 to 15 FUNCTION digit_value(c : character) RETURN integer IS BEGIN IF (c >= '0') AND (c <= '9') THEN RETURN (character'pos(c) - character'pos('0')); ELSIF (c >= 'a') AND (c <= 'f') THEN RETURN (character'pos(c) - character'pos('a') + 10); ELSIF (c >= 'A') AND (c <= 'F') THEN RETURN (character'pos(c) - character'pos('A') + 10); ELSE RETURN not_digit; END IF; END; -- skip leading white space in the line PROCEDURE skip_white(VARIABLE l : IN line; pos : OUT integer) IS BEGIN pos := l'low; FOR i IN l'low TO l'high LOOP CASE l(i) IS WHEN ' ' | ht => pos := i + 1; WHEN OTHERS => EXIT; END CASE; END LOOP; END; VARIABLE digit : integer; VARIABLE result : integer := 0; VARIABLE pos : integer; BEGIN -- skip white space skip_white(l, pos); -- calculate the value FOR i IN pos TO l'right LOOP digit := digit_value(l(i)); EXIT WHEN (digit = not_digit) OR (digit >= radix); result := result * radix + digit; pos := i + 1; END LOOP; value := result; -- remove the "used" characters from the line shrink_line(l, pos); END; PROCEDURE read_based(l : INOUT line; value : OUT integer) IS VARIABLE digit : integer; VARIABLE num : integer; VARIABLE base : integer; BEGIN read(l, num, 10); IF (l'length > 1) AND (l(l'left) = '#') THEN shrink_line(l, l'left+1); base := num; read(l, num, base); IF (l'length >= 1) AND (l(l'left) = '#') THEN shrink_line(l, l'left+1); END IF; END IF; value := num; END; PROCEDURE write(l : INOUT line; value : IN bit_vector; justified : IN side := right; field : IN width := 0; base : IN radix; use_pound : boolean := false) IS FUNCTION to_int(bv : bit_vector) RETURN integer IS VARIABLE result : integer := 0; BEGIN FOR i IN bv'RANGE LOOP result := result * 2; IF (bv(i) = '1') THEN result := result + 1; END IF; END LOOP; RETURN result; END; TYPE array_of_widths IS ARRAY(radix) OF natural; CONSTANT nibble_widths : array_of_widths := ( binary => 1, octal => 3, hex => 4, decimal=> 32); CONSTANT hex_digit : string(1 TO 16) := "0123456789ABCDEF"; ALIAS input_val : bit_vector(value'length DOWNTO 1) IS value; CONSTANT nibble_width : natural := nibble_widths(base); CONSTANT result_width : natural := (value'length + nibble_width - 1)/nibble_width; VARIABLE result : string(1 TO result_width); -- longest possible value VARIABLE result_pos : positive := 1; VARIABLE nibble_val : integer; VARIABLE bitcnt : integer; BEGIN IF base = decimal THEN write(l, to_int(value), justified, field, base, use_pound); RETURN; END IF; bitcnt := value'length MOD nibble_width; IF (bitcnt = 0) THEN bitcnt := nibble_width; END IF; FOR i IN input_val'RANGE LOOP nibble_val := nibble_val * 2; IF (input_val(i) = '1') THEN nibble_val := nibble_val + 1; END IF; bitcnt := bitcnt - 1; IF (bitcnt = 0) THEN result(result_pos) := hex_digit(nibble_val + 1); result_pos := result_pos + 1; nibble_val := 0; bitcnt := nibble_width; END IF; END LOOP; write(l, result, justified, field); END; PROCEDURE write(l : INOUT line; value : IN integer; justified : IN side := right; field : IN width := 0; base : IN radix; use_pound : boolean := false) IS FUNCTION to_bv(int : integer) RETURN bit_vector IS VARIABLE bv : bit_vector(32 DOWNTO 1) := (OTHERS => '0'); VARIABLE pos : integer := 0; VARIABLE tmpval : integer := int; BEGIN FOR i IN 1 TO 32 LOOP pos := pos + 1; IF (tmpval MOD 2) = 1 THEN bv(i) := '1'; END IF; tmpval := tmpval / 2; EXIT WHEN tmpval = 0; END LOOP; RETURN bv(pos DOWNTO 1); END; VARIABLE tmp : line; BEGIN IF (base = decimal) THEN IF (use_pound) THEN write_string(tmp, "10#"); END IF; write(tmp, value); IF (use_pound) THEN write_string(tmp, "#"); END IF; write(l, tmp.ALL, justified, field); deallocate(tmp); ELSE write(l, to_bv(value), justified, field, base, use_pound); END IF; END; END io_utils;
--------------------------------------------------------------------------- -- (c) 2013 mark watson -- I am happy for anyone to use this for non-commercial use. -- If my vhdl files are used commercially or otherwise sold, -- please contact me for explicit permission at scrameta (gmail). -- This applies for source and binary form and derived works. --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_unsigned.ALL; use ieee.numeric_std.ALL; ENTITY cpu IS PORT ( CLK,RESET,ENABLE : IN STD_logic; DI : IN std_logic_vector(7 downto 0); IRQ_n : in std_logic; NMI_n : in std_logic; MEMORY_READY : in std_logic; THROTTLE : in std_logic; RDY : in std_logic; DO : OUT std_logic_vector(7 downto 0); A : OUT std_logic_vector(15 downto 0); R_W_n : OUT std_logic; CPU_FETCH : out std_logic ); END cpu; architecture vhdl of cpu is component cpu_65xx is generic ( pipelineOpcode : boolean; pipelineAluMux : boolean; pipelineAluOut : boolean ); port ( clk : in std_logic; enable : in std_logic; halt : in std_logic := '0'; reset : in std_logic; nmi_n : in std_logic := '1'; irq_n : in std_logic := '1'; so_n : in std_logic := '1'; d : in unsigned(7 downto 0); q : out unsigned(7 downto 0); addr : out unsigned(15 downto 0); we : out std_logic; debugOpcode : out unsigned(7 downto 0); debugPc : out unsigned(15 downto 0); debugA : out unsigned(7 downto 0); debugX : out unsigned(7 downto 0); debugY : out unsigned(7 downto 0); debugS : out unsigned(7 downto 0); debug_flags : out unsigned(7 downto 0) ); end component; signal CPU_ENABLE: std_logic; -- Apply Antic HALT and throttle -- Support for Peter's core (NMI patch applied) signal debugOpcode : unsigned(7 downto 0); signal debugPc : unsigned(15 downto 0); signal debugA : unsigned(7 downto 0); signal debugX : unsigned(7 downto 0); signal debugY : unsigned(7 downto 0); signal debugS : unsigned(7 downto 0); signal di_unsigned : unsigned(7 downto 0); signal do_unsigned : unsigned(7 downto 0); signal addr_unsigned : unsigned(15 downto 0); signal CPU_ENABLE_RDY : std_logic; -- it has not RDY line signal WE : std_logic; signal nmi_pending_next : std_logic; -- NMI during RDY signal nmi_pending_reg : std_logic; signal nmi_n_adjusted : std_logic; signal nmi_n_reg : std_logic; signal nmi_edge : std_logic; signal CPU_ENABLE_RESET : std_logic; signal not_rdy : std_logic; BEGIN CPU_ENABLE <= ENABLE and memory_ready and THROTTLE; -- CPU designed by Peter W - as used in Chameleon di_unsigned <= unsigned(di); cpu_6502_peter:cpu_65xx generic map ( pipelineOpcode => false, pipelineAluMux => false, pipelineAluOut => false ) port map ( clk => clk, enable => CPU_ENABLE_RDY, halt => '0', reset=>reset, nmi_n=>nmi_n_adjusted, irq_n=>irq_n, d=>di_unsigned, q=>do_unsigned, addr=>addr_unsigned, WE=>WE, debugOpcode => debugOpcode, debugPc => debugPc, debugA => debugA, debugX => debugX, debugY => debugY, debugS => debugS ); CPU_ENABLE_RDY <= (CPU_ENABLE and (rdy or we)) or reset; CPU_ENABLE_RESET <= CPU_ENABLE or reset; not_rdy <= not(rdy); nmi_edge <= not(nmi_n) and nmi_n_reg; nmi_pending_next <= (nmi_edge and not(rdy or we)) or (nmi_pending_reg and not(rdy)) or (nmi_pending_reg and rdy and not(cpu_enable)); nmi_n_adjusted <= not(nmi_pending_reg) and nmi_n; -- register process(clk,reset) begin if (RESET = '1') then nmi_pending_reg <= '0'; nmi_n_reg <= '1'; elsif (clk'event and clk='1') then nmi_pending_reg <= nmi_pending_next; nmi_n_reg <= nmi_n; end if; end process; -- outputs r_w_n <= not(we); do <= std_logic_vector(do_unsigned); a <= std_logic_vector(addr_unsigned); CPU_FETCH <= ENABLE and THROTTLE; END vhdl;
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; ENTITY osc_handler IS PORT( CLK : in std_logic; RESET : in std_logic; NOTE_ON_OSC : in std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on) NOTE_OFF_OSC : in std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on) NOTE0, NOTE1 : out std_logic_vector(7 downto 0); ENABLE0, ENABLE1 : out std_logic ); END osc_handler; ARCHITECTURE behav of osc_handler is signal osc_case : std_logic := '0'; signal aNOTE0, aNOTE1 : std_logic_vector(7 downto 0); signal OLD_NOTE : std_logic_vector(7 downto 0) := (others => '0'); --Note ON/OFF 0x80(off), 0xFF(on) BEGIN process(CLK, RESET) variable flag : std_logic := '0'; begin if reset = '0' then NOTE0 <= (others => '0'); NOTE1 <= (others => '0'); osc_case <= '0'; aNOTE0 <= (others => '0'); aNOTE1 <= (others => '0'); ENABLE0 <= '0'; ENABLE1 <= '0'; elsif rising_edge(clk) then OLD_NOTE <= NOTE_ON_OSC; if NOTE_ON_OSC /= OLD_NOTE then flag := '1'; else flag := '0'; end if; if flag = '1' then case(osc_case) is when '0' => aNOTE0 <= NOTE_ON_OSC; osc_case <= NOT osc_case; when '1' => aNOTE1 <= NOTE_ON_OSC; osc_case <= NOT osc_case; when others => --DO NOTHING end case; end if; if NOTE_OFF_OSC = aNOTE0 then ENABLE0 <= '0'; else NOTE0 <= aNOTE0; ENABLE0 <= '1'; end if; if NOTE_OFF_OSC = aNOTE1 then ENABLE1 <= '0'; else NOTE1 <= aNOTE1; ENABLE1 <= '1'; end if; end if; end process; END behav;
-- -- Package File Template -- -- Purpose: This package defines supplemental types, subtypes, -- constants, and functions -- -- To use any of the example code shown below, uncomment the lines and modify as necessary -- -- -- -- -- How to use? --note this line.The package is compiled to this directory by default. --so don't forget to include this directory. --library work; --this line also is must.This includes the particular package into your program. --use work.test_pkg.all; -- -- -- -- ---------------------------------------------------------------------------------------------------- -- LIBRARIES ---------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; ---------------------------------------------------------------------------------------------------- -- PACKGE ---------------------------------------------------------------------------------------------------- package types is type bus002 is array(natural range <>) of std_logic_vector( 1 downto 0); type bus004 is array(natural range <>) of std_logic_vector( 3 downto 0); type bus005 is array(natural range <>) of std_logic_vector( 4 downto 0); type bus006 is array(natural range <>) of std_logic_vector( 5 downto 0); type bus007 is array(natural range <>) of std_logic_vector( 6 downto 0); type bus008 is array(natural range <>) of std_logic_vector( 7 downto 0); type bus009 is array(natural range <>) of std_logic_vector( 8 downto 0); type bus010 is array(natural range <>) of std_logic_vector( 9 downto 0); type bus011 is array(natural range <>) of std_logic_vector( 10 downto 0); type bus012 is array(natural range <>) of std_logic_vector( 11 downto 0); type bus013 is array(natural range <>) of std_logic_vector( 12 downto 0); type bus014 is array(natural range <>) of std_logic_vector( 13 downto 0); type bus015 is array(natural range <>) of std_logic_vector( 14 downto 0); type bus016 is array(natural range <>) of std_logic_vector( 15 downto 0); type bus017 is array(natural range <>) of std_logic_vector( 16 downto 0); type bus018 is array(natural range <>) of std_logic_vector( 17 downto 0); type bus019 is array(natural range <>) of std_logic_vector( 18 downto 0); type bus020 is array(natural range <>) of std_logic_vector( 19 downto 0); type bus021 is array(natural range <>) of std_logic_vector( 20 downto 0); type bus022 is array(natural range <>) of std_logic_vector( 21 downto 0); type bus023 is array(natural range <>) of std_logic_vector( 22 downto 0); type bus024 is array(natural range <>) of std_logic_vector( 23 downto 0); type bus025 is array(natural range <>) of std_logic_vector( 24 downto 0); type bus026 is array(natural range <>) of std_logic_vector( 25 downto 0); type bus027 is array(natural range <>) of std_logic_vector( 26 downto 0); type bus028 is array(natural range <>) of std_logic_vector( 27 downto 0); type bus029 is array(natural range <>) of std_logic_vector( 28 downto 0); type bus030 is array(natural range <>) of std_logic_vector( 29 downto 0); type bus031 is array(natural range <>) of std_logic_vector( 30 downto 0); type bus032 is array(natural range <>) of std_logic_vector( 31 downto 0); type bus064 is array(natural range <>) of std_logic_vector( 63 downto 0); type bus128 is array(natural range <>) of std_logic_vector(127 downto 0); type bus256 is array(natural range <>) of std_logic_vector(255 downto 0); -- type <new_type> is -- record -- <type_name> : std_logic_vector( 7 downto 0); -- <type_name> : std_logic; -- end record; -- -- Declare constants -- -- constant <constant_name> : time := <time_unit> ns; -- constant <constant_name> : integer := <value; -- -- Declare functions and procedure -- -- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>; -- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>); -- --*************************************************************************************************** end types; --*************************************************************************************************** ---------------------------------------------------------------------------------------------------- -- PACKGE BODY ---------------------------------------------------------------------------------------------------- package body types is function reverse_any_vector (a: in std_logic_vector) return std_logic_vector is variable result: std_logic_vector(a'RANGE); alias aa: std_logic_vector(a'REVERSE_RANGE) is a; begin for i in aa'RANGE loop result(i) := aa(i); end loop; return result; end; ---- Example 1 -- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is -- variable <variable_name> : <type_declaration>; -- begin -- <variable_name> := <signal_name> xor <signal_name>; -- return <variable_name>; -- end <function_name>; ---- Example 2 -- function <function_name> (signal <signal_name> : in <type_declaration>; -- signal <signal_name> : in <type_declaration> ) return <type_declaration> is -- begin -- if (<signal_name> = '1') then -- return <signal_name>; -- else -- return 'Z'; -- end if; -- end <function_name>; ---- Procedure Example -- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is -- -- begin -- -- end <procedure_name>; --************************************************************************************************** end types; --***************************************************************************************************
-- $Id: nexys4d_dram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2018- by Walter F.J. Mueller <[email protected]> -- ------------------------------------------------------------------------------ -- Module Name: nexys4d_dram_dummy - syn -- Description: nexys4d target (base; serport loopback, dram project) -- -- Dependencies: - -- To test: tb_nexys4d_dram -- Target Devices: generic -- Tool versions: viv 2017.2; ghdl 0.34 -- -- Revision History: -- Date Rev Version Comment -- 2018-12-30 1099 1.0 Initial version (derived from nexys4_dummy) ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use work.slvtypes.all; entity nexys4d_dram_dummy is -- NEXYS 4DDR dummy (base+dram) -- implements nexys4d_dram_aif port ( I_CLK100 : in slbit; -- 100 MHz board clock I_RXD : in slbit; -- receive data (board view) O_TXD : out slbit; -- transmit data (board view) O_RTS_N : out slbit; -- rx rts (board view; act.low) I_CTS_N : in slbit; -- tx cts (board view; act.low) I_SWI : in slv16; -- n4d switches I_BTN : in slv5; -- n4d buttons I_BTNRST_N : in slbit; -- n4d reset button O_LED : out slv16; -- n4d leds O_RGBLED0 : out slv3; -- n4d rgb-led 0 O_RGBLED1 : out slv3; -- n4d rgb-led 1 O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) DDR2_DQ : inout slv16; -- dram: data in/out DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p) DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n) DDR2_ADDR : out slv13; -- dram: address DDR2_BA : out slv3; -- dram: bank address DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low) DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low) DDR2_WE_N : out slbit; -- dram: write enable (act.low) DDR2_CK_P : out slv1; -- dram: clock (diff-p) DDR2_CK_N : out slv1; -- dram: clock (diff-n) DDR2_CKE : out slv1; -- dram: clock enable DDR2_CS_N : out slv1; -- dram: chip select (act.low) DDR2_DM : out slv2; -- dram: data input mask DDR2_ODT : out slv1 -- dram: on-die termination ); end nexys4d_dram_dummy; architecture syn of nexys4d_dram_dummy is begin O_TXD <= I_RXD; -- loop back serport O_RTS_N <= I_CTS_N; O_LED <= I_SWI; -- mirror SWI on LED O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3); O_ANO_N <= (others=>'1'); O_SEG_N <= (others=>'1'); DDR2_DQ <= (others=>'Z'); DDR2_DQS_P <= (others=>'Z'); DDR2_DQS_N <= (others=>'Z'); DDR2_ADDR <= (others=>'0'); DDR2_BA <= (others=>'0'); DDR2_RAS_N <= '1'; DDR2_CAS_N <= '1'; DDR2_WE_N <= '1'; DDR2_CK_P <= (others=>'0'); DDR2_CK_N <= (others=>'1'); DDR2_CKE <= (others=>'0'); DDR2_CS_N <= (others=>'1'); DDR2_DM <= (others=>'0'); DDR2_ODT <= (others=>'0'); end syn;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity aurora_ctrl is port ( pwdn_in : in std_logic ; user_clk : in std_logic ; dcm_not_locked : out std_logic; loopback : out std_logic_vector(1 downto 0); power_down : out std_logic; nfc_req_1 : out std_logic ; nfc_nb : out std_logic_vector(3 downto 0) ); end aurora_ctrl; architecture aurora_ctrl_b1 of aurora_ctrl is signal pwdn_reg : std_logic_vector(1 downto 0); begin dcm_not_locked <= '0'; loopback <= "00"; process(user_clk) begin if user_clk = '1' and user_clk'event then pwdn_reg <= pwdn_reg(0)&pwdn_in; end if; end process; -- power_down <= pwdn_reg(1); power_down <= '0'; -- Native Flow Control Interface nfc_req_1 <= '1'; nfc_nb <= "0000"; end aurora_ctrl_b1;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity aurora_ctrl is port ( pwdn_in : in std_logic ; user_clk : in std_logic ; dcm_not_locked : out std_logic; loopback : out std_logic_vector(1 downto 0); power_down : out std_logic; nfc_req_1 : out std_logic ; nfc_nb : out std_logic_vector(3 downto 0) ); end aurora_ctrl; architecture aurora_ctrl_b1 of aurora_ctrl is signal pwdn_reg : std_logic_vector(1 downto 0); begin dcm_not_locked <= '0'; loopback <= "00"; process(user_clk) begin if user_clk = '1' and user_clk'event then pwdn_reg <= pwdn_reg(0)&pwdn_in; end if; end process; -- power_down <= pwdn_reg(1); power_down <= '0'; -- Native Flow Control Interface nfc_req_1 <= '1'; nfc_nb <= "0000"; end aurora_ctrl_b1;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1574.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s10b00x00p04n01i01574ent IS END c08s10b00x00p04n01i01574ent; ARCHITECTURE c08s10b00x00p04n01i01574arch OF c08s10b00x00p04n01i01574ent IS BEGIN TESTING: PROCESS variable k : integer := 0; BEGIN L : for i in 1 to 10 loop next L when i > 5; k := k + 1; end loop; assert NOT( k=5 ) report "***PASSED TEST: c08s10b00x00p04n01i01574" severity NOTE; assert ( k=5 ) report "***FAILED TEST: c08s10b00x00p04n01i01574 - The current iteration of the loop is terminated if the value of the condition is TRUE" severity ERROR; wait; END PROCESS TESTING; END c08s10b00x00p04n01i01574arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1574.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s10b00x00p04n01i01574ent IS END c08s10b00x00p04n01i01574ent; ARCHITECTURE c08s10b00x00p04n01i01574arch OF c08s10b00x00p04n01i01574ent IS BEGIN TESTING: PROCESS variable k : integer := 0; BEGIN L : for i in 1 to 10 loop next L when i > 5; k := k + 1; end loop; assert NOT( k=5 ) report "***PASSED TEST: c08s10b00x00p04n01i01574" severity NOTE; assert ( k=5 ) report "***FAILED TEST: c08s10b00x00p04n01i01574 - The current iteration of the loop is terminated if the value of the condition is TRUE" severity ERROR; wait; END PROCESS TESTING; END c08s10b00x00p04n01i01574arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1574.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s10b00x00p04n01i01574ent IS END c08s10b00x00p04n01i01574ent; ARCHITECTURE c08s10b00x00p04n01i01574arch OF c08s10b00x00p04n01i01574ent IS BEGIN TESTING: PROCESS variable k : integer := 0; BEGIN L : for i in 1 to 10 loop next L when i > 5; k := k + 1; end loop; assert NOT( k=5 ) report "***PASSED TEST: c08s10b00x00p04n01i01574" severity NOTE; assert ( k=5 ) report "***FAILED TEST: c08s10b00x00p04n01i01574 - The current iteration of the loop is terminated if the value of the condition is TRUE" severity ERROR; wait; END PROCESS TESTING; END c08s10b00x00p04n01i01574arch;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.math_real.all; entity bug is port ( dummy : in std_ulogic ); end entity; architecture rtl of bug is constant a : real := floor(15.0/4.0); constant b : real := ceil(15.0/4.0); begin end architecture;
-- File: dyplo_hdl_node.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an "as is", as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic's maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library dyplo_hdl_node_lib; use dyplo_hdl_node_lib.hdl_node_package.all; use dyplo_hdl_node_lib.hdl_node_user_params.all; library user_logic; use user_logic.all; entity dyplo_hdl_node is port( -- Miscellaneous node_id : in std_logic_vector(c_hdl_node_id_width - 1 downto 0); -- DAB interface dab_clk : in std_logic; dab_rst : in std_logic; dab_addr : in std_logic_vector(c_hdl_dab_awidth - 1 downto 0); dab_sel : in std_logic; dab_wvalid : in std_logic; dab_rvalid : in std_logic; dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); -- Receive data from backplane to FIFO b2f_tdata : in std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); b2f_tstream_id : in std_logic_vector(c_hdl_stream_id_width - 1 downto 0); b2f_tvalid : in std_logic; b2f_tready : out std_logic; -- Send data from FIFO to backplane f2b_tdata : out std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); f2b_tstream_id : out std_logic_vector(c_hdl_stream_id_width - 1 downto 0); f2b_tvalid : out std_logic; f2b_tready : in std_logic; -- Serial fifo status info fifo_status_sync : in std_logic; fifo_status_flag : out std_logic; -- fifo statuses of destination fifo's dest_fifo_status : in std_logic_vector(3 downto 0); -- Clock signals user_clocks : in std_logic_vector(3 downto 0) ); attribute secure_config : string; attribute secure_config of dyplo_hdl_node : entity is "PROTECT"; attribute secure_netlist : string; attribute secure_netlist of dyplo_hdl_node : entity is "ENCRYPT"; attribute secure_net_editing : string; attribute secure_net_editing of dyplo_hdl_node : entity is "PROHIBIT"; attribute secure_net_probing : string; attribute secure_net_probing of dyplo_hdl_node : entity is "PROHIBIT"; end dyplo_hdl_node; architecture rtl of dyplo_hdl_node is component dyplo_user_logic_adder is generic( INPUT_STREAMS : integer := 4; OUTPUT_STREAMS : integer := 4 ); port( -- Processor bus interface dab_clk : in std_logic; dab_rst : in std_logic; dab_addr : in std_logic_vector(15 downto 0); dab_sel : in std_logic; dab_wvalid : in std_logic; dab_rvalid : in std_logic; dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); -- Streaming input interfaces cin_tdata : in cin_tdata_ul_type; cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0); cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0); cin_tlevel : in cin_tlevel_ul_type; -- Streaming output interfaces cout_tdata : out cout_tdata_ul_type; cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0); cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0); -- Clock signals user_clocks : in std_logic_vector(3 downto 0) ); end component dyplo_user_logic_adder; signal dab_sel_ul : std_logic; signal dab_wvalid_ul : std_logic; signal dab_rvalid_ul : std_logic; signal dab_rdata_ul : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); signal cin_tdata_i : cin_tdata_ul_type; signal cin_tvalid_i : std_logic_vector(c_input_streams - 1 downto 0); signal cin_tready_i : std_logic_vector(c_input_streams - 1 downto 0); signal cin_tlevel_i : cin_tlevel_ul_type; signal cout_tdata_i : cout_tdata_ul_type; signal cout_tvalid_i : std_logic_vector(c_output_streams - 1 downto 0); signal cout_tready_i : std_logic_vector(c_output_streams - 1 downto 0); begin ----------------------------------------------------------------------------- -- CONTROL MEMORY MAP FOR CPU FIFO INTERFACE -- ----------------------------------------------------------------------------- -- The available memory range for the CPU fifo control is limited to -- -- 64Kbyte/32 = 2Kbytes or 512 words. The maximum burst transfer of the -- -- AXI bus is 256 words. The actual FIFO data memory range is also limited -- -- to 64Kbytes or 16Kwords. Also, the space is divided between reading and -- -- writing. This leaves 8Kwords per direction and with a burst length of -- -- 256 words, maximum 32 input streams and 32 output streams can be -- -- supported. -- ----------------------------------------------------------------------------- -- Each fifo has the following metrics: -- -- - FIFO full and FIFO empty flag -- -- - FIFO fill level compare register and compare flag -- -- - Actual FIFO fill level indicator -- -- - Under/overflow detection flag when operating FIFO out of range -- -- -- -- Per input FIFO (from FPGA fabric to the CPU) it is required to specify -- -- the stream source. Also, a maskable interrupt should be issued per -- -- input FIFO to signal the need to empty the FIFO by the CPU. -- ----------------------------------------------------------------------------- dyplo_hdl_node_logic_i : dyplo_hdl_node_logic generic map ( INPUT_STREAMS => c_input_streams, OUTPUT_STREAMS => c_output_streams ) port map( -- Miscellaneous node_id => node_id, -- DAB interface dab_clk => dab_clk, dab_rst => dab_rst, dab_addr => dab_addr, dab_sel => dab_sel, dab_wvalid => dab_wvalid, dab_rvalid => dab_rvalid, dab_wdata => dab_wdata, dab_rdata => dab_rdata, -- Receive data from backplane to FIFO b2f_tdata => b2f_tdata, b2f_tstream_id => b2f_tstream_id, b2f_tvalid => b2f_tvalid, b2f_tready => b2f_tready, -- Send data from FIFO to backplane f2b_tdata => f2b_tdata, f2b_tstream_id => f2b_tstream_id, f2b_tvalid => f2b_tvalid, f2b_tready => f2b_tready, -- Serial fifo status info fifo_status_sync => fifo_status_sync, fifo_status_flag => fifo_status_flag, -- fifo statuses of destination fifo's dest_fifo_status => dest_fifo_status(c_output_streams - 1 downto 0), -- DAB interface to user logic dab_sel_ul => dab_sel_ul, dab_wvalid_ul => dab_wvalid_ul, dab_rvalid_ul => dab_rvalid_ul, dab_rdata_ul => dab_rdata_ul, -- In streams to user logic cin_tdata_ul => cin_tdata_i, cin_tvalid_ul => cin_tvalid_i, cin_tready_ul => cin_tready_i, cin_tlevel_ul => cin_tlevel_i, -- Out streams from user logic cout_tdata_ul => cout_tdata_i, cout_tvalid_ul => cout_tvalid_i, cout_tready_ul => cout_tready_i ); dyplo_user_logic_i : dyplo_user_logic_adder generic map( INPUT_STREAMS => c_input_streams, OUTPUT_STREAMS => c_output_streams ) port map( -- Processor bus interface dab_clk => dab_clk, dab_rst => dab_rst, dab_addr => dab_addr(15 downto 0), dab_sel => dab_sel_ul, dab_wvalid => dab_wvalid_ul, dab_rvalid => dab_rvalid_ul, dab_wdata => dab_wdata, dab_rdata => dab_rdata_ul, -- Streaming input interfaces cin_tdata => cin_tdata_i, cin_tvalid => cin_tvalid_i, cin_tready => cin_tready_i, cin_tlevel => cin_tlevel_i, -- Streaming output interfaces cout_tdata => cout_tdata_i, cout_tvalid => cout_tvalid_i, cout_tready => cout_tready_i, -- Clock signals user_clocks => user_clocks ); end rtl;
-- Copyright (c) 2011-2014, Ailamazyan Program Systems Institute (Russian -- Academy of Science). See COPYING in top-level directory. configuration emu_top_cfg of emu_top256 is for emu_top256 for app : ast_io use entity work.wrap_emu; end for; end for; end;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc382.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x01p04n01i00382ent IS END c03s02b01x01p04n01i00382ent; ARCHITECTURE c03s02b01x01p04n01i00382arch OF c03s02b01x01p04n01i00382ent IS type days is (sun, mon, tue, wed, thu, fri, sat); type bit_vctor is array (days range mon to fri) of integer; BEGIN TESTING: PROCESS variable k : bit_vctor; BEGIN k(mon) := 1; k(tue) := 2; k(wed) := 3; k(thu) := 4; k(fri) := 5; assert NOT ( k(mon) = 1 and k(tue) = 2 and k(wed) = 3 and k(thu) = 4 and k(fri) = 5 ) report "***PASSED TEST: c03s02b01x01p04n01i00382" severity NOTE; assert ( k(mon) = 1 and k(tue) = 2 and k(wed) = 3 and k(thu) = 4 and k(fri) = 5 ) report "***FAILED TEST: c03s02b01x01p04n01i00382 - An index constraint is compatible with the type denoted by the type mark if and only if the constraint defined by each discrete range is compatible with the corresponding subtype." severity ERROR; wait; END PROCESS TESTING; END c03s02b01x01p04n01i00382arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc382.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x01p04n01i00382ent IS END c03s02b01x01p04n01i00382ent; ARCHITECTURE c03s02b01x01p04n01i00382arch OF c03s02b01x01p04n01i00382ent IS type days is (sun, mon, tue, wed, thu, fri, sat); type bit_vctor is array (days range mon to fri) of integer; BEGIN TESTING: PROCESS variable k : bit_vctor; BEGIN k(mon) := 1; k(tue) := 2; k(wed) := 3; k(thu) := 4; k(fri) := 5; assert NOT ( k(mon) = 1 and k(tue) = 2 and k(wed) = 3 and k(thu) = 4 and k(fri) = 5 ) report "***PASSED TEST: c03s02b01x01p04n01i00382" severity NOTE; assert ( k(mon) = 1 and k(tue) = 2 and k(wed) = 3 and k(thu) = 4 and k(fri) = 5 ) report "***FAILED TEST: c03s02b01x01p04n01i00382 - An index constraint is compatible with the type denoted by the type mark if and only if the constraint defined by each discrete range is compatible with the corresponding subtype." severity ERROR; wait; END PROCESS TESTING; END c03s02b01x01p04n01i00382arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc382.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x01p04n01i00382ent IS END c03s02b01x01p04n01i00382ent; ARCHITECTURE c03s02b01x01p04n01i00382arch OF c03s02b01x01p04n01i00382ent IS type days is (sun, mon, tue, wed, thu, fri, sat); type bit_vctor is array (days range mon to fri) of integer; BEGIN TESTING: PROCESS variable k : bit_vctor; BEGIN k(mon) := 1; k(tue) := 2; k(wed) := 3; k(thu) := 4; k(fri) := 5; assert NOT ( k(mon) = 1 and k(tue) = 2 and k(wed) = 3 and k(thu) = 4 and k(fri) = 5 ) report "***PASSED TEST: c03s02b01x01p04n01i00382" severity NOTE; assert ( k(mon) = 1 and k(tue) = 2 and k(wed) = 3 and k(thu) = 4 and k(fri) = 5 ) report "***FAILED TEST: c03s02b01x01p04n01i00382 - An index constraint is compatible with the type denoted by the type mark if and only if the constraint defined by each discrete range is compatible with the corresponding subtype." severity ERROR; wait; END PROCESS TESTING; END c03s02b01x01p04n01i00382arch;
-- Descp. counts the number of color matches -- -- entity name: g05_color_matches -- -- Version 1.0 -- Author: Felix Dube; [email protected] & Auguste Lalande; [email protected] -- Date: October 15, 2015 library ieee; use ieee.std_logic_1164.all; library lpm; use lpm.lpm_components.all; entity g05_color_matches is port ( P1, P2, P3, P4 : in std_logic_vector(2 downto 0); G1, G2, G3, G4 : in std_logic_vector(2 downto 0); num_exact_matches : out std_logic_vector(2 downto 0); num_color_matches : out std_logic_vector(2 downto 0) ); end g05_color_matches; architecture behavior of g05_color_matches is component g05_minimum3 is port ( N, M : in std_logic_vector(2 downto 0); min : out std_logic_vector(2 downto 0) ); end component; component g05_num1s is port ( X : in std_logic_vector(3 downto 0); num1s : out std_logic_vector(2 downto 0) ); end component; component g05_num_matches is port ( P1, P2, P3, P4 : in std_logic_vector(2 downto 0); G1, G2, G3, G4 : in std_logic_vector(2 downto 0); N : out std_logic_vector(2 downto 0) ); end component; signal EQ_P1, EQ_P2, EQ_P3, EQ_P4 : std_logic_vector(7 downto 0); signal EQ_G1, EQ_G2, EQ_G3, EQ_G4 : std_logic_vector(7 downto 0); signal P_C0, P_C1, P_C2, P_C3, P_C4, P_C5 : std_logic_vector(2 downto 0); signal G_C0, G_C1, G_C2, G_C3, G_C4, G_C5 : std_logic_vector(2 downto 0); signal M_C0, M_C1, M_C2, M_C3, M_C4, M_C5 : std_logic_vector(2 downto 0); signal color_matches_all : std_logic_vector(2 downto 0); signal add1, add2, add3, add4 : std_logic_vector(2 downto 0); signal num_matches : std_logic_vector(2 downto 0); begin --decode patern colors lpm_decode_P1 : lpm_decode generic map (lpm_width => 3, lpm_decodes => 8) port map (data => P1, eq => EQ_P1); lpm_decode_P2 : lpm_decode generic map (lpm_width => 3, lpm_decodes => 8) port map (data => P2, eq => EQ_P2); lpm_decode_P3 : lpm_decode generic map (lpm_width => 3, lpm_decodes => 8) port map (data => P3, eq => EQ_P3); lpm_decode_P4 : lpm_decode generic map (lpm_width => 3, lpm_decodes => 8) port map (data => P4, eq => EQ_P4); --count the number of each color in the pattern num1s_P_C0 : g05_num1s port map (X(0) => EQ_P1(0), X(1) => EQ_P2(0), X(2) => EQ_P3(0), X(3) => EQ_P4(0), num1s => P_C0); num1s_P_C1 : g05_num1s port map (X(0) => EQ_P1(1), X(1) => EQ_P2(1), X(2) => EQ_P3(1), X(3) => EQ_P4(1), num1s => P_C1); num1s_P_C2 : g05_num1s port map (X(0) => EQ_P1(2), X(1) => EQ_P2(2), X(2) => EQ_P3(2), X(3) => EQ_P4(2), num1s => P_C2); num1s_P_C3 : g05_num1s port map (X(0) => EQ_P1(3), X(1) => EQ_P2(3), X(2) => EQ_P3(3), X(3) => EQ_P4(3), num1s => P_C3); num1s_P_C4 : g05_num1s port map (X(0) => EQ_P1(4), X(1) => EQ_P2(4), X(2) => EQ_P3(4), X(3) => EQ_P4(4), num1s => P_C4); num1s_P_C5 : g05_num1s port map (X(0) => EQ_P1(5), X(1) => EQ_P2(5), X(2) => EQ_P3(5), X(3) => EQ_P4(5), num1s => P_C5); --decode guess colors lpm_decode_G1 : lpm_decode generic map (lpm_width => 3, lpm_decodes => 8) port map (data => G1, eq => EQ_G1); lpm_decode_G2 : lpm_decode generic map (lpm_width => 3, lpm_decodes => 8) port map (data => G2, eq => EQ_G2); lpm_decode_G3 : lpm_decode generic map (lpm_width => 3, lpm_decodes => 8) port map (data => G3, eq => EQ_G3); lpm_decode_G4 : lpm_decode generic map (lpm_width => 3, lpm_decodes => 8) port map (data => G4, eq => EQ_G4); --count the number of each color in the guess num1s_G_C0 : g05_num1s port map (X(0) => EQ_G1(0), X(1) => EQ_G2(0), X(2) => EQ_G3(0), X(3) => EQ_G4(0), num1s => G_C0); num1s_G_C1 : g05_num1s port map (X(0) => EQ_G1(1), X(1) => EQ_G2(1), X(2) => EQ_G3(1), X(3) => EQ_G4(1), num1s => G_C1); num1s_G_C2 : g05_num1s port map (X(0) => EQ_G1(2), X(1) => EQ_G2(2), X(2) => EQ_G3(2), X(3) => EQ_G4(2), num1s => G_C2); num1s_G_C3 : g05_num1s port map (X(0) => EQ_G1(3), X(1) => EQ_G2(3), X(2) => EQ_G3(3), X(3) => EQ_G4(3), num1s => G_C3); num1s_G_C4 : g05_num1s port map (X(0) => EQ_G1(4), X(1) => EQ_G2(4), X(2) => EQ_G3(4), X(3) => EQ_G4(4), num1s => G_C4); num1s_G_C5 : g05_num1s port map (X(0) => EQ_G1(5), X(1) => EQ_G2(5), X(2) => EQ_G3(5), X(3) => EQ_G4(5), num1s => G_C5); --count the number of times each color is in both the pattern and the guess min3_C0 : g05_minimum3 port map (M => P_C0, N => G_C0, min => M_C0); min3_C1 : g05_minimum3 port map (M => P_C1, N => G_C1, min => M_C1); min3_C2 : g05_minimum3 port map (M => P_C2, N => G_C2, min => M_C2); min3_C3 : g05_minimum3 port map (M => P_C3, N => G_C3, min => M_C3); min3_C4 : g05_minimum3 port map (M => P_C4, N => G_C4, min => M_C4); min3_C5 : g05_minimum3 port map (M => P_C5, N => G_C5, min => M_C5); --find the number of color matches which also include exact matches sum_1: lpm_add_sub generic map (lpm_width => 3) port map (dataa => M_C0, datab => M_C1, result => add1, add_sub => '1'); sum_2: lpm_add_sub generic map (lpm_width => 3) port map (dataa => add1, datab => M_C2, result => add2, add_sub => '1'); sum_3: lpm_add_sub generic map (lpm_width => 3) port map (dataa => add2, datab => M_C3, result => add3, add_sub => '1'); sum_4: lpm_add_sub generic map (lpm_width => 3) port map (dataa => add3, datab => M_C4, result => add4, add_sub => '1'); sum_5: lpm_add_sub generic map (lpm_width => 3) port map (dataa => add4, datab => M_C5, result => color_matches_all, add_sub => '1'); --find the exact matches num_matches_exact : g05_num_matches port map (P1 => P1, P2 => P2, P3 => P3, P4 => P4, G1 => G1, G2 => G2, G3 => G3, G4 => G4, N => num_matches); --find the number of color matches excluding the exact matches color_matches : lpm_add_sub generic map (lpm_width => 3) port map (dataa => color_matches_all, datab => num_matches, result => num_color_matches, add_sub => '0'); num_exact_matches <= num_matches; end behavior;
--! @file strobed_trig_table_tb.vhd --! @brief Data strobed sin/cos lookup table generator testbench --! @author Scott Teal ([email protected]) --! @date 2013-11-19 --! @copyright --! Copyright 2013 Richard Scott Teal, Jr. --! --! Licensed under the Apache License, Version 2.0 (the "License"); you may not --! use this file except in compliance with the License. You may obtain a copy --! of the License at --! --! http://www.apache.org/licenses/LICENSE-2.0 --! --! Unless required by applicable law or agreed to in writing, software --! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT --! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the --! License for the specific language governing permissions and limitations --! under the License. --! Standard IEEE library library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; use ieee.fixed_float_types.all; library boostdsp; use boostdsp.fixed_pkg.all; use boostdsp.util_pkg.all; use boostdsp.basic_pkg; --! Tests the boostdsp.strobed_trig_table entity. --! @TODO Use sfixed_as_signed to get vis_sine & vis_cosine. entity strobed_trig_table_tb is end entity; --! Tests the boostdsp.trig_table entity by running through all possible angle --! values. architecture sim of strobed_trig_table_tb is constant clk_p : time := 2 ns; --! Clock period constant clk_hp : time := clk_p / 2; --! 1/2 clock period signal clk : std_logic := '0'; --! Clock for UUT signal rst : std_logic := '1'; --! Reset for UUT signal angle : ufixed(-1 downto -9) := to_ufixed(0.0, -1, -9); --! Input angle signal strobe_in : std_logic := '0'; --! Data strobe into table signal sine : sfixed(1 downto -6); --! Sine output signal cosine : sfixed(1 downto -6); --! Cosine output signal strobe_out : std_logic; --! Data strobe from table signal vis_sine : signed(7 downto 0); --! Visualize output in Modelsim signal vis_cosine : signed(7 downto 0); --! Visualize output in Modelsim constant angle_lsb : real := 2.0**(angle'low); --! LSB of angle counter begin --! Trigometric Table Unit Under Test uut : basic_pkg.strobed_trig_table port map ( clk => clk, rst => rst, angle => angle, strobe_in => strobe_in, sine => sine, cosine => cosine, strobe_out => strobe_out ); --! Clock generator clk_proc : process begin wait for clk_hp; clk <= not clk; end process; --! Reset generator rst_proc : process begin wait for clk_p * 4; rst <= '0'; wait; end process; --! Incremeting angle through entire range test_input : process begin wait for clk_p; angle <= resize(angle + to_ufixed(angle_lsb,angle), angle'high, angle'low, fixed_wrap, fixed_truncate); strobe_in <= '1'; wait for clk_p; strobe_in <= '0'; end process; --! Visualize sine output vis_sine <= sfixed_as_signed(sine); --! Visualize cosine output vis_cosine <= sfixed_as_signed(cosine); end sim;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1403.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p06n01i01403ent IS END c08s05b00x00p06n01i01403ent; ARCHITECTURE c08s05b00x00p06n01i01403arch OF c08s05b00x00p06n01i01403ent IS BEGIN TESTING: PROCESS variable T : INTEGER := 1; subtype ST is BIT_VECTOR(T to 10); variable OK : BIT_VECTOR(T+1 to 11); variable ILL : BIT_VECTOR(T to 11); variable V : ST; BEGIN V := OK; assert NOT(V = "0000000000") report "***PASSED TEST: c08s05b00x00p06n01i01403" severity NOTE; assert (V = "0000000000") report "***FAILED TEST: c08s05b00x00p06n01i01403 - Variable assignment scalar subtype check test failed." severity ERROR; wait; END PROCESS TESTING; END c08s05b00x00p06n01i01403arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1403.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p06n01i01403ent IS END c08s05b00x00p06n01i01403ent; ARCHITECTURE c08s05b00x00p06n01i01403arch OF c08s05b00x00p06n01i01403ent IS BEGIN TESTING: PROCESS variable T : INTEGER := 1; subtype ST is BIT_VECTOR(T to 10); variable OK : BIT_VECTOR(T+1 to 11); variable ILL : BIT_VECTOR(T to 11); variable V : ST; BEGIN V := OK; assert NOT(V = "0000000000") report "***PASSED TEST: c08s05b00x00p06n01i01403" severity NOTE; assert (V = "0000000000") report "***FAILED TEST: c08s05b00x00p06n01i01403 - Variable assignment scalar subtype check test failed." severity ERROR; wait; END PROCESS TESTING; END c08s05b00x00p06n01i01403arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1403.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p06n01i01403ent IS END c08s05b00x00p06n01i01403ent; ARCHITECTURE c08s05b00x00p06n01i01403arch OF c08s05b00x00p06n01i01403ent IS BEGIN TESTING: PROCESS variable T : INTEGER := 1; subtype ST is BIT_VECTOR(T to 10); variable OK : BIT_VECTOR(T+1 to 11); variable ILL : BIT_VECTOR(T to 11); variable V : ST; BEGIN V := OK; assert NOT(V = "0000000000") report "***PASSED TEST: c08s05b00x00p06n01i01403" severity NOTE; assert (V = "0000000000") report "***FAILED TEST: c08s05b00x00p06n01i01403 - Variable assignment scalar subtype check test failed." severity ERROR; wait; END PROCESS TESTING; END c08s05b00x00p06n01i01403arch;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: grpci2_gen -- File: grpci2_gen.vhd -- Author: Nils-Johan Wessman - Aeroflex Gaisler -- Description: Std_logic wrapper for GRPCI2 ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library grlib; use grlib.amba.all; --use grlib.stdlib.all; --use grlib.devices.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.pci.all; entity grpci2_gen is generic ( memtech : integer := DEFMEMTECH; tbmemtech : integer := DEFMEMTECH; -- For trace buffers oepol : integer := 0; hmask : integer := 0; -- Need to set according to the size of the decoded AHB address range irqmode : integer range 0 to 3 := 0; master : integer range 0 to 1 := 1; target : integer range 0 to 1 := 1; dma : integer range 0 to 1 := 1; tracebuffer : integer range 0 to 16384 := 0; confspace : integer range 0 to 1 := 1; vendorid : integer := 16#0000#; deviceid : integer := 16#0000#; classcode : integer := 16#000000#; revisionid : integer := 16#00#; cap_pointer : integer := 16#40#; ext_cap_pointer : integer := 16#00#; iobase : integer := 16#FFF#; extcfg : integer := 16#0000000#; bar0 : integer range 0 to 31 := 28; bar1 : integer range 0 to 31 := 0; bar2 : integer range 0 to 31 := 0; bar3 : integer range 0 to 31 := 0; bar4 : integer range 0 to 31 := 0; bar5 : integer range 0 to 31 := 0; bar0_map : integer := 16#000000#; bar1_map : integer := 16#000000#; bar2_map : integer := 16#000000#; bar3_map : integer := 16#000000#; bar4_map : integer := 16#000000#; bar5_map : integer := 16#000000#; bartype : integer range 0 to 65535 := 16#0000#; barminsize : integer range 5 to 31 := 12; fifo_depth : integer range 3 to 7 := 3; fifo_count : integer range 2 to 4 := 2; conv_endian : integer range 0 to 1 := 1; -- 1: little (PCI) <~> big (AHB), 0: big (PCI) <=> big (AHB) deviceirq : integer range 0 to 1 := 1; deviceirqmask : integer range 0 to 15 := 16#0#; hostirq : integer range 0 to 1 := 1; hostirqmask : integer range 0 to 15 := 16#0#; nsync : integer range 0 to 2 := 2; -- with nsync = 0, wrfst needed on syncram... hostrst : integer range 0 to 2 := 0;-- 0: PCI reset is never driven, 1: PCI reset is driven from AHB reset if host, 2: PCI reset is always driven from AHB reset bypass : integer range 0 to 1 := 1; ft : integer range 0 to 1 := 0; scantest : integer range 0 to 1 := 0; debug : integer range 0 to 1 := 0; tbapben : integer range 0 to 1 := 0; netlist : integer range 0 to 1 := 0; -- Use PHY netlist multifunc : integer range 0 to 1 := 0; -- Enables Multi-function support multiint : integer range 0 to 1 := 0; masters : integer := 16#FFFF#; mf1_deviceid : integer := 16#0000#; mf1_classcode : integer := 16#000000#; mf1_revisionid : integer := 16#00#; mf1_bar0 : integer range 0 to 31 := 0; mf1_bar1 : integer range 0 to 31 := 0; mf1_bar2 : integer range 0 to 31 := 0; mf1_bar3 : integer range 0 to 31 := 0; mf1_bar4 : integer range 0 to 31 := 0; mf1_bar5 : integer range 0 to 31 := 0; mf1_bartype : integer range 0 to 65535 := 16#0000#; mf1_bar0_map : integer := 16#000000#; mf1_bar1_map : integer := 16#000000#; mf1_bar2_map : integer := 16#000000#; mf1_bar3_map : integer := 16#000000#; mf1_bar4_map : integer := 16#000000#; mf1_bar5_map : integer := 16#000000#; mf1_cap_pointer : integer := 16#40#; mf1_ext_cap_pointer : integer := 16#00#; mf1_extcfg : integer := 16#0000000#; mf1_masters : integer := 16#0000# ); port( rst : in std_logic; -- AMBA reset clk : in std_logic; -- AMBA clock pciclk : in std_logic; -- PCI clock -- dirq : in std_logic_vector(3 downto 0); -- From interrupt controller to PCI interrupt -- pci_rst_i : in std_logic; -- PCI reset in pci_rst_o : out std_logic; -- PCI reset out pci_gnt : in std_logic; -- PCI grant pci_req_o : out std_logic; -- PCI request out pci_req_oe : out std_logic; -- PCI request output enable pci_idsel : in std_logic; -- PCI IDSEL pci_ad_i : in std_logic_vector(31 downto 0); -- PCI AD in pci_ad_o : out std_logic_vector(31 downto 0); -- PCI AD out pci_ad_oe : out std_logic_vector(31 downto 0); -- PCI AD output enable pci_cbe_i : in std_logic_vector(3 downto 0); -- PCI CBE in pci_cbe_o : out std_logic_vector(3 downto 0); -- PCI CBE out pci_cbe_oe : out std_logic_vector(3 downto 0); -- PCI CBE output enable pci_frame_i : in std_logic; -- PCI FRAME in pci_frame_o : out std_logic; -- PCI FRAME out pci_frame_oe : out std_logic; -- PCI FRAME output enable pci_irdy_i : in std_logic; -- PCI IRDY in pci_irdy_o : out std_logic; -- PCI IRDY out pci_irdy_oe : out std_logic; -- PCI IRDY output enable pci_trdy_i : in std_logic; -- PCI TRDY in pci_trdy_o : out std_logic; -- PCI TRDY out pci_trdy_oe : out std_logic; -- PCI TRDY output enable pci_stop_i : in std_logic; -- PCI STOP in pci_stop_o : out std_logic; -- PCI STOP out pci_stop_oe : out std_logic; -- PCI STOP output enable pci_devsel_i : in std_logic; -- PCI DEVSEL in pci_devsel_o : out std_logic; -- PCI DEVSEL out pci_devsel_oe : out std_logic; -- PCI DEVSEL output enable pci_perr_i : in std_logic; -- PCI PERR in pci_perr_o : out std_logic; -- PCI PERR out pci_perr_oe : out std_logic; -- PCI PERR output enable pci_serr_i : in std_logic; -- PCI SERR in pci_serr_o : out std_logic; -- PCI SERR out pci_serr_oe : out std_logic; -- PCI SERR output enable pci_par_i : in std_logic; -- PCI PAR in pci_par_o : out std_logic; -- PCI PAR out pci_par_oe : out std_logic; -- PCI PAR output enable pci_int_i : in std_logic_vector(3 downto 0); -- PCI INT[D..A] in pci_int_oe : out std_logic_vector(3 downto 0); -- PCI INT[D..A] output enable pci_host : in std_logic; -- GRPCI2 specific, determine host/peripheral mode pci_pci66 : in std_logic; -- PCI M66EN -- apb_psel : in std_logic; -- slave select apb_penable : in std_ulogic; -- strobe apb_paddr : in std_logic_vector(31 downto 0); -- address bus (byte) apb_pwrite : in std_ulogic; -- write apb_pwdata : in std_logic_vector(31 downto 0); -- write data bus apb_prdata : out std_logic_vector(31 downto 0); -- read data bus -- apb_pirq : out std_logic_vector(4 downto 0); -- interrupt bus (GRLIB specific) -- ahbsi_hsel : in std_logic; -- slave select ahbsi_haddr : in std_logic_vector(31 downto 0); -- address bus (byte) ahbsi_hwrite : in std_ulogic; -- read/write ahbsi_htrans : in std_logic_vector(1 downto 0); -- transfer type ahbsi_hsize : in std_logic_vector(2 downto 0); -- transfer size ahbsi_hburst : in std_logic_vector(2 downto 0); -- burst type ahbsi_hwdata : in std_logic_vector(AHBDW-1 downto 0); -- write data bus ahbsi_hprot : in std_logic_vector(3 downto 0); -- protection control ahbsi_hready : in std_ulogic; -- transfer done ahbsi_hmaster : in std_logic_vector(3 downto 0); -- current master ahbsi_hmastlock : in std_ulogic; -- locked access -- ahbsi_hmbsel : in std_logic_vector(0 to NAHBAMR-1); -- memory bank select (GRLIB specific, need to be -- decoded for the two address ranges the PCI core -- occupies in the AHB address range. -- ahbso_hready : out std_ulogic; -- transfer done ahbso_hresp : out std_logic_vector(1 downto 0); -- response type ahbso_hrdata : out std_logic_vector(AHBDW-1 downto 0); -- read data bus ahbso_hsplit : out std_logic_vector(NAHBMST-1 downto 0); -- split completion -- testen : in std_ulogic; -- scan test enable testrst : in std_ulogic; -- scan test reset scanen : in std_ulogic; -- scan enable testoen : in std_ulogic; -- test output enable testin : in std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams -- ahbmi_hgrant : in std_logic; -- bus grant ahbmi_hready : in std_ulogic; -- transfer done ahbmi_hresp : in std_logic_vector(1 downto 0); -- response type ahbmi_hrdata : in std_logic_vector(AHBDW-1 downto 0); -- read data bus -- ahbmo_hbusreq : out std_ulogic; -- bus request ahbmo_hlock : out std_ulogic; -- lock request ahbmo_htrans : out std_logic_vector(1 downto 0); -- transfer type ahbmo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte) ahbmo_hwrite : out std_ulogic; -- read/write ahbmo_hsize : out std_logic_vector(2 downto 0); -- transfer size ahbmo_hburst : out std_logic_vector(2 downto 0); -- burst type ahbmo_hprot : out std_logic_vector(3 downto 0); -- protection control ahbmo_hwdata : out std_logic_vector(AHBDW-1 downto 0); -- write data bus -- ahbdmo_hbusreq : out std_ulogic; -- bus request ahbdmo_hlock : out std_ulogic; -- lock request ahbdmo_htrans : out std_logic_vector(1 downto 0); -- transfer type ahbdmo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte) ahbdmo_hwrite : out std_ulogic; -- read/write ahbdmo_hsize : out std_logic_vector(2 downto 0); -- transfer size ahbdmo_hburst : out std_logic_vector(2 downto 0); -- burst type ahbdmo_hprot : out std_logic_vector(3 downto 0); -- protection control ahbdmo_hwdata : out std_logic_vector(AHBDW-1 downto 0); -- write data bus -- ptarst : out std_logic; -- PCI reset to connect to AMBA reset -- tbapb_psel : in std_logic; -- slave select tbapb_penable : in std_ulogic; -- strobe tbapb_paddr : in std_logic_vector(31 downto 0); -- address bus (byte) tbapb_pwrite : in std_ulogic; -- write tbapb_pwdata : in std_logic_vector(31 downto 0); -- write data bus tbapb_prdata : out std_logic_vector(31 downto 0); -- read data bus -- debugo : out std_logic_vector(debug*255 downto 0) -- DEBUG output ); end; architecture rtl of grpci2_gen is signal pcii : pci_in_type; signal pcio : pci_out_type; signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_type; signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_type; signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_type; signal ahbdmo : ahb_mst_out_type; signal tbapbi : apb_slv_in_type; signal tbapbo : apb_slv_out_type; begin pcii.rst <= pci_rst_i; pcii.gnt <= pci_gnt; pcii.idsel <= pci_idsel; pcii.ad <= pci_ad_i; pcii.cbe <= pci_cbe_i; pcii.frame <= pci_frame_i; pcii.irdy <= pci_irdy_i; pcii.trdy <= pci_trdy_i; pcii.devsel <= pci_devsel_i; pcii.stop <= pci_stop_i; pcii.lock <= '0'; pcii.perr <= pci_perr_i; pcii.serr <= pci_serr_i; pcii.par <= pci_par_i; pcii.host <= pci_host; pcii.pci66 <= pci_pci66; pcii.pme_status <= '0'; pcii.int <= pci_int_i; pci_ad_oe <= pcio.vaden; --pci_vad_oe <= pcio.vaden; pci_cbe_oe <= pcio.cbeen; pci_frame_oe <= pcio.frameen; pci_irdy_oe <= pcio.irdyen; pci_trdy_oe <= pcio.trdyen; pci_devsel_oe <= pcio.devselen; pci_stop_oe <= pcio.stopen; --pci_ctrl_oe <= pcio.ctrlen; pci_perr_oe <= pcio.perren; pci_par_oe <= pcio.paren; pci_req_oe <= pcio.reqen; --pci_lock_oe <= pcio.locken; pci_serr_oe <= pcio.serren; --pci_int_oe <= pcio.inten; pci_int_oe <= pcio.vinten; pci_req_o <= pcio.req; pci_ad_o <= pcio.ad; pci_cbe_o <= pcio.cbe; pci_frame_o <= pcio.frame; pci_irdy_o <= pcio.irdy; pci_trdy_o <= pcio.trdy; pci_devsel_o <= pcio.devsel; pci_stop_o <= pcio.stop; pci_perr_o <= pcio.perr; pci_serr_o <= pcio.serr; pci_par_o <= pcio.par; --pci_lock_o <= pcio.lock; --pci_power_state <= pcio.power_state; --pci_pme_enable <= pcio.pme_enable; --pci_pme_clear <= pcio.pme_clear; --pci_int_o <= pcio.int; pci_rst_o <= pcio.rst; apbi.psel(0) <= apb_psel; apbi.penable <= apb_penable; apbi.paddr <= apb_paddr; apbi.pwrite <= apb_pwrite; apbi.pwdata <= apb_pwdata; apb_prdata <= apbo.prdata; -- apb_pirq <= apbo.pirq(4 downto 0); -- apbi.pirq <= (others => '0'); apbi.testen <= '0'; apbi.testrst <= '0'; apbi.scanen <= '0'; apbi.testoen <= '0'; apbi.testin <= (others => '0'); tbapbi.psel(0) <= tbapb_psel; tbapbi.penable <= tbapb_penable; tbapbi.paddr <= tbapb_paddr; tbapbi.pwrite <= tbapb_pwrite; tbapbi.pwdata <= tbapb_pwdata; tbapb_prdata <= tbapbo.prdata; -- tbapbi.pirq <= (others => '0'); tbapbi.testen <= '0'; tbapbi.testrst <= '0'; tbapbi.scanen <= '0'; tbapbi.testoen <= '0'; tbapbi.testin <= (others => '0'); ahbmi.hgrant(0) <= ahbmi_hgrant; ahbmi.hready <= ahbmi_hready; ahbmi.hresp <= ahbmi_hresp; ahbmi.hrdata <= ahbmi_hrdata; -- ahbmi.hirq <= (others => '0'); ahbmi.testen <= '0'; ahbmi.testrst <= '0'; ahbmi.scanen <= '0'; ahbmi.testoen <= '0'; ahbmi.testin <= (others => '0'); ahbmo_hbusreq <= ahbmo.hbusreq; ahbmo_hlock <= ahbmo.hlock; ahbmo_htrans <= ahbmo.htrans; ahbmo_haddr <= ahbmo.haddr; ahbmo_hwrite <= ahbmo.hwrite; ahbmo_hsize <= ahbmo.hsize; ahbmo_hburst <= ahbmo.hburst; ahbmo_hprot <= ahbmo.hprot; ahbmo_hwdata <= ahbmo.hwdata; ahbdmo_hbusreq <= ahbdmo.hbusreq; ahbdmo_hlock <= ahbdmo.hlock; ahbdmo_htrans <= ahbdmo.htrans; ahbdmo_haddr <= ahbdmo.haddr; ahbdmo_hwrite <= ahbdmo.hwrite; ahbdmo_hsize <= ahbdmo.hsize; ahbdmo_hburst <= ahbdmo.hburst; ahbdmo_hprot <= ahbdmo.hprot; ahbdmo_hwdata <= ahbdmo.hwdata; ahbsi.hsel(0) <= ahbsi_hsel; ahbsi.haddr <= ahbsi_haddr; ahbsi.hwrite <= ahbsi_hwrite; ahbsi.htrans <= ahbsi_htrans; ahbsi.hsize <= ahbsi_hsize; ahbsi.hburst <= ahbsi_hburst; ahbsi.hwdata <= ahbsi_hwdata; ahbsi.hprot <= ahbsi_hprot; ahbsi.hready <= ahbsi_hready; ahbsi.hmaster <= ahbsi_hmaster; ahbsi.hmastlock <= ahbsi_hmastlock; -- ahbsi.hmbsel <= ahbsi_hmbsel; -- ahbsi.hirq <= (others => '0'); ahbsi.testen <= testen; ahbsi.testrst <= testrst; ahbsi.scanen <= scanen; ahbsi.testoen <= testoen; ahbsi.testin <= testin; ahbso_hready <= ahbso.hready; ahbso_hresp <= ahbso.hresp; ahbso_hrdata <= ahbso.hrdata; ahbso_hsplit <= ahbso.hsplit; gen : grpci2 generic map( memtech => memtech, tbmemtech => tbmemtech, oepol => oepol, hmindex => 0, hdmindex => 0, hsindex => 0, haddr => 0, hmask => hmask, ioaddr => 0, pindex => 0, paddr => 0, pmask => 0, irq => 0, irqmode => irqmode, master => master, target => target, dma => dma, tracebuffer => tracebuffer, confspace => confspace, vendorid => vendorid, deviceid => deviceid, classcode => classcode, revisionid => revisionid, cap_pointer => cap_pointer, ext_cap_pointer => ext_cap_pointer, iobase => iobase, extcfg => extcfg, bar0 => bar0, bar1 => bar1, bar2 => bar2, bar3 => bar3, bar4 => bar4, bar5 => bar5, bar0_map => bar0_map, bar1_map => bar1_map, bar2_map => bar2_map, bar3_map => bar3_map, bar4_map => bar4_map, bar5_map => bar5_map, bartype => bartype, barminsize => barminsize, fifo_depth => fifo_depth, fifo_count => fifo_count, conv_endian => conv_endian, deviceirq => deviceirq, deviceirqmask => deviceirqmask, hostirq => hostirq, hostirqmask => hostirqmask, nsync => nsync, hostrst => hostrst, bypass => bypass, ft => ft, scantest => scantest, debug => debug, tbapben => tbapben, tbpindex => 0, tbpaddr => 0, tbpmask => 0, netlist => netlist, multifunc => multifunc, multiint => multiint, masters => masters, mf1_deviceid => mf1_deviceid, mf1_classcode => mf1_classcode, mf1_revisionid => mf1_revisionid, mf1_bar0 => mf1_bar0, mf1_bar1 => mf1_bar1, mf1_bar2 => mf1_bar2, mf1_bar3 => mf1_bar3, mf1_bar4 => mf1_bar4, mf1_bar5 => mf1_bar5, mf1_bartype => mf1_bartype, mf1_bar0_map => mf1_bar0_map, mf1_bar1_map => mf1_bar1_map, mf1_bar2_map => mf1_bar2_map, mf1_bar3_map => mf1_bar3_map, mf1_bar4_map => mf1_bar4_map, mf1_bar5_map => mf1_bar5_map, mf1_cap_pointer => mf1_cap_pointer, mf1_ext_cap_pointer => mf1_ext_cap_pointer, mf1_extcfg => mf1_extcfg, mf1_masters => mf1_masters) port map( rst => rst, clk => clk, pciclk => pciclk, dirq => dirq, pcii => pcii, pcio => pcio, apbi => apbi, apbo => apbo, ahbsi => ahbsi, ahbso => ahbso, ahbmi => ahbmi, ahbmo => ahbmo, ahbdmi => ahbmi, ahbdmo => ahbdmo, ptarst => ptarst, tbapbi => tbapbi, tbapbo => tbapbo, debugo => debugo); end;
library verilog; use verilog.vl_types.all; entity View_vlg_vec_tst is end View_vlg_vec_tst;
library verilog; use verilog.vl_types.all; entity View_vlg_vec_tst is end View_vlg_vec_tst;
-- ------------------------------------------------------------- -- -- Generated Configuration for ioblock3_e -- -- Generated -- by: wig -- on: Mon Jul 18 15:56:34 2005 -- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: ioblock3_e-conf-c.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $ -- $Date: 2005/07/19 07:13:11 $ -- $Log: ioblock3_e-conf-c.vhd,v $ -- Revision 1.3 2005/07/19 07:13:11 wig -- Update testcases. Added highlow/nolowbus -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.36 , [email protected] -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/conf -- -- Start of Generated Configuration ioblock3_e_conf / ioblock3_e -- configuration ioblock3_e_conf of ioblock3_e is for rtl -- Generated Configuration for ioc_data_10 : ioc_r_iou use configuration work.ioc_r_iou_conf; end for; for ioc_data_9 : ioc_r_iou use configuration work.ioc_r_iou_conf; end for; for ioc_data_i33 : ioc_g_i use configuration work.ioc_g_i_conf; end for; for ioc_data_i34 : ioc_g_i use configuration work.ioc_g_i_conf; end for; for ioc_data_o35 : ioc_g_o use configuration work.ioc_g_o_conf; end for; for ioc_data_o36 : ioc_g_o use configuration work.ioc_g_o_conf; end for; for ioc_disp_10 : ioc_r_io3 use configuration work.ioc_r_io3_conf; end for; for ioc_disp_9 : ioc_r_io3 use configuration work.ioc_r_io3_conf; end for; end for; end ioblock3_e_conf; -- -- End of Generated Configuration ioblock3_e_conf -- -- --!End of Configuration/ies -- --------------------------------------------------------------
---------------------------------------------------------------------------------- -- Company: LARC - Escola Politecnica - University of Sao Paulo -- Engineer: Pedro Maat C. Massolino -- -- Create Date: 05/12/2012 -- Design Name: RAM_double_multiple_access -- Module Name: RAM_double_multiple_access_file -- Project Name: Essentials -- Target Devices: Any -- Tool versions: Xilinx ISE 13.3 WebPack -- -- Description: -- -- Circuit to simulate the behavioral of multiple memory RAM that shares the same content. -- It is useful when you want to access more than one location at the same time, and -- the locations for each access can be anywhere in the memory, where in banks in most -- time is one address after another. -- It can be seen as one single with multiple I/O operating at the same time. -- In this double version it is possible to read and write at same cycle. -- -- The circuits parameters -- -- number_of_memories : -- -- The total number of memories or the total number of I/O's applied. -- -- ram_address_size : -- -- Address size of the RAM used on the circuit. -- -- ram_word_size : -- -- The size of internal word of the RAM. -- -- file_ram_word_size : -- -- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD) -- -- load_file_name : -- -- The name of file to be loaded.(ARCH: FILE_LOAD) -- -- dump_file_name : -- -- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD) -- -- Dependencies: -- VHDL-93 -- -- IEEE.NUMERIC_STD.ALL; -- IEEE.STD_LOGIC_TEXTIO.ALL; -- STD.TEXTIO.ALL; -- -- Revision: -- Revision 1.0 -- Additional Comments: -- ---------------------------------------------------------------------------------- architecture file_load of ram_double_multiple_access is type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0); pure function load_ram (ram_file_name : in string) return ramtype is FILE ram_file : text is in ram_file_name; variable line_n : line; variable memory_ram : ramtype; variable file_read_buffer : std_logic_vector((file_ram_word_size - 1) downto 0); variable file_buffer_amount : integer; variable ram_buffer_amount : integer; begin file_buffer_amount := file_ram_word_size; for I in ramtype'range loop ram_buffer_amount := 0; if (not endfile(ram_file) or (file_buffer_amount /= file_ram_word_size)) then while ram_buffer_amount /= ram_word_size loop if file_buffer_amount = file_ram_word_size then if (not endfile(ram_file)) then readline (ram_file, line_n); read (line_n, file_read_buffer); else file_read_buffer := (others => '0'); end if; file_buffer_amount := 0; end if; memory_ram(I)(ram_buffer_amount) := file_read_buffer(file_buffer_amount); ram_buffer_amount := ram_buffer_amount + 1; file_buffer_amount := file_buffer_amount + 1; end loop; else memory_ram(I) := (others => '0'); end if; end loop; return memory_ram; end function; procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is FILE ram_file : text is out ram_file_name; variable line_n : line; begin for I in ramtype'range loop write (line_n, memory_ram(I)); writeline (ram_file, line_n); end loop; end procedure; signal memory_ram : ramtype := load_ram(load_file_name); begin process (clk) begin if clk'event and clk = '1' then if rst = '1' then memory_ram <= load_ram(load_file_name); end if; if dump = '1' then dump_ram(dump_file_name, memory_ram); end if; if rw_a = '1' then for index in 0 to (number_of_memories - 1) loop memory_ram(to_integer(unsigned(address_a(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)); end loop; end if; if rw_b = '1' then for index in 0 to (number_of_memories - 1) loop memory_ram(to_integer(unsigned(address_b(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)); end loop; end if; for index in 0 to (number_of_memories - 1) loop data_out_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_a(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))); data_out_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_b(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))); end loop; end if; end process; end file_load;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc500.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b02x00p02n01i00500ent IS END c03s02b02x00p02n01i00500ent; ARCHITECTURE c03s02b02x00p02n01i00500arch OF c03s02b02x00p02n01i00500ent IS type rec_type is record x : integer; y : real; z : boolean; b : bit; end record; BEGIN TESTING: PROCESS variable v1 : rec_type; BEGIN v1.x := 12; v1.y := 1.2; v1.z := true; v1.b := bit'('0'); assert NOT(v1.x=12 and v1.y=1.2 and v1.z=true and v1.b='0') report "***PASSED TEST: c03s02b02x00p02n01i00500" severity NOTE; assert (v1.x=12 and v1.y=1.2 and v1.z=true and v1.b='0') report "***FAILED TEST: c03s02b02x00p02n01i00500 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record." severity ERROR; wait; END PROCESS TESTING; END c03s02b02x00p02n01i00500arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc500.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b02x00p02n01i00500ent IS END c03s02b02x00p02n01i00500ent; ARCHITECTURE c03s02b02x00p02n01i00500arch OF c03s02b02x00p02n01i00500ent IS type rec_type is record x : integer; y : real; z : boolean; b : bit; end record; BEGIN TESTING: PROCESS variable v1 : rec_type; BEGIN v1.x := 12; v1.y := 1.2; v1.z := true; v1.b := bit'('0'); assert NOT(v1.x=12 and v1.y=1.2 and v1.z=true and v1.b='0') report "***PASSED TEST: c03s02b02x00p02n01i00500" severity NOTE; assert (v1.x=12 and v1.y=1.2 and v1.z=true and v1.b='0') report "***FAILED TEST: c03s02b02x00p02n01i00500 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record." severity ERROR; wait; END PROCESS TESTING; END c03s02b02x00p02n01i00500arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc500.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b02x00p02n01i00500ent IS END c03s02b02x00p02n01i00500ent; ARCHITECTURE c03s02b02x00p02n01i00500arch OF c03s02b02x00p02n01i00500ent IS type rec_type is record x : integer; y : real; z : boolean; b : bit; end record; BEGIN TESTING: PROCESS variable v1 : rec_type; BEGIN v1.x := 12; v1.y := 1.2; v1.z := true; v1.b := bit'('0'); assert NOT(v1.x=12 and v1.y=1.2 and v1.z=true and v1.b='0') report "***PASSED TEST: c03s02b02x00p02n01i00500" severity NOTE; assert (v1.x=12 and v1.y=1.2 and v1.z=true and v1.b='0') report "***FAILED TEST: c03s02b02x00p02n01i00500 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record." severity ERROR; wait; END PROCESS TESTING; END c03s02b02x00p02n01i00500arch;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package very_common_pkg is constant VIM_HDL_VERSION : string := "0.1"; component clock_divider is generic ( DIVIDER : integer := 10 ); port ( reset : in std_logic; clk_input : in std_logic; clk_output : out std_logic ); end component; component clk_en_generator is generic ( DIVIDER : integer := 10 ); port ( reset : in std_logic; clk_input : in std_logic; clk_en : out std_logic ); end component; end package; -- package body very_common_pkg is -- end package body;
-- megafunction wizard: %ROM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: PhSeROM.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 12.1 Build 177 11/07/2012 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2012 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY PhSeROM IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END PhSeROM; ARCHITECTURE SYN OF phserom IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); COMPONENT altsyncram GENERIC ( address_aclr_a : STRING; clock_enable_input_a : STRING; clock_enable_output_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock0 : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(3 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_a => "NONE", clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", init_file => "PhaseSelectErr.mif", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", numwords_a => 256, operation_mode => "ROM", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", widthad_a => 8, width_a => 4, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "PhaseSelectErr.mif" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "4" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INIT_FILE STRING "PhaseSelectErr.mif" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf
-- ------------------------------------------------------------- -- -- Entity Declaration for inst_e_e -- -- Generated -- by: wig -- on: Wed Jun 7 17:05:33 2006 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_e_e-e.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $ -- $Date: 2006/06/22 07:19:59 $ -- $Log: inst_e_e-e.vhd,v $ -- Revision 1.2 2006/06/22 07:19:59 wig -- Updated testcases and extended MixTest.pl to also verify number of created files. -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.45 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_e_e -- entity inst_e_e is -- Generics: -- No Generated Generics for Entity inst_e_e -- Generated Port Declaration: port( -- Generated Port for Entity inst_e_e video_i : in std_ulogic_vector(3 downto 0); widesig_i : in std_ulogic_vector(31 downto 0); p_mix_widesig_r_0_gi : in std_ulogic; p_mix_widesig_r_1_gi : in std_ulogic; p_mix_widesig_r_2_gi : in std_ulogic; p_mix_widesig_r_3_gi : in std_ulogic; p_mix_widesig_r_4_gi : in std_ulogic; p_mix_widesig_r_5_gi : in std_ulogic; p_mix_widesig_r_6_gi : in std_ulogic; p_mix_widesig_r_7_gi : in std_ulogic; p_mix_widesig_r_8_gi : in std_ulogic; p_mix_widesig_r_9_gi : in std_ulogic; p_mix_widesig_r_10_gi : in std_ulogic; p_mix_widesig_r_11_gi : in std_ulogic; p_mix_widesig_r_12_gi : in std_ulogic; p_mix_widesig_r_13_gi : in std_ulogic; p_mix_widesig_r_14_gi : in std_ulogic; p_mix_widesig_r_15_gi : in std_ulogic; p_mix_widesig_r_16_gi : in std_ulogic; p_mix_widesig_r_17_gi : in std_ulogic; p_mix_widesig_r_18_gi : in std_ulogic; p_mix_widesig_r_19_gi : in std_ulogic; p_mix_widesig_r_20_gi : in std_ulogic; p_mix_widesig_r_21_gi : in std_ulogic; p_mix_widesig_r_22_gi : in std_ulogic; p_mix_widesig_r_23_gi : in std_ulogic; p_mix_widesig_r_24_gi : in std_ulogic; p_mix_widesig_r_25_gi : in std_ulogic; p_mix_widesig_r_26_gi : in std_ulogic; p_mix_widesig_r_27_gi : in std_ulogic; p_mix_widesig_r_28_gi : in std_ulogic; p_mix_widesig_r_29_gi : in std_ulogic; p_mix_widesig_r_30_gi : in std_ulogic; p_mix_unsplice_a1_no3_125_0_gi : in std_ulogic_vector(125 downto 0); p_mix_unsplice_a1_no3_127_127_gi : in std_ulogic; p_mix_unsplice_a2_all128_127_0_gi : in std_ulogic_vector(127 downto 0); p_mix_unsplice_a3_up100_100_0_gi : in std_ulogic_vector(100 downto 0); p_mix_unsplice_a4_mid100_99_2_gi : in std_ulogic_vector(97 downto 0); p_mix_unsplice_a5_midp100_99_2_gi : in std_ulogic_vector(97 downto 0); p_mix_unsplice_bad_a_1_1_gi : in std_ulogic; p_mix_unsplice_bad_b_1_0_gi : in std_ulogic_vector(1 downto 0); p_mix_widemerge_a1_31_0_gi : in std_ulogic_vector(31 downto 0) -- End of Generated Port for Entity inst_e_e ); end inst_e_e; -- -- End of Generated Entity inst_e_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RlfItrBP2dXV2n8Ld+8AcLKvHOqD6HaeHtcM1ZQvksYtjq1Fs5oVI2SBjV8AmO9IiyJSpMdfy0uh Su8ntPzG7g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NpDp4Y0GkdshfA8BWf95HAAEdqfO3hEOHloNvcNt0LAVXuTaHC2Y2Kd7U+G172t+jQqqpZoY8zn5 d2TLAMcs1n0/kUB5mIdWLbzKbP2wxQCQsBypKDXsXIVT9pC7YXZVywzQv/yoqztIlsUnnV4K8kZ/ 988seSyskp0Zq/n2reY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RlfItrBP2dXV2n8Ld+8AcLKvHOqD6HaeHtcM1ZQvksYtjq1Fs5oVI2SBjV8AmO9IiyJSpMdfy0uh Su8ntPzG7g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NpDp4Y0GkdshfA8BWf95HAAEdqfO3hEOHloNvcNt0LAVXuTaHC2Y2Kd7U+G172t+jQqqpZoY8zn5 d2TLAMcs1n0/kUB5mIdWLbzKbP2wxQCQsBypKDXsXIVT9pC7YXZVywzQv/yoqztIlsUnnV4K8kZ/ 988seSyskp0Zq/n2reY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RlfItrBP2dXV2n8Ld+8AcLKvHOqD6HaeHtcM1ZQvksYtjq1Fs5oVI2SBjV8AmO9IiyJSpMdfy0uh Su8ntPzG7g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NpDp4Y0GkdshfA8BWf95HAAEdqfO3hEOHloNvcNt0LAVXuTaHC2Y2Kd7U+G172t+jQqqpZoY8zn5 d2TLAMcs1n0/kUB5mIdWLbzKbP2wxQCQsBypKDXsXIVT9pC7YXZVywzQv/yoqztIlsUnnV4K8kZ/ 988seSyskp0Zq/n2reY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RlfItrBP2dXV2n8Ld+8AcLKvHOqD6HaeHtcM1ZQvksYtjq1Fs5oVI2SBjV8AmO9IiyJSpMdfy0uh Su8ntPzG7g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NpDp4Y0GkdshfA8BWf95HAAEdqfO3hEOHloNvcNt0LAVXuTaHC2Y2Kd7U+G172t+jQqqpZoY8zn5 d2TLAMcs1n0/kUB5mIdWLbzKbP2wxQCQsBypKDXsXIVT9pC7YXZVywzQv/yoqztIlsUnnV4K8kZ/ 988seSyskp0Zq/n2reY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block tZNydnyeLYdVQs0bj8l6U7q20KMO/Wxt6mUC5MVZeoPp+GMb+R0We34z9dZmKaphxEVFA2tx6hAt hFheNyU/FLCU2dnjhx7aco4wUxhFkq6zS5/fN8Bx9YteBhDg2CPxmhZADfOKA6bGMHggG5czBrZC sAa8BlqHUS6ni5BRkq0KRiyuNKgv2Bs9cjQ8Bmiby2mPqhuEcFCOn51f8Mtj1VrpO2bmA/tNWO+M jqObEmiLHNdW3dnj7TCllBV2aQLxpuDYupA2+cOociKLVf5HJWJoyby4W3vz2sH7X/hdY0tW1hqz WLNhT202sv7yuwfesAiiGfksaHY8UwFM1K9hAA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4ABns/uCsb5/6KK7PwZTtRkykKVwbLhqo58xiIO46mNP3jN2/yCw+egRwO5MZtPdjugLgl4sIfjS ntQ0OJooKKjTjPcVpeo9hTEELOGZsaTuRHThmlHsw+YcH0uiqUneG5wgi7zMYSZEoeC6KZhock4m CAhbJYYW7NydsuHSkNU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block cRraZTE3WlbZKmgtC8RzLH6Hv9U9rVkLkXiZMrpJOUr4w4jkAXuQACYsPE+MmYGcFeel4bdLbK4O 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RlfItrBP2dXV2n8Ld+8AcLKvHOqD6HaeHtcM1ZQvksYtjq1Fs5oVI2SBjV8AmO9IiyJSpMdfy0uh Su8ntPzG7g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NpDp4Y0GkdshfA8BWf95HAAEdqfO3hEOHloNvcNt0LAVXuTaHC2Y2Kd7U+G172t+jQqqpZoY8zn5 d2TLAMcs1n0/kUB5mIdWLbzKbP2wxQCQsBypKDXsXIVT9pC7YXZVywzQv/yoqztIlsUnnV4K8kZ/ 988seSyskp0Zq/n2reY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RlfItrBP2dXV2n8Ld+8AcLKvHOqD6HaeHtcM1ZQvksYtjq1Fs5oVI2SBjV8AmO9IiyJSpMdfy0uh Su8ntPzG7g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NpDp4Y0GkdshfA8BWf95HAAEdqfO3hEOHloNvcNt0LAVXuTaHC2Y2Kd7U+G172t+jQqqpZoY8zn5 d2TLAMcs1n0/kUB5mIdWLbzKbP2wxQCQsBypKDXsXIVT9pC7YXZVywzQv/yoqztIlsUnnV4K8kZ/ 988seSyskp0Zq/n2reY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block tZNydnyeLYdVQs0bj8l6U7q20KMO/Wxt6mUC5MVZeoPp+GMb+R0We34z9dZmKaphxEVFA2tx6hAt hFheNyU/FLCU2dnjhx7aco4wUxhFkq6zS5/fN8Bx9YteBhDg2CPxmhZADfOKA6bGMHggG5czBrZC sAa8BlqHUS6ni5BRkq0KRiyuNKgv2Bs9cjQ8Bmiby2mPqhuEcFCOn51f8Mtj1VrpO2bmA/tNWO+M jqObEmiLHNdW3dnj7TCllBV2aQLxpuDYupA2+cOociKLVf5HJWJoyby4W3vz2sH7X/hdY0tW1hqz WLNhT202sv7yuwfesAiiGfksaHY8UwFM1K9hAA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4ABns/uCsb5/6KK7PwZTtRkykKVwbLhqo58xiIO46mNP3jN2/yCw+egRwO5MZtPdjugLgl4sIfjS ntQ0OJooKKjTjPcVpeo9hTEELOGZsaTuRHThmlHsw+YcH0uiqUneG5wgi7zMYSZEoeC6KZhock4m CAhbJYYW7NydsuHSkNU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block cRraZTE3WlbZKmgtC8RzLH6Hv9U9rVkLkXiZMrpJOUr4w4jkAXuQACYsPE+MmYGcFeel4bdLbK4O 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RlfItrBP2dXV2n8Ld+8AcLKvHOqD6HaeHtcM1ZQvksYtjq1Fs5oVI2SBjV8AmO9IiyJSpMdfy0uh Su8ntPzG7g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NpDp4Y0GkdshfA8BWf95HAAEdqfO3hEOHloNvcNt0LAVXuTaHC2Y2Kd7U+G172t+jQqqpZoY8zn5 d2TLAMcs1n0/kUB5mIdWLbzKbP2wxQCQsBypKDXsXIVT9pC7YXZVywzQv/yoqztIlsUnnV4K8kZ/ 988seSyskp0Zq/n2reY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RlfItrBP2dXV2n8Ld+8AcLKvHOqD6HaeHtcM1ZQvksYtjq1Fs5oVI2SBjV8AmO9IiyJSpMdfy0uh Su8ntPzG7g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NpDp4Y0GkdshfA8BWf95HAAEdqfO3hEOHloNvcNt0LAVXuTaHC2Y2Kd7U+G172t+jQqqpZoY8zn5 d2TLAMcs1n0/kUB5mIdWLbzKbP2wxQCQsBypKDXsXIVT9pC7YXZVywzQv/yoqztIlsUnnV4K8kZ/ 988seSyskp0Zq/n2reY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RlfItrBP2dXV2n8Ld+8AcLKvHOqD6HaeHtcM1ZQvksYtjq1Fs5oVI2SBjV8AmO9IiyJSpMdfy0uh Su8ntPzG7g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NpDp4Y0GkdshfA8BWf95HAAEdqfO3hEOHloNvcNt0LAVXuTaHC2Y2Kd7U+G172t+jQqqpZoY8zn5 d2TLAMcs1n0/kUB5mIdWLbzKbP2wxQCQsBypKDXsXIVT9pC7YXZVywzQv/yoqztIlsUnnV4K8kZ/ 988seSyskp0Zq/n2reY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015 - 2016, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: Various -- File: atmel_simprims.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: ATMEL ATC18 behavioural models -- Modelled after IO33/PCILIB data sheets ------------------------------------------------------------------------------ -- pragma translate_off -- input pad library ieee; use ieee.std_logic_1164.all; entity pc33d00z is port (pad : in std_logic; cin : out std_logic); end; architecture rtl of pc33d00z is begin cin <= to_x01(pad) after 1 ns; end; -- input pad with pull-up library ieee; use ieee.std_logic_1164.all; entity pc33d00uz is port (pad : inout std_logic; cin : out std_logic); end; architecture rtl of pc33d00uz is begin cin <= to_x01(pad) after 1 ns; pad <= 'H'; end; -- input schmitt pad library ieee; use ieee.std_logic_1164.all; entity pc33d20z is port (pad : in std_logic; cin : out std_logic); end; architecture rtl of pc33d20z is begin cin <= to_x01(pad) after 1 ns; end; -- input schmitt pad with pull-up library ieee; use ieee.std_logic_1164.all; entity pc33d20uz is port (pad : inout std_logic; cin : out std_logic); end; architecture rtl of pc33d20uz is begin cin <= to_x01(pad) after 1 ns; pad <= 'H'; end; -- output pads library ieee; use ieee.std_logic_1164.all; entity pt33o01z is port (i : in std_logic; pad : out std_logic); end; architecture rtl of pt33o01z is begin pad <= to_x01(i) after 2 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33o02z is port (i : in std_logic; pad : out std_logic); end; architecture rtl of pt33o02z is begin pad <= to_x01(i) after 2 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33o04z is port (i : in std_logic; pad : out std_logic); end; architecture rtl of pt33o04z is begin pad <= to_x01(i) after 2 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33o08z is port (i : in std_logic; pad : out std_logic); end; architecture rtl of pt33o08z is begin pad <= to_x01(i) after 2 ns; end; -- output tri-state pads library ieee; use ieee.std_logic_1164.all; entity pt33t01z is port (i, oen : in std_logic; pad : out std_logic); end; architecture rtl of pt33t01z is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33t02z is port (i, oen : in std_logic; pad : out std_logic); end; architecture rtl of pt33t02z is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33t04z is port (i, oen : in std_logic; pad : out std_logic); end; architecture rtl of pt33t04z is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33t08z is port (i, oen : in std_logic; pad : out std_logic); end; architecture rtl of pt33t08z is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end; -- output tri-state pads with pull-up library ieee; use ieee.std_logic_1164.all; entity pt33t01uz is port (i, oen : in std_logic; pad : out std_logic); end; architecture rtl of pt33t01uz is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33t02uz is port (i, oen : in std_logic; pad : out std_logic); end; architecture rtl of pt33t02uz is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33t04uz is port (i, oen : in std_logic; pad : out std_logic); end; architecture rtl of pt33t04uz is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end; -- bidirectional pad library ieee; use ieee.std_logic_1164.all; entity pt33b01z is port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end; architecture rtl of pt33b01z is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; cin <= to_x01(pad) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33b02z is port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end; architecture rtl of pt33b02z is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; cin <= to_x01(pad) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33b08z is port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end; architecture rtl of pt33b08z is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; cin <= to_x01(pad) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33b04z is port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end; architecture rtl of pt33b04z is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; cin <= to_x01(pad) after 1 ns; end; -- bidirectional pads with pull-up library ieee; use ieee.std_logic_1164.all; entity pt33b01uz is port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end; architecture rtl of pt33b01uz is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; cin <= to_x01(pad) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33b02uz is port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end; architecture rtl of pt33b02uz is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; cin <= to_x01(pad) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33b08uz is port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end; architecture rtl of pt33b08uz is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; cin <= to_x01(pad) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; entity pt33b04uz is port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end; architecture rtl of pt33b04uz is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; cin <= to_x01(pad) after 1 ns; end; -- PCI output pad library ieee; use ieee.std_logic_1164.all; entity pp33o01z is port (i : in std_logic; pad : out std_logic); end; architecture rtl of pp33o01z is begin pad <= to_x01(i) after 2 ns; end; -- PCI bidirectional pad library ieee; use ieee.std_logic_1164.all; entity pp33b01z is port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic); end; architecture rtl of pp33b01z is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; cin <= to_x01(pad) after 1 ns; end; -- PCI output tri-state pad library ieee; use ieee.std_logic_1164.all; entity pp33t01z is port (i, oen : in std_logic; pad : out std_logic); end; architecture rtl of pp33t01z is begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; end; -- pragma translate_on
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pctrl.vhd -- -- Description: -- Used for protocol control on write and read interface stimulus and status generation -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pkg.ALL; ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pctrl IS GENERIC( AXI_CHANNEL : STRING :="NONE"; C_APPLICATION_TYPE : INTEGER := 0; C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_WR_PNTR_WIDTH : INTEGER := 0; C_RD_PNTR_WIDTH : INTEGER := 0; C_CH_TYPE : INTEGER := 0; FREEZEON_ERROR : INTEGER := 0; TB_STOP_CNT : INTEGER := 2; TB_SEED : INTEGER := 2 ); PORT( RESET_WR : IN STD_LOGIC; RESET_RD : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; FULL : IN STD_LOGIC; EMPTY : IN STD_LOGIC; ALMOST_FULL : IN STD_LOGIC; ALMOST_EMPTY : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); DOUT_CHK : IN STD_LOGIC; PRC_WR_EN : OUT STD_LOGIC; PRC_RD_EN : OUT STD_LOGIC; RESET_EN : OUT STD_LOGIC; SIM_DONE : OUT STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ENTITY; ARCHITECTURE fg_pc_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_pctrl IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH); SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); SIGNAL wr_en_i : STD_LOGIC := '0'; SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL state : STD_LOGIC := '0'; SIGNAL wr_control : STD_LOGIC := '0'; SIGNAL rd_control : STD_LOGIC := '0'; SIGNAL stop_on_err : STD_LOGIC := '0'; SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8); SIGNAL sim_done_i : STD_LOGIC := '0'; SIGNAL reset_ex1 : STD_LOGIC := '0'; SIGNAL reset_ex2 : STD_LOGIC := '0'; SIGNAL reset_ex3 : STD_LOGIC := '0'; SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0'); SIGNAL prc_we_i : STD_LOGIC := '0'; SIGNAL prc_re_i : STD_LOGIC := '0'; SIGNAL reset_en_i : STD_LOGIC := '0'; SIGNAL state_d1 : STD_LOGIC := '0'; SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); BEGIN status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & ae_chk_i; STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high); prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0'; prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0'; SIM_DONE <= sim_done_i; rdw_gt_wrw <= (OTHERS => '1'); wrw_gt_rdw <= (OTHERS => '1'); PROCESS(RD_CLK) BEGIN IF (RD_CLK'event AND RD_CLK='1') THEN IF(prc_re_i = '1') THEN rd_activ_cont <= rd_activ_cont + "1"; END IF; END IF; END PROCESS; PROCESS(sim_done_i) BEGIN assert sim_done_i = '0' report "Simulation Complete for:" & AXI_CHANNEL severity note; END PROCESS; ----------------------------------------------------- -- SIM_DONE SIGNAL GENERATION ----------------------------------------------------- PROCESS (RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN --sim_done_i <= '0'; ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN sim_done_i <= '1'; END IF; END IF; END PROCESS; -- TB Timeout/Stop fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE PROCESS (RD_CLK) BEGIN IF (RD_CLK'event AND RD_CLK='1') THEN IF(state = '0' AND state_d1 = '1') THEN sim_stop_cntr <= sim_stop_cntr - "1"; END IF; END IF; END PROCESS; END GENERATE fifo_tb_stop_run; -- Stop when error found PROCESS (RD_CLK) BEGIN IF (RD_CLK'event AND RD_CLK='1') THEN IF(sim_done_i = '0') THEN status_d1_i <= status_i OR status_d1_i; END IF; IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN stop_on_err <= '1'; END IF; END IF; END PROCESS; ----------------------------------------------------- ----------------------------------------------------- -- CHECKS FOR FIFO ----------------------------------------------------- -- Reset pulse extension require for FULL flags checks -- FULL flag may stay high for 3 clocks after reset is removed. PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN reset_ex1 <= '1'; reset_ex2 <= '1'; reset_ex3 <= '1'; ELSIF (WR_CLK'event AND WR_CLK='1') THEN reset_ex1 <= '0'; reset_ex2 <= reset_ex1; reset_ex3 <= reset_ex2; END IF; END PROCESS; PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN post_rst_dly_rd <= (OTHERS => '1'); ELSIF (RD_CLK'event AND RD_CLK='1') THEN post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4); END IF; END PROCESS; PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN post_rst_dly_wr <= (OTHERS => '1'); ELSIF (WR_CLK'event AND WR_CLK='1') THEN post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4); END IF; END PROCESS; -- FULL de-assert Counter PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN full_ds_timeout <= (OTHERS => '0'); ELSIF(WR_CLK'event AND WR_CLK='1') THEN IF(state = '1') THEN IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN full_ds_timeout <= full_ds_timeout + '1'; END IF; ELSE full_ds_timeout <= (OTHERS => '0'); END IF; END IF; END PROCESS; -- EMPTY deassert counter PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN empty_ds_timeout <= (OTHERS => '0'); ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF(state = '0') THEN IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN empty_ds_timeout <= empty_ds_timeout + '1'; END IF; ELSE empty_ds_timeout <= (OTHERS => '0'); END IF; END IF; END PROCESS; -- Full check signal generation PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN full_chk_i <= '0'; ELSIF(WR_CLK'event AND WR_CLK='1') THEN IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN full_chk_i <= '0'; ELSE full_chk_i <= AND_REDUCE(full_as_timeout) OR AND_REDUCE(full_ds_timeout); END IF; END IF; END PROCESS; -- Empty checks PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN empty_chk_i <= '0'; ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN empty_chk_i <= '0'; ELSE empty_chk_i <= AND_REDUCE(empty_as_timeout) OR AND_REDUCE(empty_ds_timeout); END IF; END IF; END PROCESS; fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE PRC_WR_EN <= prc_we_i AFTER 50 ns; PRC_RD_EN <= prc_re_i AFTER 50 ns; data_chk_i <= dout_chk; END GENERATE fifo_d_chk; -- Almost empty flag checks PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN ae_chk_i <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR (state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN ae_chk_i <= '1'; ELSE ae_chk_i <= '0'; END IF; END IF; END PROCESS; ----------------------------------------------------- RESET_EN <= reset_en_i; PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN state_d1 <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN state_d1 <= state; END IF; END PROCESS; data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE ----------------------------------------------------- -- WR_EN GENERATION ----------------------------------------------------- gen_rand_wr_en:system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+1 ) PORT MAP( CLK => WR_CLK, RESET => RESET_WR, RANDOM_NUM => wr_en_gen, ENABLE => '1' ); PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN wr_en_i <= '0'; ELSIF(WR_CLK'event AND WR_CLK='1') THEN IF(state = '1') THEN wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control; ELSE wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); END IF; END IF; END PROCESS; ----------------------------------------------------- -- WR_EN CONTROL ----------------------------------------------------- PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN wr_cntr <= (OTHERS => '0'); wr_control <= '1'; full_as_timeout <= (OTHERS => '0'); ELSIF(WR_CLK'event AND WR_CLK='1') THEN IF(state = '1') THEN IF(wr_en_i = '1') THEN wr_cntr <= wr_cntr + "1"; END IF; full_as_timeout <= (OTHERS => '0'); ELSE wr_cntr <= (OTHERS => '0'); IF(rd_en_i = '0') THEN IF(wr_en_i = '1') THEN full_as_timeout <= full_as_timeout + "1"; END IF; ELSE full_as_timeout <= (OTHERS => '0'); END IF; END IF; wr_control <= NOT wr_cntr(wr_cntr'high); END IF; END PROCESS; ----------------------------------------------------- -- RD_EN GENERATION ----------------------------------------------------- gen_rand_rd_en:system_axi_vdma_0_wrapper_fifo_generator_v9_3_1_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED ) PORT MAP( CLK => RD_CLK, RESET => RESET_RD, RANDOM_NUM => rd_en_gen, ENABLE => '1' ); PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN rd_en_i <= '0'; ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF(state = '0') THEN rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4)); ELSE rd_en_i <= rd_en_gen(0) OR rd_en_gen(6); END IF; END IF; END PROCESS; ----------------------------------------------------- -- RD_EN CONTROL ----------------------------------------------------- PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN rd_cntr <= (OTHERS => '0'); rd_control <= '1'; empty_as_timeout <= (OTHERS => '0'); ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF(state = '0') THEN IF(rd_en_i = '1') THEN rd_cntr <= rd_cntr + "1"; END IF; empty_as_timeout <= (OTHERS => '0'); ELSE rd_cntr <= (OTHERS => '0'); IF(wr_en_i = '0') THEN IF(rd_en_i = '1') THEN empty_as_timeout <= empty_as_timeout + "1"; END IF; ELSE empty_as_timeout <= (OTHERS => '0'); END IF; END IF; rd_control <= NOT rd_cntr(rd_cntr'high); END IF; END PROCESS; ----------------------------------------------------- -- STIMULUS CONTROL ----------------------------------------------------- PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN state <= '0'; reset_en_i <= '0'; ELSIF(WR_CLK'event AND WR_CLK='1') THEN CASE state IS WHEN '0' => IF(FULL = '1' AND EMPTY = '0') THEN state <= '1'; reset_en_i <= '0'; END IF; WHEN '1' => IF(EMPTY = '1' AND FULL = '0') THEN state <= '0'; reset_en_i <= '1'; END IF; WHEN OTHERS => state <= state; END CASE; END IF; END PROCESS; END GENERATE data_fifo_en; END ARCHITECTURE;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Sun Jun 04 12:45:05 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top system_xlconstant_0_3 -prefix -- system_xlconstant_0_3_ system_xlconstant_0_3_sim_netlist.vhdl -- Design : system_xlconstant_0_3 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_xlconstant_0_3 is port ( dout : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of system_xlconstant_0_3 : entity is true; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_xlconstant_0_3 : entity is "yes"; end system_xlconstant_0_3; architecture STRUCTURE of system_xlconstant_0_3 is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; begin dout(9) <= \<const0>\; dout(8) <= \<const0>\; dout(7) <= \<const0>\; dout(6) <= \<const0>\; dout(5) <= \<const0>\; dout(4) <= \<const1>\; dout(3) <= \<const0>\; dout(2) <= \<const1>\; dout(1) <= \<const0>\; dout(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); end STRUCTURE;
--------------------------------------------------------------------- ---- ---- ---- WISHBONE revB2 compl. I2C Master Core; byte-controller ---- ---- ---- ---- ---- ---- Author: Richard Herveille ---- ---- [email protected] ---- ---- www.asics.ws ---- ---- ---- ---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- ---- ---- --------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2000 Richard Herveille ---- ---- [email protected] ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer.---- ---- ---- ---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ---- POSSIBILITY OF SUCH DAMAGE. ---- ---- ---- --------------------------------------------------------------------- -- CVS Log -- -- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004-02-18 11:41:48 rherveille Exp $ -- -- $Date: 2004-02-18 11:41:48 $ -- $Revision: 1.5 $ -- $Author: rherveille $ -- $Locker: $ -- $State: Exp $ -- -- Change History: -- $Log: not supported by cvs2svn $ -- Revision 1.4 2003/08/09 07:01:13 rherveille -- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. -- Fixed a potential bug in the byte controller's host-acknowledge generation. -- -- Revision 1.3 2002/12/26 16:05:47 rherveille -- Core is now a Multimaster I2C controller. -- -- Revision 1.2 2002/11/30 22:24:37 rherveille -- Cleaned up code -- -- Revision 1.1 2001/11/05 12:02:33 rherveille -- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. -- Code updated, is now up-to-date to doc. rev.0.4. -- Added headers. -- -- ------------------------------------------ -- Byte controller section ------------------------------------------ -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity i2c_master_byte_ctrl is port ( clk : in std_logic; rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) ena : in std_logic; -- core enable signal clk_cnt : in unsigned(15 downto 0); -- 4x SCL -- input signals start, stop, read, write, ack_in : std_logic; din : in std_logic_vector(7 downto 0); -- output signals cmd_ack : out std_logic; -- command done ack_out : out std_logic; i2c_busy : out std_logic; -- arbitration lost i2c_al : out std_logic; -- i2c bus busy dout : out std_logic_vector(7 downto 0); -- i2c lines scl_i : in std_logic; -- i2c clock line input scl_o : out std_logic; -- i2c clock line output scl_oen : out std_logic; -- i2c clock line output enable, active low sda_i : in std_logic; -- i2c data line input sda_o : out std_logic; -- i2c data line output sda_oen : out std_logic -- i2c data line output enable, active low ); end entity i2c_master_byte_ctrl; architecture structural of i2c_master_byte_ctrl is component i2c_master_bit_ctrl is port ( clk : in std_logic; rst : in std_logic; nReset : in std_logic; ena : in std_logic; -- core enable signal clk_cnt : in unsigned(15 downto 0); -- clock prescale value cmd : in std_logic_vector(3 downto 0); cmd_ack : out std_logic; -- command done busy : out std_logic; -- i2c bus busy al : out std_logic; -- arbitration lost din : in std_logic; dout : out std_logic; -- i2c lines scl_i : in std_logic; -- i2c clock line input scl_o : out std_logic; -- i2c clock line output scl_oen : out std_logic; -- i2c clock line output enable, active low sda_i : in std_logic; -- i2c data line input sda_o : out std_logic; -- i2c data line output sda_oen : out std_logic -- i2c data line output enable, active low ); end component i2c_master_bit_ctrl; -- commands for bit_controller block constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; -- signals for bit_controller signal core_cmd : std_logic_vector(3 downto 0); signal core_ack, core_txd, core_rxd : std_logic; signal al : std_logic; -- signals for shift register signal sr : std_logic_vector(7 downto 0); -- 8bit shift register signal shift, ld : std_logic; -- signals for state machine signal go, host_ack : std_logic; signal dcnt : unsigned(2 downto 0); -- data counter signal cnt_done : std_logic; begin -- hookup bit_controller bit_ctrl: i2c_master_bit_ctrl port map( clk => clk, rst => rst, nReset => nReset, ena => ena, clk_cnt => clk_cnt, cmd => core_cmd, cmd_ack => core_ack, busy => i2c_busy, al => al, din => core_txd, dout => core_rxd, scl_i => scl_i, scl_o => scl_o, scl_oen => scl_oen, sda_i => sda_i, sda_o => sda_o, sda_oen => sda_oen ); i2c_al <= al; -- generate host-command-acknowledge cmd_ack <= host_ack; -- generate go-signal go <= (read or write or stop) and not host_ack; -- assign Dout output to shift-register dout <= sr; -- generate shift register shift_register: process(clk, nReset) begin if (nReset = '0') then sr <= (others => '0'); elsif (clk'event and clk = '1') then if (rst = '1') then sr <= (others => '0'); elsif (ld = '1') then sr <= din; elsif (shift = '1') then sr <= (sr(6 downto 0) & core_rxd); end if; end if; end process shift_register; -- generate data-counter data_cnt: process(clk, nReset) begin if (nReset = '0') then dcnt <= (others => '0'); elsif (clk'event and clk = '1') then if (rst = '1') then dcnt <= (others => '0'); elsif (ld = '1') then dcnt <= (others => '1'); -- load counter with 7 elsif (shift = '1') then dcnt <= dcnt -1; end if; end if; end process data_cnt; cnt_done <= '1' when (dcnt = 0) else '0'; -- -- state machine -- statemachine : block type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); signal c_state : states; begin -- -- command interpreter, translate complex commands into simpler I2C commands -- nxt_state_decoder: process(clk, nReset) begin if (nReset = '0') then core_cmd <= I2C_CMD_NOP; core_txd <= '0'; shift <= '0'; ld <= '0'; host_ack <= '0'; c_state <= st_idle; ack_out <= '0'; elsif (clk'event and clk = '1') then if (rst = '1' or al = '1') then core_cmd <= I2C_CMD_NOP; core_txd <= '0'; shift <= '0'; ld <= '0'; host_ack <= '0'; c_state <= st_idle; ack_out <= '0'; else -- initialy reset all signal core_txd <= sr(7); shift <= '0'; ld <= '0'; host_ack <= '0'; case c_state is when st_idle => if (go = '1') then if (start = '1') then c_state <= st_start; core_cmd <= I2C_CMD_START; elsif (read = '1') then c_state <= st_read; core_cmd <= I2C_CMD_READ; elsif (write = '1') then c_state <= st_write; core_cmd <= I2C_CMD_WRITE; else -- stop c_state <= st_stop; core_cmd <= I2C_CMD_STOP; end if; ld <= '1'; end if; when st_start => if (core_ack = '1') then if (read = '1') then c_state <= st_read; core_cmd <= I2C_CMD_READ; else c_state <= st_write; core_cmd <= I2C_CMD_WRITE; end if; ld <= '1'; end if; when st_write => if (core_ack = '1') then if (cnt_done = '1') then c_state <= st_ack; core_cmd <= I2C_CMD_READ; else c_state <= st_write; -- stay in same state core_cmd <= I2C_CMD_WRITE; -- write next bit shift <= '1'; end if; end if; when st_read => if (core_ack = '1') then if (cnt_done = '1') then c_state <= st_ack; core_cmd <= I2C_CMD_WRITE; else c_state <= st_read; -- stay in same state core_cmd <= I2C_CMD_READ; -- read next bit end if; shift <= '1'; core_txd <= ack_in; end if; when st_ack => if (core_ack = '1') then -- check for stop; Should a STOP command be generated ? if (stop = '1') then c_state <= st_stop; core_cmd <= I2C_CMD_STOP; else c_state <= st_idle; core_cmd <= I2C_CMD_NOP; -- generate command acknowledge signal host_ack <= '1'; end if; -- assign ack_out output to core_rxd (contains last received bit) ack_out <= core_rxd; core_txd <= '1'; else core_txd <= ack_in; end if; when st_stop => if (core_ack = '1') then c_state <= st_idle; core_cmd <= I2C_CMD_NOP; -- generate command acknowledge signal host_ack <= '1'; end if; when others => -- illegal states c_state <= st_idle; core_cmd <= I2C_CMD_NOP; report ("Byte controller entered illegal state."); end case; end if; end if; end process nxt_state_decoder; end block statemachine; end architecture structural;
------------------------------------------------------------------------------- -- axi_quad_spi.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- ******************************************************************* -- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.* -- ** * -- ** This file contains confidential and proprietary information * -- ** of Xilinx, Inc. and is protected under U.S. and * -- ** international copyright and other intellectual property * -- ** laws. * -- ** * -- ** DISCLAIMER * -- ** This disclaimer is not a license and does not grant any * -- ** rights to the materials distributed herewith. Except as * -- ** otherwise provided in a valid license issued to you by * -- ** Xilinx, and to the maximum extent permitted by applicable * -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * -- ** (2) Xilinx shall not be liable (whether in contract or tort, * -- ** including negligence, or under any other theory of * -- ** liability) for any loss or damage of any kind or nature * -- ** related to, arising under or in connection with these * -- ** materials, including for any direct, or any indirect, * -- ** special, incidental, or consequential loss or damage * -- ** (including loss of data, profits, goodwill, or any type of * -- ** loss or damage suffered as a result of any action brought * -- ** by a third party) even if such damage or loss was * -- ** reasonably foreseeable or Xilinx had been advised of the * -- ** possibility of the same. * -- ** * -- ** CRITICAL APPLICATIONS * -- ** Xilinx products are not designed or intended to be fail- * -- ** safe, or for use in any application requiring fail-safe * -- ** performance, such as life-support or safety devices or * -- ** systems, Class III medical devices, nuclear facilities, * -- ** applications related to the deployment of airbags, or any * -- ** other applications that could lead to death, personal * -- ** injury, or severe property or environmental damage * -- ** (individually and collectively, "Critical * -- ** Applications"). Customer assumes the sole risk and * -- ** liability of any use of Xilinx products in Critical * -- ** Applications, subject only to applicable laws and * -- ** regulations governing limitations on product liability. * -- ** * -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * -- ** PART OF THIS FILE AT ALL TIMES. * -- ******************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_quad_spi.vhd -- Version: v3.0 -- Description: This is the top-level design file for the AXI Quad SPI core. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.conv_std_logic_vector; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use ieee.std_logic_misc.all; -- library unsigned is used for overloading of "=" which allows integer to -- be compared to std_logic_vector use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.FD; use unisim.vcomponents.FDRE; use UNISIM.vcomponents.all; library axi_lite_ipif_v3_0_4; use axi_lite_ipif_v3_0_4.axi_lite_ipif; use axi_lite_ipif_v3_0_4.ipif_pkg.all; library axi_quad_spi_v3_2_8; use axi_quad_spi_v3_2_8.all; ------------------------------------------------------------------------------- entity axi_quad_spi is generic( -- Async_Clk parameter is added only for Vivado, it is not used in the design, this is -- NON HDL parameter Async_Clk : integer := 0; -- General Parameters C_FAMILY : string := "virtex7"; C_SELECT_XPM : integer := 1; C_SUB_FAMILY : string := "virtex7"; C_INSTANCE : string := "axi_quad_spi_inst"; ------------------------- C_SPI_MEM_ADDR_BITS : integer := 24; -- allowed values are 24 or 32 only and used in XIP mode C_TYPE_OF_AXI4_INTERFACE : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode C_XIP_MODE : integer range 0 to 1 := 0;--default NON XIP Mode C_UC_FAMILY : integer range 0 to 1 := 0;--default NON XIP Mode --C_AXI4_CLK_PS : integer := 10000;--AXI clock period --C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period C_FIFO_DEPTH : integer := 256;-- allowed 0,16,256. C_SCK_RATIO : integer := 16;--default in legacy mode C_NUM_SS_BITS : integer range 1 to 32:= 1; C_NUM_TRANSFER_BITS : integer := 8; -- allowed 8, 16, 32 ------------------------- C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating -- Standard, Dual or Quad mode -- in Ports as well as internal -- functionality C_USE_STARTUP : integer range 0 to 1 := 1; -- C_SPI_MEMORY : integer range 0 to 3 := 1; -- 0 - mixed mode, -- 1 - winbond, -- 2 - numonyx -- 3 - spansion -- used to differentiate -- internal look up table -- for commands. ------------------------- -- AXI4 Lite Interface Parameters *as max address is 7c, only 7 address bits are used C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7; C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; ------------------------- --*C_BASEADDR : std_logic_vector := x"FFFFFFFF"; --*C_HIGHADDR : std_logic_vector := x"00000000"; ------------------------- -- AXI4 Full Interface Parameters *as max 24 bits of address are supported on SPI interface, only 24 address bits are used C_S_AXI4_ADDR_WIDTH : integer ;--range 24 to 24 := 24; C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32; C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4 ; C_SHARED_STARTUP : integer range 0 to 1 := 0; ------------------------- -- To FIX CR# 685366, below lines are added again in RTL (Vivado Requirement), but these parameters are not used in the core RTL C_S_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF"; C_S_AXI4_HIGHADDR : std_logic_vector := x"00000000"; ------------------------- C_LSB_STUP : integer range 0 to 1 := 0 ); port( -- external async clock for SPI interface logic ext_spi_clk : in std_logic; -- axi4 lite interface clk and reset signals s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; -- axi4 full interface clk and reset signals s_axi4_aclk : in std_logic; s_axi4_aresetn : in std_logic; ------------------------------- ------------------------------- --*axi4 lite port interface* -- ------------------------------- ------------------------------- -- axi write address channel signals --------------- s_axi_awaddr : in std_logic_vector (6 downto 0);--((C_S_AXI_ADDR_WIDTH-1) downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; --------------- -- axi write data channel signals --------------- s_axi_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0); s_axi_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI_DATA_WIDTH/8)-1) downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; --------------- -- axi write response channel signals --------------- s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; --------------- -- axi read address channel signals --------------- s_axi_araddr : in std_logic_vector(6 downto 0); -- ((C_S_AXI_ADDR_WIDTH-1) downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; --------------- -- axi read address channel signals --------------- s_axi_rdata : out std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; ------------------------------- ------------------------------- --*axi4 full port interface* -- ------------------------------- ------------------------------------ -- axi write address Channel Signals ------------------------------------ s_axi4_awid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); s_axi4_awaddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0); --((C_S_AXI4_ADDR_WIDTH-1) downto 0); s_axi4_awlen : in std_logic_vector(7 downto 0); s_axi4_awsize : in std_logic_vector(2 downto 0); s_axi4_awburst : in std_logic_vector(1 downto 0); s_axi4_awlock : in std_logic; -- not supported in design s_axi4_awcache : in std_logic_vector(3 downto 0);-- not supported in design s_axi4_awprot : in std_logic_vector(2 downto 0);-- not supported in design s_axi4_awvalid : in std_logic; s_axi4_awready : out std_logic; --------------------------------------- -- axi4 full write Data Channel Signals --------------------------------------- s_axi4_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI4_DATA_WIDTH-1)downto 0); s_axi4_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI4_DATA_WIDTH/8)-1) downto 0); s_axi4_wlast : in std_logic; s_axi4_wvalid : in std_logic; s_axi4_wready : out std_logic; ------------------------------------------- -- axi4 full write Response Channel Signals ------------------------------------------- s_axi4_bid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); s_axi4_bresp : out std_logic_vector(1 downto 0); s_axi4_bvalid : out std_logic; s_axi4_bready : in std_logic; ----------------------------------- -- axi read address Channel Signals ----------------------------------- s_axi4_arid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); s_axi4_araddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0); s_axi4_arlen : in std_logic_vector(7 downto 0); s_axi4_arsize : in std_logic_vector(2 downto 0); s_axi4_arburst : in std_logic_vector(1 downto 0); s_axi4_arlock : in std_logic; -- not supported in design s_axi4_arcache : in std_logic_vector(3 downto 0);-- not supported in design s_axi4_arprot : in std_logic_vector(2 downto 0);-- not supported in design s_axi4_arvalid : in std_logic; s_axi4_arready : out std_logic; -------------------------------- -- axi read data Channel Signals -------------------------------- s_axi4_rid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); s_axi4_rdata : out std_logic_vector(31 downto 0);--((C_S_AXI4_DATA_WIDTH-1) downto 0); s_axi4_rresp : out std_logic_vector(1 downto 0); s_axi4_rlast : out std_logic; s_axi4_rvalid : out std_logic; s_axi4_rready : in std_logic; -------------------------------- ------------------------------- --*SPI port interface * -- ------------------------------- io0_i : in std_logic; -- MOSI signal in standard SPI io0_o : out std_logic; io0_t : out std_logic; ------------------------------- io1_i : in std_logic; -- MISO signal in standard SPI io1_o : out std_logic; io1_t : out std_logic; ----------------- -- quad mode pins ----------------- io2_i : in std_logic; io2_o : out std_logic; io2_t : out std_logic; --------------- io3_i : in std_logic; io3_o : out std_logic; io3_t : out std_logic; --------------------------------- -- common pins ---------------- spisel : in std_logic; ----- sck_i : in std_logic; sck_o : out std_logic; sck_t : out std_logic; ----- ss_i : in std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP); ss_o : out std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP); ss_t : out std_logic; ------------------------ -- STARTUP INTERFACE ------------------------ cfgclk : out std_logic; -- FGCLK , -- 1-bit output: Configuration main clock output cfgmclk : out std_logic; -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output eos : out std_logic; -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup. preq : out std_logic; -- REQ , -- 1-bit output: PROGRAM request to fabric output clk : in std_logic; -- input gsr : in std_logic; -- input gts : in std_logic; -- input keyclearb : in std_logic; -- input usrcclkts : in std_logic; -- input usrdoneo : in std_logic; -- input usrdonets : in std_logic; -- input pack : in std_logic; -- input ---------------------- -- INTERRUPT INTERFACE ---------------------- ip2intc_irpt : out std_logic --------------------------------- ); ------------------------------- -- Fan-out attributes for XST attribute MAX_FANOUT : string; attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000"; attribute MAX_FANOUT of S_AXI4_ACLK : signal is "10000"; attribute MAX_FANOUT of EXT_SPI_CLK : signal is "10000"; attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000"; attribute MAX_FANOUT of S_AXI4_ARESETN : signal is "10000"; attribute INITIALVAL : string; attribute INITIALVAL of SPISEL : signal is "VCC"; ------------------------------- end entity axi_quad_spi; -------------------------------------------------------------------------------- architecture imp of axi_quad_spi is ---------------------------------------------------------------------------------- -- below attributes are added to reduce the synth warnings in Vivado tool attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ---------------------------------------------------------------------------------- --------------------------------------------------------------------------------- ---- constant added for webtalk information --------------------------------------------------------------------------------- -- constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_quad_spi,{" -- & "C_FAMILY = " & C_FAMILY -- & ",C_SUB_FAMILY = " & C_SUB_FAMILY -- & ",C_INSTANCE = " & C_INSTANCE -- & ",C_S_AXI_ADDR_WIDTH = " & integer'image(C_S_AXI_ADDR_WIDTH) -- & ",C_S_AXI_DATA_WIDTH = " & integer'image(C_S_AXI_DATA_WIDTH) -- & ",C_S_AXI4_ADDR_WIDTH = " & integer'image(C_S_AXI4_ADDR_WIDTH) -- & ",C_S_AXI4_DATA_WIDTH = " & integer'image(C_S_AXI4_DATA_WIDTH) -- & ",C_S_AXI4_ID_WIDTH = " & integer'image(C_S_AXI4_ID_WIDTH) -- & ",C_FIFO_DEPTH = " & integer'image(C_FIFO_DEPTH) -- & ",C_SCK_RATIO = " & integer'image(C_SCK_RATIO) -- & ",C_NUM_SS_BITS = " & integer'image(C_NUM_SS_BITS) -- & ",C_NUM_TRANSFER_BITS = " & integer'image(C_NUM_TRANSFER_BITS) -- & ",C_USE_STARTUP = " & integer'image(C_USE_STARTUP) -- & ",C_SPI_MODE = " & integer'image(C_SPI_MODE) -- & ",C_SPI_MEMORY = " & integer'image(C_SPI_MEMORY) -- & ",C_TYPE_OF_AXI4_INTERFACE = " & integer'image(C_TYPE_OF_AXI4_INTERFACE) -- & ",C_XIP_MODE = " & integer'image(C_XIP_MODE) -- & "}"; -- -- attribute CORE_GENERATION_INFO : string; -- attribute CORE_GENERATION_INFO of imp : architecture is C_CORE_GENERATION_INFO; ------------------------------------------------------------- ------------------------------------------------------------- -- Function Declaration ------------------------------------------------------------- -- get_fifo_presence - This function returns the 0 or 1 based upon the FIFO Depth. -- function get_fifo_presence(C_FIFO_DEPTH: integer) return integer is ----- begin ----- if(C_FIFO_DEPTH = 0)then return 0; else return 1; end if; end function get_fifo_presence; function get_fifo_depth(C_FIFO_EXIST: integer; C_FIFO_DEPTH : integer) return integer is ----- begin ----- if(C_FIFO_EXIST = 1)then return C_FIFO_DEPTH; else return 64; -- to ensure that log2 functions does not become invalid end if; end function get_fifo_depth; ------------------------------ function get_fifo_occupancy_count(C_FIFO_DEPTH: integer) return integer is ----- variable j : integer := 0; variable k : integer := 0; ----- begin ----- if (C_FIFO_DEPTH = 0) then return 4; else for i in 0 to 11 loop if(2**i >= C_FIFO_DEPTH) then if(k = 0) then j := i; end if; k := 1; end if; end loop; return j; end if; ------- end function get_fifo_occupancy_count; ------------------------------ -- Constant declarations ------------------------------ --------------------- ******************* ------------------------------------ -- Core Parameters --------------------- ******************* ------------------------------------ -- constant C_FIFO_EXIST : integer := get_fifo_presence(C_FIFO_DEPTH); constant C_FIFO_DEPTH_UPDATED : integer := get_fifo_depth(C_FIFO_EXIST, C_FIFO_DEPTH); -- width of control register constant C_SPICR_REG_WIDTH : integer := 10;-- refer DS -- width of status register constant C_SPISR_REG_WIDTH : integer := 11;-- refer DS -- count the counter width for calculating FIFO occupancy constant C_OCCUPANCY_NUM_BITS : integer := get_fifo_occupancy_count(C_FIFO_DEPTH_UPDATED); -- width of spi shift register constant C_SPI_NUM_BITS_REG : integer := 8;-- this is fixed constant C_NUM_SPI_REGS : integer := 8;-- this is fixed constant C_IPISR_IPIER_BITS : integer := 14;-- total 14 interrupts - 0 to 13 --------------------- ******************* ------------------------------------ -- AXI lite parameters --------------------- ******************* ------------------------------------ constant C_S_AXI_SPI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000007c"; constant C_USE_WSTRB : integer := 1; constant C_DPHASE_TIMEOUT : integer := 20; -- interupt mode constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to (C_IPISR_IPIER_BITS-1)):= ( others => INTR_REG_EVENT -- when C_SPI_MODE = 0 -- Seven interrupts if C_FIFO_DEPTH_UPDATED = 0 -- OR -- Eight interrupts if C_FIFO_DEPTH_UPDATED = 0 and slave mode ----------------------- OR --------------------------- -- Nine interrupts if C_FIFO_DEPTH_UPDATED = 16 and slave mode -- OR -- Seven interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode -- when C_SPI_MODE = 1 or 2 -- Thirteen interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode ); constant ZEROES : std_logic_vector(31 downto 0):= X"00000000"; -- this constant is defined as the start of SPI register addresses. constant C_IP_REG_ADDR_OFFSET : std_logic_vector := X"00000060"; -- Address range array constant C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( -- interrupt address base & high range --ZEROES & C_BASEADDR, --ZEROES & (C_BASEADDR or X"0000003F"),--interrupt address higher range ZEROES & X"00000000", ZEROES & X"0000003F",--interrupt address higher range -- soft reset register base & high addr --ZEROES & (C_BASEADDR or X"00000040"), --ZEROES & (C_BASEADDR or X"00000043"),--soft reset register high addr ZEROES & X"00000040", -- ZEROES & X"00000043",--soft reset register high addr ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes -- SPI registers Base & High Address -- Range is 60 to 78 -- for internal registers --ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET), --ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000018") ZEROES & C_IP_REG_ADDR_OFFSET, ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018") ); -- AXI4 Address range array constant C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL: SLV64_ARRAY_TYPE := ( -- interrupt address base & high range --*ZEROES & C_S_AXI4_BASEADDR, --*ZEROES & (C_S_AXI4_BASEADDR or X"0000003F"),--interrupt address higher range ZEROES & X"00000000", ZEROES & X"0000003F",--soft reset register high addr -- soft reset register base & high addr --*ZEROES & (C_S_AXI4_BASEADDR or X"00000040"), --*ZEROES & (C_S_AXI4_BASEADDR or X"00000043"),--soft reset register high addr ZEROES & X"00000040", -- ZEROES & X"00000043",--soft reset register high addr ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes -- SPI registers Base & High Address -- Range is 60 to 78 -- for internal registers ZEROES & (C_IP_REG_ADDR_OFFSET), ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018") ); -- No. of CE's required per address range constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => 16 , -- 16 CEs required for interrupt --1 => 1, -- 1 CE required for soft reset 1 => 8, -- 8 CE required for Addressing Holes in soft reset 2 => C_NUM_SPI_REGS ); -- no. of Chip Enable Signals constant C_NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY); -- no. of Chip Select Signals constant C_NUM_CS_SIGNALS : integer := (C_ARD_ADDR_RANGE_ARRAY'LENGTH/2); ----------------------------- ----------------------- ******************* ------------------------------------ ---- XIP Mode parameters ----------------------- ******************* ------------------------------------ -- No. of XIP SPI registers constant C_NUM_XIP_SPI_REGS : integer := 2;-- this is fixed -- width of XIP control register constant C_XIP_SPICR_REG_WIDTH: integer := 2;-- refer DS -- width of XIP status register constant C_XIP_SPISR_REG_WIDTH: integer := 5;-- refer DS -- Address range array constant C_XIP_LITE_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( -- XIP SPI registers Base & High Address -- Range is 60 to 64 -- for internal registers --*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET), --*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000004") ZEROES & (C_IP_REG_ADDR_OFFSET), ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000004") ); -- No. of CE's required per address range constant C_XIP_LITE_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => C_NUM_XIP_SPI_REGS -- 2 CEs required for XIP lite interface ); -- no. of Chip Enable Signals constant C_NUM_XIP_CE_SIGNALS : integer := calc_num_ce(C_XIP_LITE_ARD_NUM_CE_ARRAY); function assign_addr_bits (addr_bits_info : integer) return string is variable addr_width_24 : integer:= 24; variable addr_width_32 : integer:= 32; begin if addr_bits_info = 24 then -- old logic for 24 bit addressing return X"00FFFFFF";--addr_width_24; else return X"FFFFFFFF";--addr_width_32; end if; end function assign_addr_bits; constant C_XIP_ADDR_OFFSET : std_logic_vector := X"FFFFFFFF";--assign_addr_bits(C_SPI_MEM_ADDR_BITS); -- X"00FFFFFF"; -- XIP Full Interface Address range array constant C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( -- XIP SPI registers Base & High Address -- Range is 60 to 64 -- for internal registers --*ZEROES & (C_S_AXI4_BASEADDR), --*ZEROES & (C_S_AXI4_BASEADDR or C_24_BIT_ADDR_OFFSET) ZEROES & X"00000000", ZEROES & C_XIP_ADDR_OFFSET ); -- No. of CE's required per address range constant C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => C_NUM_XIP_SPI_REGS -- 0 CEs required for XIP Full interface ); --------------------------------------------------------------------------------- constant C_XIP_FIFO_DEPTH : integer := 264; ------------------------------------------------------------------------------- ----Startup Signals signal di_int : std_logic_vector(3 downto 0); -- output signal di_int_sync : std_logic_vector(3 downto 0); -- output signal dts_int : std_logic_vector(3 downto 0); -- input signal do_int : std_logic_vector(3 downto 0); -- input -- signal declaration signal bus2ip_clk : std_logic; signal bus2ip_be_int : std_logic_vector (((C_S_AXI_DATA_WIDTH/8)-1)downto 0); signal bus2ip_rdce_int : std_logic_vector ((C_NUM_CE_SIGNALS-1)downto 0); signal bus2ip_wrce_int : std_logic_vector ((C_NUM_CE_SIGNALS-1)downto 0); signal bus2ip_data_int : std_logic_vector ((C_S_AXI_DATA_WIDTH-1)downto 0); signal ip2bus_data_int : std_logic_vector ((C_S_AXI_DATA_WIDTH-1)downto 0 ) := (others => '0'); signal ip2bus_wrack_int : std_logic := '0'; signal ip2bus_rdack_int : std_logic := '0'; signal ip2bus_error_int : std_logic := '0'; signal bus2ip_reset_int : std_logic; signal bus2ip_reset_ipif_inverted: std_logic; -- XIP signals signal bus2ip_xip_rdce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1); signal bus2ip_xip_wrce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1); signal io0_i_sync : std_logic; signal io1_i_sync : std_logic; signal io2_i_sync : std_logic; signal io3_i_sync : std_logic; signal io0_i_sync_int : std_logic; signal io1_i_sync_int : std_logic; signal io2_i_sync_int : std_logic; signal io3_i_sync_int : std_logic; signal io0_i_int : std_logic; signal io1_i_int : std_logic; signal io2_i_int : std_logic; signal io3_i_int : std_logic; signal io0_o_int : std_logic; signal io1_o_int : std_logic; signal io2_o_int : std_logic; signal io3_o_int : std_logic; signal io0_t_int : std_logic; signal io1_t_int : std_logic; signal io2_t_int : std_logic; signal io3_t_int : std_logic; signal burst_tr_int : std_logic; signal rready_int : std_logic; signal bus2ip_reset_ipif4_inverted : std_logic; signal fcsbo_int : std_logic; signal ss_o_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0); signal ss_t_int : std_logic; signal ss_i_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0); signal fcsbts_int : std_logic; signal startup_di : std_logic_vector(1 downto 0); -- output signal startup_do : std_logic_vector(1 downto 0) := (others => '1'); -- output signal startup_dts : std_logic_vector(1 downto 0) := (others => '0'); -- output ----- begin ----- --------STUP and XIP mode STARTUP_USED_1: if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1) generate begin DI_INT_IO3_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => di_int_sync(3), C => EXT_SPI_CLK, D => di_int(3) --MOSI_I ); DI_INT_IO2_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => di_int_sync(2), C => EXT_SPI_CLK, D => di_int(2) -- MISO_I ); DI_INT_IO1_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => di_int_sync(1), C => EXT_SPI_CLK, D => di_int(1) ); ----------------------- DI_INT_IO0_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => di_int_sync(0), C => EXT_SPI_CLK, D => di_int(0) ); io0_i_sync_int <= di_int_sync(0); io1_i_sync_int <= di_int_sync(1); io2_i_sync_int <= di_int_sync(2); io3_i_sync_int <= di_int_sync(3); end generate STARTUP_USED_1; DATA_STARTUP_EN : if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1 and C_XIP_MODE = 1) generate ----- begin ----- do_int(0) <= io0_o_int; dts_int(0) <= io0_t_int ; do_int(1) <= io1_o_int; dts_int(1) <= io1_t_int ; fcsbo_int <= ss_o_int(0); fcsbts_int <= ss_t_int; NUM_SS : if (C_NUM_SS_BITS = 1) generate begin ss_o <= (others => '0'); ss_t <= '0'; end generate NUM_SS; NUM_SS_G1 : if (C_NUM_SS_BITS > 1) generate begin ss_i_int <= ss_i((C_NUM_SS_BITS-1) downto 1) & '1'; ss_o <= ss_o_int((C_NUM_SS_BITS-1) downto 1);-- & '0'; ss_t <= ss_t_int; end generate NUM_SS_G1; DATA_OUT_NQUAD: if C_SPI_MODE = 0 or C_SPI_MODE = 1 generate begin startup_di <= di_int_sync(3) & di_int_sync(2); do_int(2) <= startup_do(0); do_int(3) <= startup_do(1); dts_int(2) <= startup_dts(0); dts_int(3) <= startup_dts(1); --do <= do_int(3) & do_int(1); --dts <= dts_int(3) & dts_int(1); end generate DATA_OUT_NQUAD; DATA_OUT_QUAD: if C_SPI_MODE = 2 generate begin --di <= "00";--di_int(3) & di_int(2); do_int(2) <= io2_o_int;--do(2); do_int(3) <= io3_o_int;--do(1); --do <= do_int(3) & do_int(1); dts_int(2) <= io2_t_int;--dts_int(3) & dts_int(1); dts_int(3) <= io3_t_int;--dts_int(3) & dts_int(1); end generate DATA_OUT_QUAD; end generate DATA_STARTUP_EN; DATA_STARTUP_DIS : if ((C_USE_STARTUP = 0 or (C_USE_STARTUP = 1 and C_UC_FAMILY = 0)) and C_XIP_MODE = 1) generate ----- begin ----- io0_o <= io0_o_int; io0_t <= io0_t_int; io1_t <= io1_t_int; io1_o <= io1_o_int; io2_o <= io2_o_int; io2_t <= io2_t_int; io3_t <= io3_t_int; io3_o <= io3_o_int; ss_i_int <= ss_i; ss_o <= ss_o_int;-- & '0'; ss_t <= ss_t_int; end generate DATA_STARTUP_DIS; --------STUP and XIP mode off STARTUP_USED: if (C_USE_STARTUP = 0 or C_UC_FAMILY = 0) generate begin io0_i_sync_int <= io0_i_sync; io1_i_sync_int <= io1_i_sync; io2_i_sync_int <= io2_i_sync; io3_i_sync_int <= io3_i_sync; end generate STARTUP_USED; IO0_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => io0_i_sync, C => ext_spi_clk, D => io0_i --MOSI_I ); IO1_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => io1_i_sync, C => ext_spi_clk, D => io1_i -- MISO_I ); IO2_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => io2_i_sync, C => ext_spi_clk, D => io2_i ); ----------------------- IO3_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => io3_i_sync, C => ext_spi_clk, D => io3_i ); ----------------------- ------------------------------------------------------------------------------- --------------- -- AXI_QUAD_SPI_LEGACY_MODE: This logic is legacy AXI4 Lite interface based design --------------- QSPI_LEGACY_MD_GEN : if C_TYPE_OF_AXI4_INTERFACE = 0 generate --------------- begin ----- AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif generic map ( ---------------------------------------------------- C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , ---------------------------------------------------- C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE , C_USE_WSTRB => C_USE_WSTRB , C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT , ---------------------------------------------------- C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY , C_FAMILY => C_FAMILY ---------------------------------------------------- ) port map ( --------------------------------------------------------- S_AXI_ACLK => s_axi_aclk, -- in S_AXI_ARESETN => s_axi_aresetn, -- in --------------------------------------------------------- S_AXI_AWADDR => s_axi_awaddr, -- in S_AXI_AWVALID => s_axi_awvalid, -- in S_AXI_AWREADY => s_axi_awready, -- out S_AXI_WDATA => s_axi_wdata, -- in S_AXI_WSTRB => s_axi_wstrb, -- in S_AXI_WVALID => s_axi_wvalid, -- in S_AXI_WREADY => s_axi_wready, -- out S_AXI_BRESP => s_axi_bresp, -- out S_AXI_BVALID => s_axi_bvalid, -- out S_AXI_BREADY => s_axi_bready, -- in S_AXI_ARADDR => s_axi_araddr, -- in S_AXI_ARVALID => s_axi_arvalid, -- in S_AXI_ARREADY => s_axi_arready, -- out S_AXI_RDATA => s_axi_rdata, -- out S_AXI_RRESP => s_axi_rresp, -- out S_AXI_RVALID => s_axi_rvalid, -- out S_AXI_RREADY => s_axi_rready, -- in ---------------------------------------------------------- -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, -- out Bus2IP_Resetn => bus2ip_reset_int, -- out ---------------------------------------------------------- Bus2IP_Addr => open, -- out -- not used signal Bus2IP_RNW => open, -- out Bus2IP_BE => bus2ip_be_int, -- out Bus2IP_CS => open, -- out -- not used signal Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian Bus2IP_Data => bus2ip_data_int, -- out -- little endian ---------------------------------------------------------- IP2Bus_Data => ip2bus_data_int, -- in -- little endian IP2Bus_WrAck => ip2bus_wrack_int, -- in IP2Bus_RdAck => ip2bus_rdack_int, -- in IP2Bus_Error => ip2bus_error_int -- in ---------------------------------------------------------- ); ---------------------- --REG_RST_FRM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RST_FRM_IPIF: process (S_AXI_ACLK) is begin if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then bus2ip_reset_ipif_inverted <= not(bus2ip_reset_int); end if; end process REG_RST_FRM_IPIF; -- ---------------------------------------------------------------------- -- -- Instansiating the SPI core -- ---------------------------------------------------------------------- QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_2_8.qspi_core_interface generic map ( ------------------------------------------------ -- AXI parameters C_LSB_STUP => C_LSB_STUP, C_FAMILY => C_FAMILY , Async_Clk => Async_Clk , C_SUB_FAMILY => C_FAMILY , C_UC_FAMILY => C_UC_FAMILY , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, ------------------------------------------------ -- local constants C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS , ------------------------------------------------ -- SPI parameters --C_AXI4_CLK_PS => C_AXI4_CLK_PS , --C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , C_SCK_RATIO => C_SCK_RATIO , C_NUM_SS_BITS => C_NUM_SS_BITS , C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS, C_SPI_MODE => C_SPI_MODE , C_USE_STARTUP => C_USE_STARTUP , C_SPI_MEMORY => C_SPI_MEMORY , C_SELECT_XPM => C_SELECT_XPM , C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, ------------------------------------------------ -- local constants C_FIFO_EXIST => C_FIFO_EXIST , C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG, C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS, C_SHARED_STARTUP => C_SHARED_STARTUP, ------------------------------------------------ -- local constants C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, ------------------------------------------------ -- local constants C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH , C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH ) port map ( EXT_SPI_CLK => ext_spi_clk, -- in --------------------------------------------------- -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, -- in Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in --------------------------------------------------- Bus2IP_BE => bus2ip_be_int, -- in vector -- Bus2IP_CS => bus2ip_cs_int, Bus2IP_RdCE => bus2ip_rdce_int, -- in vector Bus2IP_WrCE => bus2ip_wrce_int, -- in vector Bus2IP_Data => bus2ip_data_int, -- in vector --------------------------------------------------- IP2Bus_Data => ip2bus_data_int, -- out vector IP2Bus_WrAck => ip2bus_wrack_int, -- out IP2Bus_RdAck => ip2bus_rdack_int, -- out IP2Bus_Error => ip2bus_error_int, -- out --------------------------------------------------- burst_tr => burst_tr_int, rready => '0', WVALID => '0', --------------------------------------------------- --SPI Ports IO0_I => io0_i_sync,-- mosi IO0_O => io0_o, IO0_T => io0_t, ----- IO1_I => io1_i_sync,-- miso IO1_O => io1_o, IO1_T => io1_t, ----- IO2_I => io2_i_sync, IO2_O => io2_o, IO2_T => io2_t, ----- IO3_I => io3_i_sync, IO3_O => io3_o, IO3_T => io3_t, ----- SCK_I => sck_i, SCK_O => sck_o, SCK_T => sck_t, ----- SPISEL => spisel, ----- SS_I => ss_i, SS_O => ss_o, SS_T => ss_t, ----- IP2INTC_Irpt => ip2intc_irpt, CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup. PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output DI => startup_di, -- output DO => startup_do, -- 4-bit input DTS => startup_dts, -- 4-bit input GSR => gsr, -- 1-bit input, SetReset CLK => clk, -- 1-bit input, SetReset GTS => gts, -- 1-bit input KEYCLEARB => keyclearb, --1-bit input USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input USRDONETS => usrdonets, -- SRDONETS -- 1-bit input PACK => pack ----- ); burst_tr_int <= '0'; end generate QSPI_LEGACY_MD_GEN; ------------------------------------------------------------------------------ QSPI_ENHANCED_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 0 generate --------------- begin ----- -- AXI_QUAD_SPI_I: core instance QSPI_ENHANCED_MD_IPIF_I : entity axi_quad_spi_v3_2_8.axi_qspi_enhanced_mode generic map( -- General Parameters C_FAMILY => C_FAMILY , -- : string := "virtex7"; C_SUB_FAMILY => C_FAMILY , -- : string := "virtex7"; ------------------------- --C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, -- : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode --C_XIP_MODE => C_XIP_MODE , -- : integer range 0 to 1 := 0;--default NON XIP Mode --C_AXI4_CLK_PS => C_AXI4_CLK_PS , -- : integer := 10000;--AXI clock period --C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , -- : integer := 10000;--ext clock period C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , -- : integer := 16;-- allowed 0,16,256. C_SCK_RATIO => C_SCK_RATIO , -- : integer := 16;--default in legacy mode C_NUM_SS_BITS => C_NUM_SS_BITS , -- : integer range 1 to 32:= 1; C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS , -- : integer := 8; -- allowed 8, 16, 32 ------------------------- C_SPI_MODE => C_SPI_MODE , -- : integer range 0 to 2 := 0; -- used for differentiating C_USE_STARTUP => C_USE_STARTUP , -- : integer range 0 to 1 := 1; -- C_SPI_MEMORY => C_SPI_MEMORY , -- : integer range 0 to 2 := 1; -- 0 - mixed mode, ------------------------- -- AXI4 Full Interface Parameters C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH , -- : integer range 32 to 32 := 32; C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer range 32 to 32 := 32; C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH , -- : integer range 1 to 16 := 4; ------------------------- --*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR , -- : std_logic_vector := x"FFFFFFFF"; --*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR , -- : std_logic_vector := x"00000000" ------------------------- C_S_AXI_SPI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE , ------------------------- C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL , C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY , C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS -- newly added ) port map( -- external async clock for SPI interface logic EXT_SPI_CLK => ext_spi_clk , -- : in std_logic; ----------------------------------- S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic; S_AXI4_ARESETN => s_axi4_aresetn , -- : in std_logic; ------------------------------- ------------------------------- --*AXI4 Full port interface* -- ------------------------------- ------------------------------------ -- AXI Write Address channel signals ------------------------------------ S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0); S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0); S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0); S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0); S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic; S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic; --------------------------------------- -- AXI4 Full Write data channel signals --------------------------------------- S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0); S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0); S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic; S_AXI4_WVALID => s_axi4_wvalid, -- : in std_logic; S_AXI4_WREADY => s_axi4_wready, -- : out std_logic; ------------------------------------------- -- AXI4 Full Write response channel Signals ------------------------------------------- S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0); S_AXI4_BVALID => s_axi4_bvalid, -- : out std_logic; S_AXI4_BREADY => s_axi4_bready, -- : in std_logic; ----------------------------------- -- AXI Read Address channel signals ----------------------------------- S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0); S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0); S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0); S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0); S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic; S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic; -------------------------------- -- AXI Read Data Channel signals -------------------------------- S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0); S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0); S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic; S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic; S_AXI4_RREADY => s_axi4_rready, -- : in std_logic; ---------------------------------------------------------- -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, -- out Bus2IP_Reset => bus2ip_reset_ipif_inverted , -- out ---------------------------------------------------------- -- Bus2IP_Addr => open, -- out -- not used signal Bus2IP_RNW => open, -- out Bus2IP_BE => bus2ip_be_int, -- out Bus2IP_CS => open, -- out -- not used signal Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian Bus2IP_Data => bus2ip_data_int, -- out -- little endian ---------------------------------------------------------- IP2Bus_Data => ip2bus_data_int, -- in -- little endian IP2Bus_WrAck => ip2bus_wrack_int, -- in IP2Bus_RdAck => ip2bus_rdack_int, -- in IP2Bus_Error => ip2bus_error_int, -- in ---------------------------------------------------------- burst_tr => burst_tr_int, -- in rready => rready_int ); -- ---------------------------------------------------------------------- -- -- Instansiating the SPI core -- ---------------------------------------------------------------------- QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_2_8.qspi_core_interface generic map ( ------------------------------------------------ -- AXI parameters C_LSB_STUP => C_LSB_STUP, C_FAMILY => C_FAMILY , Async_Clk => Async_Clk , C_SELECT_XPM => C_SELECT_XPM , C_SUB_FAMILY => C_FAMILY , C_UC_FAMILY => C_UC_FAMILY , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, ------------------------------------------------ -- local constants C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS , ------------------------------------------------ -- SPI parameters --C_AXI4_CLK_PS => C_AXI4_CLK_PS , --C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , C_SCK_RATIO => C_SCK_RATIO , C_NUM_SS_BITS => C_NUM_SS_BITS , C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS, C_SPI_MODE => C_SPI_MODE , C_USE_STARTUP => C_USE_STARTUP , C_SPI_MEMORY => C_SPI_MEMORY , C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, ------------------------------------------------ -- local constants C_FIFO_EXIST => C_FIFO_EXIST , C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG, C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS, C_SHARED_STARTUP => C_SHARED_STARTUP, ------------------------------------------------ -- local constants C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, ------------------------------------------------ -- local constants C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH , C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH ) port map ( EXT_SPI_CLK => EXT_SPI_CLK, -- in --------------------------------------------------- -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, -- in Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in --------------------------------------------------- Bus2IP_BE => bus2ip_be_int, -- in vector -- Bus2IP_CS => bus2ip_cs_int, Bus2IP_RdCE => bus2ip_rdce_int, -- in vector Bus2IP_WrCE => bus2ip_wrce_int, -- in vector Bus2IP_Data => bus2ip_data_int, -- in vector --------------------------------------------------- IP2Bus_Data => ip2bus_data_int, -- out vector IP2Bus_WrAck => ip2bus_wrack_int, -- out IP2Bus_RdAck => ip2bus_rdack_int, -- out IP2Bus_Error => ip2bus_error_int, -- out --------------------------------------------------- burst_tr => burst_tr_int, rready => rready_int, WVALID => S_AXI4_WVALID, --SPI Ports IO0_I => io0_i_sync,-- mosi IO0_O => io0_o, IO0_T => io0_t, ----- IO1_I => io1_i_sync,-- miso IO1_O => io1_o, IO1_T => io1_t, ----- IO2_I => io2_i_sync, IO2_O => io2_o, IO2_T => io2_t, ----- IO3_I => io3_i_sync, IO3_O => io3_o, IO3_T => io3_t, ----- SCK_I => sck_i, SCK_O => sck_o, SCK_T => sck_t, ----- SPISEL => spisel, ----- SS_I => ss_i, SS_O => ss_o, SS_T => ss_t, ----- IP2INTC_Irpt => ip2intc_irpt, CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup. PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output DI => startup_di, -- output DO => startup_do, -- 4-bit input DTS => startup_dts, -- 4-bit input CLK => clk, -- 1-bit input, SetReset GSR => gsr, -- 1-bit input, SetReset GTS => gts, -- 1-bit input KEYCLEARB => keyclearb, --1-bit input USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input USRDONETS => usrdonets, -- SRDONETS -- 1-bit input PACK => pack ----- ); end generate QSPI_ENHANCED_MD_GEN; -------------------------------------------------------------------------------- ----------------- -- XIP_MODE: This logic is used in XIP mode where AXI4 Lite & AXI4 Full interface -- used in the design --------------- XIP_MODE_GEN : if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 1 generate --------------- constant XIPCR : natural := 0; -- at address C_BASEADDR + 60 h constant XIPSR : natural := 1; -- signal bus2ip_reset_int : std_logic; signal bus2ip_clk_int : std_logic; signal bus2ip_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal ip2bus_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal ip2bus_wrack_int : std_logic; signal ip2bus_rdack_int : std_logic; signal ip2bus_error_int : std_logic; signal bus2ip_reset_ipif_inverted: std_logic; signal IP2Bus_XIPCR_WrAck : std_logic; signal IP2Bus_XIPCR_RdAck : std_logic; signal XIPCR_1_CPOL_int : std_logic; signal XIPCR_0_CPHA_int : std_logic; signal IP2Bus_XIPCR_Data_int : std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0); signal IP2Bus_XIPSR_Data_int : std_logic_vector((C_XIP_SPISR_REG_WIDTH-1) downto 0); signal TO_XIPSR_AXI_TR_ERR_int : std_logic; signal TO_XIPSR_mst_modf_err_int : std_logic; signal TO_XIPSR_axi_rx_full_int : std_logic; signal TO_XIPSR_axi_rx_empty_int : std_logic; signal xipsr_cpha_cpol_err_int :std_logic; signal xipsr_cmd_err_int :std_logic; signal ip2bus_xipsr_wrack :std_logic; signal ip2bus_xipsr_rdack :std_logic; signal xipsr_axi_tr_err_int :std_logic; signal xipsr_axi_tr_done_int :std_logic; signal ip2bus_xipsr_rdack_int :std_logic; signal ip2bus_xipsr_wrack_int :std_logic; signal MISO_I_int :std_logic; signal SCK_O_int :std_logic; signal TO_XIPSR_trans_error_int :std_logic; signal TO_XIPSR_CPHA_CPOL_ERR_int :std_logic; signal ip2bus_wrack_core_reg_d1 :std_logic; signal ip2bus_wrack_core_reg :std_logic; signal ip2bus_rdack_core_reg_d1 :std_logic; signal ip2bus_rdack_core_reg_d2 :std_logic; signal ip2Bus_RdAck_core_reg_d3 :std_logic; signal Rst_to_spi_int :std_logic; begin ----- ---- AXI4 Lite interface instance and interface with the port list AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif generic map ( ---------------------------------------------------- C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , ---------------------------------------------------- C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE , C_USE_WSTRB => C_USE_WSTRB , C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT , ---------------------------------------------------- C_ARD_ADDR_RANGE_ARRAY => C_XIP_LITE_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_XIP_LITE_ARD_NUM_CE_ARRAY , C_FAMILY => C_FAMILY ---------------------------------------------------- ) port map ( -- AXI4 Lite interface --------------------------------------------------------- S_AXI_ACLK => s_axi_aclk, -- in S_AXI_ARESETN => s_axi_aresetn, -- in --------------------------------------------------------- S_AXI_AWADDR => s_axi_awaddr, -- in S_AXI_AWVALID => s_axi_awvalid, -- in S_AXI_AWREADY => s_axi_awready, -- out S_AXI_WDATA => s_axi_wdata, -- in S_AXI_WSTRB => s_axi_wstrb, -- in S_AXI_WVALID => s_axi_wvalid, -- in S_AXI_WREADY => s_axi_wready, -- out S_AXI_BRESP => s_axi_bresp, -- out S_AXI_BVALID => s_axi_bvalid, -- out S_AXI_BREADY => s_axi_bready, -- in S_AXI_ARADDR => s_axi_araddr, -- in S_AXI_ARVALID => s_axi_arvalid, -- in S_AXI_ARREADY => s_axi_arready, -- out S_AXI_RDATA => s_axi_rdata, -- out S_AXI_RRESP => s_axi_rresp, -- out S_AXI_RVALID => s_axi_rvalid, -- out S_AXI_RREADY => s_axi_rready, -- in ---------------------------------------------------------- -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk_int , -- out Bus2IP_Resetn => bus2ip_reset_int, -- out ---------------------------------------------------------- Bus2IP_Addr => open, -- out -- not used signal Bus2IP_RNW => open, -- out Bus2IP_BE => open, -- bus2ip_be_int, -- out Bus2IP_CS => open, -- out -- not used signal Bus2IP_RdCE => bus2ip_xip_rdce_int, -- out -- little endian Bus2IP_WrCE => bus2ip_xip_wrce_int, -- out -- little endian Bus2IP_Data => bus2ip_data_int, -- out -- little endian ---------------------------------------------------------- IP2Bus_Data => ip2bus_data_int, -- in -- little endian IP2Bus_WrAck => ip2bus_wrack_int, -- in IP2Bus_RdAck => ip2bus_rdack_int, -- in IP2Bus_Error => ip2bus_error_int -- in ---------------------------------------------------------- ); -------------------------------------------------------------------------- ip2bus_error_int <= '0'; -- there is no error in this mode ---------------------- --REG_RST_FRM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RST_FRM_IPIF: process (S_AXI_ACLK) is begin if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then bus2ip_reset_ipif_inverted <= not(S_AXI_ARESETN); end if; end process REG_RST_FRM_IPIF; -------------------------------------------------------------------------- XIP_CR_I : entity axi_quad_spi_v3_2_8.xip_cntrl_reg generic map ( C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_SPI_MODE => C_SPI_MODE ) port map( Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic; Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic; ------------------------ Bus2IP_XIPCR_WrCE => bus2ip_xip_wrce_int(XIPCR), -- : in std_logic; Bus2IP_XIPCR_RdCE => bus2ip_xip_rdce_int(XIPCR), -- : in std_logic; Bus2IP_XIPCR_data => bus2ip_data_int , -- : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1)); ------------------------ ip2Bus_RdAck_core => ip2Bus_RdAck_core_reg_d2, -- IP2Bus_XIPCR_WrAck, ip2Bus_WrAck_core => ip2Bus_WrAck_core_reg, -- IP2Bus_XIPCR_RdAck, ------------------------ --XIPCR_7_0_CMD => XIPCR_7_0_CMD, -- out std_logic_vector; XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic; XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic; ------------------------ IP2Bus_XIPCR_Data => IP2Bus_XIPCR_Data_int, -- out std_logic; ------------------------ TO_XIPSR_CPHA_CPOL_ERR=> TO_XIPSR_CPHA_CPOL_ERR_int -- out std_logic ); -------------------------------------------------------------------------- REG_WR_ACK_P:process(S_AXI_ACLK)is begin ----- if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then if(bus2ip_reset_ipif_inverted = '1')then ip2Bus_WrAck_core_reg_d1 <= '0'; ip2Bus_WrAck_core_reg <= '0'; else ip2Bus_WrAck_core_reg_d1 <= bus2ip_xip_wrce_int(XIPCR) or bus2ip_xip_wrce_int(XIPSR); ip2Bus_WrAck_core_reg <= (bus2ip_xip_wrce_int(XIPCR) or bus2ip_xip_wrce_int(XIPSR)) and (not ip2Bus_WrAck_core_reg_d1); end if; end if; end process REG_WR_ACK_P; ------------------------- ip2bus_wrack_int <= ip2Bus_WrAck_core_reg; ------------------------- REG_RD_ACK_P:process(S_AXI_ACLK)is begin ----- if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then if(bus2ip_reset_ipif_inverted = '1')then ip2Bus_RdAck_core_reg_d1 <= '0'; ip2Bus_RdAck_core_reg_d2 <= '0'; ip2Bus_RdAck_core_reg_d3 <= '0'; else ip2Bus_RdAck_core_reg_d1 <= bus2ip_xip_rdce_int(XIPCR) or bus2ip_xip_rdce_int(XIPSR); ip2Bus_RdAck_core_reg_d2 <= (bus2ip_xip_rdce_int(XIPCR) or bus2ip_xip_rdce_int(XIPSR)) and (not ip2Bus_RdAck_core_reg_d1); ip2Bus_RdAck_core_reg_d3 <= ip2Bus_RdAck_core_reg_d2; end if; end if; end process REG_RD_ACK_P; ------------------------- ip2bus_rdack_int <= ip2Bus_RdAck_core_reg_d3; ------------------------- REG_IP2BUS_DATA_P:process(S_AXI_ACLK)is begin ----- if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then if(bus2ip_reset_ipif_inverted = '1')then ip2bus_data_int <= (others => '0'); elsif(ip2Bus_RdAck_core_reg_d2 = '1') then ip2bus_data_int <= ("000000000000000000000000000000" & IP2Bus_XIPCR_Data_int) or ("000000000000000000000000000" & IP2Bus_XIPSR_Data_int); end if; end if; end process REG_IP2BUS_DATA_P; ------------------------- -------------------------------------------------------------------------- XIP_SR_I : entity axi_quad_spi_v3_2_8.xip_status_reg generic map ( C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ) port map( Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic; Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic; ------------------------ XIPSR_AXI_TR_ERR => TO_XIPSR_AXI_TR_ERR_int, -- : in std_logic; XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int, -- : in std_logic; XIPSR_MST_MODF_ERR => TO_XIPSR_mst_modf_err_int, -- : in std_logic; XIPSR_AXI_RX_FULL => TO_XIPSR_axi_rx_full_int, -- : in std_logic; XIPSR_AXI_RX_EMPTY => TO_XIPSR_axi_rx_empty_int, -- : in std_logic; ------------------------ Bus2IP_XIPSR_WrCE => bus2ip_xip_wrce_int(XIPSR), Bus2IP_XIPSR_RdCE => bus2ip_xip_rdce_int(XIPSR), ------------------- IP2Bus_XIPSR_Data => IP2Bus_XIPSR_Data_int , ip2Bus_RdAck => ip2Bus_RdAck_core_reg_d3 ); --------------------------------------------------------------------------- --REG_RST4_FRM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RST4_FRM_IPIF: process (S_AXI4_ACLK) is begin if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then bus2ip_reset_ipif4_inverted <= not(S_AXI4_ARESETN); end if; end process REG_RST4_FRM_IPIF; ------------------------------------------------------------------------- RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_2_8.reset_sync_module port map( EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic; Soft_Reset_frm_axi => bus2ip_reset_ipif4_inverted ,-- in std_logic; Rst_to_spi => Rst_to_spi_int -- out std_logic; ); -------------------------------------------------------------------------- AXI_QSPI_XIP_I : entity axi_quad_spi_v3_2_8.axi_qspi_xip_if generic map ( C_FAMILY => C_FAMILY , Async_Clk => Async_Clk , C_SUB_FAMILY => C_FAMILY , ------------------------- --C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, --C_XIP_MODE => C_XIP_MODE , --C_AXI4_CLK_PS => C_AXI4_CLK_PS , --C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , --C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS , C_SCK_RATIO => C_SCK_RATIO , C_NUM_SS_BITS => C_NUM_SS_BITS , C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS , ------------------------- C_SPI_MODE => C_SPI_MODE , C_USE_STARTUP => C_USE_STARTUP , C_SPI_MEMORY => C_SPI_MEMORY , ------------------------- -- AXI4 Full Interface Parameters C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH , C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH , ------------------------- --*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR , --*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR , ------------------------- --C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH , --C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH , ------------------------- C_XIP_FULL_ARD_ADDR_RANGE_ARRAY => C_XIP_FULL_ARD_ADDR_RANGE_ARRAY, C_XIP_FULL_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY ) port map ( -- external async clock for SPI interface logic EXT_SPI_CLK => ext_spi_clk , -- : in std_logic; Rst_to_spi => Rst_to_spi_int, ---------------------------------- S_AXI_ACLK => s_axi_aclk , -- : in std_logic; S_AXI_ARESETN => bus2ip_reset_ipif_inverted, -- : in std_logic; ---------------------------------- S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic; S_AXI4_ARESET => bus2ip_reset_ipif4_inverted, -- : in std_logic; ------------------------------- --*AXI4 Full port interface* -- ------------------------------- ------------------------------------ -- AXI Write Address Channel Signals ------------------------------------ S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0); S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0); S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0); S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0); S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic; S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic; --------------------------------------- -- AXI4 Full Write data channel Signals --------------------------------------- S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0); S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0); S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic; S_AXI4_WVALID => s_axi4_wvalid , -- : in std_logic; S_AXI4_WREADY => s_axi4_wready , -- : out std_logic; ------------------------------------------- -- AXI4 Full Write response channel Signals ------------------------------------------- S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0); S_AXI4_BVALID => s_axi4_bvalid , -- : out std_logic; S_AXI4_BREADY => s_axi4_bready , -- : in std_logic; ----------------------------------- -- AXI Read Address channel signals ----------------------------------- S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0); S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0); S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0); S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0); S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic; S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic; -------------------------------- -- AXI Read Data Channel signals -------------------------------- S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0); S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0); S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic; S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic; S_AXI4_RREADY => s_axi4_rready, -- : in std_logic; -------------------------------- XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int , -- in std_logic ------------------------------- TO_XIPSR_trans_error => TO_XIPSR_AXI_TR_ERR_int , -- out std_logic TO_XIPSR_mst_modf_err => TO_XIPSR_mst_modf_err_int, TO_XIPSR_axi_rx_full => TO_XIPSR_axi_rx_full_int , TO_XIPSR_axi_rx_empty => TO_XIPSR_axi_rx_empty_int, ------------------------------- XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic; XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic; --*SPI port interface * -- ------------------------------- IO0_I => io0_i_sync_int, -- : in std_logic; -- MOSI signal in standard SPI IO0_O => io0_o_int, -- : out std_logic; IO0_T => io0_t_int, -- : out std_logic; ------------------------------- IO1_I => io1_i_sync_int, -- : in std_logic; -- MISO signal in standard SPI IO1_O => io1_o_int, -- : out std_logic; IO1_T => io1_t_int, -- : out std_logic; ----------------- -- quad mode pins ----------------- IO2_I => io2_i_sync_int, -- : in std_logic; IO2_O => io2_o_int, -- : out std_logic; IO2_T => io2_t_int, -- : out std_logic; --------------- IO3_I => io3_i_sync_int, -- : in std_logic; IO3_O => io3_o_int, -- : out std_logic; IO3_T => io3_t_int, -- : out std_logic; --------------------------------- -- common pins ---------------- SPISEL => spisel, -- : in std_logic; ----- SCK_I => sck_i , -- : in std_logic; SCK_O_reg => SCK_O_int , -- : out std_logic; SCK_T => sck_t , -- : out std_logic; ----- SS_I => ss_i_int , -- : in std_logic_vector((C_NUM_SS_BITS-1) downto 0); SS_O => ss_o_int , -- : out std_logic_vector((C_NUM_SS_BITS-1) downto 0); SS_T => ss_t_int -- : out std_logic; ---------------------- ); -- no interrupt from this mode of core IP2INTC_Irpt <= '0'; ------------------------------------------------------- ------------------------------------------------------- SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate ----- begin ----- SCK_O <= SCK_O_int; -- output from the core MISO_I_int <= io1_i_sync; -- input to the core end generate SCK_MISO_NO_STARTUP_USED; ------------------------------------------------------- SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate ----- begin ----- QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2_8.qspi_startup_block --------------------- generic map ( C_SUB_FAMILY => C_FAMILY , -- support for V6/V7/K7/A7 families only ----------------- C_USE_STARTUP => C_USE_STARTUP, ----------------- C_SHARED_STARTUP => C_SHARED_STARTUP, C_SPI_MODE => C_SPI_MODE ----------------- ) port map ( SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module IO1_I_startup => io1_i_sync, -- : in std_logic; -- input from the top level port list IO1_Int => MISO_I_int,-- : out std_logic Bus2IP_Clk => Bus2IP_Clk, reset2ip_reset => bus2ip_reset_ipif4_inverted, CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup. PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output DI => di_int, -- output DO => do_int, -- 4-bit input DTS => dts_int, -- 4-bit input FCSBO => fcsbo_int, -- 1-bit input FCSBTS => fcsbts_int,-- 1-bit input CLK => clk, -- 1-bit input, SetReset GSR => gsr, -- 1-bit input, SetReset GTS => gts, -- 1-bit input KEYCLEARB => keyclearb, --1-bit input USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input USRDONETS => usrdonets, -- SRDONETS -- 1-bit input PACK => pack ); -------------------- end generate SCK_MISO_STARTUP_USED; end generate XIP_MODE_GEN; ------------------------------------------------------------------------------ end architecture imp; ------------------------------------------------------------------------------
------------------------------------------------------------------------------- -- axi_quad_spi.vhd - Entity and architecture ------------------------------------------------------------------------------- -- -- ******************************************************************* -- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.* -- ** * -- ** This file contains confidential and proprietary information * -- ** of Xilinx, Inc. and is protected under U.S. and * -- ** international copyright and other intellectual property * -- ** laws. * -- ** * -- ** DISCLAIMER * -- ** This disclaimer is not a license and does not grant any * -- ** rights to the materials distributed herewith. Except as * -- ** otherwise provided in a valid license issued to you by * -- ** Xilinx, and to the maximum extent permitted by applicable * -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * -- ** (2) Xilinx shall not be liable (whether in contract or tort, * -- ** including negligence, or under any other theory of * -- ** liability) for any loss or damage of any kind or nature * -- ** related to, arising under or in connection with these * -- ** materials, including for any direct, or any indirect, * -- ** special, incidental, or consequential loss or damage * -- ** (including loss of data, profits, goodwill, or any type of * -- ** loss or damage suffered as a result of any action brought * -- ** by a third party) even if such damage or loss was * -- ** reasonably foreseeable or Xilinx had been advised of the * -- ** possibility of the same. * -- ** * -- ** CRITICAL APPLICATIONS * -- ** Xilinx products are not designed or intended to be fail- * -- ** safe, or for use in any application requiring fail-safe * -- ** performance, such as life-support or safety devices or * -- ** systems, Class III medical devices, nuclear facilities, * -- ** applications related to the deployment of airbags, or any * -- ** other applications that could lead to death, personal * -- ** injury, or severe property or environmental damage * -- ** (individually and collectively, "Critical * -- ** Applications"). Customer assumes the sole risk and * -- ** liability of any use of Xilinx products in Critical * -- ** Applications, subject only to applicable laws and * -- ** regulations governing limitations on product liability. * -- ** * -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * -- ** PART OF THIS FILE AT ALL TIMES. * -- ******************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_quad_spi.vhd -- Version: v3.0 -- Description: This is the top-level design file for the AXI Quad SPI core. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.conv_std_logic_vector; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use ieee.std_logic_misc.all; -- library unsigned is used for overloading of "=" which allows integer to -- be compared to std_logic_vector use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.FD; use unisim.vcomponents.FDRE; use UNISIM.vcomponents.all; library axi_lite_ipif_v3_0_4; use axi_lite_ipif_v3_0_4.axi_lite_ipif; use axi_lite_ipif_v3_0_4.ipif_pkg.all; library axi_quad_spi_v3_2_8; use axi_quad_spi_v3_2_8.all; ------------------------------------------------------------------------------- entity axi_quad_spi is generic( -- Async_Clk parameter is added only for Vivado, it is not used in the design, this is -- NON HDL parameter Async_Clk : integer := 0; -- General Parameters C_FAMILY : string := "virtex7"; C_SELECT_XPM : integer := 1; C_SUB_FAMILY : string := "virtex7"; C_INSTANCE : string := "axi_quad_spi_inst"; ------------------------- C_SPI_MEM_ADDR_BITS : integer := 24; -- allowed values are 24 or 32 only and used in XIP mode C_TYPE_OF_AXI4_INTERFACE : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode C_XIP_MODE : integer range 0 to 1 := 0;--default NON XIP Mode C_UC_FAMILY : integer range 0 to 1 := 0;--default NON XIP Mode --C_AXI4_CLK_PS : integer := 10000;--AXI clock period --C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period C_FIFO_DEPTH : integer := 256;-- allowed 0,16,256. C_SCK_RATIO : integer := 16;--default in legacy mode C_NUM_SS_BITS : integer range 1 to 32:= 1; C_NUM_TRANSFER_BITS : integer := 8; -- allowed 8, 16, 32 ------------------------- C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating -- Standard, Dual or Quad mode -- in Ports as well as internal -- functionality C_USE_STARTUP : integer range 0 to 1 := 1; -- C_SPI_MEMORY : integer range 0 to 3 := 1; -- 0 - mixed mode, -- 1 - winbond, -- 2 - numonyx -- 3 - spansion -- used to differentiate -- internal look up table -- for commands. ------------------------- -- AXI4 Lite Interface Parameters *as max address is 7c, only 7 address bits are used C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7; C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; ------------------------- --*C_BASEADDR : std_logic_vector := x"FFFFFFFF"; --*C_HIGHADDR : std_logic_vector := x"00000000"; ------------------------- -- AXI4 Full Interface Parameters *as max 24 bits of address are supported on SPI interface, only 24 address bits are used C_S_AXI4_ADDR_WIDTH : integer ;--range 24 to 24 := 24; C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32; C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4 ; C_SHARED_STARTUP : integer range 0 to 1 := 0; ------------------------- -- To FIX CR# 685366, below lines are added again in RTL (Vivado Requirement), but these parameters are not used in the core RTL C_S_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF"; C_S_AXI4_HIGHADDR : std_logic_vector := x"00000000"; ------------------------- C_LSB_STUP : integer range 0 to 1 := 0 ); port( -- external async clock for SPI interface logic ext_spi_clk : in std_logic; -- axi4 lite interface clk and reset signals s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; -- axi4 full interface clk and reset signals s_axi4_aclk : in std_logic; s_axi4_aresetn : in std_logic; ------------------------------- ------------------------------- --*axi4 lite port interface* -- ------------------------------- ------------------------------- -- axi write address channel signals --------------- s_axi_awaddr : in std_logic_vector (6 downto 0);--((C_S_AXI_ADDR_WIDTH-1) downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; --------------- -- axi write data channel signals --------------- s_axi_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0); s_axi_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI_DATA_WIDTH/8)-1) downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; --------------- -- axi write response channel signals --------------- s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; --------------- -- axi read address channel signals --------------- s_axi_araddr : in std_logic_vector(6 downto 0); -- ((C_S_AXI_ADDR_WIDTH-1) downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; --------------- -- axi read address channel signals --------------- s_axi_rdata : out std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; ------------------------------- ------------------------------- --*axi4 full port interface* -- ------------------------------- ------------------------------------ -- axi write address Channel Signals ------------------------------------ s_axi4_awid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); s_axi4_awaddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0); --((C_S_AXI4_ADDR_WIDTH-1) downto 0); s_axi4_awlen : in std_logic_vector(7 downto 0); s_axi4_awsize : in std_logic_vector(2 downto 0); s_axi4_awburst : in std_logic_vector(1 downto 0); s_axi4_awlock : in std_logic; -- not supported in design s_axi4_awcache : in std_logic_vector(3 downto 0);-- not supported in design s_axi4_awprot : in std_logic_vector(2 downto 0);-- not supported in design s_axi4_awvalid : in std_logic; s_axi4_awready : out std_logic; --------------------------------------- -- axi4 full write Data Channel Signals --------------------------------------- s_axi4_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI4_DATA_WIDTH-1)downto 0); s_axi4_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI4_DATA_WIDTH/8)-1) downto 0); s_axi4_wlast : in std_logic; s_axi4_wvalid : in std_logic; s_axi4_wready : out std_logic; ------------------------------------------- -- axi4 full write Response Channel Signals ------------------------------------------- s_axi4_bid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); s_axi4_bresp : out std_logic_vector(1 downto 0); s_axi4_bvalid : out std_logic; s_axi4_bready : in std_logic; ----------------------------------- -- axi read address Channel Signals ----------------------------------- s_axi4_arid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); s_axi4_araddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0); s_axi4_arlen : in std_logic_vector(7 downto 0); s_axi4_arsize : in std_logic_vector(2 downto 0); s_axi4_arburst : in std_logic_vector(1 downto 0); s_axi4_arlock : in std_logic; -- not supported in design s_axi4_arcache : in std_logic_vector(3 downto 0);-- not supported in design s_axi4_arprot : in std_logic_vector(2 downto 0);-- not supported in design s_axi4_arvalid : in std_logic; s_axi4_arready : out std_logic; -------------------------------- -- axi read data Channel Signals -------------------------------- s_axi4_rid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); s_axi4_rdata : out std_logic_vector(31 downto 0);--((C_S_AXI4_DATA_WIDTH-1) downto 0); s_axi4_rresp : out std_logic_vector(1 downto 0); s_axi4_rlast : out std_logic; s_axi4_rvalid : out std_logic; s_axi4_rready : in std_logic; -------------------------------- ------------------------------- --*SPI port interface * -- ------------------------------- io0_i : in std_logic; -- MOSI signal in standard SPI io0_o : out std_logic; io0_t : out std_logic; ------------------------------- io1_i : in std_logic; -- MISO signal in standard SPI io1_o : out std_logic; io1_t : out std_logic; ----------------- -- quad mode pins ----------------- io2_i : in std_logic; io2_o : out std_logic; io2_t : out std_logic; --------------- io3_i : in std_logic; io3_o : out std_logic; io3_t : out std_logic; --------------------------------- -- common pins ---------------- spisel : in std_logic; ----- sck_i : in std_logic; sck_o : out std_logic; sck_t : out std_logic; ----- ss_i : in std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP); ss_o : out std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP); ss_t : out std_logic; ------------------------ -- STARTUP INTERFACE ------------------------ cfgclk : out std_logic; -- FGCLK , -- 1-bit output: Configuration main clock output cfgmclk : out std_logic; -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output eos : out std_logic; -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup. preq : out std_logic; -- REQ , -- 1-bit output: PROGRAM request to fabric output clk : in std_logic; -- input gsr : in std_logic; -- input gts : in std_logic; -- input keyclearb : in std_logic; -- input usrcclkts : in std_logic; -- input usrdoneo : in std_logic; -- input usrdonets : in std_logic; -- input pack : in std_logic; -- input ---------------------- -- INTERRUPT INTERFACE ---------------------- ip2intc_irpt : out std_logic --------------------------------- ); ------------------------------- -- Fan-out attributes for XST attribute MAX_FANOUT : string; attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000"; attribute MAX_FANOUT of S_AXI4_ACLK : signal is "10000"; attribute MAX_FANOUT of EXT_SPI_CLK : signal is "10000"; attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000"; attribute MAX_FANOUT of S_AXI4_ARESETN : signal is "10000"; attribute INITIALVAL : string; attribute INITIALVAL of SPISEL : signal is "VCC"; ------------------------------- end entity axi_quad_spi; -------------------------------------------------------------------------------- architecture imp of axi_quad_spi is ---------------------------------------------------------------------------------- -- below attributes are added to reduce the synth warnings in Vivado tool attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ---------------------------------------------------------------------------------- --------------------------------------------------------------------------------- ---- constant added for webtalk information --------------------------------------------------------------------------------- -- constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_quad_spi,{" -- & "C_FAMILY = " & C_FAMILY -- & ",C_SUB_FAMILY = " & C_SUB_FAMILY -- & ",C_INSTANCE = " & C_INSTANCE -- & ",C_S_AXI_ADDR_WIDTH = " & integer'image(C_S_AXI_ADDR_WIDTH) -- & ",C_S_AXI_DATA_WIDTH = " & integer'image(C_S_AXI_DATA_WIDTH) -- & ",C_S_AXI4_ADDR_WIDTH = " & integer'image(C_S_AXI4_ADDR_WIDTH) -- & ",C_S_AXI4_DATA_WIDTH = " & integer'image(C_S_AXI4_DATA_WIDTH) -- & ",C_S_AXI4_ID_WIDTH = " & integer'image(C_S_AXI4_ID_WIDTH) -- & ",C_FIFO_DEPTH = " & integer'image(C_FIFO_DEPTH) -- & ",C_SCK_RATIO = " & integer'image(C_SCK_RATIO) -- & ",C_NUM_SS_BITS = " & integer'image(C_NUM_SS_BITS) -- & ",C_NUM_TRANSFER_BITS = " & integer'image(C_NUM_TRANSFER_BITS) -- & ",C_USE_STARTUP = " & integer'image(C_USE_STARTUP) -- & ",C_SPI_MODE = " & integer'image(C_SPI_MODE) -- & ",C_SPI_MEMORY = " & integer'image(C_SPI_MEMORY) -- & ",C_TYPE_OF_AXI4_INTERFACE = " & integer'image(C_TYPE_OF_AXI4_INTERFACE) -- & ",C_XIP_MODE = " & integer'image(C_XIP_MODE) -- & "}"; -- -- attribute CORE_GENERATION_INFO : string; -- attribute CORE_GENERATION_INFO of imp : architecture is C_CORE_GENERATION_INFO; ------------------------------------------------------------- ------------------------------------------------------------- -- Function Declaration ------------------------------------------------------------- -- get_fifo_presence - This function returns the 0 or 1 based upon the FIFO Depth. -- function get_fifo_presence(C_FIFO_DEPTH: integer) return integer is ----- begin ----- if(C_FIFO_DEPTH = 0)then return 0; else return 1; end if; end function get_fifo_presence; function get_fifo_depth(C_FIFO_EXIST: integer; C_FIFO_DEPTH : integer) return integer is ----- begin ----- if(C_FIFO_EXIST = 1)then return C_FIFO_DEPTH; else return 64; -- to ensure that log2 functions does not become invalid end if; end function get_fifo_depth; ------------------------------ function get_fifo_occupancy_count(C_FIFO_DEPTH: integer) return integer is ----- variable j : integer := 0; variable k : integer := 0; ----- begin ----- if (C_FIFO_DEPTH = 0) then return 4; else for i in 0 to 11 loop if(2**i >= C_FIFO_DEPTH) then if(k = 0) then j := i; end if; k := 1; end if; end loop; return j; end if; ------- end function get_fifo_occupancy_count; ------------------------------ -- Constant declarations ------------------------------ --------------------- ******************* ------------------------------------ -- Core Parameters --------------------- ******************* ------------------------------------ -- constant C_FIFO_EXIST : integer := get_fifo_presence(C_FIFO_DEPTH); constant C_FIFO_DEPTH_UPDATED : integer := get_fifo_depth(C_FIFO_EXIST, C_FIFO_DEPTH); -- width of control register constant C_SPICR_REG_WIDTH : integer := 10;-- refer DS -- width of status register constant C_SPISR_REG_WIDTH : integer := 11;-- refer DS -- count the counter width for calculating FIFO occupancy constant C_OCCUPANCY_NUM_BITS : integer := get_fifo_occupancy_count(C_FIFO_DEPTH_UPDATED); -- width of spi shift register constant C_SPI_NUM_BITS_REG : integer := 8;-- this is fixed constant C_NUM_SPI_REGS : integer := 8;-- this is fixed constant C_IPISR_IPIER_BITS : integer := 14;-- total 14 interrupts - 0 to 13 --------------------- ******************* ------------------------------------ -- AXI lite parameters --------------------- ******************* ------------------------------------ constant C_S_AXI_SPI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000007c"; constant C_USE_WSTRB : integer := 1; constant C_DPHASE_TIMEOUT : integer := 20; -- interupt mode constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to (C_IPISR_IPIER_BITS-1)):= ( others => INTR_REG_EVENT -- when C_SPI_MODE = 0 -- Seven interrupts if C_FIFO_DEPTH_UPDATED = 0 -- OR -- Eight interrupts if C_FIFO_DEPTH_UPDATED = 0 and slave mode ----------------------- OR --------------------------- -- Nine interrupts if C_FIFO_DEPTH_UPDATED = 16 and slave mode -- OR -- Seven interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode -- when C_SPI_MODE = 1 or 2 -- Thirteen interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode ); constant ZEROES : std_logic_vector(31 downto 0):= X"00000000"; -- this constant is defined as the start of SPI register addresses. constant C_IP_REG_ADDR_OFFSET : std_logic_vector := X"00000060"; -- Address range array constant C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( -- interrupt address base & high range --ZEROES & C_BASEADDR, --ZEROES & (C_BASEADDR or X"0000003F"),--interrupt address higher range ZEROES & X"00000000", ZEROES & X"0000003F",--interrupt address higher range -- soft reset register base & high addr --ZEROES & (C_BASEADDR or X"00000040"), --ZEROES & (C_BASEADDR or X"00000043"),--soft reset register high addr ZEROES & X"00000040", -- ZEROES & X"00000043",--soft reset register high addr ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes -- SPI registers Base & High Address -- Range is 60 to 78 -- for internal registers --ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET), --ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000018") ZEROES & C_IP_REG_ADDR_OFFSET, ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018") ); -- AXI4 Address range array constant C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL: SLV64_ARRAY_TYPE := ( -- interrupt address base & high range --*ZEROES & C_S_AXI4_BASEADDR, --*ZEROES & (C_S_AXI4_BASEADDR or X"0000003F"),--interrupt address higher range ZEROES & X"00000000", ZEROES & X"0000003F",--soft reset register high addr -- soft reset register base & high addr --*ZEROES & (C_S_AXI4_BASEADDR or X"00000040"), --*ZEROES & (C_S_AXI4_BASEADDR or X"00000043"),--soft reset register high addr ZEROES & X"00000040", -- ZEROES & X"00000043",--soft reset register high addr ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes -- SPI registers Base & High Address -- Range is 60 to 78 -- for internal registers ZEROES & (C_IP_REG_ADDR_OFFSET), ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018") ); -- No. of CE's required per address range constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => 16 , -- 16 CEs required for interrupt --1 => 1, -- 1 CE required for soft reset 1 => 8, -- 8 CE required for Addressing Holes in soft reset 2 => C_NUM_SPI_REGS ); -- no. of Chip Enable Signals constant C_NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY); -- no. of Chip Select Signals constant C_NUM_CS_SIGNALS : integer := (C_ARD_ADDR_RANGE_ARRAY'LENGTH/2); ----------------------------- ----------------------- ******************* ------------------------------------ ---- XIP Mode parameters ----------------------- ******************* ------------------------------------ -- No. of XIP SPI registers constant C_NUM_XIP_SPI_REGS : integer := 2;-- this is fixed -- width of XIP control register constant C_XIP_SPICR_REG_WIDTH: integer := 2;-- refer DS -- width of XIP status register constant C_XIP_SPISR_REG_WIDTH: integer := 5;-- refer DS -- Address range array constant C_XIP_LITE_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( -- XIP SPI registers Base & High Address -- Range is 60 to 64 -- for internal registers --*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET), --*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000004") ZEROES & (C_IP_REG_ADDR_OFFSET), ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000004") ); -- No. of CE's required per address range constant C_XIP_LITE_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => C_NUM_XIP_SPI_REGS -- 2 CEs required for XIP lite interface ); -- no. of Chip Enable Signals constant C_NUM_XIP_CE_SIGNALS : integer := calc_num_ce(C_XIP_LITE_ARD_NUM_CE_ARRAY); function assign_addr_bits (addr_bits_info : integer) return string is variable addr_width_24 : integer:= 24; variable addr_width_32 : integer:= 32; begin if addr_bits_info = 24 then -- old logic for 24 bit addressing return X"00FFFFFF";--addr_width_24; else return X"FFFFFFFF";--addr_width_32; end if; end function assign_addr_bits; constant C_XIP_ADDR_OFFSET : std_logic_vector := X"FFFFFFFF";--assign_addr_bits(C_SPI_MEM_ADDR_BITS); -- X"00FFFFFF"; -- XIP Full Interface Address range array constant C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( -- XIP SPI registers Base & High Address -- Range is 60 to 64 -- for internal registers --*ZEROES & (C_S_AXI4_BASEADDR), --*ZEROES & (C_S_AXI4_BASEADDR or C_24_BIT_ADDR_OFFSET) ZEROES & X"00000000", ZEROES & C_XIP_ADDR_OFFSET ); -- No. of CE's required per address range constant C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => C_NUM_XIP_SPI_REGS -- 0 CEs required for XIP Full interface ); --------------------------------------------------------------------------------- constant C_XIP_FIFO_DEPTH : integer := 264; ------------------------------------------------------------------------------- ----Startup Signals signal di_int : std_logic_vector(3 downto 0); -- output signal di_int_sync : std_logic_vector(3 downto 0); -- output signal dts_int : std_logic_vector(3 downto 0); -- input signal do_int : std_logic_vector(3 downto 0); -- input -- signal declaration signal bus2ip_clk : std_logic; signal bus2ip_be_int : std_logic_vector (((C_S_AXI_DATA_WIDTH/8)-1)downto 0); signal bus2ip_rdce_int : std_logic_vector ((C_NUM_CE_SIGNALS-1)downto 0); signal bus2ip_wrce_int : std_logic_vector ((C_NUM_CE_SIGNALS-1)downto 0); signal bus2ip_data_int : std_logic_vector ((C_S_AXI_DATA_WIDTH-1)downto 0); signal ip2bus_data_int : std_logic_vector ((C_S_AXI_DATA_WIDTH-1)downto 0 ) := (others => '0'); signal ip2bus_wrack_int : std_logic := '0'; signal ip2bus_rdack_int : std_logic := '0'; signal ip2bus_error_int : std_logic := '0'; signal bus2ip_reset_int : std_logic; signal bus2ip_reset_ipif_inverted: std_logic; -- XIP signals signal bus2ip_xip_rdce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1); signal bus2ip_xip_wrce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1); signal io0_i_sync : std_logic; signal io1_i_sync : std_logic; signal io2_i_sync : std_logic; signal io3_i_sync : std_logic; signal io0_i_sync_int : std_logic; signal io1_i_sync_int : std_logic; signal io2_i_sync_int : std_logic; signal io3_i_sync_int : std_logic; signal io0_i_int : std_logic; signal io1_i_int : std_logic; signal io2_i_int : std_logic; signal io3_i_int : std_logic; signal io0_o_int : std_logic; signal io1_o_int : std_logic; signal io2_o_int : std_logic; signal io3_o_int : std_logic; signal io0_t_int : std_logic; signal io1_t_int : std_logic; signal io2_t_int : std_logic; signal io3_t_int : std_logic; signal burst_tr_int : std_logic; signal rready_int : std_logic; signal bus2ip_reset_ipif4_inverted : std_logic; signal fcsbo_int : std_logic; signal ss_o_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0); signal ss_t_int : std_logic; signal ss_i_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0); signal fcsbts_int : std_logic; signal startup_di : std_logic_vector(1 downto 0); -- output signal startup_do : std_logic_vector(1 downto 0) := (others => '1'); -- output signal startup_dts : std_logic_vector(1 downto 0) := (others => '0'); -- output ----- begin ----- --------STUP and XIP mode STARTUP_USED_1: if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1) generate begin DI_INT_IO3_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => di_int_sync(3), C => EXT_SPI_CLK, D => di_int(3) --MOSI_I ); DI_INT_IO2_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => di_int_sync(2), C => EXT_SPI_CLK, D => di_int(2) -- MISO_I ); DI_INT_IO1_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => di_int_sync(1), C => EXT_SPI_CLK, D => di_int(1) ); ----------------------- DI_INT_IO0_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => di_int_sync(0), C => EXT_SPI_CLK, D => di_int(0) ); io0_i_sync_int <= di_int_sync(0); io1_i_sync_int <= di_int_sync(1); io2_i_sync_int <= di_int_sync(2); io3_i_sync_int <= di_int_sync(3); end generate STARTUP_USED_1; DATA_STARTUP_EN : if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1 and C_XIP_MODE = 1) generate ----- begin ----- do_int(0) <= io0_o_int; dts_int(0) <= io0_t_int ; do_int(1) <= io1_o_int; dts_int(1) <= io1_t_int ; fcsbo_int <= ss_o_int(0); fcsbts_int <= ss_t_int; NUM_SS : if (C_NUM_SS_BITS = 1) generate begin ss_o <= (others => '0'); ss_t <= '0'; end generate NUM_SS; NUM_SS_G1 : if (C_NUM_SS_BITS > 1) generate begin ss_i_int <= ss_i((C_NUM_SS_BITS-1) downto 1) & '1'; ss_o <= ss_o_int((C_NUM_SS_BITS-1) downto 1);-- & '0'; ss_t <= ss_t_int; end generate NUM_SS_G1; DATA_OUT_NQUAD: if C_SPI_MODE = 0 or C_SPI_MODE = 1 generate begin startup_di <= di_int_sync(3) & di_int_sync(2); do_int(2) <= startup_do(0); do_int(3) <= startup_do(1); dts_int(2) <= startup_dts(0); dts_int(3) <= startup_dts(1); --do <= do_int(3) & do_int(1); --dts <= dts_int(3) & dts_int(1); end generate DATA_OUT_NQUAD; DATA_OUT_QUAD: if C_SPI_MODE = 2 generate begin --di <= "00";--di_int(3) & di_int(2); do_int(2) <= io2_o_int;--do(2); do_int(3) <= io3_o_int;--do(1); --do <= do_int(3) & do_int(1); dts_int(2) <= io2_t_int;--dts_int(3) & dts_int(1); dts_int(3) <= io3_t_int;--dts_int(3) & dts_int(1); end generate DATA_OUT_QUAD; end generate DATA_STARTUP_EN; DATA_STARTUP_DIS : if ((C_USE_STARTUP = 0 or (C_USE_STARTUP = 1 and C_UC_FAMILY = 0)) and C_XIP_MODE = 1) generate ----- begin ----- io0_o <= io0_o_int; io0_t <= io0_t_int; io1_t <= io1_t_int; io1_o <= io1_o_int; io2_o <= io2_o_int; io2_t <= io2_t_int; io3_t <= io3_t_int; io3_o <= io3_o_int; ss_i_int <= ss_i; ss_o <= ss_o_int;-- & '0'; ss_t <= ss_t_int; end generate DATA_STARTUP_DIS; --------STUP and XIP mode off STARTUP_USED: if (C_USE_STARTUP = 0 or C_UC_FAMILY = 0) generate begin io0_i_sync_int <= io0_i_sync; io1_i_sync_int <= io1_i_sync; io2_i_sync_int <= io2_i_sync; io3_i_sync_int <= io3_i_sync; end generate STARTUP_USED; IO0_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => io0_i_sync, C => ext_spi_clk, D => io0_i --MOSI_I ); IO1_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => io1_i_sync, C => ext_spi_clk, D => io1_i -- MISO_I ); IO2_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => io2_i_sync, C => ext_spi_clk, D => io2_i ); ----------------------- IO3_I_REG: component FD generic map ( INIT => '0' ) port map ( Q => io3_i_sync, C => ext_spi_clk, D => io3_i ); ----------------------- ------------------------------------------------------------------------------- --------------- -- AXI_QUAD_SPI_LEGACY_MODE: This logic is legacy AXI4 Lite interface based design --------------- QSPI_LEGACY_MD_GEN : if C_TYPE_OF_AXI4_INTERFACE = 0 generate --------------- begin ----- AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif generic map ( ---------------------------------------------------- C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , ---------------------------------------------------- C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE , C_USE_WSTRB => C_USE_WSTRB , C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT , ---------------------------------------------------- C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY , C_FAMILY => C_FAMILY ---------------------------------------------------- ) port map ( --------------------------------------------------------- S_AXI_ACLK => s_axi_aclk, -- in S_AXI_ARESETN => s_axi_aresetn, -- in --------------------------------------------------------- S_AXI_AWADDR => s_axi_awaddr, -- in S_AXI_AWVALID => s_axi_awvalid, -- in S_AXI_AWREADY => s_axi_awready, -- out S_AXI_WDATA => s_axi_wdata, -- in S_AXI_WSTRB => s_axi_wstrb, -- in S_AXI_WVALID => s_axi_wvalid, -- in S_AXI_WREADY => s_axi_wready, -- out S_AXI_BRESP => s_axi_bresp, -- out S_AXI_BVALID => s_axi_bvalid, -- out S_AXI_BREADY => s_axi_bready, -- in S_AXI_ARADDR => s_axi_araddr, -- in S_AXI_ARVALID => s_axi_arvalid, -- in S_AXI_ARREADY => s_axi_arready, -- out S_AXI_RDATA => s_axi_rdata, -- out S_AXI_RRESP => s_axi_rresp, -- out S_AXI_RVALID => s_axi_rvalid, -- out S_AXI_RREADY => s_axi_rready, -- in ---------------------------------------------------------- -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, -- out Bus2IP_Resetn => bus2ip_reset_int, -- out ---------------------------------------------------------- Bus2IP_Addr => open, -- out -- not used signal Bus2IP_RNW => open, -- out Bus2IP_BE => bus2ip_be_int, -- out Bus2IP_CS => open, -- out -- not used signal Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian Bus2IP_Data => bus2ip_data_int, -- out -- little endian ---------------------------------------------------------- IP2Bus_Data => ip2bus_data_int, -- in -- little endian IP2Bus_WrAck => ip2bus_wrack_int, -- in IP2Bus_RdAck => ip2bus_rdack_int, -- in IP2Bus_Error => ip2bus_error_int -- in ---------------------------------------------------------- ); ---------------------- --REG_RST_FRM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RST_FRM_IPIF: process (S_AXI_ACLK) is begin if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then bus2ip_reset_ipif_inverted <= not(bus2ip_reset_int); end if; end process REG_RST_FRM_IPIF; -- ---------------------------------------------------------------------- -- -- Instansiating the SPI core -- ---------------------------------------------------------------------- QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_2_8.qspi_core_interface generic map ( ------------------------------------------------ -- AXI parameters C_LSB_STUP => C_LSB_STUP, C_FAMILY => C_FAMILY , Async_Clk => Async_Clk , C_SUB_FAMILY => C_FAMILY , C_UC_FAMILY => C_UC_FAMILY , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, ------------------------------------------------ -- local constants C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS , ------------------------------------------------ -- SPI parameters --C_AXI4_CLK_PS => C_AXI4_CLK_PS , --C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , C_SCK_RATIO => C_SCK_RATIO , C_NUM_SS_BITS => C_NUM_SS_BITS , C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS, C_SPI_MODE => C_SPI_MODE , C_USE_STARTUP => C_USE_STARTUP , C_SPI_MEMORY => C_SPI_MEMORY , C_SELECT_XPM => C_SELECT_XPM , C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, ------------------------------------------------ -- local constants C_FIFO_EXIST => C_FIFO_EXIST , C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG, C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS, C_SHARED_STARTUP => C_SHARED_STARTUP, ------------------------------------------------ -- local constants C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, ------------------------------------------------ -- local constants C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH , C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH ) port map ( EXT_SPI_CLK => ext_spi_clk, -- in --------------------------------------------------- -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, -- in Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in --------------------------------------------------- Bus2IP_BE => bus2ip_be_int, -- in vector -- Bus2IP_CS => bus2ip_cs_int, Bus2IP_RdCE => bus2ip_rdce_int, -- in vector Bus2IP_WrCE => bus2ip_wrce_int, -- in vector Bus2IP_Data => bus2ip_data_int, -- in vector --------------------------------------------------- IP2Bus_Data => ip2bus_data_int, -- out vector IP2Bus_WrAck => ip2bus_wrack_int, -- out IP2Bus_RdAck => ip2bus_rdack_int, -- out IP2Bus_Error => ip2bus_error_int, -- out --------------------------------------------------- burst_tr => burst_tr_int, rready => '0', WVALID => '0', --------------------------------------------------- --SPI Ports IO0_I => io0_i_sync,-- mosi IO0_O => io0_o, IO0_T => io0_t, ----- IO1_I => io1_i_sync,-- miso IO1_O => io1_o, IO1_T => io1_t, ----- IO2_I => io2_i_sync, IO2_O => io2_o, IO2_T => io2_t, ----- IO3_I => io3_i_sync, IO3_O => io3_o, IO3_T => io3_t, ----- SCK_I => sck_i, SCK_O => sck_o, SCK_T => sck_t, ----- SPISEL => spisel, ----- SS_I => ss_i, SS_O => ss_o, SS_T => ss_t, ----- IP2INTC_Irpt => ip2intc_irpt, CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup. PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output DI => startup_di, -- output DO => startup_do, -- 4-bit input DTS => startup_dts, -- 4-bit input GSR => gsr, -- 1-bit input, SetReset CLK => clk, -- 1-bit input, SetReset GTS => gts, -- 1-bit input KEYCLEARB => keyclearb, --1-bit input USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input USRDONETS => usrdonets, -- SRDONETS -- 1-bit input PACK => pack ----- ); burst_tr_int <= '0'; end generate QSPI_LEGACY_MD_GEN; ------------------------------------------------------------------------------ QSPI_ENHANCED_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 0 generate --------------- begin ----- -- AXI_QUAD_SPI_I: core instance QSPI_ENHANCED_MD_IPIF_I : entity axi_quad_spi_v3_2_8.axi_qspi_enhanced_mode generic map( -- General Parameters C_FAMILY => C_FAMILY , -- : string := "virtex7"; C_SUB_FAMILY => C_FAMILY , -- : string := "virtex7"; ------------------------- --C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, -- : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode --C_XIP_MODE => C_XIP_MODE , -- : integer range 0 to 1 := 0;--default NON XIP Mode --C_AXI4_CLK_PS => C_AXI4_CLK_PS , -- : integer := 10000;--AXI clock period --C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , -- : integer := 10000;--ext clock period C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , -- : integer := 16;-- allowed 0,16,256. C_SCK_RATIO => C_SCK_RATIO , -- : integer := 16;--default in legacy mode C_NUM_SS_BITS => C_NUM_SS_BITS , -- : integer range 1 to 32:= 1; C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS , -- : integer := 8; -- allowed 8, 16, 32 ------------------------- C_SPI_MODE => C_SPI_MODE , -- : integer range 0 to 2 := 0; -- used for differentiating C_USE_STARTUP => C_USE_STARTUP , -- : integer range 0 to 1 := 1; -- C_SPI_MEMORY => C_SPI_MEMORY , -- : integer range 0 to 2 := 1; -- 0 - mixed mode, ------------------------- -- AXI4 Full Interface Parameters C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH , -- : integer range 32 to 32 := 32; C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer range 32 to 32 := 32; C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH , -- : integer range 1 to 16 := 4; ------------------------- --*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR , -- : std_logic_vector := x"FFFFFFFF"; --*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR , -- : std_logic_vector := x"00000000" ------------------------- C_S_AXI_SPI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE , ------------------------- C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL , C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY , C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS -- newly added ) port map( -- external async clock for SPI interface logic EXT_SPI_CLK => ext_spi_clk , -- : in std_logic; ----------------------------------- S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic; S_AXI4_ARESETN => s_axi4_aresetn , -- : in std_logic; ------------------------------- ------------------------------- --*AXI4 Full port interface* -- ------------------------------- ------------------------------------ -- AXI Write Address channel signals ------------------------------------ S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0); S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0); S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0); S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0); S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic; S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic; --------------------------------------- -- AXI4 Full Write data channel signals --------------------------------------- S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0); S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0); S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic; S_AXI4_WVALID => s_axi4_wvalid, -- : in std_logic; S_AXI4_WREADY => s_axi4_wready, -- : out std_logic; ------------------------------------------- -- AXI4 Full Write response channel Signals ------------------------------------------- S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0); S_AXI4_BVALID => s_axi4_bvalid, -- : out std_logic; S_AXI4_BREADY => s_axi4_bready, -- : in std_logic; ----------------------------------- -- AXI Read Address channel signals ----------------------------------- S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0); S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0); S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0); S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0); S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic; S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic; -------------------------------- -- AXI Read Data Channel signals -------------------------------- S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0); S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0); S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic; S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic; S_AXI4_RREADY => s_axi4_rready, -- : in std_logic; ---------------------------------------------------------- -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, -- out Bus2IP_Reset => bus2ip_reset_ipif_inverted , -- out ---------------------------------------------------------- -- Bus2IP_Addr => open, -- out -- not used signal Bus2IP_RNW => open, -- out Bus2IP_BE => bus2ip_be_int, -- out Bus2IP_CS => open, -- out -- not used signal Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian Bus2IP_Data => bus2ip_data_int, -- out -- little endian ---------------------------------------------------------- IP2Bus_Data => ip2bus_data_int, -- in -- little endian IP2Bus_WrAck => ip2bus_wrack_int, -- in IP2Bus_RdAck => ip2bus_rdack_int, -- in IP2Bus_Error => ip2bus_error_int, -- in ---------------------------------------------------------- burst_tr => burst_tr_int, -- in rready => rready_int ); -- ---------------------------------------------------------------------- -- -- Instansiating the SPI core -- ---------------------------------------------------------------------- QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_2_8.qspi_core_interface generic map ( ------------------------------------------------ -- AXI parameters C_LSB_STUP => C_LSB_STUP, C_FAMILY => C_FAMILY , Async_Clk => Async_Clk , C_SELECT_XPM => C_SELECT_XPM , C_SUB_FAMILY => C_FAMILY , C_UC_FAMILY => C_UC_FAMILY , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, ------------------------------------------------ -- local constants C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS , ------------------------------------------------ -- SPI parameters --C_AXI4_CLK_PS => C_AXI4_CLK_PS , --C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , C_SCK_RATIO => C_SCK_RATIO , C_NUM_SS_BITS => C_NUM_SS_BITS , C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS, C_SPI_MODE => C_SPI_MODE , C_USE_STARTUP => C_USE_STARTUP , C_SPI_MEMORY => C_SPI_MEMORY , C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, ------------------------------------------------ -- local constants C_FIFO_EXIST => C_FIFO_EXIST , C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG, C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS, C_SHARED_STARTUP => C_SHARED_STARTUP, ------------------------------------------------ -- local constants C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, ------------------------------------------------ -- local constants C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH , C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH ) port map ( EXT_SPI_CLK => EXT_SPI_CLK, -- in --------------------------------------------------- -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, -- in Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in --------------------------------------------------- Bus2IP_BE => bus2ip_be_int, -- in vector -- Bus2IP_CS => bus2ip_cs_int, Bus2IP_RdCE => bus2ip_rdce_int, -- in vector Bus2IP_WrCE => bus2ip_wrce_int, -- in vector Bus2IP_Data => bus2ip_data_int, -- in vector --------------------------------------------------- IP2Bus_Data => ip2bus_data_int, -- out vector IP2Bus_WrAck => ip2bus_wrack_int, -- out IP2Bus_RdAck => ip2bus_rdack_int, -- out IP2Bus_Error => ip2bus_error_int, -- out --------------------------------------------------- burst_tr => burst_tr_int, rready => rready_int, WVALID => S_AXI4_WVALID, --SPI Ports IO0_I => io0_i_sync,-- mosi IO0_O => io0_o, IO0_T => io0_t, ----- IO1_I => io1_i_sync,-- miso IO1_O => io1_o, IO1_T => io1_t, ----- IO2_I => io2_i_sync, IO2_O => io2_o, IO2_T => io2_t, ----- IO3_I => io3_i_sync, IO3_O => io3_o, IO3_T => io3_t, ----- SCK_I => sck_i, SCK_O => sck_o, SCK_T => sck_t, ----- SPISEL => spisel, ----- SS_I => ss_i, SS_O => ss_o, SS_T => ss_t, ----- IP2INTC_Irpt => ip2intc_irpt, CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup. PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output DI => startup_di, -- output DO => startup_do, -- 4-bit input DTS => startup_dts, -- 4-bit input CLK => clk, -- 1-bit input, SetReset GSR => gsr, -- 1-bit input, SetReset GTS => gts, -- 1-bit input KEYCLEARB => keyclearb, --1-bit input USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input USRDONETS => usrdonets, -- SRDONETS -- 1-bit input PACK => pack ----- ); end generate QSPI_ENHANCED_MD_GEN; -------------------------------------------------------------------------------- ----------------- -- XIP_MODE: This logic is used in XIP mode where AXI4 Lite & AXI4 Full interface -- used in the design --------------- XIP_MODE_GEN : if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 1 generate --------------- constant XIPCR : natural := 0; -- at address C_BASEADDR + 60 h constant XIPSR : natural := 1; -- signal bus2ip_reset_int : std_logic; signal bus2ip_clk_int : std_logic; signal bus2ip_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal ip2bus_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal ip2bus_wrack_int : std_logic; signal ip2bus_rdack_int : std_logic; signal ip2bus_error_int : std_logic; signal bus2ip_reset_ipif_inverted: std_logic; signal IP2Bus_XIPCR_WrAck : std_logic; signal IP2Bus_XIPCR_RdAck : std_logic; signal XIPCR_1_CPOL_int : std_logic; signal XIPCR_0_CPHA_int : std_logic; signal IP2Bus_XIPCR_Data_int : std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0); signal IP2Bus_XIPSR_Data_int : std_logic_vector((C_XIP_SPISR_REG_WIDTH-1) downto 0); signal TO_XIPSR_AXI_TR_ERR_int : std_logic; signal TO_XIPSR_mst_modf_err_int : std_logic; signal TO_XIPSR_axi_rx_full_int : std_logic; signal TO_XIPSR_axi_rx_empty_int : std_logic; signal xipsr_cpha_cpol_err_int :std_logic; signal xipsr_cmd_err_int :std_logic; signal ip2bus_xipsr_wrack :std_logic; signal ip2bus_xipsr_rdack :std_logic; signal xipsr_axi_tr_err_int :std_logic; signal xipsr_axi_tr_done_int :std_logic; signal ip2bus_xipsr_rdack_int :std_logic; signal ip2bus_xipsr_wrack_int :std_logic; signal MISO_I_int :std_logic; signal SCK_O_int :std_logic; signal TO_XIPSR_trans_error_int :std_logic; signal TO_XIPSR_CPHA_CPOL_ERR_int :std_logic; signal ip2bus_wrack_core_reg_d1 :std_logic; signal ip2bus_wrack_core_reg :std_logic; signal ip2bus_rdack_core_reg_d1 :std_logic; signal ip2bus_rdack_core_reg_d2 :std_logic; signal ip2Bus_RdAck_core_reg_d3 :std_logic; signal Rst_to_spi_int :std_logic; begin ----- ---- AXI4 Lite interface instance and interface with the port list AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif generic map ( ---------------------------------------------------- C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , ---------------------------------------------------- C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE , C_USE_WSTRB => C_USE_WSTRB , C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT , ---------------------------------------------------- C_ARD_ADDR_RANGE_ARRAY => C_XIP_LITE_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_XIP_LITE_ARD_NUM_CE_ARRAY , C_FAMILY => C_FAMILY ---------------------------------------------------- ) port map ( -- AXI4 Lite interface --------------------------------------------------------- S_AXI_ACLK => s_axi_aclk, -- in S_AXI_ARESETN => s_axi_aresetn, -- in --------------------------------------------------------- S_AXI_AWADDR => s_axi_awaddr, -- in S_AXI_AWVALID => s_axi_awvalid, -- in S_AXI_AWREADY => s_axi_awready, -- out S_AXI_WDATA => s_axi_wdata, -- in S_AXI_WSTRB => s_axi_wstrb, -- in S_AXI_WVALID => s_axi_wvalid, -- in S_AXI_WREADY => s_axi_wready, -- out S_AXI_BRESP => s_axi_bresp, -- out S_AXI_BVALID => s_axi_bvalid, -- out S_AXI_BREADY => s_axi_bready, -- in S_AXI_ARADDR => s_axi_araddr, -- in S_AXI_ARVALID => s_axi_arvalid, -- in S_AXI_ARREADY => s_axi_arready, -- out S_AXI_RDATA => s_axi_rdata, -- out S_AXI_RRESP => s_axi_rresp, -- out S_AXI_RVALID => s_axi_rvalid, -- out S_AXI_RREADY => s_axi_rready, -- in ---------------------------------------------------------- -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk_int , -- out Bus2IP_Resetn => bus2ip_reset_int, -- out ---------------------------------------------------------- Bus2IP_Addr => open, -- out -- not used signal Bus2IP_RNW => open, -- out Bus2IP_BE => open, -- bus2ip_be_int, -- out Bus2IP_CS => open, -- out -- not used signal Bus2IP_RdCE => bus2ip_xip_rdce_int, -- out -- little endian Bus2IP_WrCE => bus2ip_xip_wrce_int, -- out -- little endian Bus2IP_Data => bus2ip_data_int, -- out -- little endian ---------------------------------------------------------- IP2Bus_Data => ip2bus_data_int, -- in -- little endian IP2Bus_WrAck => ip2bus_wrack_int, -- in IP2Bus_RdAck => ip2bus_rdack_int, -- in IP2Bus_Error => ip2bus_error_int -- in ---------------------------------------------------------- ); -------------------------------------------------------------------------- ip2bus_error_int <= '0'; -- there is no error in this mode ---------------------- --REG_RST_FRM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RST_FRM_IPIF: process (S_AXI_ACLK) is begin if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then bus2ip_reset_ipif_inverted <= not(S_AXI_ARESETN); end if; end process REG_RST_FRM_IPIF; -------------------------------------------------------------------------- XIP_CR_I : entity axi_quad_spi_v3_2_8.xip_cntrl_reg generic map ( C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_SPI_MODE => C_SPI_MODE ) port map( Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic; Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic; ------------------------ Bus2IP_XIPCR_WrCE => bus2ip_xip_wrce_int(XIPCR), -- : in std_logic; Bus2IP_XIPCR_RdCE => bus2ip_xip_rdce_int(XIPCR), -- : in std_logic; Bus2IP_XIPCR_data => bus2ip_data_int , -- : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1)); ------------------------ ip2Bus_RdAck_core => ip2Bus_RdAck_core_reg_d2, -- IP2Bus_XIPCR_WrAck, ip2Bus_WrAck_core => ip2Bus_WrAck_core_reg, -- IP2Bus_XIPCR_RdAck, ------------------------ --XIPCR_7_0_CMD => XIPCR_7_0_CMD, -- out std_logic_vector; XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic; XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic; ------------------------ IP2Bus_XIPCR_Data => IP2Bus_XIPCR_Data_int, -- out std_logic; ------------------------ TO_XIPSR_CPHA_CPOL_ERR=> TO_XIPSR_CPHA_CPOL_ERR_int -- out std_logic ); -------------------------------------------------------------------------- REG_WR_ACK_P:process(S_AXI_ACLK)is begin ----- if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then if(bus2ip_reset_ipif_inverted = '1')then ip2Bus_WrAck_core_reg_d1 <= '0'; ip2Bus_WrAck_core_reg <= '0'; else ip2Bus_WrAck_core_reg_d1 <= bus2ip_xip_wrce_int(XIPCR) or bus2ip_xip_wrce_int(XIPSR); ip2Bus_WrAck_core_reg <= (bus2ip_xip_wrce_int(XIPCR) or bus2ip_xip_wrce_int(XIPSR)) and (not ip2Bus_WrAck_core_reg_d1); end if; end if; end process REG_WR_ACK_P; ------------------------- ip2bus_wrack_int <= ip2Bus_WrAck_core_reg; ------------------------- REG_RD_ACK_P:process(S_AXI_ACLK)is begin ----- if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then if(bus2ip_reset_ipif_inverted = '1')then ip2Bus_RdAck_core_reg_d1 <= '0'; ip2Bus_RdAck_core_reg_d2 <= '0'; ip2Bus_RdAck_core_reg_d3 <= '0'; else ip2Bus_RdAck_core_reg_d1 <= bus2ip_xip_rdce_int(XIPCR) or bus2ip_xip_rdce_int(XIPSR); ip2Bus_RdAck_core_reg_d2 <= (bus2ip_xip_rdce_int(XIPCR) or bus2ip_xip_rdce_int(XIPSR)) and (not ip2Bus_RdAck_core_reg_d1); ip2Bus_RdAck_core_reg_d3 <= ip2Bus_RdAck_core_reg_d2; end if; end if; end process REG_RD_ACK_P; ------------------------- ip2bus_rdack_int <= ip2Bus_RdAck_core_reg_d3; ------------------------- REG_IP2BUS_DATA_P:process(S_AXI_ACLK)is begin ----- if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then if(bus2ip_reset_ipif_inverted = '1')then ip2bus_data_int <= (others => '0'); elsif(ip2Bus_RdAck_core_reg_d2 = '1') then ip2bus_data_int <= ("000000000000000000000000000000" & IP2Bus_XIPCR_Data_int) or ("000000000000000000000000000" & IP2Bus_XIPSR_Data_int); end if; end if; end process REG_IP2BUS_DATA_P; ------------------------- -------------------------------------------------------------------------- XIP_SR_I : entity axi_quad_spi_v3_2_8.xip_status_reg generic map ( C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ) port map( Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic; Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic; ------------------------ XIPSR_AXI_TR_ERR => TO_XIPSR_AXI_TR_ERR_int, -- : in std_logic; XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int, -- : in std_logic; XIPSR_MST_MODF_ERR => TO_XIPSR_mst_modf_err_int, -- : in std_logic; XIPSR_AXI_RX_FULL => TO_XIPSR_axi_rx_full_int, -- : in std_logic; XIPSR_AXI_RX_EMPTY => TO_XIPSR_axi_rx_empty_int, -- : in std_logic; ------------------------ Bus2IP_XIPSR_WrCE => bus2ip_xip_wrce_int(XIPSR), Bus2IP_XIPSR_RdCE => bus2ip_xip_rdce_int(XIPSR), ------------------- IP2Bus_XIPSR_Data => IP2Bus_XIPSR_Data_int , ip2Bus_RdAck => ip2Bus_RdAck_core_reg_d3 ); --------------------------------------------------------------------------- --REG_RST4_FRM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RST4_FRM_IPIF: process (S_AXI4_ACLK) is begin if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then bus2ip_reset_ipif4_inverted <= not(S_AXI4_ARESETN); end if; end process REG_RST4_FRM_IPIF; ------------------------------------------------------------------------- RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_2_8.reset_sync_module port map( EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic; Soft_Reset_frm_axi => bus2ip_reset_ipif4_inverted ,-- in std_logic; Rst_to_spi => Rst_to_spi_int -- out std_logic; ); -------------------------------------------------------------------------- AXI_QSPI_XIP_I : entity axi_quad_spi_v3_2_8.axi_qspi_xip_if generic map ( C_FAMILY => C_FAMILY , Async_Clk => Async_Clk , C_SUB_FAMILY => C_FAMILY , ------------------------- --C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, --C_XIP_MODE => C_XIP_MODE , --C_AXI4_CLK_PS => C_AXI4_CLK_PS , --C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , --C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS , C_SCK_RATIO => C_SCK_RATIO , C_NUM_SS_BITS => C_NUM_SS_BITS , C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS , ------------------------- C_SPI_MODE => C_SPI_MODE , C_USE_STARTUP => C_USE_STARTUP , C_SPI_MEMORY => C_SPI_MEMORY , ------------------------- -- AXI4 Full Interface Parameters C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH , C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH , ------------------------- --*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR , --*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR , ------------------------- --C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH , --C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH , ------------------------- C_XIP_FULL_ARD_ADDR_RANGE_ARRAY => C_XIP_FULL_ARD_ADDR_RANGE_ARRAY, C_XIP_FULL_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY ) port map ( -- external async clock for SPI interface logic EXT_SPI_CLK => ext_spi_clk , -- : in std_logic; Rst_to_spi => Rst_to_spi_int, ---------------------------------- S_AXI_ACLK => s_axi_aclk , -- : in std_logic; S_AXI_ARESETN => bus2ip_reset_ipif_inverted, -- : in std_logic; ---------------------------------- S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic; S_AXI4_ARESET => bus2ip_reset_ipif4_inverted, -- : in std_logic; ------------------------------- --*AXI4 Full port interface* -- ------------------------------- ------------------------------------ -- AXI Write Address Channel Signals ------------------------------------ S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0); S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0); S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0); S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0); S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic; S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic; --------------------------------------- -- AXI4 Full Write data channel Signals --------------------------------------- S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0); S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0); S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic; S_AXI4_WVALID => s_axi4_wvalid , -- : in std_logic; S_AXI4_WREADY => s_axi4_wready , -- : out std_logic; ------------------------------------------- -- AXI4 Full Write response channel Signals ------------------------------------------- S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0); S_AXI4_BVALID => s_axi4_bvalid , -- : out std_logic; S_AXI4_BREADY => s_axi4_bready , -- : in std_logic; ----------------------------------- -- AXI Read Address channel signals ----------------------------------- S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0); S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0); S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0); S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0); S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic; S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic; -------------------------------- -- AXI Read Data Channel signals -------------------------------- S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0); S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0); S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0); S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic; S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic; S_AXI4_RREADY => s_axi4_rready, -- : in std_logic; -------------------------------- XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int , -- in std_logic ------------------------------- TO_XIPSR_trans_error => TO_XIPSR_AXI_TR_ERR_int , -- out std_logic TO_XIPSR_mst_modf_err => TO_XIPSR_mst_modf_err_int, TO_XIPSR_axi_rx_full => TO_XIPSR_axi_rx_full_int , TO_XIPSR_axi_rx_empty => TO_XIPSR_axi_rx_empty_int, ------------------------------- XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic; XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic; --*SPI port interface * -- ------------------------------- IO0_I => io0_i_sync_int, -- : in std_logic; -- MOSI signal in standard SPI IO0_O => io0_o_int, -- : out std_logic; IO0_T => io0_t_int, -- : out std_logic; ------------------------------- IO1_I => io1_i_sync_int, -- : in std_logic; -- MISO signal in standard SPI IO1_O => io1_o_int, -- : out std_logic; IO1_T => io1_t_int, -- : out std_logic; ----------------- -- quad mode pins ----------------- IO2_I => io2_i_sync_int, -- : in std_logic; IO2_O => io2_o_int, -- : out std_logic; IO2_T => io2_t_int, -- : out std_logic; --------------- IO3_I => io3_i_sync_int, -- : in std_logic; IO3_O => io3_o_int, -- : out std_logic; IO3_T => io3_t_int, -- : out std_logic; --------------------------------- -- common pins ---------------- SPISEL => spisel, -- : in std_logic; ----- SCK_I => sck_i , -- : in std_logic; SCK_O_reg => SCK_O_int , -- : out std_logic; SCK_T => sck_t , -- : out std_logic; ----- SS_I => ss_i_int , -- : in std_logic_vector((C_NUM_SS_BITS-1) downto 0); SS_O => ss_o_int , -- : out std_logic_vector((C_NUM_SS_BITS-1) downto 0); SS_T => ss_t_int -- : out std_logic; ---------------------- ); -- no interrupt from this mode of core IP2INTC_Irpt <= '0'; ------------------------------------------------------- ------------------------------------------------------- SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate ----- begin ----- SCK_O <= SCK_O_int; -- output from the core MISO_I_int <= io1_i_sync; -- input to the core end generate SCK_MISO_NO_STARTUP_USED; ------------------------------------------------------- SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate ----- begin ----- QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2_8.qspi_startup_block --------------------- generic map ( C_SUB_FAMILY => C_FAMILY , -- support for V6/V7/K7/A7 families only ----------------- C_USE_STARTUP => C_USE_STARTUP, ----------------- C_SHARED_STARTUP => C_SHARED_STARTUP, C_SPI_MODE => C_SPI_MODE ----------------- ) port map ( SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module IO1_I_startup => io1_i_sync, -- : in std_logic; -- input from the top level port list IO1_Int => MISO_I_int,-- : out std_logic Bus2IP_Clk => Bus2IP_Clk, reset2ip_reset => bus2ip_reset_ipif4_inverted, CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup. PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output DI => di_int, -- output DO => do_int, -- 4-bit input DTS => dts_int, -- 4-bit input FCSBO => fcsbo_int, -- 1-bit input FCSBTS => fcsbts_int,-- 1-bit input CLK => clk, -- 1-bit input, SetReset GSR => gsr, -- 1-bit input, SetReset GTS => gts, -- 1-bit input KEYCLEARB => keyclearb, --1-bit input USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input USRDONETS => usrdonets, -- SRDONETS -- 1-bit input PACK => pack ); -------------------- end generate SCK_MISO_STARTUP_USED; end generate XIP_MODE_GEN; ------------------------------------------------------------------------------ end architecture imp; ------------------------------------------------------------------------------
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Tue Sep 17 19:45:27 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_zynq_snick_auto_pc_0_stub.vhdl -- Design : gcd_zynq_snick_auto_pc_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg400-3 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is Port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2"; begin end;
-- -- BananaCore - A processor written in VHDL -- -- Created by Rogiel Sulzbach. -- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved. -- library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; use ieee.std_logic_1164.std_logic; library BananaCore; use BananaCore.Core.all; use BananaCore.Memory.all; use BananaCore.RegisterPackage.all; -- The LoadInstructionExecutor entity entity LoadInstructionExecutor is port( -- the processor main clock clock: in BananaCore.Core.Clock; -- enables the instruction enable: in std_logic; -- the first register to operate on (argument 0) arg0_address: in RegisterAddress; -- the first register to operate on (argument 1) arg1_address: in RegisterAddress; -- the address to operate on (argument 2) arg2_address: in MemoryAddress; -- a bus indicating if the instruction is ready or not instruction_ready: out std_logic := '0'; ------------------------------------------ -- MEMORY BUS ------------------------------------------ -- the address to read/write memory from/to memory_address: out MemoryAddress := (others => '0'); -- the memory being read to memory_data_read: in MemoryData; -- the memory being written to memory_data_write: out MemoryData := (others => '0'); -- the operation to perform on the memory memory_operation: out MemoryOperation := MEMORY_OP_DISABLED; -- a flag indicating if a memory operation should be performed memory_enable: out std_logic := '0'; -- a flag indicating if a memory operation has completed memory_ready: in std_logic; ------------------------------------------ -- REGISTER BUS ------------------------------------------ -- the processor register address bus register_address: out RegisterAddress := (others => '0'); -- the processor register data bus register_data_read: in RegisterData; -- the processor register data bus register_data_write: out RegisterData := (others => '0'); -- the processor register operation signal register_operation: out RegisterOperation := OP_REG_DISABLED; -- the processor register enable signal register_enable: out std_logic := '0'; -- a flag indicating if a register operation has completed register_ready: in std_logic ); end LoadInstructionExecutor; architecture LoadInstructionExecutorImpl of LoadInstructionExecutor is type state_type is ( check, fetch_mem0, store_mem0, fetch_mem1, store_mem1, fetch_register, store_register, store_result, complete ); signal state: state_type := fetch_mem0; signal result: RegisterData; begin process (clock) begin if clock'event and clock = '1' then if enable = '1' then case state is when check => if arg0_address = "0000" then state <= fetch_register; elsif arg0_address = "0001" then state <= fetch_mem0; elsif arg0_address = "0010" then state <= store_result; result <= std_logic_vector(arg2_address); else state <= complete; end if; when fetch_mem0 => instruction_ready <= '0'; memory_address <= arg2_address; memory_operation <= MEMORY_OP_READ; memory_enable <= '1'; state <= store_mem0; when store_mem0 => if memory_ready = '1' then result(7 downto 0) <= memory_data_read; memory_enable <= '0'; state <= fetch_mem1; else state <= store_mem0; end if; when fetch_mem1 => instruction_ready <= '0'; memory_address <= arg2_address + 1; memory_operation <= MEMORY_OP_READ; memory_enable <= '1'; state <= store_mem1; when store_mem1 => if memory_ready = '1' then result(8 downto 15) <= memory_data_read; memory_enable <= '0'; state <= store_result; else state <= store_mem1; end if; when fetch_register => register_address <= arg2_address(11 downto 8); register_operation <= OP_REG_GET; register_enable <= '1'; state <= store_register; when store_register => if register_ready = '1' then result <= register_data_read; state <= store_result; register_enable <= '0'; else state <= store_register; end if; when store_result => register_address <= arg1_address; register_operation <= OP_REG_SET; register_data_write <= result; register_enable <= '1'; state <= complete; when complete => if register_ready = '1' then instruction_ready <= '1'; register_enable <= '0'; register_operation <= OP_REG_GET; end if; state <= complete; end case; else instruction_ready <= '0'; register_enable <= '0'; register_operation <= OP_REG_GET; memory_enable <= '0'; state <= check; end if; end if; end process; end LoadInstructionExecutorImpl;
---------------------------------------------------------------------------------- -- Company: ITESM CQ -- Engineer: Miguel Gonzalez A01203712 -- -- Create Date: 10:39:53 11/10/2015 -- Design Name: -- Module Name: Freq_Div - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: Frequency divider -- -- Dependencies: -- -- Revision: -- Revision 0.0.1 - File Created -- Revision 1.0.0 - Motor Implementation -- Additional Comments: -- -- ### TODO ### GENERIC =>> FDIV ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity Freq_Div is Port ( in_rst : in STD_LOGIC; in_clk : in STD_LOGIC; out_time_base : out STD_LOGIC); end Freq_Div; architecture Behavioral of Freq_Div is -- constants constant FOSC : integer := 100_000_000; constant FDIV : integer := 1_000_000; constant CTAMAX : integer := FOSC / FDIV; -- internal signals signal cont : integer range 0 to CtaMax; begin Freq_Divider: process (in_Rst, in_Clk) begin if in_rst = '1' then cont <= 0; elsif (rising_edge(in_clk)) then if cont = CTAMAX then cont <= 0; out_time_base <= '1'; else cont <= cont + 1; out_time_base <= '0'; end if; end if; end process Freq_Divider; end Behavioral;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity mul_344 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(14 downto 0) ); end mul_344; architecture augh of mul_344 is signal tmp_res : signed(46 downto 0); begin -- The actual multiplication tmp_res <= signed(in_a) * signed(in_b); -- Set the output result <= std_logic_vector(tmp_res(31 downto 0)); end architecture;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity mul_344 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(14 downto 0) ); end mul_344; architecture augh of mul_344 is signal tmp_res : signed(46 downto 0); begin -- The actual multiplication tmp_res <= signed(in_a) * signed(in_b); -- Set the output result <= std_logic_vector(tmp_res(31 downto 0)); end architecture;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc12.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s02b00x00p02n01i00012ent IS END c04s02b00x00p02n01i00012ent; ARCHITECTURE c04s02b00x00p02n01i00012arch OF c04s02b00x00p02n01i00012ent IS --reserved word misspelled subtyp GROUND is BIT range '0' to '0'; BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c04s02b00x00p02n01i00012 - The reserved word is misspelled." severity ERROR; wait; END PROCESS TESTING; END c04s02b00x00p02n01i00012arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc12.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s02b00x00p02n01i00012ent IS END c04s02b00x00p02n01i00012ent; ARCHITECTURE c04s02b00x00p02n01i00012arch OF c04s02b00x00p02n01i00012ent IS --reserved word misspelled subtyp GROUND is BIT range '0' to '0'; BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c04s02b00x00p02n01i00012 - The reserved word is misspelled." severity ERROR; wait; END PROCESS TESTING; END c04s02b00x00p02n01i00012arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc12.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s02b00x00p02n01i00012ent IS END c04s02b00x00p02n01i00012ent; ARCHITECTURE c04s02b00x00p02n01i00012arch OF c04s02b00x00p02n01i00012ent IS --reserved word misspelled subtyp GROUND is BIT range '0' to '0'; BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c04s02b00x00p02n01i00012 - The reserved word is misspelled." severity ERROR; wait; END PROCESS TESTING; END c04s02b00x00p02n01i00012arch;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015 - 2016, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: ahbram -- File: ahbram.vhd -- Author: Jiri Gaisler - Gaisler Research -- Modified: Jan Andersson - Aeroflex Gaisler -- Description: AHB ram. 0-waitstate read, 0/1-waitstate write. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.config_types.all; use grlib.config.all; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; library techmap; use techmap.gencomp.all; entity ahbram is generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff#; tech : integer := DEFMEMTECH; kbytes : integer := 1; pipe : integer := 0; maccsz : integer := AHBDW; scantest: integer := 0); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type ); end; architecture rtl of ahbram is constant abits : integer := log2ext(kbytes) + 8 - maccsz/64; constant dw : integer := maccsz; constant hconfig : ahb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0), 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32); type reg_type is record hwrite : std_ulogic; hready : std_ulogic; hsel : std_ulogic; addr : std_logic_vector(abits-1+log2(dw/8) downto 0); size : std_logic_vector(2 downto 0); prdata : std_logic_vector((dw-1)*pipe downto 0); pwrite : std_ulogic; pready : std_ulogic; end record; constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1; constant RES : reg_type := (hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'), size => (others => '0'), prdata => (others => '0'), pwrite => '0', pready => '1'); signal r, c : reg_type; signal ramsel : std_logic_vector(dw/8-1 downto 0); signal write : std_logic_vector(dw/8-1 downto 0); signal ramaddr : std_logic_vector(abits-1 downto 0); signal ramdata : std_logic_vector(dw-1 downto 0); signal hwdata : std_logic_vector(dw-1 downto 0); begin comb : process (ahbsi, r, rst, ramdata) variable bs : std_logic_vector(dw/8-1 downto 0); variable v : reg_type; variable haddr : std_logic_vector(abits-1 downto 0); variable hrdata : std_logic_vector(dw-1 downto 0); variable seldata : std_logic_vector(dw-1 downto 0); variable raddr : std_logic_vector(3 downto 2); variable adsel : std_logic; begin v := r; v.hready := '1'; bs := (others => '0'); v.pready := r.hready; if pipe=0 then adsel := r.hwrite or not r.hready; else adsel := r.hwrite or r.pwrite; v.hready := r.hready or not r.pwrite; end if; if adsel = '1' then haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8)); else haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8)); bs := (others => '0'); end if; raddr := (others => '0'); v.pwrite := '0'; if pipe/=0 and (r.hready='1' or r.pwrite='0') then v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0); end if; if ahbsi.hready = '1' then if pipe=0 then v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0); end if; v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1); v.size := ahbsi.hsize(2 downto 0); v.hwrite := ahbsi.hwrite and v.hsel; if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then v.hready := '0'; v.pwrite := r.hwrite; end if; end if; if r.hwrite = '1' then case r.size is when HSIZE_BYTE => bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1'; when HSIZE_HWORD => for i in 0 to dw/16-1 loop if i = conv_integer(r.addr(log2(dw/16) downto 1)) then bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1'); end if; end loop; -- i when HSIZE_WORD => if dw = 32 then bs := (others => '1'); else for i in 0 to dw/32-1 loop if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1'); end if; end loop; -- i end if; when HSIZE_DWORD => if dw = 32 then null; elsif dw = 64 then bs := (others => '1'); else for i in 0 to dw/64-1 loop if i = conv_integer(r.addr(3)) then bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1'); end if; end loop; -- i end if; when HSIZE_4WORD => if dw < 128 then null; elsif dw = 128 then bs := (others => '1'); else for i in 0 to dw/64-1 loop if i = conv_integer(r.addr(3)) then bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1'); end if; end loop; -- i end if; when others => --HSIZE_8WORD if dw < 256 then null; else bs := (others => '1'); end if; end case; v.hready := not (v.hsel and not ahbsi.hwrite); v.hwrite := v.hwrite and v.hready; end if; -- Duplicate read data on word basis, unless CORE_ACDM is enabled if CORE_ACDM = 0 then if dw = 32 then seldata := ramdata; elsif dw = 64 then if r.size = HSIZE_DWORD then seldata := ramdata; else if r.addr(2) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2); else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if; seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0); end if; elsif dw = 128 then if r.size = HSIZE_4WORD then seldata := ramdata; elsif r.size = HSIZE_DWORD then if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2); else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if; seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0); else raddr := r.addr(3 downto 2); case raddr is when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4); when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4); when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4); when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0); end case; seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) & seldata(dw/4-1 downto 0) & seldata(dw/4-1 downto 0); end if; else seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size); end if; else seldata := ramdata; end if; if pipe = 0 then v.prdata := (others => '0'); hrdata := seldata; else v.prdata := seldata; hrdata := r.prdata; end if; if (not RESET_ALL) and (rst = '0') then v.hwrite := RES.hwrite; v.hready := RES.hready; end if; write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop; ramaddr <= haddr; c <= v; ahbso.hrdata <= ahbdrivedata(hrdata); ahbso.hready <= r.hready; end process; ahbso.hresp <= "00"; ahbso.hsplit <= (others => '0'); ahbso.hirq <= (others => '0'); ahbso.hconfig <= hconfig; ahbso.hindex <= hindex; -- Select correct write data hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2), conv_std_logic_vector(log2(dw/8), 3)); aram : syncrambw generic map (tech, abits, dw, scantest) port map ( clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin); reg : process (clk) begin if rising_edge(clk) then r <= c; if RESET_ALL and rst = '0' then r <= RES; end if; end if; end process; -- pragma translate_off bootmsg : report_version generic map ("ahbram" & tost(hindex) & ": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes"); -- pragma translate_on end;
library ieee; use ieee.std_logic_1164.all; entity dff is generic( formal_g : boolean := true ); port( reset : in std_logic; clk : in std_logic; d : in std_logic; q : out std_logic ); end entity dff; architecture rtl of dff is signal q_int : std_logic; begin dff_proc : process(clk, reset) begin if reset = '1' then q_int <= '0'; elsif rising_edge(clk) then q_int <= d; end if; end process dff_proc; -- drive q_int to output port q <= q_int; formal_gen : if formal_g = true generate begin -- set all declarations to run on clk default clock is rising_edge(clk); d_in_check : assert always {d} |=> {q_int}; not_d_in_check : assert always {not d} |=> {not q_int}; end generate formal_gen; end rtl;
architecture RTL of FIFO is procedure proc1 is begin end procedure proc1; procedure proc1 ( constant a : in integer; signal d : out std_logic ) is begin end procedure proc1; procedure proc1 (constant a : in integer; signal d : out std_logic); -- Fixes follow procedure proc1 (constant a : in integer; signal d : out std_logic ) is begin end procedure proc1; begin end architecture RTL;
------------------------------------------------------------------------------- -- Copyright (c) 2013 Xilinx, Inc. -- All Rights Reserved ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 13.4 -- \ \ Application: XILINX CORE Generator -- / / Filename : chipscope_ila_1024.vhd -- /___/ /\ Timestamp : Tue Aug 13 15:39:30 BRT 2013 -- \ \ / \ -- \___\/\___\ -- -- Design Name: VHDL Synthesis Wrapper ------------------------------------------------------------------------------- -- This wrapper is used to integrate with Project Navigator and PlanAhead LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY chipscope_ila_1024 IS port ( CONTROL: inout std_logic_vector(35 downto 0); CLK: in std_logic; TRIG0: in std_logic_vector(7 downto 0); TRIG1: in std_logic_vector(31 downto 0); TRIG2: in std_logic_vector(31 downto 0); TRIG3: in std_logic_vector(31 downto 0); TRIG4: in std_logic_vector(31 downto 0)); END chipscope_ila_1024; ARCHITECTURE chipscope_ila_1024_a OF chipscope_ila_1024 IS BEGIN END chipscope_ila_1024_a;
------------------------------------------------------------------------------- -- Copyright (c) 2013 Xilinx, Inc. -- All Rights Reserved ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 13.4 -- \ \ Application: XILINX CORE Generator -- / / Filename : chipscope_ila_1024.vhd -- /___/ /\ Timestamp : Tue Aug 13 15:39:30 BRT 2013 -- \ \ / \ -- \___\/\___\ -- -- Design Name: VHDL Synthesis Wrapper ------------------------------------------------------------------------------- -- This wrapper is used to integrate with Project Navigator and PlanAhead LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY chipscope_ila_1024 IS port ( CONTROL: inout std_logic_vector(35 downto 0); CLK: in std_logic; TRIG0: in std_logic_vector(7 downto 0); TRIG1: in std_logic_vector(31 downto 0); TRIG2: in std_logic_vector(31 downto 0); TRIG3: in std_logic_vector(31 downto 0); TRIG4: in std_logic_vector(31 downto 0)); END chipscope_ila_1024; ARCHITECTURE chipscope_ila_1024_a OF chipscope_ila_1024 IS BEGIN END chipscope_ila_1024_a;
architecture RTL of FIFO is begin CASE_LABEL : case data generate when a = 1 => signal signal1 : std_logic; constant con1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin when b = 2 => signal sig1 : std_logic; constant constant1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin when c = 2 => signal sig1 : std_logic; constant con1 : std_logic; shared variable vars1 : std_logic; alias a is name; alias a : subtype_indication is name; begin end generate; -- Violations below CASE_LABEL : case data generate when a = 1 => signal signal1 : std_logic; constant con1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin when b = 2 => signal sig1 : std_logic; constant constant1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin when c = 2 => signal sig1 : std_logic; constant con1 : std_logic; shared variable vars1 : std_logic; alias a is name; alias a : subtype_indication is name; begin end generate; end;
architecture RTL of FIFO is begin CASE_LABEL : case data generate when a = 1 => signal signal1 : std_logic; constant con1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin when b = 2 => signal sig1 : std_logic; constant constant1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin when c = 2 => signal sig1 : std_logic; constant con1 : std_logic; shared variable vars1 : std_logic; alias a is name; alias a : subtype_indication is name; begin end generate; -- Violations below CASE_LABEL : case data generate when a = 1 => signal signal1 : std_logic; constant con1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin when b = 2 => signal sig1 : std_logic; constant constant1 : std_logic; shared variable var1 : std_logic; alias a is name; alias a : subtype_indication is name; begin when c = 2 => signal sig1 : std_logic; constant con1 : std_logic; shared variable vars1 : std_logic; alias a is name; alias a : subtype_indication is name; begin end generate; end;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity datapath is port ( clock: in std_logic; reset: in std_logic; stall: in std_logic; mwait: in std_logic; irq_vector: in std_logic_vector(31 downto 0); irq: in std_logic; irq_ack: out std_logic; exception: out std_logic; inst_addr: out std_logic_vector(31 downto 0); inst_in: in std_logic_vector(31 downto 0); data_addr: out std_logic_vector(31 downto 0); data_in: in std_logic_vector(31 downto 0); data_out: out std_logic_vector(31 downto 0); data_w: out std_logic_vector(3 downto 0); data_b: out std_logic; data_h: out std_logic; data_access: out std_logic ); end datapath; architecture arch_datapath of datapath is -- datapath signals signal inst_in_s, data_in_s, pc, pc_last, pc_last2, pc_plus4, pc_next, result, branch, ext32b, ext32h, alu_src1, alu_src2: std_logic_vector(31 downto 0); signal ext32: std_logic_vector(31 downto 12); signal opcode, funct7: std_logic_vector(6 downto 0); signal funct3: std_logic_vector(2 downto 0); signal read_reg1, read_reg2, write_reg: std_logic_vector(4 downto 0); signal rs1, rs2, rd: std_logic_vector(4 downto 0); signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0); signal imm_i, imm_s, imm_sb, imm_uj, branch_src1, branch_src2: std_logic_vector(31 downto 0); signal imm_u: std_logic_vector(31 downto 12); signal wreg, zero, less_than, branch_taken, jump_taken, stall_reg: std_logic; signal irq_ack_s, irq_ack_s_dly, bds, data_access_s, data_access_s_dly: std_logic; -- control signals signal reg_write_ctl, alu_src1_ctl, sig_read_ctl, reg_to_mem, mem_to_reg, except: std_logic; signal jump_ctl, mem_write_ctl, mem_read_ctl: std_logic_vector(1 downto 0); signal alu_src2_ctl, branch_ctl: std_logic_vector(2 downto 0); signal alu_op_ctl: std_logic_vector(3 downto 0); signal rs1_r, rs2_r, rd_r: std_logic_vector(4 downto 0); signal imm_i_r, imm_s_r, imm_sb_r, imm_uj_r: std_logic_vector(31 downto 0); signal imm_u_r: std_logic_vector(31 downto 12); signal reg_write_ctl_r, alu_src1_ctl_r, sig_read_ctl_r, reg_to_mem_r, mem_to_reg_r: std_logic; signal jump_ctl_r, mem_write_ctl_r, mem_read_ctl_r: std_logic_vector(1 downto 0); signal alu_src2_ctl_r, branch_ctl_r: std_logic_vector(2 downto 0); signal alu_op_ctl_r: std_logic_vector(3 downto 0); begin -- -- FETCH STAGE -- -- 1st stage, instruction memory access, PC update, interrupt acknowledge logic -- program counter logic process(clock, reset, reg_to_mem_r, mem_to_reg_r, stall, stall_reg) begin if reset = '1' then pc <= (others => '0'); pc_last <= (others => '0'); pc_last2 <= (others => '0'); elsif clock'event and clock = '1' then if stall = '0' then pc <= pc_next; pc_last <= pc; pc_last2 <= pc_last; end if; end if; end process; pc_plus4 <= pc + 4; pc_next <= irq_vector when (irq = '1' and irq_ack_s = '1') or except = '1' else branch when branch_taken = '1' or jump_taken = '1' else pc_last when data_access_s = '1' else pc_plus4; -- interrupt acknowledge logic irq_ack_s <= '1' when irq = '1' and bds = '0' and branch_taken = '0' and jump_taken = '0' and reg_to_mem_r = '0' and mem_to_reg_r = '0' else '0'; irq_ack <= irq_ack_s_dly; exception <= '1' when except = '1' else '0'; process(clock, reset, irq, irq_ack_s, mem_to_reg_r, stall, mwait) begin if reset = '1' then irq_ack_s_dly <= '0'; bds <= '0'; data_access_s_dly <= '0'; stall_reg <= '0'; elsif clock'event and clock = '1' then stall_reg <= stall; if stall = '0' then data_access_s_dly <= data_access_s; if mwait = '0' then irq_ack_s_dly <= irq_ack_s; if branch_taken = '1' or jump_taken = '1' then bds <= '1'; else bds <= '0'; end if; end if; end if; end if; end process; -- -- DECODE STAGE -- -- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and branches -- pipeline bubble insertion on loads/stores, exceptions, branches and interrupts inst_in_s <= x"00000000" when data_access_s = '1' or except = '1' or branch_taken = '1' or jump_taken = '1' or bds = '1' or irq_ack_s = '1' else inst_in(7 downto 0) & inst_in(15 downto 8) & inst_in(23 downto 16) & inst_in(31 downto 24); -- instruction decode opcode <= inst_in_s(6 downto 0); funct3 <= inst_in_s(14 downto 12); funct7 <= inst_in_s(31 downto 25); rd <= inst_in_s(11 downto 7); rs1 <= inst_in_s(19 downto 15); rs2 <= inst_in_s(24 downto 20); imm_i <= ext32(31 downto 12) & inst_in_s(31 downto 20); imm_s <= ext32(31 downto 12) & inst_in_s(31 downto 25) & inst_in_s(11 downto 7); imm_sb <= ext32(31 downto 13) & inst_in_s(31) & inst_in_s(7) & inst_in_s(30 downto 25) & inst_in_s(11 downto 8) & '0'; imm_u <= inst_in_s(31 downto 12); imm_uj <= ext32(31 downto 21) & inst_in_s(31) & inst_in_s(19 downto 12) & inst_in_s(20) & inst_in_s(30 downto 21) & '0'; ext32 <= (others => '1') when inst_in_s(31) = '1' else (others => '0'); -- control unit control_unit: entity work.control port map( opcode => opcode, funct3 => funct3, funct7 => funct7, reg_write => reg_write_ctl, alu_src1 => alu_src1_ctl, alu_src2 => alu_src2_ctl, alu_op => alu_op_ctl, jump => jump_ctl, branch => branch_ctl, mem_write => mem_write_ctl, mem_read => mem_read_ctl, sig_read => sig_read_ctl ); reg_to_mem <= '1' when mem_write_ctl /= "00" else '0'; mem_to_reg <= '1' when mem_read_ctl /= "00" else '0'; process(clock, reset, irq_ack_s, bds, stall, mwait) begin if reset = '1' then rd_r <= (others => '0'); rs1_r <= (others => '0'); rs2_r <= (others => '0'); imm_i_r <= (others => '0'); imm_s_r <= (others => '0'); imm_sb_r <= (others => '0'); imm_u_r <= (others => '0'); imm_uj_r <= (others => '0'); reg_write_ctl_r <= '0'; alu_src1_ctl_r <= '0'; alu_src2_ctl_r <= (others => '0'); alu_op_ctl_r <= (others => '0'); jump_ctl_r <= (others => '0'); branch_ctl_r <= (others => '0'); mem_write_ctl_r <= (others => '0'); mem_read_ctl_r <= (others => '0'); sig_read_ctl_r <= '0'; reg_to_mem_r <= '0'; mem_to_reg_r <= '0'; elsif clock'event and clock = '1' then if stall = '0' and mwait = '0' then rd_r <= rd; rs1_r <= rs1; rs2_r <= rs2; imm_i_r <= imm_i; imm_s_r <= imm_s; imm_sb_r <= imm_sb; imm_u_r <= imm_u; imm_uj_r <= imm_uj; reg_write_ctl_r <= reg_write_ctl; alu_src1_ctl_r <= alu_src1_ctl; alu_src2_ctl_r <= alu_src2_ctl; alu_op_ctl_r <= alu_op_ctl; jump_ctl_r <= jump_ctl; branch_ctl_r <= branch_ctl; mem_write_ctl_r <= mem_write_ctl; mem_read_ctl_r <= mem_read_ctl; sig_read_ctl_r <= sig_read_ctl; reg_to_mem_r <= reg_to_mem; mem_to_reg_r <= mem_to_reg; end if; end if; end process; -- -- EXECUTE STAGE -- -- 3rd stage (a) register file access (read) -- the register file register_bank: entity work.reg_bank port map( clock => clock, read_reg1 => read_reg1, read_reg2 => read_reg2, write_reg => write_reg, wreg => wreg, write_data => write_data, read_data1 => read_data1, read_data2 => read_data2 ); -- register file read/write selection and write enable read_reg1 <= rs1_r; read_reg2 <= rs2_r; write_reg <= rd_r; wreg <= (reg_write_ctl_r or mem_to_reg_r) and not mwait and not stall_reg; -- 3rd stage (b) ALU operation alu: entity work.alu port map( op1 => alu_src1, op2 => alu_src2, alu_op => alu_op_ctl_r, result => result, zero => zero, less_than => less_than ); alu_src1 <= read_data1 when alu_src1_ctl_r = '0' else pc_last2; alu_src2 <= imm_u_r & x"000" when alu_src2_ctl_r = "000" else imm_i_r when alu_src2_ctl_r = "001" else imm_s_r when alu_src2_ctl_r = "010" else pc when alu_src2_ctl_r = "011" else x"000000" & "000" & rs2_r when alu_src2_ctl_r = "100" else read_data2; branch_src1 <= read_data1 when jump_ctl_r = "11" else pc_last2; branch_src2 <= imm_uj_r when jump_ctl_r = "10" else imm_i_r when jump_ctl_r = "11" else imm_sb_r; branch <= branch_src1 + branch_src2; branch_taken <= '1' when (zero = '1' and branch_ctl_r = "001") or -- BEQ (zero = '0' and branch_ctl_r = "010") or -- BNE (less_than = '1' and branch_ctl_r = "011") or -- BLT (less_than = '0' and branch_ctl_r = "100") or -- BGE (less_than = '1' and branch_ctl_r = "101") or -- BLTU (less_than = '0' and branch_ctl_r = "110") -- BGEU else '0'; except <= '1' when branch_ctl_r = "111" else '0'; jump_taken <= '1' when jump_ctl_r /= "00" else '0'; inst_addr <= pc; data_addr <= result; data_b <= '1' when mem_read_ctl_r = "01" or mem_write_ctl_r = "01" else '0'; data_h <= '1' when mem_read_ctl_r = "10" or mem_write_ctl_r = "10" else '0'; data_access_s <= '1' when reg_to_mem_r = '1' or mem_to_reg_r = '1' else '0'; data_access <= '1' when data_access_s = '1' and data_access_s_dly = '0' else '0'; -- 3rd stage (c) data memory / write back operation, register file access (write) -- memory access, store operations process(mem_write_ctl_r, result, read_data2) begin case mem_write_ctl_r is when "11" => -- store word data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(23 downto 16) & read_data2(31 downto 24); data_w <= "1111"; when "01" => -- store byte data_out <= read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0); case result(1 downto 0) is when "11" => data_w <= "0001"; when "10" => data_w <= "0010"; when "01" => data_w <= "0100"; when others => data_w <= "1000"; end case; when "10" => -- store half word data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(7 downto 0) & read_data2(15 downto 8); case result(1) is when '1' => data_w <= "0011"; when others => data_w <= "1100"; end case; when others => -- WTF?? data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(23 downto 16) & read_data2(31 downto 24); data_w <= "0000"; end case; end process; -- memory access, load operations process(mem_read_ctl_r, result, data_in) begin case mem_read_ctl_r is when "01" => -- load byte case result(1 downto 0) is when "11" => data_in_s <= x"000000" & data_in(7 downto 0); when "10" => data_in_s <= x"000000" & data_in(15 downto 8); when "01" => data_in_s <= x"000000" & data_in(23 downto 16); when others => data_in_s <= x"000000" & data_in(31 downto 24); end case; when "10" => -- load half word case result(1) is when '1' => data_in_s <= x"0000" & data_in(7 downto 0) & data_in(15 downto 8); when others => data_in_s <= x"0000" & data_in(23 downto 16) & data_in(31 downto 24); end case; when others => -- load word data_in_s <= data_in(7 downto 0) & data_in(15 downto 8) & data_in(23 downto 16) & data_in(31 downto 24); end case; end process; -- write back ext32b <= x"000000" & data_in_s(7 downto 0) when (data_in_s(7) = '0' or sig_read_ctl_r = '0') else x"ffffff" & data_in_s(7 downto 0); ext32h <= x"0000" & data_in_s(15 downto 0) when (data_in_s(15) = '0' or sig_read_ctl_r = '0') else x"ffff" & data_in_s(15 downto 0); write_data <= data_in_s when mem_read_ctl_r = "11" else ext32b when mem_read_ctl_r = "01" else ext32h when mem_read_ctl_r = "10" else pc_last when jump_taken = '1' else result; end arch_datapath;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.devices.all; library gaisler; use gaisler.ddrpkg.all; entity ddr3if is generic ( hindex: integer; haddr: integer := 16#400#; hmask: integer := 16#000#; burstlen: integer := 8 ); port ( pll_ref_clk: in std_ulogic; global_reset_n: in std_ulogic; mem_a: out std_logic_vector(13 downto 0); mem_ba: out std_logic_vector(2 downto 0); mem_ck: out std_ulogic; mem_ck_n: out std_ulogic; mem_cke: out std_ulogic; mem_reset_n: out std_ulogic; mem_cs_n: out std_ulogic; mem_dm: out std_logic_vector(3 downto 0); mem_ras_n: out std_ulogic; mem_cas_n: out std_ulogic; mem_we_n: out std_ulogic; mem_dq: inout std_logic_vector(31 downto 0); mem_dqs: inout std_logic_vector(3 downto 0); mem_dqs_n: inout std_logic_vector(3 downto 0); mem_odt: out std_ulogic; oct_rzqin: in std_logic; ahb_clk: in std_ulogic; ahb_rst: in std_ulogic; ahbsi: in ahb_slv_in_type; ahbso: out ahb_slv_out_type ); end; architecture rtl of ddr3if is component ddr3ctrl1 is port ( pll_ref_clk : in std_logic := 'X'; -- clk global_reset_n : in std_logic := 'X'; -- reset_n soft_reset_n : in std_logic := 'X'; -- reset_n afi_clk : out std_logic; -- clk afi_half_clk : out std_logic; -- clk afi_reset_n : out std_logic; -- reset_n afi_reset_export_n : out std_logic; -- reset_n mem_a : out std_logic_vector(13 downto 0); -- mem_a mem_ba : out std_logic_vector(2 downto 0); -- mem_ba mem_ck : out std_logic_vector(0 downto 0); -- mem_ck mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n mem_cke : out std_logic_vector(0 downto 0); -- mem_cke mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n mem_dm : out std_logic_vector(3 downto 0); -- mem_dm mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n mem_reset_n : out std_logic; -- mem_reset_n mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n mem_odt : out std_logic_vector(0 downto 0); -- mem_odt avl_ready : out std_logic; -- waitrequest_n avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address avl_rdata_valid : out std_logic; -- readdatavalid avl_rdata : out std_logic_vector(127 downto 0); -- readdata avl_wdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata avl_be : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable avl_read_req : in std_logic := 'X'; -- read avl_write_req : in std_logic := 'X'; -- write avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount local_init_done : out std_logic; -- local_init_done local_cal_success : out std_logic; -- local_cal_success local_cal_fail : out std_logic; -- local_cal_fail oct_rzqin : in std_logic := 'X'; -- rzqin pll_mem_clk : out std_logic; -- pll_mem_clk pll_write_clk : out std_logic; -- pll_write_clk pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk pll_locked : out std_logic; -- pll_locked pll_avl_clk : out std_logic; -- pll_avl_clk pll_config_clk : out std_logic; -- pll_config_clk pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk afi_phy_clk : out std_logic; -- afi_phy_clk pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk ); end component ddr3ctrl1; signal vcc: std_ulogic; signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic; signal local_init_done, local_cal_success, local_cal_fail: std_ulogic; signal ck_p_arr, ck_n_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0); signal rasn_arr, casn_arr, wen_arr, odt_arr: std_logic_vector(0 downto 0); signal avlsi: ddravl_slv_in_type; signal avlso: ddravl_slv_out_type; begin vcc <= '1'; mem_ck <= ck_p_arr(0); mem_ck_n <= ck_n_arr(0); mem_cke <= cke_arr(0); mem_cs_n <= cs_arr(0); mem_ras_n <= rasn_arr(0); mem_cas_n <= casn_arr(0); mem_we_n <= wen_arr(0); mem_odt <= odt_arr(0); ctrl0: ddr3ctrl1 port map ( pll_ref_clk => pll_ref_clk, global_reset_n => global_reset_n, soft_reset_n => vcc, afi_clk => afi_clk, afi_half_clk => afi_half_clk, afi_reset_n => afi_reset_n, afi_reset_export_n => open, mem_a => mem_a, mem_ba => mem_ba, mem_ck => ck_p_arr, mem_ck_n => ck_n_arr, mem_cke => cke_arr, mem_cs_n => cs_arr, mem_dm => mem_dm, mem_ras_n => rasn_arr, mem_cas_n => casn_arr, mem_we_n => wen_arr, mem_reset_n => mem_reset_n, mem_dq => mem_dq, mem_dqs => mem_dqs, mem_dqs_n => mem_dqs_n, mem_odt => odt_arr, avl_ready => avlso.ready, avl_burstbegin => avlsi.burstbegin, avl_addr => avlsi.addr(24 downto 0), avl_rdata_valid => avlso.rdata_valid, avl_rdata => avlso.rdata(127 downto 0), avl_wdata => avlsi.wdata(127 downto 0), avl_be => avlsi.be(15 downto 0), avl_read_req => avlsi.read_req, avl_write_req => avlsi.write_req, avl_size => avlsi.size(2 downto 0), local_init_done => local_init_done, local_cal_success => local_cal_success, local_cal_fail => local_cal_fail, oct_rzqin => oct_rzqin, pll_mem_clk => open, pll_write_clk => open, pll_write_clk_pre_phy_clk => open, pll_addr_cmd_clk => open, pll_locked => open, pll_avl_clk => open, pll_config_clk => open, pll_mem_phy_clk => open, afi_phy_clk => open, pll_avl_phy_clk => open ); avlso.rdata(avlso.rdata'high downto 128) <= (others => '0'); ahb2avl0: ahb2avl_async generic map ( hindex => hindex, haddr => haddr, hmask => hmask, burstlen => burstlen, nosync => 0, avldbits => 128, avlabits => 25 ) port map ( rst_ahb => ahb_rst, clk_ahb => ahb_clk, ahbsi => ahbsi, ahbso => ahbso, rst_avl => afi_reset_n, clk_avl => afi_clk, avlsi => avlsi, avlso => avlso ); end;
------------------------------------------------------------------------------- -- Entity : axi_powerlink ------------------------------------------------------------------------------- -- -- (c) B&R, 2012 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- Design unit header -- -- -- This is the toplevel file for using the POWERLINK IP-Core -- with Xilinx AXI. -- ------------------------------------------------------------------------------- -- -- 2012-01-12 V0.01 zelenkaj First version -- 2012-01-26 V0.02 zelenkaj Added number of SMI generic feature -- 2012-01-27 V0.10 zelenkaj Incremented PdiRev -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.math_real.log2; use ieee.math_real.ceil; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; use proc_common_v3_00_a.ipif_pkg.all; library axi_lite_ipif_v1_01_a; use axi_lite_ipif_v1_01_a.axi_lite_ipif; library axi_master_burst_v1_00_a; use axi_master_burst_v1_00_a.axi_master_burst; -- standard libraries declarations library UNISIM; use UNISIM.vcomponents.all; -- pragma synthesis_off library IEEE; use IEEE.vital_timing.all; -- pragma synthesis_on -- other libraries declarations library AXI_LITE_IPIF_V1_01_A; library AXI_MASTER_BURST_V1_00_A; entity axi_powerlink is generic( -- general C_GEN_PDI : boolean := false; C_GEN_PAR_IF : boolean := false; C_GEN_SPI_IF : boolean := false; C_GEN_AXI_BUS_IF : boolean := false; C_GEN_SIMPLE_IO : boolean := false; -- openMAC C_MAC_PKT_SIZE : integer := 1024; C_MAC_PKT_SIZE_LOG2 : integer := 10; C_MAC_RX_BUFFERS : integer := 16; C_USE_RMII : boolean := false; C_TX_INT_PKT : boolean := false; C_RX_INT_PKT : boolean := false; C_USE_2ND_PHY : boolean := true; C_NUM_SMI : integer range 1 to 2 := 2; --pdi C_PDI_GEN_ASYNC_BUF_0 : boolean := true; C_PDI_ASYNC_BUF_0 : integer := 50; C_PDI_GEN_ASYNC_BUF_1 : boolean := true; C_PDI_ASYNC_BUF_1 : integer := 50; C_PDI_GEN_LED : boolean := false; C_PDI_GEN_TIME_SYNC : boolean := true; C_PDI_GEN_SECOND_TIMER : boolean := false; C_PDI_GEN_EVENT : boolean := true; --global pdi and mac C_NUM_RPDO : integer := 3; C_RPDO_0_BUF_SIZE : integer := 100; C_RPDO_1_BUF_SIZE : integer := 100; C_RPDO_2_BUF_SIZE : integer := 100; C_NUM_TPDO : integer := 1; C_TPDO_BUF_SIZE : integer := 100; -- pap C_PAP_DATA_WIDTH : integer := 16; --C_PAP_BIG_END : boolean := false; C_PAP_LOW_ACT : boolean := false; -- spi C_SPI_CPOL : boolean := false; C_SPI_CPHA : boolean := false; --C_SPI_BIG_END : boolean := false; -- simpleIO C_PIO_VAL_LENGTH : integer := 50; -- debug C_OBSERVER_ENABLE : boolean := false; -- clock stabiliser C_INSTANCE_ODDR2 : boolean := false; -- PDI AP AXI Slave C_S_AXI_PDI_AP_BASEADDR : std_logic_vector := X"00000000"; C_S_AXI_PDI_AP_HIGHADDR : std_logic_vector := X"000FFFFF"; C_S_AXI_PDI_AP_DATA_WIDTH : integer := 32; C_S_AXI_PDI_AP_ADDR_WIDTH : integer := 32; C_S_AXI_PDI_AP_USE_WSTRB : integer := 1; C_S_AXI_PDI_AP_DPHASE_TIMEOUT : integer := 8; -- PDI AP AXI Slave C_S_AXI_SMP_PCP_BASEADDR : std_logic_vector := X"00000000"; C_S_AXI_SMP_PCP_HIGHADDR : std_logic_vector := X"000FFFFF"; C_S_AXI_SMP_PCP_DATA_WIDTH : integer := 32; C_S_AXI_SMP_PCP_ADDR_WIDTH : integer := 32; C_S_AXI_SMP_PCP_USE_WSTRB : integer := 1; C_S_AXI_SMP_PCP_DPHASE_TIMEOUT : integer := 8; -- PDI PCP AXI Slave C_S_AXI_PDI_PCP_BASEADDR : std_logic_vector := X"00000000"; C_S_AXI_PDI_PCP_HIGHADDR : std_logic_vector := X"000FFFFF"; C_S_AXI_PDI_PCP_DATA_WIDTH : integer := 32; C_S_AXI_PDI_PCP_ADDR_WIDTH : integer := 32; C_S_AXI_PDI_PCP_USE_WSTRB : integer := 1; C_S_AXI_PDI_PCP_DPHASE_TIMEOUT : integer := 8; -- openMAC DMA AXI Master C_M_AXI_MAC_DMA_ADDR_WIDTH : INTEGER := 32; C_M_AXI_MAC_DMA_DATA_WIDTH : INTEGER := 32; C_M_AXI_MAC_DMA_NATIVE_DWIDTH : INTEGER := 32; C_M_AXI_MAC_DMA_LENGTH_WIDTH : INTEGER := 12; C_M_AXI_MAC_DMA_MAX_BURST_LEN : INTEGER := 16; C_MAC_DMA_BURST_SIZE_RX : INTEGER := 8; --in bytes C_MAC_DMA_BURST_SIZE_TX : INTEGER := 8; --in bytes C_MAC_DMA_FIFO_SIZE_RX : INTEGER := 32; --in bytes C_MAC_DMA_FIFO_SIZE_TX : INTEGER := 32; --in bytes -- openMAC PKT AXI Slave C_S_AXI_MAC_PKT_BASEADDR : std_logic_vector := X"00000000"; C_S_AXI_MAC_PKT_HIGHADDR : std_logic_vector := X"000FFFFF"; C_S_AXI_MAC_PKT_DATA_WIDTH : integer := 32; C_S_AXI_MAC_PKT_ADDR_WIDTH : integer := 32; C_S_AXI_MAC_PKT_USE_WSTRB : integer := 1; C_S_AXI_MAC_PKT_DPHASE_TIMEOUT : integer := 8; -- openMAC REG AXI Slave --- MAC_REG C_S_AXI_MAC_REG_RNG0_BASEADDR : std_logic_vector := X"00000000"; C_S_AXI_MAC_REG_RNG0_HIGHADDR : std_logic_vector := X"0000FFFF"; --- MAC_CMP C_S_AXI_MAC_REG_RNG1_BASEADDR : std_logic_vector := X"00000000"; C_S_AXI_MAC_REG_RNG1_HIGHADDR : std_logic_vector := X"0000FFFF"; C_S_AXI_MAC_REG_DATA_WIDTH : integer := 32; C_S_AXI_MAC_REG_ADDR_WIDTH : integer := 32; C_S_AXI_MAC_REG_USE_WSTRB : integer := 1; C_S_AXI_MAC_REG_DPHASE_TIMEOUT : integer := 8; C_S_AXI_MAC_REG_ACLK_FREQ_HZ : integer := 20 --clock frequency in Hz ); port( M_AXI_MAC_DMA_aclk : in std_logic; M_AXI_MAC_DMA_aresetn : in std_logic; M_AXI_MAC_DMA_arready : in std_logic; M_AXI_MAC_DMA_awready : in std_logic; M_AXI_MAC_DMA_bvalid : in std_logic; M_AXI_MAC_DMA_rlast : in std_logic; M_AXI_MAC_DMA_rvalid : in std_logic; M_AXI_MAC_DMA_wready : in std_logic; S_AXI_MAC_PKT_ACLK : in std_logic; S_AXI_MAC_PKT_ARESETN : in std_logic; S_AXI_MAC_PKT_ARVALID : in std_logic; S_AXI_MAC_PKT_AWVALID : in std_logic; S_AXI_MAC_PKT_BREADY : in std_logic; S_AXI_MAC_PKT_RREADY : in std_logic; S_AXI_MAC_PKT_WVALID : in std_logic; S_AXI_MAC_REG_ACLK : in std_logic; S_AXI_MAC_REG_ARESETN : in std_logic; S_AXI_MAC_REG_ARVALID : in std_logic; S_AXI_MAC_REG_AWVALID : in std_logic; S_AXI_MAC_REG_BREADY : in std_logic; S_AXI_MAC_REG_RREADY : in std_logic; S_AXI_MAC_REG_WVALID : in std_logic; S_AXI_PDI_AP_ACLK : in std_logic; S_AXI_PDI_AP_ARESETN : in std_logic; S_AXI_PDI_AP_ARVALID : in std_logic; S_AXI_PDI_AP_AWVALID : in std_logic; S_AXI_PDI_AP_BREADY : in std_logic; S_AXI_PDI_AP_RREADY : in std_logic; S_AXI_PDI_AP_WVALID : in std_logic; S_AXI_PDI_PCP_ACLK : in std_logic; S_AXI_PDI_PCP_ARESETN : in std_logic; S_AXI_PDI_PCP_ARVALID : in std_logic; S_AXI_PDI_PCP_AWVALID : in std_logic; S_AXI_PDI_PCP_BREADY : in std_logic; S_AXI_PDI_PCP_RREADY : in std_logic; S_AXI_PDI_PCP_WVALID : in std_logic; S_AXI_SMP_PCP_ACLK : in std_logic; S_AXI_SMP_PCP_ARESETN : in std_logic; S_AXI_SMP_PCP_ARVALID : in std_logic; S_AXI_SMP_PCP_AWVALID : in std_logic; S_AXI_SMP_PCP_BREADY : in std_logic; S_AXI_SMP_PCP_RREADY : in std_logic; S_AXI_SMP_PCP_WVALID : in std_logic; clk100 : in std_logic; pap_cs : in std_logic; pap_cs_n : in std_logic; pap_rd : in std_logic; pap_rd_n : in std_logic; pap_wr : in std_logic; pap_wr_n : in std_logic; phy0_RxDv : in std_logic; phy0_RxErr : in std_logic; phy0_SMIDat_I : in std_logic; phy0_link : in std_logic; phy1_RxDv : in std_logic; phy1_RxErr : in std_logic; phy1_SMIDat_I : in std_logic; phy1_link : in std_logic; phyMii0_RxClk : in std_logic; phyMii0_RxDv : in std_logic; phyMii0_RxEr : in std_logic; phyMii0_TxClk : in std_logic; phyMii1_RxClk : in std_logic; phyMii1_RxDv : in std_logic; phyMii1_RxEr : in std_logic; phyMii1_TxClk : in std_logic; phy_SMIDat_I : in std_logic; spi_clk : in std_logic; spi_mosi : in std_logic; spi_sel_n : in std_logic; M_AXI_MAC_DMA_bresp : in std_logic_vector(1 downto 0); M_AXI_MAC_DMA_rdata : in std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0); M_AXI_MAC_DMA_rresp : in std_logic_vector(1 downto 0); S_AXI_MAC_PKT_ARADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0); S_AXI_MAC_PKT_AWADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0); S_AXI_MAC_PKT_WDATA : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0); S_AXI_MAC_PKT_WSTRB : in std_logic_vector((C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0); S_AXI_MAC_REG_ARADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0); S_AXI_MAC_REG_AWADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0); S_AXI_MAC_REG_WDATA : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); S_AXI_MAC_REG_WSTRB : in std_logic_vector((C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0); S_AXI_PDI_AP_ARADDR : in std_logic_vector(C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0); S_AXI_PDI_AP_AWADDR : in std_logic_vector(C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0); S_AXI_PDI_AP_WDATA : in std_logic_vector(C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0); S_AXI_PDI_AP_WSTRB : in std_logic_vector((C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0); S_AXI_PDI_PCP_ARADDR : in std_logic_vector(C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0); S_AXI_PDI_PCP_AWADDR : in std_logic_vector(C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0); S_AXI_PDI_PCP_WDATA : in std_logic_vector(C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0); S_AXI_PDI_PCP_WSTRB : in std_logic_vector((C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0); S_AXI_SMP_PCP_ARADDR : in std_logic_vector(C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0); S_AXI_SMP_PCP_AWADDR : in std_logic_vector(C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0); S_AXI_SMP_PCP_WDATA : in std_logic_vector(C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0); S_AXI_SMP_PCP_WSTRB : in std_logic_vector((C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0); pap_addr : in std_logic_vector(15 downto 0); pap_be : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0); pap_be_n : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0); pap_data_I : in std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0); pap_gpio_I : in std_logic_vector(1 downto 0); phy0_RxDat : in std_logic_vector(1 downto 0); phy1_RxDat : in std_logic_vector(1 downto 0); phyMii0_RxDat : in std_logic_vector(3 downto 0); phyMii1_RxDat : in std_logic_vector(3 downto 0); pio_pconfig : in std_logic_vector(3 downto 0); pio_portInLatch : in std_logic_vector(3 downto 0); pio_portio_I : in std_logic_vector(31 downto 0); M_AXI_MAC_DMA_arvalid : out std_logic; M_AXI_MAC_DMA_awvalid : out std_logic; M_AXI_MAC_DMA_bready : out std_logic; M_AXI_MAC_DMA_md_error : out std_logic; M_AXI_MAC_DMA_rready : out std_logic; M_AXI_MAC_DMA_wlast : out std_logic; M_AXI_MAC_DMA_wvalid : out std_logic; S_AXI_MAC_PKT_ARREADY : out std_logic; S_AXI_MAC_PKT_AWREADY : out std_logic; S_AXI_MAC_PKT_BVALID : out std_logic; S_AXI_MAC_PKT_RVALID : out std_logic; S_AXI_MAC_PKT_WREADY : out std_logic; S_AXI_MAC_REG_ARREADY : out std_logic; S_AXI_MAC_REG_AWREADY : out std_logic; S_AXI_MAC_REG_BVALID : out std_logic; S_AXI_MAC_REG_RVALID : out std_logic; S_AXI_MAC_REG_WREADY : out std_logic; S_AXI_PDI_AP_ARREADY : out std_logic; S_AXI_PDI_AP_AWREADY : out std_logic; S_AXI_PDI_AP_BVALID : out std_logic; S_AXI_PDI_AP_RVALID : out std_logic; S_AXI_PDI_AP_WREADY : out std_logic; S_AXI_PDI_PCP_ARREADY : out std_logic; S_AXI_PDI_PCP_AWREADY : out std_logic; S_AXI_PDI_PCP_BVALID : out std_logic; S_AXI_PDI_PCP_RVALID : out std_logic; S_AXI_PDI_PCP_WREADY : out std_logic; S_AXI_SMP_PCP_ARREADY : out std_logic; S_AXI_SMP_PCP_AWREADY : out std_logic; S_AXI_SMP_PCP_BVALID : out std_logic; S_AXI_SMP_PCP_RVALID : out std_logic; S_AXI_SMP_PCP_WREADY : out std_logic; ap_asyncIrq : out std_logic; ap_asyncIrq_n : out std_logic; ap_syncIrq : out std_logic; ap_syncIrq_n : out std_logic; led_error : out std_logic; led_status : out std_logic; mac_irq : out std_logic; pap_ack : out std_logic; pap_ack_n : out std_logic; pap_data_T : out std_logic; phy0_Rst_n : out std_logic; phy0_SMIClk : out std_logic; phy0_SMIDat_O : out std_logic; phy0_SMIDat_T : out std_logic; phy0_TxEn : out std_logic; phy0_clk : out std_logic; phy1_Rst_n : out std_logic; phy1_SMIClk : out std_logic; phy1_SMIDat_O : out std_logic; phy1_SMIDat_T : out std_logic; phy1_TxEn : out std_logic; phy1_clk : out std_logic; phyMii0_TxEn : out std_logic; phyMii0_TxEr : out std_logic; phyMii1_TxEn : out std_logic; phyMii1_TxEr : out std_logic; phy_Rst_n : out std_logic; phy_SMIClk : out std_logic; phy_SMIDat_O : out std_logic; phy_SMIDat_T : out std_logic; pio_operational : out std_logic; spi_miso : out std_logic; tcp_irq : out std_logic; M_AXI_MAC_DMA_araddr : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0); M_AXI_MAC_DMA_arburst : out std_logic_vector(1 downto 0); M_AXI_MAC_DMA_arcache : out std_logic_vector(3 downto 0); M_AXI_MAC_DMA_arlen : out std_logic_vector(7 downto 0); M_AXI_MAC_DMA_arprot : out std_logic_vector(2 downto 0); M_AXI_MAC_DMA_arsize : out std_logic_vector(2 downto 0); M_AXI_MAC_DMA_awaddr : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0); M_AXI_MAC_DMA_awburst : out std_logic_vector(1 downto 0); M_AXI_MAC_DMA_awcache : out std_logic_vector(3 downto 0); M_AXI_MAC_DMA_awlen : out std_logic_vector(7 downto 0); M_AXI_MAC_DMA_awprot : out std_logic_vector(2 downto 0); M_AXI_MAC_DMA_awsize : out std_logic_vector(2 downto 0); M_AXI_MAC_DMA_wdata : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0); M_AXI_MAC_DMA_wstrb : out std_logic_vector((C_M_AXI_MAC_DMA_DATA_WIDTH/8)-1 downto 0); S_AXI_MAC_PKT_BRESP : out std_logic_vector(1 downto 0); S_AXI_MAC_PKT_RDATA : out std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0); S_AXI_MAC_PKT_RRESP : out std_logic_vector(1 downto 0); S_AXI_MAC_REG_BRESP : out std_logic_vector(1 downto 0); S_AXI_MAC_REG_RDATA : out std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); S_AXI_MAC_REG_RRESP : out std_logic_vector(1 downto 0); S_AXI_PDI_AP_BRESP : out std_logic_vector(1 downto 0); S_AXI_PDI_AP_RDATA : out std_logic_vector(C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0); S_AXI_PDI_AP_RRESP : out std_logic_vector(1 downto 0); S_AXI_PDI_PCP_BRESP : out std_logic_vector(1 downto 0); S_AXI_PDI_PCP_RDATA : out std_logic_vector(C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0); S_AXI_PDI_PCP_RRESP : out std_logic_vector(1 downto 0); S_AXI_SMP_PCP_BRESP : out std_logic_vector(1 downto 0); S_AXI_SMP_PCP_RDATA : out std_logic_vector(C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0); S_AXI_SMP_PCP_RRESP : out std_logic_vector(1 downto 0); led_gpo : out std_logic_vector(7 downto 0); led_opt : out std_logic_vector(1 downto 0); led_phyAct : out std_logic_vector(1 downto 0); led_phyLink : out std_logic_vector(1 downto 0); pap_data_O : out std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0); pap_gpio_O : out std_logic_vector(1 downto 0); pap_gpio_T : out std_logic_vector(1 downto 0); phy0_TxDat : out std_logic_vector(1 downto 0); phy1_TxDat : out std_logic_vector(1 downto 0); phyMii0_TxDat : out std_logic_vector(3 downto 0); phyMii1_TxDat : out std_logic_vector(3 downto 0); pio_portOutValid : out std_logic_vector(3 downto 0); pio_portio_O : out std_logic_vector(31 downto 0); pio_portio_T : out std_logic_vector(31 downto 0); test_port : out std_logic_vector(255 downto 0) := (others => '0') ); -- Entity declarations -- -- Click here to add additional declarations -- attribute SIGIS : string; -- Entity attributes -- attribute SIGIS of M_AXI_MAC_DMA_aclk : signal is "Clk"; attribute SIGIS of M_AXI_MAC_DMA_aresetn : signal is "Rst"; attribute SIGIS of S_AXI_MAC_PKT_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_MAC_PKT_ARESETN : signal is "Rst"; attribute SIGIS of S_AXI_MAC_REG_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_MAC_REG_ARESETN : signal is "Rst"; attribute SIGIS of S_AXI_PDI_AP_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_PDI_AP_ARESETN : signal is "Rst"; attribute SIGIS of S_AXI_PDI_PCP_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_PDI_PCP_ARESETN : signal is "Rst"; attribute SIGIS of S_AXI_SMP_PCP_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_SMP_PCP_ARESETN : signal is "Rst"; attribute SIGIS of clk100 : signal is "Clk"; attribute SIGIS of phy0_clk : signal is "Clk"; attribute SIGIS of phy1_clk : signal is "Clk"; end axi_powerlink; architecture struct of axi_powerlink is ---- Architecture declarations ----- function get_max( a, b : integer) return integer is begin if a < b then return b; else return a; end if; end get_max; ---- Component declarations ----- component ipif_master_handler generic( C_MAC_DMA_IPIF_AWIDTH : integer := 32; C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32; dma_highadr_g : integer := 31; gen_rx_fifo_g : boolean := true; gen_tx_fifo_g : boolean := true; m_burstcount_width_g : integer := 4 ); port ( Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0); Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1'; Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0); Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1'; Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1'; Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1'; Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1'; Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1'; Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0'; Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0'; Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0'; Bus2MAC_DMA_Mst_Error : in std_logic := '0'; Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0'; MAC_DMA_CLK : in std_logic; MAC_DMA_Rst : in std_logic; m_address : in std_logic_vector(dma_highadr_g downto 0); m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0); m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0); m_byteenable : in std_logic_vector(3 downto 0); m_read : in std_logic := '0'; m_write : in std_logic := '0'; m_writedata : in std_logic_vector(31 downto 0); MAC_DMA2Bus_MstRd_Req : out std_logic := '0'; MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1'; MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1'; MAC_DMA2Bus_MstWr_Req : out std_logic := '0'; MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0); MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1'; MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0); MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1'; MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1'; MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1'; MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0); MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0); MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0); MAC_DMA2Bus_Mst_Lock : out std_logic := '0'; MAC_DMA2Bus_Mst_Reset : out std_logic := '0'; MAC_DMA2Bus_Mst_Type : out std_logic := '0'; m_clk : out std_logic; m_readdata : out std_logic_vector(31 downto 0); m_readdatavalid : out std_logic := '0'; m_waitrequest : out std_logic := '1' ); end component; component openMAC_16to32conv generic( bus_address_width : integer := 10; gEndian : string := "little" ); port ( bus_address : in std_logic_vector(bus_address_width-1 downto 0); bus_byteenable : in std_logic_vector(3 downto 0); bus_read : in std_logic; bus_select : in std_logic; bus_write : in std_logic; bus_writedata : in std_logic_vector(31 downto 0); clk : in std_logic; rst : in std_logic; s_readdata : in std_logic_vector(15 downto 0); s_waitrequest : in std_logic; bus_ack_rd : out std_logic; bus_ack_wr : out std_logic; bus_readdata : out std_logic_vector(31 downto 0); s_address : out std_logic_vector(bus_address_width-1 downto 0); s_byteenable : out std_logic_vector(1 downto 0); s_chipselect : out std_logic; s_read : out std_logic; s_write : out std_logic; s_writedata : out std_logic_vector(15 downto 0) ); end component; component powerlink generic( Simulate : boolean := false; endian_g : string := "little"; gNumSmi : integer range 1 to 2 := 2; genABuf1_g : boolean := true; genABuf2_g : boolean := true; genEvent_g : boolean := false; genInternalAp_g : boolean := true; genIoBuf_g : boolean := true; genLedGadget_g : boolean := false; genOnePdiClkDomain_g : boolean := false; genPdi_g : boolean := true; genSimpleIO_g : boolean := false; genSmiIO : boolean := true; genSpiAp_g : boolean := false; genTimeSync_g : boolean := false; gen_dma_observer_g : boolean := true; iAsyBuf1Size_g : integer := 100; iAsyBuf2Size_g : integer := 100; iBufSizeLOG2_g : integer := 10; iBufSize_g : integer := 1024; iPdiRev_g : integer := 21930; iRpdo0BufSize_g : integer := 100; iRpdo1BufSize_g : integer := 100; iRpdo2BufSize_g : integer := 100; iRpdos_g : integer := 3; iTpdoBufSize_g : integer := 100; iTpdos_g : integer := 1; m_burstcount_const_g : boolean := true; m_burstcount_width_g : integer := 4; m_data_width_g : integer := 16; m_rx_burst_size_g : integer := 16; m_rx_fifo_size_g : integer := 16; m_tx_burst_size_g : integer := 16; m_tx_fifo_size_g : integer := 16; papBigEnd_g : boolean := false; papDataWidth_g : integer := 8; papLowAct_g : boolean := false; pioValLen_g : integer := 50; spiBigEnd_g : boolean := false; spiCPHA_g : boolean := false; spiCPOL_g : boolean := false; use2ndCmpTimer_g : boolean := true; use2ndPhy_g : boolean := true; useIntPacketBuf_g : boolean := true; useRmii_g : boolean := true; useRxIntPacketBuf_g : boolean := true ); port ( ap_address : in std_logic_vector(12 downto 0); ap_byteenable : in std_logic_vector(3 downto 0); ap_chipselect : in std_logic; ap_read : in std_logic; ap_write : in std_logic; ap_writedata : in std_logic_vector(31 downto 0); clk50 : in std_logic; clkAp : in std_logic; clkEth : in std_logic; clkPcp : in std_logic; m_clk : in std_logic; m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0'); m_readdatavalid : in std_logic := '0'; m_waitrequest : in std_logic; mac_address : in std_logic_vector(11 downto 0); mac_byteenable : in std_logic_vector(1 downto 0); mac_chipselect : in std_logic; mac_read : in std_logic; mac_write : in std_logic; mac_writedata : in std_logic_vector(15 downto 0); mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0); mbf_byteenable : in std_logic_vector(3 downto 0); mbf_chipselect : in std_logic; mbf_read : in std_logic; mbf_write : in std_logic; mbf_writedata : in std_logic_vector(31 downto 0); pap_addr : in std_logic_vector(15 downto 0); pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0); pap_cs : in std_logic; pap_cs_n : in std_logic; pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0'); pap_rd : in std_logic; pap_rd_n : in std_logic; pap_wr : in std_logic; pap_wr_n : in std_logic; pcp_address : in std_logic_vector(12 downto 0); pcp_byteenable : in std_logic_vector(3 downto 0); pcp_chipselect : in std_logic; pcp_read : in std_logic; pcp_write : in std_logic; pcp_writedata : in std_logic_vector(31 downto 0); phy0_RxDat : in std_logic_vector(1 downto 0); phy0_RxDv : in std_logic; phy0_RxErr : in std_logic; phy0_SMIDat_I : in std_logic := '1'; phy0_link : in std_logic := '0'; phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0'); phy1_RxDv : in std_logic; phy1_RxErr : in std_logic; phy1_SMIDat_I : in std_logic := '1'; phy1_link : in std_logic := '0'; phyMii0_RxClk : in std_logic; phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii0_RxDv : in std_logic; phyMii0_RxEr : in std_logic; phyMii0_TxClk : in std_logic; phyMii1_RxClk : in std_logic; phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0'); phyMii1_RxDv : in std_logic; phyMii1_RxEr : in std_logic; phyMii1_TxClk : in std_logic; phy_SMIDat_I : in std_logic := '1'; pio_pconfig : in std_logic_vector(3 downto 0); pio_portInLatch : in std_logic_vector(3 downto 0); pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0'); pkt_clk : in std_logic; rst : in std_logic; rstAp : in std_logic; rstPcp : in std_logic; smp_address : in std_logic; smp_byteenable : in std_logic_vector(3 downto 0); smp_read : in std_logic; smp_write : in std_logic; smp_writedata : in std_logic_vector(31 downto 0); spi_clk : in std_logic; spi_mosi : in std_logic; spi_sel_n : in std_logic; tcp_address : in std_logic_vector(1 downto 0); tcp_byteenable : in std_logic_vector(3 downto 0); tcp_chipselect : in std_logic; tcp_read : in std_logic; tcp_write : in std_logic; tcp_writedata : in std_logic_vector(31 downto 0); ap_asyncIrq : out std_logic := '0'; ap_asyncIrq_n : out std_logic := '1'; ap_irq : out std_logic := '0'; ap_irq_n : out std_logic := '1'; ap_readdata : out std_logic_vector(31 downto 0) := (others => '0'); ap_syncIrq : out std_logic := '0'; ap_syncIrq_n : out std_logic := '1'; ap_waitrequest : out std_logic; led_error : out std_logic := '0'; led_gpo : out std_logic_vector(7 downto 0) := (others => '0'); led_opt : out std_logic_vector(1 downto 0) := (others => '0'); led_phyAct : out std_logic_vector(1 downto 0) := (others => '0'); led_phyLink : out std_logic_vector(1 downto 0) := (others => '0'); led_status : out std_logic := '0'; m_address : out std_logic_vector(29 downto 0) := (others => '0'); m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0) := (others => '0'); m_read : out std_logic := '0'; m_write : out std_logic := '0'; m_writedata : out std_logic_vector(m_data_width_g-1 downto 0) := (others => '0'); mac_irq : out std_logic := '0'; mac_readdata : out std_logic_vector(15 downto 0) := (others => '0'); mac_waitrequest : out std_logic; mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0'); mbf_waitrequest : out std_logic; pap_ack : out std_logic := '0'; pap_ack_n : out std_logic := '1'; pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0); pap_data_T : out std_logic; pap_gpio_O : out std_logic_vector(1 downto 0); pap_gpio_T : out std_logic_vector(1 downto 0); pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); pcp_waitrequest : out std_logic; phy0_Rst_n : out std_logic := '1'; phy0_SMIClk : out std_logic := '0'; phy0_SMIDat_O : out std_logic; phy0_SMIDat_T : out std_logic; phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy0_TxEn : out std_logic := '0'; phy1_Rst_n : out std_logic := '1'; phy1_SMIClk : out std_logic := '0'; phy1_SMIDat_O : out std_logic; phy1_SMIDat_T : out std_logic; phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0'); phy1_TxEn : out std_logic := '0'; phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii0_TxEn : out std_logic := '0'; phyMii0_TxEr : out std_logic := '0'; phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0'); phyMii1_TxEn : out std_logic := '0'; phyMii1_TxEr : out std_logic := '0'; phy_Rst_n : out std_logic := '1'; phy_SMIClk : out std_logic := '0'; phy_SMIDat_O : out std_logic; phy_SMIDat_T : out std_logic; pio_operational : out std_logic := '0'; pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0'); pio_portio_O : out std_logic_vector(31 downto 0); pio_portio_T : out std_logic_vector(31 downto 0); smp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); smp_waitrequest : out std_logic; spi_miso : out std_logic := '0'; tcp_irq : out std_logic := '0'; tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0'); tcp_waitrequest : out std_logic; pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0'); pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0'); phy0_SMIDat : inout std_logic := '1'; phy1_SMIDat : inout std_logic := '1'; phy_SMIDat : inout std_logic := '1'; pio_portio : inout std_logic_vector(31 downto 0) := (others => '0') ); end component; component axi_lite_ipif generic( C_ARD_ADDR_RANGE_ARRAY : slv64_array_type := (X"0000_0000_7000_0000",X"0000_0000_7000_00FF",X"0000_0000_7000_0100",X"0000_0000_7000_01FF"); C_ARD_NUM_CE_ARRAY : integer_array_type := (4,12); C_DPHASE_TIMEOUT : integer range 0 to 512 := 8; C_FAMILY : string := "virtex6"; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) := X"000001FF"; C_USE_WSTRB : integer := 0 ); port ( IP2Bus_Data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); IP2Bus_Error : in std_logic; IP2Bus_RdAck : in std_logic; IP2Bus_WrAck : in std_logic; S_AXI_ACLK : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARESETN : in std_logic; S_AXI_ARVALID : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; Bus2IP_Addr : out std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); Bus2IP_BE : out std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); Bus2IP_CS : out std_logic_vector((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0); Bus2IP_Clk : out std_logic; Bus2IP_Data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); Bus2IP_RNW : out std_logic; Bus2IP_RdCE : out std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0); Bus2IP_Resetn : out std_logic; Bus2IP_WrCE : out std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0); S_AXI_ARREADY : out std_logic; S_AXI_AWREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic ); end component; component axi_master_burst generic( C_ADDR_PIPE_DEPTH : integer range 1 to 14 := 1; C_FAMILY : string := "virtex6"; C_LENGTH_WIDTH : integer range 12 to 20 := 12; C_MAX_BURST_LEN : integer range 16 to 256 := 16; C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32; C_M_AXI_DATA_WIDTH : integer range 32 to 256 := 32; C_NATIVE_DATA_WIDTH : integer range 32 to 128 := 32 ); port ( ip2bus_mst_addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0); ip2bus_mst_be : in std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0); ip2bus_mst_length : in std_logic_vector(C_LENGTH_WIDTH-1 downto 0); ip2bus_mst_lock : in std_logic; ip2bus_mst_reset : in std_logic; ip2bus_mst_type : in std_logic; ip2bus_mstrd_dst_dsc_n : in std_logic; ip2bus_mstrd_dst_rdy_n : in std_logic; ip2bus_mstrd_req : in std_logic; ip2bus_mstwr_d : in std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0); ip2bus_mstwr_eof_n : in std_logic; ip2bus_mstwr_rem : in std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0); ip2bus_mstwr_req : in std_logic; ip2bus_mstwr_sof_n : in std_logic; ip2bus_mstwr_src_dsc_n : in std_logic; ip2bus_mstwr_src_rdy_n : in std_logic; m_axi_aclk : in std_logic; m_axi_aresetn : in std_logic; m_axi_arready : in std_logic; m_axi_awready : in std_logic; m_axi_bresp : in std_logic_vector(1 downto 0); m_axi_bvalid : in std_logic; m_axi_rdata : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0); m_axi_rlast : in std_logic; m_axi_rresp : in std_logic_vector(1 downto 0); m_axi_rvalid : in std_logic; m_axi_wready : in std_logic; bus2ip_mst_cmd_timeout : out std_logic; bus2ip_mst_cmdack : out std_logic; bus2ip_mst_cmplt : out std_logic; bus2ip_mst_error : out std_logic; bus2ip_mst_rearbitrate : out std_logic; bus2ip_mstrd_d : out std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0); bus2ip_mstrd_eof_n : out std_logic; bus2ip_mstrd_rem : out std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0); bus2ip_mstrd_sof_n : out std_logic; bus2ip_mstrd_src_dsc_n : out std_logic; bus2ip_mstrd_src_rdy_n : out std_logic; bus2ip_mstwr_dst_dsc_n : out std_logic; bus2ip_mstwr_dst_rdy_n : out std_logic; m_axi_araddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0); m_axi_arburst : out std_logic_vector(1 downto 0); m_axi_arcache : out std_logic_vector(3 downto 0); m_axi_arlen : out std_logic_vector(7 downto 0); m_axi_arprot : out std_logic_vector(2 downto 0); m_axi_arsize : out std_logic_vector(2 downto 0); m_axi_arvalid : out std_logic; m_axi_awaddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0); m_axi_awburst : out std_logic_vector(1 downto 0); m_axi_awcache : out std_logic_vector(3 downto 0); m_axi_awlen : out std_logic_vector(7 downto 0); m_axi_awprot : out std_logic_vector(2 downto 0); m_axi_awsize : out std_logic_vector(2 downto 0); m_axi_awvalid : out std_logic; m_axi_bready : out std_logic; m_axi_rready : out std_logic; m_axi_wdata : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0); m_axi_wlast : out std_logic; m_axi_wstrb : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0); m_axi_wvalid : out std_logic; md_error : out std_logic ); end component; ---- Architecture declarations ----- constant C_FAMILY : string := "spartan6"; constant C_ADDR_PAD_ZERO : std_logic_vector(31 downto 0) := (others => '0'); -- openMAC REG PLB Slave constant C_MAC_REG_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG0_BASEADDR; constant C_MAC_REG_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG0_HIGHADDR; constant C_MAC_REG_MINSIZE : std_logic_vector(31 downto 0) := conv_std_logic_vector(get_max(conv_integer(C_S_AXI_MAC_REG_RNG0_HIGHADDR), conv_integer(C_S_AXI_MAC_REG_RNG1_HIGHADDR)), 32); -- openMAC CMP PLB Slave constant C_MAC_CMP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG1_BASEADDR; constant C_MAC_CMP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG1_HIGHADDR; -- openMAC PKT PLB Slave constant C_MAC_PKT_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_PKT_BASEADDR; constant C_MAC_PKT_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_PKT_HIGHADDR; constant C_MAC_PKT_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_MAC_PKT_HIGHADDR; -- SimpleIO Slave constant C_SMP_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_SMP_PCP_BASEADDR; constant C_SMP_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_SMP_PCP_HIGHADDR; constant C_SMP_PCP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_SMP_PCP_HIGHADDR; -- PDI PCP Slave constant C_PDI_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_PCP_BASEADDR; constant C_PDI_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_PCP_HIGHADDR; constant C_PDI_PCP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_PDI_PCP_HIGHADDR; -- AP PCP Slave constant C_PDI_AP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_AP_BASEADDR; constant C_PDI_AP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_AP_HIGHADDR; constant C_PDI_AP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_PDI_AP_HIGHADDR; -- POWERLINK IP-core constant C_MAC_PKT_EN : boolean := C_TX_INT_PKT or C_RX_INT_PKT; constant C_MAC_PKT_RX_EN : boolean := C_RX_INT_PKT; constant C_DMA_EN : boolean := not C_TX_INT_PKT or not C_RX_INT_PKT; constant C_PKT_BUF_EN : boolean := C_MAC_PKT_EN; constant C_M_BURSTCOUNT_WIDTH : integer := integer(ceil(log2(real(get_max(C_MAC_DMA_BURST_SIZE_RX,C_MAC_DMA_BURST_SIZE_TX)/4)))) + 1; --in dwords constant C_M_FIFO_SIZE_RX : integer := C_MAC_DMA_FIFO_SIZE_RX/4; --in dwords constant C_M_FIFO_SIZE_TX : integer := C_MAC_DMA_FIFO_SIZE_TX/4; --in dwords ---- Constants ----- constant VCC_CONSTANT : std_logic := '1'; constant GND_CONSTANT : std_logic := '0'; ---- Signal declarations used on the diagram ---- signal ap_chipselect : std_logic; signal ap_read : std_logic; signal ap_waitrequest : std_logic; signal ap_write : std_logic; signal bus2MAC_DMA_mstrd_eof_n : std_logic; signal bus2MAC_DMA_mstrd_sof_n : std_logic; signal bus2MAC_DMA_mstrd_src_dsc_n : std_logic; signal bus2MAC_DMA_mstrd_src_rdy_n : std_logic; signal bus2MAC_DMA_mstwr_dst_dsc_n : std_logic; signal bus2MAC_DMA_mstwr_dst_rdy_n : std_logic; signal bus2MAC_DMA_mst_cmdack : std_logic; signal bus2MAC_DMA_mst_cmd_timeout : std_logic; signal bus2MAC_DMA_mst_cmplt : std_logic; signal bus2MAC_DMA_mst_error : std_logic; signal bus2MAC_DMA_mst_rearbitrate : std_logic; signal Bus2MAC_PKT_Clk : std_logic; signal Bus2MAC_PKT_Reset : std_logic := '0'; signal Bus2MAC_PKT_Resetn : std_logic; signal Bus2MAC_PKT_RNW : std_logic; signal Bus2MAC_REG_Clk : std_logic; signal Bus2MAC_REG_Reset : std_logic := '0'; signal Bus2MAC_REG_Resetn : std_logic; signal Bus2MAC_REG_RNW : std_logic; signal Bus2MAC_REG_RNW_n : std_logic; signal Bus2PDI_AP_Clk : std_logic; signal Bus2PDI_AP_Reset : std_logic := '0'; signal Bus2PDI_AP_Resetn : std_logic; signal Bus2PDI_AP_RNW : std_logic; signal Bus2PDI_PCP_Clk : std_logic; signal Bus2PDI_PCP_Reset : std_logic := '0'; signal Bus2PDI_PCP_Resetn : std_logic; signal Bus2PDI_PCP_RNW : std_logic; signal Bus2SMP_PCP_Clk : std_logic; signal Bus2SMP_PCP_Reset : std_logic := '0'; signal Bus2SMP_PCP_Resetn : std_logic; signal Bus2SMP_PCP_RNW : std_logic; signal clk50 : std_logic; signal clkAp : std_logic; signal clkPcp : std_logic; signal GND : std_logic; signal IP2Bus_Error_s : std_logic; signal IP2Bus_RdAck_s : std_logic; signal IP2Bus_WrAck_s : std_logic; signal mac_chipselect : std_logic; signal MAC_CMP2Bus_Error : std_logic; signal MAC_CMP2Bus_RdAck : std_logic; signal MAC_CMP2Bus_WrAck : std_logic; signal MAC_DMA2bus_mstrd_dst_dsc_n : std_logic; signal MAC_DMA2bus_mstrd_dst_rdy_n : std_logic; signal MAC_DMA2bus_mstrd_req : std_logic; signal MAC_DMA2bus_mstwr_eof_n : std_logic; signal MAC_DMA2bus_mstwr_req : std_logic; signal MAC_DMA2bus_mstwr_sof_n : std_logic; signal MAC_DMA2bus_mstwr_src_dsc_n : std_logic; signal MAC_DMA2bus_mstwr_src_rdy_n : std_logic; signal MAC_DMA2bus_mst_lock : std_logic; signal MAC_DMA2bus_mst_reset : std_logic; signal MAC_DMA2bus_mst_type : std_logic; signal MAC_DMA_areset : std_logic; signal mac_irq_s : std_logic; signal MAC_PKT2Bus_Error : std_logic; signal MAC_PKT2Bus_RdAck : std_logic; signal MAC_PKT2Bus_WrAck : std_logic; signal mac_read : std_logic; signal MAC_REG2Bus_Error : std_logic; signal MAC_REG2Bus_RdAck : std_logic; signal MAC_REG2Bus_WrAck : std_logic; signal mac_waitrequest : std_logic; signal mac_write : std_logic; signal mbf_chipselect : std_logic; signal mbf_read : std_logic; signal mbf_waitrequest : std_logic; signal mbf_write : std_logic; signal m_clk : std_logic; signal m_read : std_logic; signal m_readdatavalid : std_logic; signal m_waitrequest : std_logic; signal m_write : std_logic; signal NET38418 : std_ulogic; signal NET38470 : std_ulogic; signal pcp_chipselect : std_logic; signal pcp_read : std_logic; signal pcp_waitrequest : std_logic; signal pcp_write : std_logic; signal PDI_AP2Bus_Error : std_logic; signal PDI_AP2Bus_RdAck : std_logic; signal PDI_AP2Bus_WrAck : std_logic; signal PDI_PCP2Bus_Error : std_logic; signal PDI_PCP2Bus_RdAck : std_logic; signal PDI_PCP2Bus_WrAck : std_logic; signal pkt_clk : std_logic; signal rst : std_logic := '0'; signal rstAp : std_logic := '0'; signal rstPcp : std_logic := '0'; signal smp_address : std_logic; signal smp_chipselect : std_logic; signal SMP_PCP2Bus_Error : std_logic; signal SMP_PCP2Bus_RdAck : std_logic; signal SMP_PCP2Bus_WrAck : std_logic; signal smp_read : std_logic; signal smp_waitrequest : std_logic; signal smp_write : std_logic; signal tcp_chipselect : std_logic; signal tcp_irq_s : std_logic; signal tcp_read : std_logic; signal tcp_waitrequest : std_logic; signal tcp_write : std_logic; signal VCC : std_logic; signal ap_address : std_logic_vector (12 downto 0); signal ap_byteenable : std_logic_vector (3 downto 0); signal ap_readdata : std_logic_vector (31 downto 0); signal ap_writedata : std_logic_vector (31 downto 0); signal bus2MAC_DMA_mstrd_d : std_logic_vector (C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0); signal bus2MAC_DMA_mstrd_rem : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0); signal Bus2MAC_PKT_Addr : std_logic_vector (C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0); signal Bus2MAC_PKT_BE : std_logic_vector ((C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0); signal Bus2MAC_PKT_CS : std_logic_vector (0 downto 0); signal Bus2MAC_PKT_Data : std_logic_vector (C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0); signal Bus2MAC_REG_Addr : std_logic_vector (C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0); signal Bus2MAC_REG_BE : std_logic_vector ((C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0); signal Bus2MAC_REG_CS : std_logic_vector (1 downto 0); signal Bus2MAC_REG_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); signal Bus2PDI_AP_Addr : std_logic_vector (C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0); signal Bus2PDI_AP_BE : std_logic_vector ((C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0); signal Bus2PDI_AP_CS : std_logic_vector (0 downto 0); signal Bus2PDI_AP_Data : std_logic_vector (C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0); signal Bus2PDI_PCP_Addr : std_logic_vector (C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0); signal Bus2PDI_PCP_BE : std_logic_vector ((C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0); signal Bus2PDI_PCP_CS : std_logic_vector (0 downto 0); signal Bus2PDI_PCP_Data : std_logic_vector (C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0); signal Bus2SMP_PCP_Addr : std_logic_vector (C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0); signal Bus2SMP_PCP_BE : std_logic_vector ((C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0); signal Bus2SMP_PCP_CS : std_logic_vector (0 downto 0); signal Bus2SMP_PCP_Data : std_logic_vector (C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0); signal IP2Bus_Data_s : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); signal mac_address : std_logic_vector (11 downto 0); signal mac_address_full : std_logic_vector (C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0); signal mac_byteenable : std_logic_vector (1 downto 0); signal MAC_CMP2Bus_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); signal MAC_DMA2Bus_MstWr_d : std_logic_vector (C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0); signal MAC_DMA2bus_mstwr_rem : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0); signal MAC_DMA2bus_mst_addr : std_logic_vector (C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0); signal MAC_DMA2bus_mst_be : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0); signal MAC_DMA2bus_mst_length : std_logic_vector (C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0); signal MAC_PKT2Bus_Data : std_logic_vector (C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0); signal mac_readdata : std_logic_vector (15 downto 0); signal MAC_REG2Bus_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0); signal mac_writedata : std_logic_vector (15 downto 0); signal mbf_address : std_logic_vector (C_MAC_PKT_SIZE_LOG2-3 downto 0); signal mbf_byteenable : std_logic_vector (3 downto 0); signal mbf_readdata : std_logic_vector (31 downto 0); signal mbf_writedata : std_logic_vector (31 downto 0); signal m_address : std_logic_vector (29 downto 0); signal m_burstcount : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0); signal m_burstcounter : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0); signal m_byteenable : std_logic_vector (3 downto 0); signal m_readdata : std_logic_vector (31 downto 0); signal m_writedata : std_logic_vector (31 downto 0); signal pcp_address : std_logic_vector (12 downto 0); signal pcp_byteenable : std_logic_vector (3 downto 0); signal pcp_readdata : std_logic_vector (31 downto 0); signal pcp_writedata : std_logic_vector (31 downto 0); signal PDI_AP2Bus_Data : std_logic_vector (C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0); signal PDI_PCP2Bus_Data : std_logic_vector (C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0); signal smp_byteenable : std_logic_vector (3 downto 0); signal SMP_PCP2Bus_Data : std_logic_vector (C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0); signal smp_readdata : std_logic_vector (31 downto 0); signal smp_writedata : std_logic_vector (31 downto 0); signal tcp_address : std_logic_vector (1 downto 0); signal tcp_byteenable : std_logic_vector (3 downto 0); signal tcp_readdata : std_logic_vector (31 downto 0); signal tcp_writedata : std_logic_vector (31 downto 0); begin ---- User Signal Assignments ---- -- connect mac reg with mac cmp or reg output signals with Bus2MAC_REG_CS select IP2Bus_Data_s <= MAC_CMP2Bus_Data when "01", MAC_REG2Bus_Data when others; --"10" and others are decoded to MAC_REG IP2Bus_WrAck_s <= MAC_REG2Bus_WrAck or MAC_CMP2Bus_WrAck; IP2Bus_RdAck_s <= MAC_REG2Bus_RdAck or MAC_CMP2Bus_RdAck; IP2Bus_Error_s <= MAC_REG2Bus_Error or MAC_CMP2Bus_Error; mac_address <= mac_address_full(mac_address'range); --mac_cmp assignments ---cmp_clk <= Bus2MAC_CMP_Clk; tcp_writedata <= Bus2MAC_REG_Data; tcp_read <= Bus2MAC_REG_RNW; tcp_write <= not Bus2MAC_REG_RNW; tcp_chipselect <= Bus2MAC_REG_CS(0); tcp_byteenable <= Bus2MAC_REG_BE; tcp_address <= Bus2MAC_REG_Addr(3 downto 2); MAC_CMP2Bus_Data <= tcp_readdata; MAC_CMP2Bus_RdAck <= tcp_chipselect and tcp_read and not tcp_waitrequest; MAC_CMP2Bus_WrAck <= tcp_chipselect and tcp_write and not tcp_waitrequest; MAC_CMP2Bus_Error <= '0'; --mac_pkt assignments pkt_clk <= Bus2MAC_PKT_Clk; Bus2MAC_PKT_Reset <= not Bus2MAC_PKT_Resetn; mbf_writedata <= Bus2MAC_PKT_Data; -- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) & -- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24); mbf_read <= Bus2MAC_PKT_RNW; mbf_write <= not Bus2MAC_PKT_RNW; mbf_chipselect <= Bus2MAC_PKT_CS(0); mbf_byteenable <= Bus2MAC_PKT_BE; mbf_address <= Bus2MAC_PKT_Addr(C_MAC_PKT_SIZE_LOG2-1 downto 2); MAC_PKT2Bus_Data <= mbf_readdata; MAC_PKT2Bus_RdAck <= mbf_chipselect and mbf_read and not mbf_waitrequest; MAC_PKT2Bus_WrAck <= mbf_chipselect and mbf_write and not mbf_waitrequest; MAC_PKT2Bus_Error <= '0'; --test_port --test_port(181 downto 179) <= mac_chipselect & mac_write & mac_read; --test_port(178) <= mac_waitrequest; --test_port(177 downto 176) <= mac_byteenable; -- --test_port(171 downto 160) <= mac_address; --test_port(159 downto 144) <= mac_writedata; --test_port(143 downto 128) <= mac_readdata; -- --test_port(104 downto 102) <= Bus2MAC_REG_CS & Bus2MAC_REG_RNW; --test_port(101 downto 100) <= IP2Bus_WrAck_s & IP2Bus_RdAck_s; --test_port(99 downto 96) <= Bus2MAC_REG_BE; -- --test_port(95 downto 64) <= Bus2MAC_REG_Addr; --test_port(63 downto 32) <= Bus2MAC_REG_Data; --test_port(31 downto 0) <= IP2Bus_Data_s; test_port(255 downto 251) <= m_read & m_write & m_waitrequest & m_readdatavalid & MAC_DMA2Bus_Mst_Type; test_port(244 downto 240) <= MAC_DMA2Bus_MstWr_Req & MAC_DMA2Bus_MstWr_sof_n & MAC_DMA2Bus_MstWr_eof_n & MAC_DMA2Bus_MstWr_src_rdy_n & Bus2MAC_DMA_MstWr_dst_rdy_n; test_port(234 downto 230) <= MAC_DMA2Bus_MstRd_Req & Bus2MAC_DMA_MstRd_sof_n & Bus2MAC_DMA_MstRd_eof_n & Bus2MAC_DMA_MstRd_src_rdy_n & MAC_DMA2Bus_MstRd_dst_rdy_n; test_port(142 downto 140) <= Bus2MAC_DMA_Mst_Cmplt & Bus2MAC_DMA_Mst_Error & Bus2MAC_DMA_Mst_Cmd_Timeout; test_port(MAC_DMA2Bus_Mst_Length'length+120-1 downto 120) <= MAC_DMA2Bus_Mst_Length; test_port(m_burstcount'length+110-1 downto 110) <= m_burstcount; test_port(m_burstcounter'length+96-1 downto 96) <= m_burstcounter; test_port(95 downto 64) <= "00" & m_address; test_port(63 downto 32) <= m_writedata; test_port(31 downto 0) <= m_readdata; ---- Component instantiations ---- MAC_REG_16to32 : openMAC_16to32conv generic map ( bus_address_width => C_S_AXI_MAC_REG_ADDR_WIDTH, gEndian => "little" ) port map( bus_ack_rd => MAC_REG2Bus_RdAck, bus_ack_wr => MAC_REG2Bus_WrAck, bus_address => Bus2MAC_REG_Addr( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ), bus_byteenable => Bus2MAC_REG_BE( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ), bus_read => Bus2MAC_REG_RNW, bus_readdata => MAC_REG2Bus_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), bus_select => Bus2MAC_REG_CS(1), bus_write => Bus2MAC_REG_RNW_n, bus_writedata => Bus2MAC_REG_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), clk => Bus2MAC_REG_Clk, rst => Bus2MAC_REG_Reset, s_address => mac_address_full( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ), s_byteenable => mac_byteenable, s_chipselect => mac_chipselect, s_read => mac_read, s_readdata => mac_readdata, s_waitrequest => mac_waitrequest, s_write => mac_write, s_writedata => mac_writedata ); MAC_REG_AXI_SINGLE_SLAVE : axi_lite_ipif generic map ( C_ARD_ADDR_RANGE_ARRAY => (C_MAC_REG_BASE,C_MAC_REG_HIGH,C_MAC_CMP_BASE,C_MAC_CMP_HIGH), C_ARD_NUM_CE_ARRAY => (1,1), C_DPHASE_TIMEOUT => C_S_AXI_MAC_REG_DPHASE_TIMEOUT, C_FAMILY => C_FAMILY, C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_REG_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_REG_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_MAC_REG_MINSIZE, C_USE_WSTRB => C_S_AXI_MAC_REG_USE_WSTRB ) port map( Bus2IP_Addr => Bus2MAC_REG_Addr( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ), Bus2IP_BE => Bus2MAC_REG_BE( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ), Bus2IP_CS => Bus2MAC_REG_CS( 1 downto 0 ), Bus2IP_Clk => Bus2MAC_REG_Clk, Bus2IP_Data => Bus2MAC_REG_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), Bus2IP_RNW => Bus2MAC_REG_RNW, Bus2IP_RdCE => open, Bus2IP_Resetn => Bus2MAC_REG_Resetn, Bus2IP_WrCE => open, IP2Bus_Data => IP2Bus_Data_s( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), IP2Bus_Error => IP2Bus_Error_s, IP2Bus_RdAck => IP2Bus_RdAck_s, IP2Bus_WrAck => IP2Bus_WrAck_s, S_AXI_ACLK => S_AXI_MAC_REG_ACLK, S_AXI_ARADDR => S_AXI_MAC_REG_ARADDR( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ), S_AXI_ARESETN => S_AXI_MAC_REG_ARESETN, S_AXI_ARREADY => S_AXI_MAC_REG_ARREADY, S_AXI_ARVALID => S_AXI_MAC_REG_ARVALID, S_AXI_AWADDR => S_AXI_MAC_REG_AWADDR( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ), S_AXI_AWREADY => S_AXI_MAC_REG_AWREADY, S_AXI_AWVALID => S_AXI_MAC_REG_AWVALID, S_AXI_BREADY => S_AXI_MAC_REG_BREADY, S_AXI_BRESP => S_AXI_MAC_REG_BRESP, S_AXI_BVALID => S_AXI_MAC_REG_BVALID, S_AXI_RDATA => S_AXI_MAC_REG_RDATA( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), S_AXI_RREADY => S_AXI_MAC_REG_RREADY, S_AXI_RRESP => S_AXI_MAC_REG_RRESP, S_AXI_RVALID => S_AXI_MAC_REG_RVALID, S_AXI_WDATA => S_AXI_MAC_REG_WDATA( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ), S_AXI_WREADY => S_AXI_MAC_REG_WREADY, S_AXI_WSTRB => S_AXI_MAC_REG_WSTRB( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ), S_AXI_WVALID => S_AXI_MAC_REG_WVALID ); THE_POWERLINK_IP_CORE : powerlink generic map ( Simulate => false, endian_g => "little", gNumSmi => C_NUM_SMI, genABuf1_g => C_PDI_GEN_ASYNC_BUF_0, genABuf2_g => C_PDI_GEN_ASYNC_BUF_1, genEvent_g => C_PDI_GEN_EVENT, genInternalAp_g => C_GEN_AXI_BUS_IF, genIoBuf_g => false, genLedGadget_g => C_PDI_GEN_LED, genOnePdiClkDomain_g => false, genPdi_g => C_GEN_PDI, genSimpleIO_g => C_GEN_SIMPLE_IO, genSmiIO => false, genSpiAp_g => C_GEN_SPI_IF, genTimeSync_g => C_PDI_GEN_TIME_SYNC, gen_dma_observer_g => C_OBSERVER_ENABLE, iAsyBuf1Size_g => C_PDI_ASYNC_BUF_0, iAsyBuf2Size_g => C_PDI_ASYNC_BUF_1, iBufSizeLOG2_g => C_MAC_PKT_SIZE_LOG2, iBufSize_g => C_MAC_PKT_SIZE, iPdiRev_g => 2, iRpdo0BufSize_g => C_RPDO_0_BUF_SIZE, iRpdo1BufSize_g => C_RPDO_1_BUF_SIZE, iRpdo2BufSize_g => C_RPDO_2_BUF_SIZE, iRpdos_g => C_NUM_RPDO, iTpdoBufSize_g => C_TPDO_BUF_SIZE, iTpdos_g => C_NUM_TPDO, m_burstcount_const_g => true, m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH, m_data_width_g => 32, m_rx_burst_size_g => C_MAC_DMA_BURST_SIZE_RX/4, m_rx_fifo_size_g => C_M_FIFO_SIZE_RX, m_tx_burst_size_g => C_MAC_DMA_BURST_SIZE_TX/4, m_tx_fifo_size_g => C_M_FIFO_SIZE_TX, papBigEnd_g => false, papDataWidth_g => C_PAP_DATA_WIDTH, papLowAct_g => C_PAP_LOW_ACT, pioValLen_g => C_PIO_VAL_LENGTH, spiBigEnd_g => false, spiCPHA_g => C_SPI_CPHA, spiCPOL_g => C_SPI_CPOL, use2ndCmpTimer_g => C_PDI_GEN_SECOND_TIMER, use2ndPhy_g => C_USE_2ND_PHY, useIntPacketBuf_g => C_MAC_PKT_EN, useRmii_g => C_USE_RMII, useRxIntPacketBuf_g => C_MAC_PKT_RX_EN ) port map( ap_address => ap_address, ap_asyncIrq => ap_asyncIrq, ap_asyncIrq_n => ap_asyncIrq_n, ap_byteenable => ap_byteenable, ap_chipselect => ap_chipselect, ap_irq => open, ap_irq_n => open, ap_read => ap_read, ap_readdata => ap_readdata, ap_syncIrq => ap_syncIrq, ap_syncIrq_n => ap_syncIrq_n, ap_waitrequest => ap_waitrequest, ap_write => ap_write, ap_writedata => ap_writedata, clk50 => clk50, clkAp => clkAp, clkEth => clk100, clkPcp => clkPcp, led_error => led_error, led_gpo => led_gpo, led_opt => led_opt, led_phyAct => led_phyAct, led_phyLink => led_phyLink, led_status => led_status, m_address => m_address, m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ), m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ), m_byteenable => m_byteenable( 3 downto 0 ), m_clk => m_clk, m_read => m_read, m_readdata => m_readdata( 31 downto 0 ), m_readdatavalid => m_readdatavalid, m_waitrequest => m_waitrequest, m_write => m_write, m_writedata => m_writedata( 31 downto 0 ), mac_address => mac_address, mac_byteenable => mac_byteenable, mac_chipselect => mac_chipselect, mac_irq => mac_irq_s, mac_read => mac_read, mac_readdata => mac_readdata, mac_waitrequest => mac_waitrequest, mac_write => mac_write, mac_writedata => mac_writedata, mbf_address => mbf_address( C_MAC_PKT_SIZE_LOG2-3 downto 0 ), mbf_byteenable => mbf_byteenable, mbf_chipselect => mbf_chipselect, mbf_read => mbf_read, mbf_readdata => mbf_readdata, mbf_waitrequest => mbf_waitrequest, mbf_write => mbf_write, mbf_writedata => mbf_writedata, pap_ack => pap_ack, pap_ack_n => pap_ack_n, pap_addr => pap_addr, pap_be => pap_be( C_PAP_DATA_WIDTH/8-1 downto 0 ), pap_be_n => pap_be_n( C_PAP_DATA_WIDTH/8-1 downto 0 ), pap_cs => pap_cs, pap_cs_n => pap_cs_n, pap_data => open, pap_data_I => pap_data_I( C_PAP_DATA_WIDTH-1 downto 0 ), pap_data_O => pap_data_O( C_PAP_DATA_WIDTH-1 downto 0 ), pap_data_T => pap_data_T, pap_gpio => open, pap_gpio_I => pap_gpio_I, pap_gpio_O => pap_gpio_O, pap_gpio_T => pap_gpio_T, pap_rd => pap_rd, pap_rd_n => pap_rd_n, pap_wr => pap_wr, pap_wr_n => pap_wr_n, pcp_address => pcp_address, pcp_byteenable => pcp_byteenable, pcp_chipselect => pcp_chipselect, pcp_read => pcp_read, pcp_readdata => pcp_readdata, pcp_waitrequest => pcp_waitrequest, pcp_write => pcp_write, pcp_writedata => pcp_writedata, phy0_Rst_n => phy0_Rst_n, phy0_RxDat => phy0_RxDat, phy0_RxDv => phy0_RxDv, phy0_RxErr => phy0_RxErr, phy0_SMIClk => phy0_SMIClk, phy0_SMIDat => open, phy0_SMIDat_I => phy0_SMIDat_I, phy0_SMIDat_O => phy0_SMIDat_O, phy0_SMIDat_T => phy0_SMIDat_T, phy0_TxDat => phy0_TxDat, phy0_TxEn => phy0_TxEn, phy0_link => phy0_link, phy1_Rst_n => phy1_Rst_n, phy1_RxDat => phy1_RxDat, phy1_RxDv => phy1_RxDv, phy1_RxErr => phy1_RxErr, phy1_SMIClk => phy1_SMIClk, phy1_SMIDat => open, phy1_SMIDat_I => phy1_SMIDat_I, phy1_SMIDat_O => phy1_SMIDat_O, phy1_SMIDat_T => phy1_SMIDat_T, phy1_TxDat => phy1_TxDat, phy1_TxEn => phy1_TxEn, phy1_link => phy1_link, phyMii0_RxClk => phyMii0_RxClk, phyMii0_RxDat => phyMii0_RxDat, phyMii0_RxDv => phyMii0_RxDv, phyMii0_RxEr => phyMii0_RxEr, phyMii0_TxClk => phyMii0_TxClk, phyMii0_TxDat => phyMii0_TxDat, phyMii0_TxEn => phyMii0_TxEn, phyMii0_TxEr => phyMii0_TxEr, phyMii1_RxClk => phyMii1_RxClk, phyMii1_RxDat => phyMii1_RxDat, phyMii1_RxDv => phyMii1_RxDv, phyMii1_RxEr => phyMii1_RxEr, phyMii1_TxClk => phyMii1_TxClk, phyMii1_TxDat => phyMii1_TxDat, phyMii1_TxEn => phyMii1_TxEn, phyMii1_TxEr => phyMii1_TxEr, phy_Rst_n => phy_Rst_n, phy_SMIClk => phy_SMIClk, phy_SMIDat => open, phy_SMIDat_I => phy_SMIDat_I, phy_SMIDat_O => phy_SMIDat_O, phy_SMIDat_T => phy_SMIDat_T, pio_operational => pio_operational, pio_pconfig => pio_pconfig, pio_portInLatch => pio_portInLatch, pio_portOutValid => pio_portOutValid, pio_portio => open, pio_portio_I => pio_portio_I, pio_portio_O => pio_portio_O, pio_portio_T => pio_portio_T, pkt_clk => pkt_clk, rst => rst, rstAp => rstAp, rstPcp => rstPcp, smp_address => smp_address, smp_byteenable => smp_byteenable, smp_read => smp_read, smp_readdata => smp_readdata, smp_waitrequest => smp_waitrequest, smp_write => smp_write, smp_writedata => smp_writedata, spi_clk => spi_clk, spi_miso => spi_miso, spi_mosi => spi_mosi, spi_sel_n => spi_sel_n, tcp_address => tcp_address, tcp_byteenable => tcp_byteenable, tcp_chipselect => tcp_chipselect, tcp_irq => tcp_irq_s, tcp_read => tcp_read, tcp_readdata => tcp_readdata, tcp_waitrequest => tcp_waitrequest, tcp_write => tcp_write, tcp_writedata => tcp_writedata ); MAC_DMA_areset <= not(M_AXI_MAC_DMA_aresetn); Bus2MAC_REG_RNW_n <= not(Bus2MAC_REG_RNW); clk50 <= Bus2MAC_REG_Clk; Bus2MAC_REG_Reset <= not(Bus2MAC_REG_Resetn); rstPcp <= Bus2SMP_PCP_Reset or Bus2PDI_PCP_Reset or Bus2MAC_PKT_Reset; rstAp <= Bus2PDI_AP_Reset; rst <= Bus2MAC_REG_Reset; ---- Power , ground assignment ---- GND <= GND_CONSTANT; VCC <= VCC_CONSTANT; MAC_REG2Bus_Error <= GND; ---- Terminal assignment ---- -- Output\buffer terminals mac_irq <= mac_irq_s; tcp_irq <= tcp_irq_s; ---- Generate statements ---- genMacDmaPlbBurst : if C_DMA_EN = TRUE generate begin MAC_DMA_AXI_BURST_MASTER : axi_master_burst generic map ( C_ADDR_PIPE_DEPTH => 1, C_FAMILY => C_FAMILY, C_LENGTH_WIDTH => C_M_AXI_MAC_DMA_LENGTH_WIDTH, C_MAX_BURST_LEN => C_M_AXI_MAC_DMA_MAX_BURST_LEN, C_M_AXI_ADDR_WIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH, C_M_AXI_DATA_WIDTH => C_M_AXI_MAC_DMA_DATA_WIDTH, C_NATIVE_DATA_WIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH ) port map( bus2ip_mst_cmd_timeout => bus2MAC_DMA_mst_cmd_timeout, bus2ip_mst_cmdack => bus2MAC_DMA_mst_cmdack, bus2ip_mst_cmplt => bus2MAC_DMA_mst_cmplt, bus2ip_mst_error => bus2MAC_DMA_mst_error, bus2ip_mst_rearbitrate => bus2MAC_DMA_mst_rearbitrate, bus2ip_mstrd_d => bus2MAC_DMA_mstrd_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ), bus2ip_mstrd_eof_n => bus2MAC_DMA_mstrd_eof_n, bus2ip_mstrd_rem => bus2MAC_DMA_mstrd_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ), bus2ip_mstrd_sof_n => bus2MAC_DMA_mstrd_sof_n, bus2ip_mstrd_src_dsc_n => bus2MAC_DMA_mstrd_src_dsc_n, bus2ip_mstrd_src_rdy_n => bus2MAC_DMA_mstrd_src_rdy_n, bus2ip_mstwr_dst_dsc_n => bus2MAC_DMA_mstwr_dst_dsc_n, bus2ip_mstwr_dst_rdy_n => bus2MAC_DMA_mstwr_dst_rdy_n, ip2bus_mst_addr => MAC_DMA2bus_mst_addr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ), ip2bus_mst_be => MAC_DMA2bus_mst_be( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ), ip2bus_mst_length => MAC_DMA2bus_mst_length( C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0 ), ip2bus_mst_lock => MAC_DMA2bus_mst_lock, ip2bus_mst_reset => MAC_DMA2bus_mst_reset, ip2bus_mst_type => MAC_DMA2bus_mst_type, ip2bus_mstrd_dst_dsc_n => MAC_DMA2bus_mstrd_dst_dsc_n, ip2bus_mstrd_dst_rdy_n => MAC_DMA2bus_mstrd_dst_rdy_n, ip2bus_mstrd_req => MAC_DMA2bus_mstrd_req, ip2bus_mstwr_d => MAC_DMA2bus_mstwr_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ), ip2bus_mstwr_eof_n => MAC_DMA2bus_mstwr_eof_n, ip2bus_mstwr_rem => MAC_DMA2bus_mstwr_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ), ip2bus_mstwr_req => MAC_DMA2bus_mstwr_req, ip2bus_mstwr_sof_n => MAC_DMA2bus_mstwr_sof_n, ip2bus_mstwr_src_dsc_n => MAC_DMA2bus_mstwr_src_dsc_n, ip2bus_mstwr_src_rdy_n => MAC_DMA2bus_mstwr_src_rdy_n, m_axi_aclk => M_AXI_MAC_DMA_aclk, m_axi_araddr => M_AXI_MAC_DMA_araddr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ), m_axi_arburst => M_AXI_MAC_DMA_arburst, m_axi_arcache => M_AXI_MAC_DMA_arcache, m_axi_aresetn => M_AXI_MAC_DMA_aresetn, m_axi_arlen => M_AXI_MAC_DMA_arlen, m_axi_arprot => M_AXI_MAC_DMA_arprot, m_axi_arready => M_AXI_MAC_DMA_arready, m_axi_arsize => M_AXI_MAC_DMA_arsize, m_axi_arvalid => M_AXI_MAC_DMA_arvalid, m_axi_awaddr => M_AXI_MAC_DMA_awaddr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ), m_axi_awburst => M_AXI_MAC_DMA_awburst, m_axi_awcache => M_AXI_MAC_DMA_awcache, m_axi_awlen => M_AXI_MAC_DMA_awlen, m_axi_awprot => M_AXI_MAC_DMA_awprot, m_axi_awready => M_AXI_MAC_DMA_awready, m_axi_awsize => M_AXI_MAC_DMA_awsize, m_axi_awvalid => M_AXI_MAC_DMA_awvalid, m_axi_bready => M_AXI_MAC_DMA_bready, m_axi_bresp => M_AXI_MAC_DMA_bresp, m_axi_bvalid => M_AXI_MAC_DMA_bvalid, m_axi_rdata => M_AXI_MAC_DMA_rdata( C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0 ), m_axi_rlast => M_AXI_MAC_DMA_rlast, m_axi_rready => M_AXI_MAC_DMA_rready, m_axi_rresp => M_AXI_MAC_DMA_rresp, m_axi_rvalid => M_AXI_MAC_DMA_rvalid, m_axi_wdata => M_AXI_MAC_DMA_wdata( C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0 ), m_axi_wlast => M_AXI_MAC_DMA_wlast, m_axi_wready => M_AXI_MAC_DMA_wready, m_axi_wstrb => M_AXI_MAC_DMA_wstrb( (C_M_AXI_MAC_DMA_DATA_WIDTH/8)-1 downto 0 ), m_axi_wvalid => M_AXI_MAC_DMA_wvalid, md_error => M_AXI_MAC_DMA_md_error ); end generate genMacDmaPlbBurst; genThePlbMaster : if C_DMA_EN = TRUE generate begin THE_IPIF_MASTER_HANDLER : ipif_master_handler generic map ( C_MAC_DMA_IPIF_AWIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH, C_MAC_DMA_IPIF_NATIVE_DWIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH, dma_highadr_g => m_address'high, gen_rx_fifo_g => not C_RX_INT_PKT, gen_tx_fifo_g => not C_TX_INT_PKT, m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH ) port map( Bus2MAC_DMA_MstRd_d => bus2MAC_DMA_mstrd_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ), Bus2MAC_DMA_MstRd_eof_n => bus2MAC_DMA_mstrd_eof_n, Bus2MAC_DMA_MstRd_rem => bus2MAC_DMA_mstrd_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ), Bus2MAC_DMA_MstRd_sof_n => bus2MAC_DMA_mstrd_sof_n, Bus2MAC_DMA_MstRd_src_dsc_n => bus2MAC_DMA_mstrd_src_dsc_n, Bus2MAC_DMA_MstRd_src_rdy_n => bus2MAC_DMA_mstrd_src_rdy_n, Bus2MAC_DMA_MstWr_dst_dsc_n => bus2MAC_DMA_mstwr_dst_dsc_n, Bus2MAC_DMA_MstWr_dst_rdy_n => bus2MAC_DMA_mstwr_dst_rdy_n, Bus2MAC_DMA_Mst_CmdAck => bus2MAC_DMA_mst_cmdack, Bus2MAC_DMA_Mst_Cmd_Timeout => bus2MAC_DMA_mst_cmd_timeout, Bus2MAC_DMA_Mst_Cmplt => bus2MAC_DMA_mst_cmplt, Bus2MAC_DMA_Mst_Error => bus2MAC_DMA_mst_error, Bus2MAC_DMA_Mst_Rearbitrate => bus2MAC_DMA_mst_rearbitrate, MAC_DMA2Bus_MstRd_Req => MAC_DMA2bus_mstrd_req, MAC_DMA2Bus_MstRd_dst_dsc_n => MAC_DMA2bus_mstrd_dst_dsc_n, MAC_DMA2Bus_MstRd_dst_rdy_n => MAC_DMA2bus_mstrd_dst_rdy_n, MAC_DMA2Bus_MstWr_Req => MAC_DMA2bus_mstwr_req, MAC_DMA2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ), MAC_DMA2Bus_MstWr_eof_n => MAC_DMA2bus_mstwr_eof_n, MAC_DMA2Bus_MstWr_rem => MAC_DMA2bus_mstwr_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ), MAC_DMA2Bus_MstWr_sof_n => MAC_DMA2bus_mstwr_sof_n, MAC_DMA2Bus_MstWr_src_dsc_n => MAC_DMA2bus_mstwr_src_dsc_n, MAC_DMA2Bus_MstWr_src_rdy_n => MAC_DMA2bus_mstwr_src_rdy_n, MAC_DMA2Bus_Mst_Addr => MAC_DMA2bus_mst_addr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ), MAC_DMA2Bus_Mst_BE => MAC_DMA2bus_mst_be( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ), MAC_DMA2Bus_Mst_Length => MAC_DMA2bus_mst_length( C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0 ), MAC_DMA2Bus_Mst_Lock => MAC_DMA2bus_mst_lock, MAC_DMA2Bus_Mst_Reset => MAC_DMA2bus_mst_reset, MAC_DMA2Bus_Mst_Type => MAC_DMA2bus_mst_type, MAC_DMA_CLK => M_AXI_MAC_DMA_aclk, MAC_DMA_Rst => MAC_DMA_areset, m_address => m_address( 29 downto 0 ), m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ), m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ), m_byteenable => m_byteenable, m_clk => m_clk, m_read => m_read, m_readdata => m_readdata, m_readdatavalid => m_readdatavalid, m_waitrequest => m_waitrequest, m_write => m_write, m_writedata => m_writedata ); end generate genThePlbMaster; genMacPktPLbSingleSlave : if C_PKT_BUF_EN generate begin MAC_PKT_AXI_SINGLE_SLAVE : axi_lite_ipif generic map ( C_ARD_ADDR_RANGE_ARRAY => (C_MAC_PKT_BASE,C_MAC_PKT_HIGH), C_ARD_NUM_CE_ARRAY => (0=>1), C_DPHASE_TIMEOUT => C_S_AXI_MAC_PKT_DPHASE_TIMEOUT, C_FAMILY => C_FAMILY, C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_PKT_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_PKT_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_MAC_PKT_MINSIZE, C_USE_WSTRB => C_S_AXI_MAC_PKT_USE_WSTRB ) port map( Bus2IP_Addr => Bus2MAC_PKT_Addr( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ), Bus2IP_BE => Bus2MAC_PKT_BE( (C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0 ), Bus2IP_CS => Bus2MAC_PKT_CS( 0 downto 0 ), Bus2IP_Clk => Bus2MAC_PKT_Clk, Bus2IP_Data => Bus2MAC_PKT_Data( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ), Bus2IP_RNW => Bus2MAC_PKT_RNW, Bus2IP_RdCE => open, Bus2IP_Resetn => Bus2MAC_PKT_Resetn, Bus2IP_WrCE => open, IP2Bus_Data => MAC_PKT2Bus_Data( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ), IP2Bus_Error => MAC_PKT2Bus_Error, IP2Bus_RdAck => MAC_PKT2Bus_RdAck, IP2Bus_WrAck => MAC_PKT2Bus_WrAck, S_AXI_ACLK => S_AXI_MAC_PKT_ACLK, S_AXI_ARADDR => S_AXI_MAC_PKT_ARADDR( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ), S_AXI_ARESETN => S_AXI_MAC_PKT_ARESETN, S_AXI_ARREADY => S_AXI_MAC_PKT_ARREADY, S_AXI_ARVALID => S_AXI_MAC_PKT_ARVALID, S_AXI_AWADDR => S_AXI_MAC_PKT_AWADDR( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ), S_AXI_AWREADY => S_AXI_MAC_PKT_AWREADY, S_AXI_AWVALID => S_AXI_MAC_PKT_AWVALID, S_AXI_BREADY => S_AXI_MAC_PKT_BREADY, S_AXI_BRESP => S_AXI_MAC_PKT_BRESP, S_AXI_BVALID => S_AXI_MAC_PKT_BVALID, S_AXI_RDATA => S_AXI_MAC_PKT_RDATA( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ), S_AXI_RREADY => S_AXI_MAC_PKT_RREADY, S_AXI_RRESP => S_AXI_MAC_PKT_RRESP, S_AXI_RVALID => S_AXI_MAC_PKT_RVALID, S_AXI_WDATA => S_AXI_MAC_PKT_WDATA( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ), S_AXI_WREADY => S_AXI_MAC_PKT_WREADY, S_AXI_WSTRB => S_AXI_MAC_PKT_WSTRB( (C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0 ), S_AXI_WVALID => S_AXI_MAC_PKT_WVALID ); end generate genMacPktPLbSingleSlave; genPdiPcp : if (C_GEN_PDI) generate begin PDI_PCP_AXI_SINGLE_SLAVE : axi_lite_ipif generic map ( C_ARD_ADDR_RANGE_ARRAY => (C_PDI_PCP_BASE,C_PDI_PCP_HIGH), C_ARD_NUM_CE_ARRAY => (0=>1), C_DPHASE_TIMEOUT => C_S_AXI_PDI_PCP_DPHASE_TIMEOUT, C_FAMILY => C_FAMILY, C_S_AXI_ADDR_WIDTH => C_S_AXI_PDI_PCP_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_PDI_PCP_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_PDI_PCP_MINSIZE, C_USE_WSTRB => C_S_AXI_PDI_PCP_USE_WSTRB ) port map( Bus2IP_Addr => Bus2PDI_PCP_Addr( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ), Bus2IP_BE => Bus2PDI_PCP_BE( (C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0 ), Bus2IP_CS => Bus2PDI_PCP_CS( 0 downto 0 ), Bus2IP_Clk => Bus2PDI_PCP_Clk, Bus2IP_Data => Bus2PDI_PCP_Data( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ), Bus2IP_RNW => Bus2PDI_PCP_RNW, Bus2IP_RdCE => open, Bus2IP_Resetn => Bus2PDI_PCP_Resetn, Bus2IP_WrCE => open, IP2Bus_Data => PDI_PCP2Bus_Data( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ), IP2Bus_Error => PDI_PCP2Bus_Error, IP2Bus_RdAck => PDI_PCP2Bus_RdAck, IP2Bus_WrAck => PDI_PCP2Bus_WrAck, S_AXI_ACLK => S_AXI_PDI_PCP_ACLK, S_AXI_ARADDR => S_AXI_PDI_PCP_ARADDR( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ), S_AXI_ARESETN => S_AXI_PDI_PCP_ARESETN, S_AXI_ARREADY => S_AXI_PDI_PCP_ARREADY, S_AXI_ARVALID => S_AXI_PDI_PCP_ARVALID, S_AXI_AWADDR => S_AXI_PDI_PCP_AWADDR( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ), S_AXI_AWREADY => S_AXI_PDI_PCP_AWREADY, S_AXI_AWVALID => S_AXI_PDI_PCP_AWVALID, S_AXI_BREADY => S_AXI_PDI_PCP_BREADY, S_AXI_BRESP => S_AXI_PDI_PCP_BRESP, S_AXI_BVALID => S_AXI_PDI_PCP_BVALID, S_AXI_RDATA => S_AXI_PDI_PCP_RDATA( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ), S_AXI_RREADY => S_AXI_PDI_PCP_RREADY, S_AXI_RRESP => S_AXI_PDI_PCP_RRESP, S_AXI_RVALID => S_AXI_PDI_PCP_RVALID, S_AXI_WDATA => S_AXI_PDI_PCP_WDATA( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ), S_AXI_WREADY => S_AXI_PDI_PCP_WREADY, S_AXI_WSTRB => S_AXI_PDI_PCP_WSTRB( (C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0 ), S_AXI_WVALID => S_AXI_PDI_PCP_WVALID ); end generate genPdiPcp; genPcpPdiLink : if C_GEN_PDI generate begin --pdi_pcp assignments clkPcp <= Bus2PDI_PCP_Clk; Bus2PDI_PCP_Reset <= not Bus2PDI_PCP_Resetn; pcp_writedata <= Bus2PDI_PCP_Data; -- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) & -- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24); pcp_read <= Bus2PDI_PCP_RNW; pcp_write <= not Bus2PDI_PCP_RNW; pcp_chipselect <= Bus2PDI_PCP_CS(0); pcp_byteenable <= Bus2PDI_PCP_BE; pcp_address <= Bus2PDI_PCP_Addr(14 downto 2); PDI_PCP2Bus_Data <= pcp_readdata; PDI_PCP2Bus_RdAck <= pcp_chipselect and pcp_read and not pcp_waitrequest; PDI_PCP2Bus_WrAck <= pcp_chipselect and pcp_write and not pcp_waitrequest; PDI_PCP2Bus_Error <= '0'; end generate genPcpPdiLink; genPdiAp : if (C_GEN_AXI_BUS_IF) generate begin PDI_AP_AXI_SINGLE_SLAVE : axi_lite_ipif generic map ( C_ARD_ADDR_RANGE_ARRAY => (C_PDI_AP_BASE,C_PDI_AP_HIGH), C_ARD_NUM_CE_ARRAY => (0=>1), C_DPHASE_TIMEOUT => C_S_AXI_PDI_AP_DPHASE_TIMEOUT, C_FAMILY => C_FAMILY, C_S_AXI_ADDR_WIDTH => C_S_AXI_PDI_AP_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_PDI_AP_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_PDI_AP_MINSIZE, C_USE_WSTRB => C_S_AXI_PDI_AP_USE_WSTRB ) port map( Bus2IP_Addr => Bus2PDI_AP_Addr( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ), Bus2IP_BE => Bus2PDI_AP_BE( (C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0 ), Bus2IP_CS => Bus2PDI_AP_CS( 0 downto 0 ), Bus2IP_Clk => Bus2PDI_AP_Clk, Bus2IP_Data => Bus2PDI_AP_Data( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ), Bus2IP_RNW => Bus2PDI_AP_RNW, Bus2IP_RdCE => open, Bus2IP_Resetn => Bus2PDI_AP_Resetn, Bus2IP_WrCE => open, IP2Bus_Data => PDI_AP2Bus_Data( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ), IP2Bus_Error => PDI_AP2Bus_Error, IP2Bus_RdAck => PDI_AP2Bus_RdAck, IP2Bus_WrAck => PDI_AP2Bus_WrAck, S_AXI_ACLK => S_AXI_PDI_AP_ACLK, S_AXI_ARADDR => S_AXI_PDI_AP_ARADDR( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ), S_AXI_ARESETN => S_AXI_PDI_AP_ARESETN, S_AXI_ARREADY => S_AXI_PDI_AP_ARREADY, S_AXI_ARVALID => S_AXI_PDI_AP_ARVALID, S_AXI_AWADDR => S_AXI_PDI_AP_AWADDR( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ), S_AXI_AWREADY => S_AXI_PDI_AP_AWREADY, S_AXI_AWVALID => S_AXI_PDI_AP_AWVALID, S_AXI_BREADY => S_AXI_PDI_AP_BREADY, S_AXI_BRESP => S_AXI_PDI_AP_BRESP, S_AXI_BVALID => S_AXI_PDI_AP_BVALID, S_AXI_RDATA => S_AXI_PDI_AP_RDATA( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ), S_AXI_RREADY => S_AXI_PDI_AP_RREADY, S_AXI_RRESP => S_AXI_PDI_AP_RRESP, S_AXI_RVALID => S_AXI_PDI_AP_RVALID, S_AXI_WDATA => S_AXI_PDI_AP_WDATA( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ), S_AXI_WREADY => S_AXI_PDI_AP_WREADY, S_AXI_WSTRB => S_AXI_PDI_AP_WSTRB( (C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0 ), S_AXI_WVALID => S_AXI_PDI_AP_WVALID ); end generate genPdiAp; genApPdiLink : if C_GEN_PDI generate begin --ap_pcp assignments clkAp <= Bus2PDI_AP_Clk; Bus2PDI_AP_Reset <= not Bus2PDI_AP_Resetn; ap_writedata <= Bus2PDI_AP_Data; -- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) & -- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24); ap_read <= Bus2PDI_AP_RNW; ap_write <= not Bus2PDI_AP_RNW; ap_chipselect <= Bus2PDI_AP_CS(0); ap_byteenable <= Bus2PDI_AP_BE; ap_address <= Bus2PDI_AP_Addr(14 downto 2); PDI_AP2Bus_Data <= ap_readdata; PDI_AP2Bus_RdAck <= ap_chipselect and ap_read and not ap_waitrequest; PDI_AP2Bus_WrAck <= ap_chipselect and ap_write and not ap_waitrequest; PDI_AP2Bus_Error <= '0'; end generate genApPdiLink; genSmpIo : if (C_GEN_SIMPLE_IO) generate begin SMP_IO_AXI_SINGLE_SLAVE : axi_lite_ipif generic map ( C_ARD_ADDR_RANGE_ARRAY => (C_SMP_PCP_BASE,C_SMP_PCP_HIGH), C_ARD_NUM_CE_ARRAY => (0=>1), C_DPHASE_TIMEOUT => C_S_AXI_SMP_PCP_DPHASE_TIMEOUT, C_FAMILY => C_FAMILY, C_S_AXI_ADDR_WIDTH => C_S_AXI_SMP_PCP_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_SMP_PCP_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_SMP_PCP_MINSIZE, C_USE_WSTRB => C_S_AXI_SMP_PCP_USE_WSTRB ) port map( Bus2IP_Addr => Bus2SMP_PCP_Addr( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ), Bus2IP_BE => Bus2SMP_PCP_BE( (C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0 ), Bus2IP_CS => Bus2SMP_PCP_CS( 0 downto 0 ), Bus2IP_Clk => Bus2SMP_PCP_Clk, Bus2IP_Data => Bus2SMP_PCP_Data( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ), Bus2IP_RNW => Bus2SMP_PCP_RNW, Bus2IP_RdCE => open, Bus2IP_Resetn => Bus2SMP_PCP_Resetn, Bus2IP_WrCE => open, IP2Bus_Data => SMP_PCP2Bus_Data( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ), IP2Bus_Error => SMP_PCP2Bus_Error, IP2Bus_RdAck => SMP_PCP2Bus_RdAck, IP2Bus_WrAck => SMP_PCP2Bus_WrAck, S_AXI_ACLK => S_AXI_SMP_PCP_ACLK, S_AXI_ARADDR => S_AXI_SMP_PCP_ARADDR( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ), S_AXI_ARESETN => S_AXI_SMP_PCP_ARESETN, S_AXI_ARREADY => S_AXI_SMP_PCP_ARREADY, S_AXI_ARVALID => S_AXI_SMP_PCP_ARVALID, S_AXI_AWADDR => S_AXI_SMP_PCP_AWADDR( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ), S_AXI_AWREADY => S_AXI_SMP_PCP_AWREADY, S_AXI_AWVALID => S_AXI_SMP_PCP_AWVALID, S_AXI_BREADY => S_AXI_SMP_PCP_BREADY, S_AXI_BRESP => S_AXI_SMP_PCP_BRESP, S_AXI_BVALID => S_AXI_SMP_PCP_BVALID, S_AXI_RDATA => S_AXI_SMP_PCP_RDATA( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ), S_AXI_RREADY => S_AXI_SMP_PCP_RREADY, S_AXI_RRESP => S_AXI_SMP_PCP_RRESP, S_AXI_RVALID => S_AXI_SMP_PCP_RVALID, S_AXI_WDATA => S_AXI_SMP_PCP_WDATA( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ), S_AXI_WREADY => S_AXI_SMP_PCP_WREADY, S_AXI_WSTRB => S_AXI_SMP_PCP_WSTRB( (C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0 ), S_AXI_WVALID => S_AXI_SMP_PCP_WVALID ); end generate genSmpIo; genSimpleIoSignals : if C_GEN_SIMPLE_IO generate begin --SMP_PCP assignments clkPcp <= Bus2SMP_PCP_Clk; Bus2SMP_PCP_Reset <= not Bus2SMP_PCP_Resetn; smp_writedata <= Bus2SMP_PCP_Data; smp_read <= Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0); smp_write <= not Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0); smp_chipselect <= Bus2SMP_PCP_CS(0); smp_byteenable <= Bus2SMP_PCP_BE; smp_address <= Bus2SMP_PCP_Addr(2); SMP_PCP2Bus_Data <= smp_readdata; SMP_PCP2Bus_RdAck <= smp_chipselect and smp_read and not smp_waitrequest; SMP_PCP2Bus_WrAck <= smp_chipselect and smp_write and not smp_waitrequest; SMP_PCP2Bus_Error <= '0'; end generate genSimpleIoSignals; oddr2_0 : if not C_INSTANCE_ODDR2 generate begin phy0_clk <= clk50; phy1_clk <= clk50; end generate oddr2_0; oddr2_1 : if C_INSTANCE_ODDR2 generate begin U10 : ODDR2 port map( C0 => clk50, C1 => NET38418, CE => VCC, D0 => VCC, D1 => GND, Q => phy0_clk, R => GND, S => GND ); U11 : ODDR2 port map( C0 => clk50, C1 => NET38470, CE => VCC, D0 => VCC, D1 => GND, Q => phy1_clk, R => GND, S => GND ); NET38470 <= not(clk50); NET38418 <= not(clk50); end generate oddr2_1; end struct;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mux1_tb is end mux1_tb; architecture TB of mux1_tb is component mux1 port( in0 : in std_logic; in1 : in std_logic; sel : in std_logic; output : out std_logic); end component; signal in0 : std_logic; signal in1 : std_logic; signal sel : std_logic; signal output : std_logic; signal sim_done : std_logic := '0'; begin -- TB UUT: entity work.mux1 port map(in0 => in0, in1 => in1, sel => sel, output => output); process variable temp : std_logic_vector(2 downto 0); begin for i in 0 to 7 loop temp := std_logic_vector(to_unsigned(i, 3)); in1 <= temp(2); in0 <= temp(1); sel <= temp(0); wait for 10 ns; end loop; -- i report "SIMULATION FINISHED!"; sim_done <= '1'; wait; end process; end TB;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.usb_pkg.all; use work.io_bus_pkg.all; library unisim; use unisim.vcomponents.all; entity usb_host_io is generic ( g_simulation : boolean := false ); port ( ulpi_clock : in std_logic; ulpi_reset : in std_logic; -- ULPI Interface ULPI_DATA : inout std_logic_vector(7 downto 0); ULPI_DIR : in std_logic; ULPI_NXT : in std_logic; ULPI_STP : out std_logic; -- LED interface usb_busy : out std_logic; -- register interface bus sys_clock : in std_logic; sys_reset : in std_logic; sys_io_req : in t_io_req; sys_io_resp : out t_io_resp ); end usb_host_io; architecture wrap of usb_host_io is signal descr_addr : std_logic_vector(8 downto 0); signal descr_rdata : std_logic_vector(31 downto 0); signal descr_wdata : std_logic_vector(31 downto 0); signal descr_en : std_logic; signal descr_we : std_logic; signal buf_addr : std_logic_vector(10 downto 0); signal buf_rdata : std_logic_vector(7 downto 0); signal buf_wdata : std_logic_vector(7 downto 0); signal buf_en : std_logic; signal buf_we : std_logic; signal tx_busy : std_logic; signal tx_ack : std_logic; signal send_token : std_logic; signal send_handsh : std_logic; signal tx_pid : std_logic_vector(3 downto 0); signal tx_token : std_logic_vector(10 downto 0); signal send_data : std_logic; signal no_data : std_logic; signal user_data : std_logic_vector(7 downto 0); signal user_last : std_logic; signal user_next : std_logic; signal rx_pid : std_logic_vector(3 downto 0) := X"0"; signal rx_token : std_logic_vector(10 downto 0) := (others => '0'); signal valid_token : std_logic := '0'; signal valid_handsh : std_logic := '0'; signal valid_packet : std_logic := '0'; signal data_valid : std_logic := '0'; signal data_start : std_logic := '0'; signal data_out : std_logic_vector(7 downto 0) := X"12"; signal rx_error : std_logic := '0'; signal tx_data : std_logic_vector(7 downto 0) := X"00"; signal tx_last : std_logic := '0'; signal tx_valid : std_logic := '0'; signal tx_start : std_logic := '0'; signal tx_next : std_logic := '0'; signal rx_data : std_logic_vector(7 downto 0); signal status : std_logic_vector(7 downto 0); signal rx_last : std_logic; signal rx_valid : std_logic; signal rx_store : std_logic; signal rx_register : std_logic; signal reg_read : std_logic := '0'; signal reg_write : std_logic; signal reg_ack : std_logic; signal reg_addr : std_logic_vector(5 downto 0); signal reg_wdata : std_logic_vector(7 downto 0); -- signal reset_pkt : std_logic; -- signal reset_valid : std_logic; -- signal reset_last : std_logic; -- signal reset_data : std_logic_vector(7 downto 0); signal send_reset_data : std_logic; signal reset_last : std_logic; signal reset_data : std_logic_vector(7 downto 0); signal reset_done : std_logic; signal sof_enable : std_logic; signal scan_enable : std_logic; signal speed : std_logic_vector(1 downto 0); signal abort : std_logic; signal sys_addr_i : std_logic_vector(sys_io_req.address'range); signal sys_buf_en : std_logic; signal sys_descr_en : std_logic; signal sys_sel_d : std_logic_vector(2 downto 0); signal sys_buf_rdata : std_logic_vector(7 downto 0); signal sys_descr_rdata : std_logic_vector(7 downto 0); signal sys_cmd_read : std_logic; signal sys_cmd_write : std_logic; signal sys_cmd_rdata : std_logic_vector(7 downto 0); signal sys_cmd_full : std_logic; signal sys_cmd_count : std_logic_vector(2 downto 0); signal sys_resp_get : std_logic; signal sys_resp_data : std_logic_vector(8 downto 0); signal sys_resp_empty : std_logic; signal cmd_get : std_logic; signal cmd_empty : std_logic; signal cmd_data : std_logic_vector(7 downto 0); signal resp_put : std_logic; signal resp_full : std_logic; signal resp_data : std_logic_vector(8 downto 0); begin i_host: entity work.ulpi_host port map ( clock => ulpi_clock, reset => ulpi_reset, -- Descriptor RAM interface descr_addr => descr_addr, descr_rdata => descr_rdata, descr_wdata => descr_wdata, descr_en => descr_en, descr_we => descr_we, -- Buffer RAM interface buf_addr => buf_addr, buf_rdata => buf_rdata, buf_wdata => buf_wdata, buf_en => buf_en, buf_we => buf_we, -- Transmit Path Interface tx_busy => tx_busy, tx_ack => tx_ack, -- Interface to send tokens and handshakes send_token => send_token, send_handsh => send_handsh, tx_pid => tx_pid, tx_token => tx_token, -- Interface to send data packets send_data => send_data, no_data => no_data, user_data => user_data, user_last => user_last, user_next => user_next, -- Interface to bus reset unit reset_done => reset_done, sof_enable => sof_enable, scan_enable => scan_enable, speed => speed, abort => abort, -- Receive Path Interface rx_pid => rx_pid, rx_token => rx_token, valid_token => valid_token, valid_handsh => valid_handsh, valid_packet => valid_packet, data_valid => data_valid, data_start => data_start, data_out => data_out, rx_error => rx_error ); i_descr_ram: RAMB16_S9_S36 port map ( CLKA => sys_clock, SSRA => sys_reset, ENA => sys_descr_en, WEA => sys_io_req.write, ADDRA => sys_addr_i(10 downto 0), DIA => sys_io_req.data, DIPA => "0", DOA => sys_descr_rdata, CLKB => ulpi_clock, SSRB => ulpi_reset, ENB => descr_en, WEB => descr_we, ADDRB => descr_addr, DIB => descr_wdata, DIPB => X"0", DOB => descr_rdata ); i_buf_ram: RAMB16_S9_S9 port map ( CLKA => sys_clock, SSRA => sys_reset, ENA => sys_buf_en, WEA => sys_io_req.write, ADDRA => sys_addr_i(10 downto 0), DIA => sys_io_req.data, DIPA => "0", DOA => sys_buf_rdata, CLKB => ulpi_clock, SSRB => ulpi_reset, ENB => buf_en, WEB => buf_we, ADDRB => buf_addr(10 downto 0), DIB => buf_wdata, DIPB => "0", DOB => buf_rdata ); i_tx: entity work.ulpi_tx port map ( clock => ulpi_clock, reset => ulpi_reset, -- Bus Interface tx_start => tx_start, tx_last => tx_last, tx_valid => tx_valid, tx_next => tx_next, tx_data => tx_data, -- Status speed => speed, status => status, busy => tx_busy, tx_ack => tx_ack, -- Interface to send tokens send_token => send_token, send_handsh => send_handsh, pid => tx_pid, token => tx_token, -- Interface to send data packets send_data => send_data, user_data => user_data, user_last => user_last, user_next => user_next, -- Interface to read/write registers and reset packets send_reset_data => send_reset_data, reset_data => reset_data(0), reset_last => reset_last ); i_rx: entity work.ulpi_rx generic map ( g_allow_token => false ) port map ( clock => ulpi_clock, reset => ulpi_reset, rx_data => rx_data, rx_last => rx_last, rx_valid => rx_valid, rx_store => rx_store, pid => rx_pid, token => rx_token, valid_token => valid_token, valid_handsh => valid_handsh, valid_packet => valid_packet, data_out => data_out, data_valid => data_valid, data_start => data_start, error => rx_error ); i_bus: entity work.ulpi_bus port map ( clock => ulpi_clock, reset => ulpi_reset, ULPI_DATA => ULPI_DATA, ULPI_DIR => ULPI_DIR, ULPI_NXT => ULPI_NXT, ULPI_STP => ULPI_STP, status => status, -- register interface reg_read => reg_read, reg_write => reg_write, reg_address => reg_addr, reg_wdata => reg_wdata, reg_ack => reg_ack, -- stream interface tx_data => tx_data, tx_last => tx_last, tx_valid => tx_valid, tx_start => tx_start, tx_next => tx_next, rx_data => rx_data, rx_last => rx_last, rx_register => rx_register, rx_store => rx_store, rx_valid => rx_valid ); i_reset: entity work.bus_reset generic map ( g_simulation => g_simulation ) port map ( clock => ulpi_clock, reset => ulpi_reset, reset_done => reset_done, sof_enable => sof_enable, scan_enable => scan_enable, speed => speed, abort => abort, -- Command / response interface cmd_get => cmd_get, cmd_empty => cmd_empty, cmd_data => cmd_data, resp_put => resp_put, resp_full => resp_full, resp_data => resp_data, -- status status => status, usb_busy => usb_busy, -- register interface reg_read => reg_read, reg_write => reg_write, reg_rdata => rx_data, reg_wdata => reg_wdata, reg_address => reg_addr, reg_ack => reg_ack, -- interface to packet transmitter send_packet => send_reset_data, user_data => reset_data, user_last => reset_last, user_valid => open ); i_cmd_fifo: entity work.async_fifo generic map ( g_data_width => 8, g_depth_bits => 3, g_count_bits => 3, g_threshold => 3, g_storage => "distributed" ) port map ( -- write port signals (synchronized to write clock) wr_clock => sys_clock, wr_reset => sys_reset, wr_en => sys_cmd_write, wr_din => sys_io_req.data, wr_flush => '0', wr_count => sys_cmd_count, wr_full => open, wr_almost_full => sys_cmd_full, wr_error => open, wr_inhibit => open, -- read port signals (synchronized to read clock) rd_clock => ulpi_clock, rd_reset => ulpi_reset, rd_en => cmd_get, rd_dout => cmd_data, rd_count => open, rd_empty => cmd_empty, rd_almost_empty => open, rd_error => open ); i_resp_fifo: entity work.async_fifo generic map ( g_data_width => 9, g_depth_bits => 3, g_count_bits => 3, g_threshold => 3, g_storage => "distributed" ) port map ( -- write port signals (synchronized to write clock) wr_clock => ulpi_clock, wr_reset => ulpi_reset, wr_en => resp_put, wr_din => resp_data, wr_flush => '0', wr_count => open, wr_full => resp_full, wr_almost_full => open, wr_error => open, wr_inhibit => open, -- read port signals (synchronized to read clock) rd_clock => sys_clock, rd_reset => sys_reset, rd_en => sys_resp_get, rd_dout => sys_resp_data, rd_count => open, rd_empty => sys_resp_empty, rd_almost_empty => open, rd_error => open ); -- BUS INTERFACE -- -- command / response output word generator process(sys_clock) begin if rising_edge(sys_clock) then sys_resp_get <= '0'; case sys_io_req.address(1 downto 0) is when "00" => sys_cmd_rdata <= sys_resp_data(7 downto 0); when "01" => sys_cmd_rdata <= not sys_resp_empty & "000000" & sys_resp_data(8); when "10" => sys_cmd_rdata <= sys_cmd_full & "0000" & sys_cmd_count; when "11" => sys_cmd_rdata <= X"00"; sys_resp_get <= sys_cmd_read; -- if reading, we'll pull one when others => null; end case; end if; end process; sys_addr_i(sys_addr_i'high downto 0) <= std_logic_vector(sys_io_req.address(sys_addr_i'range)); sys_buf_en <= (sys_io_req.read or sys_io_req.write) and sys_io_req.address(12); sys_descr_en <= (sys_io_req.read or sys_io_req.write) and not sys_io_req.address(12) and not sys_io_req.address(11); sys_cmd_read <= sys_io_req.read and not sys_io_req.address(12) and sys_io_req.address(11); sys_cmd_write <= sys_io_req.write and not sys_io_req.address(12) and sys_io_req.address(11); process(sys_clock) begin if rising_edge(sys_clock) then sys_io_resp.ack <= sys_io_req.read or sys_io_req.write; sys_sel_d <= sys_io_req.read & std_logic_vector(sys_io_req.address(12 downto 11)); end if; end process; with sys_sel_d select sys_io_resp.data <= sys_buf_rdata when "110" | "111", sys_descr_rdata when "100", sys_cmd_rdata when "101", X"00" when others; end wrap;