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--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : SUB_RAMZ --
-- Design : EV_JPEG_ENC --
-- Author : Michal Krepa -- -- --
-- --
--------------------------------------------------------------------------------
--
-- File : SUB_RAMZ.VHD
-- Created : 22/03/2009
--
--------------------------------------------------------------------------------
--
-- Description : RAM memory simulation model
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity SUB_RAMZ is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port (
d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
);
end SUB_RAMZ;
architecture RTL of SUB_RAMZ is
type mem_type is array ((2**RAMADDR_W)-1 downto 0) of
STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal mem : mem_type;
signal read_addr : STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
--attribute ram_style: string;
--attribute ram_style of mem : signal is "distributed";
begin
-------------------------------------------------------------------------------
q_sg:
-------------------------------------------------------------------------------
q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
-------------------------------------------------------------------------------
read_proc: -- register read address
-------------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'event then
read_addr <= raddr;
end if;
end process;
-------------------------------------------------------------------------------
write_proc: --write access
-------------------------------------------------------------------------------
process (clk) begin
if clk = '1' and clk'event then
if we = '1' then
mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
end if;
end if;
end process;
end RTL; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc300.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p03n01i00300ent IS
END c03s01b04x00p03n01i00300ent;
ARCHITECTURE c03s01b04x00p03n01i00300arch OF c03s01b04x00p03n01i00300ent IS
type REAL1 is range REAL'LOW-1.0 to REAL'HIGH+1.0;
BEGIN
TESTING: PROCESS
variable temp : REAL1 := REAL'LOW - 1.0;
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b04x00p03n01i00300 - Range exceeds implementation."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p03n01i00300arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc300.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p03n01i00300ent IS
END c03s01b04x00p03n01i00300ent;
ARCHITECTURE c03s01b04x00p03n01i00300arch OF c03s01b04x00p03n01i00300ent IS
type REAL1 is range REAL'LOW-1.0 to REAL'HIGH+1.0;
BEGIN
TESTING: PROCESS
variable temp : REAL1 := REAL'LOW - 1.0;
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b04x00p03n01i00300 - Range exceeds implementation."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p03n01i00300arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc300.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p03n01i00300ent IS
END c03s01b04x00p03n01i00300ent;
ARCHITECTURE c03s01b04x00p03n01i00300arch OF c03s01b04x00p03n01i00300ent IS
type REAL1 is range REAL'LOW-1.0 to REAL'HIGH+1.0;
BEGIN
TESTING: PROCESS
variable temp : REAL1 := REAL'LOW - 1.0;
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b04x00p03n01i00300 - Range exceeds implementation."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p03n01i00300arch;
|
architecture rtl of fifo is
constant sig8 : record_type_3(element1(7 downto 0),element2(4 downto 0)(7 downto 0)
(elementA(7 downto 0)
,elementB(3 downto 0)
),element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),element5(elementE
(3 downto
0)
(6
downto 0)
,elementF(7 downto 0)
),element6(4 downto
0),element7(7 downto 0));
constant sig9 : t_data_struct(data(7 downto 0));
constant sig9 : t_data_struct(data(7 downto 0)
);
begin
end architecture rtl;
|
package pkg_B is
generic (
B: integer := 2
);
procedure showB;
end pkg_B;
package body pkg_B is
procedure showB is
begin
report "B:" & integer'image(B);
end procedure showB;
end package body pkg_B;
|
------------------------------------------------------------------------
-- EppCtrl.vhd -- Digilent Epp Interface Module
------------------------------------------------------------------------
-- Author : Mircea Dabacan
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Software version: Xilinx ISE 6.2.03i
-- WebPack
------------------------------------------------------------------------
-- This file contains the design for an EPP interface controller.
-- This configuration, in conjunction with a communication module,
-- (Digilent USB, Serial, Network or Parallel module) allows the user
-- to interface some other FPGA implemented "client" components
-- (Digilent Library components or user generated ones)
-- to a PC application program (a Digilent utility or user generated).
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- All the Digilent communication modules above emulate an EPP interface
-- at the FPGA board connector pins, compatible to EppCtrl controller.
-- The controller performs the following functions:
-- - manages the EPP standard handshake
-- - implements the standard EPP Address Register
-- - provides the signals needed to read/write EPP Data Registers.
-- The "client" component(s) is (are) responsible to implement the
-- specific required data registers, as explained below:
-- - declare the data read and write registers;
-- - assign an Epp address for each.
-- A couple of read- respective write- registers can be
-- assigned to the same Epp address. Assign a unique address
-- to each register (couple) throughout all the
-- client components connected to the same EppCtrl.
-- The totality of assigned addresses builds the component
-- address range. If less the 256 (couples of) registers are
-- required, "mirror" or "alias" addresses can be used
-- (incomplete regEppAdrOut(7:0) decoding).
-- The mirror addresses are not allowed to overlap throughout
-- all the client components connected to the same EppCtrl.
-- - use the same clock signal for all data registers as well as
-- for EppCtrl component Write Data registers
-- - connect the inputs of all write registers to busEppOut(7:0)
-- - decode regEppAdrOut(7:0) to generate the CS signal for each
-- write register
-- - use ctlEppDwrOut as WE signal for all the write registers
-- Read Data registers
-- - connect the outputs of all read registers to busEppIn(7:0)
-- THROUGH A MUX
-- - use the regEppAdrOut(7:0) as MUX address lines.
-- - defines two types of Data Register access
-- - Register Transfer - reads or writes a client data register,
-- - no handshake to the client component.
-- - Process Launch - launches a client process and
-- - waits it to complete.
-- The client process is required to conform to the handshake
-- protocol described below.
-- A client data register transfer is also performed.
-- The client component decides to which type the current
-- Data Register Access belongs: a clock period (20ns for 50MHz
-- clock frequency) after ctlEppDwrOut becomes active,
-- EppCtrl samples the HandShakeReqIn input signal.
-- - if inactive, the current transfer cycle completes without a
-- handshake protocol.
-- - if active (HIGH), the current transfer cycle uses a
-- handshake protocol:
--
-- The Handshake protocol
-- - the busEppOut, ctlEppRdCycleOut and regEppAdrOut(7:0)
-- signals freeze
-- - (for a WRITE cycle, ctlEppDwrOut pulses LOW for
-- 1 CK period - the selected write register is set)
-- - the ctlEppStartOut signal is set active (HIGH)
-- - (for a READ cycle, client application places data on
-- busEppIn(7:0))
-- - the controller waits for the ctlEppDoneIn signal to
-- become active (HIGH)
-- - (for a READ cycle, the data transfer is performed 1 CK
-- period later)
-- - the ctlEppStartOut signal is set inactive (LOW)
-- - the controller waits for the ctlEppDoneIn signal to
-- become inactive (LOW)
-- - a new transfer cycle can begin (if required by the PC
-- application)
-- A client component can use the handshake protocol feature for
-- various purposes:
-- - blocking the EppCtrl at all:
-- - activate the HandShakeReqIn input signal
-- - wait for the ctlEppStartOut signal to become active.
-- - keep the ctlEppDoneIn signal inactive (LOW) for the
-- desired time (the Epp interface freezes - the PC
-- software could exit with a time-out error)
-- - activate the ctlEppDoneIn signal.
-- - wait for the ctlEppStartOut signal to become inactive.
-- - inactivate ctlEppDoneIn,
-- - continue its own action.
-- - blocking the EppCtrl cycles for a specific client component:
-- - activate the HandShakeReqIn input signal when the
-- regEppAdrOut(7:0) value belongs to the address range
-- assigned to the specific client component.
-- - wait for the ctlEppStartOut signal to become active.
-- - keep the ctlEppDoneIn signal inactive (LOW) for the
-- desired time (the Epp interface freezes - the PC
-- software could exit with a time-out error)
-- - activate the ctlEppDoneIn signal.
-- - wait for the ctlEppStartOut signal to become inactive.
-- - inactivate ctlEppDoneIn,
-- - continue its own action.
-- - enlarging the EppCtrl cycles for specific data register
-- transfer cycles:
-- - activate the HandShakeReqIn input signal when the
-- regEppAdrOut(7:0) value equals any Data Register address
-- that requires an internal process.
-- (ctlEppRdCycleOut signal can be used to discriminate
-- between read and write cycles; ctlEppDwrOut signal
-- cannot be used because it is not yet active when
-- HandshakeReqIn is sampled)
-- - wait for the ctlEppStartOut signal to become active.
-- - launch the appropriate process (based on the
-- regEppAdrOut(7:0) and ctlEppRdCycleOut values)
-- - keep the ctlEppDoneIn signal inactive (LOW) until the
-- process completes(the Epp interface freezes - the PC
-- software could exit with a time-out error)
-- - get ready for the current transfer cycle completion.
-- - activate the ctlEppDoneIn signal.
-- - wait for the ctlEppStartOut signal to become inactive.
-- - inactivate ctlEppDoneIn,
-- - continue its own action.
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- Epp bus signals
-- clk : in std_logic; -- system clock (50MHz)
-- EppAstb: in std_logic; -- Address strobe
-- EppDstb: in std_logic; -- Data strobe
-- EppWr : in std_logic; -- Port write signal
-- EppRst : in std_logic; -- Port reset signal
-- pint : out std_logic; -- Port interrupt request (not used)
-- EppDB : inout std_logic_vector(7 downto 0); -- port data bus
-- EppWait: out std_logic; -- Port wait signal
-- User signals
-- busEppOut: out std_logic_vector(7 downto 0); -- Data Output bus
-- busEppIn: in std_logic_vector(7 downto 0); -- Data Input bus
-- ctlEppDwrOut: out std_logic; -- Data Write pulse
-- ctlEppRdCycleOut: inout std_logic; -- Indicates a READ Epp cycle
-- regEppAdrOut: inout std_logic_vector(7 downto 0) := "00000000";
-- Epp Address Register content
-- HandShakeReqIn: in std_logic; -- User Handshake Request
-- ctlEppStartOut: out std_logic; -- Automatic process Start
-- ctlEppDoneIn: in std_logic -- Automatic process Done
------------------------------------------------------------------------
-- Revision History:
-- 10/21/2004(MirceaD): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity EppCtrl is
Port (
-- Epp-like bus signals
clk : in std_logic; -- system clock (50MHz)
EppAstb: in std_logic; -- Address strobe
EppDstb: in std_logic; -- Data strobe
EppWr : in std_logic; -- Port write signal
EppRst : in std_logic; -- Port reset signal
-- pint : out std_logic; -- Port interrupt request (not used)
EppDB : inout std_logic_vector(7 downto 0); -- port data bus
EppWait: out std_logic; -- Port wait signal
-- User signals
busEppOut: out std_logic_vector(7 downto 0); -- Data Output bus
busEppIn: in std_logic_vector(7 downto 0); -- Data Input bus
ctlEppDwrOut: out std_logic; -- Data Write pulse
ctlEppRdCycleOut: inout std_logic; -- Indicates a READ Epp cycle
regEppAdrOut: inout std_logic_vector(7 downto 0) := "00000000";
-- Epp Address Register content
HandShakeReqIn: in std_logic; -- User Handshake Request
ctlEppStartOut: out std_logic; -- Automatic process Start
ctlEppDoneIn: in std_logic -- Automatic process Done
);
end EppCtrl;
architecture Behavioral of EppCtrl is
------------------------------------------------------------------------
-- Constant and Signal Declarations
------------------------------------------------------------------------
-- The following constants define state codes for the EPP port interface
-- state machine.
-- The states are such a way assigned that each transition
-- changes a single state register bit (Grey code - like)
constant stEppReady : std_logic_vector(2 downto 0) := "000";
constant stEppStb : std_logic_vector(2 downto 0) := "010";
constant stEppRegTransf : std_logic_vector(2 downto 0) := "110";
constant stEppSetProc : std_logic_vector(2 downto 0) := "011";
constant stEppLaunchProc: std_logic_vector(2 downto 0) := "111";
constant stEppWaitProc : std_logic_vector(2 downto 0) := "101";
constant stEppDone : std_logic_vector(2 downto 0) := "100";
-- Epp state register and next state signal for the Epp FSM
signal stEppCur: std_logic_vector(2 downto 0) := stEppReady;
signal stEppNext: std_logic_vector(2 downto 0);
-- The attribute lines below prevent the ISE compiler to extract and
-- optimize the state machines.
-- WebPack 5.1 doesn't need them (the default value is NO)
-- WebPack 6.2 has the default value YES, so without these lines would
-- "optimize" the state machines.
-- Although the overall circuit would be optimized, the particular goal
-- of "glitch free output signals" may not be reached.
-- That is the reason of implementing the state machine as described in
-- the constant declarations above.
attribute fsm_extract : string;
attribute fsm_extract of stEppCur: signal is "no";
attribute fsm_extract of stEppNext: signal is "no";
attribute fsm_encoding : string;
attribute fsm_encoding of stEppCur: signal is "user";
attribute fsm_encoding of stEppNext: signal is "user";
attribute signal_encoding : string;
attribute signal_encoding of stEppCur: signal is "user";
attribute signal_encoding of stEppNext: signal is "user";
-- Signals used by Epp state machine
signal busEppInternal: std_logic_vector(7 downto 0);
-- signal ctlEppDir : std_logic;
signal ctlEppAwr : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Map basic status and control signals
------------------------------------------------------------------------
-- Epp signals
-- Port signals
-- Synchronized Epp inputs:
process(clk)
begin
if clk'event and clk='1' then
if stEppCur = stEppReady then
ctlEppRdCycleOut <= '0';
elsif stEppCur = stEppStb then
ctlEppRdCycleOut <= EppWr;
-- not equivalent to EppWr due to default state
end if;
end if;
end process;
busEppOut <= EppDB; -- name meaning change!!!
EppDB <=busEppInternal when (ctlEppRdCycleOut = '1') else "ZZZZZZZZ";
busEppInternal <= regEppAdrOut when EppAstb = '0' else busEppIn;
-- Epp State machine related signals
EppWait <= '1' when stEppCur = stEppDone else '0';
ctlEppAwr <= '1' when stEppCur = stEppRegTransf and
EppAstb = '0' and
EppWr = '0' else
'0';
ctlEppDwrOut <= '1' when (stEppCur = stEppRegTransf or
stEppCur = stEppSetProc)
and EppDstb = '0'
and EppWr = '0' else
'0';
ctlEppStartOut <= '1' when stEppCur = stEppLaunchProc else
'0';
------------------------------------------------------------------------
-- EPP Interface Control State Machine
------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'Event then
if EppRst = '0' then
stEppCur <= stEppReady;
else
stEppCur <= stEppNext;
end if;
end if;
end process;
process (stEppCur)
begin
case stEppCur is
-- Idle state waiting for the beginning of an EPP cycle
when stEppReady =>
if EppAstb = '0' or EppDstb = '0' then
-- Epp cycle recognized
stEppNext <= stEppStb;
else
-- Remain in ready state
stEppNext <= stEppReady;
end if;
when stEppStb =>
if EppDstb = '0' and HandShakeReqIn = '1' then
stEppNext <= stEppSetProc;
else
stEppNext <= stEppRegTransf;
end if;
-- Data or Address register transfer
when stEppRegTransf =>
stEppNext <= stEppDone;
-- Automatic Process
when stEppSetProc =>
stEppNext <= stEppLaunchProc;
when stEppLaunchProc =>
if ctlEppDoneIn = '0' then
stEppNext <= stEppLaunchProc;
else
stEppNext <= stEppWaitProc;
end if;
when stEppWaitProc =>
if ctlEppDoneIn = '1' then
stEppNext <= stEppWaitProc;
else
stEppNext <= stEppDone;
end if;
when stEppDone =>
if EppAstb = '0' or EppDstb = '0' then
stEppNext <= stEppDone;
else
stEppNext <= stEppReady;
end if;
-- Some unknown state
when others =>
stEppNext <= stEppReady;
end case;
end process;
-- EPP Address register
process (clk, ctlEppAwr)
begin
if clk = '1' and clk'Event then
if ctlEppAwr = '1' then
regEppAdrOut <= EppDB;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------
-- Design Name : lfsr
-- File Name : lfsr_updown_tb.vhd
-- Function : Linear feedback shift register
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity lfsr_updown_tb is
end entity;
architecture test of lfsr_updown_tb is
constant WIDTH :integer := 8;
signal clk :std_logic := '0';
signal reset :std_logic := '1';
signal enable :std_logic := '0';
signal up_down :std_logic := '0';
signal count :std_logic_vector (WIDTH-1 downto 0);
signal overflow :std_logic;
component lfsr_updown is
generic (
WIDTH :integer := 8
);
port (
clk :in std_logic; -- Clock input
reset :in std_logic; -- Reset input
enable :in std_logic; -- Enable input
up_down :in std_logic; -- Up Down input
count :out std_logic_vector (WIDTH-1 downto 0); -- Count output
overflow :out std_logic -- Overflow output
);
end component;
constant PERIOD :time := 20 ns;
begin
clk <= not clk after PERIOD/2;
reset <= '0' after PERIOD*10;
enable <= '1' after PERIOD*11;
up_down <= '1' after PERIOD*22;
-- Display the time and result
process (reset, enable, up_down, count, overflow)
variable wrbuf :line;
begin
write(wrbuf, string'("Time: " ));
writeline(output, wrbuf);
write(wrbuf, now);
writeline(output, wrbuf);
write(wrbuf, string'(" rst: " ));
writeline(output, wrbuf);
write(wrbuf, reset);
writeline(output, wrbuf);
write(wrbuf, string'(" enable: " ));
writeline(output, wrbuf);
write(wrbuf, enable);
writeline(output, wrbuf);
write(wrbuf, string'(" up_down: " ));
writeline(output, wrbuf);
write(wrbuf, up_down);
writeline(output, wrbuf);
write(wrbuf, string'(" count: " ));
writeline(output, wrbuf);
write(wrbuf, count);
writeline(output, wrbuf);
write(wrbuf, string'(" overflow: "));
writeline(output, wrbuf);
write(wrbuf, overflow);
writeline(output, wrbuf);
end process;
Inst_lfsr_updown : lfsr_updown
port map (
clk => clk,
reset => reset,
enable => enable,
up_down => up_down,
count => count,
overflow => overflow
);
end architecture;
|
-------------------------------------------------------
-- Design Name : lfsr
-- File Name : lfsr_updown_tb.vhd
-- Function : Linear feedback shift register
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity lfsr_updown_tb is
end entity;
architecture test of lfsr_updown_tb is
constant WIDTH :integer := 8;
signal clk :std_logic := '0';
signal reset :std_logic := '1';
signal enable :std_logic := '0';
signal up_down :std_logic := '0';
signal count :std_logic_vector (WIDTH-1 downto 0);
signal overflow :std_logic;
component lfsr_updown is
generic (
WIDTH :integer := 8
);
port (
clk :in std_logic; -- Clock input
reset :in std_logic; -- Reset input
enable :in std_logic; -- Enable input
up_down :in std_logic; -- Up Down input
count :out std_logic_vector (WIDTH-1 downto 0); -- Count output
overflow :out std_logic -- Overflow output
);
end component;
constant PERIOD :time := 20 ns;
begin
clk <= not clk after PERIOD/2;
reset <= '0' after PERIOD*10;
enable <= '1' after PERIOD*11;
up_down <= '1' after PERIOD*22;
-- Display the time and result
process (reset, enable, up_down, count, overflow)
variable wrbuf :line;
begin
write(wrbuf, string'("Time: " ));
writeline(output, wrbuf);
write(wrbuf, now);
writeline(output, wrbuf);
write(wrbuf, string'(" rst: " ));
writeline(output, wrbuf);
write(wrbuf, reset);
writeline(output, wrbuf);
write(wrbuf, string'(" enable: " ));
writeline(output, wrbuf);
write(wrbuf, enable);
writeline(output, wrbuf);
write(wrbuf, string'(" up_down: " ));
writeline(output, wrbuf);
write(wrbuf, up_down);
writeline(output, wrbuf);
write(wrbuf, string'(" count: " ));
writeline(output, wrbuf);
write(wrbuf, count);
writeline(output, wrbuf);
write(wrbuf, string'(" overflow: "));
writeline(output, wrbuf);
write(wrbuf, overflow);
writeline(output, wrbuf);
end process;
Inst_lfsr_updown : lfsr_updown
port map (
clk => clk,
reset => reset,
enable => enable,
up_down => up_down,
count => count,
overflow => overflow
);
end architecture;
|
-------------------------------------------------------
-- Design Name : lfsr
-- File Name : lfsr_updown_tb.vhd
-- Function : Linear feedback shift register
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity lfsr_updown_tb is
end entity;
architecture test of lfsr_updown_tb is
constant WIDTH :integer := 8;
signal clk :std_logic := '0';
signal reset :std_logic := '1';
signal enable :std_logic := '0';
signal up_down :std_logic := '0';
signal count :std_logic_vector (WIDTH-1 downto 0);
signal overflow :std_logic;
component lfsr_updown is
generic (
WIDTH :integer := 8
);
port (
clk :in std_logic; -- Clock input
reset :in std_logic; -- Reset input
enable :in std_logic; -- Enable input
up_down :in std_logic; -- Up Down input
count :out std_logic_vector (WIDTH-1 downto 0); -- Count output
overflow :out std_logic -- Overflow output
);
end component;
constant PERIOD :time := 20 ns;
begin
clk <= not clk after PERIOD/2;
reset <= '0' after PERIOD*10;
enable <= '1' after PERIOD*11;
up_down <= '1' after PERIOD*22;
-- Display the time and result
process (reset, enable, up_down, count, overflow)
variable wrbuf :line;
begin
write(wrbuf, string'("Time: " ));
writeline(output, wrbuf);
write(wrbuf, now);
writeline(output, wrbuf);
write(wrbuf, string'(" rst: " ));
writeline(output, wrbuf);
write(wrbuf, reset);
writeline(output, wrbuf);
write(wrbuf, string'(" enable: " ));
writeline(output, wrbuf);
write(wrbuf, enable);
writeline(output, wrbuf);
write(wrbuf, string'(" up_down: " ));
writeline(output, wrbuf);
write(wrbuf, up_down);
writeline(output, wrbuf);
write(wrbuf, string'(" count: " ));
writeline(output, wrbuf);
write(wrbuf, count);
writeline(output, wrbuf);
write(wrbuf, string'(" overflow: "));
writeline(output, wrbuf);
write(wrbuf, overflow);
writeline(output, wrbuf);
end process;
Inst_lfsr_updown : lfsr_updown
port map (
clk => clk,
reset => reset,
enable => enable,
up_down => up_down,
count => count,
overflow => overflow
);
end architecture;
|
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 75216)
`protect data_block
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|
`protect begin_protected
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|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
type phase_type is (wash, other_phase);
signal phase : phase_type := other_phase;
type cycle_type is (delicate_cycle, other_cycle);
signal cycle_select : cycle_type := delicate_cycle;
type speed_type is (slow, fast);
signal agitator_speed : speed_type := slow;
signal agitator_on : boolean := false;
begin
process_1_e : process (phase, cycle_select) is
begin
-- code from book:
if phase = wash then
if cycle_select = delicate_cycle then
agitator_speed <= slow;
else
agitator_speed <= fast;
end if;
agitator_on <= true;
end if;
-- end of code from book
end process process_1_e;
stimulus : process is
begin
cycle_select <= other_cycle; wait for 100 ns;
phase <= wash; wait for 100 ns;
cycle_select <= delicate_cycle; wait for 100 ns;
cycle_select <= other_cycle; wait for 100 ns;
phase <= other_phase; wait for 100 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
type phase_type is (wash, other_phase);
signal phase : phase_type := other_phase;
type cycle_type is (delicate_cycle, other_cycle);
signal cycle_select : cycle_type := delicate_cycle;
type speed_type is (slow, fast);
signal agitator_speed : speed_type := slow;
signal agitator_on : boolean := false;
begin
process_1_e : process (phase, cycle_select) is
begin
-- code from book:
if phase = wash then
if cycle_select = delicate_cycle then
agitator_speed <= slow;
else
agitator_speed <= fast;
end if;
agitator_on <= true;
end if;
-- end of code from book
end process process_1_e;
stimulus : process is
begin
cycle_select <= other_cycle; wait for 100 ns;
phase <= wash; wait for 100 ns;
cycle_select <= delicate_cycle; wait for 100 ns;
cycle_select <= other_cycle; wait for 100 ns;
phase <= other_phase; wait for 100 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
type phase_type is (wash, other_phase);
signal phase : phase_type := other_phase;
type cycle_type is (delicate_cycle, other_cycle);
signal cycle_select : cycle_type := delicate_cycle;
type speed_type is (slow, fast);
signal agitator_speed : speed_type := slow;
signal agitator_on : boolean := false;
begin
process_1_e : process (phase, cycle_select) is
begin
-- code from book:
if phase = wash then
if cycle_select = delicate_cycle then
agitator_speed <= slow;
else
agitator_speed <= fast;
end if;
agitator_on <= true;
end if;
-- end of code from book
end process process_1_e;
stimulus : process is
begin
cycle_select <= other_cycle; wait for 100 ns;
phase <= wash; wait for 100 ns;
cycle_select <= delicate_cycle; wait for 100 ns;
cycle_select <= other_cycle; wait for 100 ns;
phase <= other_phase; wait for 100 ns;
wait;
end process stimulus;
end architecture test;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_apb
-- File: i2c2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from I2C.
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity i2c2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb_apb;
architecture rtl of i2c2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
constant SLVA_OFF : std_logic_vector(4 downto 2) := "100";
constant SLVC_OFF : std_logic_vector(4 downto 2) := "101";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2C2AHB, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
i2c2ahbi : i2c2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal i2c2ahbo : i2c2ahb_out_type;
begin
bridge : i2c2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
i2ci => i2ci, i2co => i2co, i2c2ahbi => r.i2c2ahbi,
i2c2ahbo => i2c2ahbo);
comb: process (r, rstn, apbi, i2c2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := i2c2ahbo.prot; v.dmax := i2c2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.i2c2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.i2c2ahbi.haddr;
when MASK_OFF => apbout := r.i2c2ahbi.hmask;
when SLVA_OFF => apbout(6 downto 0) := r.i2c2ahbi.slvaddr;
when SLVC_OFF => apbout(6 downto 0) := r.i2c2ahbi.cfgaddr;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.i2c2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.i2c2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.i2c2ahbi.hmask := apbi.pwdata;
when SLVA_OFF => v.i2c2ahbi.slvaddr := apbi.pwdata(6 downto 0);
when SLVC_OFF => v.i2c2ahbi.cfgaddr := apbi.pwdata(6 downto 0);
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((i2c2ahbo.dma and not r.dmax) or
(i2c2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or i2c2ahbo.prot; v.wr := i2c2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.i2c2ahbi.en := conv_std_logic(resen = 1);
v.i2c2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.i2c2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.i2c2ahbi.slvaddr := conv_std_logic_vector(i2cslvaddr, 7);
v.i2c2ahbi.cfgaddr := conv_std_logic_vector(i2ccfgaddr, 7);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in i2c2ahbx...
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity aggr01 is
port (a : std_logic_vector (7 downto 0);
b : out std_logic_vector (7 downto 0));
end aggr01;
architecture behav of aggr01 is
constant mask : std_logic_vector (7 downto 0) :=
(0 => '1', others => '0');
begin
b <= a and mask;
end behav;
|
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 11:35:57 05/16/2016
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY dds_tb IS
END dds_tb;
ARCHITECTURE behavior OF dds_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dds
PORT(
clk : IN std_logic;
freq : IN unsigned(16 downto 0);
form : IN unsigned(1 downto 0);
amp : OUT unsigned(11 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal freq : unsigned(16 downto 0) := (others => '0');
signal form : unsigned(1 downto 0) := (others => '0');
--Outputs
signal amp : unsigned(11 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns; --50mhz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dds PORT MAP (
clk => clk,
freq => freq,
form => form,
amp => amp
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
form <= "00";
freq <= to_unsigned(50000,17);
wait for 40 us;
freq <= to_unsigned(100000,17);
wait for 20 us;
form <= "01";
freq <= to_unsigned(50000,17);
wait for 40 us;
freq <= to_unsigned(100000,17);
wait for 20 us;
form <= "10";
freq <= to_unsigned(50000,17);
wait for 40 us;
freq <= to_unsigned(100000,17);
wait for 20 us;
form <= "11";
freq <= to_unsigned(50000,17);
wait for 40 us;
freq <= to_unsigned(100000,17);
wait for 20 us;
wait;
end process;
END;
|
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 2.3
-- \ \ Application : MIG
-- / / Filename : ddr_mig.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module can be instantiated in the
-- system and interconnect as shown in user design wrapper file (user top module).
-- In addition to the memory controller, the module instantiates:
-- 1. Clock generation/distribution, reset logic
-- 2. IDELAY control block
-- 3. Debug logic
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ddr_mig is
generic (
RST_ACT_LOW : integer := 1;
-- =1 for active low reset,
-- =0 for active high.
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
CK_WIDTH : integer := 1;
-- # of CK/CK# outputs to memory.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
nCS_PER_RANK : integer := 1;
-- # of unique CS outputs per rank for phy
CKE_WIDTH : integer := 1;
-- # of CKE outputs to memory.
DATA_BUF_ADDR_WIDTH : integer := 5;
DQ_CNT_WIDTH : integer := 4;
-- = ceil(log2(DQ_WIDTH))
DQ_PER_DM : integer := 8;
DM_WIDTH : integer := 2;
-- # of DM (data mask)
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC : string := "OFF";
ECC_TEST : string := "OFF";
PAYLOAD_WIDTH : integer := 16;
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--Possible Parameters
--1.BANK_ROW_COLUMN : Address mapping is
-- in form of Bank Row Column.
--2.ROW_BANK_COLUMN : Address mapping is
-- in the form of Row Bank Column.
--3.TG_TEST : Scrambles Address bits
-- for distributed Addressing.
nBANK_MACHS : integer := 4;
RANKS : integer := 1;
-- # of Ranks.
ODT_WIDTH : integer := 1;
-- # of ODT outputs to memory.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
USE_CS_PORT : integer := 1;
-- # = 1, When Chip Select (CS#) output is enabled
-- = 0, When Chip Select (CS#) output is disabled
-- If CS_N disabled, user must connect
-- DRAM CS_N input(s) to ground
USE_DM_PORT : integer := 1;
-- # = 1, When Data Mask option is enabled
-- = 0, When Data Mask option is disbaled
-- When Data Mask option is disabled in
-- MIG Controller Options page, the logic
-- related to Data Mask should not get
-- synthesized
USE_ODT_PORT : integer := 1;
-- # = 1, When ODT output is enabled
-- = 0, When ODT output is disabled
PHY_CONTROL_MASTER_BANK : integer := 0;
-- The bank index where master PHY_CONTROL resides,
-- equal to the PLL residing bank
MEM_DENSITY : string := "1Gb";
-- Indicates the density of the Memory part
-- Added for the sake of Vivado simulations
MEM_SPEEDGRADE : string := "25E";
-- Indicates the Speed grade of Memory Part
-- Added for the sake of Vivado simulations
MEM_DEVICE_WIDTH : integer := 16;
-- Indicates the device width of the Memory Part
-- Added for the sake of Vivado simulations
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
AL : string := "0";
-- DDR3 SDRAM:
-- Additive Latency (Mode Register 1).
-- # = "0", "CL-1", "CL-2".
-- DDR2 SDRAM:
-- Additive Latency (Extended Mode Register).
nAL : integer := 0;
-- # Additive Latency in number of clock
-- cycles.
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
BURST_TYPE : string := "SEQ";
-- DDR3 SDRAM: Burst Type (Mode Register 0).
-- DDR2 SDRAM: Burst Type (Mode Register).
-- # = "SEQ" - (Sequential),
-- = "INT" - (Interleaved).
CL : integer := 5;
-- in number of clock cycles
-- DDR3 SDRAM: CAS Latency (Mode Register 0).
-- DDR2 SDRAM: CAS Latency (Mode Register).
OUTPUT_DRV : string := "HIGH";
-- Output Drive Strength (Extended Mode Register).
-- # = "HIGH" - FULL,
-- = "LOW" - REDUCED.
RTT_NOM : string := "50";
-- RTT (Nominal) (Extended Mode Register).
-- = "150" - 150 Ohms,
-- = "75" - 75 Ohms,
-- = "50" - 50 Ohms.
ADDR_CMD_MODE : string := "1T" ;
-- # = "1T", "2T".
REG_CTRL : string := "OFF";
-- # = "ON" - RDIMMs,
-- = "OFF" - Components, SODIMMs, UDIMMs.
--***************************************************************************
-- The following parameters are multiplier and divisor factors for PLLE2.
-- Based on the selected design frequency these parameters vary.
--***************************************************************************
CLKIN_PERIOD : integer := 4999;
-- Input Clock Period
CLKFBOUT_MULT : integer := 6;
-- write PLL VCO multiplier
DIVCLK_DIVIDE : integer := 1;
-- write PLL VCO divisor
CLKOUT0_PHASE : real := 0.0;
-- Phase for PLL output clock (CLKOUT0)
CLKOUT0_DIVIDE : integer := 2;
-- VCO output divisor for PLL output clock (CLKOUT0)
CLKOUT1_DIVIDE : integer := 4;
-- VCO output divisor for PLL output clock (CLKOUT1)
CLKOUT2_DIVIDE : integer := 64;
-- VCO output divisor for PLL output clock (CLKOUT2)
CLKOUT3_DIVIDE : integer := 16;
-- VCO output divisor for PLL output clock (CLKOUT3)
MMCM_VCO : integer := 1200;
-- Max Freq (MHz) of MMCM VCO
MMCM_MULT_F : integer := 15;
-- write MMCM VCO multiplier
MMCM_DIVCLK_DIVIDE : integer := 1;
-- write MMCM VCO divisor
--***************************************************************************
-- Memory Timing Parameters. These parameters varies based on the selected
-- memory part.
--***************************************************************************
tCKE : integer := 7500;
-- memory tCKE paramter in pS
tFAW : integer := 45000;
-- memory tRAW paramter in pS.
tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
tRAS : integer := 40000;
-- memory tRAS paramter in pS.
tRCD : integer := 15000;
-- memory tRCD paramter in pS.
tREFI : integer := 7800000;
-- memory tREFI paramter in pS.
tRFC : integer := 127500;
-- memory tRFC paramter in pS.
tRP : integer := 12500;
-- memory tRP paramter in pS.
tRRD : integer := 10000;
-- memory tRRD paramter in pS.
tRTP : integer := 7500;
-- memory tRTP paramter in pS.
tWTR : integer := 7500;
-- memory tWTR paramter in pS.
tZQI : integer := 128000000;
-- memory tZQI paramter in nS.
tZQCS : integer := 64;
-- memory tZQCS paramter in clock cycles.
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- The following parameters varies based on the pin out entered in MIG GUI.
-- Do not change any of these parameters directly by editing the RTL.
-- Any changes required should be done through GUI and the design regenerated.
--***************************************************************************
BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
-- Byte lanes used in an IO column.
BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
DATA_CTL_B0 : std_logic_vector(3 downto 0) := "0101";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B2 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"FFC3F7FFF3FE";
PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
-- control/address/data pin mapping parameters
CK_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000003";
ADDR_MAP
: std_logic_vector(191 downto 0) := X"00000000001003301A01903203A034018036012011017015";
BANK_MAP : std_logic_vector(35 downto 0) := X"01301601B";
CAS_MAP : std_logic_vector(11 downto 0) := X"039";
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000038";
ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000035";
CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000037";
PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
RAS_MAP : std_logic_vector(11 downto 0) := X"014";
WE_MAP : std_logic_vector(11 downto 0) := X"03B";
DQS_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000200";
DATA0_MAP : std_logic_vector(95 downto 0) := X"008004009007005001006003";
DATA1_MAP : std_logic_vector(95 downto 0) := X"022028020024027025026021";
DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000029002";
MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000001";
-- Mapping of Ranks.
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
-- Mapping of Ranks.
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
IBUF_LPWR_MODE : string := "OFF";
-- to phy_top
DATA_IO_IDLE_PWRDWN : string := "ON";
-- # = "ON", "OFF"
BANK_TYPE : string := "HR_IO";
-- # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
DATA_IO_PRIM_TYPE : string := "HR_LP";
-- # = "HP_LP", "HR_LP", "DEFAULT"
CKE_ODT_AUX : string := "FALSE";
USER_REFRESH : string := "OFF";
WRLVL : string := "OFF";
-- # = "ON" - DDR3 SDRAM
-- = "OFF" - DDR2 SDRAM.
ORDERING : string := "STRICT";
-- # = "NORM", "STRICT", "RELAXED".
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
-- Calibration row address will be used for
-- calibration read and write operations
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
-- Calibration column address will be used for
-- calibration read and write operations
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
-- Calibration bank address will be used for
-- calibration read and write operations
TCQ : integer := 100;
IODELAY_GRP0 : string := "DDR_IODELAY_MIG0";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency (200MHz).
IODELAY_GRP1 : string := "DDR_IODELAY_MIG1";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency (300MHz/400MHz).
SYSCLK_TYPE : string := "NO_BUFFER";
-- System clock type DIFFERENTIAL, SINGLE_ENDED,
-- NO_BUFFER
REFCLK_TYPE : string := "USE_SYSTEM_CLOCK";
-- Reference clock type DIFFERENTIAL, SINGLE_ENDED
-- NO_BUFFER, USE_SYSTEM_CLOCK
SYS_RST_PORT : string := "FALSE";
-- "TRUE" - if pin is selected for sys_rst
-- and IBUF will be instantiated.
-- "FALSE" - if pin is not selected for sys_rst
FPGA_SPEED_GRADE : integer := 1;
-- FPGA speed grade
REF_CLK_MMCM_IODELAY_CTRL : string := "FALSE";
CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
DRAM_TYPE : string := "DDR2";
CAL_WIDTH : string := "HALF";
STARVE_LIMIT : integer := 2;
-- # = 2,3,4.
--***************************************************************************
-- Referece clock frequency parameters
--***************************************************************************
REFCLK_FREQ : real := 200.0;
-- IODELAYCTRL reference clock frequency
DIFF_TERM_REFCLK : string := "TRUE";
-- Differential Termination for idelay
-- reference clock input pins
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
tCK : integer := 3333;
-- memory tCK paramter.
-- # = Clock Period in pS.
nCK_PER_CLK : integer := 4;
-- # of memory CKs per fabric CLK
DIFF_TERM_SYSCLK : string := "TRUE";
-- Differential Termination for System
-- clock input pins
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "EXTERNAL"
-- # = "INTERNAL", "EXTERNAL"
-- RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port (
-- Inouts
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH/8)-1 downto 0) ;
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
-- The 12 MSB bits of the temperature sensor transfer
-- function need to be connected to this port. This port
-- will be synchronized w.r.t. to fabric clock internally.
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity ddr_mig;
architecture arch_ddr_mig of ddr_mig is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;
constant DATA_WIDTH : integer := 16;
function ECCWIDTH return integer is
begin
if(ECC = "OFF") then
return 0;
else
if(DATA_WIDTH <= 4) then
return 4;
elsif(DATA_WIDTH <= 10) then
return 5;
elsif(DATA_WIDTH <= 26) then
return 6;
elsif(DATA_WIDTH <= 57) then
return 7;
elsif(DATA_WIDTH <= 120) then
return 8;
elsif(DATA_WIDTH <= 247) then
return 9;
else
return 10;
end if;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant TAPSPERKCLK : integer := 56;
function TEMP_MON return string is
begin
if(SIMULATION = "TRUE") then
return "ON";
else
return "OFF";
end if;
end function;
constant BM_CNT_WIDTH : integer := clogb2(nBANK_MACHS);
constant ECC_WIDTH : integer := ECCWIDTH;
constant DATA_BUF_OFFSET_WIDTH : integer := 1;
constant MC_ERR_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH
+ COL_WIDTH + DATA_BUF_OFFSET_WIDTH;
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
constant TEMP_MON_EN : string := TEMP_MON;
-- Enable or disable the temp monitor module
constant tTEMPSAMPLE : integer := 10000000; -- sample every 10 us
constant XADC_CLK_PERIOD : integer := 5000; -- Use 200 MHz IODELAYCTRL clock
component mig_7series_v2_3_iodelay_ctrl is
generic(
TCQ : integer;
IODELAY_GRP0 : string;
IODELAY_GRP1 : string;
REFCLK_TYPE : string;
SYSCLK_TYPE : string;
SYS_RST_PORT : string;
RST_ACT_LOW : integer;
DIFF_TERM_REFCLK : string;
FPGA_SPEED_GRADE : integer;
REF_CLK_MMCM_IODELAY_CTRL : string
);
port (
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
clk_ref_i : in std_logic;
sys_rst : in std_logic;
clk_ref : out std_logic_vector(1 downto 0);
sys_rst_o : out std_logic;
iodelay_ctrl_rdy : out std_logic_vector(1 downto 0)
);
end component mig_7series_v2_3_iodelay_ctrl;
component mig_7series_v2_3_clk_ibuf is
generic (
SYSCLK_TYPE : string;
DIFF_TERM_SYSCLK : string
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk_i : in std_logic;
mmcm_clk : out std_logic
);
end component mig_7series_v2_3_clk_ibuf;
component mig_7series_v2_3_infrastructure is
generic (
SIMULATION : string := "TRUE";
TCQ : integer;
CLKIN_PERIOD : integer;
nCK_PER_CLK : integer;
SYSCLK_TYPE : string;
UI_EXTRA_CLOCKS : string := "FALSE";
CLKFBOUT_MULT : integer;
DIVCLK_DIVIDE : integer;
CLKOUT0_PHASE : real;
CLKOUT0_DIVIDE : integer;
CLKOUT1_DIVIDE : integer;
CLKOUT2_DIVIDE : integer;
CLKOUT3_DIVIDE : integer;
MMCM_VCO : integer;
MMCM_MULT_F : integer;
MMCM_DIVCLK_DIVIDE : integer;
MMCM_CLKOUT0_EN : string := "FALSE";
MMCM_CLKOUT1_EN : string := "FALSE";
MMCM_CLKOUT2_EN : string := "FALSE";
MMCM_CLKOUT3_EN : string := "FALSE";
MMCM_CLKOUT4_EN : string := "FALSE";
MMCM_CLKOUT0_DIVIDE : integer := 1;
MMCM_CLKOUT1_DIVIDE : integer := 1;
MMCM_CLKOUT2_DIVIDE : integer := 1;
MMCM_CLKOUT3_DIVIDE : integer := 1;
MMCM_CLKOUT4_DIVIDE : integer := 1;
RST_ACT_LOW : integer;
tCK : integer;
MEM_TYPE : string
);
port (
mmcm_clk : in std_logic;
sys_rst : in std_logic;
iodelay_ctrl_rdy : in std_logic_vector(1 downto 0);
psen : in std_logic;
psincdec : in std_logic;
clk : out std_logic;
mem_refclk : out std_logic;
freq_refclk : out std_logic;
sync_pulse : out std_logic;
mmcm_ps_clk : out std_logic;
poc_sample_pd : out std_logic;
iddr_rst : out std_logic;
psdone : out std_logic;
auxout_clk : out std_logic;
ui_addn_clk_0 : out std_logic;
ui_addn_clk_1 : out std_logic;
ui_addn_clk_2 : out std_logic;
ui_addn_clk_3 : out std_logic;
ui_addn_clk_4 : out std_logic;
pll_locked : out std_logic;
mmcm_locked : out std_logic;
rstdiv0 : out std_logic;
rst_phaser_ref : out std_logic;
ref_dll_lock : in std_logic
);
end component mig_7series_v2_3_infrastructure;
component mig_7series_v2_3_tempmon is
generic (
TCQ : integer;
TEMP_MON_CONTROL : string;
XADC_CLK_PERIOD : integer;
tTEMPSAMPLE : integer
);
port (
clk : in std_logic;
xadc_clk : in std_logic;
rst : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
device_temp : out std_logic_vector(11 downto 0)
);
end component mig_7series_v2_3_tempmon;
component mig_7series_v2_3_memc_ui_top_std is
generic (
TCQ : integer;
DDR3_VDD_OP_VOLT : string := "135";
PAYLOAD_WIDTH : integer;
ADDR_CMD_MODE : string;
AL : string;
BANK_WIDTH : integer;
BM_CNT_WIDTH : integer;
BURST_MODE : string;
BURST_TYPE : string;
CA_MIRROR : string := "FALSE";
CK_WIDTH : integer;
CL : integer;
COL_WIDTH : integer;
CMD_PIPE_PLUS1 : string;
CS_WIDTH : integer;
CKE_WIDTH : integer;
CWL : integer := 5;
DATA_WIDTH : integer;
DATA_BUF_ADDR_WIDTH : integer;
DATA_BUF_OFFSET_WIDTH : integer := 1;
DDR2_DQSN_ENABLE : string := "YES";
DM_WIDTH : integer;
DQ_CNT_WIDTH : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_TYPE : string;
DRAM_WIDTH : integer;
ECC : string;
ECC_WIDTH : integer;
ECC_TEST : string;
MC_ERR_ADDR_WIDTH : integer;
MASTER_PHY_CTL : integer;
nAL : integer;
nBANK_MACHS : integer;
nCK_PER_CLK : integer;
nCS_PER_RANK : integer;
ORDERING : string;
IBUF_LPWR_MODE : string;
BANK_TYPE : string;
DATA_IO_PRIM_TYPE : string;
DATA_IO_IDLE_PWRDWN : string;
IODELAY_GRP0 : string;
IODELAY_GRP1 : string;
FPGA_SPEED_GRADE : integer;
OUTPUT_DRV : string;
REG_CTRL : string;
RTT_NOM : string;
RTT_WR : string := "120";
STARVE_LIMIT : integer;
tCK : integer;
tCKE : integer;
tFAW : integer;
tPRDI : integer;
tRAS : integer;
tRCD : integer;
tREFI : integer;
tRFC : integer;
tRP : integer;
tRRD : integer;
tRTP : integer;
tWTR : integer;
tZQI : integer;
tZQCS : integer;
USER_REFRESH : string;
TEMP_MON_EN : string;
WRLVL : string;
DEBUG_PORT : string;
CAL_WIDTH : string;
RANK_WIDTH : integer;
RANKS : integer;
ODT_WIDTH : integer;
ROW_WIDTH : integer;
ADDR_WIDTH : integer;
APP_MASK_WIDTH : integer;
APP_DATA_WIDTH : integer;
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
PHY_0_BITLANES : std_logic_vector(47 downto 0);
PHY_1_BITLANES : std_logic_vector(47 downto 0);
PHY_2_BITLANES : std_logic_vector(47 downto 0);
CK_BYTE_MAP : std_logic_vector(143 downto 0);
ADDR_MAP : std_logic_vector(191 downto 0);
BANK_MAP : std_logic_vector(35 downto 0);
CAS_MAP : std_logic_vector(11 downto 0);
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
CKE_MAP : std_logic_vector(95 downto 0);
ODT_MAP : std_logic_vector(95 downto 0);
CKE_ODT_AUX : string;
CS_MAP : std_logic_vector(119 downto 0);
PARITY_MAP : std_logic_vector(11 downto 0);
RAS_MAP : std_logic_vector(11 downto 0);
WE_MAP : std_logic_vector(11 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
DATA0_MAP : std_logic_vector(95 downto 0);
DATA1_MAP : std_logic_vector(95 downto 0);
DATA2_MAP : std_logic_vector(95 downto 0);
DATA3_MAP : std_logic_vector(95 downto 0);
DATA4_MAP : std_logic_vector(95 downto 0);
DATA5_MAP : std_logic_vector(95 downto 0);
DATA6_MAP : std_logic_vector(95 downto 0);
DATA7_MAP : std_logic_vector(95 downto 0);
DATA8_MAP : std_logic_vector(95 downto 0);
DATA9_MAP : std_logic_vector(95 downto 0);
DATA10_MAP : std_logic_vector(95 downto 0);
DATA11_MAP : std_logic_vector(95 downto 0);
DATA12_MAP : std_logic_vector(95 downto 0);
DATA13_MAP : std_logic_vector(95 downto 0);
DATA14_MAP : std_logic_vector(95 downto 0);
DATA15_MAP : std_logic_vector(95 downto 0);
DATA16_MAP : std_logic_vector(95 downto 0);
DATA17_MAP : std_logic_vector(95 downto 0);
MASK0_MAP : std_logic_vector(107 downto 0);
MASK1_MAP : std_logic_vector(107 downto 0);
SLOT_0_CONFIG : std_logic_vector(7 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
MEM_ADDR_ORDER : string;
CALIB_ROW_ADD : std_logic_vector(15 downto 0);
CALIB_COL_ADD : std_logic_vector(11 downto 0);
CALIB_BA_ADD : std_logic_vector(2 downto 0);
SIM_BYPASS_INIT_CAL : string;
REFCLK_FREQ : real;
USE_CS_PORT : integer;
USE_DM_PORT : integer;
USE_ODT_PORT : integer;
IDELAY_ADJ : string;
FINE_PER_BIT : string;
CENTER_COMP_MODE : string;
PI_VAL_ADJ : string;
TAPSPERKCLK : integer := 56
);
port (
clk : in std_logic;
clk_ref : in std_logic_vector(1 downto 0);
mem_refclk : in std_logic;
freq_refclk : in std_logic;
pll_lock : in std_logic;
sync_pulse : in std_logic;
rst : in std_logic;
rst_phaser_ref : in std_logic;
ref_dll_lock : out std_logic;
iddr_rst : in std_logic;
mmcm_ps_clk : in std_logic;
poc_sample_pd : in std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_parity : out std_logic;
ddr_we_n : out std_logic;
bank_mach_next : out std_logic_vector(BM_CNT_WIDTH-1 downto 0);
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_hi_pri : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8)-1 downto 0);
app_wdf_wren : in std_logic;
app_correct_en_i : in std_logic;
app_raw_not_ecc : in std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_ecc_multiple_err : out std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
psen : out std_logic;
psincdec : out std_logic;
psdone : in std_logic;
device_temp : in std_logic_vector(11 downto 0);
dbg_idel_down_all : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_rddata : out std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_final_po_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
dbg_prbs_final_dqs_tap_cnt_r : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_prbs_first_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_prbs_second_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
init_calib_complete : out std_logic;
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_cpt_tap_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
dbg_rddata_valid : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
dbg_rd_data_offset : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
dbg_pi_phaselock_start : out std_logic;
dbg_pi_phaselocked_done : out std_logic;
dbg_pi_phaselock_err : out std_logic;
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_pi_dqsfound_err : out std_logic;
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrcal_err : out std_logic;
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_calib_rd_data_offset_1 : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_calib_rd_data_offset_2 : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_data_offset : out std_logic_vector(5 downto 0);
dbg_data_offset_1 : out std_logic_vector(5 downto 0);
dbg_data_offset_2 : out std_logic_vector(5 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic;
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector((DRAM_WIDTH*16)-1 downto 0)
);
end component mig_7series_v2_3_memc_ui_top_std;
-- Signal declarations
signal bank_mach_next : std_logic_vector(BM_CNT_WIDTH-1 downto 0);
signal clk : std_logic;
signal clk_ref : std_logic_vector(1 downto 0);
signal iodelay_ctrl_rdy : std_logic_vector(1 downto 0);
signal clk_ref_in : std_logic;
signal sys_rst_o : std_logic;
signal freq_refclk : std_logic;
signal mem_refclk : std_logic;
signal pll_locked : std_logic;
signal sync_pulse : std_logic;
signal mmcm_ps_clk : std_logic;
signal poc_sample_pd : std_logic;
signal psen : std_logic;
signal psincdec : std_logic;
signal psdone : std_logic;
signal iddr_rst : std_logic;
signal ref_dll_lock : std_logic;
signal rst_phaser_ref : std_logic;
signal rst : std_logic;
signal app_ecc_multiple_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal ddr2_reset_n : std_logic;
signal ddr2_parity : std_logic;
signal init_calib_complete_i : std_logic;
signal sys_clk_p : std_logic;
signal sys_clk_n : std_logic;
signal mmcm_clk : std_logic;
signal clk_ref_p : std_logic;
signal clk_ref_n : std_logic;
signal clk_ref_i : std_logic;
signal device_temp : std_logic_vector(11 downto 0);
-- Debug port signals
signal dbg_idel_down_all : std_logic;
signal dbg_idel_down_cpt : std_logic;
signal dbg_idel_up_all : std_logic;
signal dbg_idel_up_cpt : std_logic;
signal dbg_sel_all_idel_cpt : std_logic;
signal dbg_sel_idel_cpt : std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
signal dbg_po_f_stg23_sel : std_logic;
signal dbg_sel_pi_incdec : std_logic;
signal dbg_sel_po_incdec : std_logic;
signal dbg_byte_sel : std_logic_vector(DQS_CNT_WIDTH downto 0);
signal dbg_pi_f_inc : std_logic;
signal dbg_po_f_inc : std_logic;
signal dbg_pi_f_dec : std_logic;
signal dbg_po_f_dec : std_logic;
signal dbg_pi_counter_read_val : std_logic_vector(5 downto 0);
signal dbg_po_counter_read_val : std_logic_vector(8 downto 0);
signal dbg_prbs_final_dqs_tap_cnt_r : std_logic_vector(11 downto 0);
signal dbg_prbs_first_edge_taps : std_logic_vector(11 downto 0);
signal dbg_prbs_second_edge_taps : std_logic_vector(11 downto 0);
signal dbg_cpt_tap_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_dq_idelay_tap_cnt : std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_calib_top : std_logic_vector(255 downto 0);
signal dbg_cpt_first_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_cpt_second_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_rd_data_offset : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_phy_rdlvl : std_logic_vector(255 downto 0);
signal dbg_phy_wrcal : std_logic_vector(99 downto 0);
signal dbg_final_po_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
signal dbg_final_po_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
signal dbg_phy_wrlvl : std_logic_vector(255 downto 0);
signal dbg_phy_init : std_logic_vector(255 downto 0);
signal dbg_prbs_rdlvl : std_logic_vector(255 downto 0);
signal dbg_dqs_found_cal : std_logic_vector(255 downto 0);
signal dbg_pi_phaselock_start : std_logic;
signal dbg_pi_phaselocked_done : std_logic;
signal dbg_pi_phaselock_err : std_logic;
signal dbg_pi_dqsfound_start : std_logic;
signal dbg_pi_dqsfound_done : std_logic;
signal dbg_pi_dqsfound_err : std_logic;
signal dbg_wrcal_start : std_logic;
signal dbg_wrcal_done : std_logic;
signal dbg_wrcal_err : std_logic;
signal dbg_pi_dqs_found_lanes_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_pi_phase_locked_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_oclkdelay_calib_start : std_logic;
signal dbg_oclkdelay_calib_done : std_logic;
signal dbg_phy_oclkdelay_cal : std_logic_vector(255 downto 0);
signal dbg_oclkdelay_rd_data : std_logic_vector((DRAM_WIDTH*16)-1 downto 0);
signal dbg_rd_data_edge_detect : std_logic_vector(DQS_WIDTH-1 downto 0);
signal dbg_rddata : std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
signal dbg_rddata_valid : std_logic;
signal dbg_rdlvl_done : std_logic_vector(1 downto 0);
signal dbg_rdlvl_err : std_logic_vector(1 downto 0);
signal dbg_rdlvl_start : std_logic_vector(1 downto 0);
signal dbg_wrlvl_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
signal dbg_wrlvl_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
signal dbg_tap_cnt_during_wrlvl : std_logic_vector(5 downto 0);
signal dbg_wl_edge_detect_valid : std_logic;
signal dbg_wrlvl_done : std_logic;
signal dbg_wrlvl_err : std_logic;
signal dbg_wrlvl_start : std_logic;
signal dbg_rddata_r : std_logic_vector(63 downto 0);
signal dbg_rddata_valid_r : std_logic;
signal ocal_tap_cnt : std_logic_vector(53 downto 0);
signal dbg_dqs : std_logic_vector(4 downto 0);
signal dbg_bit : std_logic_vector(8 downto 0);
signal rd_data_edge_detect_r : std_logic_vector(8 downto 0);
signal wl_po_fine_cnt : std_logic_vector(53 downto 0);
signal wl_po_coarse_cnt : std_logic_vector(26 downto 0);
signal dbg_calib_rd_data_offset_1 : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_calib_rd_data_offset_2 : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_data_offset : std_logic_vector(5 downto 0);
signal dbg_data_offset_1 : std_logic_vector(5 downto 0);
signal dbg_data_offset_2 : std_logic_vector(5 downto 0);
signal all_zeros : std_logic_vector((2*nCK_PER_CLK)-1 downto 0) := (others => '0');
signal ddr2_ila_basic_int : std_logic_vector(119 downto 0);
signal ddr2_ila_wrpath_int : std_logic_vector(390 downto 0);
signal ddr2_ila_rdpath_int : std_logic_vector(1023 downto 0);
signal dbg_prbs_final_dqs_tap_cnt_r_int : std_logic_vector(11 downto 0);
signal dbg_prbs_first_edge_taps_int : std_logic_vector(11 downto 0);
signal dbg_prbs_second_edge_taps_int : std_logic_vector(11 downto 0);
begin
--***************************************************************************
ui_clk <= clk;
ui_clk_sync_rst <= rst;
sys_clk_p <= '0';
sys_clk_n <= '0';
clk_ref_i <= '0';
init_calib_complete <= init_calib_complete_i;
clk_ref_in_use_sys_clk : if (REFCLK_TYPE = "USE_SYSTEM_CLOCK") generate
clk_ref_in <= mmcm_clk;
end generate;
clk_ref_in_others : if (REFCLK_TYPE /= "USE_SYSTEM_CLOCK") generate
clk_ref_in <= clk_ref_i;
end generate;
u_iodelay_ctrl : mig_7series_v2_3_iodelay_ctrl
generic map
(
TCQ => TCQ,
IODELAY_GRP0 => IODELAY_GRP0,
IODELAY_GRP1 => IODELAY_GRP1,
REFCLK_TYPE => REFCLK_TYPE,
SYSCLK_TYPE => SYSCLK_TYPE,
SYS_RST_PORT => SYS_RST_PORT,
RST_ACT_LOW => RST_ACT_LOW,
DIFF_TERM_REFCLK => DIFF_TERM_REFCLK,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
REF_CLK_MMCM_IODELAY_CTRL => REF_CLK_MMCM_IODELAY_CTRL
)
port map
(
-- Outputs
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
sys_rst_o => sys_rst_o,
clk_ref => clk_ref,
-- Inputs
clk_ref_p => clk_ref_p,
clk_ref_n => clk_ref_n,
clk_ref_i => clk_ref_in,
sys_rst => sys_rst
);
u_ddr2_clk_ibuf : mig_7series_v2_3_clk_ibuf
generic map
(
SYSCLK_TYPE => SYSCLK_TYPE,
DIFF_TERM_SYSCLK => DIFF_TERM_SYSCLK
)
port map
(
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_clk_i => sys_clk_i,
mmcm_clk => mmcm_clk
);
-- Temperature monitoring logic
temp_mon_enabled : if (TEMP_MON_EN = "ON") generate
u_tempmon : mig_7series_v2_3_tempmon
generic map
(
TCQ => TCQ,
TEMP_MON_CONTROL => TEMP_MON_CONTROL,
XADC_CLK_PERIOD => XADC_CLK_PERIOD,
tTEMPSAMPLE => tTEMPSAMPLE
)
port map
(
clk => clk,
xadc_clk => clk_ref(0),
rst => rst,
device_temp_i => device_temp_i,
device_temp => device_temp
);
end generate;
temp_mon_disabled : if (TEMP_MON_EN /= "ON") generate
device_temp <= (others => '0');
end generate;
u_ddr2_infrastructure : mig_7series_v2_3_infrastructure
generic map
(
TCQ => TCQ,
nCK_PER_CLK => nCK_PER_CLK,
CLKIN_PERIOD => CLKIN_PERIOD,
SYSCLK_TYPE => SYSCLK_TYPE,
CLKFBOUT_MULT => CLKFBOUT_MULT,
DIVCLK_DIVIDE => DIVCLK_DIVIDE,
CLKOUT0_PHASE => CLKOUT0_PHASE,
CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => CLKOUT3_DIVIDE,
MMCM_VCO => MMCM_VCO,
MMCM_MULT_F => MMCM_MULT_F,
MMCM_DIVCLK_DIVIDE => MMCM_DIVCLK_DIVIDE,
RST_ACT_LOW => RST_ACT_LOW,
tCK => tCK,
MEM_TYPE => DRAM_TYPE
)
port map
(
-- Outputs
rstdiv0 => rst,
clk => clk,
mem_refclk => mem_refclk,
freq_refclk => freq_refclk,
sync_pulse => sync_pulse,
psen => psen,
psincdec => psincdec,
mmcm_ps_clk => mmcm_ps_clk,
poc_sample_pd => poc_sample_pd,
iddr_rst => iddr_rst,
psdone => psdone,
auxout_clk => open,
ui_addn_clk_0 => open,
ui_addn_clk_1 => open,
ui_addn_clk_2 => open,
ui_addn_clk_3 => open,
ui_addn_clk_4 => open,
pll_locked => pll_locked,
mmcm_locked => open,
rst_phaser_ref => rst_phaser_ref,
-- Inputs
mmcm_clk => mmcm_clk,
sys_rst => sys_rst_o,
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
ref_dll_lock => ref_dll_lock
);
u_memc_ui_top_std : mig_7series_v2_3_memc_ui_top_std
generic map (
TCQ => TCQ,
ADDR_CMD_MODE => ADDR_CMD_MODE,
AL => AL,
PAYLOAD_WIDTH => PAYLOAD_WIDTH,
BANK_WIDTH => BANK_WIDTH,
BM_CNT_WIDTH => BM_CNT_WIDTH,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
CK_WIDTH => CK_WIDTH,
COL_WIDTH => COL_WIDTH,
CMD_PIPE_PLUS1 => CMD_PIPE_PLUS1,
CS_WIDTH => CS_WIDTH,
nCS_PER_RANK => nCS_PER_RANK,
CKE_WIDTH => CKE_WIDTH,
DATA_WIDTH => DATA_WIDTH,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DM_WIDTH => DM_WIDTH,
DQ_CNT_WIDTH => DQ_CNT_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
DRAM_WIDTH => DRAM_WIDTH,
ECC => ECC,
ECC_WIDTH => ECC_WIDTH,
ECC_TEST => ECC_TEST,
MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
REFCLK_FREQ => REFCLK_FREQ,
nAL => nAL,
nBANK_MACHS => nBANK_MACHS,
CKE_ODT_AUX => CKE_ODT_AUX,
nCK_PER_CLK => nCK_PER_CLK,
ORDERING => ORDERING,
OUTPUT_DRV => OUTPUT_DRV,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
DATA_IO_IDLE_PWRDWN => DATA_IO_IDLE_PWRDWN,
BANK_TYPE => BANK_TYPE,
DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
IODELAY_GRP0 => IODELAY_GRP0,
IODELAY_GRP1 => IODELAY_GRP1,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
CL => CL,
tCK => tCK,
tCKE => tCKE,
tFAW => tFAW,
tPRDI => tPRDI,
tRAS => tRAS,
tRCD => tRCD,
tREFI => tREFI,
tRFC => tRFC,
tRP => tRP,
tRRD => tRRD,
tRTP => tRTP,
tWTR => tWTR,
tZQI => tZQI,
tZQCS => tZQCS,
USER_REFRESH => USER_REFRESH,
TEMP_MON_EN => TEMP_MON_EN,
WRLVL => WRLVL,
DEBUG_PORT => DEBUG_PORT,
CAL_WIDTH => CAL_WIDTH,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
ODT_WIDTH => ODT_WIDTH,
ROW_WIDTH => ROW_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
APP_DATA_WIDTH => APP_DATA_WIDTH,
APP_MASK_WIDTH => APP_MASK_WIDTH,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
PHY_0_BITLANES => PHY_0_BITLANES,
PHY_1_BITLANES => PHY_1_BITLANES,
PHY_2_BITLANES => PHY_2_BITLANES,
CK_BYTE_MAP => CK_BYTE_MAP,
ADDR_MAP => ADDR_MAP,
BANK_MAP => BANK_MAP,
CAS_MAP => CAS_MAP,
CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
CKE_MAP => CKE_MAP,
ODT_MAP => ODT_MAP,
CS_MAP => CS_MAP,
PARITY_MAP => PARITY_MAP,
RAS_MAP => RAS_MAP,
WE_MAP => WE_MAP,
DQS_BYTE_MAP => DQS_BYTE_MAP,
DATA0_MAP => DATA0_MAP,
DATA1_MAP => DATA1_MAP,
DATA2_MAP => DATA2_MAP,
DATA3_MAP => DATA3_MAP,
DATA4_MAP => DATA4_MAP,
DATA5_MAP => DATA5_MAP,
DATA6_MAP => DATA6_MAP,
DATA7_MAP => DATA7_MAP,
DATA8_MAP => DATA8_MAP,
DATA9_MAP => DATA9_MAP,
DATA10_MAP => DATA10_MAP,
DATA11_MAP => DATA11_MAP,
DATA12_MAP => DATA12_MAP,
DATA13_MAP => DATA13_MAP,
DATA14_MAP => DATA14_MAP,
DATA15_MAP => DATA15_MAP,
DATA16_MAP => DATA16_MAP,
DATA17_MAP => DATA17_MAP,
MASK0_MAP => MASK0_MAP,
MASK1_MAP => MASK1_MAP,
CALIB_ROW_ADD => CALIB_ROW_ADD,
CALIB_COL_ADD => CALIB_COL_ADD,
CALIB_BA_ADD => CALIB_BA_ADD,
SLOT_0_CONFIG => SLOT_0_CONFIG,
SLOT_1_CONFIG => SLOT_1_CONFIG,
MEM_ADDR_ORDER => MEM_ADDR_ORDER,
STARVE_LIMIT => STARVE_LIMIT,
USE_CS_PORT => USE_CS_PORT,
USE_DM_PORT => USE_DM_PORT,
USE_ODT_PORT => USE_ODT_PORT,
IDELAY_ADJ => "OFF",
FINE_PER_BIT => "OFF",
CENTER_COMP_MODE => "OFF",
PI_VAL_ADJ => "OFF",
MASTER_PHY_CTL => PHY_CONTROL_MASTER_BANK,
TAPSPERKCLK => TAPSPERKCLK
)
port map (
clk => clk,
clk_ref => clk_ref,
mem_refclk => mem_refclk, --memory clock
freq_refclk => freq_refclk,
pll_lock => pll_locked,
sync_pulse => sync_pulse,
rst => rst,
rst_phaser_ref => rst_phaser_ref,
ref_dll_lock => ref_dll_lock,
iddr_rst => iddr_rst,
mmcm_ps_clk => mmcm_ps_clk,
poc_sample_pd => poc_sample_pd,
-- Memory interface ports
ddr_dq => ddr2_dq,
ddr_dqs_n => ddr2_dqs_n,
ddr_dqs => ddr2_dqs_p,
ddr_addr => ddr2_addr,
ddr_ba => ddr2_ba,
ddr_cas_n => ddr2_cas_n,
ddr_ck_n => ddr2_ck_n,
ddr_ck => ddr2_ck_p,
ddr_cke => ddr2_cke,
ddr_cs_n => ddr2_cs_n,
ddr_dm => ddr2_dm,
ddr_odt => ddr2_odt,
ddr_ras_n => ddr2_ras_n,
ddr_reset_n => ddr2_reset_n,
ddr_parity => ddr2_parity,
ddr_we_n => ddr2_we_n,
bank_mach_next => bank_mach_next,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_hi_pri => '0',
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren,
app_ecc_multiple_err => app_ecc_multiple_err,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => app_sr_req,
app_sr_active => app_sr_active,
app_ref_req => app_ref_req,
app_ref_ack => app_ref_ack,
app_zq_req => app_zq_req,
app_zq_ack => app_zq_ack,
app_raw_not_ecc => all_zeros,
app_correct_en_i => '1',
psen => psen,
psincdec => psincdec,
psdone => psdone,
device_temp => device_temp,
-- Debug logic ports
dbg_idel_up_all => dbg_idel_up_all,
dbg_idel_down_all => dbg_idel_down_all,
dbg_idel_up_cpt => dbg_idel_up_cpt,
dbg_idel_down_cpt => dbg_idel_down_cpt,
dbg_sel_idel_cpt => dbg_sel_idel_cpt,
dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
dbg_sel_pi_incdec => dbg_sel_pi_incdec,
dbg_sel_po_incdec => dbg_sel_po_incdec,
dbg_byte_sel => dbg_byte_sel,
dbg_pi_f_inc => dbg_pi_f_inc,
dbg_pi_f_dec => dbg_pi_f_dec,
dbg_po_f_inc => dbg_po_f_inc,
dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
dbg_po_f_dec => dbg_po_f_dec,
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
dbg_calib_top => dbg_calib_top,
dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
dbg_rd_data_offset => dbg_rd_data_offset,
dbg_phy_rdlvl => dbg_phy_rdlvl,
dbg_phy_wrcal => dbg_phy_wrcal,
dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
dbg_rddata => dbg_rddata,
dbg_rddata_valid => dbg_rddata_valid,
dbg_rdlvl_done => dbg_rdlvl_done,
dbg_rdlvl_err => dbg_rdlvl_err,
dbg_rdlvl_start => dbg_rdlvl_start,
dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
dbg_wrlvl_done => dbg_wrlvl_done,
dbg_wrlvl_err => dbg_wrlvl_err,
dbg_wrlvl_start => dbg_wrlvl_start,
dbg_phy_wrlvl => dbg_phy_wrlvl,
dbg_phy_init => dbg_phy_init,
dbg_prbs_rdlvl => dbg_prbs_rdlvl,
dbg_dqs_found_cal => dbg_dqs_found_cal,
dbg_pi_counter_read_val => dbg_pi_counter_read_val,
dbg_po_counter_read_val => dbg_po_counter_read_val,
dbg_pi_phaselock_start => dbg_pi_phaselock_start,
dbg_pi_phaselocked_done => dbg_pi_phaselocked_done,
dbg_pi_phaselock_err => dbg_pi_phaselock_err,
dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
dbg_pi_dqsfound_err => dbg_pi_dqsfound_err,
dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes,
dbg_calib_rd_data_offset_1 => dbg_calib_rd_data_offset_1,
dbg_calib_rd_data_offset_2 => dbg_calib_rd_data_offset_2,
dbg_data_offset => dbg_data_offset,
dbg_data_offset_1 => dbg_data_offset_1,
dbg_data_offset_2 => dbg_data_offset_2,
dbg_wrcal_start => dbg_wrcal_start,
dbg_wrcal_done => dbg_wrcal_done,
dbg_wrcal_err => dbg_wrcal_err,
dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done,
dbg_prbs_final_dqs_tap_cnt_r => dbg_prbs_final_dqs_tap_cnt_r_int,
dbg_prbs_first_edge_taps => dbg_prbs_first_edge_taps_int,
dbg_prbs_second_edge_taps => dbg_prbs_second_edge_taps_int,
init_calib_complete => init_calib_complete_i
);
--*********************************************************************
-- Resetting all RTL debug inputs as the debug ports are not enabled
--*********************************************************************
dbg_idel_down_all <= '0';
dbg_idel_down_cpt <= '0';
dbg_idel_up_all <= '0';
dbg_idel_up_cpt <= '0';
dbg_sel_all_idel_cpt <= '0';
dbg_sel_idel_cpt <= (others => '0');
dbg_byte_sel <= (others => '0');
dbg_sel_pi_incdec <= '0';
dbg_pi_f_inc <= '0';
dbg_pi_f_dec <= '0';
dbg_po_f_inc <= '0';
dbg_po_f_dec <= '0';
dbg_po_f_stg23_sel <= '0';
dbg_sel_po_incdec <= '0';
end architecture arch_ddr_mig;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_stack - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.STD_LOGIC_UNSIGNED;
entity befunge_stack is
generic(
stack_depth_pow : integer;
word_size : integer
);
port(
clk : in std_logic;
reset : in std_logic;
stack_0_o : out std_logic_vector(word_size-1 downto 0);
stack_1_o : out std_logic_vector(word_size-1 downto 0);
stack_i : in std_logic_vector(word_size-1 downto 0);
pop1 : in std_logic;
pop2 : in std_logic;
push : in std_logic;
swap : in std_logic;
en : in std_logic
);
end befunge_stack;
architecture pc_v1 of befunge_stack is
type stack_type is array ((2**stack_depth_pow)-1 downto 0) of std_logic_vector(word_size-1 downto 0);
signal stack : stack_type;
signal stack_ptr : Unsigned(stack_depth_pow-1 downto 0);
begin
stack_0 <= stack(stack_ptr);
stack_1 <= stack(stack_ptr-1);
process(reset,clk)
variable ptr_incr : integer range(-2 to 1);
begin
if(reset = '1') then
stack_0_o <= (others => '0');
stack_1_o <= (others => '0');
stack <= (others => (others => '0'));
else
if rising_edge(clk) then
if ( en = '1' ) then
if ( pop1 = "1" ) then
ptr_incr := ptr_incr - 1;
elsif ( pop2 = "1" ) then
ptr_incr := ptr_incr - 2;
elsif ( push = "1" ) then
ptr_incr := ptr_incr + 1;
stack(stack_ptr + ptr_incr) <= stack_i;
elsif (swap = "1" ) then
stack(stack_ptr) <= stack(stack_ptr - 1);
stack(stack_ptr - 1) <= stack(stack_ptr);
end if;
stack_ptr <= std_logic_vector(stack_ptr + ptr_incr);
stack_0_o <= stack(stack_ptr + ptr_incr);
stack_1_o <= stack(stack_ptr + ptr_incr - 1);
end if;
end if;
end if;
end process;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Package: Project specific configuration.
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------
-- This file was created from the template file:
--
-- <PoCRoot>/src/common/my_config.template.vhdl
--
-- and customized for:
--
-- ML506
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML506";
constant MY_DEVICE : string := "None";
constant MY_VERBOSE : boolean := true;
end my_config;
package body my_config is
end my_config;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Package: Project specific configuration.
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------
-- This file was created from the template file:
--
-- <PoCRoot>/src/common/my_config.template.vhdl
--
-- and customized for:
--
-- ML506
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML506";
constant MY_DEVICE : string := "None";
constant MY_VERBOSE : boolean := true;
end my_config;
package body my_config is
end my_config;
|
architecture rtl of fifo is
signal sig8 : record_type_3(element1(7 downto 0),element2(4 downto 0)(7 downto 0)
(elementA(7 downto 0)
,elementB(3 downto 0)
),element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),element5(elementE
(3 downto
0)
(6
downto 0)
,elementF(7 downto 0)
),element6(4 downto
0),element7(7 downto 0));
signal sig9 : t_data_struct(data(7 downto 0));
signal sig9 : t_data_struct(data(7 downto 0)
);
begin
end architecture rtl;
|
-- FT AHB RAM
constant CFG_FTAHBRAM_EN : integer := CONFIG_FTAHBRAM_ENABLE;
constant CFG_FTAHBRAM_SZ : integer := CONFIG_FTAHBRAM_SZ;
constant CFG_FTAHBRAM_ADDR : integer := 16#CONFIG_FTAHBRAM_START#;
constant CFG_FTAHBRAM_PIPE : integer := CONFIG_FTAHBRAM_PIPE;
constant CFG_FTAHBRAM_EDAC : integer := CONFIG_FTAHBRAM_EDAC;
constant CFG_FTAHBRAM_SCRU : integer := CONFIG_FTAHBRAM_AUTOSCRUB;
constant CFG_FTAHBRAM_ECNT : integer := CONFIG_FTAHBRAM_ERRORCNTR;
constant CFG_FTAHBRAM_EBIT : integer := CONFIG_FTAHBRAM_CNTBITS;
|
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2011 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: Sep 15, 2011
-- Design Name: FMC-IMAGEON
-- Module Name: fmc_imageon_vita_receiver.vhd
-- Project Name: FMC-IMAGEON
-- Target Devices: Virtex-6
-- Kintex-7, Zynq
-- Avnet Boards: FMC-IMAGEON
--
-- Tool versions: ISE 14.1
--
-- Description: FMC-IMAGEON VITA receiver interface.
--
-- Dependencies:
--
-- Revision: Sep 15, 2011: 1.00 Initial version:
-- - VITA SPI controller
-- Sep 22, 2011: 1.01 Added:
-- - ISERDES interface
-- Sep 28, 2011: 1.02 Added:
-- - sync channel decoder
-- - crc checker
-- - data remapper
-- Oct 20, 2011: 1.03 Modify:
-- - iserdes (use BUFR)
-- Oct 21, 2011: 1.04 Added:
-- - fpn prnu correction
-- Nov 03, 2011: 1.05 Added:
-- - trigger generator
-- Dec 19, 2011: 1.06 Modified:
-- - port to Kintex-7
-- Jan 12, 2012: 1.07 Added:
-- - new fsync output port
-- Modify:
-- - syncgen
-- Feb 06, 2012: 1.08 Modify:
-- - triggergenerator
-- (new version with debounce logic)
-- - new C_XSVI_DIRECT_OUTPUT option
-- Feb 22, 2012: 1.09 Modified
-- - port to Zynq
-- - new C_XSVI_USE_SYNCGEN option
-- May 13, 2012: 1.10 Optimize
-- - remove one layer of registers
-- May 28, 2012: 1.11 Modify
-- - host_triggen_cnt_update
-- (for simultaneous update of high/low values)
-- Jun 01, 2012: 1.12 Modify:
-- - Move syncgen after demux_fifo
-- - Increase size of demux_fifo
-- (to tolerate jitter in video timing from sensor)
-- - Add programmable delay on framestart for syncgen
-- Jul 31, 2012: 1.13 Modify:
-- - define clk200, clk, clk4x with SIGIS = CLK
-- - define reset with SIGIS = RST
-- - port to Spartan-6
--
------------------------------------------------------------------
------------------------------------------------------------------------------
-- fmc_imageon_vita_receiver.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: fmc_imageon_vita_receiver.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Sep 15 13:07:23 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library fmc_imageon_vita_receiver_v1_13_a;
use fmc_imageon_vita_receiver_v1_13_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH --
-- C_S_AXI_ADDR_WIDTH --
-- C_S_AXI_MIN_SIZE --
-- C_USE_WSTRB --
-- C_DPHASE_TIMEOUT --
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY --
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK --
-- S_AXI_ARESETN --
-- S_AXI_AWADDR --
-- S_AXI_AWVALID --
-- S_AXI_WDATA --
-- S_AXI_WSTRB --
-- S_AXI_WVALID --
-- S_AXI_BREADY --
-- S_AXI_ARADDR --
-- S_AXI_ARVALID --
-- S_AXI_RREADY --
-- S_AXI_ARREADY --
-- S_AXI_RDATA --
-- S_AXI_RRESP --
-- S_AXI_RVALID --
-- S_AXI_WREADY --
-- S_AXI_BRESP --
-- S_AXI_BVALID --
-- S_AXI_AWREADY --
------------------------------------------------------------------------------
entity fmc_imageon_vita_receiver is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_XSVI_DATA_WIDTH : integer := 10;
C_XSVI_DIRECT_OUTPUT : integer := 0;
C_XSVI_USE_SYNCGEN : integer := 1;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
clk200 : in std_logic;
clk : in std_logic;
clk4x : in std_logic;
reset : in std_logic;
oe : in std_logic;
-- I/O pins
io_vita_clk_pll : out std_logic;
io_vita_reset_n : out std_logic;
io_vita_spi_sclk : out std_logic;
io_vita_spi_ssel_n : out std_logic;
io_vita_spi_mosi : out std_logic;
io_vita_spi_miso : in std_logic;
io_vita_trigger : out std_logic_vector(2 downto 0);
io_vita_monitor : in std_logic_vector(1 downto 0);
io_vita_clk_out_p : in std_logic;
io_vita_clk_out_n : in std_logic;
io_vita_sync_p : in std_logic;
io_vita_sync_n : in std_logic;
io_vita_data_p : in std_logic_vector(7 downto 0);
io_vita_data_n : in std_logic_vector(7 downto 0);
-- Trigger Port
trigger1 : in std_logic;
-- Frame Sync Port
fsync : out std_logic;
-- XSVI Port
xsvi_vsync_o : out std_logic;
xsvi_hsync_o : out std_logic;
xsvi_vblank_o : out std_logic;
xsvi_hblank_o : out std_logic;
xsvi_active_video_o : out std_logic;
xsvi_video_data_o : out std_logic_vector((C_XSVI_DATA_WIDTH-1) downto 0);
-- Debug Ports
debug_host_o : out std_logic_vector(231 downto 0);
debug_spi_o : out std_logic_vector( 95 downto 0);
debug_iserdes_o : out std_logic_vector(229 downto 0);
debug_decoder_o : out std_logic_vector(186 downto 0);
debug_crc_o : out std_logic_vector( 87 downto 0);
debug_triggen_o : out std_logic_vector( 9 downto 0);
debug_video_o : out std_logic_vector( 31 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity fmc_imageon_vita_receiver;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of fmc_imageon_vita_receiver is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 64;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity fmc_imageon_vita_receiver_v1_13_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
C_XSVI_DATA_WIDTH => C_XSVI_DATA_WIDTH,
C_XSVI_DIRECT_OUTPUT => C_XSVI_DIRECT_OUTPUT,
C_XSVI_USE_SYNCGEN => C_XSVI_USE_SYNCGEN,
C_FAMILY => C_FAMILY,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
clk200 => clk200,
clk => clk,
clk4x => clk4x,
reset => reset,
oe => oe,
-- I/O pins
io_vita_clk_pll => io_vita_clk_pll,
io_vita_reset_n => io_vita_reset_n,
io_vita_spi_sclk => io_vita_spi_sclk,
io_vita_spi_ssel_n => io_vita_spi_ssel_n,
io_vita_spi_mosi => io_vita_spi_mosi,
io_vita_spi_miso => io_vita_spi_miso,
io_vita_trigger => io_vita_trigger,
io_vita_monitor => io_vita_monitor,
io_vita_clk_out_p => io_vita_clk_out_p,
io_vita_clk_out_n => io_vita_clk_out_n,
io_vita_sync_p => io_vita_sync_p,
io_vita_sync_n => io_vita_sync_n,
io_vita_data_p => io_vita_data_p,
io_vita_data_n => io_vita_data_n,
-- Trigger Port
trigger1 => trigger1,
-- Frame Sync Port
fsync => fsync,
-- XSVI Port
xsvi_vsync_o => xsvi_vsync_o,
xsvi_hsync_o => xsvi_hsync_o,
xsvi_vblank_o => xsvi_vblank_o,
xsvi_hblank_o => xsvi_hblank_o,
xsvi_active_video_o => xsvi_active_video_o,
xsvi_video_data_o => xsvi_video_data_o,
-- Debug Ports
debug_host_o => debug_host_o,
debug_spi_o => debug_spi_o,
debug_iserdes_o => debug_iserdes_o,
debug_decoder_o => debug_decoder_o,
debug_crc_o => debug_crc_o,
debug_triggen_o => debug_triggen_o,
debug_video_o => debug_video_o,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
USE work.avalon_adc128s102_interface_pkg.ALL;
USE work.adc128S102_pkg.ALL;
ENTITY avalon_adc128s102_interface_tb IS
END ENTITY avalon_adc128s102_interface_tb;
ARCHITECTURE sim OF avalon_adc128s102_interface_tb IS
CONSTANT main_period : TIME := 8 ns; -- 125MHz
CONSTANT unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := x"00616463"; --adc
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '1';
SIGNAL slv_avs_address : STD_LOGIC_VECTOR (c_adc128S102_address_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL sl_avs_read : STD_LOGIC:= '0';
SIGNAL sl_avs_write : STD_LOGIC:= '0';
SIGNAL slv_avs_write_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_read_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_byteenable : STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0) := (OTHERS =>'1');
SIGNAL sl_sclk : STD_LOGIC:= '0';
SIGNAL slv_Ss : STD_LOGIC:= '0';
SIGNAL sl_mosi : STD_LOGIC:= '0';
SIGNAL sl_miso : STD_LOGIC:= '0';
BEGIN
--create component
my_unit_under_test : avalon_adc128s102_interface
GENERIC MAP(
BASE_CLK => 33000000,
SCLK_FREQUENCY => 1000000,
unique_id => unique_id
)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
islv_avs_address => slv_avs_address,
isl_avs_read => sl_avs_read,
isl_avs_write => sl_avs_write,
islv_avs_write_data => slv_avs_write_data,
oslv_avs_read_data => slv_avs_read_data,
osl_sclk => sl_sclk,
oslv_Ss => slv_Ss,
osl_mosi => sl_mosi,
isl_miso => sl_miso,
islv_avs_byteenable => slv_avs_byteenable
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 100*main_period;
sl_reset_n <= '1';
WAIT FOR main_period/2;
--test id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address,c_adc128S102_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(c_adc128S102_interface_version,c_fLink_interface_version_length))
REPORT "Interface Version Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_interface_version_length+c_fLink_subtype_length-1 DOWNTO c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(c_adc128S102_subtype_id,c_fLink_subtype_length))
REPORT "Subtype ID Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_avs_data_width-1 DOWNTO c_fLink_interface_version_length+c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(c_fLink_analog_input_id,c_fLink_id_length))
REPORT "Type ID Missmatch" SEVERITY FAILURE;
--test mem size register register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address,c_adc128S102_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT to_integer(UNSIGNED(slv_avs_read_data)) = 4*INTEGER(2**c_adc128S102_address_width)
REPORT "Memory Size Error: "&INTEGER'IMAGE(4*INTEGER(2**NUMBER_OF_CHANNELS))&"/"&INTEGER'IMAGE(to_integer(UNSIGNED(slv_avs_read_data))) SEVERITY FAILURE;
--test unic id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address,c_adc128S102_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data = unique_id
REPORT "Unic Id Error" SEVERITY FAILURE;
--test number of channels register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address,c_adc128S102_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(NUMBER_OF_CHANNELS,c_fLink_interface_version_length))
REPORT "Number of Channels Error" SEVERITY FAILURE;
WAIT FOR 10000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim;
|
--Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_jtag_debug_module_sysclk is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sr : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal vs_udr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end entity Video_System_CPU_jtag_debug_module_sysclk;
architecture europa of Video_System_CPU_jtag_debug_module_sysclk is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
signal enable_action_strobe : STD_LOGIC;
signal internal_jdo1 : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal ir : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jxuir : STD_LOGIC;
signal sync2_udr : STD_LOGIC;
signal sync2_uir : STD_LOGIC;
signal sync_udr : STD_LOGIC;
signal sync_uir : STD_LOGIC;
signal unxunused_resetxx2 : STD_LOGIC;
signal unxunused_resetxx3 : STD_LOGIC;
signal update_jdo_strobe : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of jdo : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of sync2_udr : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103""";
attribute ALTERA_ATTRIBUTE of sync2_uir : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103""";
begin
unxunused_resetxx2 <= std_logic'('1');
the_altera_std_synchronizer2 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => clk,
din => vs_udr,
dout => sync_udr,
reset_n => unxunused_resetxx2
);
unxunused_resetxx3 <= std_logic'('1');
the_altera_std_synchronizer3 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => clk,
din => vs_uir,
dout => sync_uir,
reset_n => unxunused_resetxx3
);
process (clk)
begin
if clk'event and clk = '1' then
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr AND NOT sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir AND NOT sync2_uir;
end if;
end process;
take_action_ocimem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("00"))))) AND NOT internal_jdo1(35)) AND internal_jdo1(34);
take_no_action_ocimem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("00"))))) AND NOT internal_jdo1(35)) AND NOT internal_jdo1(34);
take_action_ocimem_b <= (enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("00"))))) AND internal_jdo1(35);
take_action_tracemem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("01"))))) AND NOT internal_jdo1(37)) AND internal_jdo1(36);
take_no_action_tracemem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("01"))))) AND NOT internal_jdo1(37)) AND NOT internal_jdo1(36);
take_action_tracemem_b <= (enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("01"))))) AND internal_jdo1(37);
take_action_break_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND NOT internal_jdo1(36)) AND internal_jdo1(37);
take_no_action_break_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND NOT internal_jdo1(36)) AND NOT internal_jdo1(37);
take_action_break_b <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND NOT internal_jdo1(35)) AND internal_jdo1(37);
take_no_action_break_b <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND NOT internal_jdo1(35)) AND NOT internal_jdo1(37);
take_action_break_c <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND internal_jdo1(35)) AND internal_jdo1(37);
take_no_action_break_c <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND internal_jdo1(35)) AND NOT internal_jdo1(37);
take_action_tracectrl <= (enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("11"))))) AND internal_jdo1(15);
process (clk)
begin
if clk'event and clk = '1' then
if std_logic'(jxuir) = '1' then
ir <= ir_in;
end if;
if std_logic'(update_jdo_strobe) = '1' then
internal_jdo1 <= sr;
end if;
end if;
end process;
--vhdl renameroo for output signals
jdo <= internal_jdo1;
end europa;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2239.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02239ent IS
END c07s02b06x00p01n01i02239ent;
ARCHITECTURE c07s02b06x00p01n01i02239arch OF c07s02b06x00p01n01i02239ent IS
BEGIN
TESTING: PROCESS
type BYTE is array(7 downto 0) of BIT;
variable BYTEV : BYTE;
variable k : integer;
BEGIN
k := BYTEV rem BYTEV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02239 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02239arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2239.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02239ent IS
END c07s02b06x00p01n01i02239ent;
ARCHITECTURE c07s02b06x00p01n01i02239arch OF c07s02b06x00p01n01i02239ent IS
BEGIN
TESTING: PROCESS
type BYTE is array(7 downto 0) of BIT;
variable BYTEV : BYTE;
variable k : integer;
BEGIN
k := BYTEV rem BYTEV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02239 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02239arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2239.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02239ent IS
END c07s02b06x00p01n01i02239ent;
ARCHITECTURE c07s02b06x00p01n01i02239arch OF c07s02b06x00p01n01i02239ent IS
BEGIN
TESTING: PROCESS
type BYTE is array(7 downto 0) of BIT;
variable BYTEV : BYTE;
variable k : integer;
BEGIN
k := BYTEV rem BYTEV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02239 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02239arch;
|
--------------------------------------------------------------------------------
-- Company: UMD ECE
-- Engineers: Benjamin Doiron
--
-- Create Date: 12:35:25 03/26/2014
-- Design Name: Data To Ascii
-- Module Name: data_to_ascii
-- Project Name: Risc Machine Project 1
-- Target Device: Spartan 3E Board
-- Tool versions: Xilinx 14.7
-- Description: This code takes in output data from the FPU and
-- begins the process of outputting it to screen. Data is sent through
-- and each grouping of hex data is read individually. Data is collected and
-- sent to the VGA as though it were keyboard data.
--
-- Currently this is in modification and will change drastically to suit
-- the needs of the lab.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: N/A
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity data_to_ascii is
Port (
clk : in STD_LOGIC;
IN_DATA : in STD_LOGIC_VECTOR (23 downto 0);
OUT_ASCII : out STD_LOGIC_VECTOR (7 downto 0);
debugoutput : out STD_LOGIC_VECTOR (7 downto 0)
);
end data_to_ascii;
architecture Behavioral of data_to_ascii is
signal counter: integer range 0 to 6;
signal datacode : STD_LOGIC_VECTOR(3 downto 0);
signal output : STD_LOGIC_VECTOR (7 downto 0);
begin
process(clk)
begin
if(clk'event and clk = '1') then
case counter is
when 0 => datacode <= IN_DATA (23 downto 20);
when 1 => datacode <= IN_DATA (19 downto 16);
when 2 => datacode <= IN_DATA (15 downto 12);
when 3 => datacode <= IN_DATA (11 downto 8);
when 4 => datacode <= IN_DATA ( 7 downto 4);
when others => datacode <= IN_DATA ( 3 downto 0);
end case;
case datacode is
when x"0" => output <= x"30";
when x"1" => output <= x"31";
when x"2" => output <= x"32";
when x"3" => output <= x"33";
when x"4" => output <= x"34";
when x"5" => output <= x"35";
when x"6" => output <= x"36";
when x"7" => output <= x"37";
when x"8" => output <= x"38";
when x"9" => output <= x"39";
when x"A" => output <= x"41";
when x"B" => output <= x"42";
when x"C" => output <= x"43";
when x"D" => output <= x"44";
when x"E" => output <= x"45";
when x"F" => output <= x"46";
when others => output <= x"00";
end case;
debugoutput <= output;
if (output > x"00") then
OUT_ASCII <= output;
end if;
if (counter > 4) then
counter <= counter + 1;
else
counter <= 0;
end if;
end if;
end process;
-- There needs to be something that prevents it from reading the same data over and over
-- maybe a flag saying when new dats is sent out?
-- Then maybe we could put the data into a buffer or something.
-- Right now there could be issues.
end Behavioral; |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.axistream_bfm_pkg.all;
use work.vvc_methods_pkg.all; -- shared_axistream_vvc_config
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--========================================================================================================================
entity axistream_vvc is
generic (
-- When true: This VVC is an AXI4 Stream master. Data is output from BFM.
-- When false: This VVC is an AXI4 Stream slave. Data is input to BFM.
GC_VVC_IS_MASTER : boolean;
GC_DATA_WIDTH : integer;
GC_USER_WIDTH : integer := 1;
-- (Note: STRB_WIDTH = DATA_WIDTH/8)
GC_ID_WIDTH : integer := 1;
GC_DEST_WIDTH : integer := 1;
GC_INSTANCE_IDX : natural;
GC_PACKETINFO_QUEUE_COUNT_MAX : natural := 1; -- Number of PacketInfo Queues, normally one per source VVC
GC_AXISTREAM_BFM_CONFIG : t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
clk : in std_logic;
axistream_vvc_if : inout t_axistream_if := init_axistream_if_signals(GC_VVC_IS_MASTER, GC_DATA_WIDTH, GC_USER_WIDTH, GC_ID_WIDTH, GC_DEST_WIDTH)
);
begin
-- Check the interface widths to assure that the interface was correctly set up
assert (axistream_vvc_if.tdata'length = GC_DATA_WIDTH) report "axistream_vvc_if.data'length =/ GC_DATA_WIDTH" severity failure;
end entity axistream_vvc;
--========================================================================================================================
--========================================================================================================================
architecture behave of axistream_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_axistream_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_axistream_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_axistream_transaction_info(GC_INSTANCE_IDX);
begin
--========================================================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--========================================================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_AXISTREAM_BFM_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--========================================================================================================================
--========================================================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--========================================================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after running or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command executor
-- - Fetch and execute the commands
--========================================================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_result : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Reset the transaction info for waveview
--transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
if v_cmd.operation = TRANSMIT or v_cmd.operation = RECEIVE or v_cmd.operation = EXPECT then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_command_is_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
log(ID_BFM, "Running : " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd) & ".", C_SCOPE, vvc_config.msg_id_panel);
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when TRANSMIT =>
check_value(GC_VVC_IS_MASTER, true, TB_ERROR, "Sanity check: Method call only makes sense for master (source) VVC", C_SCOPE, ID_NEVER);
-- Put in queue so that the monitor VVC knows what to expect
-- Needed when the sink is in Monitor Mode, as an alternative to calling lbusExpect() for each packet
transaction_info.numPacketsSent := transaction_info.numPacketsSent + 1;
-- Call the corresponding procedure in the BFM package.
axistream_transmit(
data_array => v_cmd.data_array(0 to v_cmd.data_array_length-1),
user_array => v_cmd.user_array(0 to v_cmd.user_array_length-1),
strb_array => v_cmd.strb_array(0 to v_cmd.strb_array_length-1),
id_array => v_cmd.id_array(0 to v_cmd.id_array_length-1),
dest_array => v_cmd.dest_array(0 to v_cmd.dest_array_length-1),
msg => format_msg(v_cmd),
clk => clk,
-- Using the non-record version to avoid fatal error in Modelsim: (SIGSEGV) Bad handle or reference
axistream_if_tdata => axistream_vvc_if.tdata,
axistream_if_tkeep => axistream_vvc_if.tkeep,
axistream_if_tuser => axistream_vvc_if.tuser,
axistream_if_tstrb => axistream_vvc_if.tstrb,
axistream_if_tid => axistream_vvc_if.tid,
axistream_if_tdest => axistream_vvc_if.tdest,
axistream_if_tvalid => axistream_vvc_if.tvalid,
axistream_if_tlast => axistream_vvc_if.tlast,
axistream_if_tready => axistream_vvc_if.tready,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when RECEIVE =>
axistream_receive(data_array => v_result.data_array,
data_length => v_result.data_length,
user_array => v_result.user_array,
strb_array => v_result.strb_array,
id_array => v_result.id_array,
dest_array => v_result.dest_array,
msg => format_msg(v_cmd),
clk => clk,
-- Using the non-record version to avoid fatal error in Questa: (SIGSEGV) Bad handle or reference
axistream_if_tdata => axistream_vvc_if.tdata,
axistream_if_tkeep => axistream_vvc_if.tkeep,
axistream_if_tuser => axistream_vvc_if.tuser,
axistream_if_tstrb => axistream_vvc_if.tstrb,
axistream_if_tid => axistream_vvc_if.tid,
axistream_if_tdest => axistream_vvc_if.tdest,
axistream_if_tvalid => axistream_vvc_if.tvalid,
axistream_if_tlast => axistream_vvc_if.tlast,
axistream_if_tready => axistream_vvc_if.tready,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result );
when EXPECT =>
-- Call the corresponding procedure in the BFM package.
axistream_expect(
exp_data_array => v_cmd.data_array(0 to v_cmd.data_array_length-1),
exp_user_array => v_cmd.user_array(0 to v_cmd.user_array_length-1),
exp_strb_array => v_cmd.strb_array(0 to v_cmd.strb_array_length-1),
exp_id_array => v_cmd.id_array(0 to v_cmd.id_array_length-1),
exp_dest_array => v_cmd.dest_array(0 to v_cmd.dest_array_length-1),
msg => format_msg(v_cmd),
clk => clk,
-- Using the non-record version to avoid fatal error in Questa: (SIGSEGV) Bad handle or reference
axistream_if_tdata => axistream_vvc_if.tdata,
axistream_if_tkeep => axistream_vvc_if.tkeep,
axistream_if_tuser => axistream_vvc_if.tuser,
axistream_if_tstrb => axistream_vvc_if.tstrb,
axistream_if_tid => axistream_vvc_if.tid,
axistream_if_tdest => axistream_vvc_if.tdest,
axistream_if_tvalid => axistream_vvc_if.tvalid,
axistream_if_tlast => axistream_vvc_if.tlast,
axistream_if_tready => axistream_vvc_if.tready,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--========================================================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--========================================================================================================================
end behave;
|
entity FIFO is
port (
I_INPUT : in integer;
O_OUTPUT : out integer
);
end entity FIFO;
entity FIFO is
port (
I_INPUT : in integer;
O_OUTPUT : out integer
);
end entity FIFO;
entity FIFO is
generic (
G_GENERIC : integer
);
port (
I_INPUT : in integer;
O_OUTPUT : out integer
);
end entity FIFO;
|
-------------------------------------------------------------------------------
-- $Id: master_attachment.vhd,v 1.13 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- Master Attachment - entity and architecture
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: master_attachment.vhd
--
-- Description: Master attachment for Xilinx OPB
--
-------------------------------------------------------------------------------
--
-- master_attachment.vhd
-- addr_load_and_incr.vhd
--
-------------------------------------------------------------------------------
-- Author: MLL
-- History:
-- MLL 05/09/01 -- First version
--
-- MLL 09/18/01 -- Changed construct from if-then to state machine
--
-- FLO 12/13/01
-- ^^^^^^
-- Fixed component declaration addr_load_and_incr.
-- ~~~~~~
--
-- FLO 1/2/02
-- ^^^^^^
-- Removed _gtd from signals.
-- ~~~~~~
-- FLO 5/2/02
-- ^^^^^^
-- Removed _gtd from signals.
-- ~~~~~~
--
-- FLO 5/14/02
-- ^^^^^^
-- Retained-state retry optimization.
-- ~~~~~~
-- FLO 06/24/02
-- ^^^^^^
-- Implemented dynamic byte-enable capability.
-- ~~~~~~
-- FLO 06/28/02
-- ^^^^^^
-- Moved the contents of mst_module.vhd into a block in this file.
-- ~~~~~~
-- FLO 09/24/02
-- ^^^^^^
-- Changed the implementation of signal DMA_Request_HasPriority
-- so that master arbitration has a least recently serviced
-- grant behavior. Previous to the change, one master could
-- lock out the other for as long as it immediately re-requested.
-- ~~~~~~
-- FLO 10/11/02
-- ^^^^^^
-- Added state and logic to remember the outgoing master address that
-- is destroyed by the act of release of the bus (see Note, below)
-- and to use the remembered "shadow" address when restarting transactions under
-- retained-state retry. Adds about 33 FF and 34 LUT.
--
-- Note: Destroyed by using the reset of the address counter as a
-- way of driving zero to the bus.)
-- ~~~~~~
-- FLO 11/06/02
-- ^^^^^^
-- Added signal retained_state_retry_active to the sensitivity list for
-- the state-machine combinatorial process.
-- ~~~~~~
-- FLO 11/19/02
-- ^^^^^^
-- Master read operations do not start until new signal SA2MA_PostedWrInh
-- is false.
-- ~~~~~~
-- FLO 11/19/02
-- ^^^^^^
-- Added generic C_MASTER_ARB_MODEL, which allows for user-parameterized
-- arbitration behavior when there are both DMA and IP masters. Supports
-- fair, DMA-priority and IP-priority modes.
-- ~~~~~~
-- FLO 11/26/02
-- ^^^^^^
-- Master read operations from the IP master do *not* wait until
-- SA2MA_PostedWrInh is false. (See first 11/19/02, above.)
-- ~~~~~~
-- FLO 11/26/02
-- ^^^^^^
-- - Toggle priority when retry is not handled as retained-state.
-- - Added handling when SA reports that a master write operation
-- has received a retry on the first IPIC read.
-- ~~~~~~
-- FLO 01/07/03
-- ^^^^^^
-- - Added one clock cycle of delay to Bus2IP_MstRdAck and Bus2IP_MstLastAck
-- for a burst master read. This change makes these two signals assert
-- on the same cycle that the corresponding IPIC posted write is
-- taking place. Note that this behavior is dependent on the slave
-- attachment implementation; any change to the slave attachment's
-- MA2SA_XferAck to Bus2IP_WrReq timing needs a corresponding adjustment
-- here.
-- ~~~~~~
-- FLO 02/21/03
-- ^^^^^^
-- - Fixed incompatibility with grant parking onto this master.
-- Details: Several places OPB_MnGrant was used under the assumption that
-- it would only assert when Mn_request was true. Under parking, this
-- assumption doesn't hold. The fix is to qualify OPB_MnGrant by
-- anding it with Mn_request to produce qualified grant signal
-- bus_mngrant_i. This qualified signal is used locally in the
-- master attachment and is passed as Bus_MnGrant to the slave attachment.
-- ~~~~~~
-- FLO 05/18/2003
-- ^^^^^^
-- Changed the ack_counter to automatically adjust its required range
-- from the C_MA2SA_NUM_WIDTH parameter. Previously this was hard-coded
-- for size 8 bursts.
-- ~~~~~~
-- FLO 05/21/2004
-- ^^^^^^
-- The signal XXX2Bus_MstBE is now available one cycle earlier so that it
-- will be valid when Mst_rd_starting_pulse pulses for one clock. This
-- fixes a problem where, if both DMA and IP masters are present,
-- the wrong MstBE values would be placed into the "BE FIFO" for
-- locally mastered read operations.
-- ~~~~~~
-- FLO 05/26/2004
-- ^^^^^^
-- Added signal SA2MA_TimeOut to the interface. Assertion of this new
-- signal will terminate a master transaction with Bus2IP_MstTimeOut.
-- ~~~~~~
-- FLO 05/26/2004
-- ^^^^^^
-- Drive the low-order two Mn_Abus bits to match the numerically lowest
-- Mn_BE bit that is asserted.
-- ~~~~~~
-- FLO 05/27/2004
-- ^^^^^^
-- Removal of an VHDL alias construct.
-- ~~~~~~
-- FLO 08/11/2004
-- ^^^^^^
-- Added ouput port MA2SA_RSRA (retained_state_retry_active).
-- ~~~~~~
-- FLO 09/24/2004
-- ^^^^^^
-- Changed from up to down counter for counting acks.
-- (Part of v2_00_i 1.1 -> 1.3)
-- ~~~~~~
-- FLO 09/24/2004
-- ^^^^^^
-- -Added signal SA2MA_BufOccMinus1.
-- -Implemented write of any read data to the OPB before responding with
-- Bus2IP_MstRetry if the retry is signaled via SA2MA_Retry.
-- -Distinguish "clean retry" (all data, which is partial, is written
-- before retry) and "dirty retry" (some data read from IPIC but not
-- written to OPB before retry. Use Bus2IP_MstLastAck asserted concurrently
-- with Bus2IP_MstRetry as the indication of clean retry.
-- -Using bus2ip_msttimeout_i to exit state
-- Wait_for_Rdrdy on the timeout event.
-- ~~~~~~
-- FLO 10/27/2004
-- ^^^^^^
-- - On locally mastered writes, mn_seqaddr gets asserted if and only if
-- multiple beats have been buffered.
-- ~~~~~~
-- LCW Nov 8, 2004 -- updated for NCSim
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."=";
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
use proc_common_v1_00_b.ld_arith_reg;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity master_attachment is
generic (
C_OPB_ABUS_WIDTH : integer; -- 32 bits
C_OPB_DBUS_WIDTH : integer; -- Only 32 bits is
--supported due to the fact the the DMA registers
--were only defined for a 32-bit bus
C_MA2SA_NUM_WIDTH : integer :=4; -- 4 bits
C_DMA_ONLY : boolean; -- No IP-Master function
C_IP_MSTR_ONLY : boolean; -- No DMA-Master function
--Only one of C_DMA_ONLY or C_IP_MSTR_ONLY can be true
C_MASTER_ARB_MODEL : integer := 0
-- 0:FAIR 1:DMA_PRIORITY 2:IP_PRIORITY
);
port(
Reset : in STD_LOGIC;
--OPB ports
OPB_Clk : in STD_LOGIC;
OPB_MnGrant : in STD_LOGIC;
OPB_XferAck : in STD_LOGIC;
OPB_ErrAck : in STD_LOGIC;
OPB_TimeOut : in STD_LOGIC;
OPB_Retry : in STD_LOGIC;
--Master Attachment to OPB ports
Mn_Request : out STD_LOGIC;
Mn_Select : out STD_LOGIC;
Mn_RNW : out STD_LOGIC;
Mn_SeqAddr : out STD_LOGIC;
Mn_BusLock : out STD_LOGIC;
Mn_BE : out STD_LOGIC_VECTOR(0 to C_OPB_DBUS_WIDTH/8-1);
Mn_ABus : out STD_LOGIC_VECTOR(0 to C_OPB_ABUS_WIDTH-1);
--Master Attachment to SA ports
Bus_MnGrant : out STD_LOGIC;
MA2SA_Select : out STD_LOGIC;
MA2SA_XferAck : out STD_LOGIC;
MA2SA_Retry : out STD_LOGIC;
MA2SA_RSRA : out STD_LOGIC;
MA2SA_Rd : out STD_LOGIC;
MA2SA_Num : out STD_LOGIC_VECTOR(0 to C_MA2SA_NUM_WIDTH-1);
SA2MA_RdRdy : in STD_LOGIC;
SA2MA_WrAck : in STD_LOGIC;
SA2MA_Retry : in STD_LOGIC;
SA2MA_Error : in STD_LOGIC;
SA2MA_FifoRd : in STD_LOGIC;
SA2MA_FifoWr : in STD_LOGIC;
SA2MA_FifoBu : in STD_LOGIC;
SA2MA_PostedWrInh : in STD_LOGIC;
SA2MA_TimeOut : in STD_LOGIC;
SA2MA_BufOccMinus1 : in STD_LOGIC_VECTOR(0 to 4);
--Master Attachment from IP ports
Mstr_Sel_ma : out STD_LOGIC;
--Master Attachment from IP ports
IP2Bus_Addr : in STD_LOGIC_VECTOR(0 to C_OPB_ABUS_WIDTH-1)
:= (others => '0');
IP2Bus_MstBE : in STD_LOGIC_VECTOR(0 to C_OPB_DBUS_WIDTH/8-1)
:= (others => '0');
IP2Bus_MstWrReq : in STD_LOGIC := '0';
IP2Bus_MstRdReq : in STD_LOGIC := '0';
IP2Bus_MstBurst : in STD_LOGIC := '0';
IP2Bus_MstBusLock : in STD_LOGIC := '0';
--Master Attachment to IP ports
Bus2IP_MstWrAck_ma : out STD_LOGIC;
Bus2IP_MstRdAck_ma : out STD_LOGIC;
Bus2IP_MstRetry : out STD_LOGIC;
Bus2IP_MstError : out STD_LOGIC;
Bus2IP_MstTimeOut : out STD_LOGIC;
Bus2IP_MstLastAck : out STD_LOGIC;
--Master Attachment from DMA ports
DMA2Bus_Addr : in STD_LOGIC_VECTOR(0 to C_OPB_ABUS_WIDTH-1)
:= (others => '0');
DMA2Bus_MstBE : in STD_LOGIC_VECTOR(0 to C_OPB_DBUS_WIDTH/8-1)
:= (others => '0');
DMA2Bus_MstWrReq : in STD_LOGIC := '0';
DMA2Bus_MstRdReq : in STD_LOGIC := '0';
DMA2Bus_MstNum : in STD_LOGIC_VECTOR(0 to C_MA2SA_NUM_WIDTH-1);
DMA2Bus_MstBurst : in STD_LOGIC := '0';
DMA2Bus_MstBusLock : in STD_LOGIC := '0'
);
end master_attachment;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of master_attachment is
constant ZEROES : std_logic_vector(0 to 256) := (others => '0');
constant RESET_ACTIVE: std_logic := '1';
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl_table : bo2sl_type := ('0', '1');
function bo2sl(b: boolean) return std_logic is
begin
return bo2sl_table(b);
end bo2sl;
constant RETAIN_ADDRESS_OVER_RETRY : boolean := not C_DMA_ONLY;
-- The dma_sg takes the responsibility of keeping the presented
-- master address up-to-date with successful bus transfers;
-- extra logic to maintain the address under retained-state-retry
-- operation can be ommitted if dma_sg is the only master.
constant FAIR : integer := 0;
constant DMA_PRIORITY : integer := 0;
constant IP_PRIORITY : integer := 0;
--signals
signal MA2SA_XferAck_i : std_logic;
signal Mst_SM_cs_EQ_Wait_state : std_logic;
signal Mst_SM_cs_EQ_Wait_For_Req : std_logic;
signal Bus2IP_MstLastAck_i : std_logic;
signal MA2SA_Num_i : std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1);
signal DMA_sel_IP_sel_not : std_logic;
signal DMA_sel_IP_sel_not_p1 : std_logic;
signal DMA_Request_HasPriority : std_logic;
signal Reset_withNotReqs : std_logic;
signal XXX2Bus_MstBurst : std_logic;
signal XXX2Bus_MstBusLock : std_logic;
signal XXX2Bus_MstRdReq : std_logic;
signal XXX2Bus_MstWrReq : std_logic;
signal XXX2Bus_RNW : std_logic;
signal XXX2Bus_MstBE : std_logic_vector(0 to C_OPB_DBUS_WIDTH/8-1);
signal xxx2bus_mstbe_fifo : std_logic_vector(0 to C_OPB_DBUS_WIDTH/8-1);
signal XXX2Bus_Addr : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal Xfer_in_progress : std_logic;
signal FDRE_CE : std_logic;
signal FDRE_Reset : std_logic;
signal FDRE_SeqAddr_BusLock_Reset: std_logic;
signal Incr_N_Load : std_logic;
signal FDRE_MA2SA_Rd_Reset : std_logic;
signal Get_off_OPB_nxt_clk : std_logic;
signal Clear_SeqAddr_BusLock : std_logic;
signal Mst_rd_starting_pulse : std_logic;
signal be_fifo_wr : std_logic;
signal ma2sa_rd_i : std_logic;
signal bus_mngrant_i : std_logic;
signal mn_request_i : std_logic;
signal be_fifo_bu : std_logic_vector(0 to 3 --ToDo, eventually from generics
) := "0000";
signal loadable_Bus_Addr : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal mn_abus_i : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal mn_abus_shadow : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal retained_state_retry_active : std_logic;
signal retained_state_retry_active_p1 : std_logic;
signal FDRE_CE_d1 : std_logic;
signal toggle_priority : std_logic;
signal sa2ma_bufocc_eq0 : std_logic;
signal sa2ma_bufocc_eq1 : std_logic;
signal ipic_rd_was_retried : std_logic;
signal all_buffered_data_written : std_logic;
signal ma2sa_rd_i_set : std_logic;
signal bus2ip_msttimeout_i : std_logic;
signal mn_seqaddr_cmb : std_logic;
signal multiple_beats : std_logic;
begin
--Combinatorial operations
Mstr_Sel_ma <= DMA_sel_IP_sel_not;
FDRE_CE <= bus_mngrant_i or MA2SA_XferAck_i;
MA2SA_XferAck <= MA2SA_XferAck_i;
Bus2IP_MstLastAck <= Bus2IP_MstLastAck_i;
sa2ma_bufocc_eq0 <= SA2MA_BufOccMinus1(0);
sa2ma_bufocc_eq1 <= bo2sl(SA2MA_BufOccMinus1(1 to 4) = "0000");
FDRE_Reset <= Get_off_OPB_nxt_clk or Reset_withNotReqs;
I_LUT4: LUT4
--Generate reset signal to force reset when master aborts request
generic map(
INIT => X"AAAE"
)
port map(
O => Reset_withNotReqs,
I0 => Reset,
I1 => Xfer_in_progress,
I2 => XXX2Bus_MstWrReq,
I3 => XXX2Bus_MstRdReq
);
Mn_ABus <= mn_abus_i;
I_Addr_ld_inc: entity opb_ipif_v2_00_h.addr_load_and_incr
--Instantiate module to load word address bus and increment when bursting
generic map(
C_BUS_WIDTH => C_OPB_ABUS_WIDTH-2
)
port map(
Bus_Clk => OPB_Clk,
FDRE_CE => FDRE_CE,
FDRE_Reset => FDRE_Reset,
Incr_N_Load => Incr_N_Load,
Bus_input => loadable_Bus_Addr(0 to C_OPB_ABUS_WIDTH-3),
Bus_output => mn_abus_i(0 to C_OPB_ABUS_WIDTH-3)
);
Mn_ABus_byte_bits_vector_Generate_0: for j in C_OPB_ABUS_WIDTH-2 to
C_OPB_ABUS_WIDTH-2 generate
--Instantiate FF to load high byte-lane bit in 32-bit bus
signal bit0 : std_logic;
signal X : std_logic_vector(0 to 3);
begin
X <= xxx2bus_mstbe_fifo;
-- Hand optimized expression for the high bit of the four byte-lane case.
-- True if the first bit of X, scanning from left to right, is 2 or 3.
bit0 <= ( not X(0) and not X(1) and X(3) )
or ( not X(0) and not X(1) and X(2) );
--
I_FDRE: FDRE
port map(
Q => mn_abus_i(j),
C => OPB_Clk,
CE => FDRE_CE,
D => bit0,
R => FDRE_Reset
);
end generate Mn_ABus_byte_bits_vector_Generate_0;
Mn_ABus_byte_bits_vector_Generate_1: for j in C_OPB_ABUS_WIDTH-1 to
C_OPB_ABUS_WIDTH-1 generate
--Instantiate FF to load low byte-lane bit in 32-bit bus
signal bit1 : std_logic;
signal X : std_logic_vector(0 to 3);
begin
X <= xxx2bus_mstbe_fifo;
-- Hand optimized expression for the low bit of the four byte-lane case.
-- True if the first bit of X, scanning from left to right, is 1 or 3.
bit1 <= ( not X(0) and X(1) )
or ( not X(0) and not X(2) and X(3) );
--
I_FDRE: FDRE
port map(
Q => mn_abus_i(j),
C => OPB_Clk,
CE => FDRE_CE,
D => bit1,
R => FDRE_Reset
);
end generate Mn_ABus_byte_bits_vector_Generate_1;
--------------------------------------------------------------------------------
-- The update clock cycle for the mn_abus_shadow is one clock after the
-- update of mn_abus. This timing relationship is established here.
--------------------------------------------------------------------------------
I_RDRE_CE_D1: FDE
port map(
Q => FDRE_CE_d1,
D => FDRE_CE,
C => OPB_Clk,
CE => '1'
);
--------------------------------------------------------------------------------
-- Register to shadow the Mn_ABus; can be used to restore the address under
-- retained-state retry. All changes are shadowed except the clear caused by
-- FDRE_Reset for the purpose of releasing opb_abus.
--------------------------------------------------------------------------------
INCLUDE_MN_ABUS_SHADOW: if RETAIN_ADDRESS_OVER_RETRY generate
MN_ABUS_SHADOW_GEN: for i in 0 to C_OPB_ABUS_WIDTH-1 generate
FDE_I: FDE
port map(
Q => mn_abus_shadow(i),
D => mn_abus_i(i),
C => OPB_Clk,
CE => FDRE_CE_d1
);
end generate;
end generate;
I_SeqAddr_BusLock_LUT2: LUT2
--Generate reset signal to force reset of Mn_SeqAddr and Mn_BusLock
generic map(
INIT => X"E"
)
port map(
O => FDRE_SeqAddr_BusLock_Reset,
I0 => FDRE_Reset,
I1 => Clear_SeqAddr_BusLock
);
I_FDRE_Mn_BusLock: FDRE
--Instantiate module to gate BusLock signal
port map(
Q => Mn_BusLock,
C => OPB_Clk,
CE => FDRE_CE,
D => XXX2Bus_MstBusLock,
R => FDRE_SeqAddr_BusLock_Reset
);
MULTIPLE_BEATS_PROC : process(OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
if Reset = '1' then
multiple_beats <= '0';
elsif SA2MA_RdRdy = '1' then
multiple_beats <= not sa2ma_bufocc_eq0
and not sa2ma_bufocc_eq1; -- Two or more
-- beats have been buffered for
-- transfer to the OPB.
end if;
end if;
end process;
mn_seqaddr_cmb <= XXX2Bus_MstBurst
and ( XXX2Bus_MstRdReq
or multiple_beats
);
I_FDRE_Mn_SeqAddr: FDRE
--Instantiate module to gate Sequential address signal
port map(
Q => Mn_SeqAddr,
C => OPB_Clk,
CE => FDRE_CE,
D => mn_seqaddr_cmb,
R => FDRE_SeqAddr_BusLock_Reset
);
Set_RNW_signal_PROCESS: process(XXX2Bus_MstRdReq)
--Process to set XXX2Bus_RNW
begin
if(XXX2Bus_MstRdReq = '1') then
XXX2Bus_RNW <= '1';
else
XXX2Bus_RNW <= '0';
end if;
end process Set_RNW_signal_PROCESS;
I_FDRE_Mn_RNW: FDRE
--Instantiate module to gate RNW signal
port map(
Q => Mn_RNW,
C => OPB_Clk,
CE => FDRE_CE,
D => XXX2Bus_RNW,
R => FDRE_Reset
);
Bit_Enable_vector_Generate: for j in 0 to C_OPB_DBUS_WIDTH/8-1 generate
--Instantiate modules to gate Byte enable signals
begin
I_FDRE_Mn_BE: FDRE
port map(
Q => Mn_BE(j),
C => OPB_Clk,
CE => FDRE_CE,
D => xxx2bus_mstbe_fifo(j),
R => FDRE_Reset
);
end generate Bit_Enable_vector_Generate;
MA2SA_RD_I_PROC : process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
if FDRE_MA2SA_Rd_Reset = '1' then ma2sa_rd_i <= '0';
elsif ma2sa_rd_i_set = '1' then ma2sa_rd_i <= '1';
else null;
end if;
end if;
end process;
MA2SA_Rd <= ma2sa_rd_i;
FDRE_MA2SA_Rd_Reset <= Reset_withNotReqs
or Bus2IP_MstLastAck_i
or Mst_SM_cs_EQ_Wait_state;
-- Instantiate the FIFO
be_fifo_wr <= SA2MA_FifoWr or Mst_rd_starting_pulse;
be_fifo_bu(0 to be_fifo_bu'length-2) <= (others => '0');
be_fifo_bu(be_fifo_bu'length-1) <= SA2MA_FifoBu;
--ToDo, eventually use a generic and generate to exclude
-- this fifo and associated logic when the system does not
-- use dynamic byte enables.
SLN_DBUS_FIFO: entity proc_common_v1_00_b.srl_fifo_rbu
generic map (
C_DWIDTH => C_OPB_DBUS_WIDTH/8,
C_DEPTH => 16
)
port map (
Clk => OPB_Clk,
Reset => Mst_SM_cs_EQ_Wait_state,
FIFO_Write => be_fifo_wr,
Data_In => XXX2Bus_MstBe,
FIFO_Read => SA2MA_FifoRd,
Data_Out => xxx2bus_mstbe_fifo,
FIFO_Full => open,
FIFO_Empty => open,
Addr => open,
Num_To_Reread => be_fifo_bu,
Underflow => open,
Overflow => open
);
Bus_MnGrant <= bus_mngrant_i;
Mn_Request <= mn_request_i;
--*************************************************
Include_IP_or_DMA_MUXing: if(not(C_DMA_ONLY) and not(C_IP_MSTR_ONLY)) generate
--Muxing of IP master or DMA master signals
XXX2Bus_MstRdReq <= ( DMA_sel_IP_sel_not and DMA2Bus_MstRdReq) or
(not DMA_sel_IP_sel_not and IP2Bus_MstRdReq);
XXX2Bus_MstWrReq <= ( DMA_sel_IP_sel_not and DMA2Bus_MstWrReq) or
(not DMA_sel_IP_sel_not and IP2Bus_MstWrReq);
XXX2Bus_MstBurst <= ( DMA_sel_IP_sel_not and DMA2Bus_MstBurst) or
(not DMA_sel_IP_sel_not and IP2Bus_MstBurst);
XXX2Bus_MstBusLock <= XXX2Bus_MstBurst or
( DMA_sel_IP_sel_not and DMA2Bus_MstBusLock) or
(not DMA_sel_IP_sel_not and IP2Bus_MstBusLock);
XXX2Bus_MstBE_vector_Generate: for j in 0 to C_OPB_DBUS_WIDTH/8-1 generate
begin
XXX2Bus_MstBE(j) <= DMA2Bus_MstBE(j) when (DMA_sel_IP_sel_not_p1) = '1'
else
IP2Bus_MstBE(j);
end generate XXX2Bus_MstBE_vector_Generate;
XXX2Bus_MstABus_vector_Generate: for j in 0 to
(C_OPB_ABUS_WIDTH-1) generate
begin
XXX2Bus_Addr(j) <= ( DMA_sel_IP_sel_not and DMA2Bus_Addr(j)) or
(not DMA_sel_IP_sel_not and IP2Bus_Addr(j));
end generate XXX2Bus_MstABus_vector_Generate;
end generate Include_IP_or_DMA_MUXing;
loadable_Bus_Addr <= mn_abus_shadow when RETAIN_ADDRESS_OVER_RETRY and
retained_state_retry_active='1'
else
XXX2Bus_Addr;
DMA_Master_Only: if(C_DMA_ONLY) generate
begin
XXX2Bus_MstRdReq <= DMA2Bus_MstRdReq;
XXX2Bus_MstWrReq <= DMA2Bus_MstWrReq;
XXX2Bus_Addr <= DMA2Bus_Addr;
XXX2Bus_MstBE <= DMA2Bus_MstBE;
XXX2Bus_MstBurst <= DMA2Bus_MstBurst;
XXX2Bus_MstBusLock <= DMA2Bus_MstBusLock or DMA2Bus_MstBurst;
end generate DMA_Master_Only;
IP_Master_Only: if(C_IP_MSTR_ONLY) generate
begin
XXX2Bus_MstRdReq <= IP2Bus_MstRdReq;
XXX2Bus_MstWrReq <= IP2Bus_MstWrReq;
XXX2Bus_Addr <= IP2Bus_Addr;
XXX2Bus_MstBE <= IP2Bus_MstBE;
XXX2Bus_MstBurst <= IP2Bus_MstBurst;
XXX2Bus_MstBusLock <= IP2Bus_MstBusLock or IP2Bus_MstBurst;
end generate IP_Master_Only;
Set_Value_of_MA2SA_Num_PROCESS: process(
DMA_sel_IP_sel_not, IP2Bus_MstBurst, DMA2Bus_MstNum
)
begin
if(DMA_sel_IP_sel_not = '0') then
MA2SA_Num_i <= (others => '0');
MA2SA_Num_i(MA2SA_Num'right-3) <= IP2Bus_MstBurst;
MA2SA_Num_i(MA2SA_Num'right ) <= not IP2Bus_MstBurst;
else
MA2SA_Num_i <= DMA2Bus_MstNum;
end if;
end process Set_Value_of_MA2SA_Num_PROCESS;
MA2SA_Num <= MA2SA_Num_i;
No_Arbiter_DMA_Only: if(C_DMA_ONLY) generate
--Fix DMA_sel_IP_sel_not if DMA only
begin
DMA_sel_IP_sel_not <= '1';
DMA_sel_IP_sel_not_p1 <= '1';
DMA_Request_HasPriority <= '1';
end generate No_Arbiter_DMA_Only;
No_Arbiter_IP_Master_Only: if(C_IP_MSTR_ONLY) generate
--Fix DMA_sel_IP_sel_not if IP master only
begin
DMA_sel_IP_sel_not <= '0';
DMA_sel_IP_sel_not_p1 <= '0';
DMA_Request_HasPriority <= '0';
end generate No_Arbiter_IP_Master_Only;
Insert_Arbiter: if(not(C_DMA_ONLY) and not(C_IP_MSTR_ONLY)) generate
Priority_Arbitration_PROCESS: process(OPB_Clk)
--Process to set priority for IP and DMA requests that occur at the
--same time
begin
if(OPB_Clk'event and OPB_Clk = '1') then
-----------------------------------------------------------------------
-- Keep track of priority.
-----------------------------------------------------------------------
if(Reset = RESET_ACTIVE) then
DMA_Request_HasPriority <= '0';
elsif toggle_priority = '1' then
DMA_Request_HasPriority <= not(DMA_Request_HasPriority);
elsif (C_MASTER_ARB_MODEL = DMA_PRIORITY) then
DMA_Request_HasPriority <= '1';
elsif (C_MASTER_ARB_MODEL = IP_PRIORITY) then
DMA_Request_HasPriority <= '0';
elsif (C_MASTER_ARB_MODEL = FAIR) and (Bus2IP_MstLastAck_i = '1') then
DMA_Request_HasPriority <= not(DMA_sel_IP_sel_not);
end if;
-----------------------------------------------------------------------
-- Master selection.
-----------------------------------------------------------------------
end if;
end process Priority_Arbitration_PROCESS;
DMA_sel_IP_sel_not_p1 <=
not bo2sl(C_MASTER_ARB_MODEL = IP_PRIORITY)
--
when (Reset = RESET_ACTIVE) else -- Reset condition
(DMA2Bus_MstWrReq or (DMA2Bus_MstRdReq and not SA2MA_PostedWrInh)) and
(DMA_Request_HasPriority or not (IP2Bus_MstWrReq or IP2Bus_MstRdReq))
-------------------------------------------------------------
-- Above, new value is true when
-- DMA requesting and either DMA has priority or IP not
-- requesting.
-------------------------------------------------------------
--
when (Mst_SM_cs_EQ_Wait_For_Req and -- Condition to compute new
(DMA2Bus_MstWrReq or DMA2Bus_MstRdReq or
IP2Bus_MstWrReq or IP2Bus_MstRdReq)
) = '1' else
DMA_sel_IP_sel_not; -- Otherwise, retain state
ARB_REG_PROC : process(OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
DMA_sel_IP_sel_not <= DMA_sel_IP_sel_not_p1;
end if;
end process;
end generate Insert_Arbiter;
FSM_AND_RELATED_LOGIC: block
constant RESET_ACTIVE: std_logic := '1';
--signals
signal Mn_Select_i : std_logic;
signal Mn_Select_p1 : std_logic;
signal Bus2IP_MstLastAck_i_p1: std_logic;
signal last_mstrd_burst_ack_d1 : std_logic;
signal Bus2IP_MstWrAck_ma_p1 : std_logic;
signal Bus2IP_MstRdAck_ma_p1 : std_logic;
signal Bus2IP_MstRdAck_ma_p1_d1: std_logic;
signal either_ack : std_logic;
signal acks_left : std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1);
signal acks_left_eq1 : std_logic;
signal acks_left_eq2 : std_logic;
signal acks_left_ld : std_logic;
signal Bus2IP_MstError_Flag : std_logic;
signal bus2ip_mstretry_i : std_logic;
signal bus2ip_mstretry_i_p1 : std_logic;
signal Mst_SM_cs_EQ_Wait_state_i : std_logic;
type Master_Attach_SMtype is (Wait_state,
Wait_For_Req,
Wait_for_RdRdy,
Mn_Req,
Burst_Count_Acks,
Check_Retry_Type
);
signal Mst_SM_cs, Mst_SM_ns : Master_Attach_SMtype;
begin
--Combinatorial operations
Incr_N_Load <= not bus_mngrant_i;
bus_mngrant_i <= OPB_MnGrant and mn_request_i;
MA2SA_XferAck_i <= OPB_XferAck and Mn_Select_i;
MA2SA_Retry <= OPB_Retry and Mn_Select_i;
MA2SA_RSRA <= retained_state_retry_active;
Mn_Select <= Mn_Select_i;
MA2SA_Select <= Mn_Select_i;
Mst_SM_cs_EQ_Wait_state <= Mst_SM_cs_EQ_Wait_state_i;
Bus2IP_MstError <= Bus2IP_MstError_Flag;
Get_off_OPB_nxt_clk <= not mn_select_p1;
-- State machine combinational process
Mst_SM: process (Mst_SM_cs, XXX2Bus_MstWrReq,
XXX2Bus_MstRdReq, SA2MA_RdRdy, OPB_TimeOut,
OPB_Retry, bus_mngrant_i, MA2SA_XferAck_i,
MA2SA_Num_i, Mn_Select_i,
bus2ip_msttimeout_i, Bus2IP_MstLastAck_i, Bus2IP_MstRetry_i,
DMA2Bus_MstRdReq, DMA2Bus_MstWrReq, SA2MA_PostedWrInh,
IP2Bus_MstRdReq, IP2Bus_MstWrReq, retained_state_retry_active,
SA2MA_TimeOut, acks_left_eq1, acks_left_eq2,
DMA_sel_IP_sel_not_p1,
ma2sa_rd_i, sa2ma_bufocc_eq0, sa2ma_bufocc_eq1, all_buffered_data_written)
begin
-- Set default values
Mst_SM_ns <= Mst_SM_cs;
mn_request_i <= '0';
mn_select_p1 <= '0';
Xfer_in_progress <= '1';
Mst_SM_cs_EQ_Wait_state_i <= '0';
Mst_SM_cs_EQ_Wait_For_Req <= '0';
Clear_SeqAddr_BusLock <= '0';
Mst_rd_starting_pulse <= '0';
retained_state_retry_active_p1 <= retained_state_retry_active;
toggle_priority <= '0';
acks_left_ld <= '0';
ma2sa_rd_i_set <= '0';
case Mst_SM_cs is
when Wait_state =>
Mst_SM_ns <= Wait_For_Req;
Clear_SeqAddr_BusLock <= '1';
Mst_SM_cs_EQ_Wait_state_i <= '1';
Xfer_in_progress <= '0';
retained_state_retry_active_p1 <= '0';
when Wait_For_Req =>
Mst_SM_cs_EQ_Wait_For_Req <= '1';
Xfer_in_progress <= '0';
if ((not DMA_sel_IP_sel_not_p1 and IP2Bus_MstWrReq) or
( DMA_sel_IP_sel_not_p1 and DMA2Bus_MstWrReq)) = '1' then
ma2sa_rd_i_set <= '1';
Mst_SM_ns <= Wait_for_RdRdy;
elsif ((not DMA_sel_IP_sel_not_p1 and IP2Bus_MstRdReq) or
( DMA_sel_IP_sel_not_p1 and (DMA2Bus_MstRdReq and
not SA2MA_PostedWrInh))
) = '1' then
-- DMA reads do not proceed until posted writes
-- can be accepted because the slave sets the rate
-- for this data, which can be at one per clock.
-- An IP master read proceeds without checking
-- posted write inhibit, so, the IP master read request
-- may occur only if IPIC posted writes will succeed and
-- such posted writes will occur without regard to the
-- state of the PostedWrInh signal.
Mst_rd_starting_pulse <= '1';
Mst_SM_ns <= Mn_Req;
end if;
when Wait_for_RdRdy =>
if(SA2MA_RdRdy and not sa2ma_bufocc_eq0) = '1' then
Mst_SM_ns <= Mn_Req;
elsif (bus2ip_mstretry_i or bus2ip_msttimeout_i) = '1' then
toggle_priority <= '1';
Mst_SM_ns <= Wait_state;
end if;
when Mn_Req =>
mn_request_i <= '1';
acks_left_ld <= not retained_state_retry_active;
if(bus_mngrant_i = '1') then
Mst_SM_ns <= Burst_Count_Acks;
mn_select_p1 <= '1';
end if; -- mn_request_i must deassert in response
-- to OPB_MnGrant to assure that bus_mngrant_i
-- is asserted for exactly one clock.
-- In this state bus_mngrant_i is asserted iff
-- OPB_MnGrant is asserted (since mn_request_i = '1').
when Check_Retry_Type =>
if (XXX2Bus_MstRdReq or XXX2Bus_MstWrReq)='1' then
Mst_SM_ns <= Mn_Req; -- Transaction continued.
retained_state_retry_active_p1 <= '1';
else
toggle_priority <= '1';
Mst_SM_ns <= Wait_state; -- Transaction aborted.
end if;
when Burst_Count_Acks =>
mn_select_p1 <= Mn_Select_i
and not ( ( MA2SA_XferAck_i -- End transaction
and (acks_left_eq1 or -- if done or ...
(ma2sa_rd_i and sa2ma_bufocc_eq0)
)
)
or OPB_Retry -- retry response or
or OPB_TimeOut -- timeout response.
);
if(bus2ip_mstretry_i = '1') then
if not (ma2sa_rd_i and all_buffered_data_written) = '1' then
Mst_SM_ns <= Check_Retry_Type;
else
toggle_priority <= '1';
Mst_SM_ns <= Wait_state;
end if;
elsif(bus2ip_msttimeout_i = '1') then
Mst_SM_ns <= Wait_state;
elsif(Bus2IP_MstLastAck_i = '1') then
Mst_SM_ns <= Wait_state;
end if;
if(MA2SA_XferAck_i = '1') then
if (acks_left_eq2 or (ma2sa_rd_i and sa2ma_bufocc_eq1)) = '1' then
Clear_SeqAddr_BusLock <= '1';
end if;
end if;
when others =>
Mst_SM_ns <= Wait_state;
end case;
end process Mst_SM;
Mst_SM_Reg: process (OPB_Clk)
begin
if (OPB_Clk'event and OPB_Clk = '1') then
if (Reset_withNotReqs = RESET_ACTIVE) then
Mst_SM_cs <= Wait_state;
else
Mst_SM_cs <= Mst_SM_ns;
end if;
retained_state_retry_active <= retained_state_retry_active_p1;
end if;
end process Mst_SM_Reg;
ms_select_REG: process (OPB_Clk)
begin
if (OPB_Clk'event and OPB_Clk = '1') then
if (Reset = RESET_ACTIVE) then
Mn_Select_i <= '0';
else
Mn_Select_i <= mn_select_p1;
end if;
end if;
end process ms_select_REG;
Register_ErrAck_Flag_PROCESS: process (OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE or Mst_SM_cs_EQ_Wait_state_i = '1') then
Bus2IP_MstError_Flag <= '0';
elsif((OPB_ErrAck = '1' and Mn_Select_i = '1') or
(SA2MA_Error = '1' and Xfer_in_progress = '1')) then
Bus2IP_MstError_Flag <= '1'; -- Flag error to be noted with LastAck
-- to local master
end if;
end if;
end process Register_ErrAck_Flag_PROCESS;
RETRY_HELP_PROC: process (OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if (bus2ip_mstretry_i_p1 and Bus2IP_MstLastAck_i_p1) = '1' or
(Reset = RESET_ACTIVE) then
-- As bus2ip_mstretry_i is set, ipic_rd_was_retried is cleared. This
-- makes bus2ip_mstretry_i a one-clock pulse when it is caused in part
-- by ipic_rd_was_retried.
ipic_rd_was_retried <= '0';
elsif (SA2MA_RdRdy) = '1' then
ipic_rd_was_retried <= SA2MA_Retry;
end if;
--
if (SA2MA_RdRdy) = '1' or (Reset = RESET_ACTIVE) then
all_buffered_data_written <= sa2ma_bufocc_eq0; -- If there is
-- no buffered data at RdRdy, then there is none to write.
elsif (sa2ma_bufocc_eq0 and MA2SA_XferAck_i) = '1' then -- This captures
-- the point at which all buffered data is written because the
-- buffer proper (fifo) is empty so the only word left is in
-- the output register, and it is being ack'ed.
all_buffered_data_written <= '1';
end if;
end if;
end process;
bus2ip_mstretry_i_p1 <= (OPB_Retry and Mn_Select_i) or
(ipic_rd_was_retried and all_buffered_data_written) or
(XXX2Bus_MstRdReq and SA2MA_Retry);
Register_OPB_Retry_PROCESS: process (OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE) then bus2ip_mstretry_i <= '0';
else bus2ip_mstretry_i <= bus2ip_mstretry_i_p1;
end if;
end if;
end process Register_OPB_Retry_PROCESS;
Bus2IP_MstRetry <= bus2ip_mstretry_i;
Register_Time_Out_PROCESS: process (OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE) then
bus2ip_msttimeout_i <= '0';
else
bus2ip_msttimeout_i <= (OPB_TimeOut and Mn_Select_i) or SA2MA_TimeOut;
end if;
end if;
end process Register_Time_Out_PROCESS;
Bus2IP_MstTimeOut <= bus2ip_msttimeout_i;
either_ack <= Bus2IP_MstRdAck_ma_p1 or Bus2IP_MstWrAck_ma_p1;
--
ACKS_LEFT_I : entity proc_common_v1_00_b.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => MA2SA_Num_i'length,
C_RESET_VALUE => ZEROES(0 to MA2SA_Num_i'length-1),
C_LD_WIDTH => MA2SA_Num_i'length,
C_AD_WIDTH => 1
)
port map (
CK => OPB_Clk,
RST => '0',
Q => acks_left,
LD => MA2SA_Num_i,
AD => "1",
LOAD => acks_left_ld,
OP => either_ack
);
--
acks_left_eq1 <= bo2sl(UNSIGNED(acks_left) = 1);
acks_left_eq2 <= bo2sl(UNSIGNED(acks_left) = 2);
Mst_Ack_COMB_PROCESS: process(XXX2Bus_MstRdReq, XXX2Bus_MstWrReq,
XXX2Bus_MstBurst,
SA2MA_WrAck, MA2SA_XferAck_i,
acks_left_eq1, acks_left_eq2, MA2SA_Num_i)
begin
Bus2IP_MstWrAck_ma_p1 <= '0';
Bus2IP_MstRdAck_ma_p1 <= '0';
if(XXX2Bus_MstRdReq = '1') then
if(XXX2Bus_MstBurst = '1') then --Fire and forget with Burst
Bus2IP_MstRdAck_ma_p1 <= MA2SA_XferAck_i;
else --Wait for local Write Ack
Bus2IP_MstRdAck_ma_p1 <= SA2MA_WrAck; --when single Xfer
end if;
elsif(XXX2Bus_MstWrReq = '1') then
Bus2IP_MstWrAck_ma_p1 <= MA2SA_XferAck_i;
end if;
end process Mst_Ack_COMB_PROCESS;
RD_BURST_ACK_DELAY_PROC : process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
Bus2IP_MstRdAck_ma_p1_d1 <= Bus2IP_MstRdAck_ma_p1;
last_mstrd_burst_ack_d1 <= XXX2Bus_MstRdReq and XXX2Bus_MstBurst and
MA2SA_XferAck_i and acks_left_eq1;
end if;
end process;
Bus2IP_MstLastAck_i_p1 <= last_mstrd_burst_ack_d1 -- When MstRd, burst
or ( XXX2Bus_MstRdReq
and not XXX2Bus_MstBurst
and SA2MA_WrAck -- When MstRd, ~burst
and acks_left_eq1)
or ( XXX2Bus_MstWrReq
and MA2SA_XferAck_i -- When MstWr
and acks_left_eq1)
or ( bus2ip_mstretry_i_p1 -- When retry
and ( ( XXX2Bus_MstWrReq
and all_buffered_data_written)
or ( XXX2Bus_MstRdReq
and SA2MA_Retry)));
-- Note, for retries Bus2IP_MstLastAck serves
-- as a qualifier. It is asserted iff
-- no data is "in limbo", i.e. all data that
-- has been read from the IPIC/OPB has
-- been written to the OPB/IPIC or that
-- any read data that has been discarded
-- is rereadable (aka idempotent,
-- non-destructive readable, pre-fetchable).
-- For loccally mastered writes,
-- (XXX2Bus_MstWrReq = '1'), Bus2IP_MstLastAck
-- is asserted iff buffered data has been
-- written.
-- For loccally mastered reads,
-- (XXX2Bus_MstRdReq = '1'), Bus2IP_MstLastAck
-- is always asserted even though the data read
-- from the OPB (and not accepted by the IPIC)
-- is discarded. The consequence is that any
-- OPB data read as the first part of a locally
-- mastered read operation must either be
-- re-readable or there must be a guarantee
-- that the IPIC will not refuse it by
-- replying with retry.
MSTLASTACK_REG_PROCESS: process(OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE) then --Synchronous Reset
Bus2IP_MstLastAck_i <= '0';
else
Bus2IP_MstLastAck_i <= Bus2IP_MstLastAck_i_p1;
end if;
end if;
end process;
Mst_Ack_REG_PROCESS: process(OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE) then --Synchronous Reset
Bus2IP_MstRdAck_ma <= '0';
Bus2IP_MstWrAck_ma <= '0';
else
Bus2IP_MstWrAck_ma <= Bus2IP_MstWrAck_ma_p1;
if (XXX2Bus_MstRdReq and XXX2Bus_MstBurst) = '0' then
Bus2IP_MstRdAck_ma <= Bus2IP_MstRdAck_ma_p1;
else
Bus2IP_MstRdAck_ma <= Bus2IP_MstRdAck_ma_p1_d1;
end if;
end if;
end if;
end process Mst_Ack_REG_PROCESS;
end block FSM_AND_RELATED_LOGIC;
---
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: master_attachment.vhd,v 1.13 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- Master Attachment - entity and architecture
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: master_attachment.vhd
--
-- Description: Master attachment for Xilinx OPB
--
-------------------------------------------------------------------------------
--
-- master_attachment.vhd
-- addr_load_and_incr.vhd
--
-------------------------------------------------------------------------------
-- Author: MLL
-- History:
-- MLL 05/09/01 -- First version
--
-- MLL 09/18/01 -- Changed construct from if-then to state machine
--
-- FLO 12/13/01
-- ^^^^^^
-- Fixed component declaration addr_load_and_incr.
-- ~~~~~~
--
-- FLO 1/2/02
-- ^^^^^^
-- Removed _gtd from signals.
-- ~~~~~~
-- FLO 5/2/02
-- ^^^^^^
-- Removed _gtd from signals.
-- ~~~~~~
--
-- FLO 5/14/02
-- ^^^^^^
-- Retained-state retry optimization.
-- ~~~~~~
-- FLO 06/24/02
-- ^^^^^^
-- Implemented dynamic byte-enable capability.
-- ~~~~~~
-- FLO 06/28/02
-- ^^^^^^
-- Moved the contents of mst_module.vhd into a block in this file.
-- ~~~~~~
-- FLO 09/24/02
-- ^^^^^^
-- Changed the implementation of signal DMA_Request_HasPriority
-- so that master arbitration has a least recently serviced
-- grant behavior. Previous to the change, one master could
-- lock out the other for as long as it immediately re-requested.
-- ~~~~~~
-- FLO 10/11/02
-- ^^^^^^
-- Added state and logic to remember the outgoing master address that
-- is destroyed by the act of release of the bus (see Note, below)
-- and to use the remembered "shadow" address when restarting transactions under
-- retained-state retry. Adds about 33 FF and 34 LUT.
--
-- Note: Destroyed by using the reset of the address counter as a
-- way of driving zero to the bus.)
-- ~~~~~~
-- FLO 11/06/02
-- ^^^^^^
-- Added signal retained_state_retry_active to the sensitivity list for
-- the state-machine combinatorial process.
-- ~~~~~~
-- FLO 11/19/02
-- ^^^^^^
-- Master read operations do not start until new signal SA2MA_PostedWrInh
-- is false.
-- ~~~~~~
-- FLO 11/19/02
-- ^^^^^^
-- Added generic C_MASTER_ARB_MODEL, which allows for user-parameterized
-- arbitration behavior when there are both DMA and IP masters. Supports
-- fair, DMA-priority and IP-priority modes.
-- ~~~~~~
-- FLO 11/26/02
-- ^^^^^^
-- Master read operations from the IP master do *not* wait until
-- SA2MA_PostedWrInh is false. (See first 11/19/02, above.)
-- ~~~~~~
-- FLO 11/26/02
-- ^^^^^^
-- - Toggle priority when retry is not handled as retained-state.
-- - Added handling when SA reports that a master write operation
-- has received a retry on the first IPIC read.
-- ~~~~~~
-- FLO 01/07/03
-- ^^^^^^
-- - Added one clock cycle of delay to Bus2IP_MstRdAck and Bus2IP_MstLastAck
-- for a burst master read. This change makes these two signals assert
-- on the same cycle that the corresponding IPIC posted write is
-- taking place. Note that this behavior is dependent on the slave
-- attachment implementation; any change to the slave attachment's
-- MA2SA_XferAck to Bus2IP_WrReq timing needs a corresponding adjustment
-- here.
-- ~~~~~~
-- FLO 02/21/03
-- ^^^^^^
-- - Fixed incompatibility with grant parking onto this master.
-- Details: Several places OPB_MnGrant was used under the assumption that
-- it would only assert when Mn_request was true. Under parking, this
-- assumption doesn't hold. The fix is to qualify OPB_MnGrant by
-- anding it with Mn_request to produce qualified grant signal
-- bus_mngrant_i. This qualified signal is used locally in the
-- master attachment and is passed as Bus_MnGrant to the slave attachment.
-- ~~~~~~
-- FLO 05/18/2003
-- ^^^^^^
-- Changed the ack_counter to automatically adjust its required range
-- from the C_MA2SA_NUM_WIDTH parameter. Previously this was hard-coded
-- for size 8 bursts.
-- ~~~~~~
-- FLO 05/21/2004
-- ^^^^^^
-- The signal XXX2Bus_MstBE is now available one cycle earlier so that it
-- will be valid when Mst_rd_starting_pulse pulses for one clock. This
-- fixes a problem where, if both DMA and IP masters are present,
-- the wrong MstBE values would be placed into the "BE FIFO" for
-- locally mastered read operations.
-- ~~~~~~
-- FLO 05/26/2004
-- ^^^^^^
-- Added signal SA2MA_TimeOut to the interface. Assertion of this new
-- signal will terminate a master transaction with Bus2IP_MstTimeOut.
-- ~~~~~~
-- FLO 05/26/2004
-- ^^^^^^
-- Drive the low-order two Mn_Abus bits to match the numerically lowest
-- Mn_BE bit that is asserted.
-- ~~~~~~
-- FLO 05/27/2004
-- ^^^^^^
-- Removal of an VHDL alias construct.
-- ~~~~~~
-- FLO 08/11/2004
-- ^^^^^^
-- Added ouput port MA2SA_RSRA (retained_state_retry_active).
-- ~~~~~~
-- FLO 09/24/2004
-- ^^^^^^
-- Changed from up to down counter for counting acks.
-- (Part of v2_00_i 1.1 -> 1.3)
-- ~~~~~~
-- FLO 09/24/2004
-- ^^^^^^
-- -Added signal SA2MA_BufOccMinus1.
-- -Implemented write of any read data to the OPB before responding with
-- Bus2IP_MstRetry if the retry is signaled via SA2MA_Retry.
-- -Distinguish "clean retry" (all data, which is partial, is written
-- before retry) and "dirty retry" (some data read from IPIC but not
-- written to OPB before retry. Use Bus2IP_MstLastAck asserted concurrently
-- with Bus2IP_MstRetry as the indication of clean retry.
-- -Using bus2ip_msttimeout_i to exit state
-- Wait_for_Rdrdy on the timeout event.
-- ~~~~~~
-- FLO 10/27/2004
-- ^^^^^^
-- - On locally mastered writes, mn_seqaddr gets asserted if and only if
-- multiple beats have been buffered.
-- ~~~~~~
-- LCW Nov 8, 2004 -- updated for NCSim
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."=";
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
use proc_common_v1_00_b.ld_arith_reg;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity master_attachment is
generic (
C_OPB_ABUS_WIDTH : integer; -- 32 bits
C_OPB_DBUS_WIDTH : integer; -- Only 32 bits is
--supported due to the fact the the DMA registers
--were only defined for a 32-bit bus
C_MA2SA_NUM_WIDTH : integer :=4; -- 4 bits
C_DMA_ONLY : boolean; -- No IP-Master function
C_IP_MSTR_ONLY : boolean; -- No DMA-Master function
--Only one of C_DMA_ONLY or C_IP_MSTR_ONLY can be true
C_MASTER_ARB_MODEL : integer := 0
-- 0:FAIR 1:DMA_PRIORITY 2:IP_PRIORITY
);
port(
Reset : in STD_LOGIC;
--OPB ports
OPB_Clk : in STD_LOGIC;
OPB_MnGrant : in STD_LOGIC;
OPB_XferAck : in STD_LOGIC;
OPB_ErrAck : in STD_LOGIC;
OPB_TimeOut : in STD_LOGIC;
OPB_Retry : in STD_LOGIC;
--Master Attachment to OPB ports
Mn_Request : out STD_LOGIC;
Mn_Select : out STD_LOGIC;
Mn_RNW : out STD_LOGIC;
Mn_SeqAddr : out STD_LOGIC;
Mn_BusLock : out STD_LOGIC;
Mn_BE : out STD_LOGIC_VECTOR(0 to C_OPB_DBUS_WIDTH/8-1);
Mn_ABus : out STD_LOGIC_VECTOR(0 to C_OPB_ABUS_WIDTH-1);
--Master Attachment to SA ports
Bus_MnGrant : out STD_LOGIC;
MA2SA_Select : out STD_LOGIC;
MA2SA_XferAck : out STD_LOGIC;
MA2SA_Retry : out STD_LOGIC;
MA2SA_RSRA : out STD_LOGIC;
MA2SA_Rd : out STD_LOGIC;
MA2SA_Num : out STD_LOGIC_VECTOR(0 to C_MA2SA_NUM_WIDTH-1);
SA2MA_RdRdy : in STD_LOGIC;
SA2MA_WrAck : in STD_LOGIC;
SA2MA_Retry : in STD_LOGIC;
SA2MA_Error : in STD_LOGIC;
SA2MA_FifoRd : in STD_LOGIC;
SA2MA_FifoWr : in STD_LOGIC;
SA2MA_FifoBu : in STD_LOGIC;
SA2MA_PostedWrInh : in STD_LOGIC;
SA2MA_TimeOut : in STD_LOGIC;
SA2MA_BufOccMinus1 : in STD_LOGIC_VECTOR(0 to 4);
--Master Attachment from IP ports
Mstr_Sel_ma : out STD_LOGIC;
--Master Attachment from IP ports
IP2Bus_Addr : in STD_LOGIC_VECTOR(0 to C_OPB_ABUS_WIDTH-1)
:= (others => '0');
IP2Bus_MstBE : in STD_LOGIC_VECTOR(0 to C_OPB_DBUS_WIDTH/8-1)
:= (others => '0');
IP2Bus_MstWrReq : in STD_LOGIC := '0';
IP2Bus_MstRdReq : in STD_LOGIC := '0';
IP2Bus_MstBurst : in STD_LOGIC := '0';
IP2Bus_MstBusLock : in STD_LOGIC := '0';
--Master Attachment to IP ports
Bus2IP_MstWrAck_ma : out STD_LOGIC;
Bus2IP_MstRdAck_ma : out STD_LOGIC;
Bus2IP_MstRetry : out STD_LOGIC;
Bus2IP_MstError : out STD_LOGIC;
Bus2IP_MstTimeOut : out STD_LOGIC;
Bus2IP_MstLastAck : out STD_LOGIC;
--Master Attachment from DMA ports
DMA2Bus_Addr : in STD_LOGIC_VECTOR(0 to C_OPB_ABUS_WIDTH-1)
:= (others => '0');
DMA2Bus_MstBE : in STD_LOGIC_VECTOR(0 to C_OPB_DBUS_WIDTH/8-1)
:= (others => '0');
DMA2Bus_MstWrReq : in STD_LOGIC := '0';
DMA2Bus_MstRdReq : in STD_LOGIC := '0';
DMA2Bus_MstNum : in STD_LOGIC_VECTOR(0 to C_MA2SA_NUM_WIDTH-1);
DMA2Bus_MstBurst : in STD_LOGIC := '0';
DMA2Bus_MstBusLock : in STD_LOGIC := '0'
);
end master_attachment;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of master_attachment is
constant ZEROES : std_logic_vector(0 to 256) := (others => '0');
constant RESET_ACTIVE: std_logic := '1';
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl_table : bo2sl_type := ('0', '1');
function bo2sl(b: boolean) return std_logic is
begin
return bo2sl_table(b);
end bo2sl;
constant RETAIN_ADDRESS_OVER_RETRY : boolean := not C_DMA_ONLY;
-- The dma_sg takes the responsibility of keeping the presented
-- master address up-to-date with successful bus transfers;
-- extra logic to maintain the address under retained-state-retry
-- operation can be ommitted if dma_sg is the only master.
constant FAIR : integer := 0;
constant DMA_PRIORITY : integer := 0;
constant IP_PRIORITY : integer := 0;
--signals
signal MA2SA_XferAck_i : std_logic;
signal Mst_SM_cs_EQ_Wait_state : std_logic;
signal Mst_SM_cs_EQ_Wait_For_Req : std_logic;
signal Bus2IP_MstLastAck_i : std_logic;
signal MA2SA_Num_i : std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1);
signal DMA_sel_IP_sel_not : std_logic;
signal DMA_sel_IP_sel_not_p1 : std_logic;
signal DMA_Request_HasPriority : std_logic;
signal Reset_withNotReqs : std_logic;
signal XXX2Bus_MstBurst : std_logic;
signal XXX2Bus_MstBusLock : std_logic;
signal XXX2Bus_MstRdReq : std_logic;
signal XXX2Bus_MstWrReq : std_logic;
signal XXX2Bus_RNW : std_logic;
signal XXX2Bus_MstBE : std_logic_vector(0 to C_OPB_DBUS_WIDTH/8-1);
signal xxx2bus_mstbe_fifo : std_logic_vector(0 to C_OPB_DBUS_WIDTH/8-1);
signal XXX2Bus_Addr : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal Xfer_in_progress : std_logic;
signal FDRE_CE : std_logic;
signal FDRE_Reset : std_logic;
signal FDRE_SeqAddr_BusLock_Reset: std_logic;
signal Incr_N_Load : std_logic;
signal FDRE_MA2SA_Rd_Reset : std_logic;
signal Get_off_OPB_nxt_clk : std_logic;
signal Clear_SeqAddr_BusLock : std_logic;
signal Mst_rd_starting_pulse : std_logic;
signal be_fifo_wr : std_logic;
signal ma2sa_rd_i : std_logic;
signal bus_mngrant_i : std_logic;
signal mn_request_i : std_logic;
signal be_fifo_bu : std_logic_vector(0 to 3 --ToDo, eventually from generics
) := "0000";
signal loadable_Bus_Addr : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal mn_abus_i : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal mn_abus_shadow : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal retained_state_retry_active : std_logic;
signal retained_state_retry_active_p1 : std_logic;
signal FDRE_CE_d1 : std_logic;
signal toggle_priority : std_logic;
signal sa2ma_bufocc_eq0 : std_logic;
signal sa2ma_bufocc_eq1 : std_logic;
signal ipic_rd_was_retried : std_logic;
signal all_buffered_data_written : std_logic;
signal ma2sa_rd_i_set : std_logic;
signal bus2ip_msttimeout_i : std_logic;
signal mn_seqaddr_cmb : std_logic;
signal multiple_beats : std_logic;
begin
--Combinatorial operations
Mstr_Sel_ma <= DMA_sel_IP_sel_not;
FDRE_CE <= bus_mngrant_i or MA2SA_XferAck_i;
MA2SA_XferAck <= MA2SA_XferAck_i;
Bus2IP_MstLastAck <= Bus2IP_MstLastAck_i;
sa2ma_bufocc_eq0 <= SA2MA_BufOccMinus1(0);
sa2ma_bufocc_eq1 <= bo2sl(SA2MA_BufOccMinus1(1 to 4) = "0000");
FDRE_Reset <= Get_off_OPB_nxt_clk or Reset_withNotReqs;
I_LUT4: LUT4
--Generate reset signal to force reset when master aborts request
generic map(
INIT => X"AAAE"
)
port map(
O => Reset_withNotReqs,
I0 => Reset,
I1 => Xfer_in_progress,
I2 => XXX2Bus_MstWrReq,
I3 => XXX2Bus_MstRdReq
);
Mn_ABus <= mn_abus_i;
I_Addr_ld_inc: entity opb_ipif_v2_00_h.addr_load_and_incr
--Instantiate module to load word address bus and increment when bursting
generic map(
C_BUS_WIDTH => C_OPB_ABUS_WIDTH-2
)
port map(
Bus_Clk => OPB_Clk,
FDRE_CE => FDRE_CE,
FDRE_Reset => FDRE_Reset,
Incr_N_Load => Incr_N_Load,
Bus_input => loadable_Bus_Addr(0 to C_OPB_ABUS_WIDTH-3),
Bus_output => mn_abus_i(0 to C_OPB_ABUS_WIDTH-3)
);
Mn_ABus_byte_bits_vector_Generate_0: for j in C_OPB_ABUS_WIDTH-2 to
C_OPB_ABUS_WIDTH-2 generate
--Instantiate FF to load high byte-lane bit in 32-bit bus
signal bit0 : std_logic;
signal X : std_logic_vector(0 to 3);
begin
X <= xxx2bus_mstbe_fifo;
-- Hand optimized expression for the high bit of the four byte-lane case.
-- True if the first bit of X, scanning from left to right, is 2 or 3.
bit0 <= ( not X(0) and not X(1) and X(3) )
or ( not X(0) and not X(1) and X(2) );
--
I_FDRE: FDRE
port map(
Q => mn_abus_i(j),
C => OPB_Clk,
CE => FDRE_CE,
D => bit0,
R => FDRE_Reset
);
end generate Mn_ABus_byte_bits_vector_Generate_0;
Mn_ABus_byte_bits_vector_Generate_1: for j in C_OPB_ABUS_WIDTH-1 to
C_OPB_ABUS_WIDTH-1 generate
--Instantiate FF to load low byte-lane bit in 32-bit bus
signal bit1 : std_logic;
signal X : std_logic_vector(0 to 3);
begin
X <= xxx2bus_mstbe_fifo;
-- Hand optimized expression for the low bit of the four byte-lane case.
-- True if the first bit of X, scanning from left to right, is 1 or 3.
bit1 <= ( not X(0) and X(1) )
or ( not X(0) and not X(2) and X(3) );
--
I_FDRE: FDRE
port map(
Q => mn_abus_i(j),
C => OPB_Clk,
CE => FDRE_CE,
D => bit1,
R => FDRE_Reset
);
end generate Mn_ABus_byte_bits_vector_Generate_1;
--------------------------------------------------------------------------------
-- The update clock cycle for the mn_abus_shadow is one clock after the
-- update of mn_abus. This timing relationship is established here.
--------------------------------------------------------------------------------
I_RDRE_CE_D1: FDE
port map(
Q => FDRE_CE_d1,
D => FDRE_CE,
C => OPB_Clk,
CE => '1'
);
--------------------------------------------------------------------------------
-- Register to shadow the Mn_ABus; can be used to restore the address under
-- retained-state retry. All changes are shadowed except the clear caused by
-- FDRE_Reset for the purpose of releasing opb_abus.
--------------------------------------------------------------------------------
INCLUDE_MN_ABUS_SHADOW: if RETAIN_ADDRESS_OVER_RETRY generate
MN_ABUS_SHADOW_GEN: for i in 0 to C_OPB_ABUS_WIDTH-1 generate
FDE_I: FDE
port map(
Q => mn_abus_shadow(i),
D => mn_abus_i(i),
C => OPB_Clk,
CE => FDRE_CE_d1
);
end generate;
end generate;
I_SeqAddr_BusLock_LUT2: LUT2
--Generate reset signal to force reset of Mn_SeqAddr and Mn_BusLock
generic map(
INIT => X"E"
)
port map(
O => FDRE_SeqAddr_BusLock_Reset,
I0 => FDRE_Reset,
I1 => Clear_SeqAddr_BusLock
);
I_FDRE_Mn_BusLock: FDRE
--Instantiate module to gate BusLock signal
port map(
Q => Mn_BusLock,
C => OPB_Clk,
CE => FDRE_CE,
D => XXX2Bus_MstBusLock,
R => FDRE_SeqAddr_BusLock_Reset
);
MULTIPLE_BEATS_PROC : process(OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
if Reset = '1' then
multiple_beats <= '0';
elsif SA2MA_RdRdy = '1' then
multiple_beats <= not sa2ma_bufocc_eq0
and not sa2ma_bufocc_eq1; -- Two or more
-- beats have been buffered for
-- transfer to the OPB.
end if;
end if;
end process;
mn_seqaddr_cmb <= XXX2Bus_MstBurst
and ( XXX2Bus_MstRdReq
or multiple_beats
);
I_FDRE_Mn_SeqAddr: FDRE
--Instantiate module to gate Sequential address signal
port map(
Q => Mn_SeqAddr,
C => OPB_Clk,
CE => FDRE_CE,
D => mn_seqaddr_cmb,
R => FDRE_SeqAddr_BusLock_Reset
);
Set_RNW_signal_PROCESS: process(XXX2Bus_MstRdReq)
--Process to set XXX2Bus_RNW
begin
if(XXX2Bus_MstRdReq = '1') then
XXX2Bus_RNW <= '1';
else
XXX2Bus_RNW <= '0';
end if;
end process Set_RNW_signal_PROCESS;
I_FDRE_Mn_RNW: FDRE
--Instantiate module to gate RNW signal
port map(
Q => Mn_RNW,
C => OPB_Clk,
CE => FDRE_CE,
D => XXX2Bus_RNW,
R => FDRE_Reset
);
Bit_Enable_vector_Generate: for j in 0 to C_OPB_DBUS_WIDTH/8-1 generate
--Instantiate modules to gate Byte enable signals
begin
I_FDRE_Mn_BE: FDRE
port map(
Q => Mn_BE(j),
C => OPB_Clk,
CE => FDRE_CE,
D => xxx2bus_mstbe_fifo(j),
R => FDRE_Reset
);
end generate Bit_Enable_vector_Generate;
MA2SA_RD_I_PROC : process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
if FDRE_MA2SA_Rd_Reset = '1' then ma2sa_rd_i <= '0';
elsif ma2sa_rd_i_set = '1' then ma2sa_rd_i <= '1';
else null;
end if;
end if;
end process;
MA2SA_Rd <= ma2sa_rd_i;
FDRE_MA2SA_Rd_Reset <= Reset_withNotReqs
or Bus2IP_MstLastAck_i
or Mst_SM_cs_EQ_Wait_state;
-- Instantiate the FIFO
be_fifo_wr <= SA2MA_FifoWr or Mst_rd_starting_pulse;
be_fifo_bu(0 to be_fifo_bu'length-2) <= (others => '0');
be_fifo_bu(be_fifo_bu'length-1) <= SA2MA_FifoBu;
--ToDo, eventually use a generic and generate to exclude
-- this fifo and associated logic when the system does not
-- use dynamic byte enables.
SLN_DBUS_FIFO: entity proc_common_v1_00_b.srl_fifo_rbu
generic map (
C_DWIDTH => C_OPB_DBUS_WIDTH/8,
C_DEPTH => 16
)
port map (
Clk => OPB_Clk,
Reset => Mst_SM_cs_EQ_Wait_state,
FIFO_Write => be_fifo_wr,
Data_In => XXX2Bus_MstBe,
FIFO_Read => SA2MA_FifoRd,
Data_Out => xxx2bus_mstbe_fifo,
FIFO_Full => open,
FIFO_Empty => open,
Addr => open,
Num_To_Reread => be_fifo_bu,
Underflow => open,
Overflow => open
);
Bus_MnGrant <= bus_mngrant_i;
Mn_Request <= mn_request_i;
--*************************************************
Include_IP_or_DMA_MUXing: if(not(C_DMA_ONLY) and not(C_IP_MSTR_ONLY)) generate
--Muxing of IP master or DMA master signals
XXX2Bus_MstRdReq <= ( DMA_sel_IP_sel_not and DMA2Bus_MstRdReq) or
(not DMA_sel_IP_sel_not and IP2Bus_MstRdReq);
XXX2Bus_MstWrReq <= ( DMA_sel_IP_sel_not and DMA2Bus_MstWrReq) or
(not DMA_sel_IP_sel_not and IP2Bus_MstWrReq);
XXX2Bus_MstBurst <= ( DMA_sel_IP_sel_not and DMA2Bus_MstBurst) or
(not DMA_sel_IP_sel_not and IP2Bus_MstBurst);
XXX2Bus_MstBusLock <= XXX2Bus_MstBurst or
( DMA_sel_IP_sel_not and DMA2Bus_MstBusLock) or
(not DMA_sel_IP_sel_not and IP2Bus_MstBusLock);
XXX2Bus_MstBE_vector_Generate: for j in 0 to C_OPB_DBUS_WIDTH/8-1 generate
begin
XXX2Bus_MstBE(j) <= DMA2Bus_MstBE(j) when (DMA_sel_IP_sel_not_p1) = '1'
else
IP2Bus_MstBE(j);
end generate XXX2Bus_MstBE_vector_Generate;
XXX2Bus_MstABus_vector_Generate: for j in 0 to
(C_OPB_ABUS_WIDTH-1) generate
begin
XXX2Bus_Addr(j) <= ( DMA_sel_IP_sel_not and DMA2Bus_Addr(j)) or
(not DMA_sel_IP_sel_not and IP2Bus_Addr(j));
end generate XXX2Bus_MstABus_vector_Generate;
end generate Include_IP_or_DMA_MUXing;
loadable_Bus_Addr <= mn_abus_shadow when RETAIN_ADDRESS_OVER_RETRY and
retained_state_retry_active='1'
else
XXX2Bus_Addr;
DMA_Master_Only: if(C_DMA_ONLY) generate
begin
XXX2Bus_MstRdReq <= DMA2Bus_MstRdReq;
XXX2Bus_MstWrReq <= DMA2Bus_MstWrReq;
XXX2Bus_Addr <= DMA2Bus_Addr;
XXX2Bus_MstBE <= DMA2Bus_MstBE;
XXX2Bus_MstBurst <= DMA2Bus_MstBurst;
XXX2Bus_MstBusLock <= DMA2Bus_MstBusLock or DMA2Bus_MstBurst;
end generate DMA_Master_Only;
IP_Master_Only: if(C_IP_MSTR_ONLY) generate
begin
XXX2Bus_MstRdReq <= IP2Bus_MstRdReq;
XXX2Bus_MstWrReq <= IP2Bus_MstWrReq;
XXX2Bus_Addr <= IP2Bus_Addr;
XXX2Bus_MstBE <= IP2Bus_MstBE;
XXX2Bus_MstBurst <= IP2Bus_MstBurst;
XXX2Bus_MstBusLock <= IP2Bus_MstBusLock or IP2Bus_MstBurst;
end generate IP_Master_Only;
Set_Value_of_MA2SA_Num_PROCESS: process(
DMA_sel_IP_sel_not, IP2Bus_MstBurst, DMA2Bus_MstNum
)
begin
if(DMA_sel_IP_sel_not = '0') then
MA2SA_Num_i <= (others => '0');
MA2SA_Num_i(MA2SA_Num'right-3) <= IP2Bus_MstBurst;
MA2SA_Num_i(MA2SA_Num'right ) <= not IP2Bus_MstBurst;
else
MA2SA_Num_i <= DMA2Bus_MstNum;
end if;
end process Set_Value_of_MA2SA_Num_PROCESS;
MA2SA_Num <= MA2SA_Num_i;
No_Arbiter_DMA_Only: if(C_DMA_ONLY) generate
--Fix DMA_sel_IP_sel_not if DMA only
begin
DMA_sel_IP_sel_not <= '1';
DMA_sel_IP_sel_not_p1 <= '1';
DMA_Request_HasPriority <= '1';
end generate No_Arbiter_DMA_Only;
No_Arbiter_IP_Master_Only: if(C_IP_MSTR_ONLY) generate
--Fix DMA_sel_IP_sel_not if IP master only
begin
DMA_sel_IP_sel_not <= '0';
DMA_sel_IP_sel_not_p1 <= '0';
DMA_Request_HasPriority <= '0';
end generate No_Arbiter_IP_Master_Only;
Insert_Arbiter: if(not(C_DMA_ONLY) and not(C_IP_MSTR_ONLY)) generate
Priority_Arbitration_PROCESS: process(OPB_Clk)
--Process to set priority for IP and DMA requests that occur at the
--same time
begin
if(OPB_Clk'event and OPB_Clk = '1') then
-----------------------------------------------------------------------
-- Keep track of priority.
-----------------------------------------------------------------------
if(Reset = RESET_ACTIVE) then
DMA_Request_HasPriority <= '0';
elsif toggle_priority = '1' then
DMA_Request_HasPriority <= not(DMA_Request_HasPriority);
elsif (C_MASTER_ARB_MODEL = DMA_PRIORITY) then
DMA_Request_HasPriority <= '1';
elsif (C_MASTER_ARB_MODEL = IP_PRIORITY) then
DMA_Request_HasPriority <= '0';
elsif (C_MASTER_ARB_MODEL = FAIR) and (Bus2IP_MstLastAck_i = '1') then
DMA_Request_HasPriority <= not(DMA_sel_IP_sel_not);
end if;
-----------------------------------------------------------------------
-- Master selection.
-----------------------------------------------------------------------
end if;
end process Priority_Arbitration_PROCESS;
DMA_sel_IP_sel_not_p1 <=
not bo2sl(C_MASTER_ARB_MODEL = IP_PRIORITY)
--
when (Reset = RESET_ACTIVE) else -- Reset condition
(DMA2Bus_MstWrReq or (DMA2Bus_MstRdReq and not SA2MA_PostedWrInh)) and
(DMA_Request_HasPriority or not (IP2Bus_MstWrReq or IP2Bus_MstRdReq))
-------------------------------------------------------------
-- Above, new value is true when
-- DMA requesting and either DMA has priority or IP not
-- requesting.
-------------------------------------------------------------
--
when (Mst_SM_cs_EQ_Wait_For_Req and -- Condition to compute new
(DMA2Bus_MstWrReq or DMA2Bus_MstRdReq or
IP2Bus_MstWrReq or IP2Bus_MstRdReq)
) = '1' else
DMA_sel_IP_sel_not; -- Otherwise, retain state
ARB_REG_PROC : process(OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
DMA_sel_IP_sel_not <= DMA_sel_IP_sel_not_p1;
end if;
end process;
end generate Insert_Arbiter;
FSM_AND_RELATED_LOGIC: block
constant RESET_ACTIVE: std_logic := '1';
--signals
signal Mn_Select_i : std_logic;
signal Mn_Select_p1 : std_logic;
signal Bus2IP_MstLastAck_i_p1: std_logic;
signal last_mstrd_burst_ack_d1 : std_logic;
signal Bus2IP_MstWrAck_ma_p1 : std_logic;
signal Bus2IP_MstRdAck_ma_p1 : std_logic;
signal Bus2IP_MstRdAck_ma_p1_d1: std_logic;
signal either_ack : std_logic;
signal acks_left : std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1);
signal acks_left_eq1 : std_logic;
signal acks_left_eq2 : std_logic;
signal acks_left_ld : std_logic;
signal Bus2IP_MstError_Flag : std_logic;
signal bus2ip_mstretry_i : std_logic;
signal bus2ip_mstretry_i_p1 : std_logic;
signal Mst_SM_cs_EQ_Wait_state_i : std_logic;
type Master_Attach_SMtype is (Wait_state,
Wait_For_Req,
Wait_for_RdRdy,
Mn_Req,
Burst_Count_Acks,
Check_Retry_Type
);
signal Mst_SM_cs, Mst_SM_ns : Master_Attach_SMtype;
begin
--Combinatorial operations
Incr_N_Load <= not bus_mngrant_i;
bus_mngrant_i <= OPB_MnGrant and mn_request_i;
MA2SA_XferAck_i <= OPB_XferAck and Mn_Select_i;
MA2SA_Retry <= OPB_Retry and Mn_Select_i;
MA2SA_RSRA <= retained_state_retry_active;
Mn_Select <= Mn_Select_i;
MA2SA_Select <= Mn_Select_i;
Mst_SM_cs_EQ_Wait_state <= Mst_SM_cs_EQ_Wait_state_i;
Bus2IP_MstError <= Bus2IP_MstError_Flag;
Get_off_OPB_nxt_clk <= not mn_select_p1;
-- State machine combinational process
Mst_SM: process (Mst_SM_cs, XXX2Bus_MstWrReq,
XXX2Bus_MstRdReq, SA2MA_RdRdy, OPB_TimeOut,
OPB_Retry, bus_mngrant_i, MA2SA_XferAck_i,
MA2SA_Num_i, Mn_Select_i,
bus2ip_msttimeout_i, Bus2IP_MstLastAck_i, Bus2IP_MstRetry_i,
DMA2Bus_MstRdReq, DMA2Bus_MstWrReq, SA2MA_PostedWrInh,
IP2Bus_MstRdReq, IP2Bus_MstWrReq, retained_state_retry_active,
SA2MA_TimeOut, acks_left_eq1, acks_left_eq2,
DMA_sel_IP_sel_not_p1,
ma2sa_rd_i, sa2ma_bufocc_eq0, sa2ma_bufocc_eq1, all_buffered_data_written)
begin
-- Set default values
Mst_SM_ns <= Mst_SM_cs;
mn_request_i <= '0';
mn_select_p1 <= '0';
Xfer_in_progress <= '1';
Mst_SM_cs_EQ_Wait_state_i <= '0';
Mst_SM_cs_EQ_Wait_For_Req <= '0';
Clear_SeqAddr_BusLock <= '0';
Mst_rd_starting_pulse <= '0';
retained_state_retry_active_p1 <= retained_state_retry_active;
toggle_priority <= '0';
acks_left_ld <= '0';
ma2sa_rd_i_set <= '0';
case Mst_SM_cs is
when Wait_state =>
Mst_SM_ns <= Wait_For_Req;
Clear_SeqAddr_BusLock <= '1';
Mst_SM_cs_EQ_Wait_state_i <= '1';
Xfer_in_progress <= '0';
retained_state_retry_active_p1 <= '0';
when Wait_For_Req =>
Mst_SM_cs_EQ_Wait_For_Req <= '1';
Xfer_in_progress <= '0';
if ((not DMA_sel_IP_sel_not_p1 and IP2Bus_MstWrReq) or
( DMA_sel_IP_sel_not_p1 and DMA2Bus_MstWrReq)) = '1' then
ma2sa_rd_i_set <= '1';
Mst_SM_ns <= Wait_for_RdRdy;
elsif ((not DMA_sel_IP_sel_not_p1 and IP2Bus_MstRdReq) or
( DMA_sel_IP_sel_not_p1 and (DMA2Bus_MstRdReq and
not SA2MA_PostedWrInh))
) = '1' then
-- DMA reads do not proceed until posted writes
-- can be accepted because the slave sets the rate
-- for this data, which can be at one per clock.
-- An IP master read proceeds without checking
-- posted write inhibit, so, the IP master read request
-- may occur only if IPIC posted writes will succeed and
-- such posted writes will occur without regard to the
-- state of the PostedWrInh signal.
Mst_rd_starting_pulse <= '1';
Mst_SM_ns <= Mn_Req;
end if;
when Wait_for_RdRdy =>
if(SA2MA_RdRdy and not sa2ma_bufocc_eq0) = '1' then
Mst_SM_ns <= Mn_Req;
elsif (bus2ip_mstretry_i or bus2ip_msttimeout_i) = '1' then
toggle_priority <= '1';
Mst_SM_ns <= Wait_state;
end if;
when Mn_Req =>
mn_request_i <= '1';
acks_left_ld <= not retained_state_retry_active;
if(bus_mngrant_i = '1') then
Mst_SM_ns <= Burst_Count_Acks;
mn_select_p1 <= '1';
end if; -- mn_request_i must deassert in response
-- to OPB_MnGrant to assure that bus_mngrant_i
-- is asserted for exactly one clock.
-- In this state bus_mngrant_i is asserted iff
-- OPB_MnGrant is asserted (since mn_request_i = '1').
when Check_Retry_Type =>
if (XXX2Bus_MstRdReq or XXX2Bus_MstWrReq)='1' then
Mst_SM_ns <= Mn_Req; -- Transaction continued.
retained_state_retry_active_p1 <= '1';
else
toggle_priority <= '1';
Mst_SM_ns <= Wait_state; -- Transaction aborted.
end if;
when Burst_Count_Acks =>
mn_select_p1 <= Mn_Select_i
and not ( ( MA2SA_XferAck_i -- End transaction
and (acks_left_eq1 or -- if done or ...
(ma2sa_rd_i and sa2ma_bufocc_eq0)
)
)
or OPB_Retry -- retry response or
or OPB_TimeOut -- timeout response.
);
if(bus2ip_mstretry_i = '1') then
if not (ma2sa_rd_i and all_buffered_data_written) = '1' then
Mst_SM_ns <= Check_Retry_Type;
else
toggle_priority <= '1';
Mst_SM_ns <= Wait_state;
end if;
elsif(bus2ip_msttimeout_i = '1') then
Mst_SM_ns <= Wait_state;
elsif(Bus2IP_MstLastAck_i = '1') then
Mst_SM_ns <= Wait_state;
end if;
if(MA2SA_XferAck_i = '1') then
if (acks_left_eq2 or (ma2sa_rd_i and sa2ma_bufocc_eq1)) = '1' then
Clear_SeqAddr_BusLock <= '1';
end if;
end if;
when others =>
Mst_SM_ns <= Wait_state;
end case;
end process Mst_SM;
Mst_SM_Reg: process (OPB_Clk)
begin
if (OPB_Clk'event and OPB_Clk = '1') then
if (Reset_withNotReqs = RESET_ACTIVE) then
Mst_SM_cs <= Wait_state;
else
Mst_SM_cs <= Mst_SM_ns;
end if;
retained_state_retry_active <= retained_state_retry_active_p1;
end if;
end process Mst_SM_Reg;
ms_select_REG: process (OPB_Clk)
begin
if (OPB_Clk'event and OPB_Clk = '1') then
if (Reset = RESET_ACTIVE) then
Mn_Select_i <= '0';
else
Mn_Select_i <= mn_select_p1;
end if;
end if;
end process ms_select_REG;
Register_ErrAck_Flag_PROCESS: process (OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE or Mst_SM_cs_EQ_Wait_state_i = '1') then
Bus2IP_MstError_Flag <= '0';
elsif((OPB_ErrAck = '1' and Mn_Select_i = '1') or
(SA2MA_Error = '1' and Xfer_in_progress = '1')) then
Bus2IP_MstError_Flag <= '1'; -- Flag error to be noted with LastAck
-- to local master
end if;
end if;
end process Register_ErrAck_Flag_PROCESS;
RETRY_HELP_PROC: process (OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if (bus2ip_mstretry_i_p1 and Bus2IP_MstLastAck_i_p1) = '1' or
(Reset = RESET_ACTIVE) then
-- As bus2ip_mstretry_i is set, ipic_rd_was_retried is cleared. This
-- makes bus2ip_mstretry_i a one-clock pulse when it is caused in part
-- by ipic_rd_was_retried.
ipic_rd_was_retried <= '0';
elsif (SA2MA_RdRdy) = '1' then
ipic_rd_was_retried <= SA2MA_Retry;
end if;
--
if (SA2MA_RdRdy) = '1' or (Reset = RESET_ACTIVE) then
all_buffered_data_written <= sa2ma_bufocc_eq0; -- If there is
-- no buffered data at RdRdy, then there is none to write.
elsif (sa2ma_bufocc_eq0 and MA2SA_XferAck_i) = '1' then -- This captures
-- the point at which all buffered data is written because the
-- buffer proper (fifo) is empty so the only word left is in
-- the output register, and it is being ack'ed.
all_buffered_data_written <= '1';
end if;
end if;
end process;
bus2ip_mstretry_i_p1 <= (OPB_Retry and Mn_Select_i) or
(ipic_rd_was_retried and all_buffered_data_written) or
(XXX2Bus_MstRdReq and SA2MA_Retry);
Register_OPB_Retry_PROCESS: process (OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE) then bus2ip_mstretry_i <= '0';
else bus2ip_mstretry_i <= bus2ip_mstretry_i_p1;
end if;
end if;
end process Register_OPB_Retry_PROCESS;
Bus2IP_MstRetry <= bus2ip_mstretry_i;
Register_Time_Out_PROCESS: process (OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE) then
bus2ip_msttimeout_i <= '0';
else
bus2ip_msttimeout_i <= (OPB_TimeOut and Mn_Select_i) or SA2MA_TimeOut;
end if;
end if;
end process Register_Time_Out_PROCESS;
Bus2IP_MstTimeOut <= bus2ip_msttimeout_i;
either_ack <= Bus2IP_MstRdAck_ma_p1 or Bus2IP_MstWrAck_ma_p1;
--
ACKS_LEFT_I : entity proc_common_v1_00_b.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => MA2SA_Num_i'length,
C_RESET_VALUE => ZEROES(0 to MA2SA_Num_i'length-1),
C_LD_WIDTH => MA2SA_Num_i'length,
C_AD_WIDTH => 1
)
port map (
CK => OPB_Clk,
RST => '0',
Q => acks_left,
LD => MA2SA_Num_i,
AD => "1",
LOAD => acks_left_ld,
OP => either_ack
);
--
acks_left_eq1 <= bo2sl(UNSIGNED(acks_left) = 1);
acks_left_eq2 <= bo2sl(UNSIGNED(acks_left) = 2);
Mst_Ack_COMB_PROCESS: process(XXX2Bus_MstRdReq, XXX2Bus_MstWrReq,
XXX2Bus_MstBurst,
SA2MA_WrAck, MA2SA_XferAck_i,
acks_left_eq1, acks_left_eq2, MA2SA_Num_i)
begin
Bus2IP_MstWrAck_ma_p1 <= '0';
Bus2IP_MstRdAck_ma_p1 <= '0';
if(XXX2Bus_MstRdReq = '1') then
if(XXX2Bus_MstBurst = '1') then --Fire and forget with Burst
Bus2IP_MstRdAck_ma_p1 <= MA2SA_XferAck_i;
else --Wait for local Write Ack
Bus2IP_MstRdAck_ma_p1 <= SA2MA_WrAck; --when single Xfer
end if;
elsif(XXX2Bus_MstWrReq = '1') then
Bus2IP_MstWrAck_ma_p1 <= MA2SA_XferAck_i;
end if;
end process Mst_Ack_COMB_PROCESS;
RD_BURST_ACK_DELAY_PROC : process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
Bus2IP_MstRdAck_ma_p1_d1 <= Bus2IP_MstRdAck_ma_p1;
last_mstrd_burst_ack_d1 <= XXX2Bus_MstRdReq and XXX2Bus_MstBurst and
MA2SA_XferAck_i and acks_left_eq1;
end if;
end process;
Bus2IP_MstLastAck_i_p1 <= last_mstrd_burst_ack_d1 -- When MstRd, burst
or ( XXX2Bus_MstRdReq
and not XXX2Bus_MstBurst
and SA2MA_WrAck -- When MstRd, ~burst
and acks_left_eq1)
or ( XXX2Bus_MstWrReq
and MA2SA_XferAck_i -- When MstWr
and acks_left_eq1)
or ( bus2ip_mstretry_i_p1 -- When retry
and ( ( XXX2Bus_MstWrReq
and all_buffered_data_written)
or ( XXX2Bus_MstRdReq
and SA2MA_Retry)));
-- Note, for retries Bus2IP_MstLastAck serves
-- as a qualifier. It is asserted iff
-- no data is "in limbo", i.e. all data that
-- has been read from the IPIC/OPB has
-- been written to the OPB/IPIC or that
-- any read data that has been discarded
-- is rereadable (aka idempotent,
-- non-destructive readable, pre-fetchable).
-- For loccally mastered writes,
-- (XXX2Bus_MstWrReq = '1'), Bus2IP_MstLastAck
-- is asserted iff buffered data has been
-- written.
-- For loccally mastered reads,
-- (XXX2Bus_MstRdReq = '1'), Bus2IP_MstLastAck
-- is always asserted even though the data read
-- from the OPB (and not accepted by the IPIC)
-- is discarded. The consequence is that any
-- OPB data read as the first part of a locally
-- mastered read operation must either be
-- re-readable or there must be a guarantee
-- that the IPIC will not refuse it by
-- replying with retry.
MSTLASTACK_REG_PROCESS: process(OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE) then --Synchronous Reset
Bus2IP_MstLastAck_i <= '0';
else
Bus2IP_MstLastAck_i <= Bus2IP_MstLastAck_i_p1;
end if;
end if;
end process;
Mst_Ack_REG_PROCESS: process(OPB_Clk)
begin
if(OPB_Clk'event and OPB_Clk = '1') then
if(Reset = RESET_ACTIVE) then --Synchronous Reset
Bus2IP_MstRdAck_ma <= '0';
Bus2IP_MstWrAck_ma <= '0';
else
Bus2IP_MstWrAck_ma <= Bus2IP_MstWrAck_ma_p1;
if (XXX2Bus_MstRdReq and XXX2Bus_MstBurst) = '0' then
Bus2IP_MstRdAck_ma <= Bus2IP_MstRdAck_ma_p1;
else
Bus2IP_MstRdAck_ma <= Bus2IP_MstRdAck_ma_p1_d1;
end if;
end if;
end if;
end process Mst_Ack_REG_PROCESS;
end block FSM_AND_RELATED_LOGIC;
---
end implementation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc5.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p08n01i00005ent IS
END c04s01b00x00p08n01i00005ent;
ARCHITECTURE c04s01b00x00p08n01i00005arch OFc04s01b00x00p08n01i00005ent IS
BEGIN
TESTING: PROCESS
type I1 is range 1 to 1;
type I2 is range 1 to 1;
variable V1: I1;
variable V2: I2;
BEGIN
if V1 = V2 then -- Failure_here
-- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
null ;
end if;
assert FALSE
report "***FAILED TEST: c04s01b00x00p08n01i00005 - Types are different and hence incompatible."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p08n01i00005arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc5.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p08n01i00005ent IS
END c04s01b00x00p08n01i00005ent;
ARCHITECTURE c04s01b00x00p08n01i00005arch OFc04s01b00x00p08n01i00005ent IS
BEGIN
TESTING: PROCESS
type I1 is range 1 to 1;
type I2 is range 1 to 1;
variable V1: I1;
variable V2: I2;
BEGIN
if V1 = V2 then -- Failure_here
-- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
null ;
end if;
assert FALSE
report "***FAILED TEST: c04s01b00x00p08n01i00005 - Types are different and hence incompatible."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p08n01i00005arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc5.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p08n01i00005ent IS
END c04s01b00x00p08n01i00005ent;
ARCHITECTURE c04s01b00x00p08n01i00005arch OFc04s01b00x00p08n01i00005ent IS
BEGIN
TESTING: PROCESS
type I1 is range 1 to 1;
type I2 is range 1 to 1;
variable V1: I1;
variable V2: I2;
BEGIN
if V1 = V2 then -- Failure_here
-- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
null ;
end if;
assert FALSE
report "***FAILED TEST: c04s01b00x00p08n01i00005 - Types are different and hence incompatible."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p08n01i00005arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_arb
-- File: pt_pci_arb.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI arbiter
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
entity pt_pci_arb is
generic (
slots : integer := 5;
tval : time := 7 ns);
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end pt_pci_arb;
architecture tb of pt_pci_arb is
type queue_type is array (0 to slots-1) of integer range 0 to slots;
signal queue : queue_type;
signal queue_nr : integer range 0 to slots;
signal wfbus : boolean;
begin
arb : process(systclk)
variable i, slotgnt : integer;
variable set : boolean;
variable bus_idle : boolean;
variable vqueue_nr : integer range 0 to slots;
variable gnt,req : std_logic_vector(slots-1 downto 0);
begin
set := false; vqueue_nr := queue_nr;
if (ifcin.frame and ifcin.irdy) = '1' then bus_idle := true; else bus_idle := false; end if;
gnt := to_x01(arbin.gnt(slots-1 downto 0));
req := to_x01(arbin.req(slots-1 downto 0));
if systclk.rst = '0' then
gnt := (others => '1');
wfbus <= false;
for i in 0 to slots-1 loop
queue(i) <= 0;
end loop;
queue_nr <= 0;
elsif rising_edge(systclk.clk) then
for i in 0 to slots-1 loop
if (gnt(i) or req(i)) = '0' then
if (bus_idle or wfbus) then
set := true;
end if;
end if;
end loop;
for i in 0 to slots-1 loop
if (gnt(i) and not req(i)) = '1' then
if queue(i) = 0 then
vqueue_nr := vqueue_nr+1;
queue(i) <= vqueue_nr;
elsif (queue(i) = 1 and set = false) then
gnt := (others => '1'); gnt(i) := '0';
queue(i) <= 0;
if not bus_idle then wfbus <= true; end if;
if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif queue(i) >= 2 then
if (set = false or vqueue_nr <= 1) then
queue(i) <= queue(i)-1;
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
elsif (req(i) and not gnt(i)) = '1' then
queue(i) <= 0; gnt(i) := '1';
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif (req(i) and gnt(i)) = '1' then
if (queue(i) > 0 and set = false) then
queue(i) <= queue(i)-1;
if (vqueue_nr > 0 and queue(i) = 1) then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
end loop;
end if;
if bus_idle then wfbus <= false; end if;
queue_nr <= vqueue_nr;
arbout.req <= (others => 'Z');
arbout.gnt <= (others => 'Z');
arbout.gnt(slots-1 downto 0) <= gnt;
end process;
end;
-- pragma translate_on
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm is
generic(
pwm_bits : natural := 31
);
port(
clk : in std_logic;
resetn : in std_logic;
enable : in std_logic;
duty_cycle : in std_logic_vector(pwm_bits - 1 downto 0);
--phase : in std_logic_vector(pwm_bits - 1 downto 0);
highimp : in std_logic;
pwm_out : out std_logic;
pwm_out_n: out std_logic
);
end entity pwm;
architecture behavorial of pwm is
type state_t is (hi, lo, hz, idle);
signal pwm_state : state_t := idle;
signal counter : unsigned(pwm_bits - 1 downto 0) := (others => '0');
signal pwm_out_reg : std_logic;
begin
counter_proc:
process(clk, resetn, enable)
begin
if rising_edge(clk) then
if resetn = '0' then
counter <= (others => '0');
end if;
if enable = '1' then
counter <= counter + 1;
end if;
end if;
end process counter_proc;
state_machine:
process(clk, resetn, enable, duty_cycle, highimp)
begin
if rising_edge(clk) then
if resetn = '0' or enable = '0' then
pwm_out_reg <= '0';
elsif enable = '1' then
if highimp = '1' then pwm_out_reg <= 'Z';
else
if counter < unsigned(duty_cycle) then pwm_out_reg <= '1';
else pwm_out_reg <= '0';
end if;
end if;
end if;
end if;
end process state_machine;
pwm_out <= pwm_out_reg;
pwm_out_n <= not pwm_out_reg;
--
--outctl:
--process(clk, pwm_state)
--begin
-- if rising_edge(clk) then
-- case (pwm_state) is
-- when hi => pwm_out <= '1';
-- pwm_out_n <= '0';
-- when lo => pwm_out <= '0';
-- pwm_out_n <= '1';
-- when idle => pwm_out <= 'Z';
-- pwm_out_n <= 'Z';
-- when hz => pwm_out <= 'Z';
-- pwm_out_n <= 'Z';
-- end case;
-- end if;
--end process outctl;
end architecture behavorial;
|
-------------------------------------------------------------------------------
-- $Id: lmb_v10.vhd,v 1.1.2.1 2010/09/03 11:19:35 rolandp Exp $
-------------------------------------------------------------------------------
-- lmb_v10.vhd
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: lmb_v10.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_v10.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2010/09/03 11:19:35 $
--
-- History:
-- goran 2002-01-30 First Version
-- paulo 2002-04-10 Renamed C_NUM_SLAVES to C_LMB_NUM_SLAVES
-- roland 2010-02-13 UE, CE and Wait signals added
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer := 4;
C_LMB_DWIDTH : integer := 32;
C_LMB_AWIDTH : integer := 32;
C_EXT_RESET_HIGH : integer := 1
);
port (
-- Global Ports
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
-- LMB master signals
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
-- LMB slave signals
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
-- LMB output signals
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end entity lmb_v10;
library unisim;
use unisim.all;
architecture IMP of lmb_v10 is
component FDS is
port(
Q : out std_logic;
D : in std_logic;
C : in std_logic;
S : in std_logic);
end component FDS;
signal sys_rst_i : std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Driving the reset signal
-----------------------------------------------------------------------------
SYS_RST_PROC : process (SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_input := not SYS_Rst;
else
sys_rst_input := SYS_Rst;
end if;
sys_rst_i <= sys_rst_input;
end process SYS_RST_PROC;
POR_FF_I : FDS
port map (
Q => LMB_Rst,
D => '0',
C => LMB_Clk,
S => sys_rst_i);
-----------------------------------------------------------------------------
-- Drive all Master to Slave signals
-----------------------------------------------------------------------------
LMB_ABus <= M_ABus;
LMB_ReadStrobe <= M_ReadStrobe;
LMB_WriteStrobe <= M_WriteStrobe;
LMB_AddrStrobe <= M_AddrStrobe;
LMB_BE <= M_BE;
LMB_WriteDBus <= M_DBus;
-----------------------------------------------------------------------------
-- Drive all the Slave to Master signals
-----------------------------------------------------------------------------
Ready_ORing : process (Sl_Ready) is
variable i : std_logic;
begin -- process Ready_ORing
i := '0';
for S in Sl_Ready'range loop
i := i or Sl_Ready(S);
end loop; -- S
LMB_Ready <= i;
end process Ready_ORing;
Wait_ORing : process (Sl_Wait) is
variable i : std_logic;
begin -- process Wait_ORing
i := '0';
for S in Sl_Wait'range loop
i := i or Sl_Wait(S);
end loop; -- S
LMB_Wait <= i;
end process Wait_ORing;
SI_UE_ORing : process (Sl_UE) is
variable i : std_logic;
begin -- process UE_ORing
i := '0';
for S in Sl_UE'range loop
i := i or Sl_UE(S);
end loop; -- S
LMB_UE <= i;
end process SI_UE_ORing;
SI_CE_ORing : process (Sl_CE) is
variable i : std_logic;
begin -- process CE_ORing
i := '0';
for S in Sl_CE'range loop
i := i or Sl_CE(S);
end loop; -- S
LMB_CE <= i;
end process SI_CE_ORing;
DBus_Oring : process (Sl_Ready, Sl_DBus) is
variable Res : std_logic_vector(0 to C_LMB_DWIDTH-1);
variable Tmp : std_logic_vector(Sl_DBus'range);
variable tmp_or : std_logic;
begin -- process DBus_Oring
if (C_LMB_NUM_SLAVES = 1) then
LMB_ReadDBus <= Sl_DBus;
else
-- First gating all data signals with their resp. ready signal
for I in 0 to C_LMB_NUM_SLAVES-1 loop
for J in 0 to C_LMB_DWIDTH-1 loop
tmp(I*C_LMB_DWIDTH + J) := Sl_Ready(I) and Sl_DBus(I*C_LMB_DWIDTH + J);
end loop; -- J
end loop; -- I
-- then oring the tmp signals together
for J in 0 to C_LMB_DWIDTH-1 loop
tmp_or := '0';
for I in 0 to C_LMB_NUM_SLAVES-1 loop
tmp_or := tmp_or or tmp(I*C_LMB_DWIDTH + j);
end loop; -- J
res(J) := tmp_or;
end loop; -- I
LMB_ReadDBus <= Res;
end if;
end process DBus_Oring;
end architecture IMP;
|
library ieee;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity syncregn_tb is
-- Generic declarations of the tested unit
generic(
n : INTEGER := 4 );
end syncregn_tb;
architecture TB_ARCHITECTURE of syncregn_tb is
-- Component declaration of the tested unit
component syncregn
generic(
n : INTEGER := 4 );
port(
Din : in STD_LOGIC_VECTOR(n-1 downto 0);
EN : in STD_LOGIC;
C : in STD_LOGIC;
Dout : out STD_LOGIC_VECTOR(n-1 downto 0) );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal Din : STD_LOGIC_VECTOR(n-1 downto 0);
signal EN : STD_LOGIC;
signal C : STD_LOGIC;
-- Observed signals - signals mapped to the output ports of tested entity
signal Dout : STD_LOGIC_VECTOR(n-1 downto 0);
constant CLK_Period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : syncregn
generic map (
n => n
)
port map (
Din => Din,
EN => EN,
C => C,
Dout => Dout
);
CLK_Process: process
begin
C <= '0';
wait for CLK_Period/2;
C <= '1';
wait for CLK_Period/2;
end process;
stim_proc: process
begin
wait for CLK_Period;
Din <= "1111";
EN <= '1'; wait for CLK_Period;
EN <= '0'; wait for CLK_Period;
Din <= "0000"; wait for 2*CLK_Period;
EN <= '1'; wait for CLK_Period;
Din <= "1111"; wait for CLK_Period;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_syncregn of syncregn_tb is
for TB_ARCHITECTURE
for UUT : syncregn
use entity work.syncregn(behavior);
end for;
end for;
end TESTBENCH_FOR_syncregn;
|
------------------------------------------------------------------------------
-- Testbench for contextregfile.vhd
--
-- Project :
-- File : tb_contextregfile.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/03/06
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_ContextRegFile is
end tb_ContextRegFile;
architecture arch of tb_ContextRegFile is
constant NCONTEXTS : integer := 8;
constant WIDTH : integer := 16;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done, reg1, clr3, wrall, rdall, clrall);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal ClrContextxSI : std_logic_vector(log2(NCONTEXTS)-1 downto 0);
signal ClrContextxEI : std_logic;
signal ContextxSI : std_logic_vector(log2(NCONTEXTS)-1 downto 0);
signal EnxEI : std_logic;
signal DinxDI : std_logic_vector(WIDTH-1 downto 0);
signal DoutxDO : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ContextRegFile
generic map (
NCONTEXTS => NCONTEXTS,
WIDTH => WIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrContextxSI => ClrContextxSI,
ClrContextxEI => ClrContextxEI,
ContextxSI => ContextxSI,
EnxEI => EnxEI,
DinxDI => DinxDI,
DoutxDO => DoutxDO);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
procedure init_stimuli (
signal ClrContextxSI : out std_logic_vector(log2(NCONTEXTS)-1 downto 0);
signal ClrContextxEI : out std_logic;
signal ContextxSI : out std_logic_vector(log2(NCONTEXTS)-1 downto 0);
signal EnxEI : out std_logic;
signal DinxDI : out std_logic_vector(WIDTH-1 downto 0)) is
begin
ClrContextxSI <= (others => '0');
ClrContextxEI <= '0';
ContextxSI <= (others => '0');
EnxEI <= '0';
DinxDI <= (others => '0');
end init_stimuli;
begin -- process stimuliTb
tbStatus <= rst;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
-- enable and disable register 1
tbStatus <= reg1;
ContextxSI <= std_logic_vector(to_unsigned(1, log2(NCONTEXTS)));
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(11, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '0';
DinxDI <= std_logic_vector(to_unsigned(12, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(13, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '0';
DinxDI <= std_logic_vector(to_unsigned(14, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(15, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(0, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- write all
tbStatus <= wrall;
for c in 0 to NCONTEXTS-1 loop
ContextxSI <= std_logic_vector(to_unsigned(c, log2(NCONTEXTS)));
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(c+10, WIDTH));
wait for CLK_PERIOD;
end loop; -- c
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- read all
tbStatus <= rdall;
for c in 0 to NCONTEXTS-1 loop
ContextxSI <= std_logic_vector(to_unsigned(c, log2(NCONTEXTS)));
wait for CLK_PERIOD;
end loop; -- c
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- clear register 3
tbstatus <= clr3;
ContextxSI <= std_logic_vector(to_unsigned(3, log2(NCONTEXTS)));
ClrContextxSI <= std_logic_vector(to_unsigned(3, log2(NCONTEXTS)));
ClrContextxEI <= '1';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- clear all
tbstatus <= clrall;
for c in 0 to NCONTEXTS-1 loop
ClrContextxSI <= std_logic_vector(to_unsigned(c, log2(NCONTEXTS)));
ClrContextxEI <= '1';
wait for CLK_PERIOD;
end loop; -- c
-- read all
tbStatus <= rdall;
for c in 0 to NCONTEXTS-1 loop
ContextxSI <= std_logic_vector(to_unsigned(c, log2(NCONTEXTS)));
wait for CLK_PERIOD;
end loop; -- c
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
tbStatus <= done;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------------------
-- Filename: axi_traffic_gen_v2_0_bmg_wrap.v
-- Version : v1.0
-- Description: BMG Wrapper
-- Verilog-Standard:verilog-2001
-----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library lib_bmg_v1_0;
use lib_bmg_v1_0.all;
entity axi_traffic_gen_v2_0_bmg_wrap is
generic
(
-- Device Family
c_family : string := "virtex5";
c_xdevicefamily : string := "virtex5";
-- Finest Resolution Device Family
-- "Virtex2"
-- "Virtex2-Pro"
-- "Virtex4"
-- "Virtex5"
-- "Spartan-3A"
-- "Spartan-3A DSP"
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity axi_traffic_gen_v2_0_bmg_wrap;
architecture implementation of axi_traffic_gen_v2_0_bmg_wrap is
begin
-- component blk_mem_gen_wrapper is
-- generic
-- (
-- c_family : string := "virtex5";
-- c_xdevicefamily : string := "virtex5";
-- c_elaboration_dir : string := "";
-- c_mem_type : integer := 2;
-- c_algorithm : integer := 1;
-- c_prim_type : integer := 1;
-- c_byte_size : integer := 9; -- 8 or 9
-- c_sim_collision_check : string := "NONE";
-- c_common_clk : integer := 1; -- 0, 1
-- c_disable_warn_bhv_coll : integer := 0; -- 0, 1
-- c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- c_load_init_file : integer := 0;
-- c_init_file_name : string := "no_coe_file_loaded";
-- c_use_default_data : integer := 0; -- 0, 1
-- c_default_data : string := "0"; -- "..."
-- c_has_mem_output_regs_a : integer := 0; -- 0, 1
-- c_has_mux_output_regs_a : integer := 0; -- 0, 1
-- c_write_width_a : integer := 32; -- 1 to 1152
-- c_read_width_a : integer := 32; -- 1 to 1152
-- c_write_depth_a : integer := 64; -- 2 to 9011200
-- c_read_depth_a : integer := 64; -- 2 to 9011200
-- c_addra_width : integer := 6; -- 1 to 24
-- c_write_mode_a : string := "WRITE_FIRST";
-- c_has_ena : integer := 1; -- 0, 1
-- c_has_regcea : integer := 0; -- 0, 1
-- c_has_ssra : integer := 0; -- 0, 1
-- c_sinita_val : string := "0"; --"..."
-- c_use_byte_wea : integer := 0; -- 0, 1
-- c_wea_width : integer := 1; -- 1 to 128
-- c_has_mem_output_regs_b : integer := 0; -- 0, 1
-- c_has_mux_output_regs_b : integer := 0; -- 0, 1
-- c_write_width_b : integer := 32; -- 1 to 1152
-- c_read_width_b : integer := 32; -- 1 to 1152
-- c_write_depth_b : integer := 64; -- 2 to 9011200
-- c_read_depth_b : integer := 64; -- 2 to 9011200
-- c_addrb_width : integer := 6; -- 1 to 24
-- c_write_mode_b : string := "WRITE_FIRST";
-- c_has_enb : integer := 1; -- 0, 1
-- c_has_regceb : integer := 0; -- 0, 1
-- c_has_ssrb : integer := 0; -- 0, 1
-- c_sinitb_val : string := "0"; -- "..."
-- c_use_byte_web : integer := 0; -- 0, 1
-- c_web_width : integer := 1; -- 1 to 128
-- c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- c_use_ecc : integer := 0;
-- c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- );
-- port
-- (
-- clka : in std_logic;
-- ssra : in std_logic := '0';
-- dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
-- addra : in std_logic_vector(c_addra_width-1 downto 0);
-- ena : in std_logic := '1';
-- regcea : in std_logic := '1';
-- wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
-- douta : out std_logic_vector(c_read_width_a-1 downto 0);
-- clkb : in std_logic := '0';
-- ssrb : in std_logic := '0';
-- dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
-- addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
-- enb : in std_logic := '1';
-- regceb : in std_logic := '1';
-- web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
-- doutb : out std_logic_vector(c_read_width_b-1 downto 0);
-- dbiterr : out std_logic;
-- sbiterr : out std_logic
-- );
--end component;
proc_bmg :entity lib_bmg_v1_0.blk_mem_gen_wrapper
generic map
(
c_family => c_family ,
c_xdevicefamily => c_xdevicefamily ,
c_elaboration_dir => c_elaboration_dir ,
c_mem_type => c_mem_type ,
c_algorithm => c_algorithm ,
c_prim_type => c_prim_type ,
c_byte_size => c_byte_size ,
c_sim_collision_check => c_sim_collision_check ,
c_common_clk => c_common_clk ,
c_disable_warn_bhv_coll => c_disable_warn_bhv_coll ,
c_disable_warn_bhv_range => c_disable_warn_bhv_range ,
c_load_init_file => c_load_init_file ,
c_init_file_name => c_init_file_name ,
c_use_default_data => c_use_default_data ,
c_default_data => c_default_data ,
c_has_mem_output_regs_a => c_has_mem_output_regs_a ,
c_has_mux_output_regs_a => c_has_mux_output_regs_a ,
c_write_width_a => c_write_width_a ,
c_read_width_a => c_read_width_a ,
c_write_depth_a => c_write_depth_a ,
c_read_depth_a => c_read_depth_a ,
c_addra_width => c_addra_width ,
c_write_mode_a => c_write_mode_a ,
c_has_ena => c_has_ena ,
c_has_regcea => c_has_regcea ,
c_has_ssra => c_has_ssra ,
c_sinita_val => c_sinita_val ,
c_use_byte_wea => c_use_byte_wea ,
c_wea_width => c_wea_width ,
c_has_mem_output_regs_b => c_has_mem_output_regs_b ,
c_has_mux_output_regs_b => c_has_mux_output_regs_b ,
c_write_width_b => c_write_width_b ,
c_read_width_b => c_read_width_b ,
c_write_depth_b => c_write_depth_b ,
c_read_depth_b => c_read_depth_b ,
c_addrb_width => c_addrb_width ,
c_write_mode_b => c_write_mode_b ,
c_has_enb => c_has_enb ,
c_has_regceb => c_has_regceb ,
c_has_ssrb => c_has_ssrb ,
c_sinitb_val => c_sinitb_val ,
c_use_byte_web => c_use_byte_web ,
c_web_width => c_web_width ,
c_mux_pipeline_stages => c_mux_pipeline_stages ,
c_use_ecc => c_use_ecc ,
c_use_ramb16bwer_rst_bhv => c_use_ramb16bwer_rst_bhv
)
port map (
clka => clka ,
ssra => ssra ,
dina => dina ,
addra => addra ,
ena => ena ,
regcea => regcea ,
wea => wea ,
douta => douta ,
clkb => clkb ,
ssrb => ssrb ,
dinb => dinb ,
addrb => addrb ,
enb => enb ,
regceb => regceb ,
web => web ,
doutb => doutb ,
dbiterr => dbiterr ,
sbiterr => sbiterr
);
end implementation;
|
-------------------------------------------------------------------------------
--
-- Generic testbench elements
--
-- $Id: tb_elems-c.vhd,v 1.1 2006-05-15 21:55:27 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration tb_elems_behav_c0 of tb_elems is
for behav
end for;
end tb_elems_behav_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
--
-- Sigma-delta output
--
-- Copyright 2008,2009,2010 Álvaro Lopes <[email protected]>
--
-- Version: 1.2
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 1.2: Adapted from ALZPU to ZPUino
-- 1.1: First version, imported from old controller.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_sigmadeltaDAC;
architecture behave of AUDIO_zpuino_sa_sigmadeltaDAC is
signal delta_adder: unsigned(BITS+1 downto 0);
signal sigma_adder: unsigned(BITS+1 downto 0);
signal sigma_latch: unsigned(BITS+1 downto 0);
signal delta_b: unsigned(BITS+1 downto 0);
signal dat_q: unsigned(BITS+1 downto 0);
signal rst: std_logic := '0';
begin
dat_q(BITS+1) <= '0';
dat_q(BITS) <= '0';
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
dat_q(BITS-1 downto 0) <= unsigned(data_in);
end if;
end process;
process(sigma_latch)
begin
delta_b(BITS+1) <= sigma_latch(BITS+1);
delta_b(BITS) <= sigma_latch(BITS+1);
delta_b(BITS-1 downto 0) <= (others => '0');
end process;
process(dat_q, delta_b)
begin
delta_adder <= dat_q + delta_b;
end process;
process(delta_adder,sigma_latch)
begin
sigma_adder <= delta_adder + sigma_latch;
end process;
process(clk_96Mhz)
begin
if rising_edge(clk_96Mhz) then
if rst='1' then
sigma_latch <= (others => '0');
sigma_latch(BITS+1) <= '1';
audio_out <= '0';
else
sigma_latch <= sigma_adder;
audio_out <= sigma_latch(BITS+1);
end if;
end if;
end process;
end behave;
|
use work.text_mode_pkg.all;
use work.tbu_text_out_pkg.all;
use work.colors_pkg.all;
use work.resource_handles_helper_pkg.all;
entity text_mode_pkg_tb is
end;
architecture testbench of text_mode_pkg_tb is
constant HELLO_WORLD_STRING: text_mode_string_type := (
x => 0,
y => 0,
text => "Hello world!!! ",
visible => true
);
constant SCORE_STRING: text_mode_string_type := (
x => 0,
y => 10,
text => "SCORE: 0 ",
visible => true
);
constant STRINGS: text_mode_strings_type := (
HELLO_WORLD_STRING,
SCORE_STRING
);
begin
process begin
for y in 0 to 11 loop
for x in 0 to 79 loop
--put( to_string(character_at_x_y(x,y)) );
print( to_string(character_at_x_y(x, y, strings)), newline => false );
end loop;
print("");
end loop;
for y in 0 to 11 loop
for x in 0 to 79 loop
--put( to_string(character_at_x_y(x,y)) );
if text_pixel_at_x_y(x, y, strings) then
print( "#", newline => false );
else
print( " ", newline => false );
end if;
end loop;
print("");
end loop;
put(to_string( game_strings_count ));
std.env.finish;
end process;
end; |
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n2 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
|
-- This code is an example of the connection between com block and ethernet_udp block.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.com_package.all;
use work.ethernet_package.all;
entity com_ethernet is
generic (
MASTER_ADDR_WIDTH : integer := 2;
MASTER_PORT : std_logic_vector(15 downto 0) := x"8000";
FIFO_IN_N : integer := 4;--up to 16 fifos
FIFO_IN_ID : fifo_ID := ("000001","000010","000011",x"000100",others=>"000000");
FIFO_IN_SIZE : fifo_size := (2048,1024,2048,512,others=>0);
ONE_PACKET_SIZE : integer := 1450;
FIFO_OUT_N : integer := 3;--up to 16 fifos
FIFO_OUT_ID : fifo_ID := ("110000","100001","100010",others=>x"100000");
FIFO_OUT_SIZE : fifo_size := (512,512,others=>0)
);
port(
CLK125 : in STD_LOGIC;
clk_proc : in std_logic;
reset_n : in std_logic;
--- ETHERNET
PHY_RESET_L : out STD_LOGIC;
PHY_MDC : out STD_LOGIC;
PHY_MDIO : inout STD_LOGIC;
TX_data : out std_logic_vector(3 downto 0);
TX_dv : out std_logic;
RX_data : in std_logic_vector(3 downto 0);
RX_dv : in std_logic;
GE_TXCLK : out std_logic;
--- Clocks from PLL
clk250_marvell : in std_logic;
clk250_fpga : in std_logic;
------------à generer
flow_in0_data : in std_logic_vector(7 downto 0);
flow_in0_dv : in std_logic;
flow_in0_fv : in std_logic;
flow_in1_data : in std_logic_vector(7 downto 0);
flow_in1_dv : in std_logic;
flow_in1_fv : in std_logic;
flow_in2_data : in std_logic_vector(7 downto 0);
flow_in2_dv : in std_logic;
flow_in2_fv : in std_logic;
flow_in3_data : in std_logic_vector(7 downto 0);
flow_in3_dv : in std_logic;
flow_in3_fv : in std_logic;
flow_out0_data : out std_logic_vector(7 downto 0);
flow_out0_dv : out std_logic;
flow_out0_fv : out std_logic;
flow_out1_data : out std_logic_vector(7 downto 0);
flow_out1_dv : out std_logic;
flow_out1_fv : out std_logic;
--- PI_master
master_addr_o : out std_logic_vector(MASTER_ADDR_WIDTH downto 0);
master_wr_o : out std_logic;
master_rd_o : out std_logic;
master_datawr_o : out std_logic_vector(31 downto 0);
master_datard_i : in std_logic_vector(31 downto 0);
--- PI_slave
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end com_ethernet;
architecture RTL of com_ethernet is
signal TX_s : rgmii_t;
signal param : param_t;
signal flow_tx_out : flow_t;
signal flow_master : flow_t;
signal ID_port_in : std_logic_vector(15 downto 0);
signal ID_port_out : std_logic_vector(15 downto 0);
signal size_flow : std_logic_vector(15 downto 0);
signal TX : rgmii_t;
signal RX : rgmii_t;
signal enable_eth : std_logic;
signal enable_in0 : std_logic;
signal enable_in1 : std_logic;
signal enable_in2 : std_logic;
signal enable_in3 : std_logic;
signal mac_addr_hal_msb : std_logic_vector(23 downto 0);
signal mac_addr_hal_lsb : std_logic_vector(23 downto 0);
signal mac_addr_dest_msb: std_logic_vector(23 downto 0);
signal mac_addr_dest_lsb: std_logic_vector(23 downto 0);
signal ip_hal : std_logic_vector(31 downto 0);
signal ip_dest : std_logic_vector(31 downto 0);
signal port_dest : std_logic_vector(15 downto 0);
signal data_to_hal : std_logic_vector(7 downto 0);
signal data_to_com : std_logic_vector(7 downto 0);
signal size : std_logic_vector(15 downto 0);
signal read_data,ready : std_logic;
signal hal_ready : std_logic;
signal write_i : std_logic;
signal test : flow_t;
begin
TX_data <= TX.data;
TX_dv <= TX.dv;
RX.data <= RX_data;
RX.dv <= RX_dv;
com_inst : entity work.com
generic map(
fifo_in_N => FIFO_IN_N,
fifo_in_ID => FIFO_IN_ID,
fifo_in_size => FIFO_IN_SIZE,
one_packet => ONE_PACKET_SIZE,
fifo_out_N => FIFO_OUT_N,
fifo_out_ID => FIFO_OUT_ID,
fifo_out_size => FIFO_OUT_SIZE
)
port map (
clk_hal => clk125,
clk_proc => clk_proc,
reset_n => reset_n,
--- From flows in to HAL
hal_ready => hal_ready,
data_o => data_to_hal,
data_size_o => size,
read_data_i => read_data,
ready_o => ready,
--- From HAL to flows out
data_i => data_to_com,
write_i => write_i,
--- flow to master
flow_master => flow_master,
------------à generer
flow_in0.data => flow_in0_data,
flow_in0.dv => flow_in0_dv,
flow_in0.fv => flow_in0_fv,
flow_in1.data => flow_in1_data,
flow_in1.dv => flow_in1_dv,
flow_in1.fv => flow_in1_fv,
flow_in2.data => flow_in2_data,
flow_in2.dv => flow_in2_dv,
flow_in2.fv => flow_in2_fv,
flow_in3.data => flow_in3_data,
flow_in3.dv => flow_in3_dv,
flow_in3.fv => flow_in3_fv,
flow_out0.data => flow_out0_data,
flow_out0.dv => flow_out0_dv,
flow_out0.fv => flow_out0_fv,
flow_out1.data => flow_out1_data,
flow_out1.dv => flow_out1_dv,
flow_out1.fv => flow_out1_fv,
--- parameters from slave
------------à generer
enable_eth => enable_eth,
enable_in0 => enable_in0,
enable_in1 => enable_in1,
enable_in2 => enable_in2,
enable_in3 => enable_in3
);
ethernet_inst : entity work.ethernet_udp
port map (
--- External ports
CLK125 => clk125,
reset_n => reset_n,
PHY_RESET_L => PHY_RESET_L,
PHY_MDC => PHY_MDC,
PHY_MDIO => PHY_MDIO,
TX => TX_s,
RX => RX,
GE_TXCLK => GE_TXCLK,
--- Clocks from Clocks Interconnect
clk250_marvell => clk250_marvell,
clk250_fpga => clk250_fpga,
--- Parameters from slave
mac_addr_hal_msb => mac_addr_hal_msb,
mac_addr_hal_lsb => mac_addr_hal_lsb,
mac_addr_dest_msb => mac_addr_dest_msb,
mac_addr_dest_lsb => mac_addr_dest_lsb,
ip_hal => ip_hal,
ip_dest => ip_dest,
port_dest => port_dest,
--- Receiving data to send on link
hal_ready => hal_ready,
data_i => data_to_hal,
data_size_i => size,
read_data_o => read_data,
ready_i => ready,
--- Transmitting flows received by link
data_o => data_to_com,
write_o => write_i
--ID_port_out => ID_port_out
);
TX <= TX_s;
master : entity work.com_master
generic map (pi_size_addr => MASTER_ADDR_WIDTH)
Port map(
CLK => clk_proc,
RESET_n => reset_n,
flow_in => flow_master,
master_addr_o => master_addr_o,
master_wr_o => master_wr_o,
master_rd_o => master_rd_o,
master_datawr_o => master_datawr_o,
master_datard_i => master_datard_i
);
slave : entity work.eth_slave
generic map (pi_size_addr => 3)
Port map(
CLK => clk_proc,
RESET_n => reset_n,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o,
--- parameters com
enable_eth_o => enable_eth,
enable_in0_o => enable_in0,
enable_in1_o => enable_in1,
enable_in2_o => enable_in2,
enable_in3_o => enable_in3,
--- parameters ethernet
mac_addr_hal_msb => mac_addr_hal_msb,
mac_addr_hal_lsb => mac_addr_hal_lsb,
mac_addr_dest_msb => mac_addr_dest_msb,
mac_addr_dest_lsb => mac_addr_dest_lsb,
ip_hal => ip_hal,
ip_dest => ip_dest,
port_dest => port_dest
);
end RTL;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Tests global constants, functions and settings
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
entity strings_tb is
end strings_tb;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
use PoC.simulation.all;
architecture tb of strings_tb is
constant raw_format_slv_dec_result0 : STRING := raw_format_slv_dec(STD_LOGIC_VECTOR'(x"12"));
constant raw_format_slv_dec_result1 : STRING := raw_format_slv_dec(x"3456");
constant raw_format_slv_dec_result2 : STRING := raw_format_slv_dec(x"12345678");
constant raw_format_slv_dec_result3 : STRING := raw_format_slv_dec(x"A1B2C3D4E5F607A8");
constant str_length_result0 : INTEGER := str_length("");
constant str_length_result1 : INTEGER := str_length((1 to 3 => C_POC_NUL));
constant str_length_result2 : INTEGER := str_length("Hello");
constant str_length_result3 : INTEGER := str_length("Hello" & (1 to 3 => C_POC_NUL));
constant str_match_result0 : BOOLEAN := str_match("", "");
constant str_match_result1 : BOOLEAN := str_match("", (1 to 3 => C_POC_NUL));
constant str_match_result2 : BOOLEAN := str_match("Hello", "hello");
constant str_match_result3 : BOOLEAN := str_match("Hello", "Hello");
constant str_match_result4 : BOOLEAN := str_match("Hello World", "Hello");
constant str_match_result5 : BOOLEAN := str_match("Hello", "Hello World");
constant str_match_result6 : BOOLEAN := str_match("Hello", "Hello" & (1 to 3 => C_POC_NUL));
constant str_imatch_result0 : BOOLEAN := str_imatch("", "");
constant str_imatch_result1 : BOOLEAN := str_imatch("", (1 to 3 => C_POC_NUL));
constant str_imatch_result2 : BOOLEAN := str_imatch("Hello", "hello");
constant str_imatch_result3 : BOOLEAN := str_imatch("Hello", "Hello");
constant str_imatch_result4 : BOOLEAN := str_imatch("Hello World", "Hello");
constant str_imatch_result5 : BOOLEAN := str_imatch("Hello", "Hello World");
constant str_imatch_result6 : BOOLEAN := str_imatch("Hello", "Hello" & (1 to 3 => C_POC_NUL));
begin
process
begin
-- raw_format_slv_dec tests
tbAssert((raw_format_slv_dec_result0 = "18"), "raw_format_slv_dec(0x12)=" & raw_format_slv_dec_result0 & " Expected='18'");
tbAssert((raw_format_slv_dec_result1 = "13398"), "raw_format_slv_dec(0x3456)=" & raw_format_slv_dec_result1 & " Expected='13398'");
tbAssert((raw_format_slv_dec_result2 = "305419896"), "raw_format_slv_dec(0x12345678)=" & raw_format_slv_dec_result2 & " Expected='305419896'");
tbAssert((raw_format_slv_dec_result3 = "11651590505119483816"), "raw_format_slv_dec(0xA1b2c3d4e5f607a8)=" & raw_format_slv_dec_result3 & " Expected='11651590505119483816'");
-- str_length tests
tbAssert((str_length_result0 = 0), "str_length('')=" & INTEGER'image(str_length_result0) & " Expected=0");
tbAssert((str_length_result1 = 0), "str_length('\0\0\0')=" & INTEGER'image(str_length_result1) & " Expected=0");
tbAssert((str_length_result2 = 5), "str_length('Hello')=" & INTEGER'image(str_length_result2) & " Expected=5");
tbAssert((str_length_result3 = 5), "str_length('Hello\0\0\0')=" & INTEGER'image(str_length_result3) & " Expected=5");
-- str_match tests
tbAssert((str_match_result0 = TRUE), "str_match('', '')=" & BOOLEAN'image(str_match_result0) & " Expected=TRUE");
tbAssert((str_match_result1 = TRUE), "str_match('', '\0\0\0')=" & BOOLEAN'image(str_match_result1) & " Expected=TRUE");
tbAssert((str_match_result2 = FALSE), "str_match('Hello', 'hello')=" & BOOLEAN'image(str_match_result2) & " Expected=FALSE");
tbAssert((str_match_result3 = TRUE), "str_match('Hello', 'Hello')=" & BOOLEAN'image(str_match_result3) & " Expected=TRUE");
tbAssert((str_match_result4 = FALSE), "str_match('Hello World', 'Hello')=" & BOOLEAN'image(str_match_result4) & " Expected=FALSE");
tbAssert((str_match_result5 = FALSE), "str_match('Hello', 'Hello World')=" & BOOLEAN'image(str_match_result5) & " Expected=FALSE");
tbAssert((str_match_result6 = TRUE), "str_match('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_match_result6) & " Expected=TRUE");
-- str_imatch tests
tbAssert((str_imatch_result0 = TRUE), "str_imatch('', '')=" & BOOLEAN'image(str_imatch_result0) & " Expected=TRUE");
tbAssert((str_imatch_result1 = TRUE), "str_imatch('', '\0\0\0')=" & BOOLEAN'image(str_imatch_result1) & " Expected=TRUE");
tbAssert((str_imatch_result2 = TRUE), "str_imatch('Hello', 'hello')=" & BOOLEAN'image(str_imatch_result2) & " Expected=TRUE");
tbAssert((str_imatch_result3 = TRUE), "str_imatch('Hello', 'Hello')=" & BOOLEAN'image(str_imatch_result3) & " Expected=TRUE");
tbAssert((str_imatch_result4 = FALSE), "str_imatch('Hello World', 'Hello')=" & BOOLEAN'image(str_imatch_result4) & " Expected=FALSE");
tbAssert((str_imatch_result5 = FALSE), "str_imatch('Hello', 'Hello World')=" & BOOLEAN'image(str_imatch_result5) & " Expected=FALSE");
tbAssert((str_imatch_result6 = TRUE), "str_imatch('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_imatch_result6) & " Expected=TRUE");
-- str_pos tests
-- str_ipos tests
-- str_find tests
-- str_ifind tests
-- str_replace tests
-- str_substr tests
-- str_ltrim tests
-- str_rtrim tests
-- str_trim tests
-- str_toLower tests
-- str_toUpper tests
-- simulation completed
-- Report overall simulation result
tbPrintResult;
wait;
end process;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Tests global constants, functions and settings
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
entity strings_tb is
end strings_tb;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
use PoC.simulation.all;
architecture tb of strings_tb is
constant raw_format_slv_dec_result0 : STRING := raw_format_slv_dec(STD_LOGIC_VECTOR'(x"12"));
constant raw_format_slv_dec_result1 : STRING := raw_format_slv_dec(x"3456");
constant raw_format_slv_dec_result2 : STRING := raw_format_slv_dec(x"12345678");
constant raw_format_slv_dec_result3 : STRING := raw_format_slv_dec(x"A1B2C3D4E5F607A8");
constant str_length_result0 : INTEGER := str_length("");
constant str_length_result1 : INTEGER := str_length((1 to 3 => C_POC_NUL));
constant str_length_result2 : INTEGER := str_length("Hello");
constant str_length_result3 : INTEGER := str_length("Hello" & (1 to 3 => C_POC_NUL));
constant str_match_result0 : BOOLEAN := str_match("", "");
constant str_match_result1 : BOOLEAN := str_match("", (1 to 3 => C_POC_NUL));
constant str_match_result2 : BOOLEAN := str_match("Hello", "hello");
constant str_match_result3 : BOOLEAN := str_match("Hello", "Hello");
constant str_match_result4 : BOOLEAN := str_match("Hello World", "Hello");
constant str_match_result5 : BOOLEAN := str_match("Hello", "Hello World");
constant str_match_result6 : BOOLEAN := str_match("Hello", "Hello" & (1 to 3 => C_POC_NUL));
constant str_imatch_result0 : BOOLEAN := str_imatch("", "");
constant str_imatch_result1 : BOOLEAN := str_imatch("", (1 to 3 => C_POC_NUL));
constant str_imatch_result2 : BOOLEAN := str_imatch("Hello", "hello");
constant str_imatch_result3 : BOOLEAN := str_imatch("Hello", "Hello");
constant str_imatch_result4 : BOOLEAN := str_imatch("Hello World", "Hello");
constant str_imatch_result5 : BOOLEAN := str_imatch("Hello", "Hello World");
constant str_imatch_result6 : BOOLEAN := str_imatch("Hello", "Hello" & (1 to 3 => C_POC_NUL));
begin
process
begin
-- raw_format_slv_dec tests
tbAssert((raw_format_slv_dec_result0 = "18"), "raw_format_slv_dec(0x12)=" & raw_format_slv_dec_result0 & " Expected='18'");
tbAssert((raw_format_slv_dec_result1 = "13398"), "raw_format_slv_dec(0x3456)=" & raw_format_slv_dec_result1 & " Expected='13398'");
tbAssert((raw_format_slv_dec_result2 = "305419896"), "raw_format_slv_dec(0x12345678)=" & raw_format_slv_dec_result2 & " Expected='305419896'");
tbAssert((raw_format_slv_dec_result3 = "11651590505119483816"), "raw_format_slv_dec(0xA1b2c3d4e5f607a8)=" & raw_format_slv_dec_result3 & " Expected='11651590505119483816'");
-- str_length tests
tbAssert((str_length_result0 = 0), "str_length('')=" & INTEGER'image(str_length_result0) & " Expected=0");
tbAssert((str_length_result1 = 0), "str_length('\0\0\0')=" & INTEGER'image(str_length_result1) & " Expected=0");
tbAssert((str_length_result2 = 5), "str_length('Hello')=" & INTEGER'image(str_length_result2) & " Expected=5");
tbAssert((str_length_result3 = 5), "str_length('Hello\0\0\0')=" & INTEGER'image(str_length_result3) & " Expected=5");
-- str_match tests
tbAssert((str_match_result0 = TRUE), "str_match('', '')=" & BOOLEAN'image(str_match_result0) & " Expected=TRUE");
tbAssert((str_match_result1 = TRUE), "str_match('', '\0\0\0')=" & BOOLEAN'image(str_match_result1) & " Expected=TRUE");
tbAssert((str_match_result2 = FALSE), "str_match('Hello', 'hello')=" & BOOLEAN'image(str_match_result2) & " Expected=FALSE");
tbAssert((str_match_result3 = TRUE), "str_match('Hello', 'Hello')=" & BOOLEAN'image(str_match_result3) & " Expected=TRUE");
tbAssert((str_match_result4 = FALSE), "str_match('Hello World', 'Hello')=" & BOOLEAN'image(str_match_result4) & " Expected=FALSE");
tbAssert((str_match_result5 = FALSE), "str_match('Hello', 'Hello World')=" & BOOLEAN'image(str_match_result5) & " Expected=FALSE");
tbAssert((str_match_result6 = TRUE), "str_match('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_match_result6) & " Expected=TRUE");
-- str_imatch tests
tbAssert((str_imatch_result0 = TRUE), "str_imatch('', '')=" & BOOLEAN'image(str_imatch_result0) & " Expected=TRUE");
tbAssert((str_imatch_result1 = TRUE), "str_imatch('', '\0\0\0')=" & BOOLEAN'image(str_imatch_result1) & " Expected=TRUE");
tbAssert((str_imatch_result2 = TRUE), "str_imatch('Hello', 'hello')=" & BOOLEAN'image(str_imatch_result2) & " Expected=TRUE");
tbAssert((str_imatch_result3 = TRUE), "str_imatch('Hello', 'Hello')=" & BOOLEAN'image(str_imatch_result3) & " Expected=TRUE");
tbAssert((str_imatch_result4 = FALSE), "str_imatch('Hello World', 'Hello')=" & BOOLEAN'image(str_imatch_result4) & " Expected=FALSE");
tbAssert((str_imatch_result5 = FALSE), "str_imatch('Hello', 'Hello World')=" & BOOLEAN'image(str_imatch_result5) & " Expected=FALSE");
tbAssert((str_imatch_result6 = TRUE), "str_imatch('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_imatch_result6) & " Expected=TRUE");
-- str_pos tests
-- str_ipos tests
-- str_find tests
-- str_ifind tests
-- str_replace tests
-- str_substr tests
-- str_ltrim tests
-- str_rtrim tests
-- str_trim tests
-- str_toLower tests
-- str_toUpper tests
-- simulation completed
-- Report overall simulation result
tbPrintResult;
wait;
end process;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Tests global constants, functions and settings
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
entity strings_tb is
end strings_tb;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
use PoC.simulation.all;
architecture tb of strings_tb is
constant raw_format_slv_dec_result0 : STRING := raw_format_slv_dec(STD_LOGIC_VECTOR'(x"12"));
constant raw_format_slv_dec_result1 : STRING := raw_format_slv_dec(x"3456");
constant raw_format_slv_dec_result2 : STRING := raw_format_slv_dec(x"12345678");
constant raw_format_slv_dec_result3 : STRING := raw_format_slv_dec(x"A1B2C3D4E5F607A8");
constant str_length_result0 : INTEGER := str_length("");
constant str_length_result1 : INTEGER := str_length((1 to 3 => C_POC_NUL));
constant str_length_result2 : INTEGER := str_length("Hello");
constant str_length_result3 : INTEGER := str_length("Hello" & (1 to 3 => C_POC_NUL));
constant str_match_result0 : BOOLEAN := str_match("", "");
constant str_match_result1 : BOOLEAN := str_match("", (1 to 3 => C_POC_NUL));
constant str_match_result2 : BOOLEAN := str_match("Hello", "hello");
constant str_match_result3 : BOOLEAN := str_match("Hello", "Hello");
constant str_match_result4 : BOOLEAN := str_match("Hello World", "Hello");
constant str_match_result5 : BOOLEAN := str_match("Hello", "Hello World");
constant str_match_result6 : BOOLEAN := str_match("Hello", "Hello" & (1 to 3 => C_POC_NUL));
constant str_imatch_result0 : BOOLEAN := str_imatch("", "");
constant str_imatch_result1 : BOOLEAN := str_imatch("", (1 to 3 => C_POC_NUL));
constant str_imatch_result2 : BOOLEAN := str_imatch("Hello", "hello");
constant str_imatch_result3 : BOOLEAN := str_imatch("Hello", "Hello");
constant str_imatch_result4 : BOOLEAN := str_imatch("Hello World", "Hello");
constant str_imatch_result5 : BOOLEAN := str_imatch("Hello", "Hello World");
constant str_imatch_result6 : BOOLEAN := str_imatch("Hello", "Hello" & (1 to 3 => C_POC_NUL));
begin
process
begin
-- raw_format_slv_dec tests
tbAssert((raw_format_slv_dec_result0 = "18"), "raw_format_slv_dec(0x12)=" & raw_format_slv_dec_result0 & " Expected='18'");
tbAssert((raw_format_slv_dec_result1 = "13398"), "raw_format_slv_dec(0x3456)=" & raw_format_slv_dec_result1 & " Expected='13398'");
tbAssert((raw_format_slv_dec_result2 = "305419896"), "raw_format_slv_dec(0x12345678)=" & raw_format_slv_dec_result2 & " Expected='305419896'");
tbAssert((raw_format_slv_dec_result3 = "11651590505119483816"), "raw_format_slv_dec(0xA1b2c3d4e5f607a8)=" & raw_format_slv_dec_result3 & " Expected='11651590505119483816'");
-- str_length tests
tbAssert((str_length_result0 = 0), "str_length('')=" & INTEGER'image(str_length_result0) & " Expected=0");
tbAssert((str_length_result1 = 0), "str_length('\0\0\0')=" & INTEGER'image(str_length_result1) & " Expected=0");
tbAssert((str_length_result2 = 5), "str_length('Hello')=" & INTEGER'image(str_length_result2) & " Expected=5");
tbAssert((str_length_result3 = 5), "str_length('Hello\0\0\0')=" & INTEGER'image(str_length_result3) & " Expected=5");
-- str_match tests
tbAssert((str_match_result0 = TRUE), "str_match('', '')=" & BOOLEAN'image(str_match_result0) & " Expected=TRUE");
tbAssert((str_match_result1 = TRUE), "str_match('', '\0\0\0')=" & BOOLEAN'image(str_match_result1) & " Expected=TRUE");
tbAssert((str_match_result2 = FALSE), "str_match('Hello', 'hello')=" & BOOLEAN'image(str_match_result2) & " Expected=FALSE");
tbAssert((str_match_result3 = TRUE), "str_match('Hello', 'Hello')=" & BOOLEAN'image(str_match_result3) & " Expected=TRUE");
tbAssert((str_match_result4 = FALSE), "str_match('Hello World', 'Hello')=" & BOOLEAN'image(str_match_result4) & " Expected=FALSE");
tbAssert((str_match_result5 = FALSE), "str_match('Hello', 'Hello World')=" & BOOLEAN'image(str_match_result5) & " Expected=FALSE");
tbAssert((str_match_result6 = TRUE), "str_match('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_match_result6) & " Expected=TRUE");
-- str_imatch tests
tbAssert((str_imatch_result0 = TRUE), "str_imatch('', '')=" & BOOLEAN'image(str_imatch_result0) & " Expected=TRUE");
tbAssert((str_imatch_result1 = TRUE), "str_imatch('', '\0\0\0')=" & BOOLEAN'image(str_imatch_result1) & " Expected=TRUE");
tbAssert((str_imatch_result2 = TRUE), "str_imatch('Hello', 'hello')=" & BOOLEAN'image(str_imatch_result2) & " Expected=TRUE");
tbAssert((str_imatch_result3 = TRUE), "str_imatch('Hello', 'Hello')=" & BOOLEAN'image(str_imatch_result3) & " Expected=TRUE");
tbAssert((str_imatch_result4 = FALSE), "str_imatch('Hello World', 'Hello')=" & BOOLEAN'image(str_imatch_result4) & " Expected=FALSE");
tbAssert((str_imatch_result5 = FALSE), "str_imatch('Hello', 'Hello World')=" & BOOLEAN'image(str_imatch_result5) & " Expected=FALSE");
tbAssert((str_imatch_result6 = TRUE), "str_imatch('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_imatch_result6) & " Expected=TRUE");
-- str_pos tests
-- str_ipos tests
-- str_find tests
-- str_ifind tests
-- str_replace tests
-- str_substr tests
-- str_ltrim tests
-- str_rtrim tests
-- str_trim tests
-- str_toLower tests
-- str_toUpper tests
-- simulation completed
-- Report overall simulation result
tbPrintResult;
wait;
end process;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Tests global constants, functions and settings
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
entity strings_tb is
end strings_tb;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
use PoC.simulation.all;
architecture tb of strings_tb is
constant raw_format_slv_dec_result0 : STRING := raw_format_slv_dec(STD_LOGIC_VECTOR'(x"12"));
constant raw_format_slv_dec_result1 : STRING := raw_format_slv_dec(x"3456");
constant raw_format_slv_dec_result2 : STRING := raw_format_slv_dec(x"12345678");
constant raw_format_slv_dec_result3 : STRING := raw_format_slv_dec(x"A1B2C3D4E5F607A8");
constant str_length_result0 : INTEGER := str_length("");
constant str_length_result1 : INTEGER := str_length((1 to 3 => C_POC_NUL));
constant str_length_result2 : INTEGER := str_length("Hello");
constant str_length_result3 : INTEGER := str_length("Hello" & (1 to 3 => C_POC_NUL));
constant str_match_result0 : BOOLEAN := str_match("", "");
constant str_match_result1 : BOOLEAN := str_match("", (1 to 3 => C_POC_NUL));
constant str_match_result2 : BOOLEAN := str_match("Hello", "hello");
constant str_match_result3 : BOOLEAN := str_match("Hello", "Hello");
constant str_match_result4 : BOOLEAN := str_match("Hello World", "Hello");
constant str_match_result5 : BOOLEAN := str_match("Hello", "Hello World");
constant str_match_result6 : BOOLEAN := str_match("Hello", "Hello" & (1 to 3 => C_POC_NUL));
constant str_imatch_result0 : BOOLEAN := str_imatch("", "");
constant str_imatch_result1 : BOOLEAN := str_imatch("", (1 to 3 => C_POC_NUL));
constant str_imatch_result2 : BOOLEAN := str_imatch("Hello", "hello");
constant str_imatch_result3 : BOOLEAN := str_imatch("Hello", "Hello");
constant str_imatch_result4 : BOOLEAN := str_imatch("Hello World", "Hello");
constant str_imatch_result5 : BOOLEAN := str_imatch("Hello", "Hello World");
constant str_imatch_result6 : BOOLEAN := str_imatch("Hello", "Hello" & (1 to 3 => C_POC_NUL));
begin
process
begin
-- raw_format_slv_dec tests
tbAssert((raw_format_slv_dec_result0 = "18"), "raw_format_slv_dec(0x12)=" & raw_format_slv_dec_result0 & " Expected='18'");
tbAssert((raw_format_slv_dec_result1 = "13398"), "raw_format_slv_dec(0x3456)=" & raw_format_slv_dec_result1 & " Expected='13398'");
tbAssert((raw_format_slv_dec_result2 = "305419896"), "raw_format_slv_dec(0x12345678)=" & raw_format_slv_dec_result2 & " Expected='305419896'");
tbAssert((raw_format_slv_dec_result3 = "11651590505119483816"), "raw_format_slv_dec(0xA1b2c3d4e5f607a8)=" & raw_format_slv_dec_result3 & " Expected='11651590505119483816'");
-- str_length tests
tbAssert((str_length_result0 = 0), "str_length('')=" & INTEGER'image(str_length_result0) & " Expected=0");
tbAssert((str_length_result1 = 0), "str_length('\0\0\0')=" & INTEGER'image(str_length_result1) & " Expected=0");
tbAssert((str_length_result2 = 5), "str_length('Hello')=" & INTEGER'image(str_length_result2) & " Expected=5");
tbAssert((str_length_result3 = 5), "str_length('Hello\0\0\0')=" & INTEGER'image(str_length_result3) & " Expected=5");
-- str_match tests
tbAssert((str_match_result0 = TRUE), "str_match('', '')=" & BOOLEAN'image(str_match_result0) & " Expected=TRUE");
tbAssert((str_match_result1 = TRUE), "str_match('', '\0\0\0')=" & BOOLEAN'image(str_match_result1) & " Expected=TRUE");
tbAssert((str_match_result2 = FALSE), "str_match('Hello', 'hello')=" & BOOLEAN'image(str_match_result2) & " Expected=FALSE");
tbAssert((str_match_result3 = TRUE), "str_match('Hello', 'Hello')=" & BOOLEAN'image(str_match_result3) & " Expected=TRUE");
tbAssert((str_match_result4 = FALSE), "str_match('Hello World', 'Hello')=" & BOOLEAN'image(str_match_result4) & " Expected=FALSE");
tbAssert((str_match_result5 = FALSE), "str_match('Hello', 'Hello World')=" & BOOLEAN'image(str_match_result5) & " Expected=FALSE");
tbAssert((str_match_result6 = TRUE), "str_match('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_match_result6) & " Expected=TRUE");
-- str_imatch tests
tbAssert((str_imatch_result0 = TRUE), "str_imatch('', '')=" & BOOLEAN'image(str_imatch_result0) & " Expected=TRUE");
tbAssert((str_imatch_result1 = TRUE), "str_imatch('', '\0\0\0')=" & BOOLEAN'image(str_imatch_result1) & " Expected=TRUE");
tbAssert((str_imatch_result2 = TRUE), "str_imatch('Hello', 'hello')=" & BOOLEAN'image(str_imatch_result2) & " Expected=TRUE");
tbAssert((str_imatch_result3 = TRUE), "str_imatch('Hello', 'Hello')=" & BOOLEAN'image(str_imatch_result3) & " Expected=TRUE");
tbAssert((str_imatch_result4 = FALSE), "str_imatch('Hello World', 'Hello')=" & BOOLEAN'image(str_imatch_result4) & " Expected=FALSE");
tbAssert((str_imatch_result5 = FALSE), "str_imatch('Hello', 'Hello World')=" & BOOLEAN'image(str_imatch_result5) & " Expected=FALSE");
tbAssert((str_imatch_result6 = TRUE), "str_imatch('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_imatch_result6) & " Expected=TRUE");
-- str_pos tests
-- str_ipos tests
-- str_find tests
-- str_ifind tests
-- str_replace tests
-- str_substr tests
-- str_ltrim tests
-- str_rtrim tests
-- str_trim tests
-- str_toLower tests
-- str_toUpper tests
-- simulation completed
-- Report overall simulation result
tbPrintResult;
wait;
end process;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_gnd_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_gnd_GN is
Begin
output <= '0';
end architecture; |
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_block.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the block level VHDL design for the Tri-Mode
-- Ethernet MAC Example Design.
--
-- This block level:
--
-- * instantiates all clock enable logic required to operate the
-- TEMAC and its example design;
--
-- * instantiates appropriate PHY interface module (GMII/MII/RGMII)
-- as required based on the user configuration;
--
-- Please refer to the Datasheet, Getting Started Guide, and
-- the Tri-Mode Ethernet MAC User Gude for further information.
--
--
-- -----------------------------------------|
-- | BLOCK LEVEL WRAPPER |
-- | |
-- | --------------------- |
-- | | ETHERNET MAC | |
-- | | CORE | |
-- | | | |
-- --|--->| Tx Tx |-------------->|
-- | | AXI PHY | |
-- | | I/F I/F | |
-- | | | |
-- | | | |
-- | | | |
-- | | Rx Rx | |
-- | | AXI PHY | |
-- <-|----| I/F I/F |<--------------|
-- | | | |
-- | --------------------- |
-- | |
-- | clock enable logic |
-- | |
-- -----------------------------------------|
--
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the block level example design.
--------------------------------------------------------------------------------
entity temac_10_100_1000_block is
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic;
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- Configuration Vector
-----------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end temac_10_100_1000_block;
architecture wrapper of temac_10_100_1000_block is
-----------------------------------------------------------------------------
-- Component Declaration for TEMAC (the Tri-Mode EMAC core).
-----------------------------------------------------------------------------
component temac_10_100_1000
port(
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
gtx_clk : in std_logic;
clk_enable : in std_logic;
-- Receiver Interface
----------------------------
-- rx_axi_clk : in std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- rx_enable : in std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Transmitter Interface
-------------------------------
-- tx_axi_clk : in std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
-- tx_enable : in std_logic;
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- Current Speed Indication
---------------------------
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- Physical Interface of the core
--------------------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- Configuration Vector
-----------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component temac_10_100_1000_sync_block
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component temac_10_100_1000_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- internal signals used in this block level wrapper.
------------------------------------------------------------------------------
attribute keep : string;
signal glbl_rst : std_logic;
signal gmii_tx_en_int : std_logic; -- Internal gmii_tx_en signal.
signal gmii_tx_er_int : std_logic; -- Internal gmii_tx_er signal.
signal gmii_txd_int : std_logic_vector(7 downto 0); -- Internal gmii_txd signal.
signal gmii_rx_dv_int : std_logic; -- gmii_rx_dv registered in IOBs.
signal gmii_rx_er_int : std_logic; -- gmii_rx_er registered in IOBs.
signal gmii_rxd_int : std_logic_vector(7 downto 0); -- gmii_rxd registered in IOBs.
signal txspeedis10100 : std_logic; -- MAC speed setting resampled on the transmitter clock
signal rxspeedis10100 : std_logic; -- MAC speed setting resampled on the receiver clock
signal tx_reset_int : std_logic; -- Synchronous reset in the MAC and rgmii Tx domain
signal rx_reset_int : std_logic; -- Synchronous reset in the MAC and rgmii Rx domain
signal rx_statistics_vector_int : std_logic_vector(27 downto 0);
signal rx_statistics_valid_int : std_logic;
signal tx_statistics_vector_int : std_logic_vector(31 downto 0);
signal tx_statistics_valid_int : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_addr : std_logic_vector(31 downto 0);
signal bus2ip_cs : std_logic;
signal bus2ip_rdce : std_logic;
signal bus2ip_wrce : std_logic;
signal bus2ip_data : std_logic_vector(31 downto 0);
signal ip2bus_data : std_logic_vector(31 downto 0);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal tx_axis_mac_tuser_int : std_logic_vector(0 downto 0);
begin
-- assign outputs
rx_reset <= rx_reset_int;
tx_reset <= tx_reset_int;
glbl_rst <= not glbl_rstn;
rx_statistics_vector <= rx_statistics_vector_int;
rx_statistics_valid <= rx_statistics_valid_int;
tx_statistics_vector <= tx_statistics_vector_int;
tx_statistics_valid <= tx_statistics_valid_int;
gmii_tx_en <= gmii_tx_en_int;
gmii_tx_er <= gmii_tx_er_int;
gmii_txd <= gmii_txd_int;
gmii_rx_dv_int <= gmii_rx_dv;
gmii_rx_er_int <= gmii_rx_er;
gmii_rxd_int <= gmii_rxd;
-----------------------------------------------------------------------------
-- Instantiate the TEMAC core
-----------------------------------------------------------------------------
trimac_core : temac_10_100_1000
port map (
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
gtx_clk => gtx_clk,
clk_enable => clk_enable,
-- Receiver Interface
-- rx_axi_clk => gtx_clk,
rx_reset => rx_reset_int,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Receiver Statistics
rx_statistics_vector => rx_statistics_vector_int,
rx_statistics_valid => rx_statistics_valid_int,
-- Transmitter Interface
-- tx_axi_clk => gtx_clk,
tx_reset => tx_reset_int,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser_int,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_ifg_delay => tx_ifg_delay,
-- tx_enable => clk_enable,
-- Transmitter Statistics
tx_statistics_vector => tx_statistics_vector_int,
tx_statistics_valid => tx_statistics_valid_int,
-- MAC Control Interface
pause_req => pause_req,
pause_val => pause_val,
-- Current Speed Indication
speedis100 => speedis100,
speedis10100 => speedis10100,
-- Physical Interface of the core
gmii_txd => gmii_txd_int,
gmii_tx_en => gmii_tx_en_int,
gmii_tx_er => gmii_tx_er_int,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
-- Configuration Vectors
rx_configuration_vector => rx_configuration_vector,
tx_configuration_vector => tx_configuration_vector);
tx_axis_mac_tuser_int(0) <= tx_axis_mac_tuser;
end wrapper;
|
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_block.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the block level VHDL design for the Tri-Mode
-- Ethernet MAC Example Design.
--
-- This block level:
--
-- * instantiates all clock enable logic required to operate the
-- TEMAC and its example design;
--
-- * instantiates appropriate PHY interface module (GMII/MII/RGMII)
-- as required based on the user configuration;
--
-- Please refer to the Datasheet, Getting Started Guide, and
-- the Tri-Mode Ethernet MAC User Gude for further information.
--
--
-- -----------------------------------------|
-- | BLOCK LEVEL WRAPPER |
-- | |
-- | --------------------- |
-- | | ETHERNET MAC | |
-- | | CORE | |
-- | | | |
-- --|--->| Tx Tx |-------------->|
-- | | AXI PHY | |
-- | | I/F I/F | |
-- | | | |
-- | | | |
-- | | | |
-- | | Rx Rx | |
-- | | AXI PHY | |
-- <-|----| I/F I/F |<--------------|
-- | | | |
-- | --------------------- |
-- | |
-- | clock enable logic |
-- | |
-- -----------------------------------------|
--
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the block level example design.
--------------------------------------------------------------------------------
entity temac_10_100_1000_block is
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic;
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- Configuration Vector
-----------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end temac_10_100_1000_block;
architecture wrapper of temac_10_100_1000_block is
-----------------------------------------------------------------------------
-- Component Declaration for TEMAC (the Tri-Mode EMAC core).
-----------------------------------------------------------------------------
component temac_10_100_1000
port(
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
gtx_clk : in std_logic;
clk_enable : in std_logic;
-- Receiver Interface
----------------------------
-- rx_axi_clk : in std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- rx_enable : in std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Transmitter Interface
-------------------------------
-- tx_axi_clk : in std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
-- tx_enable : in std_logic;
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- Current Speed Indication
---------------------------
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- Physical Interface of the core
--------------------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- Configuration Vector
-----------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component temac_10_100_1000_sync_block
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component temac_10_100_1000_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- internal signals used in this block level wrapper.
------------------------------------------------------------------------------
attribute keep : string;
signal glbl_rst : std_logic;
signal gmii_tx_en_int : std_logic; -- Internal gmii_tx_en signal.
signal gmii_tx_er_int : std_logic; -- Internal gmii_tx_er signal.
signal gmii_txd_int : std_logic_vector(7 downto 0); -- Internal gmii_txd signal.
signal gmii_rx_dv_int : std_logic; -- gmii_rx_dv registered in IOBs.
signal gmii_rx_er_int : std_logic; -- gmii_rx_er registered in IOBs.
signal gmii_rxd_int : std_logic_vector(7 downto 0); -- gmii_rxd registered in IOBs.
signal txspeedis10100 : std_logic; -- MAC speed setting resampled on the transmitter clock
signal rxspeedis10100 : std_logic; -- MAC speed setting resampled on the receiver clock
signal tx_reset_int : std_logic; -- Synchronous reset in the MAC and rgmii Tx domain
signal rx_reset_int : std_logic; -- Synchronous reset in the MAC and rgmii Rx domain
signal rx_statistics_vector_int : std_logic_vector(27 downto 0);
signal rx_statistics_valid_int : std_logic;
signal tx_statistics_vector_int : std_logic_vector(31 downto 0);
signal tx_statistics_valid_int : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_addr : std_logic_vector(31 downto 0);
signal bus2ip_cs : std_logic;
signal bus2ip_rdce : std_logic;
signal bus2ip_wrce : std_logic;
signal bus2ip_data : std_logic_vector(31 downto 0);
signal ip2bus_data : std_logic_vector(31 downto 0);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal tx_axis_mac_tuser_int : std_logic_vector(0 downto 0);
begin
-- assign outputs
rx_reset <= rx_reset_int;
tx_reset <= tx_reset_int;
glbl_rst <= not glbl_rstn;
rx_statistics_vector <= rx_statistics_vector_int;
rx_statistics_valid <= rx_statistics_valid_int;
tx_statistics_vector <= tx_statistics_vector_int;
tx_statistics_valid <= tx_statistics_valid_int;
gmii_tx_en <= gmii_tx_en_int;
gmii_tx_er <= gmii_tx_er_int;
gmii_txd <= gmii_txd_int;
gmii_rx_dv_int <= gmii_rx_dv;
gmii_rx_er_int <= gmii_rx_er;
gmii_rxd_int <= gmii_rxd;
-----------------------------------------------------------------------------
-- Instantiate the TEMAC core
-----------------------------------------------------------------------------
trimac_core : temac_10_100_1000
port map (
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
gtx_clk => gtx_clk,
clk_enable => clk_enable,
-- Receiver Interface
-- rx_axi_clk => gtx_clk,
rx_reset => rx_reset_int,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Receiver Statistics
rx_statistics_vector => rx_statistics_vector_int,
rx_statistics_valid => rx_statistics_valid_int,
-- Transmitter Interface
-- tx_axi_clk => gtx_clk,
tx_reset => tx_reset_int,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser_int,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_ifg_delay => tx_ifg_delay,
-- tx_enable => clk_enable,
-- Transmitter Statistics
tx_statistics_vector => tx_statistics_vector_int,
tx_statistics_valid => tx_statistics_valid_int,
-- MAC Control Interface
pause_req => pause_req,
pause_val => pause_val,
-- Current Speed Indication
speedis100 => speedis100,
speedis10100 => speedis10100,
-- Physical Interface of the core
gmii_txd => gmii_txd_int,
gmii_tx_en => gmii_tx_en_int,
gmii_tx_er => gmii_tx_er_int,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
-- Configuration Vectors
rx_configuration_vector => rx_configuration_vector,
tx_configuration_vector => tx_configuration_vector);
tx_axis_mac_tuser_int(0) <= tx_axis_mac_tuser;
end wrapper;
|
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array :=
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"); -- Comment
begin
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1061.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01061ent IS
END c06s04b00x00p03n02i01061ent;
ARCHITECTURE c06s04b00x00p03n02i01061arch OF c06s04b00x00p03n02i01061ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type ENUM1 is (EN1, EN2, EN3);
type A11 is array (THREE) of BOOLEAN;
type A32 is array (ENUM1, ENUM1) of A11;
variable V1 : BOOLEAN;
variable V32: A32 ;
BEGIN
V1 := V32(EN2)(2); -- ONE LESS
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01061 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01061arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1061.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01061ent IS
END c06s04b00x00p03n02i01061ent;
ARCHITECTURE c06s04b00x00p03n02i01061arch OF c06s04b00x00p03n02i01061ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type ENUM1 is (EN1, EN2, EN3);
type A11 is array (THREE) of BOOLEAN;
type A32 is array (ENUM1, ENUM1) of A11;
variable V1 : BOOLEAN;
variable V32: A32 ;
BEGIN
V1 := V32(EN2)(2); -- ONE LESS
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01061 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01061arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1061.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01061ent IS
END c06s04b00x00p03n02i01061ent;
ARCHITECTURE c06s04b00x00p03n02i01061arch OF c06s04b00x00p03n02i01061ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type ENUM1 is (EN1, EN2, EN3);
type A11 is array (THREE) of BOOLEAN;
type A32 is array (ENUM1, ENUM1) of A11;
variable V1 : BOOLEAN;
variable V32: A32 ;
BEGIN
V1 := V32(EN2)(2); -- ONE LESS
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01061 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01061arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue93 is
port (foo : out std_logic;
bar : out std_logic);
end ;
architecture beh of issue93 is
begin
(foo, bar) <= "10" + "01"; -- crashes
end architecture;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library hynix;
use hynix.components.all;
use work.debug.all;
use work.config.all;
library hynix;
use hynix.components.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 8 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk_vga : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic_vector(1 downto 0);
signal ddr_clkb : std_logic_vector(1 downto 0);
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(3 downto 0); -- dm
signal ddr_dqs : std_logic_vector(3 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(3 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(1 downto 0); -- bank address
signal ddr_dq : std_logic_vector(31 downto 0); -- data
signal ddr_dq2 : std_logic_vector(31 downto 0); -- data
signal ddr_odt : std_logic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(2 downto 0);
signal brdyn : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk_vga <= not clk_vga after 20 ns;
rst <= '1', '0' after 100 ns;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => rst,
reset_o1 => rstn1,
reset_o2 => rstn2,
clk_in => clk,
clk_vga => clk_vga,
errorn => error,
-- PROM
address => address(23 downto 0),
data => data(31 downto 24),
romsn => romsn,
oen => oen,
writen => writen,
iosn => iosn,
testdata => data(23 downto 0),
-- DDR2
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_clk_fb_out => ddr_clk_fb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_we => ddr_we,
ddr_ras => ddr_ras,
ddr_cas => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_odt => ddr_odt,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(3 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxdt(3 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- SVGA
vid_hsync => vid_hsync,
vid_vsync => vid_vsync,
vid_r => vid_r,
vid_g => vid_g,
vid_b => vid_b,
-- SPI flash select
spi_sel_n => spi_sel_n,
spi_clk => spi_clk,
spi_mosi => spi_mosi,
-- Output signals for LEDs
led => led
);
ddr2mem : if (CFG_DDR2SP /= 0) generate
ddr2mem0 : for i in 0 to 1 generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => true, PUSCheckFlag => false,
index => 1-i, bbits => 32, fname => sdramfile)
port map (DQ => ddr_dq2(i*16+15 downto i*16),
LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2),
UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1),
LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas,
RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba,
ADDR => ddr_ad(12 downto 0), CKE => ddr_cke,
CLK => ddr_clk(i), CLKB => ddr_clkb(i), UDM => ddr_dm(i*2+1));
end generate;
ddr2delay0 : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 1.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
prom0 : sram
generic map (index => 6, abits => 24, fname => promfile)
port map (address(23 downto 0), data(31 downto 24), romsn, writen, oen);
phy0 : if (CFG_GRETH = 1) generate
etxdt(7 downto 4) <= "0000";
emdio <= 'H';
p0: phy
generic map (address => 1)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, '0');
end generate;
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0) -- Dual output is not supported in this design
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- DMA (single- and multiword) mode access controller ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 9th, 2001. Initial release
--
-- CVS Log
--
-- $Id: atahost_dma_actrl.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_dma_actrl.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
--
-- Host accesses to DMA ports are 32bit wide. Accesses are made by 2 consecutive 16bit accesses to the ATA
-- device's DataPort. The MSB HostData(31:16) is transfered first, then the LSB HostData(15:0) is transfered.
--
---------------------------
-- DMA Access Controller --
---------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity atahost_dma_actrl is
generic(
tech : integer := 0; -- fifo mem technology
fdepth : integer := 8; -- DMA fifo depth
TWIDTH : natural := 8; -- counter width
-- DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
IDEctrl_rst : in std_logic; -- IDE control register bit0, 'rst'
sel : in std_logic; -- DMA buffers selected
we : in std_logic; -- write enable input
ack : out std_logic; -- acknowledge output
dev0_Tm,
dev0_Td,
dev0_Teoc : in std_logic_vector(7 downto 0); -- DMA mode timing device 0
dev1_Tm,
dev1_Td,
dev1_Teoc : in std_logic_vector(7 downto 0); -- DMA mode timing device 1
DMActrl_DMAen,
DMActrl_dir,
DMActrl_Bytesw, --Jagre 2006-12-04, byte swap ATA data
DMActrl_BeLeC0,
DMActrl_BeLeC1 : in std_logic; -- control register settings
TxD : in std_logic_vector(31 downto 0); -- DMA transmit data
TxFull : out std_logic; -- DMA transmit buffer full
TxEmpty : out std_logic;
RxQ : out std_logic_vector(31 downto 0); -- DMA receive data
RxEmpty : out std_logic; -- DMA receive buffer empty
RxFull : out std_logic; -- DMA receive buffer full
DMA_req : out std_logic; -- DMA request to external DMA engine
DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine
DMARQ : in std_logic; -- ATA devices request DMA transfer
SelDev : in std_logic; -- Selected device
Go : in std_logic; -- Start transfer sequence
Done : out std_logic; -- Transfer sequence done
DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
DDo : out std_logic_vector(15 downto 0); -- Data towards ATA DD bus
DIOR,
DIOW : out std_logic
);
end entity atahost_dma_actrl;
architecture structural of atahost_dma_actrl is
--
-- component declarations
--
component atahost_dma_tctrl is
generic(
TWIDTH : natural := 8; -- counter width
-- DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 6; -- 70ns
DMA_mode0_Td : natural := 28; -- 290ns
DMA_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- timing register settings
Tm : in std_logic_vector(TWIDTH -1 downto 0); -- Tm time (in clk-ticks)
Td : in std_logic_vector(TWIDTH -1 downto 0); -- Td time (in clk-ticks)
Teoc : in std_logic_vector(TWIDTH -1 downto 0); -- end of cycle time
-- control signals
go : in std_logic; -- DMA controller selected (strobe signal)
we : in std_logic; -- DMA direction '1' = write, '0' = read
-- return signals
done : out std_logic; -- finished cycle
dstrb : out std_logic; -- data strobe
-- ATA signals
DIOR, -- IOread signal, active high
DIOW : out std_logic -- IOwrite signal, active high
);
end component atahost_dma_tctrl;
component atahost_reg_buf is
generic (
WIDTH : natural := 8
);
port(
clk : in std_logic;
nReset : in std_logic;
rst : in std_logic;
D : in std_logic_vector(WIDTH -1 downto 0);
Q : out std_logic_vector(WIDTH -1 downto 0);
rd : in std_logic;
wr : in std_logic;
valid : out std_logic
);
end component atahost_reg_buf;
component atahost_dma_fifo is
generic(tech : integer:=0;
abits : integer:=3;
dbits : integer:=32;
depth : integer:=8);
port( clk : in std_logic;
reset : in std_logic;
write_enable : in std_logic;
read_enable : in std_logic;
data_in : in std_logic_vector(dbits-1 downto 0);
data_out : out std_logic_vector(dbits-1 downto 0);
write_error : out std_logic:='0';
read_error : out std_logic:='0';
level : out natural range 0 to depth;
empty : out std_logic:='1';
full : out std_logic:='0'
);
end component atahost_dma_fifo;
signal Tdone, Tfw : std_logic;
signal RxWr, TxRd : std_logic;
signal assync_TxRd, s_TxFull : std_logic; -----------------------Erik Jagre 2006-10-27
signal dstrb, rd_dstrb, wr_dstrb : std_logic;
signal TxbufQ, RxbufD : std_logic_vector(31 downto 0);
signal iRxEmpty : std_logic;
constant abits : integer := Log2(fdepth);
begin
-- note: *fw = *first_word, *lw = *last_word
--
-- generate DDi/DDo controls
--
gen_DMA_sigs: block
signal writeDfw, writeDlw : std_logic_vector(15 downto 0);
signal readDfw, readDlw : std_logic_vector(15 downto 0);
signal BeLeC : std_logic; -- BigEndian <-> LittleEndian conversion
begin
-- generate byte_swap signal
BeLeC <= (not SelDev and DMActrl_BeLeC0) or (SelDev and DMActrl_BeLeC1);
-- generate Tfw (Transfering first word)
gen_Tfw: process(clk, nReset)
begin
if (nReset = '0') then
Tfw <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
Tfw <= '0';
else
Tfw <= go or (Tfw and not Tdone);
end if;
end if;
end process gen_Tfw;
-- transmit data part
gen_writed_pipe:process(clk)
begin
if (clk'event and clk = '1') then
if (TxRd = '1') then -- reload registers
if (BeLeC = '1') then -- Do big<->little endian conversion
writeDfw(15 downto 8) <= TxbufQ( 7 downto 0); -- TxbufQ = data from transmit buffer
writeDfw( 7 downto 0) <= TxbufQ(15 downto 8);
writeDlw(15 downto 8) <= TxbufQ(23 downto 16);
writeDlw( 7 downto 0) <= TxbufQ(31 downto 24);
else -- don't do big<->little endian conversion
writeDfw <= TxbufQ(31 downto 16);
writeDlw <= TxbufQ(15 downto 0);
end if;
elsif (wr_dstrb = '1') then -- next word to transfer
writeDfw <= writeDlw;
end if;
end if;
end process gen_writed_pipe;
--Jagre 2006-12-04
--swap byte orderD when MActrl_Bytesw is set to '1'
DDo(15 downto 8) <= writeDfw(15 downto 8) when DMActrl_Bytesw='0' else
writeDfw(7 downto 0);
DDo(7 downto 0) <= writeDfw(7 downto 0) when DMActrl_Bytesw='0' else
writeDfw(15 downto 8);
--DDo <= writeDfw; -- assign DMA data out
-- generate transmit register read request
gen_Tx_rreq: process(clk, nReset)
begin
if (nReset = '0') then
TxRd <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
TxRd <= '0';
else
TxRd <= go and DMActrl_dir;
end if;
end if;
end process gen_Tx_rreq;
assync_TxRd <= go and DMActrl_dir; --Jagre 2006-12-14
-- receive
gen_readd_pipe:process(clk)
begin
if (clk'event and clk = '1') then
if (rd_dstrb = '1') then
readDfw <= readDlw; -- shift previous read word to msb
if (BeLeC = '1' xor DMActrl_Bytesw = '1') then -- swap bytes, DMActrl_Bytesw added 2006-12-04, Jagre
readDlw(15 downto 8) <= DDi( 7 downto 0);
readDlw( 7 downto 0) <= DDi(15 downto 8);
else -- don't swap bytes
readDlw <= DDi;
end if;
end if;
end if;
end process gen_readd_pipe;
-- RxD = data to receive buffer
RxbufD <= (readDfw & readDlw) when (BeLeC = '0') else (readDlw & readDfw);
-- generate receive register write request
gen_Rx_wreq: process(clk, nReset)
begin
if (nReset = '0') then
RxWr <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
RxWr <= '0';
else
RxWr <= not Tfw and rd_dstrb;
end if;
end if;
end process gen_Rx_wreq;
end block gen_DMA_sigs;
--
-- Hookup DMA read / write buffers
--
gen_DMAbuf: block
signal DMArst : std_logic;
signal RxRd, TxWr : std_logic;
begin
-- generate DMA reset signal
DMArst <= rst or IDEctrl_rst;
Txfifo: atahost_dma_fifo
generic map(dbits=>32,depth=>fdepth,tech=>tech,abits=>abits)
port map( clk => clk,
reset => DMArst,
write_enable => TxWr,
read_enable => assync_TxRd,
data_in => TxD,
data_out => TxbufQ,
write_error => open,
read_error => open,
level => open,
empty => TxEmpty,
full => s_TxFull
);
Rxfifo: atahost_dma_fifo
generic map(dbits=>32,depth=>fdepth,tech=>tech,abits=>abits)
port map( clk => clk,
reset => DMArst,
write_enable => RxWr,
read_enable => RxRd,
data_in => RxbufD,
data_out => RxQ,
write_error => open,
read_error => open,
level => open,
empty => iRxEmpty,
full => RxFull
);
RxEmpty <= iRxEmpty; -- avoid 'cannot associate OUT port with BUFFER port' error
--
-- generate DMA buffer access signals
--
RxRd <= sel and not we and not iRxEmpty;
TxWr <= sel and we and not s_TxFull;
ack <= RxRd or TxWr; -- DMA buffer access acknowledge
end block gen_DMAbuf;
--
-- generate request signal for external DMA engine
--
gen_DMA_req: block
signal hgo : std_logic;
signal iDMA_req : std_logic;
signal request : std_logic;
begin
-- generate hold-go
gen_hgo : process(clk, nReset)
begin
if (nReset = '0') then
hgo <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
hgo <= '0';
else
hgo <= go or (hgo and not (wr_dstrb and not Tfw) and DMActrl_dir);
end if;
end if;
end process gen_hgo;
request <= (DMActrl_dir and DMARQ and not s_TxFull and not hgo) or not iRxEmpty;
process(clk, nReset)
begin
if (nReset = '0') then
iDMA_req <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
iDMA_req <= '0';
else
iDMA_req <= DMActrl_DMAen and not DMA_ack and (request or iDMA_req);
-- DMA_req <= (DMActrl_DMAen and DMActrl_dir and DMARQ and not TxFull and not hgo) or not iRxEmpty;
end if;
end if;
end process;
DMA_req <= iDMA_req;
end block gen_DMA_req;
--
-- DMA timing controller
--
DMA_timing_ctrl: block
signal Tm, Td, Teoc, Tdmack_ext : std_logic_vector(TWIDTH -1 downto 0);
signal dTfw, igo : std_logic;
begin
--
-- generate internal GO signal
--
gen_igo : process(clk, nReset)
begin
if (nReset = '0') then
igo <= '0';
dTfw <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
igo <= '0';
dTfw <= '0';
else
igo <= go or (not Tfw and dTfw);
dTfw <= Tfw;
end if;
end if;
end process gen_igo;
--
-- select timing settings for the addressed device
--
sel_dev_t: process(clk)
begin
if (clk'event and clk = '1') then
if (SelDev = '1') then -- device1 selected
Tm <= dev1_Tm;
Td <= dev1_Td;
Teoc <= dev1_Teoc;
else -- device0 selected
Tm <= dev0_Tm;
Td <= dev0_Td;
Teoc <= dev0_Teoc;
end if;
end if;
end process sel_dev_t;
--
-- hookup timing controller
--
DMA_timing_ctrl: atahost_dma_tctrl
generic map (
TWIDTH => TWIDTH,
DMA_mode0_Tm => DMA_mode0_Tm,
DMA_mode0_Td => DMA_mode0_Td,
DMA_mode0_Teoc => DMA_mode0_Teoc
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
Tm => Tm,
Td => Td,
Teoc => Teoc,
go => igo,
we => DMActrl_dir,
done => Tdone,
dstrb => dstrb,
DIOR => dior,
DIOW => diow
);
done <= Tdone and not Tfw; -- done transfering last word
rd_dstrb <= dstrb and not DMActrl_dir; -- read data strobe
wr_dstrb <= dstrb and DMActrl_dir; -- write data strobe
TxFull <= s_TxFull;
end block DMA_timing_ctrl;
end architecture structural;
|
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- DMA (single- and multiword) mode access controller ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 9th, 2001. Initial release
--
-- CVS Log
--
-- $Id: atahost_dma_actrl.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_dma_actrl.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
--
-- Host accesses to DMA ports are 32bit wide. Accesses are made by 2 consecutive 16bit accesses to the ATA
-- device's DataPort. The MSB HostData(31:16) is transfered first, then the LSB HostData(15:0) is transfered.
--
---------------------------
-- DMA Access Controller --
---------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity atahost_dma_actrl is
generic(
tech : integer := 0; -- fifo mem technology
fdepth : integer := 8; -- DMA fifo depth
TWIDTH : natural := 8; -- counter width
-- DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
IDEctrl_rst : in std_logic; -- IDE control register bit0, 'rst'
sel : in std_logic; -- DMA buffers selected
we : in std_logic; -- write enable input
ack : out std_logic; -- acknowledge output
dev0_Tm,
dev0_Td,
dev0_Teoc : in std_logic_vector(7 downto 0); -- DMA mode timing device 0
dev1_Tm,
dev1_Td,
dev1_Teoc : in std_logic_vector(7 downto 0); -- DMA mode timing device 1
DMActrl_DMAen,
DMActrl_dir,
DMActrl_Bytesw, --Jagre 2006-12-04, byte swap ATA data
DMActrl_BeLeC0,
DMActrl_BeLeC1 : in std_logic; -- control register settings
TxD : in std_logic_vector(31 downto 0); -- DMA transmit data
TxFull : out std_logic; -- DMA transmit buffer full
TxEmpty : out std_logic;
RxQ : out std_logic_vector(31 downto 0); -- DMA receive data
RxEmpty : out std_logic; -- DMA receive buffer empty
RxFull : out std_logic; -- DMA receive buffer full
DMA_req : out std_logic; -- DMA request to external DMA engine
DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine
DMARQ : in std_logic; -- ATA devices request DMA transfer
SelDev : in std_logic; -- Selected device
Go : in std_logic; -- Start transfer sequence
Done : out std_logic; -- Transfer sequence done
DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
DDo : out std_logic_vector(15 downto 0); -- Data towards ATA DD bus
DIOR,
DIOW : out std_logic
);
end entity atahost_dma_actrl;
architecture structural of atahost_dma_actrl is
--
-- component declarations
--
component atahost_dma_tctrl is
generic(
TWIDTH : natural := 8; -- counter width
-- DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 6; -- 70ns
DMA_mode0_Td : natural := 28; -- 290ns
DMA_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- timing register settings
Tm : in std_logic_vector(TWIDTH -1 downto 0); -- Tm time (in clk-ticks)
Td : in std_logic_vector(TWIDTH -1 downto 0); -- Td time (in clk-ticks)
Teoc : in std_logic_vector(TWIDTH -1 downto 0); -- end of cycle time
-- control signals
go : in std_logic; -- DMA controller selected (strobe signal)
we : in std_logic; -- DMA direction '1' = write, '0' = read
-- return signals
done : out std_logic; -- finished cycle
dstrb : out std_logic; -- data strobe
-- ATA signals
DIOR, -- IOread signal, active high
DIOW : out std_logic -- IOwrite signal, active high
);
end component atahost_dma_tctrl;
component atahost_reg_buf is
generic (
WIDTH : natural := 8
);
port(
clk : in std_logic;
nReset : in std_logic;
rst : in std_logic;
D : in std_logic_vector(WIDTH -1 downto 0);
Q : out std_logic_vector(WIDTH -1 downto 0);
rd : in std_logic;
wr : in std_logic;
valid : out std_logic
);
end component atahost_reg_buf;
component atahost_dma_fifo is
generic(tech : integer:=0;
abits : integer:=3;
dbits : integer:=32;
depth : integer:=8);
port( clk : in std_logic;
reset : in std_logic;
write_enable : in std_logic;
read_enable : in std_logic;
data_in : in std_logic_vector(dbits-1 downto 0);
data_out : out std_logic_vector(dbits-1 downto 0);
write_error : out std_logic:='0';
read_error : out std_logic:='0';
level : out natural range 0 to depth;
empty : out std_logic:='1';
full : out std_logic:='0'
);
end component atahost_dma_fifo;
signal Tdone, Tfw : std_logic;
signal RxWr, TxRd : std_logic;
signal assync_TxRd, s_TxFull : std_logic; -----------------------Erik Jagre 2006-10-27
signal dstrb, rd_dstrb, wr_dstrb : std_logic;
signal TxbufQ, RxbufD : std_logic_vector(31 downto 0);
signal iRxEmpty : std_logic;
constant abits : integer := Log2(fdepth);
begin
-- note: *fw = *first_word, *lw = *last_word
--
-- generate DDi/DDo controls
--
gen_DMA_sigs: block
signal writeDfw, writeDlw : std_logic_vector(15 downto 0);
signal readDfw, readDlw : std_logic_vector(15 downto 0);
signal BeLeC : std_logic; -- BigEndian <-> LittleEndian conversion
begin
-- generate byte_swap signal
BeLeC <= (not SelDev and DMActrl_BeLeC0) or (SelDev and DMActrl_BeLeC1);
-- generate Tfw (Transfering first word)
gen_Tfw: process(clk, nReset)
begin
if (nReset = '0') then
Tfw <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
Tfw <= '0';
else
Tfw <= go or (Tfw and not Tdone);
end if;
end if;
end process gen_Tfw;
-- transmit data part
gen_writed_pipe:process(clk)
begin
if (clk'event and clk = '1') then
if (TxRd = '1') then -- reload registers
if (BeLeC = '1') then -- Do big<->little endian conversion
writeDfw(15 downto 8) <= TxbufQ( 7 downto 0); -- TxbufQ = data from transmit buffer
writeDfw( 7 downto 0) <= TxbufQ(15 downto 8);
writeDlw(15 downto 8) <= TxbufQ(23 downto 16);
writeDlw( 7 downto 0) <= TxbufQ(31 downto 24);
else -- don't do big<->little endian conversion
writeDfw <= TxbufQ(31 downto 16);
writeDlw <= TxbufQ(15 downto 0);
end if;
elsif (wr_dstrb = '1') then -- next word to transfer
writeDfw <= writeDlw;
end if;
end if;
end process gen_writed_pipe;
--Jagre 2006-12-04
--swap byte orderD when MActrl_Bytesw is set to '1'
DDo(15 downto 8) <= writeDfw(15 downto 8) when DMActrl_Bytesw='0' else
writeDfw(7 downto 0);
DDo(7 downto 0) <= writeDfw(7 downto 0) when DMActrl_Bytesw='0' else
writeDfw(15 downto 8);
--DDo <= writeDfw; -- assign DMA data out
-- generate transmit register read request
gen_Tx_rreq: process(clk, nReset)
begin
if (nReset = '0') then
TxRd <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
TxRd <= '0';
else
TxRd <= go and DMActrl_dir;
end if;
end if;
end process gen_Tx_rreq;
assync_TxRd <= go and DMActrl_dir; --Jagre 2006-12-14
-- receive
gen_readd_pipe:process(clk)
begin
if (clk'event and clk = '1') then
if (rd_dstrb = '1') then
readDfw <= readDlw; -- shift previous read word to msb
if (BeLeC = '1' xor DMActrl_Bytesw = '1') then -- swap bytes, DMActrl_Bytesw added 2006-12-04, Jagre
readDlw(15 downto 8) <= DDi( 7 downto 0);
readDlw( 7 downto 0) <= DDi(15 downto 8);
else -- don't swap bytes
readDlw <= DDi;
end if;
end if;
end if;
end process gen_readd_pipe;
-- RxD = data to receive buffer
RxbufD <= (readDfw & readDlw) when (BeLeC = '0') else (readDlw & readDfw);
-- generate receive register write request
gen_Rx_wreq: process(clk, nReset)
begin
if (nReset = '0') then
RxWr <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
RxWr <= '0';
else
RxWr <= not Tfw and rd_dstrb;
end if;
end if;
end process gen_Rx_wreq;
end block gen_DMA_sigs;
--
-- Hookup DMA read / write buffers
--
gen_DMAbuf: block
signal DMArst : std_logic;
signal RxRd, TxWr : std_logic;
begin
-- generate DMA reset signal
DMArst <= rst or IDEctrl_rst;
Txfifo: atahost_dma_fifo
generic map(dbits=>32,depth=>fdepth,tech=>tech,abits=>abits)
port map( clk => clk,
reset => DMArst,
write_enable => TxWr,
read_enable => assync_TxRd,
data_in => TxD,
data_out => TxbufQ,
write_error => open,
read_error => open,
level => open,
empty => TxEmpty,
full => s_TxFull
);
Rxfifo: atahost_dma_fifo
generic map(dbits=>32,depth=>fdepth,tech=>tech,abits=>abits)
port map( clk => clk,
reset => DMArst,
write_enable => RxWr,
read_enable => RxRd,
data_in => RxbufD,
data_out => RxQ,
write_error => open,
read_error => open,
level => open,
empty => iRxEmpty,
full => RxFull
);
RxEmpty <= iRxEmpty; -- avoid 'cannot associate OUT port with BUFFER port' error
--
-- generate DMA buffer access signals
--
RxRd <= sel and not we and not iRxEmpty;
TxWr <= sel and we and not s_TxFull;
ack <= RxRd or TxWr; -- DMA buffer access acknowledge
end block gen_DMAbuf;
--
-- generate request signal for external DMA engine
--
gen_DMA_req: block
signal hgo : std_logic;
signal iDMA_req : std_logic;
signal request : std_logic;
begin
-- generate hold-go
gen_hgo : process(clk, nReset)
begin
if (nReset = '0') then
hgo <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
hgo <= '0';
else
hgo <= go or (hgo and not (wr_dstrb and not Tfw) and DMActrl_dir);
end if;
end if;
end process gen_hgo;
request <= (DMActrl_dir and DMARQ and not s_TxFull and not hgo) or not iRxEmpty;
process(clk, nReset)
begin
if (nReset = '0') then
iDMA_req <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
iDMA_req <= '0';
else
iDMA_req <= DMActrl_DMAen and not DMA_ack and (request or iDMA_req);
-- DMA_req <= (DMActrl_DMAen and DMActrl_dir and DMARQ and not TxFull and not hgo) or not iRxEmpty;
end if;
end if;
end process;
DMA_req <= iDMA_req;
end block gen_DMA_req;
--
-- DMA timing controller
--
DMA_timing_ctrl: block
signal Tm, Td, Teoc, Tdmack_ext : std_logic_vector(TWIDTH -1 downto 0);
signal dTfw, igo : std_logic;
begin
--
-- generate internal GO signal
--
gen_igo : process(clk, nReset)
begin
if (nReset = '0') then
igo <= '0';
dTfw <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
igo <= '0';
dTfw <= '0';
else
igo <= go or (not Tfw and dTfw);
dTfw <= Tfw;
end if;
end if;
end process gen_igo;
--
-- select timing settings for the addressed device
--
sel_dev_t: process(clk)
begin
if (clk'event and clk = '1') then
if (SelDev = '1') then -- device1 selected
Tm <= dev1_Tm;
Td <= dev1_Td;
Teoc <= dev1_Teoc;
else -- device0 selected
Tm <= dev0_Tm;
Td <= dev0_Td;
Teoc <= dev0_Teoc;
end if;
end if;
end process sel_dev_t;
--
-- hookup timing controller
--
DMA_timing_ctrl: atahost_dma_tctrl
generic map (
TWIDTH => TWIDTH,
DMA_mode0_Tm => DMA_mode0_Tm,
DMA_mode0_Td => DMA_mode0_Td,
DMA_mode0_Teoc => DMA_mode0_Teoc
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
Tm => Tm,
Td => Td,
Teoc => Teoc,
go => igo,
we => DMActrl_dir,
done => Tdone,
dstrb => dstrb,
DIOR => dior,
DIOW => diow
);
done <= Tdone and not Tfw; -- done transfering last word
rd_dstrb <= dstrb and not DMActrl_dir; -- read data strobe
wr_dstrb <= dstrb and DMActrl_dir; -- write data strobe
TxFull <= s_TxFull;
end block DMA_timing_ctrl;
end architecture structural;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 30-05-2016
-- Module Name: control.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity control is
port (clk : in std_logic;
cond : in std_logic;
op : in std_logic_vector (3 downto 0);
PCen : out std_logic;
PCwrite : out std_logic;
IorD : out std_logic_vector (1 downto 0);
memread : out std_logic;
memwrite : out std_logic;
memtoreg : out std_logic_vector (1 downto 0);
IRe : out std_logic;
PCscr : out std_logic_vector (1 downto 0);
ALUop : out std_logic_vector (3 downto 0);
ALUsrcB : out std_logic_vector (1 downto 0);
ALUsrcA : out std_logic_vector (1 downto 0);
AluFunc : out std_logic_vector (1 downto 0);
regdest : out std_logic_vector (1 downto 0);
regwrite : out std_logic);
end control;
architecture rtl of control is
type state is (RST, S0, S1, S2, S3, SR0, SI0, SI10, SI11, SI20, SI210, SI220, SI221, SI30, SI31, SJ0);
signal current_state, next_state : state := RST;
begin
process (clk)
begin
if clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
process(current_state)
begin
case current_state is
when RST =>
next_state <= S0;
when S0 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '1';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "01";
ALUop <= "1111";
ALUsrcB <= "01";
ALUsrcA <= "00";
AluFunc <= "00";
regdest <= "00";
regwrite <= '0';
next_state <= S1;
when S1 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '1';
PCscr <= "00";
ALUop <= "1111";
ALUsrcB <= "01";
ALUsrcA <= "00";
AluFunc <= "00";
regdest <= "00";
regwrite <= '0';
next_state <= S2;
when S2 =>
PCen <= '1';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "00";
ALUop <= "1111";
ALUsrcB <= "01";
ALUsrcA <= "00";
AluFunc <= "00";
regdest <= "00";
regwrite <= '0';
next_state <= S3;
when S3 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "01";
ALUop <= "1111";
ALUsrcB <= "01";
ALUsrcA <= "00";
AluFunc <= "01";
regdest <= "00";
regwrite <= '0';
if op = "1111" then
next_state <= SR0;
elsif op = "0000" then
next_state <= SJ0;
else
next_state <= SI0;
end if;
when SR0 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "00";
ALUop <= op;
ALUsrcB <= "00";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "01";
regwrite <= '1';
next_state <= S0;
when SJ0 =>
PCen <= '1';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "00";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "00";
regwrite <= '0';
next_state <= S0;
when SI0 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "00";
regwrite <= '0';
if op (3 downto 2) = "00" and op(1 downto 0) /= "00" then
next_state <= SI10;
elsif op (3 downto 2) = "01" and op(1 downto 0) /= "11" then
next_state <= SI10;
elsif op = "0111" or op = "1000" then
next_state <= SI20;
else
next_state <= SI30;
end if;
when SI10 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "00";
regwrite <= '0';
next_state <= SI11;
when SI11 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "00";
regwrite <= '1';
next_state <= S0;
when SI20 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "00";
regdest <= "00";
regwrite <= '0';
if op = "1000" then
next_state <= SI210;
end if;
if op = "0111" then
next_state <= SI220;
end if;
when SI210 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "01";
memread <= '0';
memwrite <= '1';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "00";
regdest <= "00";
regwrite <= '0';
next_state <= S0;
when SI220 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "01";
memread <= '1';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "00";
regwrite <= '0';
next_state <= SI221;
when SI221 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "01";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "01";
AluFunc <= "01";
regdest <= "00";
regwrite <= '1';
next_state <= S0;
when SI30 =>
PCen <= '0';
PCwrite <= '0';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "10";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "00";
AluFunc <= "10";
regdest <= "00";
regwrite <= '0';
if cond = '1' then
next_state <= SI31;
else
next_state <= S0;
end if;
when SI31 =>
PCen <= '0';
PCwrite <= '1';
IorD <= "00";
memread <= '0';
memwrite <= '0';
memtoreg <= "00";
IRe <= '0';
PCscr <= "00";
ALUop <= op;
ALUsrcB <= "10";
ALUsrcA <= "00";
AluFunc <= "01";
regdest <= "00";
regwrite <= '0';
next_state <= S0;
when others =>
next_state <= current_state;
end case;
end process;
end architecture rtl;
|
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal clk : std_logic;
signal counter : natural;
signal rst : std_logic;
begin
dut: entity work.ent
port map (
rst => rst,
clk => clk,
counter => counter);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
pulse;
assert counter = 0 severity failure;
rst <= '0';
pulse;
assert counter = 1 severity failure;
pulse;
assert counter = 2 severity failure;
pulse;
assert counter = 3 severity failure;
wait;
end process;
end behav;
|
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : DAC Model
-- Last update : 02.12.2013
-----------------------------------------------------------------
-- Libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity dac_model is
generic(
SYSTEM_CYCLE_TIME : time := 20 ns; -- 50 MHz
FILE_NAME_DUMP : string := "dac_dump.txt"
);
port(
-- Global Signals
end_simulation : in std_ulogic;
-- SPI Signals
spi_clk : in std_ulogic;
spi_mosi : in std_ulogic;
spi_cs_n : in std_ulogic;
-- DAC Signals
dac_ldac_n : in std_ulogic
);
end entity dac_model;
architecture sim of dac_model is
type dac_reg_t is array (0 to 1) of real;
signal rx : std_ulogic_vector(15 downto 0);
file file_dump : text open write_mode is FILE_NAME_DUMP;
begin
process
variable vref : real := 2.048;
variable dac_out : dac_reg_t;
variable dac_pre : dac_reg_t;
variable v_out : string(1 to 4);
variable outLine : line;
begin
dac_out := (others => (real(0)));
dac_pre := (others => (real(0)));
rx <= (others => '0');
loop
exit when end_simulation = '1';
if spi_cs_n = '0' then
for i in 0 to 15 loop
wait until spi_clk = '1';
rx <= rx(14 downto 0) & spi_mosi;
wait until spi_clk = '0';
end loop;
wait until spi_cs_n = '1';
if rx(13) = '1' then
dac_pre(to_integer(unsigned(rx(15 downto 15)))) := vref * real(to_integer(unsigned(rx(11 downto 4)))) / real(256);
else
dac_pre(to_integer(unsigned(rx(15 downto 15)))) := real(2) * vref * real(to_integer(unsigned(rx(11 downto 4)))) / real(256);
end if;
if dac_pre(to_integer(unsigned(rx(15 downto 15)))) > real(3.3) then
dac_pre(to_integer(unsigned(rx(15 downto 15)))) := real(3.3);
end if;
else
wait for SYSTEM_CYCLE_TIME;
end if;
if dac_ldac_n = '0' then
for i in 0 to 1 loop
if dac_pre(i) /= dac_out(i) then
dac_out(i) := dac_pre(i);
v_out := integer'image(integer(dac_out(i)*real(1000)));
write(outLine, "DAC" & integer'image(i) & " = " & v_out(1) & "." & v_out(2 to 4) & "V");
writeline(file_dump, outLine);
write(outLine, "[DAC] Setting output voltage of DAC" & integer'image(i) & " to " & v_out(1) & "." & v_out(2 to 4) & "V");
writeline(output, outLine);
end if;
end loop;
end if;
end loop;
file_close(file_dump);
wait;
end process;
end architecture sim; |
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