content
stringlengths 1
1.04M
⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
OevQvFsolXiIelwFTsJirV6Gbn6iqq2k558/BxYyB28z6OkU85T9HqNSCCKfNwP4wWWVkgv4GHAx
Jy0sN/6OCw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
dIYJawsr6cc7wucJUmqeKNx9RcAAdwvxb/0+8/MkD/yxO/GHE7ox5BMSIar4TGvN9RmtdLN0/Qlf
UJ4U6fSCLNEE2L+cLdo0TK+3cATagUATZF49wcN2Gt+IMvECvEHpqOzhEN9Pe61AjMFoWK1DmGd1
ol2/dF/uiDIeGSY1QKw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Umz29ds1G/359pCCXvaJxi73V8DX/ioC3NcFoPC/SPcFGzWa7G8h2ThMxyPfXJAhQJjSebl9fGDz
dIYTNUINO8B9xnoSwI5nSZq+WJthT/6f5Bcp4p1MqD244kjH/mVO5WRtoMSm+CUIRtojI0yFWB/T
6A6+4moYwJn2DzIGok9AVsQ3pmnqfjI3gpj4azqwY+WQDTbVZiIRPzYSqcJBqIxUb9DYJWdMkH64
rVMKUFKxLfIFvaoYZqtxG+NQBdYXIj20xO6xX2kuHcw3DvHYw9oMcwAQ2ylDpzXGS7g3gNmUR9UD
xxN6o7fHwNKPcDsYQAokyFHG62z5tKXsUSadsg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
pnAee803TJmFvFZoLC4XIJASlUZRXo/S7hEz3wrtiERaDmVjbkRRPWuiGVmgskihOAumT4MUKGZg
sM/hVBGHHnDHBONKQor7stSCullCDfm3Rbu8rmZhc7l+AUfnyJAESUh9xiox8ywwatYPnqwcGXPx
j95FPrW7pCG8i0dLOII=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
iXyE+SxITwpDwXoaBvO/onK49w+Tvz8LJvGpaCKtwDLw8dzSbW1q4wde8Rf8Jn5vAPHCPr4in186
YtVtwfzWJBMl8JW9zJmIP/dvNMQA9aIQBRwGuVpv/NzzwTzYQ6CsLiBj1WMe3MtgQ3vcnHi/L3R1
pNLJ6zAivALPSp+wqnPl7wJtSXIpBP/PKa1uFFmdMmRbViq17xygeziH7twe+s01beq4jP8obnyl
zF8RNKkQKgaG5Bj/QVdUBisFAnzrclRkCOyGnoF0af34byGOHv7XdGoOccq+cceJWb8Yd/svve49
nJpwSP+CysAMBELoxw59Ks7S7Rdwhmp9Q05xCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 89248)
`protect data_block
y8o9mpKG3xq4+7rclTtlyUiUYQh74vpgG/qbMuWuwSqCczeroC10EnmkPDSzbqRRfKxB2tAuJogk
cwIcrN8qx/rNTH/PYTUpf3sEKS6ytBr8v+qkvR16WylupvRaByswJPg1sczmvwwzCDXUaMpamiAu
LyurB63C5jShtsRzBVYDHvgRRyd84lZXk7Mkt+c9Z+5LQLASEKFaPiSLroPHJP4eN19n92PCiq1H
0MB4o86VG9kdm29FeBECgjTqiwxnFlpyxN7jrSfeQ+hzKjdHHP+kvN8ESAmdN9v674jdVlbJl3c3
TFzGF6VGJEPoYef2y9g/K0xYUiZfDhQNuwuuEvCwLzHP1nl9LntdSaRXK7rBsAps8dODEA+3p4Aw
qjtpsWi/ySls6L1ZblUFJCjlA7K+1PSdLQOtsV1od0evT5NB2V1dQkpMpcoCvdH6LpRDses52Fes
E2lVQKUjUoE4S/2Mete/WOJHaadyicvmepXrJm+hJKm58VH5Qfej3DEryGoJB3w9+bByXQRX2V5h
rcqZrQihw+qcd9vIcPRi1t2j1SLbWWFyOrui7EO7R4iFO5i7rzds5b2cnAKgW4EHm0z20VAn+xhe
kN5D5pukE2flQgGTH+n6KhzjQzX42wlMQtgkvfyvf5lkAYs6jfTtkZqTX3Et/tzw1Jn1xvPf4Laj
+K0EAJYc1M7zS3USwz6WIa4gLP6RChNDTBFptNrLinYb9WtHgVY1HbBsjbYIbz7HW6JOqmcPrq+0
l29zboIqW+LgsekKaeP9nHmQPRC0LBbsn6QE7lMSkIdFjIxq+uWeLhlT0KX2TBMYqRGU37jCZ7AF
w7tkXEcEZ90rqUb6Eac45GV9t3SF8ZMrbB/rdAx+OduOQq8yrbjcsbXDN+XpeJVtCizq93BX2Bvg
T5tSLLWvbTyJSzoTfXrGCJYDh/v9N/8bosVgj9nGirvlNTbcbn6CR+Fl97R/B3uQY/y+QP3bLhLZ
g1cyb53aXlqkHn4GY8MjrR5N1FURuKdOyM33Jq8yw2zk05QIEJs2xlmuF14bXfNCrsSNvq27BCCh
L25ZF8xeRjnrd/xKgVkzG0c+o87ipGXZsHrxmAkDdN1E29nAbnmZgB0zyIKaK5mn5D51sK0W+OJx
tLD1Hpf8hwfI2USj5gr6s77FjkM+MbEGWQDbTianvoJp6z5/mhyn/kBluVsRfArTTNRAkR7fc6rL
lT8XlY+XoK5z3/fR1du78/qYbbrv7KBYEsO8WDItNJuK1ov3lGwpfcRYwGG9k6OSQxm7hUdiEVTv
NJ36H2ms0lJ92VYFXbYrv0KZ3Qy8Pwl1P3jQl9TC/ZnenwNmtT2wqngmsNKuZD2xfp6SMWKyGKKb
6LXuXv1qtpygykVfKcF8SJ+2oXuDRDxgKi/JB7ZACjvexS6v1NqKp/Gv99rsW/5x0D9ceYXCpifP
GgVCCgxcea90Yuh3yXz/82G1koQGKn/3p219T/OnLBQkz8Wk5QJkw6RTbc5r+HQon9Anr9v4oBAT
5wvST/SvX+z11V7hjr5Vz5GWRX3NNwDrKSCnaEX+D3TI0zZnEOp3waXcTJfZwKlLPaDUietSZO5Z
QhvpzKfAd1crZC0itoEo5k5pqrxddKj+xcJbWUDOmPNgFjup5qLVDeoyJti2ZyFaTnh6suvKXn3p
PmFWcLxWkMSKRwuzGBElPSda03KQ1jfCImD/XnkbBcsro8AeHXIBWkASs/CG+QQGyF1/M8QkKX5/
tD3kk9LzWtNS/gGtNYFGCYSp/+Yl7CQJVAT1w5sM1ujtS9UPHf3Z2Sg8Y9JYUYg9CQ45RwpbkCwW
gtk975dR331sCbLtDzqCtAwOEWhnWlaf8kPp+DPgFgRx+ZUq5B/nCuxxOYSumBaDpJ3w/6kpxh65
9RMtm26dd9mU33qy3AAi8SyaAPERGCOYpYv8+i3WMhN8c+KwHEedCQzoSYKy/R2qmGQZC5vJrklm
Z3THy+cn+mSf3z9cRdcgkxECz2pLc2912CNBLxe9SvUNnfFJFWBGZWvJlVgs8Vri08/+BsuUpe3Z
LG2TpOcZK9sGC+45rGKmVTEzGCXA6wp1LwgNyNTn35UlM3fU96DHjWPnAZ0ifQM/E/0UWkXa+YoP
QBA7H5Yu63RfRmXtKHhu2yamVHGOg8NwBtXr10bHRUA+EPW4/1Hc65Oc8H2LdlK0uaJnS/BY1uQd
0qd0Xw0kn7HB/KHwb7K9hh59h/n0HjR2/Ize1ZWZfyufm7s2HxlOkuPb3s1tkoJRxv8zG1VghiSH
yDQ+PcXut4GTw0gHRHNUsEL7PT45xgGBCCuI/M+DNoYaBycx5urT6n/MIREeoX/1iXWSKtSlzL60
PFQAllhETO1uRg9TtgfJjvOLulRAcCDHQ9oe8l5SgA3JqHwhH2i/Bruxf35UTj4kQh4VozvCkcLL
EPW6g+SbcjEpRpG13xrqWpVDyRHHH+EywPW9vq2GhMfwp1PjNPhXwhye1Uqkab+9CELVyF+Ah/TL
LritE5PrSLog1hQU7As8zpxTzLw/h2a0xoEo2kxP3deBiJuyQNLakxctDlUGqWFg8a7RV9fU6Z6u
Yllbpnwy9PRPOo126ZdTIoXEjLJGh8eZbUd9AlEM7aF8Uf0whOibDphbqTFLki+XJo/KOajSD4zI
i7teQDuOnw2uHmCNC7isnk/8IotunWPjw4ZxWUi2MyEpj3Jg5IsQZTrgDQVgLuD7jQ5DgctWw68G
4ZNN0oITEfw/5cZTnBhtNsk7H73ltBO1bG5GAWKUk8RCmLTyv1VHtftOWHTgWDOBZHRf72GsNEr/
AV3vGlgf1GZSeJH7HCyyexfeuz5lEOYwAlN0Y88IOCWaXLXQlyppZe9WlQq940/CBXsc45dJFKbw
PT9pSixKjAZ2p1QrIATlPLdICAtCF1xiR++tLidziRXAQCDouNIloxREtSB03ZbLzCUdRu4l9FRX
d+BPyy6mubXPnOCZ43WU4w9Qo34fZu0gW68rTssrFKToGIxT4s/YSCbLI8154ifPPFi7+/De3hj2
Gq2ZddSVZNbkA8sOnQ1qJSXP0r8ThHQvfYVSTNjje8n8PJyOxYqhtmUaJuraUgB8o7TbPVcCXIHe
bX5W9ajCQPqJvXKPykQPYuuyfkIgvuPGdtXeRQY1/BYHkiXYtO7SeJFFzlLA1b9NoUTf5GXHXRYN
cC7rFDheCyoJ9xLrXZ0Vapsoa/r9PDJbcioZ3say2g4da4pyj+XG9JAfAw11MZfp8dIdnDr0qlPy
YkXZZrJGPOZVBEZF8r8tsaaMJ0FN8KJU8vtmpX/ajHVqbV2Ggk2E+qdbsm75L6xweuCtWHLe3h1R
yir8uHHAuFszoCK/rGxRFXQrqEDgXOKwuU72q8opbgObxgWzD1JKptHDRYFtUZRScTAFW9aWhrmM
YoIDMWReYTdVhw0V/q13kLsFEwLPd0X67CI7saT69cNcSfOkSGIBCU7/N6LTmcTYG1DMx1t0LQGu
mRKZmOUU13y7aLo+Rw9Gyna35Y4+rf9NCv5Eu2YPTR67ZErBYj+BTmF/P5Azd4zUyRtm7PTPWVYq
YCXpoo+Wjc425KTwGe65WZKSGSFepYyx1P3xB7yEWAqPziK9FBFGm/Q9fI6wIus4mwJ9bTt3Sti9
5Gx1cnV1VETOcjNfz8VLjVNOUBm6SVvJL4qEVobCkFZnMyx7vTKbrZJgD9ytYMe3OUPHBTzZ3x7F
5qLv0ZFxu0c/Ndv2E075/QOWPZ9fCaLiVJsvDyLq1dkiqVuXLTtilXJBhFi1PV2VVv2/GfwAFkjx
qKWUblRkmpEgyxJQnTSqCwGXe2iqQ68WY4FgPbKxPOyVpFDMCEDqD+RPFYBVY/CyUlUAh+3RrkaQ
EeuK3Nf+u378uLHMrIm435IToR+47iq1QQpvmCG32/I6bjFiHIDJPXpTAKktRo5hSjpd2FPYxdhs
fk12J5E0pWQnnmSg5kbS6r+VlaM6S9vnQa8IOZp2lWTiE0FHPj67Bg9X6wg9HORHBZQXGjAd33wt
LX+R9VlQxc075vlNxhwQLCkZtL15BOmm6vmZfF+Y2EuvKlWEV1rUjmjON8ZmHVzjXYqZi948LDo7
MQ+iEOyFmdyytsL5ARFer3/v+FaFVFz3+J5/9s120WJqv7uC45mIdq5oR+QUXfGpE6MJTdEzh6SX
l2iGUhtoHKGshRyWkJDKgoZaT79cwy5D1ol0V1N69xyNRhCTbZyFhx4cxoRNJWhQ1foGouDre1tG
7GQ6gVghExCUY5zdAKKDMJ0VENewHWFQriPMtVKszo+/milZWF3EfytMsBAItqkemi2Cny/UAphw
0AUBbCEvl8Z7NjyrsqAuoDnxDGnlncap84yMWbLHAMXjO8GX8lndDcMUIkLWiE33Ypz0IpGNj1Aa
pFQxoiMuUBOvomnYqsC8IxfoIAWutB2ucxvhEIR6Wc7WRRwrRSvq/+n1hU+UeR7qKR249PkeoyFA
aCrIn0+XwLDjaFW64JSoBExfJlL/B9RCsTesKTQKtgYwgtU87zYWme+hjShDSjbeEKRQo8o+m3Qe
Fx7XpPxE/oovPyV30aCN/COvK4bYVZaXJq1VIUKGSK0+cahZVSRRS3/eqmvSWcjYvzYXttWgGlxP
Z5Ohpz0AumMA04PqorEOjo579f3X1w/Ar3jqfIYyC+5L2p+Pn3cEWFQpcNlfPrWNDpClIASD0w/K
LsdjoZpB9IW/YF+kUZfHrq7eftCSSv4QzEBs5Xlr/Cztj/Td31HJSdeYZv3RX6h0TLdJgaYM88Ze
8Bdnetav9B8XnVhSUd4I9eiTe+e/R+ttwKRonFAp+xFQ9SQ9xLjX0SAejqeHRF64l60JAkIetKt8
Zp3OVNosHebJVehsiCZ5v9Vzecj+K1kdNkXWYZIa8gcwO/maD6eGrz230g7deC2DxO3iJcicS20R
wwsX/uSIJYkb5PXIdW7sGkAdMl7n0j3WRjFPVSgDcBb64KfxumYmBj7VmJGAEdNmTAogE0oaZGYV
GjaLbnSOfQSgPGfyAb7c451VYvyhPjTxZopcTyv/+34c6yY+R9rWKTPHS3EGxppeAZCHqXsTkcLR
3NPltW8dp0pyj71iRjRPYYcFRe1wkEcJ4AwqKY3pm5ITJMYi2aeaFBvVCyt8cX64kOqBo6k1Sqy0
+rDIeeErw1fEYTd7iL1I/xbgmSd4vai8U5BDDe0GwfeQqP5ZsanXrcP/C0qmfMZ+jncNFtGEllVL
7bvh4PsfftD2a3TweSdzOJYbAxT/NWIEw03mTc0WD156ldVFgvQmjWHHvtKW3QxF598q0+MWpv12
IPYDyphQMZwJksTcGvnF6AnvBJN1TJZA+5rzyFRYg9cyG078CeBf5tNrHabRRPbxE4vFipMxSbXF
EBxoLOjN+hbjt+hpV4CgzkllS3+ygYI7srdOs7eD/HfvOtg3Jj2/IAA6JxZcajteWbhklTrXyExW
TynIu0IDSaRI9/3MXM3OExNpdscEEtyuOp0MstcxP5/uo1E3onGPj436T45psNl9Emiq+hXyfUsj
csoD/omdAEJVIg1lcI+IOSmn29KoxAeMhxlZBPjodayriUpi/AeNdIwWDl8XTRw0aT4oHeaENKEx
mgwu2s1qij+yLAXVd+CIEdXmAmIgUQhCSNZypsSrmclu+HZG6zeWpUoig+24mO+b2LmiSWPpKKch
/lRAvhcOqvpltP3VqjRLX+zsq67SjYigIYvJsl3PGEI3IXVsUU4TfL8LXmA0sUUlObesVVie2/Em
pL8QfY+OETgI6ukMFvaCdO5Vne35+WrBGB70i2wVVNCNq1q5kXc5rUlOhlIthueNPfrj42X6Uwxz
hAM8cC0RJY1uytuinBLnihJgHAJbv/+nyR05dRwwLDc1dNexTivn0hVg4InB1OuL+fE5kpFpqyHg
t/ymc6GFA/CXhn1QXdXgsyZn9Zg3rBB+gCy08yKzRe/Z12Dbsmi7Vnp7QMW42kWSbZSJ228NFNpP
7M6JxGko5EZyvZ31Dh+UOSmMJn2TkkrHzvMNTQ0IkTZllGWMPvgV02YwAKFcO83Aibn06TScb4WB
CjoQ0kK48srEVQkBHQt5VPmo3idOCD4CwqCSn2//LkEAktaKguFpAgVf1vcOaGgAStgwzdQB7b2q
Oe9Qn0FOUIALdWzIxsmcCd2Fl6PuGwITT1vANJDhbl9TuoomP8vzmRtzfm2FVFjPjosoxYAHTcAM
hg2tnkk7hF/MjILLVd/vhtGsmSoH8N6+K1lnvrUTsi8UO+X0TE2wFeTZIbsySJj6kSv5ffR9+dJf
G+eNfbbYSs8CQCCnbx6dfX3m+BOGBFIFF4TGdS0OshMh5D8AYMpn6CYpd9xTE5FbzsfQtxn5uzUy
tqoKFCx9/RVQgh496g4PjQokzP1EJaAbSj4wuTbqyCcRwPDBsl5ooDxzF+MnyFQpjcyt/WjRQzHD
3C8m+iO/4If0g7YFBvb2mUYblrLn052kQQcx7HRD04WHHKw/uV9NbUaG7K+2lA64Moz0Q1eHXXFG
bM68/ylg0pyiUBvVRFHDliQSiW0vAF/89Z8j3CyJYIklWmGuW8NcgcIYEKk1mc9F6taH/aFYzfYe
stPkS0ygLUkpX9zP9unlAaN+iRwssAI9ND5UbbtcPmWs5po+H0bu19XtNqd9E3RDzhNVvcs4DMb9
grZYU7FYk0jCXr/ZXkxnKCJv5+feAM3t+yTE2Gx09kgTfTKt1RUe7GhSMiFSPZ6LPkTs+mTy+jSz
cW3qI4Rles59npqjhYVa7BgJ1eTYJgGbrccr+WPnZ3lYseQXHigWJTpt7HCChhu6tnRJJPSFss2w
VbpbsT2bt3QSoEFMI4CuaAIL4rbHCxEsTU00VqYlWUY0AhknCrlt0wkRYCNExuVV02VZtxlpZsyB
2fV4TqV99GVtUUt8gHd2Y2kxTA44t7RArqToo96sXoADeqFsKZYNkISco+CI9nHQDhv/PI+E30Zp
Mc9kKOorFwQ3uwFi85EI0gLm8zqJ47D3rXCoRWb410F0/mr2G4ZGKVzjs98lmOoeNYSf8sgYeoJl
EqGupEnDTePbCrZ4dpR9jAWBo043jD4Yf68zMA2jcvNYhsXYnidU5FXL4jM2oN58UTpxe2jsZgKE
BSdtKT7kfdLVv45moCEOW5hHuGhn5rlPduCRgj2Wt+EO/PGCI96GWaOcC9hhusrkl7AuXjov6UZP
Zzp2AdjG3ZtMdwTQv/rV6ZK9Anu2k48m+UA7c/dPImsfw5f0QHTrX4RnJUu/3Veunw4nlKG7uF55
VJ+rRP0IAbmmuchy/CmuzVUJYV6mqURCNEXC+e39n47mS6X10X/VIRzHdQi59rTpShgLQWO+TZt7
xoSc/BaLo2PE41TviukAkz8StuWBb9EEkunlNlxU83IOpBtMhEzRENK0sbZ9sBC0Ns15mc2ulw2S
vOOLAJ1X7leC9BEDw2p58NTqd8FKdgNblp4W1Zdt1RbphwuyT/8PWhb485vip2ZSdmG/xZt+a4ro
Y+Ic9jcxseb2de4ylTzUc64m88DpZW7byhNS3Q/Eay5Q7EjWnZnBdLgGUT8odMQZ0fhE+YO5A3Df
BMZQ7yvhrBerMHJD5UG2avVBBSmB7p71COY7QfUEUDWBaL4f0VMGtm3BgnjT/VxGGbdDJKHUcx+Z
zOz6MaBKCpc1KE+RUKMzEKnWJWnUaXIg/9FdJJzdhTktA4akQ1QLgX9YP6kRcRZYeZzE1y4SaWkB
pnFMzXeLepfAQiAUJcdFivh1bZB9rCOJ9T/tYY+ZfPVR2ABX5MXeEJfzynaQCKS2rEW5QgwwVIQq
KKBpvclZDyogv9JIi20Y7DcqwvqNYV58UqQYOxMcaz38plADedpnpn3VBt2jrUw3K/SdKTVyRu0F
g31xxWE/nYg2251gFm35udJIIz39MedV7WjLu9nzTK/NdJdRaP3KxTyHKFBqSCzpgbO6H8dhWUvb
tQLKfVvZkM1jf55UpDdVVHQoseqpfx4YjfKeeVZtfaMXZUttZUKK62eO7J3LaDGskpWSufJnaM/+
U9izLRLtX9U6u8bSGyiW4tiYFta3WIAS2UR+xMCPlz7xWaHyrvdFtGE6+BAg3Rfc/okeYhgs8qm1
ni/sAoYmcNTq+CYiKkxAwwv2tRlO9hvOqSLBRXSVK6/mW924ewHp6Ce+IXdUFOHjgL1q8p/xi+sK
soc/n+T8+gZtLzsRDBH0vBwWhLS1GyDG9E0SPtnzRT4ataJPW0rXsEnxibqacTaJvtGIfkfh12hm
gE8+kW5ZWe8dtcMeLtLLOGtdrlv5RxmfeFpFWSXJkSk9q/e3pk/HP0sK93wYrr/GqnQLtmDyz5vy
zkfxl4+Ggvhrc2hOwzgUzzdcxetSfPAlLiEUD4QzqmTovnb+LicFpMN+xW1gjzJg5JA3hBRN0FkL
ZsPZQh0zKGZJcOzT/FJruebOEamolJqT/lugewY1dBFeJUDC9qhjblj/cjnhCsLJ2yVPRIcw9j11
yHn/p0wMmaT8/BJdZPzeH8EQE/IN05rOhofcayJ0tUndX7nyMGVGd3GNvSIsEKrjE7dqmheBWuSZ
xn4Gg/LLoEBT7R5lTkZM/QSB7CtvkODMzWpxZ6hiKg9m32YXn4lZDVjbC7EAW8G8wIFU/tQEqkfF
5mlicIaZQnwcn5Q+ZCDvGPzT3a7qukBsfWfeaZGOEP3BArfOqsgGhhjn0kjDXWwvqM8t8wJG0UUB
wzzJDBx9q+QOYcHLbNy6fpJ11NNoXND6Lo6B/fylLVKMzA1Yw1JScLnPpH0tviOsWpuUqr3xauxo
jKHnU/c8rxaGuffiXQoeiS4hYGEic3WojR1aCaUjHlaVqoIEFs0i3E8Vd2m2fcl8ZBr1nydcJ7Ud
np7ZS8ydgbbYDKK8SXumxBvj2A+SkOvnjLMttGh5fOEiecEe+po/3xjD0N1AP0Q9ttL5zjo00YAE
LopCr8YlIHS6oqSQOIBro/KiLaZOSLr9A1vVUy70pMvwMWsIf1ekis3E5LwW0gmaq6UfLPvOkD+t
KlTi4jVSnDVH5xOd/Un+bkFz+j2/0d2gVjnHQY08M7DzksmoP8zDPm/siHTCoPEiY0BS+6zkj0ta
vbOfTkWlodAXQi0cZb0NIoCvi7UtyaXUO0ooeFjR+Hd/MVb+7/C0c0yZWuVCJPJiMLrazON0CLkL
hkNU1S+JUd0dC7cr12pUAGkZS4Uyhk9G57G+26h6iUg9zg6eSUl4nv2Sai6RjKAUTiKpcdZkqqN+
tXHHBXyfQNlpHgu6M2a8AjuqeVWAEieCBDgahSFNm36uD1y8De62C+XV+k+6e8m/xg4FYNVpl2d4
NGr+Cbjy/RoH48ciOdlZ9FUUgJZMRns6MUxhwo3NKSthjEePvCfOnU2vp7ccZgfoNHTZPLW14ICV
5fDg0FLM1gNf6fePKLc1W1K9mUohH/AsXg3nRXV2r9THMyq/Il+ukmSrdjdHe8Z2uZQehnPp4q7m
IJIDV61opkYJAd4v+YHogGJvlNxkTKF3x+NosdrlLAvU/ZjTr0TDF4sjEfFNSj2TLnantNjd4/TD
UOzIT50/XKiklUHxzyYQW2DBpentGQJh0GYPpF6qZ1Uu6HhMKjVaOwbPmVtp/6lyd8AQFTn/tNB7
exIVQws/AZTsuUGKk6oyNfX/y8nJllEL2TRU/V6C8HQEoQFd2znHK/lSO3Resji4G5gDee4F18AZ
0jD66sFZVJeBpWlnjo4UN0/PqPoL3RsQOYPBHcDY7rQumztjbnkYjoXLkO+j4CNXjDDNE9wcJdZC
r5K6JF6UwTIPS0ZN1ZjESkwJyctAnEpRNciM1ZahG9gT/GcFYgaZiTGdk+4gxRmLNYEm2m3rM94R
asKIVg+WR1KfsYFyfIdT29zQ6kfo2D3RAiulB7ttN4FiCLbH9MZtUMyEHlJz5rrI5rNydy5SAYoC
HiX7ZjcFJ0SS7CcH/nL2f+PWQvcVyxocQhyly3kWYmZFyTCXYDiFFNP52YJjPW9oQZdlPCBTtGlU
B5yy8y1KhlnS5t9JvlKoFNaa6iYHZUq3TO2+ywtq5HZlwJ34LrfVov2iBIajo5jkyVB/2hHmXnQC
u+jEzX8MpxLHBwkeI9J0xHb8OZUax6TUIawNiORAMMf43dkvnVBPm6dKeWOJnPFM/Gtv06+X6PY1
wuIN6mBkTVA9TZnjx0jQo6sI26B0DNlmYARqWzbStW/PrO6MsOnxRiwnDH/R4EthaGo4GnXySIv7
4qIrjpkHgsRexmxYoBZHu9lzxkjv4BVYmeksmT31NSmjSe3nSeeZpEmaYAkz21ITuOLObv/LkByk
piOp0xhkAIsRWPfDfkSGiYZReWCUp0+6TIylv3JtnSeM7gUXyZTM7JB9/3O8ehhcOFgXETdduqMO
RfKgPkeeV5q4FJiJnX4zBtCnfsBp5rcZoTQ/lquuMwQlDNVVxS06BNoZxqtvGqphJlAnYxEW5HWo
Dg0LRs0LYKsFE7xZKEaGI1REN2Y2aDZkwOt/TKDAmV7PfGP1qS3RF5YhPGzGQoi/utZhXMVZ7F0+
M8nSy19NvIHCWuwzzcrSd38U0IxTJgrNyZVqN1bDAZ5EQxDOBFE1sd9CGpQE89kmDVFuKMhBus7B
euQsSyNL/Tp6JEvRkeEoTLakyIMMKrGS8wRB5BhzujTX/0GXQhRQpTjLfNHeWsXHNPUEiZbp3KPY
FPDWHqrAAZ7VHP3xZENRb0aS/EdbLcC8rM6vXQXRcccbpiRXdE74bSn+w3ZZW8ul9nb+3JMDbHfw
IQON4oy0BtM+f8EO183w908KXdMDgzcChmGnrc4VIUPA8RrIn8+pe8MIXb3tzxSPOqKedA7ePbty
YShBdPDQSyZZLxXXZcjncNq7hbzPfQizXyTKb5KdQGY7B73LQnG2kU78eXBvDsyyVgvjVFtRmCMW
8xevCv+ZDJZBNV9rRJaM3sLHyjpIIwZSIA8mVXjk5nF2SMwkfcui6tOd/6UrfSg7GcNtaj/WM5q2
5r4/UT5b+NYlitjEV/k2I1hQsBKtwrGP0TKiIp5FxRJgIGHoaJ7sX9hAfKmKdO3JfVNxc1tIlUS3
2Lh6B3GWoac9cVqYBBtVEKjCMOexr83p0DcmxF7nmw8haZTp605djku7UkuPgOP//efmMLecbsSU
twXE0amfQfE7XYc+kACkjI8O+4K1kpNv36Ak9AjDYzhxjOR5HrnSYOxtvbQhDUpIWpuDjmKal+DJ
R35ZRVDN52KtWha9iiDtDZd8YJo3ySxn/rBhTK9OKonG9G86S7es5brtISaeKrkqMoJhmtydTT64
v2j4Y4iuDqnV0H1dXo8Ag56r5hwUuhD/3EkNVmNRabHlWpCkjTsgalQ0tlKSmufxBLqNA7tATZpn
mYhrnJ2UnMJF7c/9FNR+vYEv0EpfAoXU/1MAuAxHLTVASpREo24Ma/mf7w+AgJYQvLikKxktY3SL
/nEW5rDCIKGi5TAk7EVnBnPsgtgIaJ7NncpIi4eWBJoUy3sTgOG3L8UMxszFqS6JzxcG/oQM74o2
ziLnEht6oqeRbn3R7gnXcu40Z2H0pWPFsVRPyJXs66zgDTQS9LDSA30+pRu8ktMIKUO13Dfuq2SE
KNil3NiO17sdHndbz32ttmnKf2XitxVmUFIbSQ7RnvODMK719b0419TPYjxeS8WiBL/DQ9CwTv50
jhZMnQptkqYEZwg35AjJLzbE9ipqrkUh67/+nwhyo6LgCpXLbz1s3b//6sIjTWhQMq0oiNA/mvJn
y2ocVmAc4ug/LcGRVr+2TPZQXEpGjYL4iZX//dzHimv0IH5mAEGTgYQ76Pb8oVbk23izFEJvvGoK
8ACM7tLZ9PpjyZZlBvOvWPWcCM8nmo7W2gsG74yOqqqbW4Dj0SnYRTNXPH8nTZ7hYsx7mZQRO6yk
32kcH3auou+NcFlhdlH8Ai1EuE3WsQ3lPel3fqpzHwYq5I/QT313w5ocQn8Ane8Bs+M3avoCYZG7
mHGFMbvriVxqKz2nXQYSHTK6zt9KlcIkOTBmzz+1MuMLXlG7coTro8HeSXDk/ePZFAVggVmta99i
ily847NGoQ0ZDeBSP34rvhhvwYxUnCBBCag5MZ/4mwmuT2LeJdOlnWDwaHRZxZortEjBJFfKYhUs
DyWAt6g8GuKaFs5UOnkJfrdSldf/+PLC0h8JPEA6WhslKtHnKBywGfoZ0VNWIUfAXhDigRLwLEdq
m/cA3o7RzVFEag+EiEcxJLF4YCsdzUU4hHTZweUTz1BnN2ffYUj2JTCXCZ9fQqnZm578aLJ3tddu
8qvwB/rKwZc4rbZaUUKo7nbHtrGwAXeOR1gNJaMo0hn7CXeHkI6v3lqEQzJXVnhu96tr7go1E1cA
Mp3Y/oub0jXY7NGddBTKqlANE2rSyV67BpxcQ+WhCOHsexrkfLz4qgSQ0PjvT3heGL1BYenhOzfK
AcAwykf/EGaclBfItMY4aXcu+K65s/Vym799VG2cbU7Vk68BN6mH8wvYjvLDlW4RHylXBL3jBD/N
KjlCCyE6ibg+iCISUKko+8/1URSamyulSArlxnmWdMEti6mnl+fXOIUU1htHA9rVppQoASjekbX8
DyYg8ysdOSfwBYpckXS3rw4Xuegp9MBTYGUpSsq32fRiGSyN0ij1WWMnCWoezsSxxjLNU2KgOGDo
oUe5wwmgwrpZadCT4ZHa1WtrNIz5M9tvwY+GufV2on9f0UtGiL3j042mAMzBQQDSPps5upAJxdse
CCrzG16/chM+m3pctYsxEKiIg3gGWQb9CFZU9pemP4wU52jgBTtRw6lVVnNdC3x/q0eQUzLGZFJ6
2VaMVdz8JcsnWT+qFstfcsFvGAHIxAws70T69jyCG4suGHaEykmDa5q8m1X+UUjOUG/nzfCpzK9n
UEPgdrH4K9pUrZ5NSCn6tc5rYe2VN98HDA0zWaDVutau5Hvq3hD1xuiGFXguIKoyWqIRNLiYbYIz
HalvNahBPt59+m5LaVGs5w4LgBXOg0FU3WyIUMcxH+nifo8h6oUAix8xhuY6ehSlJ48pygwp66k4
6nQWc/2V3iUl7kj9h5bF6RD4gT9PQR5aj4J4K2aR+mCd+ekK9Foa4SQ+5djV+2QHv/QxHqJpP1ul
bu6ax050tFCJnzNEmSr8ca4Ztdcq2xajS8IfMjn8DmPU/7tMlPsL/SQOxhUYOk8wvZvnNnAqKvrU
+q20q9NqeJ0tkNsCeYj6emTS9JRGj0Dh1Dvrri9aqWiHBvRPxWZ2hG3k2/j3I6KVa2wTc/bsBR48
QC8LS609tR23BZXhq/qgaVrfothQ/NRGS/xzjUi5ndV634ebqQzvBROJ1zN+3B3mg2D3Wfr5yj/O
KLZWVECcDHs6w1DOF806sF69YOaA2b/YeawgA45i28h8/BVv3QDnBBBQFL6tC5JMtaXnnk7UYgvH
QV1Baars5Xd0ScTQC5ZjK/7spYGBUmXUHKsSiimqCr9aQJX1RACQIWaoVS6G7wolzcdjbF/xBdPM
nIeApD/Pmn9ws7JYzTfLYqX0TG5AUrFxQUVKlZdgmgUKVf6Tkj1RZ/G5in7ZH4iq6dohHpE59V8X
Ab7mN+W9lToLdZqRG+WmhhWCbM6lBDQiq/AaZGv8NZZ/WkHBfSPZulssQbj3a/OH3nhHHmyryv3P
WaAsZucwglWNaNM24rfmxQBLCMKjKXakMMY31is+J6vTs95Jgphot6TpNWTeSzRCoBaW7HYTwAMR
uxd0OOBDdYbpvbje1PxUWmmt621FfUWSFJbLFSCZUax7wLMhn2XC8wStJL8y5ALjg27mpXj4rh91
H/2quMnlWI4xvQjMc2Y33BSqUkCSUhVWXen8ee5Nc3gMLxbYcbXpQC0YvSkOkKybLTXqEu4YAS7G
9TRCQHNEQDBl7HSpQBpPqrBbO0sl3SRgRuIm0d1Yo5Kn2gNEmKslJ0F1lJVn+6xpM2arByt+Etuc
nlACcJvwiMxtKT4B4bCE4ZlD9SPxBfZvGs4jcrI0MktPZ+Pm19rQn2T3PRM+CHotMBJfmlyykH3T
8/CHE+49uMaMhDdLBrIxERnRK4gOr+Z1ZPuzz9ub2yv0wgiI7vU+Zr5FlAheUQb8xBALAuy+a87Y
+6gQSuAyFUuELkM4k58bGMtPQgIH6KdD87YF49koXOrSu7rDM+5+/PraGCbiwONkkbGzoT1XR6nw
3LwI/bpKn1Vx2Y+rSsI4fFtBovPJnUaUf6jKGpa39Sa8lHc7e3TbN/hL4ENoyimvE6BaJGR4MN7p
NRmNaCPWTufw3ISvViyAwhYKIBzrl8VWY8ljKGXUYY+ouV3e124yQjC1v19N/+mJ6ZxvoKlTGeVH
TPA9yjlg0E9l9NVBIkhtCXAL9COmU2csjJ94pphI9ddg6PSLibO7b9ruda1n1XxBTVnzYNJIbDEd
JDX1mrp0c5hCANbjtYcmsaTHu5l9WFAm5Djjaf+s9snfBDOr4t42yhj5dsHpcGdRfnp2IZquh374
7nDz/+x3Ekr2lZrBsIBrDrVglcowSPVpYZo/KqBuVIL5Dz48DF623ynRyyFviDTEequXxJW6QtLU
60iBQMmP8hWANJdBxLW41qnFKTmVPW49AaNpSkIg6eivMDiP1snw1zXaZ/Q8gRTx6YYpRzRSe5HU
XmlgPTL9sNjzr0GDGG/dj4eL1Jvx50SFH7yezR4jPjHIN3oA65ZWgf7z34oQEoJQ13Bs006J1u+u
CSxPzsatmflaw8zl3FWs0Rb4mjjtgR4r0VJi6Ga8JCpkfFJZOHkIROWh0dh5EgIjqZyl88AgY6vL
XtaBmJ2iiqL0JxSKYcgT3IbfeplS7xF4AE2uqSwGARD2Y328b4KdQE6o3URcUomxJNovW/m5kWrE
2deEYsmN6s1F+APbS3s4dRpif0jSoP8GgHKIYaDqhVL7GeJ8j0A1u5QisfPvFudyhB1ArK87VhbV
QPXWrtAuTAXYzaUrZfUNy3i4SbjE8ANGHCv4MW1fvtNKvla9v+z+XuhzubaZ2kPtigVYGEDX6hdP
AB8kkHRo3LnlR+xCUy/KdrqKC5pJ48RasTOiTl3LSu4Wx4UhnuWQ0pa9iybwOALHUWvhEuppgqL6
2uUcIgni+UUDmD3wHSfP/j+AqnZHEUhZaLZgBMNRgs1zkpV7QSWetBNK/vIPzXmgvW18OhXRZaia
6Ihf3sOHFEE2tIiW5yumUkDQmT26YaFpAhsZiPQWHJLHq6GpHLdtQOI4bP0gwqKoxWpd2AsCMkJ4
sLeDUiWVoWpoVE+lwqodBzBWv6hrQz+kl/B2ho3LcE+NYvFDvEyDbGxmfJOCgVUQneJV1sAk53BE
GEXKWem3yHiSAJx+2S+fuzrzGnHvRb6RoFcXCCK6BW3HqlZEyG2EEQlVVZeuxOfru/RkNcv16fju
EMqZjg26grps8cWCzUcnUXWnr5lttK5WMYpd1+cgCH83mWx3eSqgfoN+9t988KEWjVhuWUWENjXZ
Jr/G2sLVEhg34kkidVY9ELyA43YUtccrPyE2k7Ud5/aAjV421NcDi1yEByrAzNs6VAqMDg/UYZmy
R4UXGISB/MqIO4wRfl8Yn5q+Z5GBQDFgQJOV/qRUxBMBCNWjrhRqtPWlIWX3CwRYN++siaD3n4Lo
90sShZK79H09wMYcGkK4zjQhffu/ztRbMp7T5KaYAPWp4Z85QaKQGvdPkB17i8N+PlRRDnU6wESs
nZ5MA0C9Tu/vyQWJZohcyoWWe2NfHwyu1aFCE+9vgC4EkPkZXrYiEZCxjy+bylX6oCLQ2dL9KuRZ
2atEQLScPvk+T8QAVfcrk8UrUHflwTzhuR340GeGpM57G+HoV8Uvjo2v4BAcFO9e7UqrhsOp3YKT
Fz5S6li+wAtGWi+hAaqCkYA9IuztN3G/XYhO6+03BPCNq4Vq/K1MxpnnTn3CDIa0FJPfyapQgmRa
HO2DxfIZQsN3j+LaHe3HJEO1dvB1tNVznCKt52l2Vx04S8QpW+XAK9Xu+6fd/qVuPWIRVz7hmhsK
15S7wrakdsNoaaaTCPY08c0K22SjZ+sO7qNy4gDGMocBDaOiokY9+zHjR76pti0H4YIg4MUvgU3H
Ghjk53yYLa55SlP19V8834TsHqpndCwaT3xzvsoGwDQ78QFQrewCYDRVkAjPH8LgFxnAQk6iR/2S
b+KDmy5WUK0nCm8wHSROolJq2GE9ab+/G6G9QO29GythXdRPP6pcOvTFIfSAESHsagBWrpNNcIo8
6Cmtde5xNHXNn1n/S0UHdXviWmq8UjAZ/RgA+aE3lZJwqNYwr6h/J2W8m3ZlJr7CroeWHxveIuAk
yP64t0wMAY/5TEuBjDs50lFBzzSk3T7ATk/XUkb7uCCRWFF2xp0JdiQVfm5hPrSDuL6OPV22KVEQ
d6F2gNNIdmSVSyaGQjNzj831HzvtDnG8K5QU6P6OD95MFw+7HQmJk80BdWzYnMYm1JNxVKTq6qQ5
Wohre9YIRZNaEQAussIVOw2WxQ+08ypN9EgFKwcxC9iU487szj5o2s2fE2Jyr5PpdOTiP9miMxvD
0zsJF/7oS1AUFxHLQ5oAtxhLrrJhBf9BC+dCNP4TSGFjqP5h3o9UDDXlYXWqdgdjz+SDASH1Qr/5
VTEqptwbqoC1r5B3g/WcJL7vsl9nODj2gBjfcRPK91avT2EISkfBiTde0q5O7I4YAKoFB/lOgbIo
GLJsF1ag8N6hmwJvk4bsGzDPDofsUq+v3tKAfMvH9QMoyplsL2hIrSO6wm8PbiBALXVDfI0m6zP2
Dn2RGcao7r0kyyqIFS4fT4lDJuy7+Dt3aR3wA00Q28dJ7C6TCOWs5fQe4cCXMDm1W1jmQ+tpzf7T
dc/tyauWsew/5ZWrgF+ynRJDSGygHZbPoojAyjVgLLFYZheMFBPFkkhK2ONZKkMqi9aXKN9zg3oo
6eLfscjo9V5Qg7mBllvUYFuSC/6ZWrqGdVF5es/mis6wV2c6VgX0rS3dtqMr+59Ben2ZhuOabd9U
2PB4N5oFl44d05blPcUafhfrz5s6NhKdKX2j5SD9PlMDZsMxVGT8IDZleDq3HrSosp6XRowX0J9R
0FlxJUNmeASvAPWNg126tVk1sK7HnsWXr3C4+iduByta0jSxGnVSgh08q5f/VDqQH0EFwH2dZO/G
/w6nRgitbIxf6G5SdXcuZGMAKV7OCmD1YjMicSnAEXme1ve7ITM1AjG/9d/N9R8ehp2zihxNPY+p
uQsG2zrHgxh9Qxh5fNI/HJXDzT2fqHK2kwFGGs0LXyJf3avqzFpU6vs9E5AcN4HdgrlTxnjW39Cz
UsB9APTZWTIF9g0OqnddxM9krt5zrk6NRv9b14HTjx6dJVmnygptJRnvzLUU/K76xqjQIPHdcZoC
K1Q5DPcl2T+X8gFE6gcZOpjALCwzpPb7ScCbuoTlF5ycxcnG0J9xsEzuQFcCOsk2ZMKobGYJ24K5
aAHHG5LnnI8/g5G/4/Lt79Dej5Wd6yfC6WAmp68oTzNajg/ZYzYqtDfXWlwM9FaCD6EFQU6W3Ivx
e7fwF0Q41xb0SNprhNkzybpvu4nOxSKhQ8qUqKSJRHI21hAAe7zHDEWfeHqT6zGUy5lS8Q6SSY/2
44g/nm9oxGP2hDil6I+ht18TPq/lPthmmGmJ0V4fW9dI0/7SO9qKM/WKpVHDU/T1OWje4rdbE87y
Q82MX1YsMcu0DzPH9XjIv4iOtaZQRNeytSKk+lG/ipASVqJGi5DgTG8X48bZRiLmc+OZp7qoAoBD
rfNmE6AsCjanmwUDolp6trb6C3aSUBlWR0e6zB6+J2ApIofBYGQtP/LzMuBAYKhGEzmtFdYDs7FJ
vqPDMNqZbUk/rNZeSZ/bVbm4gA9NBqOXktHh1RIjJ8ybqpePQGO+7ohE99JnehBZj0/2TQ739cpG
uV4rOVstOB8JlfmnAC1tnCDOgJuUoKdKdXj0NfUlRkomBs8c86YrDgrFjI2/NN2hF+kue60bKE7F
zoBbrXr+f4hmrBv3I8OUQlbGEnmasiNcgdNQu4FWtS9ql+UOMDf5azknXl32Idm0HLynuv6JDz5o
mLw63y8kLq4YXnl4G/5hc5j2eZPzgkV096uImsOSFOZ2TR+zLXi6il1cOihR/BwCGect3HrOSrqe
QDpKnmFGHVhtOv4QDeHCStb3U+O4Z9kQKMK4c2u6Q4a9DUTEQLNfMJRG5U+68w+wECuwc3CAiISs
9hafI+JvdSTNepvqK/T54bKXmfw3GDRs9unpmGBrcM0oDFsRdqqFfwygeVgr/ShDls5/ZtwmJiUQ
6DHwrttApknbCRYm7LAcJTlN7gImneOFQAF+wSMK3yITxry31HbzehKSaFArc173w8ZOV2iZK7wo
h71oSTIxJOeHgQ/PAlGj7K5RCWK5ecDKZ1NCXMi59+gXxxll7aQMoMkjyYBLz2GFP+mWpm9KdAmT
NpnN65TqWy502HaF5bq/7umMWwiNNctj0mk8/CLcNGehb2Kd7OnfZJ4R58WG3FKkQv25hMA5wuXt
9hfa7YCcKZITOkrpvLLPKj3A0TGGObCMAmvt/v4bP9dSwptBoAPE0ExbMq8+JanbEVymU2bEy2QL
Csin3f/WY3loKPxZA75erunW/FjAvKaE3KAk3DmCOPo0F75/FV0QOIKODSchLBa6TrAgWrbTVcYx
ChoHZQb4EGVx9GUbtq8/Zn0yVoAnDZTc6b+h/ee3sH1fYLehA/hK0gLt7ESdYPKJIChOA7uYwyBl
IGcUlv7rpqlQFFu0VS7rDOBPbK1KwOY8SpERS8wpajvj7vcSnWoRa6cHNbc7BT2eCyexWO4fo+pi
QDcrYfPpoW7VKA0L8dia2DTGJh7aZAOELD5vNpbgPlhXHa3M+mWZgwU4o8vmOYiHY6vuL1JkiURA
232DJ5hMI164pdfsn/PKTv3S0bsqN/l3d9TddFC5BMxioTqeLuFNC8fToAl4YCbEe5VhDTYMiQG1
VWYBn9IyCHKaRdnnahOJxOClM7aMXGrSJ7lg/zMw0sh2ijb5Zb7+H+FGGDeEBXjJaMVRnxjnebF8
0MBHvAXPdPPh/ZgPzPyGXWnmUMDWo+B05RCQMJXBc03uhnEQSxeRIaosyjbBtgohqfmUk9Yt988A
aiFw7H+CcmvlSt1m9d/gcRzo/k+jyDrsrv9ok0dtCKVa9SXcvlQWYl27TLQkOAcbVmVGM8NdKSNg
m2IZzwoZJJZvQ16X859LFWyfMQDt3ESyqDyxwG+RN1ELXHOWhD+MU9YIObMZkXQTKme+qvuXpROZ
G2MmmeO5z5VLRiNQOY8Ewu6atRALHEA7o1zaD/Mis6UF3gUauCzg2pMg85qAdmkIq2cduIP17297
b+X+WogZmL7oy7/R17GIEO75VplR9TRDeuUHewP8ReUsWMB2ud0Bh1nh8qAM1vtFPmNnHY5eo3bw
n/KBYFFHF9bdOFlq0EGBtxu9LnVPb1QGDWGYPHFq23Sh8szvgqF4mS2Synu8hz2QNeDKgeV71Opf
GOWGvfmvmELijAuhcgQT4GSjUeyDUMdDG60f/SUw3Mn0+AHBiIY45lJPeNdWpoGZGvcz6dWEoz0y
T3sxb69f1kLoBh+BHh8EXdgmjq5NSSCfcMQX04dj3w44HjXEz/Xw/ATz149HPWIr02r/UkcHxmiE
mLEdn+yKfwyUxJq2UtzPHPftBSCs6WkiVPEeLRP26H+Ss8hCUKx6bkgZYy59Vh2FhDc+9i9/b/Yx
vyD7CZjPhE4HfzMnVJtYgxeNYXKpkAK6Ix7Pi0q8bRU9J54e9ootSkhWEZKxzY8XZYBz5vnGKVF/
mqTDEO1JKA4TdLRviKFkIL3dx4IwHmYaCcsGfzuoeCiJ9lZmt4qsJyO9uf9JpFo/PfE0AxYjvtpH
uWyeM0+C3jlBtBZ7RtrWD2wzo1B3jaqUqglvU9GC8QZeuEGiV1Rpr9FJQ7sXEHORrPhYCH3JDBI1
6zTw1EQEaqfInxLr24oRbKtcX80UyYKYb0UJHtmUz23JpQvLyUbKGxilxxggdXjvvRVgPtNbExRm
BxKAdT1fULphg1HyaEDlRxwLWMwV9z4d1tdLngoAR5WRUD1dQWnt8YyDStpXdMY++6jcv8swRcnN
oxHaAraWVg/DVammalcFb5ftlTiJelvKVFsmJa7ZhVQM7agXmerld6RrmG3JJ3ATgw91fB99BhV/
Hz0+E20f2llCkmffcCYB1a1mtSb9h4I9S0CazsnUwmgGU25YukmN8fpTc+TwwxUNc0Njr931bBS9
+VXLiOsRT+zFLqWFbxPO7Bo87Q/JJGBdJTUJbDPjGDKubE93V7/PhUkR3xYuaMpzzxkgQCkAen1q
4BzZRR8PxkCuopx72Vd9I+oEDLrPqqT5pElXXB8Xu22jbyHRzf5SLXKrn06KUSrsXjgsNUnPZMG4
zTimJXYyX6zYed8KdCN5Qi30xKGVTqyEPv0XVq/qi/MluEcvyIilTPtJUAlHlpKN+bJxiN2WZj27
oiP3Uea6Cn5c/5Mn0RfAJ9YnirChdBf8QXiUtsex13ewF+jtqSi93PaDC+5IfwWMqJHx5HF2nvcu
bAxR7RFNsADUcqMODxF6876HwDdKgoXA+/KwMYdFofvf0p1Wcmnh5kB0R/kKwGg4O2Qc8YRUJSgc
JfZBNbUiEczjQe88pVpDXr2ILsBrI4sU5veBOYJzQ9/b5P2e4DEpiSRudboQxq1uvnSLT/hvoaRK
Ew4BBLHEtMRJFX1QWIMeKyxZ+XyWAKXK/RR9TnfmYVR6hyE4fUcXN6jOQuPj2b6sb3vE2cCL58wa
siKHDAgk/XBPwV+6T1GzptpCLEJQLenaBZBBedqqvF1MTdyyLu66nyJ453yqcF9TLklfrQolHNdu
H6FCgFSP0dKH4mV/z4gk4ya59VDrBbZWrSjOIbjPbJGZeqH9gA59LvT1pOnAbc9XUaiZUJo06nu8
I8Nwuaa+GZGUpLjD4NyGVvn00q9b62FAH3tIgvPBsVdYl5KyFdcENxKtEiLHzGhnMcW4rWp7CtTY
pHi8tCgwCvCoOgb1+rcAO4T2472g6tCaV/EQU0Zrp4tW6C4/qeXzUQT5jPRbCgnVKBVMtf+lw5WV
0wYHWEMX0PLCPXhpR7T5phuUgKoqHmCMcastxQVov9ZpMsMoXpY76vkbC/Ra/0Qr1ZLIVloEZhT5
366ERafOp8sZUylTvq54ZqOJjbb0VApNWdbq9yuh4vqa0AR4O/jHuyaR8bv2jaRy5eNnD2ndDREO
pJSYZD8n3Wx8F0Twx3/2zcZRAvDyN7AUErVqnvm43G8QWDgwgocoDaBbm+2G2BkrP0FIascZP/eg
6NpaJd0tmYNMokpGnIVvrneCnm+CjyiyEbhOzuaHYhzkRIVBzrd/PRqOEi6SB8st0nd59MLZ3lEF
idSaancqMJZxCHWKlbiSnvKSSc3ybVsyPRRc+zJq79IUPKA7O2jQYmj9xOcRbKhVl4KGbDCUa5Ki
sFehQoPPiSACBUgfEJPAbw6B1C4K1UTIMb2jQDgDdU2/y5E33DvTlCBqugOUJSOfcbUs8bxgrZlc
p8T96w/BSJZ+DjmHY4w9Pjc5jb7c2qGIxOhWNljWNdp8bE9ZVogO4TbNv9L0bTwmOfP/8p6AmO2t
6iNk63fS9hdG16xpWUc8ygFmYEQjSAtbx8UvrDOCgeJnceZ3dWmliZ1m61EXfW0ehmoW1oRI01qM
dB+AHYLNFyeTivMWHlm1OC5Qoddj1Mvhduh9VACDLK/UpufX3U3Mkg+u8/frTEruG63zH/Z7TLKx
ZOJWaQhnvYXb+yDJFNUWntdD9cN0m31dGK55toySFgabXdSiqDnbniQOU10/c3Al0mbfXnCnjSUI
Q8ib+Q8ChRAuh7hQELhW+mhJYbSqBaZamnpZqUYRpQcQgqM1zVq3SqH3R+qe3UHxpLNLqNkoavCL
A/SLdQ7lq3ZZxIIdkZgTV0uR16Al1rXkDgYLx19/j76HAheu5Z5aJuQyXvxkhb1QW4l3KnwNDUyH
CW9hJSiPGoD7Am1ChNbZ2dP8KcxmE1O2J91TevWMhA5uvUJ/n2ANKSlO1EiOtw1TtjHcSJRWZpTq
N8PDNnUUlcy3TE2blUx9oYp0CXANg9jTi9LgECKKQkakjua773WwulgqWsL4SFhb/jDg5kOSe7//
/rll53TC+yXR3gs2nC0XQJ5WUI/jm/O6c7u31356hAkoiP/miFvzlfhusC9Z81sKeq8WBXv/J5Wq
Dg+FrSXg6erOvFYES8T53fxmMj+fxDoVMWNn9TbFHZ4Ty1hVHX9RW0Z9+9f3NVnSRsoVb4VIyfdf
i2u7T7OResr8eSVvMxu4OdfqSvT09evR92+GbtD4P+vwjYJb50KfCWByOxKFYtluV85oYs/SV1dY
dRODzfBCg+TxR3EVPuG0MXIyeLOmLYXDS5+a1gqkOQYH97YvQ8HlTJDSGtm3jTYqsDNAo4iyIKLH
KDOq6OOQ1UvtEQh7oEnzunVdwhbWS9TvXR9AnfnchJLSMuqaSDq1mm0vU1vzNPZwOA/e69tx3i9f
26GEN1hPVgy2kNw2LFrg4kGx2HLMMaWKf2zWfPgpz14hGvYVv0MMcdNcKrwTMtIaI3lG21JpbgUu
wESaiDODcTym0LM73c2y5tyo0JWjPhDJEnUQyR5iIF8RM/y0/4mnzHQr1F+wuflsb5UMOHCxAB/7
iF/Rvz6zmY0vTKZjs7De3dJJQZaP75GAEe77S0C6JgBtiXygLDXBpPardrKIoAs9oOSRu/ewJRvc
/cxB53btCC1vqWMgImJdUxf4+pmzGy4WTBRocdA6ZvUYLQE8cIyMF2hSgjMPDRhdXXxBDVuWhxa+
NVO1kzq6aMep9La8FtxMZyV/MhRkoNivBSDFjsS1E4RcXOHx50fBsjNvAvaCYhLx2nPZiRBjoZRQ
XluwAqXCd1sZNuuSbSdgEQht2afrKccT157WZei/34Cx0xVb99UBJaBcjracAYIUWOdRd9eNoRh0
Y9SQ2fg8p5C7VdHCOpqvyZDGqUR/N7SlmEmesTLNJwjnGSipriEZ9jsykHnswW+7tU4lPj5qpjx4
1de5gQhjoLCAuYuh4Ltu38Us+C8KT2zW4nS/c1/Juaq9EqyMTdL2IHBFrjSQo0j8rjv4Q2BrflDv
e0NetwmY3iVohgabx/orTUffGKeGX04ESBQCdrJo8dJvYKrnu67R+8h2Dp1DSYaf1XwLp4IxytUc
ChzK7I6dhT98qGgNZXCbLCtD918SXpqLYGDOGAbCq9kV4J/1fuGgUqlaSida1a+vWhCGS+szRWXA
aq3c0U3RhmiT9HRM/aQWxuCK5zkKgxrLDnpQLhVQpy7wnAsXqMTGGOH6u09+Ni4FFvFLPAsm7Lr5
Xe9ao8uMneKu96k/9Ms2SVmNrFXa1K7a7byDP8Nrao6fP5+euxySlrMXNBONAMjS/E4uyRTpw8Mh
ZNR/qDYm7YkghT0W4Yfrk/3UKghfH39WDDOtH5cuUY1GDhCGcI2yRTghhfdLGA/cymk7nNzgMjix
1vNOl2GkvmSK2amQhHQej8iX9gJYHlptD4QTQe9RJjW+modiNn/70LSxFeoR+ye0zoh6pItmLQXR
RgTFHUo8oi0wpRjEy/fZ2SxlnE9nuwgx782dvyn0XQimMevyY5a8Ky2wVHeWF9jCobUHMjWWPFUE
Sn10aId2sfjkfq1JS3Mr0uLYYKQ7lBKwq7XTGxYfrFhE56Rwx7tD8ZweNKd6oviJXc0vgH5aQ0Tn
oO/sVL4ptvDjkPxLUqLURmdMyFkwOQ2Gp96mfkgqFO6pMoNwM8gw2jzthsT5rG3CFwOAVYAV00n+
I73WqnP/NevUZ4Lyjo2GOdBXohUfTHzGs3vPZiWa8ATYfyEGJXLWy6rPsmxjYxeL/MwV/56Nysu7
Sz++rhkFbz825fSLR7PRA0yJ+n7hNQ2OUrSzCxu8uNnOttG1v7HD32df1nUpEnzQ9Tw8V/GgaI2E
vqUw7cjJaIylxII3K85GZ6EnciUy3tsd6uy4QZEpJaRBWfo/vFz0cZPaHogDbAwCs4YHSSLke5Em
N5VI+ZzsrCKfofsdnhnLf3tRjimOgiGog8yfC8Z3dRIze/yDSB5ZSVh+mizxQF2pn/LvuAT6Wq/v
IuXciqdPYpv6xz2m4xKaY4uZ++15+hOzTEtrbM8kwEt7R9W4bA+84ptJ/CAOCJjVtGA0JVrWSyXS
4FwhfEgWcnPLmqWFLgREo1/ZnNBBk444oDOf7apH8kiUc5wcb9FS6OeJGusemgpbktzGQvyRU4x5
Z4VgmpKfX3Z4bcmm1+Ys1i4hJH18EhWqAigB+tphxNMZSK/NCC9MleSrktHLenOzbz4dELxvhMsp
cp0NhIgf0o3GNGSzxtG/+5kzS9SXa2pscGrHIeq8pqB4baAUQb7doAg7KiXTtuT89jSVhYFKBl/a
/PPm74boEEtxlQr+obBqAV3qihx2Tkz/i+pq4lT39OXOAx6fc2dAlfYbj8aY5Tzc17ulyz9IXOOw
k5o+MYIinlLEeeU6xQ9nggu5957U8aPXaFalV3ApWxrLeUQFiOLh2sndGupFzfHsa9CMMny5P+XM
DFz8ZGcKDinEHNmZkm3JG8+ZoWkNbiL99HDiqON9AF9LeofeaBASYHU9VhNrgK3vRzFfT2mJiEPs
51fdJ2sPWyLz24O0bEfUd5X4eS+xvX/fBbptDTyZQxTgdguxXaw0kXSQ+jtg7KZKaCj69UYl05KQ
V1FAc5hYnUE4SLRsv6S2ZOBUJDS7Q7x+PCdz+kIiPIfgADfEIHHvP+eYARWW5iILhu92PFx6jTC3
Y8obs+Vpy0aZpHg4h9ZSiQg7pjnymrvkct6nv2MCSzdFolcWJThmhtiGoNtawg5qiMPjsavgA1jN
TnLwHNdjm7itJX9zHEVUAxP7x9HfTQvBAhcplkENBIdsaGvlHK8AvTXZmnqwvAFOzuBpOlPcvS2l
aYVIRK919ai/iid1emYyYf4TfV1nEIYQ4uNgHxZAqfTT5OBJSfBoR2HiwE0mrnlLrdbh/r6Pew4w
tsufd8SfymZjvvSRQ50NGEXAo2gMYOoWdxJymo3nqE1bBHx7pZYXHm2WvCsW7hl8ozJ6lgUJiig4
v9uMBbcMGqkeAksZ5AW8L3F5VDax2nabIZ9g0F26DEG06moybZf26aBfi/p9XI+gaH1TP2Xnm1EH
g8MOzXeS3Qu17CA/1cIUgUbDi5vLXhe6eDqusrOmuCo1wG+Z6MGRHXAqvDaWZ6l9LwlH4MsuEPiw
ldUGoP2I0DPCcOHzWq51maXAH3obCsIFa5W8f1QsWzFgaCo2Fi6UoluPuAHIYt2xorObICUJq7Sc
Fpo5zKLO+PyCKs8iFHOyuAQYMEiRkgb4mxhu2AmpIBLklN6U8l0xf+jC/F1XvFagRQ+MMuUk/0Vs
2xgtzStPLjSn3jQn2lkTnZ9tz1iZMDrMolToQtPgDh2E6sOfad544p8thtWMg9RNruI4Jv78qrbm
1oFm4uAm1zoIPpSRcsi/VViyIEYAuz47bImfU6QKg8Of3dOH5JdbWVF0QgB6MylC/mEMOtqpMThk
tV/CHh3xWkxCq/62brB2FXMUYGrsVmWK3MSDo8qHAeOXYkkoUqAM+L4SLssPJ2tchM7Im8ChPC8w
QvzQSm9FnqE9Y5qbKDpYpghgkY+3Tog46vG7wb9Idu1uD8OoD91/WkDWIuYFZpuoDdxggfFT77vc
yF5m/U8Ko8y+LCO3OUWFapiZytt8AggvY1IXtT3CnKiXQsGXr9Z91qcly7eAD0XA+4LTO30yC55N
BSAKhe5+lfd9F5e6njo8hOfoVMt/pk4reaWGz6gYenDhvDJGbW77r6ubryrBfs7yWs8Gt3AytRyD
6FgF2ba3518C1PZgv+wOzxAaxHKvX9R1ulZdD02ZC49t3ElIR48JVbor5FC+6jsxh/CyqC/zROp5
/Sk3dM/2PZcR6oFXdXV64GbRJWOvinrPU+BjCjMB93yXyywtyFMa6KZBjNbd5kUw6eO3n/fwr8HV
nGE5bEah8rM0pLavBAbcVPLFEcj6S63nWkwqqk4QwnYsREmcNxwxPYogCbIfmUu9uAeycHB4dHzu
4eJ6lwhq7SHbBnN6ZIyZuRt2iMTWpObWr4284DItuxTUa3BnGeBL7vU1xGZIhlslHcyOZ0YZYOUo
rS37+GaH2pUfJIB8WizQ2BSxxrKyoGKSHhZgwqi1thV5muviZu0GqOgnWGxF2FrqSriYOlBo+RT7
wsXgu72kOQasOLtIctOpukIFJtzjVyjx495NVxN228rQ7QKZIW/Nff5neZfw38JJfuY0EX0kTvLb
7QmP22LRySs+hvR9lxCWML2fJ5CQ3vq+Kqn96gPuuExCAHvzmEjPYboTB+bl8+u4yJ/UlZURU9WU
D8iGjJkUuV1noVdMsMDOB8CBSyekCO5pVyUM6MSJTFXR4pEtnE+le+eZjzhCKFZcLe30XphJ0pcM
QDN0mNVD178oYnVUgzIv6WF6IHXmYeYjMvAW4eejKpF2P/3o1+ECr+K9S536pvF8qtxzeorz7vTi
43AhN1FZoWluVh1FjjxNI2stjLwZYRMNM2TWH/S/0ul7wGQgQFV939PxCh4S6faHMAAaddjO+mr6
XK860i9f8Xrrlxp6dhmYKhAwgnCea0emHSpiPHuig4SuJIu25WHAPYinD5KDkZTx06mi/AWne3rg
Tu6VSE/S5/NJAileQ73eQ3PYUkEREkONOswU45Sy7gdc+5UmwgEIei7EOyLG9VPUVvwq51dxlwNH
ZRWV+EvBWlF+pHxjBevXtZmbuztxaDeSyz24aXcHmL1oXI3f0dT/QXOAlHlERReCjG92/0HpqLEC
w9pPUozysmDKyOHXNwxs1v+VIWEsLHyW08UWODazE6slwBgatKmqdqXXtP7ug8LrWtFCKTgZq/nQ
zHP/ChZdw4Eip0zOKmE9M7j4JeYJPU9oBB2+af7BdV0Pva6Xq2WNIKIBC43nvie4ymjBf8aoLcWJ
q4dkm9iQjO4iRCCFkcjrYvU8kx7oeD0xSGRU4+6EjWAPC/8d5V/Bc8mXWynBuP7ZvZSUtUEdmmbd
hWPBCesHeOwIXvuvr7Rqz/DLXlkcOKX3rzkiMcSSZVQrIVtd6iFBYFYW5dpNfb76/8JSeGiNJFbJ
aedQh7ec9cMgZo32Kz5gY2g5XcVfm2nUjfunKvCDxWJirGEA8deQxrqjbZ2rZeK1bRRnBukG+I3D
EA812faZdxSoNONS4epVjeMXeOw8kRAF3wTyFZ9i0FGKezKibyh7dwQZe6z/njO0wx3BLvACXMzF
c48eg/RzWujgGt9sZhkKuh2oBWPX5uPfQhGJsg/Ynm/rKaWIP/hnwzRfi8GyTs8Yk7KBmd852xaQ
1EGBEyBOxEK3n4RNkLP7j3B/UbdmlcrPIeGY0wYS9XOC+hztnj7hAbt57t4WsRrddokDDtF01yKT
695ZmXEXM8zgN8mTjNoe/waIc54xABuL5NEGsd/RHfO+0Vczcft5l5SIFhtM+QWhFRX/Xaf2wHqb
s2Yquk50NGnEzPzlSVngUwmQEx8/9DtYeYIAkGkebnvR8j3BYeaBvXKCmRXW/wT+4eNDHdhvZ/oi
D1cHsjoDoL5E9ZQBrOd2SQMe2j63Corvs9OjvncvV6Wm151tWa5lpTueYmXucGzQ68bDw22elqUo
JHWbRpbALkQo/gttVO7vQy84jrAv4UPJzofQlG7ZApenASnQL9XbkMGyWn31fAifE8vam08koak+
IAl5w/broMPLw+ZmKW0sN5RZj6ei0Ky8nMun76cBI8mxu8VD4pcwpJiPegi6V1WZqNh9gVjbMz+0
NhTxpT9a3IH4nWHIU2zAShbROxwdnRd2Je+g938GUn8+H4KHmAG/WOdV8ksFbuDLmNJYMF9OWiAd
yVMTWeGD0r/ByBecvNKtZFMh5DwDDyOKOeGoMa3Yqqg1Pkzeh1Kfcj/D+ELinMraO6TDAT5rWjdz
ynkn9gvnX5zfzCahvsrYB4XpXzM+Uu9kpBcIAXRHZBTF+wX+hd8izH/b9HbtsisEpfMZ0IPb6q1p
zBv/TP+5ePP0+423BXAK0YZ8TVgKPHxpzLa2BMa5DQY0mnTo/WyAQdjDk+J53sE5sFrjL11Q/WNP
PMNc1yvtPppsXLedLPq0su82VqOm0Q7oqO8UbvQk52D5wJXD05ap6Af//cNxsh4XvRjjsnusm9SH
FG1k8pWSbw3GmvkfRR3S+naGk/vZkYlmWTjYlaKGXHEaAeWSErp+SIIyorTM8PCjUOpl+WVhHvLr
06cMcMAKbwIIddzks+HfpNlbrPMRJZpXZFt+ebR/OLKoLA6Ge7sm2qG5XCHKwKofBzClSlUr8d8P
tq6S+NxQE7hybptJiUcQ7BrItC330gXQyQb5qbsLFjFOT/P41BontQnid4YRec48zyXaTW3QS3H6
4yoXjHSdLqwMwmnIJvTN6GnMn/YwacXwrcvXks6sN+KoLWGO9jOZpRvRt+SNF70CpQNhjdRFCUVu
vPmMsKslr0Bdd+W1G+Y4a+j/LvXKgBNWbvfx9S1O/wowIfNV3DfKkrQU4hv4Z52cnhHXvsTGGYkT
jg8ZELPs5RG1QhIYh1x02n4eXhPBRp0vgmW3ewDN9m+Ozr40Yzj6nDZI1OkBbVn8aEtzeLWixpDS
nwIYj6VHN/D22/zq531Lk4JSAXW1CAF1dz/qS722TO9is2U3FMouxYnNrwyfZLQyZJMHKrg+d30k
LX9E+tPIjtWG9O/IkPjy9rG0BM+CvWBh3yE25c/jmf4S56e7TtT2/9qRKylKsrXIr62FXdSlD+SZ
/oAGVPuTfWou8jcP+KMYPIJuG0yQOz49r+Zg0rQ5ka49lDDL2Ipb7Ba0HiJKDTj7+rm1WZSNzYxs
eZOwTCRIVuKruhTDUdmHuztuyCb0YSZulQUTpd4Fg4A/VbBwd7nqGdDaOD4pv3+cABZW59fBiyLN
N3gXYi1W3t5Vt7OmmWhkgy30hc/E/CrI98JqYWJ9vXlFH4NioZUsPbYR3rZ4TIOfbNDvdYiyR/98
tvbSTQPkobdQn/K98pWOIn2vrGOLgF44lHAfSEWadaJ5yAZ6kpPgfM0R1/BjNX1X8BOd4zwTe558
aJxCFro5Rwoolv0MCHfnbpBxBqAbTNhoBLCJARFIP1d3K8nebvRbqqmXkQOtpvFeS/X4IhR8YYDv
3qndW9Aw1PUmvUMPmXDkr56YObL/2gltzd+bSaI8R+w+bsSzNLf+wkbSRqnyQhhc4U8ZgvMO0Rqe
ZpwlMPZ5mN/0kr2gbOY0wEKDx8J0iHcY60lg9r02b83jJ4Ry01KFaLVoA71Oj61G48A9azFAxK49
lvfHjBPNLmVQ64R2hE8BRmOUZIa7krhvc6je0gt1Tg9yHmW8LoHYi136m8Br6zhMy3IDEMoq19S+
21QFXx2DJp2dPVMxYcb74bQCA5aOAxX3WQGd5VQJVa5VRfGqQsba4m8oez6RPI8j4+DaQ5PGng/q
/OjlSQj2rxQvwhodu9LxSC8QTeLNco4Pex1pTd46W7YPV/fZmqfMWAGl0kREBPRv5yNvkuvsjhM6
J22mV2QnvF6J1bQEOBEDaOSaLou56HwdWD55/mBHDWf9h+UOb2FyBRhUP9DClsFNl4JWpCGdEZDe
M4/jnwWTGa6RvDF6JGFTPhgVFb+trDCL5rHAKPxqmi4DT7L9dX6T0YR2YzFFAPb2l4ihpRqC4LIF
my7dBecO/BLoXqLHP2QTkwWbqmiwx3LzjtlikoJ8kHWXfFvP3RHhYvXxX2VlLOvMvC24mxU2WHRk
jod6jfu6q1NOnUIkbaXTKUlWWPTO4leOft9ICOOU2jwVy3IR8SIm2uoMjaOZgfqLzuOUKB+r2E5P
Xr0fQW6N4rn5d8nLOJlDHPM9wrZOp5pakETqHsaAJAg1xAQmJwUorzZFgW4aA2oqludzZUDUudGH
p6BBqOntbf67JsbOXCX393xW8J+kTpO6Saixm9nfe13R71yHMz6+RGq0icDoIyrNsgd8K8apDZOg
r19n/VwZj0APOjlFQJuOXLzfcs+kjfSrfv+ewZCNOjVDGZBCkKXxejwdMjMnGC42nUPNlm2rJ7Tz
nIVOcIk9eRCgIItTGgQInWHpMhR6psC808rnoKBatFODmXtujWaDXTjvbqZ0bSGvvOv8RbkXjsdJ
NmmMDWbPzU9enCWPHEVF+8WYoaeG02Ca+leduSY1ub1dtwkJbdw4xYxpLoMn0XZEjT+xapvQbgdH
nx+ZtgmQKQzqO63xDvxm0u+RtVV4Ov/KTyU9nLvyHYc9F49lIxGuNUOcOwgTF4plsI05ZbwRUYBU
evqHioU6nj9YHUa/QkCnh5/obe85ZWk5B/FtjRjz5cvfLxZM9PlwaR4JDhXTTIqtTWVso9S2QyKc
m4KmzvFj3oP9EDpkXDC3ZtJM309zlEbltYp1JzqDPPvfK3iNbbA0HtaLD1dNGV8dmZzEU7OC75a/
APQ/KbTechpSZhR7PpKWS78FtHC/ITOn64NiUb+36cwKhxNvAqeTxzfJ3rI8stMwdBiqQKH0EvsW
FBKOaRyJMeie8pOlBt0k2VnleKLzU2KDnt5Str6X/Tmj4JCqYggV5GbVfsROvQrp0SOjxlkZ37dQ
Le+ely2674JDxFqykpuomLxdKBgVPgzTRmZicbcxhWFXjgRI4wUywFjp3ZRP3OKukjO7L/CoXIlt
l/8irzf+mo0+97hYMVD78/tAvUlOGfLfGVgvha7Wir18DvfN5qyHst/excaiITip9eLwlrUASpjE
raeAP76GI/Mx2GLjcSlbz4QliLcx1zYd+stPTTm4yPGT034y2BRAuMphk7FIVYP0wd+YG0L9fnW1
9m15ch+sypH/lGhgRaKfvSwnGPpdlUbn/cp+KnP35Z767UJT/gG+4fZc4+kjDS7TNYS3lpOmVmu3
8ta8r3eoScTCU1IN4Tr3IY6uT6Bo/71qTPGxeXIrXIPE7bqS6UFahn/NPS00RSzEgxwrm38IwMru
GCz7xk5HjcTdr6MU/iOeqn31S6PXtqsKmVgGTiuuhHQFC4tbdoaH6dVihL4pGo809BIEER6ie9Vv
sd89dhSVbVJVdHJpw3xr9osfuIcPEPqGhiMdqxmqlCx9X+82RJJAEvFpEcuVbF2+r0k8shdVCyPg
Aw09dNH8EeEsOYzlQ6gwo/Arn82epO4NR1zbhqUfAsrH0HDbU3zF7F1d64HfjWwClY9/XDdVEvLP
WKY6c22e1OWhdmCnXEJ9vDQqZgbRjSZdMaVJRNsEGGDx9/3wwiKIvBmem2Y3vetNgaWa1zeczmvr
47NPBJ219qV/apHjp55wrtU+IiHyFZLb15L9pMqSj8n7VnoAiCNpuWwO6L/pmFw4ZfomlXk5qkUG
9M0oj3Rt029uUJhkZiBnzDXzCZMFNFJuOmNeyjgzaaPcQFbAvfLnOO86Jd7Aem9/c7YIFLH3NEKK
OUjNDKJDOtOvSalUijxKaQZjZaz08fz6YtvebNJ+9WUjMbG0ctYSYpB9Yv0lasHOj4cJ514u7Ml9
3eX+7ckn7i+2L3K0mhYTBfLRSqNWpglJ7l7XrEq+SYTcknjqvBrSXlMdHPeUQqG+4Q0oVX3Rvde6
haXN2eDYqA1eeJAbKzP4BdZXqlU0hXee7TJzdsXdrK4g6jVsMa0qw7rpSAoGGqRfwJIgaO1S7pjk
wSbTZCrhaLutMLy0oIDRwiV49bRcnMDCYuaTBvSjZUxpN/1YLDJVrR5f5rcwINPUKJ+JFM35Bmm6
nhf7+2JXDzzH9raANyG1NzH4aQWE7a617T3NTsUtvHR8bUCH6ujOOZKzkaRcwgdgaHLFLSA/b9wn
pA67vEuWT0Dfx9ygqRgalEjaMY8hHmd7kWurEzTQhl2/O65FbIV+ETnjrqb/CUS7PVT9sB0RdFOQ
yJ1Hn3JmDTqrLAXJ7/f4/zMX0Ir12xkZun1nwExwZ7LzaKE+mH59iQN8X25SBm9sfQqMcCmpbCjg
nhJXD7BxaxKlDCuhDJWjoaQCjStjEbmiNJLX6+2Q1hkYV8BlG3g/E27hPJRNVa5xCQRFG2rNxEBL
+8oVnXXHsi7INVG8tJqkG60r6/jQcLZRAOiTFyEnmFkHJiF0GNHII8FVMUi/kS1/o0u7eBM/tuss
6p77zcWKZ9lfnTsE1NSKn6Rl1mrpK5bRuUvEpKSoC5e5l7zaEXSiLyE/D1nI/H+7Lir3PKTkwVan
3PVNhkLChQv9YBWQERvtFplq8f71yU4dnPmKvmLhStFtItz6cworRnTjNKBSsCr8fWIg2bbcelDq
PgHscB+DJER7KqVgcJr+ncHIyRhJ4t8BlOWf5xtpaAjj3zzyXXDmqJ1U1Mb4RDaJ9x8HAIUebYfJ
lxFJD/RYbhmdXApGP0KiEn+dN5+hPpmTAMy/hZTNTvPFhNqVCZWDnO2CKT833AH/h4HYh6QK0p4g
QoNLjmDya6FiEfg4B1gOfw7a3HWOc/9fk57QD31VtLnLd+pSAYZDDcHGbe/fR7yTLrXs5xnCOqvm
54d0qV0RDeKKpSlLgP7idRPGx+fZYai+KPfDjNjj818vngNzkoGoaycutlrnLVfDL2sN8DOqsOUF
anIEkAv8PSJLzVcdxcn2XpSZMDxvZdwWsJ0SEzV6EU9POUgZUaGZXHE+ByUIfKHk74vM/DAWi53G
p+dY9QH/pqZxgcXcmofCv6my8N22pZT/meaVSL/HRO3btA7E5ltO6OZ9+PGbuUf71iGEZHUKSnEA
uStDkey3lzHkKhRkJwJ8t47rufxugEc7s+wCF8kz6Wk8V3sPNTA+cVR8AHyDwCRItUDfbHKMYYVu
ac14qeZHZLkd4nRFvO+Em3QST+2+yegKGj9H93f89ecS0eJvzyolK3fC0qzAlK0irCKALZJ9jP1H
HzrDCYn4xSWhvLCdbHXzkC0TzO8oSSvHg0BBmHqHFBxNbh6Nk4DAQRXVU8cnOeiJMPhv387g42ZH
73iTlzOUJl66qmzJJuNyYqt/ubDiNOsFDpJtNNRl5QFbanyqqiUani21UPELtfq+sDoDY7g6bEAp
tBOOts4Vblo885yOx0GbwNibhMp9KQPANtr3qKfNKyeKdjZOx+xqnWgtGrkMmqfPIvnllTm0oj7p
+vBjPng0zjYgWrmZL6y9WOktf4v2eMTq3vCJ/J33xrbyjYc3OdeKLh3K+I7Gwl1I6X4T8WuHYTjU
ULzye/rMnc/z5oOuR+YwEVAw8W24eTkcE/xYGhGFwMq0TSHuW+n4+NOhSCulHsdp0fsjul90X4Cu
Kxd347bnGlgx7KqdYsd1oH1kZ5Oo5xdNfX5KxjfS8XuWVoqyPZTWJwKy9I76aMWpp+1NpxCcWR87
SgSgWRyFLf1IZx1OHJxxtl75BivAftBveK56SRkHaI3qsjVeNmw2bYTX61P4vO2Oh2tTy7nbOIJX
TtFBo+U2EBSl2WTbTdhIafa2LxAkKr/G8rS0VgqiM2k+gqWLd7VcozKGDUtx/X2+88QKn4LoTFKQ
G3tobdR3/htbahvzWKQYok8RKS7yVjslGiCJlOUL276HdskCQrDYl0IiuXpyhTQZTxVxqWqoWvBp
1coYD+LrQlbRFnBu0XDTDZiGtjldlnL1XhfiaN34KnDqeYfgQZFeRCOHPb90UONzHvGWuluWfvGS
wfWFz4qWNM6lquL4RaDh9FxsAbOwUBqeNIoTS1AaPGzvpU9nA9+yReBGSJXRTAf7pIH0T5rkYPkU
WI5+5s21MboQ55OyVoMMpx0pIJG1J6RUuS0IkeTWRZskbX1LUIZiorERIwEHW2lvZbXQp1nK5fB6
Z7haI/rejvwIf1sSWF11r8ibF2FWnFq1/XORp6IGaA3VUkG00TVn0TmBZtMSJdUnX4RgP4wemH96
5HwhcGBe93dVG+z9Sz6fn+UCeE5SMeLRMkkTpal5EjMN2MkRByrgCJNI3tiU1p9Lg2+EYEYQGkZX
OTP2dz2UenQExHKRY9JCvRXmpDAWbQH+5e8bZ8Lxr6J8AvyLw5wONs89S8wSxGrIktYOFFwkaWtg
N45JD72dOXWKcsnni5q6YF+h1bSYfgAVx1wOMlLgD1WDJ710kgL2aqHGB6iUkA54BEpnxMa5MPaj
WrLdgniyx9mRB7xIjxE61Ekj53uAJrIKekZTTf2o187QQbm4CYt/fByTXaUPjlI66XrNxprnkeDy
lNlW+bZIHZoC0I9jMxYPvNECB2TfpiJdgsI1ouMPCyuRIgtesb7kHtfXgNb+w/AoyzTWIb2VJMMs
01mpLUYfO6dAA9VeWQERwZTGA+OFFmcetRKY+BAFv4JORmKET1Da+rPOcXfKeiCzEyMqsRmLnDtY
+TXf8jg9X655awXFjkIv55uaBsRQ84gEgZRF5kFbwjGaNomdD+MLUFPvjrRoEMMEGRZDTIExnicv
xHNnM7rodwsA/Yd9jK+R/9qdblP5e3V0DgvI45nl8hsWOkFyAIc26oBHxF8x1DlZd89qV6+4lxT+
sR0sXejYItyKNnRops7tLl52Z3gO4KD0TyvyQehandZycVdlpZTIgASiLZvNNmC/8bgOPq7adJwM
1A+Hfwv0WFZBdzszr8tW5EI/FlLJ32gwwEplE+tY3sMpS68cHqrozQugh2r5ubx2u8fcp7KtgMsV
aDq4Zuguz5XqyEipHJIP68tm42NtsicL80vDaYvvNvoR5symGxwwVGArxCXxDhiyjkF71IghuXuD
RdZjGJVZ5W7OldXqYqCHuOIFqAQLC+gAZ3zN0y+mo0O9YGbXHpGxj7OKvv2sBNOCmcXgLQVu8ekK
/6cIILwYZ4/LP1ijzQDyki9xYLbB9RSMrmASTBPLhaMOkonQy34IooxzBIpHGSi86oJbYnY+5/l1
rLNYsSKUWy2Evi2qLVMpkQs87Le+2acehB6L+mGkZraJxoZuizYGJFEVsWFIGXUoCiMZu2LN6XJX
JTMGFGovEMfxYK9eHBRYMdD/gjeQ/lVXhS9rDRnZYvES6vy/l9QSuELlFJYHmhdYQr5LOP9MCAks
gyNj+i0IP4zXbpTFOnZviygPf2KV6MZVK0t5P+23e0I77n9JxTq9RSF0i+NpL8YLEnKg+Hph6W6F
x5Rw2a8IFayzl8gV50ds+OjExM0FYBNIh2Ye9EhINoWVGiSoH5flnTxNDbB2EWetB/uiWWcr6lrZ
4r1YBBfrEB/mbkSXUqTeO+76lEsCTusQ6ZWO4Lwmu29M/jy+cgoRxypzsR9XflYOL9MUP2vc1y/o
AukvyINfUE5H1NSxN/8LVdvbyTqN9YHQ5tuklayq9HFpuMolFgGVWee/Pir0VvBz/1GyQEwLqyHj
AQ6Z2OrCrwii3B+Vy+KLjgmJxJmIkFkJEonxHoEmxEJgQ9GHoXfVI1dUbPJ4sOVYUlJe6uhtzDZb
vI/yoNvUZSlKw+gDfklmndCf4htLUc2hXV47vO3k+XwbA6TLXEmeNq6yVclyj70VDgZ6f0RuCl8N
4L0gHYTOuOP5o4DpO7SQZmaTD4OmmGcPrxUblovxIbYxJMQzho2pfGWdwPnIdNUFITigvd6VrKmm
6jzjGomkciGg0cZywajVW1Ib4q1GcmyKco0yD1BbaTH1aXj7GAxqMw7czrtIMk/eR73Y8Km4sqEw
cnFWYcNYzgH2BNUGSNgMA3HrhQcBfeAiyh2KGzKoHGHaFzVy5L+nQL4BjBHLXVK+/HhHqAvYlVCC
Z0In3RaE4KzvWsnx2xT7en5Lni1AmUgb4IxqMj8UCHnQPcVHL2Hug/kgeT42cHXC/WGRNLUR/W4+
qQXNy3qLPSL/OONW8AdOK4yAZppKghHCgWQH9N8KyUCySSz4ppqN3EsVJHg4lJoMtjTo1BafuwH3
G+33nX55CUTCudetTgzvmwUe8dj2eSiKX1ON9pSDYou+qm4CowtcrjwGU7nz39DGT7ZbFzo8MHNm
kG+PPkAyfJRkHv0fR+gF0LIqZT7drSYMrmpXAmmuk/qUlgfU6IMdusOu3QEDI0te3JfKeJDSmH8s
kOVgkbTnNq0eFyYMctirnmS6MCzOKhIRNr1KlS6rLMPc//BhG/YS5eNoStH0ZF1KP0/RjdYYznEW
LHLgS66yqxzKdoChH10uigIXwsOhzU5YdTna8jUfzH4p1cvYfhQxtHqOFoCMbzeMh2tfvOxRukGp
uFDRWSMuQYC+j9ZEXUsGHYdejwyE7ovm1ywKv3U3h8RrXmfAYgJxRRMeirC7OgLF3/4UjSY/ANgg
FKvlMu3MT46V+CtLAktyT/+QcmD3/SN3GST/X2DDlRqMWUkvVM2m8VP4xioocp+8cBUaDuSNje3q
zEDenLYH1o56UbUivZ2XjRCJFgHRWn+DirzKfbaXgu12eOQHHTAkB/FgMc1Hz8rLv3Q0e+zkb1oj
O7ENlCQU0/6PM0SZ6ZS4vU8ms+LQrTuvtHwwRYBA8xxNs8KwIKPfCswMi/Rl8TsWB0kf3S1MAMCr
n2qeY2tY3OCtxio7vwIw4eASNOA55Wdrydk+r2otR8NjPNJ82+IbbnCnEqV46O7cX2kFMqwQu0LV
dQGARF3gz9mXjCfesD/I+VRAF+K36vgHQdT7ScF4wPjjfEHDpbZ3XiN1lBN0N3DJWcVJ4eZbRck2
tY5FUqhoPVlWFgDGxphAV1zMNpc5iHkdzs4m/cqlUsoJ1tD5jRDrhDw0yUWDrNqfjeEgvfC/r7qw
neNT/zv13O2OFjypNmULf4Zx6fzqJy/Bc4XxeUNWv5j/bhbw/npI8Z6kDla/yqq+TTzIe3do3Dzd
oW0ZqjhruqozhKt8ZpaXyPbYmF+pFXgtu20fjABg+NnJbcf+rOihyRcqSUaVAFSuGMT/zuvA2J2S
OlTskPe+jINlgdwmeilH91QBzC/GQZuVrjYLfdLGAJDNJIPhvAHQNPP+yU8AoOfilpKHjrWj3/S6
fiffZQ4WD3hFuZ6Ybl7zfw4bVKcqJexhblDJAB9D0gEvn7iOBIZd9hTf3BjEQGgmoDYBquJUC8Tz
T6sjpHhvX9V4MXCNeQjXFl/66gCI8JIh6LyF8OnnMbhKsBDK/ULALLAXOlvorwf/BsdJYat4lrA+
Kryglm9rKEPz3YwP4yqckP/AlnEw5lxgAjuts/PxuU5FEK+cb8qh8Bc/HkJ9NB674NixByndkc67
YoXGjj33dKPs8pLT4oR1fMznSR3ETJkCD7WcWhW2GRlz3QDF/+tu+sUxq6IhamkPdfgw/w3bd8nc
NB0CeQUQBE+wuLvQtU8Zcp9vlXpTFijLOpGWY0bTHH2vDqR88/iBHJ/jFWOeqGcd0Muk/5d5tNrb
4uAe0pSKaLU46gJl1xaDYZUUYAS967BmPeY86czqCDuGTV+rYHZegfhpitaJk+23Uo4mG+AqTIiI
0PEsAgxyB3KYxhh331O7VWED8nBEh9W/ta7iqTOrI5yABfX7/vm/hm7V5+qbJ4J8Yk22CmmLGSKB
TeWi1tBeEUySbXJdrllqDrYTKhz5K3pRI9hfU3HPITwPly7jNlqPmraqlmsJ11j21TCB1cyfqJij
WE3Bi/tMye3KkkYE+pqYZJzSqHxsKR3W61uBDtAdle/ajqryvXh2YMRgJWb6rLJFkNbOB78rKkVe
il2S4u+3FsodqhTgZvu5fY1/bdegw+e7jPgPsdilATcwnTKsAuoVi8hdFmsIj94FEmGTsCXG95dN
gjFYuA+qFVKpc0hixO0y0JMp6BYZqofnJsu6jF1vNglR/avv4q+03DaYrn/LXvvlmj3ublfpigaL
ONjb0om1ujh1FrRcWdwe2Y9FojkkqvgL+yxZXH7K2IPkt29q22xEOW90RRW1CcdScCzK6mZ9ccGu
Z4H0wbGH/762iYWb1iaIv5DOH/4Kpi8+T0xnBsGSeDxGi21jh/+z/FLGwgr8hxJdVjaprPbcFuYL
TUnqyV9xmATemrk/PstYptCO79cPs6oDPhcz/n0t/+gWou3SXVx5TeViBALHoPhd8pBCa+p6d7BK
tsyDX3FcGrhvtZdqddDglfOKoOnKSCH6asOUv9roYM08JMtvrt1FOKQkZr6eX06h10uQD73I7eP+
LfWo9zN6i21pdBD4YTqtPvdqbc5QAb7bRqYR9Y9jAyNxJkcJitziaiueQD6MMrxlofbfs9zmPnzY
IjnhCn2lnO6s9DR4Aym5U6wN/wJxXIFVbYTaEVhXXIbTBANMpK1wEIig7weWrcLEN0OV6M8FT5pC
q9lMhPcKvMmWfBbrCLx1HDVxER7JSKNqbLgpZV3z1MsLh3t/oPEH9UoQfYac5xCXRkC5PEbEqt4a
mw27VXWjMvGDs9I3UrIX/zM823t+jN7z0c7uvsAGF4ztAnse/BFHL8tzg0WuY/aP8Fc+Wm7eX05R
TuwXhlmZ0ChDxF2J7+PiEPDFRHI6tsgRXF7LF/nkV663nwXF6r8vZpf2d9QyY0oHKiZ2s80PlDqt
qyjaMc0HnQs4LwCaxTzJHTEV0ExTyOng3O7vyW8k1maoYc8tIanempNd88dJK6veh4wDHoxJgMlB
Yt2LVXa3g2mxzArUIiy3SExbKb/ULe6815egTvaJL5cHPal1fYv5i8RLWtQDecbPqFnQ3bXv8snt
CAoqwM6WmjHVsJsu+ru50+JNkb1IJHcBJtqa+h7Xq3E30H2ryT+LlxKzWsnOj095LMrQMaVvafdO
KoTl53ZXTs+h7YosT5wqmvRPYqioZ1g/AHqXKEqXWPjFZrsBp7gZcR2/BkvJDZMJphzVkZGot2G1
02cTMBY1Ttb51/c/leWtfYrjZE8dnbhWWmE4LggKJJVlzOEh3RKAUWUC2HXMBb0ecKH2mtTEx71e
98wVUPpJbVdncz+ziiJN2C+yU8v9ADm9ldW/EyJt51GwgSvxw6COBSzBu179JRH7Kz5+HOOpCV01
fpCvgkSfH/iPTAiT8D+RnK1QgcA+Ozomn+z1QZo41qPleEzjQAm85MKF7ZDMUUo5Hkiqncr3THIT
1RucMf+mEC1Ok1XE/Wf4V0U8uMRIM7OZRNYofUtn4W36dEtbm7CoIUFfbDsF9EE86M7HgZiKWcbR
3XKK9YwP5q8Y6d+hwYQg8LKt5Y6s7KUOZdaVGBuewYY+v+5jHRhCH1NYeUu/9xWW9zt6ADpscDGc
YRyQA6HrciExPIZ2IA04q7olScJ7JWq1U0jgVFAFTEYQ0dx3eItKIiQkv879H2IsWnXcWimEawKo
gMjFNLeR/HLlgiqPy9OTIE8MyX4pRzKuGrnQ2fddRQ4mZKhh5dGuJ+ElVzFn49avcrNQjKAIyvwM
Ugrivu1KmtXh2citpMaS36gu5jZCH0p8+JMmyQF5RAsDtFKQgjXb+B17lZL/U+dgyGPxXswf0wLD
Nvc+lJitfJs5o7PvtV5bVkPEThWkFcx5PwaGZqBpl7WH+e6uiSaTSg8pyA9NVWG2nEswUBd6OBIh
3bBN4K+QVNMLPAxt33D/ymGR7+gRtbmW63YWZgYXM/GcKlmcxGhnYx+qZO5ps+AalTIQtmihkswm
ROezwwCeo1KJJExaa+gCAiNRx8cg64TUmLlvktlpeqOoliJslLRI0NXWlk6N+KTSgOAXmUj/4S6g
wL18S28+fCRIlFaqfI4muHVxI9eewGjlXsd/zF/ZDD1ZFPmjq7QPUT1BYcUvnrxrvNUA4A77UYti
bbXmVwyJiIOYM1unKRfSMfoQ1PkTaW+g0Wk6rwCuLF+fRiiHlC4thI9a2bKh2zmQTkPRoXTxlqL2
ht5uJvGlGdC53MoplF7Zpma8pcHSoxom7t0uQehxeGyuwCN/bSSZxRoKCZtWFQYh/jcqqUR397y/
mDJE4oyxQYp4guz09AnC/0JfCgrG093h1xPUm4AzE2kyxxAZfRI67nkSV/tfqu6TZNYXCOL/Yze5
pUj74+zLB0s56JzIxPjH+LaEG/T1WvKeNWc8I06sa1i/S4Gnx23Va3e2EPt8ByGos2kiRGpKF6C8
5umOP3UzBExQxfbIhKxqCoYLYDaVqUe8TIWrmsi27zQ2AqD37O+tuQjr9KqkJqst/5486hGNG4dn
zL7Y1AY+qQFUx1qjDT+NzVev2jvG/qgH3M02HBHSGaKJNQbiSc3FV/7i/r1RYoj1ZzzY8qy3bob0
pJqX1sLm/w4vMDiQxIMcZokYtj20Vuu9P+cadnXFx3+B7KIEwTBYktQm5tOD0LTreYq5QnmXIXcu
7MPnKEcpoZrAnaU3TReDqVkBAB2LTjSWesp/HqNk+RKZevzSrDgPc6q2vDwwO3b9I+2LexPMGbvl
QLoK2yK42w61vKAoR1sGwN9jWWWXDusq3p6D0ofPglZMHvvxfVspN7V9w74s3nn7RrGyUuGN1VfF
dU0ojZBrvtPkCA7hDAMMZIOecP/IsSmVQVL1oz//qglZWmVB7eIWMSWbZDxmgBkU6DgFuxNomSm2
xMubm1miqSxqlCNWRN4LD7qbw6hKzEbM2r+oDR+7ceibU+3wrGSxSomgJpbOURQeIsD//iRwGDFq
fyiMAYF2sQsC9buzM0P0Da3LLGepf7+jT2dfag+FCqCZPLqUlFKkbIup4js8ILMbQFhakvWkiHZf
PwXWfzpoIR9NPBeGSkhJCOLNiLB83vLjgpuxTdGUOTLzGprt9MDiutLKHU1PykwPcUj6JpuZvG9N
79mIeshOSpBGMMU1F+I8R57kZTTtPi70pL382PWXo4poHujqGfyMaf0w9r9F4sNb5cfwZwEra80e
drlppIwOEjrK7MM3N7xfk8fxGCQEpjR8ITBdDAg7El6QAEWJiVUt3IvaQHudVdirI/S0JSz7/j4j
ulHmnAH+RdtRl7P6sEWZqsxdpY2IUiuwYg/XoHzGXqPsM7LHPlyULO5uc2kelx0Svo4B7qPdgvXQ
kvdffWf/HuWjLJPy2MzidVUSaAvl/zJmIZtM0vSai4xGhR9wnhS7nYceKRUgJG8i+xODZTxx2JEq
WapvBD6UgyIqrw4sTjHusR3FOlUbv/SEqzEAoEG7heL2WQliqnAAKeYu5dGPoBsLcsiYWcEnIqal
Pi/gDd1wUDb9UIRvF55ZlkxYCjJhK9+JeUEf8S7xF71ynNn9NXSbYLuDVLlPbTsNY+YCVDMkUO/E
3OAifiyIN/+X1VU0nAKO5y0Qsd1E+6eQSlOAp8EdVQUu6suapb3Enq1Q6eCPnb4nmKffaLQsOdzC
5+C6BQBsW3U3USDzeOC19r2Q+R3/9gDfRNXEU1KwpXTn2RFnayQUaT76HGhlQW2ikhrC+tP9K43t
wcQ0fIc4vaEFSFkNexGEUfIpNFef7/X+qibdS7gG4aiT5bBRVf+kBQQlT8hcDyPXJ3QxU1SUmCQX
DSjr1Z/nMYBROHjVXAtrcE23bDjH2aWnyTYCjrsolJ8T13aQDNhapOeTRLtkZnCXoYtSPaCgUPon
XaFgDTJAGg0zP3Oxp/f5O3w/+BkJVb8Vcn0X68OXWnioQZS9c4SIdgQ5Bn/ad7S5IJMGmRWZivcS
GYyYOyJ0OSi39ORtxoGfH0LKm2UEXsNAxKeKyieH9U9NDVmWRZQ0uIWB4FBdDM/tHC/UrlsVnva8
p9af2vpelyvLr4hwZnXXznMy4BNK9fJxxMshe+emD2OTbOdwIgm+iLbAQwTgHIafBdg/3wKqQiJp
MnNE6lJ3sqkVzoga6H0qT1R+urbKVRKRBI4NErf8drwW7gcckygV40bQ0eS4r7bbSmZoyccksBn5
8CGyAApl4t7u5HrdN92h+UrtZtfvYWGoA46Vlo3lI2AOlQDkV2CIMizQHNb83cQBss2YnyFcwy/J
IkECdDpZ19/GCeujmZqgHNArpuseRfZAXF8z1W1CqplOBRIaz8NeoLkpfArL+0K4jx13wMY8kHos
UmQBaexnSIP/JvgBOeqMJaI8A9kY2QY+Q6dAuC9IEjV73b8zlR05QAYWi9BygFTHUxx8adM1mNQ9
MJs0hRkqqUlyWpMdhkzdyOG0ta+eJbbGb00Iz9yfCat8nq88mfyQYT/bsyBFFkI1BfefQ9GKnZ76
4ImqJY+EX7FD6IkT8Og+LyJFP0T5XMJAnYgxZso8psQCrKXzksEZ/WWd+kFNjxmrOKGmQIV5Xoww
L8v6aF0WkvPTm4YTy7JSYXf92kWx3SBojz2R5ulvk8CQjDI9CO66yysBm9gXncoSkwpyu9IQsiII
tmqYxWPMfXTryeoYCyA2VAPmVcV+712ifcGLXJASh0Wx2XOU5ahZqKlPXx7ejmmh+72CclP+4qPt
OXt58shdIh2hFZcoysoZEDSeeP8fQDruEZTBTN8BqP2Y4hhi6Aq4vQl58KidDXXrn/fbDlTXJdI9
/APstevzFqeRQTcmF+BU6hPS19NlgCCYbQgVa2/xr4R6b3O2RUNUhOcB5cXLLH6Wv52lbpn5CKcK
ncqbBbHVePRq+ATMZytJ8dpoIFSYR9h/Djhx5MLHprsj+AztwsANDHPmEARNTEQtxQH9Km6w+Js8
VcIIKxCjAz5QL4LaWEez3rE8EJb1F1TmlI6ECSK83fZzKEuO8x5qCcNxHnJoLhxdF2mZa6eyvFJB
mRm29SVJhZoFywx9hEOaVydlMFIX/RDD2pO3qAvaicPT6ERqUBRaErmx+AFxsqj5SXubf1/5ZluR
hglEcYgmq9pg23zHpX/i9h8q8tOKYdRCjXR75O/GalN7PuwodCoLZK1zx8J4rv36HIKB5ul+y7oF
1s9zYTqIO/8mUHALp1V3U2un1JV2YFG2Gyh9/RV3kjeR3oFsKegoeH7YOe5+cpy4IHJfWrl5/RK8
ZtZSp1eP8wQvHUIe8HY2Dg5i0oYJyb9Mol2kGt6cjDpVcknHqnhHr4YaDG+h790GaU/wb2TvCSs8
QSFMYALuzgVj0Woqs5qbDkBOy5P7V4zDnnWzIK/jrzeHNDsAdYA6GQj7pt+cQjrpbRBrUtuqujpf
DhQ7Q3rkGzGHfitK8gcLyQHpUP1RCZMGJA+QFEm9BVyB5Gx7D6wpkJMcjaefHw1uneq4rR0dL8aW
QbDPbheIHzRrXjKLs58wmNsfulrVTFdQidm7zYI+kdZwuTdjDH0A2st5BVoSInL+27VNT8DXtUqe
Y4ZokDe42U+M0s6g34Pp4DMYFUqoI8DVU5JETXBguIeJ2DpZxb4Rwr/N8hx2Jxhvua02721Kd0WA
lO2icG85IYwta74v5zLZyAHY1VqJMETDgVcMpfpvSipDCGQZXcRPUn+LGOqDtt1Cz3im+Pmce2RK
Tro8J6XEuKMb7uXAPjW5pidWKiJSyeOQBwIRQux8KuaSA68ABEBFym8lS/XLrKD7KZTrCTm5Asj5
16aU9nTWOjNolk8J+yKom+ki/lbm+F6NvYuyeWY1M38o7FU6tQTTFl2NXpt4Ej3ogxXDZKGaxyqd
WGVi4vW8DNkZv4xMPjoUgUGWe4af8nTx0w8pJCGTcHAFGxmy1PDH1jpIzJrMMUQeB7tKXVBrQo9Y
jQ/0nrrRiZO2foMS9PG31nMe3XZeZrFZXFwHO11Z2Cp3df2HrYDTy0g7uSWqPwtipoubBWAcoUln
woAHLTLiYYunofCU0ytzI2OPxZUly/fUA4VE+DSPnQieH2tpNPC5xjQYZ8lztf3XXsVNczxW4aNI
IHWWDoKIcSKQPCC4cPoUwMwp2piQ4nhjenMc3M2G9gTzPyfvXAJ2giA9kBBnejYF8HvNVb/ynLpN
YKQfaZHAbXlp4G81LL2rNmoPIGZ0JShQFIxuWvm4Y5+h9addcCzTGTDgaCX0jgTFh5PZmhAV3+yZ
V7Z2v7wXcbvnQZv08V3CYOkiFCzxrOXUHV6Z3+cuV4CkO/pX5n/ufkzPq8zwvswn2fz1Yy75773G
3ap+//y593g9PjWZSrR/rhqp7J2I8tGNtW8/72SFMZYfehvqJH/YJ0tDF8mB6mMfKQKkjPFYUTE0
dL9Oldqb3cvQAJQQIKinC8qCBKcZHUC9BcEyV57ORTbZOgAaQh+EfECNKc7T23vt1cNAbZp0Rb+N
S4JNGtnUJpyajR8zgEQU8wftxtyi7Nf/IkPPA+MAOlrG0JCpexHQY+LmcvcJXJaEUGI19+WtqLDB
2wgb6LGeoGL1FtMrctvUcJun329GIc7OfySqXhMOu+F3q1S94rmIxdLZaLoW1a5pBt3Fcbjq03wS
QLj/1yc/1QXpRRw5oTXCykx/abgreaN63W+eZeGmUYmr62rPzgPzUhQ424CHtOux+cc85gNSsNWE
M3y7aEIbBEPumWDYiOSYamis5fyBt9t9YeHLlVhcI64g4k2MF+sTouU1XQhpAy1KWb4uZa62NoDZ
TgG1CJZkuFhD+xgZZAv0TVnV+1aFO+gziCK946t+Lk0+I9/fwAbTio/i+idUaGK8/fHa2td4E/19
daQ3RhrqDdMLnDHcKTFyCUdhpLJVqKOpmKzUo5j0+RdGqOdPll+kKxZLC/aT4tV8oM0L9zR8ELXE
WGHFMjcs6HFmBV/B5u7DKSn32o7LiWgmjwZK0a4OO1LwYZjFg1eGM13dXVCK0A8nNQSpqdxF3G6d
K9QLbmnvSir3vaYuHopx9uwTgAKlaNpZhzgEYDOrBpF42jP41uuD5Eg6F39ipaCtE/fYsCJmZ3h3
2FC4v3YRL7q5IZPu9iVpqr1YrLwBl4CJjEWkOt94R5Ne2ndWbxM85R3jvf3rA7BUAM7fuUL0qXbX
8Npq9KjG8VCTcciOxDYX/nD8xR0W6mleIWAqkLAPH+BjgMyoUG3b9McNhlAQo/iu1ELRR8G6tARh
OVYeCGVxF8nhcImvhU5jwWLnszOipU3pyaHd6EVFMTKPS6q1eh0YrSIPg1jFTs4dkCsmQcxu4l/d
gOEcrpqCM5d8AlnKjdhS9wUpX3b07a4n1KDLTInO3BKyY6XVFIQKD34TAmjCq0wyT66rs8AAoNpM
rSLAs0o7S5JxJH9Q1G5NnvKfJ4b7ymSl5kW1oJP7qsCGwKnYlHSN2EpTBXhWqjm/lC2ZIoI+NzCb
75O9PJuYLRTX9MvbW7nDAHYM04CaO84YE90IUQkXfGp+YEYA+9g/t379MZc29115VBPTKS5GYRY2
C78MvlfCEoLbGb1F30PKoaWS9vYu5G5CiH/f+Jyrqk+mqjGipxPRgHYgzMhDfK5iikmtrTntbwqx
XOdI8QsfHjU0LEKPRhIBv5xsqMyzg4IrjHQ+vjcvhDDgpUOAq4TO6wfhcN+PRhrGRSh1tufg+wGj
QYWvDMtekgDTskZulCh0d3tOrIH8w+JWI6hXj6epMavkYfHNR8Agx9vCvr4i1yUOw45CN6mQdB1b
wouvbIM60fk3STd9j2tuivlVs83j8SYwe+yW914WZkpcx0fgdwICL5dZ8U8aLW3h8P+yAqAaCMmr
Kes6ljYgK6pCqYRvHvMVCIbjPXWSu8lw1iaqHGJ2vsWGhe2F+4w0ZtFHUF9XhMrj/LRVuKhB8e+p
ktZhrbdGDUWEDTqUP9VMQrp/hjBQKLAQK6VJ6k2i0dh72hoJfZhRkxmzXnqSS1A91+M5/vUyNSvo
7vkhM1+1+fQjU8oKdEowST2makSGbIOHA9cteePGMr40CfEfF6QDzFtCU6VMt2QpQdLqHLRu+OaR
r6e6jcDgruzRPRN+rr8eunZmYsJfT5eWPt2sfLvFLGL2dBekmDbjGcGql7TcyPH0EoHmSL89JjG+
vjK1fTjw9bFLs17NBo8fgbKqaIcTKfTcLZ5T0kBRKqomRphrI7hD/0JL1bDIpY93ZkiEt32yRaqy
1MBV8GOdAPdpy1JMMb5nphMbG8AqK+nTTdoHO2L7MmDj6ZW0guFwgKpHMbL+Gi5nfzkWh33/4a/0
s5kkFpaoL1i5+I71EC6SAy7YDnmkbf1Pr0zOYsKRawg1XXoFy+mGcvZCL+Dn3gs6lKmAHWQ2geqZ
0ofp7tqomxy4O/xJ05QAURZGQWvQP6IhNgaxOqtEA+TQXNBjCDNefkVONYVT5GDC2qsfJF5Xtf9P
8LQb0hktmYloaX4WHDXMa37WEGwylTm6vKZqGZJ0zuqIhpseykJS7p/uTvtE3wnLCNTap7tmp/Y2
rS1jXJOHs7MeUpBOIoT1yN1tgomQkNnP9rgrSVWNnqH3mXzy0EXrCv3z4NVJy2MFTEL4bmc9Xxce
lb8xZBWpLvrZfQd4HUabJw0ZPUhjixZbK6NNzTesoiviPf9+/U+wH7K0/giof++Nup+pogmDcEF+
dxQfJvfutjJOBiebyIskP+1RAcF5cyc4R6/AJpFUJdkwG3B7o8rL/2giWp4n+KdfSK0ge/6eRkh6
x7pkCX2A+zIs3A183BPkF1afhK/+naNaLNhxY30+OwbiA6v5TMg9n6psVW68KEjsxDvmw67WjXvV
oZf2yM9lZzbjfI0V78gyFRtzM6Z1/GPkNbdpTxhkU9JVatiMrSTCPoR+63XW3wljCZJivGw9KqYr
5MQr+6uSpxA354odX7bUhID/rGeOiWgye4r1AhVxT0TyXYDaEmBVtlumhdKuvjFESjG+X26nrNS+
mNp+G63EQWzT4ALkHlnN3AtJqXaHXQ72vdr4PrFiscoQBivqe4N5kgUJzQxmaA/udaGr5EkMgLi1
0xus1u24x695N5rSsJmmQ9X2YHGXG0DaXsRWYSJoV1S817fLTDmgVY6GYRZFKxeq2hHyz30fg9w0
5+bbwlIYnlIkf85pcXz+yJAWtC1zFLNN1lSmmKli/dXBSqo/kWDlPZSNnF+XIxlOSvlID5wbfmmT
wqIoF1fFN+DZPsvt0Uj577/n7O5VqT5TEt5BrxpYrT377Q4pD/lIfv+7EJyjEwgVkW0ozlmXMqyn
ibZaStNTPs7k1ypJlcXvXJFInAK0IZwlTHxQh67QdrzIp1QWUKFlYPAeOMRWedNHHGKk1KW+4Llu
YRdKumgx+k3D767kLkBXjMt0zxB/GSXMTSm84/bC76HzdkGmt+cn6eh7SZ5l2Tad0FCh4apjgb7u
6wNEj2gPHKq3buWr5VfrBJF84JMKcw1rdlWUOGSCeqR7nJCx6NP/BjYYPjTa9a0fWFVQ2SOq0nJC
I54GzIAs0asIll9Ow06CWww2MtrXU5bKdGxjTNGQXCwPjUYRavCsgGTO7Esty8GzmTh5Uwo1LBNu
PGfD1jhfKUtXytYfCtdpJz5EirynFwSaj55jzb3NUFT+k7/ggn2eNK04ZA/b4FE37MBvsKaUlKRE
m/Ikpx4OnCxVBWmzINj5eaHHS+RB0YOIKq37bYfSyB6pQSJkAqNXEa/5um+MaKmKRVl2EQYbPCRY
fF8qcLKDmonHX2pKoz7cyLgMBLRXRNrwYDOttFkhCK0nCwYipqVzqpUKm5S28QVoSu0zqjXtBPmO
cVx0U4U/J6jry0n77ZS+BbSeJnVH1Kqnpm+patBoc3nKvXkU4kI7EaRZo2wPyS8bRZtIRAdmZpfD
XJC5l7MLtXjJsGEfrLg99Vinr+/sSFSg4398BNT55rZbjfzcShwNYnVngWrxaU5+Ghm88QrMMDlw
15+DoohgUQF6kg064lpqXeHD2jJcnMVykT+dGJUA3rFc37UBA1nkVh1yWR0dIlOYV0HIwwh3R6iK
BP1/2LraSEMTv25FD1gT+tl6uG2hzZqvbGKfkvaf8G64WYhumD7Bv27NBJJW4/ed6NguiUYhBAVo
4MBtv1WV/WoaC/g+G9HzGLRt7+5IUERVtAEyjfTO5HV1lW6WPAUkbgI19oLsUbz1SGHiY37ILbid
lmYbuvixrg5rCZFF78CPnRGE9C5TSrq3ai7u9PyEOrFZ9pcMldUZmx4mfIRmDCiqyHXNTSUpRtxa
QFcE9/EHe/Z8mGFzV5bJm6jZGK0tW3dRKSfKY94v7S9V1qDrushQ4F9SUQhHMxXLMsFjIojyZA5J
4SsrAHAn8eWG4mNK5n295Rd4z4nz5rNqG07JfcIdz7rNXh931UaNCDs30z3cyoEKR7rJAg6kJ0xi
6dTAVcoLn5EXgs6QmwAlbdq31YYWuRbz8GIevwtJl9DvxpIYeaW4e3rkG9zdwjS3YPYT/oWygc89
Hui7u3Q4EXEKSjqdP37dlXleslzfXiYNQ+AX8R+s7X1fN4igH8WF4Kz1GV6Rm/w1RZZsSZ8Gw1M7
FuzGNANb6KQhMTdnRCdfBvAJAy3GvdNGKm1z2qANvy6Bv5sLELz3c5itJqzhbhGw7wbECKldY7Xa
Vvtcjuqciw2SkwI1cQ6HW1mtAGDgae8ZTNJv3p/NmGm4LY2kiGBafph81wJjLyL62/rOq2nQuPkj
fbG3yCtuKfGfQ+u3iCHWfUZWq1wLmznia6rrNJACGwadIS90MNFkj8vWP/vn6oDbWLaegkrH7SZ0
ciCWfpWCPqDwUnvGM7zO1ostmC3/MBQIvqF3MAKMPTtH2MjoMgUtZ/Hvc6BjOvIx+RtC4Y4Gmbly
8zAe1OW83uPumLVXVQ5AOBaimRyClwrunEVfcPWWS3ApygxYc2CLGNq7fL6FYBrhWsR5x4dr/vlV
B/FSBIWlrgssy5DyZNTAcPV4SRLIITgcu3/32PENIerXfd268xAYitRIDCpQiF4kVtl1kWSY9CbQ
HTH4NLgUfsSkHWkH2PDEp/1z+j64iVA9ynLLeP4Cipendnw6wb0uafXDqXTwb3L/Cuine2bZ6lKi
iekT1zVAVqHIfuzq01XgIdVP0aZYjIkK92xBVGUiMcFY9NpequNyQ3rjcTmWfXNxNjHZ93zrdMUJ
sJUnN/FUKAMLx6W+Z9rAFv6bbdq6k5HC79b2cmQEPzDvvrtu08bKgyhxpmp6NK3t6RW5I9CfmBws
/xXtMWfJ1RBETMkiIhGxB0rZWHEJdFz9GJtEXWoM3hvnJ+lAYDNai6Zbt5FVQHQ+dX2shlijgt7y
EfiNw5aK4x2K2g7JkrbitnQ/ftpByOPvDFORb+Y87IP6HDtzB0eQ6fEe6BTM58She+QD8ebIQk+8
tMP4EcjvvgCCUqVOCEL6M9c9G1GIF+/eeyBZ+XMyZwUEdn4ggZ1aY2MZWAr/qa/LMxYjH8vit3Iz
jFk9Me1LIv9LWXd1J0lihNUL2qAPagr5F+mvhId2KZs5bJrSo3FYwnUa3fxmN6IPiR/RAxZV8z0Y
c3rtQgIIH467qd0pd7gUwUA9+yJilQDbny0FQAip1QLU4kMHXrSpM8m9r9AjRJ6iV/GggPaeWPpi
8MEgogzyhznPmua0KikvNWjWwujZ1iBjQKCmjt4ADdfTYhAWKse4oKl9U1JiHSmpcGom5i0AbWCw
qx0Dyi5bIsAFAxIr6LiclipxFiL7Gm4BJ5luzAU7/ioBzwGTDzPEacpQAbFQCM0bsi9owyChD2bU
Kk4+tCCcWSHM7FoeLOrj52G7Uf0Ft8owD04euda8EIEGLyTkuOcZFkF1DHbXFE00HUeYbb/2RLRV
lAtiuS0OTiY8GuSQ3FOQMuWbKMPMCdQs2IeNiqPxf0WQEI2vHSmS96Qniu4w+jGmVLUGHZjQIYPu
fIvXg07RyudENVwuM6anuye/kvCTyjhJhkgReWJYc6ksmtRgx3toOCLiPVlEBjQRR1USQqSflbIt
Q6NghVrbk32fq8WBkRQsSv+MEzrYtxlPuejOS2a4RxinBBBrEZwKK+C0vNC3lrTWh7QzDuaWejE0
v0r2MXk56rId/Wd580CIYclnFupAKnXHk692/dGWAcp1TzuehQM+hyRTsvxUv3z+Bgz/RZs7KBFU
LvRKFxRJ+x4KyFwKT8W11BgiG9tu/HmzOYQcy6Y28vG//iBk7vkI5OyQNx2f24H2RJ48q08EzTci
DbChatVoExVvx6mz0LG97FL4pdYjI5lpk2D3pt684/OV2BhQnhh9HwUZ3eOhFEHjfLtbAHWSetyu
u/qFA2ug8tx3Ks9Y3M8yDY/mfNmCHss9uo7uLqsH389oPyPNUuzM+GaI33PBnAGfAJSmLMF45eXL
qfPMUT1lPdTf4+i4qyOKAaQ6/oNRFnQ558alQQ2bUFyKFxS6FY0awmVJ0O1ih/dvANXTRDoabrcU
ddu7raHa88boYN3gi+fw0jlSID00gYGz4wwaq6vA3F+61ptIaVNDeXRc7Kt6SEGepCQ0sH9+PNy6
qveT8rbJYN1LHUtPDCRiqfmY14VC3udqB5inXfILdYJ4RkckfgX5EB8Cgy8FLMLCb/XsVDT8tYA7
TW5VAkVmR2gHo+r45+LqC1dsYD8Dp8/COURp4mHd0z7DFYOvzTCWYX6RBpzLkT2Tlu5AGz7WmjRw
pneYBCeUWglNV2sC6QpwCBZ4sMPPtt/uRAlld7ArgmEHkl/VMS4RbW3zdmy5qmwEFQnLMJBeiosb
KjKJY4tTtQgZA6EAzGoJEu/7wujPTk0joNRWQAt8aqVZ8ZaQuTIeu39B6ZAUJwKyDJFKQVaxZoQU
RsHxUVpyysT2czeQE8ABjgx0Drb65xYV4Uo87wJ++B2utDyrnDfrzU6iZDnzolxCmO5fZU8dNmh4
6FtU37150sfkFkAfhc6nPYT7z7Hnn9ZN0Ot3fZRT341sj3yIj1Z7X/+Y1s0ASVmotXkaOgrvKKzi
9T6Pj/j56RaUYYib12j5t8+D3HYEh7P0681pipukcEdLS39MiAoQJ7waAGy8s5e+kfvdM1218xAA
jNS0YwQAJCBVeOtGcyvO8L1mzGtMDoyvrbdhUhpm1NuoqJ1PbQuz0tnH8gZRDnkJwYfb9LO/Aw9z
xUjoWgsbZKN/Vr0fTAPX+VCU2DUZsVH2N006XjshqXpR2bP8c2C3ABHxFvEUNtasA2k5/lPlI9Or
kIz7cNzg6NsohfdWRpJoX6gBjhm1NjOFdWrf5IjjEJDcxWBmF5AAM8tibIgYij3Q6KS04lbHXk4h
Uk3xJm701shFwSJkFdvLS0fJ7MGAAfUku94z06kROU6AcUBMx/xVM7QfcwuoycwWLN2S4X/44vdI
4t9/ojHDoRlasO7lkc8oQ/B2Yhvq3z0RBb7nvfUrBOgzisUFSS50v3JL/LcCvYKoMZV48te6zZ7G
oBoyjzxfehZkwvEdqRG614sjz5RziKESv/BzjwQJkJ/abA9U68lqtNCqgadp6P72VQXhafqF7/0M
/T4BEnZyglv6SL9DiBhmOVdT9Im3g4TXYOAAPWwu4GHveI3gSC1nGssiOoeSvW6hvrWFiybJ/9pS
jKLqqbwh6ixolKkmvbrNzYCmrriT7d6SDU3jSVxCPkgYpfsimgQ0ay0WB54cmB2iN7LcNZx6RnwG
/thNguQsvJxyJ++c2LsbVQxSKxjBQzUmQ1K13YfG9f+yA9xXY4rUCNJ8k4zHLLYrRcb84irItVcc
lV2yR/zdD8Fp8IAHWwvJ8LAyWosIQ3CnFaUEObfsGTNCKA6l3rw0LH2LSpOgv4WjCQSmGGg9PaUK
LTAELRQ1XVXrb5auREoMwrWHDWLUMUyOiuuQ3CY6ZQluv4FM/1izHj38Qxl8hPS/fqbbYY2kY+Vy
phbe1NndQrpjHa0WkFZULkI0Pnqxy1YXNr4vBPn/d326yJBTJKANJzpNOhgNz6KcuydmGJgsocIh
xKlbkoUHBVDpdmxtyuzOpBjExBnsZZOOL72I6iUq/I6lMBNlXe82UR3HsVvIEx355IYlEaEgOSWa
vZkkik2+1WwDr5pORD1LS6AKQSdX+gT0AGsu4i5eBUuKzyaauOizY8rwJBLnpcmbaeMxLKcRvAyE
qV6tak1PKhZ9zapa4hREPZ/iEuxxk3z9JmZ41bAqPbAKERGpFYdS7nZc0eG0pHXJbcHjstvegF1P
BvyEo34X7cLLV51I4bzNlpxJEnpgu2K8IpG+HGfrgOW6AvBCuZKm1MK3Vs4WRD2JFbvYKEv8vg9F
pG1RwT8BgPhI4V9ZV1rCWxsXYunoW7ULsNE3jXTmHQlNLIV8g9U42O1etnusE201wfzUPW0QHyvs
o0E6C57dHxSwTsTTn0lTlcUWf60N36Gl9YSq5N5S11Efya4Cy7LH19cuRMwysW3gwTK0Nw8rKHib
IUL6wvRyiccmAe6O1D6GF2B6KSWWX9YgEtfpHup7H0eU8zaW9b2b6jeGoN+EPvvJQxpCeXbA+EgG
2wsv18gAXKZZ8KpijWUj4C1kI1cahbTvteVOGjzoCGBjLYolwpkLTVGGneXRp0KWakn3WODzUoN1
KfP1zsQnr+x5mnJZyX/BQ9cpq1pjaD3siayBq0zHBNKgXVfi7Osd9hcqbenM5t2FXM8EyZHA/GHP
Zp5nuAiVlNwat4wenqzi1imI5YtrwFEJdB5ei6Uv99DSgbfs/IFX/FsZWqbpp1djXVO9ueDCo6yN
VvmVgijF4LNAtJbrkraUYcTc5GjhHwI0MyXB9L3YIgXRBYVqbqZxEnrTTSibFrjHJQBjrBgFEkbZ
ut/ktdlZCuu3X6a9BIUyXDvceRctOzYTbgzZ+q6cu6tqjby/Ku1jB8bfJWx7E31fZGMrOwb3vlG8
y+7/OBxeEpEcUnZNNn4STMIsgUNNEKN3exXwszYKZtOGp0aJJr6r3LYPZNzdzSk+oJQxS25U7RuY
jsotRQZKMdWAkJsW6jGDe+fNxTcetolm1xRWdzG7nwMOdM4m5L5MEXi+Tm5PMhSRJmnvrBIhGLTt
AM4rwVqCo6ibkzbWWtV8KJ8bWCP1T4dcucYebXSHRoC9pXjnD4BHty0djDyHTqeLy4HpMmKrjzJq
+hfS3l1aGWpkz9Bf3bGVWGtBYVjo8fjwUoLycjzR7jcfZmw6K+uZkpt7ko1PjTCux1LJ2bMbI6U6
5vrsL9Mejd2wze5KvCx+HeOPjxTDzc3PsbGFL4CvarKLqXKeKDZ00Pn1sTICWxR3GoYPdkVHnf2T
WHU9YcPxTPw4luznvgmcPhGCt+d+0SoGdoUjOkUXLHSuJuAbqbX9VuHk+gKQsEOKWDNyRHPYGc5j
MkgQAkSDLT6eYWObzAi//8fDLnLgLj0sm7r+mshQCNuMGAH2jVRdIs7G9Lz+e7xfWH0UWRN/Wyh4
4TIzfYtvGKbqU1+DFg0JK1pEPbUo97SqpnKuUt9hF6jzSxZ0NbteWfql9p/7S3l/+QNAidfxPhsY
qF47saGeNLmMBu9Kc1O515a3mqnPRAzeTRJ13AKRP/b300kBrkrCPOpnGpR7cU5RbNj6uu2hVhWv
YE3orzg2pSD7ZB0n7K2cJROkKkppZN1ndN3GTsvjBaPvADdgG+C6Dh8+dn4I3ix0hDPIVXDJ2eR0
Si/3pxFXkaE3O4EOZ34m4hrT91LJthv544syE1Utk96GXBy/ipawXCrUB2pu9vDRdhIEjlYgFhZe
fI8U6IcOjp0Uv/Gw4iN+eiqCfxTEoVOkjuSxAyOhYFn4mOzEfp2nqrdqr5PNZdbT/RFEQ0KWsael
7ZQrLBBrQvPtj5VXfJ3Kbj1xrPmymEr02mOYwdWkfW/01k8/ovIizqH1XtT/sBN1iUNizBvNo+jd
QvsIoqSpMSejQV2bDO7QKYvTKApFM4T0hultcBhJ/euOOaweOGxpndYCMfn3K27sz5/bOSplVape
NmeO0xGLs/AahuarkWiGFHCIZqXlDGTSroijbUaG3gs5JJfPcgQkQKZXnOt31364UUzHyVJKaEUk
pcpGEUBTwq7dw1NkuW5MMgN//uEf6BkbVT2lZ1A4X7QHLZC+YjEPKnla+ObM5yd5Z/TVuDrfC+Ie
KPnp9XOEnA+9awu0cceOIOe9CgQzCxEI4EWkojIWmOViB8ieijV/3x7WqQb3f9GYasKtMH6QMh9t
rOkFezYfO3DgKd+WWiOUphW7RcLKB0MNnLqbU0DYwqCPpl7dgC44BmuTPn4aLhn4uGUAOF+vFc3g
6zUnvC4/Up8GEjtHXnhv3ZmOzD41dAKmUK6S22S8K7et2IcOrd1jygjrrgHDZWpYFoty5LawTBVT
NryjWYC0+Zc1DnxTZycZ1U9RCTc2XjTztFB5/LKx/9HLMNrlM8at5CcaYCLrzdXp9F4+/S6f0bwS
uX/EY1PNWn7VEWHZ2Vi7//yN58ado1VYkWGXYLO6pOi2HeDkBmUs7CoMbCeWlKIbrWCc7xePUM4U
ewyyZIggMYnIRCm6o1IiNBMWFnjlr7HkLV2i3GFsUDPKGze9ctuF9NYeAOf7Wb3Y3LFJEfiDw+dY
DuN3n9lct3L+pXnrsfdixrxst2LYmw+C/MzDQN42JPdxijxeH68XJn19gyiMmtOblTQFXPFnXWp8
owlk1DZaRjDDVpxV/n4pDGBD9ugJ+FSQLJ9MLvWkznKmejO7r+LnREvHHTn3QCcwof2yrOydSAvd
4ypjPoKBsGV7GeeDReUQtrVFSY20RPKiLpeS3znNfTxPJmOpO4MAnYcsCUsOVdmExDUUKyH0H4eZ
fBJwlK4koMCZ3pwW5nuI+6StnE3HBHe3UxnanuQAKKaN12rqDF6RHedu0LTntAmgElytnvGqmjNQ
QzZ3XOpCMFzxzEEhUP82gUUvjdaze/E82RMBbipl2X/g3A3hHe9MhFe/9/IRVFUUv8Y+w+LsJyQd
sVCgu6oSTtmp9aB86cfpysjdl3RY9QgNPkUuVCPxGZ6Jhm2ZlOqWcLzRg5CP82EqKVaRfxxCr/yu
XkcILjTIv6secE/emPYukM4vVkJW21bkbk6eyxmUycRUpzPGJEcDW8ahaPknxGwTYMcw7l5eqwV2
Xus86gFXVDnVJr0ELfY3BwB5Tq5XXPxx69u4E5Sj3Aodc/nIuTihpxi8EkYw7+PKSuZ1UoQh7Q2O
VqKOAUi6u9uLe3sGOC4sGUE/4TjerGRtTy5JsHR3NoEPsERLHlSrWaR+NR7YwkczMNdvD1n6+p4f
sjE7njwKFGF/mBsBOrHFxJAigQl/VnOOMfwDitCUjc3FiBZJJV34ceOkO0dYxtY4B0x2z/1/NFgn
TPfGtMJr9/xWb8Yvf21pes99TyLA/fAg7A5z7oT6RRx0n1an/UkrnMMBYHpUutDWGuoD/GbxwvFP
AZbbpIltaCnlp1gfcHhfE0/2KOUESJgex4oG/4lDtmFUR72vymSaR+ibZXwooPMqRyPRtaBUGXCQ
dSOa2eySkYDJFS5+usQA0KW19pr0FKgtaBUHpkwRBKZn00P8U3pu18SKUpbYBvHXm3FQWvq7/LND
daH6V24g10kyCnBdXSGCgq0rMGhqVMo09E/0+Q632IUeLxl+uRi5GYi2RSRKxb60Erq9UUJD2/KT
Rf1fQkVSqHJZ/uc/8rKElnKuaFDqhKx6Zli1hrOaIDjtFvznruH7Zd4xSSAdU2Dkik5ClZ3DH/UM
SeR6q6+NHY8NB2Da1k5bOgh/YP0DA2klp6dK/tSURNX9342gQQfmnynYC9+1CaLIC61k2u/PAhpf
lS1NaG8+NgLOLuNtQnXkaJ3y8oQc+5i0sukHNbcE6/glDZ3nlEbCMzdJSIQj3pP2+DdmKzxOqnNm
TAD7xwuhzfJr/C82CB/c20GVp/C7z39BMhRcMme/ed9xZYGPOzBEp6PpeW5LylgPTogUNyy75UDl
Xg1yyFSrq3rhsSU46xlWlqWcFryUW6MeP989NU89jaez2gBjh8jRoUVMl24X4QzbRpfTTug4DOeX
6DpEMxmqFCxiYP2m7XtXy2w6/p9ta+Ncndcb+lBNZjMB7JdCzcBlbBnJ6Hlh+t9/rib9Clt3FEWn
tz3wH1AC0AvjXLzUHfTT0/3fuklk4LBLuRcgOePbvrMFDteSUaEpqeyX9pgjCxTIlqUQXerfR+2S
9nJVg5jaKMhVUolMSKVjw1c4lqMIFRt97+lIOFM1YJXVTCJn8UMCLNj4GHgqP+PoJ6aJRylbFJAZ
rsr9xEjhgUFnUbctZQEsP2YiQVGAnL5H/dU1K7DoNg107iQs9I74AWckfwR9OyhpmRpEBvwpDuKx
PSwOH5a8xttbtR4dZkEgLbVsEs749zjQG1UPldVAjku6H4HYH+GMc5UeDl/vGvdZTdgFnUMEQOig
XMx/N1m/3J3LBE4R+1s1qC4Turl9Gz+pSPPGdtKCvTC8t6wBbnUKvGEbPpgH0HrTLBaXzQ2Zj8lL
J+9ToFMnkaoSV4K23xVTC0/LbY1U4gyVFpDUnEsWmUILZT1Lzf408sJwoHJYI70MIUA9Mst1TGY7
v43JUWCuxsE4n1LeUBGqOpiRQcYnoLREdQE1Vcoqn3OrS5L42Zj/1jaLvmaKahaYUz/Hlx0h1ORd
meaqmo0VH4n32qnW5jSLGwtG1/u1dowulDScO1jD/d1QDCYD678hMtaH+rexxpTy2lOC0J0F1gYC
K65zae5lDfnr5DDhSQzxMOTCKjI251HC6UYw5Jw6Q6dXvn7THYZkGyRK6fMGpmi5I4BHVQg+KVH/
60BOylEGzh8+Ee6FnK3iKL2saoQbSwrSDCKdlZk8840IJDq9zUvt27OAhOMpvMQeOX1lgmA2C3IT
M4zzLsML9envuVkH7w8swAf/bn1OoV2aNBv5XENU1VaWf608LJ/b4hcsaH1LV7EyDnCvKjD4fJtr
TVFeLU+gRA2edBm60o3mTSR/gTusH9jxQ0QbYe7uH0hds4JXoRCL3IgpW3WqxnvR3lWTYgUdAFqP
TNCG9N7cdX/k6wD9zQ2vEiNhGA2Ter9y5WdV4qcISoWTBbROiJjy462tjG1+nB9JIpFxJaqSqwtg
CpcqCh5QsWnBkNIObGcLCWbjfJHHCvdi9U68FUsGXN28MZvcs3FNq77eLgR2pSBaECYpMt2hj6MV
pHcPGRxdrJ4ZU1IO5AKdL5oXDoYHqZmUbiuXQuCFUtpPap11/JFB/0CSnIJJQQ8QxK/UzQ53qVXC
m91gbwoTlJg2SZIpyh7QvCYk7myXn5hsNXFgygUGJ86vVQO8tu8Z3go1RFgcXjaVKOooXU1UqNeZ
+PEKQSje0yu36W1VZzDdR/DtjdL3OtoM/0v4VpRvsKocSwnUZePOdCkI2ymP0HUy+eGZJZl5G7EP
7Pa4YZbUQc2NO4blr7SExndtw2jh6Y3NMpVadHbEmDPlllEuOHq7i65XMRI9U9T5SdUpCx3euN1u
WJXJerTIh38BpECODgQJxMGFyeqSC0XxX445zlyL5asUirfUpHBzcguVTV3wH+eFJ1ALM0jfbLAh
kCGw6WETSTk563+ep1vL0+EUAHmNFFvRIRhsaYiR2xr3idhf8GqjcxkIM9/f4zTMgJzw2cysm4Z3
08lMeTOr7CcqrwlQsonKFb2N/UFA32a1pbX6cT2r4YnlQ+e3nLohwMZa27ouX1/pHCB+0neol56k
wVVFWutdaM+xPiGI7dIyrWZgZcYrQcvdsfeNT2pSuqaUWJdZq5OwDluE5WKO3jrgHTjVYa86hh6m
NEexzleeVK1wkyrunquFPQ8SX2qy6+64CMyJ/GteHxJsm9fHBHlCaDj+16Gqc3HEi2uIzYI/dRwU
VxtbD6+tQoxrpZg/ax8ZGJUAIhUmfDfeCcl1beyShdG5lBLWjcxy+kBd5tCqKfU1P3aHqso+UFgD
A5Jsw7CcPAMRDaPKnTybfItGVAxgSbVOxR0CmxyUukbI+fht2ZT5IrtSb01cRnDb6shln6vuomuR
N6SS3UXBu1kf9tDsS7Xl13rb5aTY0NOIIIL1YJpjWYnCsLz88BhJP6GkhOLX5xtw+ojoLAtwSS32
VHweCKFheisTYEBIxX0XNsOxqCkTh2Ot0ISPZZ7GFa34YS6MJQQEJ67gsWuTy0B5tTE4QkSibPAE
rk2b0NZNjFcBFgSYqnwBBMS2eKriRIYQwg0WiJs2OrU6dNeCGkjU7OfDSx8SZOl/720+B4SbTygO
DqCqom77vG+T4fiB1Zh0txCM1hVH+bwy8lDlbht/aaLztDfzePAB09iE4jBlRsdBOQnGd3CyWvfR
RAWADJPtGiqX9yFw1Vp294AFYfj/yeIzAfDCMsGkSXOlr1z4EkSPKMSqOrlJGVw8wgbTF9FXZB2B
TY8PBiBabWAWPfwJB11WM8gjTsBuSqagjyMIc4wo8zFJVljBL5kyTYbSV2du3zt0ep4ZypUrrFo7
0duxwcYVe8Ov4WhkoiedQ4veH0ZfSuSXY33tFAdc51UirsN9f4r8esYg7kutZSgjdNdXxOHDPfSr
gHaoiOT5VrxSPJ2lWSPJ1o5EMpO+6xPJAREdTqRJV9WdCDjOL8Ilny8BWGarmXZnexlCpc+ZyG0h
14fVtTpKe7zi0XJmPTwjYB36sTBZPcIYrA5ymmsKvAKKwAl1bGB4+69UMVHqAKHECo5OzIBqPp/0
CLeOC5CK5kPi3KvEqat/pRO0bKgGkNmEFV0USREagPAHcCRWKn+XpB7tn8MAC4GQ3FxHtw2+6JOm
iPo96+9wO9kp0JhlHEGyVVO+2l0988L+b/re+jIQ6oFxNhB1KY2geOyz/Rbf7H4eo9S41ypsaBXQ
1xOS8HhTopjApHQIL+nQ3pJJEqj+eH2M4DcoGnAgi1Xc+2caJphPB/Tu+coSo/bLa031C71a3XQs
/YKDkb53JJBTzyiQUoeinOGjKNqSi+b7JiK4h68ncGsfCf6y/ax1SH9iC397+1NqBWaX2x9lNAWX
m9X0iWXvCGJJrfJtE0aRddRIkX30UuTYW70y9ul55Q/6/NeQHiGlHWztvv8zvLQbteMPQgQ/yfAh
8kVZF3B4zti+DM7+wnNMoGeMfqXHxltQ7x4hdjcmdFKsJ/2dBU01PQGI8nacBzeRdZYMnrTf96Nz
h81eUjAPb8qHVYjObzeEqRJXmM+2nG0JjtdcdgrhrejSbiCTRhCri9x3Yb8O6SOPEJDjIVdvnZ5U
k3kTjOtPQCUPoVT//sbNayGNSnjktjz0fseQHE0LEMPGj/HfC13ejiX70lu3bsS/JCQF+feo2t5W
vjNvDA6Q9a6X1iUi268GKYLckZ7zBHClZ8uAeWQq/MkPideFed3r1RnpGw8dMDA9SBBxNA2hnIn3
+JOc+nrajDdqLVh6PdBAvaM7KgmCDngNsoA9a0pdV1Ligs7DvzaBJo2HuHPJNcBA1JML5xnRL2sZ
qCNtCipMsKCkNkUVAlrZxmIS+oY07jdcsoco7PeMcSven99mfWYHr7B0XxkWjoREkzIncTSftQlG
Wz2YlKEQ5r+laCjFgvFKGZ1+v6024xWVz65uYM0TaXxr0BsUnh6MHkGA91gbrmsQTitItOiV23sy
xjaz04ipi6OD1keOol5CjDDZ82LJV6XjVQvIMSLM2s4NDXyXJnL0PmOtSr7vmTlqJiFllLAlO9K5
T/0daQ9lJOxxthJpEGxuTHaONatahRDXjH1o+vOOwStgXplBbdvP4bxiZG384c9JlXx0q+qa0882
IEpXy+2dREuk9VLfCcHj0H4mi/i0vFWysAxbBxxwGeXjt++NQuE8Xb8SAJDdOdtzvw40bqK6lu6t
RgJfC1Ot63IP6LQKwOmenMooxf5+ICCa93pDRdHiW9AmE55rD8Uz09HSOm5I1F6OEQLz3+WGCvZp
lIyr+7iHoOqET6lYy19gC8jdlg2G+u3McnkornvE53lJlwm5Rd94waMB/zbBlQiJsQFaz6f7LkDK
2qsI6uQWnEWVWzbX3YQ+z2xMV4hXBnEXACm8NWMShobsYPEuEfxHKI4BS8Z9/a0DhBlAQTbC2ES7
uDjIh71Rha99OFkjuvSI15FGcSqJuqQ8/yWnykxq+GWXNikezdOhhdyOwqqUJ/h71GnsYpF0lUHE
xmMLNSddySrgdeuoJ1WmqVoMSQkZmKp8Gbu3tGGv/ygSsJAm/0pBVUgDUDquCNQ9gtXF80S9Aux5
QMyNlTn14rrWTeHBGp5rDqg2LL7ETGq9ndTLu3I8lrCQcjex66DGICGpclCZCFVX7CPYgr39/sTw
VAo9iCTopno4Odtve6etuxAfNZrgQqy9V5VSRHlpXNluxLWHf7Xe3fi6pjp0jhil+26jjum7tCdF
iTcDL/2CFxdQ9awPOEgZ5Ji/kXSbWMTz1GRjglVFuWPlL3h6+dEi2d3rJoOZb42byXDWSidoNoXG
Ee42GYpeVxHFU1sKD0LwbUNxGiEocHpj+mSS65yH5mKBxX8F9a06wVh8xOj6LKADvs04t1EQtxNN
tUCR4fDxK9dbEbQhMZqBLXwUBdmUg5K+PRHsp50gLQqA34Yc2QC1sswvy4ao4eFsA6ft8H1cdwgB
a7LhvssJxlop+7+/tYbbllPPu3HdYEC9mijWnXisKZQHj50+9QjyBnm+kuaVbQra2ITqDOJfvbps
LODhZHW82clcCRNSf4Dd3vKXnrQjPgl+WiRt34LCZmPt6A8qIpaZ8KCd8xZarv6kz8ZUkOKBam6v
k+98BggOJVFg2epL8gO3nlnfHz7v+XUlncQxOc17vKgI3ltbWOLd1Our/SQZuZN0kFzSfmtAZCbp
orz0uK3XiHUhs4vJsPm75cIG1K/Hn5mkSQzcH++yQeNsYEh5t/1f8eahHZKIL+5FNoGDpZZanmf5
aP8qpA/eGEIJE7Zx12s2eAgG/b0++YdfH85yAoCmdwK2AOSSfJjiM9nxSXAkgA9qLGEQlQiGSwOc
sMfbNgTi9z4mE4poahbGhrHaxxpsh40c43RqrmhBj8ksPZM/ZQHWq4B+fzMv0l/Ki0Okcf9NlIAG
M4RZ+HPF8yj+F67PsyFpW4eznjI4MAVAjOxy/rb5CWrxxm4eTvQRwQ59MpQJITLEX35ofwVDtYjx
qkfEdRoPwvD8jmG0/kUEJtT+4WTzgEVbbB3D74KZBk6awdT/BMfLss4BSvNl8SypTHYREHI6tgST
QKC3CCxbi+IxhvsTnNhfmCNPzQk066fQz0LSQyALTtipRTbDKRBz0jrFt3cc3FKYtHCFU33yFmpa
M62aux2vKBiBoeF9HpHTlG+tiFdiPRWB3LuFecCLXHxUEdVonAsD/x4juEexGVZ90ErRy5/zxZer
EYc6v91IsOAfcL2xeesQZp1ullmALAlDHErtTKOG1r4uzSw/0GuWgMhXnIfIomiUEQvyPCgSCCaI
nn2pdcV3T4EPbHU4MwY6r/5i5xhBAdbsvVqtuTIshcOn9iQ4sMgzhd7vw4n8as0YEenu/vvbPFw+
OCghkal8bGZZgnBTisX51ZFPfUIZw7qzno1TAoLyWYW0mFjZL3h8bk2SPQZ6q1nupfOlNPLqNNYF
SYN/evaJ3QzDfqwLR2+pBAR9pcybbm/yuyvKf+IQcdMrhwRCefwRNrUr+uSHP4zxNFHntKyG+R7U
1g1OAmuNbQWNDL7eNx1Z18lgbcdIUX5lffCnEddUUf5cF66lpcI1Z/a86+gt9ZzZeDC3V3qJ1Btu
rSI/uUwz4ZPl3fXKXYAMCKxlGHVmQI5dl3BWuVC+/+wwf5yORCM1HUKSmdg7eoJveKpk7xS6iA0o
xsqo3jK02OOqfGhwvddSO6ISlC/sOutQ+ByUtSqYw8+ULh4VgeVsPLQRj3ciHXaKO0xcZVRuSPzd
5BJbBuFR29QhIr9fS5/B6K+A5abSlDngR+IGlxymYJoH9UR1e0lcxDhfsYLbFMGL1ABJp+G3i+LA
KoqHQPGBkbrI2Ii078e0Q/7qajrRlMaK96ZcqnJlpSsNou47CWRK4cJZelGcndF2aho21rmsmQWO
Kkx9nrA4/K0W9gKbRFSjGkET7g/apLz/REsoexy05bOwT1hAe1hHX0Am/b8qoYV0wl4JQ8cwyTkC
KuNCcIyJTyDrG5whcwjxy1ylF2MOj7spCvm/p+/5tioTjnk/+b6eBPdooF1ErXeWDk6vtjPdusKA
5fbZyVZBihXEwNzrUcAq0hS98OnULRTaMRyD2xpRICamx9uYN1/b+pQ3qPXXIKtOXobbrWqTA59K
UJdjGwdQ8HzaMf1to57btpHVwH6gRbcqc61QA5hVW36LeEtydeN0ZFTGKbLPUNyNrZD0Hdvwnl8W
6BIueTjwNNkv5PVcIMuJUDFcROW10055Gt/Q1a29CQgpbaVIwlhDjcYYB5zg22St/h9iqBlQwJ0b
iP8hXWbJp3LuCG4BcIOXdboWPVKmOUFEEl2D5TjjhLTPO1xGBSVNzpXYhxEsQJigOsZw+IFHm1Hp
84MT1cPoOwXa0z/uf3rQWGTTb7xxhWfQ14Vz+sFkX5wP6Cc3CB7rVkLbOTd2KhRxq9Dj3Ql0VbcT
npoQPpHBd7x94F08XraXrTQz5rBthbcHyrPNGvU/RLJs6SX+mAp3zI51cvmmyDah9POf0aZ+2CYl
sstdiGXPwora+wNhfPfwnJHlZvMO5CcrvDKziCq3Sy1hFyTZKzTSLLs+dqwpw2p1BFuJ5fNRWx7H
LboKNsx4wGX7iNZPVMlzgZtqh/QoZTgmf6gD4HRGTgrtNjSPVSPy0xoFq5HxyAisxt+yaJxuRmw3
yuJ1Z2We2/cjwdIwReitDkEjotQfSRQaHObaUzSCEhslbZaMLibpSSLcmwMrfk9ZtUBXGhpUx86e
B+HYLZGs8fdSJ3WWkvufKmSDfEBXB+KmJhRYfN3FX+pX/s2KIsURn1wDqge/X87rCEY1l++59khX
q6ATpTUKcgWb5U85KA66fK5p0nHkeIU2oGV27Mxd7MGqgEDJpMb8rFzn3ENIh2yvj3pcKmQmdR+C
JHp5rGyDf22zb7SzLwQplUD+nXx4BqzicAPMmj/xmoN1NRmo6Iwqg6dOyXt9kOyXyLHJESkmpRU9
1IRHuvWTx5CeiF8PcAK1cIanginwLfRVyotT7UbYVEcS9+/LjoYId6klKIIINRN/g+IKhC+pBTgB
RwLGZTiqB5k4OIbVpiJ2Bvzq17yUYqGHxQca7ufWuMCG6UY0BXmXwpsphFzdqF77cxpgmksqTruB
/Sa3OPakpn89i3HUGGp93A4PhcllXdYvOr9DgV13P6lWPsoEtfQ+xna3u0+FKyipmlBskp/FV9Rl
yzpjMxMs9nhi3Nq9cK3agR4AUGitHGKWAPxm0tUN+2Yz6BqRJy2zmc9igPbM1y7YoPJRKpPUUvPp
ZUz52meO1kwLujF8o6SOfkRsjQ1VhhOX+d1/+PveJQ8m3aDBBtN1RufsR+2RM0aH5U48P+7ZaM81
sd1TnIIWAhCllmYVFzlNvZVYxnn8jb1cIYcTb6Lzo/1n2t73xmIHIzCktwqPg/JePu0vIjXj4oQ0
wOxvJATTuCdJxayPbnQbslK72/Pcpma5Np8ZpAkWNJAtkm96NrHxMA4vOsEAk2N5+QWLJPG8QfZj
t7xNhdLBbo+pUOSf1XMjyre6A6B6vbt2FheWJmUE5ZPOu+PxU2l8qDru+/+1Qfwo/jKWQd7974ZA
8qiQAPwfRiUAQuHnZamdkF0ZF+IwvgYheLmNnYNBphF2dkXwSQnNQyaCwLEZW4B3RFAtZdZMudtO
6sEXNNRBrtXOSc3fjC+Y8sYkg/pEdxlZOf/JaBS27ASZwrXTCfWQr8ayT8Tp01gkl6VlLuuRf3Uj
FeTp5pIleTeyfXwDx5V/eNPNa5FjIWSK0QYXO+2mohIE3TAhNh3HA9EcbY7kENwvGnPzkoS8O+D8
iQ6/LfzRo1l7L9PVIViO9ITIB9GXAgtAZmvJiLMosv7uYprqpyDCm3coqxyUvccW7B9HD67eD3Mx
8c4dIsPncJVIvmdpCiHfSH+N3MEbaw77bZJoYDO88O2pMMHvLSXDePiSsoyVsRL8etBBbzvW8VEx
xQKsrjDVbkx1bVXQ/QjE7fZrV8n3C6WsC59WbqQBwHNFisZHMUtXv6GnXoeKMJgyOr7gVrzJx0ek
vo0JypvKz3g4kB9oLbVut27+8rKLy+PHMkvMgbZVfZMuo1FIxkMdQo14Du3TcHvDZPqZH1NUKIpA
curabw30cPgODUq41ktSKwZm8LTzyF8WzBtL6uy7AYWn1CxR+LY8C+GIxW5jBVtDYyi1jGp3cgpQ
8W1FDkENWgoQRiZqzBWu1rBZ78wou7BgeyNrMZ9paC44hYrKeFkjxf7DxXt4PpKQQR3CP5VNm6Sy
4lhP8CY7T6GLRENfarGv13gyTph6RCKCwIh1UkN5Do/aEf+g2nHFA61ALfYOXUIvOGnLeBancpZl
djHll9TZyOv5qN5pjCIFcEC1Gdl2273T2csueo2KdP0PNkl/OvpYQ77XR0tEhB3lODQefLpv30I6
CsXhiVdtfrB2xHD/jEBN01hKSliaWSTozagE+p6Lu9DZPLPV8idA4RLUNV0x2O2uIk/7oXk8FvSz
d6tn0INbqWlz9VToTB/cFJJFcMydzrjCFgyuVEWo41XUTtJAp6K3an48cG2gS3z39LamkG6Mix7m
Z4JG6TKJaSNyPgBMOpQ5MARmYIqkNNiUTWfW0GPT6JqCsr18RkHkUtCpmD/ows3seabwbSdfsa08
EcCZf70uAih9BroVfvMdp5AUTYir3iF/DErgvcUt/EQQSMuNQXO7/0ss5he2yvBq2bed8PgwzuYm
0R0x2Fq8Jj0A0rr0AxTndyvkw28UwF0fws1lUDbhPydPmhemqXegMnOpW8dRQxZpA78vf2HoCG9q
XS8eoCg4LMfKMv1jblNQZ8fzNgVX7vgKYEot/s4LxtfhBoTlL7savfwZh4cATvJC4DUtkrsico8o
VnAtRSrgqRv86AiA+GdwjpJ8IHWB4jDE+i8wvEllSVEwJtGtJy5OSUmpjO4oeTUReT15NZlPv23k
nWy8VE7u2K1J/SI2mpAUG2LZ3jEoOMeZRNjKr689WEc5S676ZUsVqDE7Rjxlle6KuQRDLqas9it5
0TekjVpu0D9OnLAzZo+KPJRCgaMmUNIQkc9HQU5Efxk5ytYoMht+C3grLrYvsEygB3CPaZF1xMsg
p8qjm4eBqwI/V/sbBLCpzbyujmTmtOXMbM0YOz6Xi+pDdkiiJc3u6bIh7+1b1+xbrsyoZUgxmY1V
rP1d170dvCYBhqaLF+W5z3rFcGCeKRWhdfBTOCdb7Z1G6FzZ6yh3ZIDtaRj/cGXQpgCTUmwzrDtF
8fxxOrFVY5QVE/W9jSlG9TlCjhJgifAWzIZptG/POCiuMFJKKGP2PRS5QtliQUS3oVXTFLBAt98z
xeC7TvUVyy0fshq3XsFcfy6un+hfHmyYIXBQAjdJFGAM1yuphu3aFstB2mtHxTjzhHuZycjGRokD
kwn0f9o44ZEJvNResMV+/ASrPoZnDY/toHvWPRxGFYYHzSe8QCyCauq7lHUMuyl1BRAwFCsCkznK
GLMphDzD1rBb+k2gC/75632ve+cCbKlC0kx0bm6KB067O6qnNqxp7aH1Ql4OXSWuLpIDWyYB4x3L
NEdT7+PyJLaRPunMr9rww1sV4AixEQsjM3psfr1t4dIzOordT887UuxPWKXKjRJOdjY2WzsFl7FC
eZskqc+2upCD2vcgzVgD/UHa0Id4Vjalp+ucMe1Fej4lOsou1q0e+e2ulZEEt7b5lDayqdVvpiPY
YMOJsx3V9meRT5cSSm0IyuK5APwRMnLwp9Gl1Bxz7B3dG6Zzn52grIl1wsVDKMKeW7Lvh4S/TIN9
4T2kr1Z9apoc/qa9nIzBTPvOS3Ap3bccub/zgt8QaNIWFqBDRgmnxpjFJZzP8wkxmwM4Ix221MPW
WKG/LZgbM4JcOD3iJ8P9bwo+MAgteyYrJuWpkKKIZCK9X+MYq6LjlxMTS23sFD2mmAdROCOryz5S
fCPQtZdLb9CLh1ANpFzJXNWVQ15bGQAubjZxGtIHUY/Qo5FWbUgF0oNbIYZrJp94BWD6qH4dk0SO
t8CtSmY2E0tUdHXCIbpfbMO9Foxv1K5/2eJfulCFv2aulC0BHxAymKU/4+qLgv2mGDPKztM29L5e
nC8KAvOdM8ee9FxdoTYh1qzX2Tp4J7r2Kgv1qlCn4ZpLI4XiMV1kZ1RzvolmuUX2gsAlmCl8tx6F
NDuryVMbaAgazig1FfeVS2qJyedfuymnlU8anZLk6obX54u8TIyJ0nQnPicNHvUkswjo4We7+4E8
7E64rehzW41GEfWMoKB8CGPWzgpQ1fPOt3btGmgReW5LzhdjkGbmS9TwHZPNUMf5Q+ify/L0BvPY
9FrZJFY2Ehh9hAMI3A2h6JinVBfOJEcf+Fw/1veRalhWklv/O3uAdMhUQ3E0vRekvn9czv7mnn9W
JdtcEkTIkJv8faXv0mvuAnuqFtBSHdhTjgxxLTTz22E20V5sAw/+BHWwuCvArPdLUHxFOKwPIToO
/YuhUhpvOiZydtJ4qhoqJ+PVpOtV85vQQz58QnW0NDh3RA8T2rClumXj12RW5uQN0rEarMPfGyLb
E3oIzIN/l0aAWyd2vFgCgEc3A7mNHV1/5Fb0aYqCJ3GsD8F3hyflC76pQRKy9O5s31lqewoS1Xc7
a2HR54ZDhj1LW8niSGNnJ7o0iuLhk9Wt7XyVB1xJlhcAQ0wBS5XgEmzx73e0gu1iNUDcPo8Rczqu
NhTe3xMnk8lBmSkPCgy3t5q+4QLraFw+Dxp4oRztViDT+4CtGpc6IVXXMA/8T6yLXzUu9KCuOMYD
Tt2Fv9EdJ5TAZS/8/9YPaVTEHnpNxUbSvHffgZpPPSaht4YLRA0WOLvS24Mc72wS1TaoOG+bklyQ
QCAARBOKZLoe7tS8HARj+rA0ir5AENOdfLzUGA/NjYN2fQ20k6eIaBJaFx45/PcPfAzkedExjP2P
ZfBpb1zaAyH3b+HYDXkc9l6rlVh5ngq8eQ7/3H1VoH2UfHRE+4QaAxzBsExVe/jlmNQz3QRlYyb4
V8VSuxP7QDS29TU7nl7YS9ujwT8VaBSn5Voqz6HhzfIaiiW36XpC9lfRqe9+iNHLYpGB6sh1GQ8M
2UaFvRwkUc+rqzJRMXRu8h4dkY1b7Ww6I8ZiDTG8WZKTh0kZVIQ71hKikDU/QgJv/la12KnhMw+1
H0M9Z1lyNmYq/1+/JDqDOFwfehCJTDKIOlczbAg8MoLYMau0H63L9p5qFoNkha+Eo3MousyCOaIl
udtyVDW8Yhr0C3dLdqUtm2PRv6FjEiJdBuMwsp2tPLY3mTwnqvJCH4v5ys/1Mzygab0fwA0FygFs
WBJ3hBM2GV5G/ITk+UTXG5MZrVG30uXzHLt8JN7dmE2POKFrVkW8ts0o8ZbxLnnC3r/GoajUxgfP
6Lq0C8VDDf+fHGlV3ZBL0NXWr3tBQtZikWxk7cStEAmaJs1JqYX1DJEugkcdjGPpLd2sgZxkpCmA
hdl1NMyahmhe5RRYdKkmjoBcAUsdCIxzgmIANYdR4LwqYjqTOxWBcuLNzt2HMjxY5LPR762YRoJD
MA54IcZ8UhpTTqPdClUJ8Aa4MOKOjGE2R82pZ8qhtJC0kOPSKZJBI+LFaT7gtPXqUWmL1FmJnYou
jEctl4T8AVPRXmIUj3vr/6UBxSlXxZoTs+ksTEIy1cX5SaIco+C97oJEpMYQWoJJ64mfmCLE5oTV
lH1ev0D4gHT/LjnfqjrCSd7+6TGdCUFdUf4VCUk7avprqPYFDNQofY2YMWS6uG+YnFy2uPcP+rRW
cUwXWg63vhc0YiN5583G4aW3iaDlMQ5UujiWgpSOveMhRNPZA/m836IeQefMB8ZIf9I6kpZUCr36
oeXVEpcqUSuq+n7y6ocvsy//O/le2n9vbdnVQHhKEiZH6X/NgjEApx3ZQVBBnUHa+E2muWBgL/Jw
DstAqo30XtjzcVhP+LGJ8Y2Q0CZcID2/AZy/1i1NggElV+7KhUP0xyHk7ZhaepRmD+UgO5bwd9ed
gwoxvNSh3mF7n2OWeC+vLSW5S4/xPtN9R/vbUdpN3G2VCaJVPolfsmoFBg535khxAybQ39O/+dEZ
Iy4l7Wyk+oDopGHsMCJhwsZUm6f9ZNQM49WHA8EecS427vCWtCFLn0rvjMLOB/VnxiEgUt/Poz3A
gK10YR0ZYsFd0cPhzHlXkQJh3YdIFpe/wkSBy9MnnSCDRPwHbWDvZnZfhVNySgU4OvvX/PP0ig6o
mep/b3g+9bqjkWxXp2ezl2S1k4eq+yXB4Mv07lqzzTGJh1c2vYdReKGVB78RwYrfO04fm3egxrFE
xEWKMidn5jHknqxiuUeVQAxfS1CDqIhJFvYt9mqiPcArbKLeWlWcitxG/mD1tO6wSYnC0s/psvOj
LHm9DSirI9lpqZcf1+meWCvwlRZAinBllHwb2UrTgh+TWkj8I9O5dw/OOub+Z8sjzMfkBAmYbyMJ
pF6bl+yucUNCvAiMTRhs4VH7syK/lu+uEoL/SR1JNELyu2TopcvVIbFNAozA1K+LB5s0N8UnbAAg
+XxCoB+ie6yBj3swxSSeVhCICp4Kd2CC582OBcrbVq/Yav5oFL4il4MAUnwgvGN/MdADTLvhO5n4
sivWm1spHuS4peX7c7KirZ6/bjjzWHMeRz2j7JV9PljS1PXDhwpxw5ZzX6oVL6G30XdLMcnBmx0+
/sMMHXMN0gPHIeDRjdnA9BNxGTrTht8LXbIrcuSiK0Dkpf5q3PZuDYf0bEn1GhsTzE00c1WRcePJ
CsTbraJ1Y9530xkSWdqeHLlMnax/VHpswChN/aLvjuZ+87dwTPOy0yVh9qClQP7qwm5YwOl1XMOW
xCOdKIyf4JKVsEEAqrr/4qwoMV4mZ4AEK/w16StBDWnk4E9kbvvRzX5JfDud7ifOisVPIfffVtqx
d0vIUcuEP/KI4B8WnBXFp8UWHAR9ktdmM3Q76uGZCwDpqWBgKxFvU8Dxq5fwdqATwzNiicAEz2x4
Hzj/GhBR5qtF/jLyzgSEXee2z5F0xF5SmGKEkoBu6H37Wa1mRA1s/eyYnIXRbPFnQCdWjy59LN20
ZUozinzK6EzHyTgeQeogLUzzGEarOezmHKPVlyiNOjdQCfmXkhCO1XYTe/xiQ7x6s02IVjQwv/cl
fytVYvv8hdSCRxaBug4mSW13tzUL0S8t/z3QDHPcqLkuEGjjtfuYo0MuWPLo8htl/AZFYjtmmVpL
W9syvINx1nwVvK1qYK+zyTEINw2LYKL/VAXQyM0MEEdDoYmp7OghPkPXvtaOPIcxIgy2kf++1aeM
oQOv30/TMpR3UbF7CdyKPUcJRaZkhyVwYiHESHsNN4aCGfrrsmrrfPMWGrXFAzU0ReK6lG5/bDlS
iyXpD7Adlq7T3dzUzp7TULqCKaSxaXpnGF16dcfRXWuQcEHDujPkN/Iod8vMBr/x0VSVGpGFHhD2
cgpV6xR3zc3I7c4HIjmeF5STmxN/LrD5yr1EpSCb1LFQyKKwmUUYI1njLxOCuZ2fZ2ruBdmLJxkR
4GYJ0ZtlqVgu0gGKvywqvR4kqxMjhPpisBRGPeioXSd8OHjpmGD/9VhJ9+e96VA4Z5Ml6Vl24CXT
Fu30lw+znJN/24j2+UqYPaRHNzx9Dk6w5yZ0NYtfSpxpUSlH3aADUFlKXeXjH0JnWzdowU0zjXoF
DGSObrB7Gijyce3oCqPRFqmgViwOhENhBMr0WsLiZ77R4GfoDCkdAU9vWV1sfMnuY5xMFw0Ft7u0
lSDSQz3zIEe2hYhABRexp5v+48eZE5fglstt0ojZ8tcZ9z5EBqMfvp34MNaGSEEwPdsbAaMmOnl7
24o/8wzUSJ8u5h4QFAUS+kZxyNQI7vYY66k3e26Hda3lufQn9yqYoptbzP+sdACGVzRtBMq1V7jB
sWlFr2mgxXwOFJd84wKa9gvDvgHJzMvWbqU61hvYQBU1vq96iYWJzKW7KPylfV4794PT1rvaEG4I
cc9YO0mWiqhpeKrZ+nww6YOWBySrCGJjvGa0F1PGWHmnx2hSkPSXgRtS0ZIwpqiNzthLixPvQBRD
v+gennATBUriNLGff2tdMS59gHE3J7xqsxCz8bt3l236rV2pCCcAgAt0tn5n/y4+f1y6pPIU87co
OM/Cyqulp9XpByLOXYU7jjE8+P0ar2Bkom8ju+Vx7Enp/Ug1EXSi5DHr5HxCGrQme+ctTTH7GcBc
6tQ8RIpa4yrP19RipEp6b0aW0UGOoMJnMaiOVReS11FZjxSXafdk/pbmP4M8IH2HHPK/AdAQjmwv
qpE/tH7AMrkOHgtmlks5y9X6mTfOKB4Vshb5a2ezIVOrz+AREoRpJgMP7gQminWDePxj/xvTXyv4
fqdfpqagYsRXSh2rYyPhCfdVTiqGcQ83HDJQNhSyr5+D6pMpS7hxP2sJyqjBS4qRYI/B0LGEXgE6
WOTCS7QOagRNwyCgDCztiW4GfjSMoI1l1ooiqq7dQFCC3P09eHcwEkeBc0bKeCBaU7KRExzeqYMz
fJYmH0pvorESHyi0h1bSJa87VKq+yZba/Ju7fv02eQNHV7PPbjvoHo1jqlscbBWRY0IYQ8YoHKYh
vPCOxWyRniCVOcoSCN9Md6TXD2UOV79KLBTmhvxWqEm6kZ16ha3iL4ASLg2JfQxryOW8dJ8W913v
OGZTX1Lyur9+1jQi2dHboM6qVr316e/EWwkXv37UTVrwhaq1WrvVTXAaL3s0NqIFhjfrYwgLFXGp
O9mVXbv6XSy550LsNzha3l37Drb9CVdxy5/aC4THtKkhTCDi0aNQ/DNy/E9EkDBEMgOqbW1WupwQ
611FhGSqPQwOLMI5WvDS9CrXEK0Kw15h08Vxg6foCkki4lXGxwG0O4XTARBT9Y1/gWOlVswr0per
aqOlBbiOMXsqLaUirnw8iNtBtMyEY/okrQWA8MxkX+tyAK/76rUeaj4c7R6n1TS1PycH0yv9JefB
WTBgYho7tz+kGHJ985BweJlqg0cOpeKbfWrNhSmGJnypInsbxAIn+/1x2dyQwg/zpNB/AjdejxA4
Nnkoq7V4AneNKCwMuBb9xlTr/f6jJExZTkDZ2grPdteMjIVCW5RthAbVEbUPlqT/5JdPs9QDVlFg
78gEQzkfIV0TZ3VHkufpccbzkGbLt8quu+B6auTZV5mqtOHoPKgK1MnMQ4cOc+YfCIAFOdOShi2Z
t+vsSMTPqt7GW9wm+2ZTUTudhTedxogVUopjNUyag3Owx1+s1Pd4LIDwY5JX3v5Uak62UfVklYB/
7KMIoMOziLF1Lfcpl2nIZsoSGdURGH2RYEwQjFkT+EHqWjyEkjZaZHSqjdBZiQ4dcrMwMQMkiefM
KeXJX/sV4yjbGLxOz+M1mlsHM17JlOo0PEJjt6YiZjmy/jVjIrQUeDwdGZrZLiDbOmguxtGOiBPt
UyKTfk8r5n9TZPtYMgYIITg5PbKzA1ug/ySBvoiUedWoIa+zGlYSMsJ2dX74F7hTcNx78R3sd3aF
0u/DBhel6VxJkq0y/kb7v4ANndngOy3hXVMYvQbZDoPjuGLUeYzwfdXWeakzcy1LDmal6whCzi6c
yKimVQZEO4m2aigv60dTr7RH9LKvSlL+qDUIbyQ3xBQTQP2PxGJv8HfKepS6Tvo2ZCn1mu/BcNYS
7cLt5OlgDlIplrASVcoVs+Rj2aqPI1vioAiifqih2s1emc4ulWT99z+NPK5jssJyDNJwVQnMjFIC
YgTXJYymo/WD+HHTPLkPd4KJRujgc0Db3xxej0OA9Qf6Zk3k+f/gJBT4T2Lo3mJ8xEdErPC1neiL
K+JQmVMqmflyGeD/CA4dmTSYUtiGCQZxae195zrori0gAi1Bm3eIPF4JMK5jL15BJbnzpsBE47h9
97DOj79ZdhLfAnQPkJ/gKSg9vbBLcO1N0PdUHMcZtC1fXC0mUr8WMuOexPzr8Rtvq27p74c9CIF+
F7H9brTPwLtt05OZRhD1Y+q9Iyn8dj3Kb5I+R/ZAPDNj2pA8TXrli7kpojPDbr07ydz/2fPOoS7D
MV4IjJPKgGGFXynOKs7G0I6ozPTlHDiQzgmYyOFkuGRw7xKYLLvg9AIw84/j+iO3n4laSWM8z85b
67NpU8Nl0WqpIYgF+HeJ8uXDV76Wmuy2NL1OeQa8Lk/mUCTw7SFAhUNw1Tx7WNu9gJMB38iuCUEe
DIgpwP/+FTGuQOn9jdzyVFwOwwec5vRlqWAn0wc7uoT/VbPOanDHSmzp4JBaAsRSe2uI4HC7PDH1
h3ElZjyhLsgajzxYcTQa9xX7lac7y6a38+4GBdOA64xAAgML7IIXTzKIBfOas/noPPjJtqUkWBCu
r84cAaWOlHR7rWHbNVcG9Vz2UW2cUooj/r3VrW9tFc41ferI104P5ZT+mN1W8QEhtASN8qe5YwED
RNXN2n6/cyqIeJruaxxYLVs10sGu4UKuZ95hY24r2u/DNaYyHDizKBt86j5RmsiyMLNDsk8jOSzu
1ecvwco6mmmkBvaPH3LW/HiaEYUiVofNoqd3DLsQujnYucJgQufIJVJvD72D08DOj5sn0bXjprHB
ySJtlUeuWSLVLCR4ebW+ckgyJ/7UYanuzjyG35twT0Hj4yacxc+phkK5f2skfppd0iPW6gX6iBgw
YD6qMTVi9qmdRxypPL9T0hXsefPUkm7Rco5ifEstLqzIbxUEZfcEgQLYMG3+ni16X6e/f5enA1cp
qGO5mQ42ortCX7aIlZDsqxxjeXXh8/bcbFaIzTEyAH34pZ9/DBGZlncQnxyG/Ov/dbSrN+Y6i7yH
hNWkHav5/eoFkcJeh5uzeSnhvqQwNsHIkwwHQFzSwJ1DTDWFpT1hvN3YhRz+4OG2hQVi3TarK8XL
uOHvxGOwjNLYReRbKAIHPFIdm/PEcKGsQSVfo5SxMEdeizM7sr+H3Icd5DtyTYwzv78vvGJ67j9H
zoTi6jN5JSPUj3VETfw9OA0xIor1dpWPIFnNrGcEqyndfcBef+S5oqS5hzeoiLlzoD6p6HfC5ANc
oyRXG0DP3jv8Y6SAx+XXjPPnICcrQXfbQNP8Ti8WM1Aj1lJuZACbYVmHPpCjpTcoYKhlYrNGgp+c
pBpd2VKPv3DGFRU4V8oYBikgG+Tt5rhOpK5nQ3lWYjGUg//GFGo548TxZ3lf3wFmpBRe9AX2a0/T
eeTECEG6FFFflad5OPM+suMRyQwWymOIZes6xbJgP/Pk9bYdpoOcXT7zqR6TmFBQebC8hsWaMOXY
wIElbskGBAL4JVKqvIofcbRpcb6MFeMpj+whRHduE6IZshiOKUSs4zUL3nz5mP/I52JwBkJFNr/S
HYvO2vHiJQ4XspMxeFI+RldyvR32GcvdcTYUSM6SDgA1ELzgYtZ3UZ9y7BynU0svde+y2Gtj5pqR
m2IxNYbWbQEHce54EMlzYuRNrj4KVGTChK64JFehaGQzNbiK0GLLtIwW6dNUXN50rJG6gr+Lo2eq
gIeJlFUK8Zd03uHL3/KnZSgcMK0+Y5VP48dCK07142IHeOR2D3GpdoDO4ekCAjn1U9zTPASPgjAz
DWuSUlOfOOxhFR5BX6lgITp5Fu0KqLfDm0/Guk6MPJ3sGDnvF2PL16bXFVHFiZe0LKJ03XwPfzsi
YL/asr6nt5XONDt57r00qZRWjY+DL1hGN/HDCSGRA+v0/Blr9BDdgU4WoLnLkNWm1Pb59DCgQQAw
jWaxQLAnwCzrer8jEpjhZQv3t18SIgO/88Dj+0WvkeUUojys9/kh/ugVByAqE4ekTRc0qxM4n/XR
srBtJig48cD//YMrGipeeo2sQaAnisZ7rJ4ZJ1lZZCbromkp2QnIwtt0xyC/OKDYBhKq+pTgX7Mm
NnnncSKSFgQyfvotCmQcUKPVIrxtbTnLx4afa9eZGf08qQCafGx7MPy10buZCa5TrX0sa7ir8SEX
KvGp/vxjR6eQ642cGgJuBKUMJCltLln9hFz/1pgGf3d8wI52GFwu98ehEosa/LFP0Gr/D7vI3LZe
2LPDLPFpCPJPIt84+J5e2iwJm1mUMWRTC+TT28TeNEE0cx1OlQq0L/Tm5gqyycv9KeYleRsDeEY8
cWQHmErdcWrU9qoHVvlYQT8UdJrdksXw9CwA2CPF1n2eT4tPcHYiJUxDrva+UXR0BQwpL8EBflL1
ty608b2ByJ/YEpq4HowEzVhv5fApH4gKeM8dTanGaFKS6bzZXme1xanb2sn0mRyxhW1YXIv4cRcK
2CIRCTGl2Grr7LG3NyGj7nrsgTDyRgvZxlicu39D4Ju9+fBPx4l2WJo+6NRfWqneg5hYyiWpEwde
gHTQscqFJHVzOjfG0Gz6wZOacd8YoC1Uk8edYrou7YBe0lTXgAZ64VZixFLRILCt6y8lI2MjJRld
iQZJ8mAxCaWm69ccl+JxgHEk9fsZbFeIFixidrQXV+oatq5HohWL/g3GKYoYelTYI4pdYcT6m98q
UmgCnb8VBSb8uZgwwTBGMOJNpO3avukA2XspjEDPiPGFJsceZlLN7cs5RtLzaGKooYfAyjEDq1wi
PNcQY7MMh1SWvLlYNhY+FmSxnMrlS2F5DmvWECqnw5LLXigDjiBO2pyASFPqTRSF9MKjzdeu8Cy5
daIDToDp4S+cxOmJGLiebwXdnQNEIb2iQhKo+qI/3wZpIj83yj677CHC6YBGn8bvUTD8ZByhK/L4
7wCJTzaHfGQ1B6Icq+6R6GG+//Op9uf3lydXPCU8sYmGJd+De6I5OzepqHmn8W0SRg9VIjAo6Kor
6CLrMIeymNth1u6jgbIuDCLNerrFnGLrEl4VDGhOQ6Vg8hzCZxHJhwM2MK7iKDCTqJonvDLTa7+m
tBKCZA16rdVAVNibOyFPriRiCnFiEUd0B2l4wpL7MqMByZ/8n7sIXtbbf3DxS4jADLWebsjQPX7O
N7Ik0XyTEqwCJYJetYuFE7npdI6Atds570fsKM0WBuymIzik7KqvNbETJ+X6Q3xjPN/jmw7+xb7i
A9bEIYZttpEMdgfLRTT2U+VQosir7fONngKTZ0/2KN8b3pcHNHO2LN1nYSXKmMDH7a9ZA/jnsBB1
LQ8AXsy2tdGOtC9GiXq+L3Ia5akXesFYEK9+6kjMrImcmPrd/MX3jPpU84mRThIl1Gixtgv3NA+Y
lqFcF1OtBNKul9DGiOsB1vrzkbj3ZBLQvTN4s5150o5WRZ+r+vg0tLdElXK0RM/X7MecJ9C29wUZ
Qp4DFwxKKwxJA9+iqd1OFCNwKR7Q0DQOR89a0M5+2mL13GZGbYJ3XQpK5iiVTIm+4reY98Wj2gUX
XLWkraW0teF8LgGikp3u25S7/hZH3uJxaf0MyiyINl7cnJMPoSp7ySWNMvUKPfvVZlK2jg7bzBmq
uKLcw35MOQasEp/tiyieGt4QQmhXT53v1E0yZV7wYuHJDYsnHMC/fIl5Ob7OkH+jejJnBR9i8iRB
1Jy5zh6rJtwHqiAVmxzX69AqccS+IsMKYC97dRnGekgL3E6k7J4B+2ug+vhfH4MqSNJ/GnmexOGw
Zu0Vyiek+zNsHSSM8CPslA2ElesMHyhJCNvtg90MTG8ZJ3VfAjrojf4uVSQKUCG/W28a0MA89YaV
ErqfAOJcVApyehIheBVXtHxYVEAlxffP2nT9dcB2UdZa2bUFX+u8W8dxDtt17C4mrXDeUPJbAw+2
DXhVhuzuG1O2kWMNHLLXepLV4bmJgvCW0cfA7pcp1DD3BwtZnPLx0/CJlb81qkeCm6/G+zo3P5Bu
ifPpOtWygahIqrHrAUg/GKfv+ava4vorpedx42LabMdh3prkzLhWuSdbpfxHlHFv8ElczXSCNRYF
lHGgEvXIY1+yZMzXNc2TeHfqE8AWNLPuXt1gnMUyEm/h0yi1Eo5JYVReVim98C4lFYyowWrtLZ7B
bDXJGN4KO65EAb4sXt37p7JieTEobfMcOZoFS00oNycrYTxKMrujImrQwTrD072SGu/PAwajHhlL
HsymzW5TNRDvuJfVSHZn2Xd9WlI96l/DSJPZeiPL1VzQLwDIKywkGleSj9jdI/dZQ62Llqs20rdH
Q2OJulmVHCKNfNnuj6nv8FLYmFXP/caVqtiOwfc7KmJEhKiqGUL6Se8NOWm9sSbETvKZh0THNrci
sPUUBA5BHqzIBbrF8MlFdjifopR73QKUa9u/SZadvjmj31QVzd2qbVaPd7OEsDPDfBaoYiRFI6YV
24yymUdp/Dx/k8o7ZeIcrjlz0ZqAWOqTPl4nIRdPwGeDOGfATlthL4x6BnLrSd1UQ6rXZyQeqc9M
CKuNWotnGXA5sCLgGkg9tVLSB6Nk5iZ0RKfhDUaTRxJrKSd0ucRzcsN8OLd+yoe7ZH633/jtRMe3
8Ll9+yUILC0x8dnkVk0cyJ3rtrP6LiyYDpWS7c2q8ei4Kozkv8HOKmUXOi2TYC5b0i5Chh79t5Dw
JI5oeiDr63C9rE+sy+2vahvYovTZ5gqxgOfZ/EZDplXKuI8VnwUEaMjGst3cD/LKMnaQrbHI4jYA
fudp3bwY1s0q+rA4/jVBBvcDdq8OEwfRN22Q4kKNoMDkeIwuTjK18203OmQraavE8ohKyT3OH6dI
wHRg+3t6BZXJyGJcmPzplro7348LWnrQ88WFJay2CXxGl8diZHrHqnFNlTbOt+MK+YAJ8yH3mz3o
wm5eIdoPY8wdYJhKEdS/3s8u2lhF4qYbuC+QtE4ait7wZBX9gO1IDAC4YXiK5Lv+X4O792Uhhw2Z
OoRCGm6D7GU5sy/k6ienqzFyjf6MzX59a/emBxZ4iMoZ/Y6QIoawD01KxDd/OCF/Q7J7AXHloLGJ
nSTJLEd4RfpEUeAw6dtHlduxkk3Ivq5QP2gexxDSCGf2k6nYJ5DqvAjvloQBuwZiER/mbQ7c8PSa
hWePVltJs2RmLrBXm/a4aPxeoz/1E3NGp0KxfFqSEqoxR0lzoKyKnTpWa8hutfCsIn9Bnv/bIZnY
kh2voyOgTWWgUGSHMwgWwP7CnwHKwBmrLskj2qgS1StZCeTDuvifej/eV2H/br9SBlhIpOWRgphs
hL8pDQIbVXQfIjQY4pCG4wSFYyu9cPLWnKMWmOoFPCYrh+pK7+avSlDl7fyhYfvthcb6Dh31vQT4
blpTmsDRDL4sMQlPyFnsSJlYNWmfrCJC2Xwr1cZDBXLmyEXGBZfKe9H8FNSfsR0TsuapuWzOMSOV
+ARZBdEiqcL9FTly8rVCgfxooPtHytXsazfjxLQZ1dfKddk5vGNyVlxsxCQIabF7VtJDZqsYkqOd
vvlsnKpMwiiXQp63IkuL/VF+B0KRPVH0czoxtRtBCww+q3ML6jbM4VouFUMw2GQxFS/D1SYaXEjy
E/I3lZtzKx5QZgcpniXTlYedSLM5AkKjKpPsBsDDVrpj8lysCakcOApZcFnX9noAL5A1tMnhIfUc
f3tSUL168B+ySPHe65kX3AilnBShZFCTjEe5xpea+AoN/U6y5h1MlUzOM3PoSjgR1BBVko1XCKph
sxRsKSaCdN63VnP1hhRrTlQe+YhjmkAp1f7YAP80DcBuGo15yWX5k5cPFzI94UV4QVHAKqlg6jqR
uJUIV3dfgJJX1K+zU9WlIXWVAbMBwz1ZqgVjImUAi4Wa0VQqV53poTLIanA0/vJXsjhAltPj/5Yj
u1Ynx7AKtQuv07xBO65+FwEHmBCWLx21NN2JfW6Uf7ereoJXc0YD++IVQjDNfF47EYkjdVf+tn+w
6Ns0shMf/v5r92rHnJZHOys63oCvnjTOzdXjlZevl9HccfylFGtQeim7oC1JrEySwE17CrJgjI1C
lOwlDrgLJQTUeOSPbABDl51ZgZ/BWbvxkiU9DVGW5HhfxGkvggDkZzo9MAwlqgOyOalOIPk71Nrb
EqoDbGYKFFAgjIq/dqWsu4VPvNSgInHvCNX8UWnttyBdbAA92h6FRP6tPNDP7moxCG59CF5He+yp
KW3hif9F+/OgNswK7BoxVlKtqxPTDzkvycU1Z3zumowTThf4ULAKgdV4hb4el1ksdL5Z/6byAGZe
TnjutOyUr0FUfiqrZpyWCfnmx/veBX9EZyYErLWtnRPwzuBi8iXhA+O62SCWTV7jcfXaaEF3RgEA
8JZ9imcJ5ZlYEhcWShZ5HCTW1Vi9N2zy82YF+m+tYIbth6t9WYMgcwp6AdQzvv4IuUXbGulFA/w3
TNeiNauE/7+uax5XXOHGgb7O0vYZ1spTFE3Ocp7LgDuV2bXdNHlQ1QTPjZQAZlCvPtQy+6Bx5Va+
qkqUliV/bwb+cxQ3lr111s2CRFvKUAg4MZm4skFs6OAKjDbgqxzCSq8Iy1cJJTArVKUyGaE9AvDJ
B8QNtHxMgtzJz3Zf2A2omKV9ny57Nmd3/y/KpAUVpGuQNZBNHTE4XvfnGNWvdeamKD/piWy5n4YJ
NTgViOiDLEGyrhhnBI/Jwu89pRWVU8usDoip0HcVBhHrhbm6z6lEqK/HBAQycJQR0Wlb4tDhd3Ct
iHNzJ0UR2r436bNgMuE7l/ph2JA3V7TkK9CbpQCQ2qUZIVwOQ2GdpvcHpa8fW04/joRHBh8CZ3NA
pNIxEaGlrhRVB/I4SPQ9r1UlsNKk2ffbP0KEiOCiFCChgu+allJnCbG7HUqfcDRFG9D2EMmwDWAY
I4eCsRrbE5M7JeHZcj5MIBeQK2v2yi0jZVo/3t+E6Hxbo51SFKyuMrT7gagsoOvsG51l74m4XthA
/shMY53Z6tc9wPxqZAby4dbLyNwm78l/RCXFDxGGjtlYRBBx656xRWutfrAZ6TBDAW/1U/DBa46H
u7fPD9oXAPJ4zeZNvk1uP4yK+7ExkkUmT2pQxGgyBMQZsayFz0h27Uie6sF76b2OOwoX3SUxvmMD
iPPRGKDg/JKhtYQFoWFM5Ud7KZ7l7FKyHAPbh3Z7zhS7zr4P0KN/4GWJ9hJZbkVVch/vhZvkPXHq
1zq8/Dg8N1agCq03lO1WTuiOcDfMubhNlyb30gsZy8YQyQMUKyy1NOepAGleMBYTlR0amEHKT7pt
mNf2srZzEgbYtCPg2LmeJFM+Y/cMLSavN0iE7qSs8H31SF6XM+tMjc74pvy0L8ZIyYGYqMZR0lRs
GyjTbH+gZAzJKXxhfjQTg+1pOTUL9cqF6j8fRG0cGiXUL5MwuzVYqEwf6FnZoJQmyalkbcuZTMSM
D8gkJOSskV9cnmKVoKJcpqWpOLOWNruZz2+RZsQi+gg9Yo+xNEesppm9DvRfuh97G44Bc18kUvhk
ye9FHOFhPGkDt0HHgsgAudOJzjp7albn9Jwufw5jRof4siOS5lbbJHtHDuYb0aGkx1DZFEbvTydL
DtZTbLC6RKR+L6AAMvkA7nDUahciJu5JE+V3R3TBOJaI5Zf1uh+TaV7MMQ21e6n57R4Txj3XT7FG
N2G1ghh5kfhfW7/ZA4LoMqQ0+ZtgdD+hMZw5ENj4wiDu5t9jXakktlvPfyU3zC6F7Ec6pfJJsYON
E/QL317qxUlDLvxKZhM1dio6X1Db47lN7rND3w6jvGfr7R6oZKPKsymXrcGtHIyhkWBf0qLmAHnU
8mrcsiAg8i4cNCHO2e2nIKNyCuY4EPFnG6ehH7Xfp+yNrhWctRhLrfVm/tAlf+RANjxwkaufuTFX
fmOH/NsiCQhS8r/nrsIfnSyeaPTs9+UbvqkqS1VV2tIGerK7pa6ziEsG6IZ0mQlXAvx0VGsk+948
abAIDaLOezv6zkWnw53vjesfEMKoNWzWY+NVbcuLDMmSXG9x4ny5MvJLvi5ePkXr2pznNy9cZyTX
Zm7QNGJsVfOhlfegqkVFk6hdwbvLmE9Go6JTYGb4fXZ7Ac6YDu02v/KHvzNRKmDaEwsMh2ULfdOO
ZYYR4XAD5GQMZZSgcEq0Lqxka0DvaJJ+fZA27FixOT4lsLByaIWa6uSLHjR3SljgCXjWJ1hUNfnC
O1+NvJ/1ItoLSZHGBgElOZQ5oWmic9a5Om1SMP1BFJATLE99ISeRnB23PD93AE6ELkwBfgdIRAzv
rKz2eGvY/KQM+LUclQT6WTV/VQdedapcW2S9bxnyoBdfkQAMPNSiXWr4DFiiU1eLLcBDvBY3N4X/
iW4DYGDuxtz4GnxVAy+Z1ut3XUEk0wAFyZpPIcGZxIMQnb9F2TEI+0zAuM/4nLLiy6G+GxnMAFpA
i97UF+zSZKEuhW2R7x5Thnld3DBUCaf37BMqjDA6RmnksnHcUiKFdcHux5662AGmoslzvwNo37E9
NYzcL4weTn+JIKINGRKT1a4hDwNiAnc4Tb9JSksFOXpi64Oqu5QZb6xnQlZXHGl+04GuVasHkpis
zhxddbhw+gHNy+IlauOSbemc6R0R7ldqv91s3jH4O58up7+ZVrKx357mqXMUzTvZA4Jgu8cafCYG
8U2XoehZX5vAyc+YVdyZ2YU5aNbumFidXSHRpUIl8k+ofhjotDO6tpSZepuArgcnndAgHhPzEoV1
IFFT0TOVdX6OnZvJlJKBKEKew0vJGG6mGwZtmce4w99oFsSXg9ZIpw04I/eYl1FxwxGHzsd8Xpk/
EWLFrEk9RY/vKWo41IxVcH2MugD0qnSPATlUkR5IVXazd8u0GaQ7n9qaiLIxovP8hHEKGNEg+2PH
MocDOjxZ2u9v7DUUE4PdYWUVSY/TWKplkcF9BT9j83VUz1TO6z5t41c6IEOW2Ac5krH8ect/Eok+
vpB2c3OlOdyJTBBwgFw+svz/l8f7r50Xx14CfKhZIjELCif7BRrlFwwr/Y9IxHwpbg4MPZJW/QGo
bNVSH+g3GawV57fXqBZV0Sp4tNrKEnUnvif4S5AJzM4qpK8QdirKnzS1raTvx0N0vfGRAQ64bIaS
hL0nQ7lo7unW7gSOlPIn8c+67yxgGvz8W6YiPURUvlNW4jsfDwTQRiQzd/eoiOSnSVwfi2KbyGef
CXBNQkBg6Jft6WZGVMmft3bhyJdrybDGsyhq4d2pO091PXJDibQrlA+pjywKBMuQPBNj7jNwdSBT
Bzn8lWNo3GVnX67Sk5omdqcYGjKpe8af6j5V5+HaCkkBRY9dU4BaaE6SjOm5bX50z9bk+fy14vD2
DGGHHDHMj8kUZmh+7LJUfKdAHnvJdd9zEsIvBEM1xhVUR6mAdI4/JAUUA7ruTQyjMDgbWU1eIqNA
qJQRNM6KKsLvo9qVuaD/hD/x327PAeFiecLLaot9Jb8XWZ+BDj6f11M+U9qfA8Ayv3mXQBpKhNgS
qETazLlLE/+wiu7y3tb641PKGGhQWnfEfoC+mOqNfmYy+3cA5UuCpmUut1yruRMYZihpRCAODP0O
6OpU5tSM11a6Si835skciyR4RdLzRSvU/mIdIpxoPf1FtlDqMFxyShtOUisbDqRjZ3wLnKju6yXo
GN4c8oayW97DbDeMgg4oPPAnl0e8pi8I5ZauEBrJcQBHD7Cr1EF1fMg2YqC/bP1CTOsH2G8n2FOz
VePCvUARzPkQZ0KKg+HojWiOeiE8pee6+HZor0yvgMh3EPFv68a4GKVkoOo9F1Vjv/mNDNZLD5Af
ZYdQltgEmsSafWrhMKABZFPRP50GJ3Ww9Lc5/jaP3Uzfa8wV06cakfFOOtLzQvBwHUvNC9icnZbx
VotG1xTHIWFSlE6oWcXtIzzYcJasKhUhSP1CT6x2k7b3pbJvXI0RWzpPiTbTk5QK7CMLUd/AfmsX
LTTbWuW40pJkJukwyXRfzr7IVvyXJHDT36pZgU0LyIyduCuNpjDheU14ZGaiCSBquaT0rqqrCyOS
OHjBIVcy5DJR+m+WIQzrkAO5i+fbVePq35mFWkKYv8Zcg/PgXY1qdSeT4e/+XA4VdefSDq+A3aag
XbAYR2PG1ZMuXaBx1dgLkLdKCj3VAU5XMzA6XxrztuNZ7V523ZCkVFW40/RA20aLKdSJTv4Z94zO
1sR14Mtijc9cPqljEHpLLUmlGasmL0l/4nOJGYhoSEL1uVvprj1ddnhUucOjQjz1LXEZgRWJjNcI
6mpS/15PsyEpWdrU2vmfM9TMbSk0Jdq978kLuqjj6ITenE/PqdgvF4YKeCVmuyMpOvJOgsSFztPm
BAfl0UYiqYNrBb2TS8XHIcCyBXMcv0RaM2K7QWeaiiLv+IuJMVee9RSJbgOr4OR2sx7cqCKaNA2j
g1VL78fiWftPtjW91z2lYFj+k66UIZR75HXrFgRbucHfCspTta63aLC6wf2FZzcLvjWyq/6q1Ixq
mKfjLACRHDfINNitJhn4/LV0tHlGThtI1kajnOEfM4izIXPs+2ZWuH+zbHfzvSfwzuSkuWTP/RP8
HJBKgT5XVY1ihVIz7Rbh8vbbsBaKgkp8iZYLB+8HwSfuS5b36hTLM4XgHXytsvOerYAA7rMa/seH
5qYVuqCFCRhgmzihxl/R3bTXcoQH+lagm4g35Udycv2aqZpvGXN0L7PbWaAa13w+SdkMEszi97pE
j4gnzg2bBi9jQnbQb36Ntaf/c3I3vq5oYcC0hsJtPrmf4kqbaIQmYV99Q1c2/KQPqNl/XgrJISCo
qXm56dQGz+YRj6BP8GHKjfQgixp0CWDa4YC6PwvybDMN6LLM0hzfaIV2pb5Yj3H0vODrfQTIn6k/
BT1r7hWVsgk5B3ZMDuJssDcIUk6M36GEFA30VefrN9MoxoMG93e/tI1+Pw5TbYwuCf7X8HQzYygB
cCXfxM+ChcP86Ei8IASWpqRCMuHGxso2w5Xfwa7Ut14uMH54yHZvPEFESad8gGGG0oVk4wODQ5Ci
tOHfhpHozA7KN2j04OLewy4QSfg/+W3NmEtxw+elNyjtHeiZXV2NIsCB3zvuztzesOJcpWkbAGQr
wYVzphTQmERV8s8eTemI1OZa0I7zeWTiWkY7b3g4pdKkRTYUNtEJK3hud1paFwPcLA99hYT+C4Lf
9YZG189vXr/eNJ/oOpQDXhKxVF9rk7kNLuCMJNQiIjlN2XC72lclQLSSYjrAkCmPgJzOVe/QJAaN
tQ+PBlFNSVRYY/COF7E025PMv4MAD3KPi2BKoB8S3fh54+CvnbOhl+mRNfwAOChr4dvO+jjM3FXc
RHZPmXTsfJQvHsCqwqculvvD64LL1ZZMrxCa69TeYcPuwzFxsrVQ0Hcc2Qnv+Ak9V+lFBZVnmxfo
jHytiqzZ/1BPt3XIWSjJpropd4yrbDlGaIcmmFzaSrSoZHLXS8Ct2rxqUAQMx9Ia5u09Fq4coSF9
IJZkltRcKVnA1lw8SJhZGAtJCrcATvc0YzaKKiunuBJb9z55QBolwRZDdLu+KVyj3vZfu830cByo
hhdVLk6DhxoucYI6T9e5nK0Lu7rMfB9vaWN3xdsKWcYJ4FVbqImpbQ1fZlHrtJa28aUaIsWlQrug
0Jgvk9y6G8h8/KiejFGa81B3QkOyzVR26Mc45znTCZQXBJjLcYznPtBcGtxGSsIpI7iR33Azr9Et
fQkX1PmlaRRc+YY78rAZ0zXIxiKIpeggH1uWMDi6mmgLZ5GUxjgvKuBn+VcmAWix40wEJzROi6qs
Pkoxj/OPTqBSVBs4oCLWWLD7X5aZmgA/naJ5uF5J1Y6wUbuoed9AWoEoAWmnBA3h3AW0ZT8zF78T
IJmcX7cHmiTOOq/99ZcpKWsVSB8RmG6gNNkYPpqFvhUMmS2wvH5lDTEE2rvBA8X3m6wxVicEFSx7
Mhudo6JQOP5Jyv3EckQgnBBX1q1Z7wsdBk2Z8O0BBL+eLiWqY5IijEQmB2elcW2VysS8e0/g3KeX
WzHByFjFgRxZ60QkkjjvZGirF94b7MCf5ciXvO8zCkIyfbdkE6ztTey7ZZ5hu3ujoM1JBdlrnPG5
pvOGYkvT3FZtOJTL6Yo9GUBwSaD+gj8QLLLlK8lr8KMfpM8dihE1Afbr3Aso24KvFOLSwTJ2fnjZ
exjHRcpVCFBEsO5frinulfCnFplbfj2atF/iQQjjd+TmRzh7tiux1cD+y2I1hGUduwd5HSux3b2X
A0iApW32QjBJct8vA89P+l4npsIZPI9y0syLgL8gcd+NVrLxXAvcZtc2GutaOGtASaZFY7Vez8qG
EVrccvhy5T1EQW7NcmRAN/Wuliaf65lGffg7p/CMzrGnc4J1UO31vKvFDGmPiQTtljcMt+wO9MOo
bKC1/Lgezn6h4uP8PKlLtXF6nhb12kS1dn5CACrJwbn5Om+dbwO8W0awasvaep9u1MFiQ7WEp76A
eaqgJnThnq2ViF/OgEtWl8/3cAYDkaMxE6PzfzLF+IoLN1JDhC2JJQMUROHqI3RTZR9rweciJAVq
erA7rM8tnjo4ETq8CfVdRTTE2HViXS2HRCZ4QLf2iEbViLCPaAejESvOOGQfBz0bTEyJInvyqmzL
QI76NrDnjLln9vqQ/3LyAtI34LfnvGq7beuuNiVHQ9xPN1N102GmlaOqd0OqSI7UYYp5UBj+wFGp
bX1pIoeR8lJzO8c9YMwYLNBHAmZZqVCDn0gy30ff6sfkKDPH0COW7Bhv8BfdhAm0AnG63i7iB0+8
4PzOEMkApEQrKiqx3q0ypIi7d0rgUQ0Wl80DFxbhEbTCZuaVcpfjWZ5/j2oAYBLBaYgZg1s+zxGW
oS7h5gk7oxwY6piS2gpaOtY7n30iA5DOMBn7j3oNv/us2yom8nmCAncKKFOH6BC6FPHFUpbJ2N/T
dsT62CLXmvBbOE1IIHE4hNZZL+VCFqLtkQgAyaMZ/rgyO+bTVWr6ZOC7PcOCWshGjAxduUTsOTCz
ozURvHfe/54vXiLzVob3NMDWtEnLwVvGJU736cZmPuOYvLMyLoxu17nypD2lRfQeUk02MDS2e3J+
8U5P8b4StDjhXViLpPjROwGpjSnX8DtOhl78uG7NyawejbEl0xU2R/qHmX9TGZJEwMC7IcuBIkmN
VJjQBFEWGJXW6wSDynmvDH4GZVB4wrkrJs3sONWquDuC2Ty0ZtxmsPfVBvBnFbpAaT2dJ8N83HeJ
Yu6OWfgxWpbpTPmri5nuXV8m0iGNrCbmJWGQjnKw2zWBV+YmdaFCDDBpNsKvwo2zQuW51K14QKS/
VUBr4rUH8welQ1ysJkjQMbmX25IMxTLwvmLYhOufcQBPIywQKpIseCbR9YUVC+kT1gKFouy4oWkz
0JFCqmkm9/cO/8D5pGiEngda92nGM/sVm94GI1t+DFNaxq0vS/3hT0Ntd7yKd8VpLGhhoX08DZvO
MF2B8U3WhlCtXr4kBIYSreT/btxFFZEs0f68Bf4bKJj1orsTZ7LNdI009YzJrKL51oU9eWSwyuJG
nFgcZLes9Nl2V6+p7vHIbmV4vxuuWiOld4m7RUo1200b++X2U0ZOI0QXK8mCmFiSffAIWGnRuDHU
9fVW2uJoSP4jmoWNdCZ+LK127JXQWoK+IICPaZ8vi5XupX7/PSTvaxl5Dw/mx/dIWPkMnM38Cqsu
CC0jOiSawEdCdlmCOdiK7a2xVtsbFp4uNu63qgC+o7NAQ5/KUF0DIKtTuCJJYDk2i/X3LcofgM8Z
OhK7F+E/F7mdSMHcM03e8DHOj8JuJQFq+ykWM7GmR1iGUxX/DayIyPi7TeTOc2JyFxZUhaQLwkzP
iZ0TkgghM7H/DA49lZ/4x1aMWNetzaUMQ3X6exap5W9HX+nqgL7O1OSGIKiDxZ18KnF8EOZCgjob
CxjCKCd4O26Z+cIxoERyjzjMzC6C3WGm7di5AhyYcQUsoZwDG2wuCYOFm5/CNqprcpGV5RWPa5t/
RHOLkJJhmqpG6Uue2AQsxN9/gJD79FQmkYXWmGzr8nagb5z8K/7534BzjK+IngCqb1TH67y/WiF8
gnCoY2KuRAZuSrWoLxRGW6aMrsi3Eash+1+9WC94pUUJxACL+LAW+8gb2ik1IK07+DZTCYbXByXt
veAz96w2l5nAkJeo16GxOY8Fuxrm1xWmam/UJXGq5oS7VJWvmqn03vM3aU+n2TSucdgepNIYBbfb
F7mV61QoVcEK11wLVrWawpdRuo4hF2MGxVtEkVHJ4andZM15qmn//ymGeJg7ZzgsZDHUGEA8xHeM
W9qV1ZSz8zgSyQ9sIRnADKer84rhDz3bNJ9t2oQd2q7U9RZ0haPUTL5OKpHYD/bWR3wnar1WPaeF
Ro5PPfevTv6zXG9/3JKSVYW7dIBOVoZOT6xTjBoDmOlR6BjYqpADfPGcT3mD8UbyIhV8WOjctcBw
mFwRDqQpGCq287B1/CkRZm+9FST+Ua3hC6z7etHdOPKx257RHfKGZYCkCisaZfSZFFA1i5UbHiuR
sVnvoKJFNGLU+1jPzTeZHoPYseEsvRiQi6EuJMGHgWwlM95IH2yjAMlqooG8HFKluIUHgZdwt7Zd
Av+Az67la4HpU/D1NQZuDY9TfIMmD7L8xJXPbIjCAxmSjayre/2qU+q0EkB0uvBFPpt93b6fR4Ne
8cAlP/N5RU3JvX6VvWS66AD/kD51DkCskNxxiJ8xktIRbgrAtr5OazZz8mJN3dleBoDyNjizE+9b
QDt3BA9oDOLKp/2Mmn+pzhmLWfPDGuk3mBzm5kUanHlQwyYKLoQe2bBJAx46FF4gdmX9gRzwW6Yt
aH8+mDUhIv7DoohghzH4UsboHtnLD0XP/eOShxMVddZrfcplyKCBo07wj9oo8aeUVbKR96jNCh7W
4daHEgSgXO1n459IU28fPYCcVenEsEd5kd69gxD0k4L/fR5e6k38Zk1oPrrRl5pXop/NgPhaFTXQ
P7xpiS2G1ZEfxBYROgSLn5lH3DPapMkyQB+WpWwwzaItSNgPLVi35UhEkMzz59jR4GguNfTvSRr/
LZL2ikHRxhZ4n2Z+op8NZLmMd37+zuc7DNy0D7sc14EdOfFofWu574KXLbbkGGNVHWFFJrvcM+dS
e0D7zwSh44Es8cQPdwge+W/Qt4qnLs2Foox9j4AGMS0br03LWpNrE/eXjVjDnXmYHh4AR+okBanr
/YFflGLP9mBs5NKFdUmtYDsnzGSLMauZivKUw92408hf1PIoReRtgSOLgoAaaPBI3kZICyUMQNt6
fMNnoMUTmrrOMVibgWlbWyJFf3m2g7U07gkRO5ta7R7mKvWcDfMzQ04M9kvnNmWt647ZOeIvMoMD
AYs3VQjnALCb98Um5mPB/c5kIWDVifmfkQ3OAtgPgSINz8XtVjtN//N/u+iX0PNwmeHel+ialNUD
yybp6BuqwTYTWa8ba5JMeI76YhTSaFa0TypWRNI2aqhrrH5r5Pq6jR/2yYzXm17J6KIA+tRotnvX
TpcMBPMwmrUQHeQ5bUOOTVGdkotQG9Le/snBwgPMqk05fTjVQ5ITLBLAZhgEq9zZekQlw7kVIg1M
8IcZdt0kHet+hu3VCvQ2bBLw5ysLxAZxRRwM3U84GAarm9qkwwaBWGDGnrJujNejR01Ir5DMY+lF
vp8fqEYL9SzLaXYXWquzAU7vMk/CUd78Ls9UNV5fNgH2oMoEaNXiptUTqbafYEzpjAzuE8JsuT+r
vvm23akWwE8ZR8uTFxwaoycPfDpQXMrFDbSb/oRp1kSWNTEZVWy77+GhQNbBaToFEoDwapyD/es3
b18MurqhNUxbfdGaJX4iZ+r3pCGTDmu9aAfdOLDpXG0+h5xyDwL8sOP94q509dI5HMj+c65v6S1H
8ylwyTWcjyEwFMrlaY9ReR1MBm0CuByFNJ/2kXULNqXo2gWJTD5dZxQyVxqoK9u8v3NmxWgTlkwX
oWs3u98FJG6589Bny28kGNbxBOWXCry/PHHcbVZH/AGfr2XozyxwfGHmSA8jTOSRsUe4uctZEZo8
gINOnC5eHi92WJKVU+RAaG5QE3SY15Eufd/oWhTk+5bUwUcAViTeVwCpAInP5+VXk7Y0rYV6SAnA
UTT/1ntmMZ0k8CwG26Fra69c/BXk3zi+HCQcFYtqTBdOjfPoINkgOnQqskmPlMBX3apBeDYjoWKQ
zMwhUqSVgofBjSSjdDgkG1YDSOeMwL393Rhdmf2FURlMJME0YSU2DxURo2hy2T+InUqtG9qhhv1C
a0HP/4W5+qijudcEHBL+VrSIrE1BzYmNfnv0BY9Idcl5tldmY4JINq/yUpaOXAXHAwfddDHL7aX0
xjP07TmH2qlIV5n9HK2t1LW7bnbr1uWzxkK/B74Pv1irLZabqw+kLlukLSDt0dqmd9If/wI/2OZF
otVGF3FKHsjF3gf4ho/sm4qQtWymEq9f9ZhmTDTaJh6drsDBCyl+JFOgcbcI/CYxsknVFVfBB4EF
NfJTXFleRHmnniLQeuUJdcnFdKL57ZMs3G/VUiUUB/r8hPlomdAnM2j6+5FJuJkWn+GU8nnyWdc/
XeVBOBwa8Ep+87isCf0UbHEBWd72wd61tFBbrC9W0mEFgNpp7oarup1We9fqHDdlpuF5ypGRhP4v
X9mzKBsQ6fyIDc+BRpDNCAktFQfQmQWUeSGjsuAaEZpQqZaiUnUnBXpbdrweKlHGsLi8l5SwlGQ+
/mZyjMAXPUBvcgp6dqgJUrMPn3781QEWYZYUusdq6P7KTi3yc0OhY9m785yemV8QCQk8Er4uulQF
PXGS9O3aLurnLw0O8YUKEfSmL/bOwPLMgg2JEhLafhLrcV2B5lLQ9gOe6zqDRBhcKzJYGJMplhTw
Sr64C0/Wvg8UTQUbh9mxykPjlLidzp05Wtpa9CLqA4oG+p0P/5IrClsr4hkl77+3HpSu6SC6/wIo
EtBCJU7a73hE+eO/lfmW94DpYR+6YDtk92h3AEqzpKB2bXs6SPeDAmWCzLYaKUM4AYwB23a1QlwA
XaX1CLHqEeak6i7DxxSscvMNudm1fqLMHuN1QrSHHdTMtpMtEHP28ZNZQZXyZGMUvUiKLr4Cw6cf
9zZPoTxA4gCIBLVHhG2jxEntaD19iEXg785+9oNGo/ksJbRGdLuruha0MfZ5pUESaTJckrkuxmwS
trU4IuPyl25PqJK1PiIlcwEkSEPYhytVuqfPsBh6oGS/PveWB/uB90Bcd+wupqn18rmKMLWTQZlN
PYKsqqLphbq/i8vDXLtMzlALSZ762jCaMcYlRpUKPTgJtjlU3RABJr6FkueK7M0cKl2GpRjQ0caU
xqOdPKxjWc4htoKzRp7bzA3XJiPI9JVkqbyoIy4PYBoUvOsg3QwXu0VHG0sU8jDEL7y9WC3OdooZ
Yj7/EoVZbPG4nZotaioisiXtu1ZeHFabFxied72yc0Q/fZX6ZXPgrCQy6hovsWbFkKpSZGiQ6UeH
fJJ7rGH/Spejop6yfzfcv1iyVOBNvc8rlc00Se0nBHkwughW6F0GEdKkRKVstqK8mfXYzvjOwE/e
AUi7tZAKt2/Pk0gmVPsCx6HtpnWFEH6o6muQK5ny3nvfCv/SNfr3/Fh1XazD9ddRaplPP7WbmgAP
U2w+3UcLtsiSAqt2Tj5qP+DTPVyl6pmouiaZiw8+KVJmoCAX88bvfFg2wAiWq4c3mg1lHLXyLPq5
01hHRy7VEkzKahlYIoEjJBlx4G9FO1ZOcC364d3wwhBBQKrai3azH9wPYHzzKNYq8SwIRlkQvFki
vNdeskdulUYutWKPtkJGeaRBSxgg/NqxiPud3AjQ3jbFbbcvjIfN1AOY9RMW3lEPiZXRYvtHrtji
Oq8x1e+2zqVYEXEWqE3gFsQCiMqyEwcP0/FkXeHwSE0D5UDM4YtbdFEsqQVJyqIlC5SO3uNV/yWy
QY1EWmeahmoiZmScC2KmtYzizHb/TA3OC+QR9pKVwAL6XO1UxTCtVe5sI+WDYYsNuZwwaUgzOoVR
HYivpKMr6mG+KKk78miin4TqlURofOVOgO/7kFw56DZNamUHYMzPbKTcR6mqqn/ZxA9HQICRmhC0
BgjYGKRlNqWRk7fEPxLFSc3Yg/zFN1xFQNHsqom+ffziWdrcJAQlH4nbDsCQ3+DIYy18UJwoKnaa
fUOQhWZc+aa77qLE1qGyT2HeV7KCKc7HJ6PgvfbU+Zy7wKsJHCCSyS208v5F+RLdHVfxjYbyZF+X
y5OKFjx3Pr5PP1MgAmqleFO6wwmAEgMKUPsE9+2qzMxzQj4m3rPQGCmvjwt/xHkaJAP1fk5gOQ54
MrhKDLErPRcP1LjpSiC/x45ezvyVRDG31ldts7LK03ue6RtF2TT+mIgCLCIhN8i1MMNSAcfEdnkt
gxymxLNS6fvJkyslOACdbbo0ficlYhEYIzRSkE/K0U+5TlzX5xFNEwtjmvcu0Mri8i95nnEsvr8c
D8mTwNru78Rxe7xpPBVAcKQtPKCqNQBJamIsDHlTc3GBYNLGiIqPOq9d54ZdChJLEY4yQU32z1ou
C+l7kU/rsgQFg0z5ArCwFPlKjcGCcrLjjGqQOTcnyZsKnNIrw6HAwjuOwCgzCtjb72A3t5Zhsctf
oHXUOfygAHs4+GzJSn41ZyebNeWjo4QpnNhygX3o/KpGfV++R/ViZW3dTlU5I8/N6nGUtfoLJTxD
6/z82J1qIxmWP7+ExRC6NIeK4fxt9vEBxUmWp06hxcv6f7hB7/FsyoA/y/k6pPLdpmU7GMikW1A6
cTrs0/tf49IIokIM2GlNHWVFgp15dj6aV2R1IK41rSG942wJY6N1Pbgj9dsNzdtasXLIoq4W/LJC
sJgyUjlPwvjHUIxKQgZo/ubDA/Vu70vkphvxkb05spyYmns3UmcnbslfdH+9kWMwQD8jgKRJ65o7
YzWg1/6UPHzUxeqNOCg+w9FRp4LBM+krp+ni0H06/cBFP/PcC51UF1CKj28qiIfQw/c1oOb3Rlk0
HoobCmlXUjqXlCJ6aGrOj6Pb7pCL7bYnSv893RQ93SH7V+mQclJAkNfikzQ0uY2SsnI65vD9KMKT
yqqqcu2Gtn4BvbZiHMq+jITEKuGoWfKj+ZWNvOKoL6Xu3yvQF69bELzNG1Ze3SU5VyXabaC0/gXS
HzyTIZ0gshhVhvho2xzBBEpU6WdTQFrWbxEMVUNDs1oYMk3aBHUEv+gpi/ExEV3uBiabl8y0rAQA
TphG7OIw1cbdFe6Dcbl8OBU7mvH0oIO6zevseg7rkb8lH8kF+gIVOW1VzSTybXPZ3pQq7sjca0ZL
DaXFJaJ5KvGSTPML7GddW76GAustVU5VWtLGMQhOdbQ+9qEEUdynCsFcAW/bEr+tvSD7K2IAZUn2
cahKM23/zxANFaLvh361v2iUAfLODrX7kUH+O5z/ePyUv0VBZFdKqYuzK9x+aV8EgbsrWEJsyJvL
PoL74UGiXsJB0SoQzfxlG+NwO7jJ52EH/EqB7YtP/gVMcfl7+EcoMjm1ZCPFxuDNDu0XZ2OrFFBs
rMDaNgqrFpkWNacSlXN4weQh4+VtlyujR/onAtHbBiYvw0nI4Dxb14jEWKPqKLMmbsmI0LxNBXQq
PN74FoCD/fpc6Qb+hWKQzgA6ieYyIhExWR7T8A8lJEw2BlLPR08KaeXuYx5AdQ97CbdPE3lFgGDa
Ax4zG090TOtw4Sjq3/8Ji5fRMWxwM2hCQfQwzcHBVTcbqm76VehUvQZfBCuC4vINZjK+kSoae1kp
N5XOgsX6eE/ZmqAKPr4BbdBtO18kInVNglHPXQxE6HinZYjeWL/ZrIJSE3JW4asqUzOfMChEJn2d
z31EwdMzLig5LrYk/F1CIdXNDnXw6POpplZ8kroW5RREd3iKskKO7ixkOJc1CnAUHVkFr1Uhgltr
jznOZ3DMy/yk/v6Ueet5JKomLT8JoiKWqd6mWlHOQO40d1DogVlrOqPDASEATNx9oG7I4TAZR3yI
70FZwRAaJAk8x94bbQfS8IYOBs7hZYLW14QgQm0J/qi7lGdAF4PHUixmDYygNbGlyERNywASPRk8
fRzISFuXiJ2HfaLsd6omK0XfTP+9ARyi4L2o1UGsU/QltndW3rK/n8Hlo8JYKLgmIsbCqsR6cz/z
K11YSAzmieVb5q8ZtEv2jAAoIuNEesMnOxLeDqtG60TNGyoePTN17HzZKhpjeKCq9jNOFr30gELC
4eIibQ+PbklDKtRWwTtYwWgLx2dSuPmtAOYRsdwTva8mwRCtpDW/Y+zhkS9fNxhzmg6QpUZfUlzl
GTmy0xy6YrQ1Rzd4QnQnYuIRolCNGN/PytoYizpyJx4quO+MOTLdn3ubcW6taNoFZp64rXIGkY6S
mDAcK1ckAEbWfR1TXRcw72m9XiKRIPxhpqcqXCyg2UmEfX6nebTaD0TM3A+OcNh6akvVPwavvggy
6xFjdnBU6GOjyWY6T2YQnnt8KRQcu9YozhVvbzEZGY+7b2DYz56OIUxAnVXJ43ZOsV/d19+fzctc
NuShvvzSW02uK0i9m3d4lUy+Oe5zf/54Qsfe6WAOvKA/jHGF26AIf7t8y2lpAJ5r600zyPCNbHhm
wjJKVfK2D24witxt5VXJZ7CGBTGXLoVbvEcp6KI6/zeUDEtDXca4jouu4ZyELHCWrmJUziWzcD60
NE9Oj3DbSPKBEaGUBlFdSeHXdanE3BHZABk0R0MeDWHaQf2DNGRzsDZW5qD1zymPICLaTlurW69R
+FevGLaZfCMhc2DFJ0lJIPegZ7Qj1WKl8k1hVjy9YZLL16O0uZ7B08JuJ0HYbPKAC1iC98Eo2Ign
j8EIhBDTbxvmPPI380hwqzYox2KGUQ5dFUXGVUQ+f+RkYmyBbspZc93ttvOz1WE8UGhyCH0mdMuy
vqEQltNiyf9U52utD+qICOnQ5FyY2fQT6+oeAIG7QHfDUpChPmJS7dCMbd3jt2qssx1SEw4nnEKa
1xmTxWPmJ4ws7xJ5lU9bFKmY9egD2ah13kQtGNBIxOOXCFnaqUJPEzVA3EtphekVO5euDHOxf1LB
SsWAm1gqdC6yUEjg9/QQyx8jgd+krfZUhpZ6g/HJG0JxQO6RGf58n7nKsUM5HVJg7W8bk1K702Z2
yUYbyjANqHPovEormnSs5OE0sMgd27/Lzhfl821TkGycBstxWLr8CyBzF6fWwyiic9+wMwNWl/Gc
U6aKaVZlYV711hzl0QGcG91DINR4jPC9LTBACTPX1zjUN1eGUjK/YX2AQpqOHyFXyXDRKCy2fqO4
3eLfI9SJ6FfRJ3X16PChroW14LvibNbz3jdsEUjjGfRR+xxit/lELSKMjtIcZt28cHF+dIo4YSFY
YpsP+FxDj22qsLXXDkpFChtkUYPNWxJJFCUF7SC6PrDLjGmadY99casjvATDwaaYpcZcCuWS/xgk
ZFdsL31eZbw/JqcDXxxv7pyRF1pht85sUN6nHZC8kJznl1TnbYD1zuKDJU59ONzugLMPDvAYmf+Q
ADJh747NNI6wto5Y9IoaFgrggL/tOCi9Q/C4dMAUdUvSUdBi3BbHkuevwCpBAqCurAErEyxVcNqV
i7QriOovGobr+XIKyLWbh4pvAUby6p3M09CySTPRL741JubajROgytQdhn4yvux13g2T1n2rHcp2
vHkqMr94LMVsYtuZHztldBcZjSZdV8UZoulA5ZqoSrNp/Zeo9B32Ge6DFMuSkkX3ELCmv255ip4l
pkJUhRk29UyOuvwCZYjR00cJQYJFj/MTRchyIAtuYCy01Zhho5EGVWDYYZHJmp6M1KXGVGIJEuLf
/FUgnGjMHHYS6ySgF3YLXBzLSIaK8DP5HeZqXvunSnPHDaa4SIuGC6RfvgVldEAXyjfXmgs05WeS
rkkmu2BS7BHQR6xlqrJHWgrOzUhNpNwjt9tjlZObLR/88F2YU7qtOMS116A8zLEkZ1hcSjM2+H9S
tyvfp+2aYFquw6lr5ig4gVIvg5ivU5vtbhp6xr8jtRf0wi28ERcEbN4aJlx72JfKeCi2wlqw3Az0
0kdDgM/GuS8Ih1nKt/FrQQO2kncttULzJG//b7zbFuB5abpXiC4Ll+1I4qjFFieoVO4vcMw53AdI
f8EZSlIijaIrEI1reQOTPPgtkhBAgQOtrLPD1ftRFTW3zKL7taJOVTNikrcjHY7DpBiPpvC6GQl+
UnRU+eRCzJYF4sR5rR/M4bXH+9BkoeL0PCUuIfOa/cfb8DLH6qddEnyw7Yd0feZOsQltQcfkkOsS
klfP3R39MHJIvXZmdYdmp15gti6DQfcUeGtDl/m86/kFIwnDWmqdJFjSSTQ28xCFAQM2YCyoA5Qj
8jjz+sSaESPH8ok94Q0a128G5017AAH9+XDzRHJpNC2yeda7pGnV22uPE5ELNXs8GR79pQSG2DJZ
RKtFavQU6BJkyfB+g3Cwv0di1yoVrdnB9ywjp7kkizw+LxGUzrXitmvqxmfB5JaWiQnK6pTQNiTa
kgnnUjIz5NkVCykPlGrHTZCfL10fWbH+rZAPzk6qsKK4ttF7cCmhhM9N9+rVNKGBfUP1YoLRmCSx
O/rvZvD+doJNbufeebe1IDmj3VsJ660othwvcONisbyGDkPW7gHYB1+B4hk3glz/0T77Eygev+U2
e39oa1FsQwL/jmfKZPWK+HvgEVi+L7bn90fY+HCy7q4CtE9VN6FsZv8ufrSXtd2dkPqj1gvoab9C
b4RdpOJpvETa+HZY3g8+i0XjfGaCfKn1beFyHSPlU7RFqre8ul19HMu/tCuxekJlDlcF0emj/HGr
O/yvpvEpq1nBLgO1sxLMs/rzkhj5eArwSpIlr0I1h4Tpu7xP+oAoI9IQPu4ZUPEYCE+iSDaIX+VQ
RsQlkRtcacQ27he/cG7Dog7A8hlyI9t2vKuzn5/0Mq+Y1nboEVDt5XOp7fjLHa/JlCiYF2/fbQCR
m8vGcskVl/EJIS6rrl12yyYU9rs0VjHHMdBaZ0ioAmsOKnGvs/fyVYQLSCgIgVR5Np8utGTQ719R
WYc2S5BKwcx8eUc9zXgHye7+8kDPNpCy0kb2ltZd1D9eXSo5H/BBGYHG41T4/1zFVTH88D+ANkUi
aSvKcox9pir6QPEeXIV4YtgMKuT0K7l+ckNUWGszp/uPl68tHD+bsgsb1fGz3eYNaoy22OOM0QfJ
uvk/t+wsaIUV3xLWwDyZIl4dl7E3oxYwWi57p/jhwh3v8jQriYF1IOCn2HrPIV7wg3YkpXCqMKfj
TyHqne15km71wxRdwYjFoQg2XDHfjSfCoLmgyPxiD2Jmb/OTDpxnQL6pUgONx83y74rpdPZ+COpv
tsX/IVZWzcaK8lv3v+KIteTjPsvN5fTtEaXK6OcgmLpLM5MqChJzpwrKj+2K5M676dsSIxb0kJeQ
t3Vjk8dEVXOq4DvJcHSDsX8xW2/tkErCk5uYM/q7tnoXGWme9a1lRPc1aJr6maSn1FCIlzUwb5Ss
TOLGQ/MUFzVC+W2lHPfa59r7pgg1tbzt1Nj1/KeIT2c322bqvYqKoEUafI9VrFvP7u1Z1TMshrfI
VldUqUj72OUV3XIjoM4wGuIQuFylyWZtqbqG4LVVnWbvf4LZm8l22djK8LlXZLJktsU04c24x+/P
EEsIHEXYy4DltAJRjlknWSh1Cbtm/SS7vHD/yj+nNC9vKog1jvLC6IxfvY1tnY32stVisHQClspa
0VgkT6SKXJ552kTz9bbi1fWCR4RdM/LgztqdAh3O7vapJDVXeFRXlpHE5Fj2PZxNRUQzNqVGlN/U
r7kIfksO/CAkVD5pwGNlLflHWbcqvrlpOiwSMtGrTiiAgf9bqHCVo24usBU0dyDvkz4XlsE4i0tq
AxPRlEnLQTBA7f4P6tDn0IhNFNivhTuYnWrTcocUqgVypp9OAG6mXqV/YksQp+Gl/3SPbctffVop
ozyymZlLhAyr+aIqVILW7rLnSqDpRnNQ3KiaJ45TtXr9qCxs/anSf1StttWTj2PxzUPbjQEq7Ooe
7SLWATnBLZtZKFILe7PdHTwNgev9dIEOnbFe+UUjI8TABo1B0xxXIpixGrdVnfZY37LQyCsUMPbI
fNYVHt69LXWErRPoR8qgcKBo3R7mAj7v1h+clTVd/qJQjXhM60k9Y7YegpJdIdd5k+2RxDu9+KMd
5aXpqWGE4N1IepUGVM6/ioDA0OHDpBAdQ9iSvh6Q7vZpO9DkOOiQDz6a0/rP8HaTYxz3YcilSjjY
pAx4QUsiuHRUi0KogLZOTeOP+gNh7fQA10Jdb7VvJ6Amx8CQltJQOb4CYzYJkWAt8qfaplhhjID1
SzxeD2AX8bt6Av0su9vr2h7qzBnDKmRTvYqp5eWkbaQD31hCjDotLR7KvFEuRdW51sEJ0FfpxTpj
yqaapc5TdazzAxXIg0zXI77J3ieX01S82SwxWkQKFsDdXk6ORNAzTE1AIrA13XHa9Yow9V3zsyLM
IRQKd62lNmYXtCFC81CNjxpSpeFcBGV3pZgSON3aZTairMk3W6FFrN96q2D2Rl6cZJfsDR5E+rua
K+V0BiClEPj9xRo3WYC/8NApK92I1HmUdzrQXQpndtj+ng2A+w0dvhFNyWBMBXsM6FUMZZIlpy8g
EBiVxnaRF7s9zeVV0pnOgMNxdKRG09Fa2OdnZRn51vymoDfPtiZOG+JnaEunlfQn2HfWs8GIWy3l
9gpDRS+OLLAB+T+bmQ8W64EuaGyV4+dS+i/Jz9yS3TVJUGLOxoXOKc3zdpQe4ZyvLfuAjE7pKpdo
AMNVsbtcB8kJvMuueGyANfPXjMn7lYFx4w/g3icpYZUWu+Y95NIeiWuaIDJAxRvQdeqYQ6h0Y84n
9y472OFg7MVP3X5CfKc0rpW59Anu/swefkPBD93oeEXTKda5iT2uPYR9hCf7V2X2tH7VS6fYigZg
N7SS/vY80VS1QoLTLSYkqRKr/Ro+vxcsqPNY90807Fp5pGo/gyzKi2ukwMiwDaoU4+hs37U0wBT3
2qEOXJOVjRDqFTCvJhTI/TR619y+bcIX+Ujyd5smMY6H0y4pJ9cKcE1IIQonuuF18LpzEBsKoxh0
3R6s8P1wN7wl8tZ3Sm+5lXeITfXvMn+1ypn+oyomoItLhoe0yrYashX7mHhqaTkfMUL7irh1jbXH
vwAO+8EGYaLrfHxzSNrAsZ9SLaiG6CsVf0HNJmrJRiz1UVGG5S3JSaAZfVXlzMmKbJfcPGD+VoUx
eGNDEKeIrp/jW8PQscsOH7lyiOvPtGxeLrSh5CsZZ5YVjVJTx9WZUDBgW42rFU6d9rdUHeVjd7T1
rJHKBZBSohU0PiIBIndVNCkiehWvBjCLvnpD8h4NtbwIeH55fqN6OS2AuRp8/0v5vMIJ5N8x1fhR
8OmjycuDRRD4d4UAgrSxbXUyKUIO16ZUwkcWTln/fUEXT9w2Yx16X4RjOtANAV6kAW9hZ76SFVOd
eMdn1VWLalsD67c8ZKfI4EiOXXuATWjEKRko4yZTV3bEk1E3AR3VcOi0WVMpCyNmnsueE1zoBOES
cZEFzy8+Ms7ai8DJ6xZkuEdqdkYbV9vyVigMJR7EOx1fdeAXIiOn6fB9mwO0tzjlf85a6nmrgBUm
ZenISy9965JCh21VZzPWg1t2Bq3VDvf+JlRo/HNzsWXYE7HzCzaHjKBX3HSZl634KbhUep2JFhO7
loSYQ3yR4QYtkk5MDTvYfDocvEBaII13UqHXwOc52YMqp4LVEkk1/tmkHV6Ma1sDstBSv5qCJUsq
a7+d9zfEy/6OP1apYMpgZQBkXCIgH90Byl64ug3YFRmovFg02V5BR1k+uwsD74wneH/TEVWYu+h1
T9CXZ0inLVWca7fwecZFUAI5U+nS1QfxA+lFUWB1zqRTIgMJ9i2bOvD2xwBjHUOL2G58UEITPftR
2/IibYv1xxQa+ulM9UBDon1sMoP8QFgmd7MuSCcieDWC1TuaNqSKApB+K8NeUhD7CVl8haldnI49
f/tb9hbrCWG8tvTd7P/jN5p1YR2SnadRvLm2lVmlM9G+lqCC3ryPfYWlMLOWGWvPGwk61BaXKoSv
JykS8IuU2bkDKY2G0C2L0iPMz9hUjiYub6tsGcfCFprDewrgIY43MmfUPGS9payuXQI8A8ToNz/g
AlpLubdNZ5zBxsB4itp5biM195DgU/6XPY6tuwv8GBZ1FruUpeMNn6gHRqb+B2893qXWB544OmFz
uZLwkIc5E+lYR5vJYVpmD26oB5lpJr7NrUKubBQweMZztlFHtnjXqVd19sexwGOplFRUW51F0MrL
ffsT1km8OXPpGHkOCcUOU5TU/8+myqNKsNxNMBYXiEnQXvHnBXB1a/h0afL2FB4018MggmS/zs0Q
M9eLF/msmmCvdpS3BvIvjeRU7Rna4RL2O3mHyII5HHfKs+IoBO4JHQ305m7iiMSJbr3e6khCWMak
pAcvv35TbjKpb7YO31AQP/xk8xgXwGib6KisNdTgQ/FmHypgQsaTlb4WZb+nB3J3NnN//iApnS3i
mcegl+xycoEdvr6HYLASDiGaBxH/a0UzZ2Kgvdk4vGIqPyIDWpGCWEpAWZe8CXZEDYzzgsxemnFE
GVr9DRx1Kbzuyd7M5Oa23X6KyRq79Px21hHPinSzjzwfnmmkvTuHQnewXpT9/3h1AErNCuGgrDBd
PpWwgCBSCQZqgkmeY2Pp/CdEkoGgMTYp2lVSYL9AyZaXQdkYHcHqX+U8jTtBYs0Y6hX63mlSrxlW
JIi99QkRgXKX53q1zstaP3cdxAI/v08qgCXMIpiYaR8C7B85zdYL4UsdhW+0P5aASYFobO/VG/6d
FgrEsG3tYgHLKeOf+3i4baakVnKEmeIIToH01rMA4Cn1E+dH4ZOSx4Qyb2ONSevXaVs2ckIHcGPs
+xfUkmakGB+jNi6rF6TZp2iOvA6FQJe1Bwk4zX5dmWvRTkmgGRuHFa7hLwTRDpmUsHQB7fRr3Ha2
tzseLALcsEyf3ovQKSb8ZNeb+byosvuMZm9cxUpMDOijlnIrYWn2dM56N+gnGu27ykWHalAwBj5S
UDQX6KeSHr2sJmL/RBGof1RYJurHjCIpPv9TwZdTQiJuBAuGCHPRMs59x3OvZ2DYb8x2SK9hvGKn
ny8W4CF0TLyoeUCJd5M6yjeAQ3oHv7XnuxEyUluGTI3lHUcYxENU2XZLgfZVpNhmFOXUqyT+9v6B
M6L4WUPMQZxwLPh/+zWC5+Ut+UxwKYedZXhyTY9LA+B2wUwDPLF0Z09MLzPHwrY4eqneitYn06A1
TWN9uFIVmksYcCIaW/W4E/tUAt1ZsQLJytZ0seLwTZ1P5vY0Dd6OM+Cxlx5fdwDososrWFHQw+EJ
8m8+nyNuvizUI1AiPkRO6/nkxL/qHccOJn3VuYyisc8P2oZFBXVFC+rkmtOB5npjbM6w69BRd5PR
GfxcWpSYVimpBsC5etgoc+B1zf48P7+WeeQJu4UHp5MWv1mQF6zBBSqYUgr8dNeiTVi1xZpa3uuA
NrJQffPQ6AnTCpx5a1SpxXMVNwZa3fUwSx9IAPgLRZ3rnyyH2qVFvvPcvol0JzHn7dNVsuB6QsUu
SOVZgfxqvFVajuGfm+4NzvpUu9QHcEXLgw8W+3EF8j21SKJyOqhj6oq7hhbORLokSY0EuAutdm1J
pLOcuww6uzWsYyf6wghkX4vHgmKmtApGq54hc1DZSPZXpIfqsw9YM4j3IUVvhcE5inor6OyZ+iFl
LBKpJek5M6tHEBhP7P4y28RMr7YG9A8olGoOeTZZAAwjQeM61VrCxCDnjHaboWGx52PQHrS5DwTJ
ueGbGQLpnfR2DGQUVdH/ixllwv8eVzEowDFNNvG7zEWx4dC2mB/3KIRtuL908YPCuhQ8CpIBGfVh
R3hx9h5qKr/RLCH99rmFyoS/HX+tnX/6sPY2bQhNyE+GWrExCTuegYhdH7sI3Syji6RBg5fRyU+j
GxqZCi3QglMtp6jwGXCbAUouhhT8rh0oujlH04UtJuGvlL7Px5DJzj2JInz1qnz6Mx2DFzRq8qAP
qoTbZcfwvd66qfqE094StrRZPekmwUVkkS+1PJmWeZJTLCcBP40EOG7PYxJPF5Qehov3qCgIlj47
8U9GTq+A05+MwUpKTxA68dlEC9rCy+4qYuuc/B9lw+9FSCzzNIEFvbNBBCg/W3mvy84I40l07TT8
lq/LFSo5/qiQTwitbRsO9Y4bfZhcRm8CjU+gUoQJ2n+epjjNNOnUSciHqwRWzI05iVv0L+cf+0/U
MddgIanq6ov6qO1jg4OMumzD5/131eW7NYRRJhgFMufmUozjFWB+Fxv81CuTN24KFS+swe4FbUxi
Bn5PNgJmQKL4fdsxzswEOLL/rQJCDjjT1jERLL+VrHiDxyXS8NJ109Hz8o4J+/XGSDVlehrPUEer
JSWjhg49QPLeSmfrCxgvPDBQmZpzi5Lr6XlRDLjHUMLg3TzXL409T9YbDIZFhT2aynXFtuxGPtgj
f3+66YXJJ4/AFwgJaU2qF4KuHQBMjxfS513HzzkRmLTuP4RaijE6yx5qdBkn7ZpzZq/eCermee2H
AxD6Q3txA8/rmaVgAgqVnIUdDAyUgsRdHqW20Qj2ChvnwbAzz62FrCweeeUwsKqvM92RwLa9/phl
sS5kM/OYsslIohkkUUnJ6J11vmzM1WD+sq1VqkkUUhGv9E+4RtNxxFWcnoIQhNOQI0AZj9gfdE8f
3YEcCB1zfAEcN+9/hslsuA0cp2zhjf7cUHcxkVxL2Q/uTorP6XJrBrU8KdUwCh817JxT9ySSHLtT
CAADj2rZHmuuZYas7pghHX/iJhNo8GDfAEtb6EP+RwLD1jpxyXuaM7OJQ5/c1XrLQpJW0lEe2ofU
05TQEBnJTGTzIisCRE7WQNB5ysa66kT+QziuRuNJsV9kznfqbn0BOAUaxRjPIjoDPaI5lXd9rEcd
6DzbZvC+f2K3wDpmnxhPMofMTpdQf4kcPiWW9fhQy9Y4e7po4GV7/NKZKjSVNxQmhuqXBsd/X9C+
+zTuwazizDB0A4lPEM/VO5xo6il+2Y4DUxHEEUmLFex2Kn227pfN9bXovPe/jCnJ+OQT4Vrny3WX
tJTTKFHAT7kPiYrebCDiXp9e4gNu9hhFoeZ4hlqPmEAed+vw9t77D+jwAg0N2RTvONHmYVjsuwaV
ad4fSkns5PSZpPDLu7yB2UF+DJC7h5KYo+Adhw/bLNcaS8qlHfilvOfH6ZNsII+SzhvxGpGsxSPW
0n6xAJpHTrMyBsucpOvqTKGap5p6uYoXM0oH3g7u9oPwCBK6OSLtT1G+cDOqyf7wAiGcbsF8jdcj
pn4VUu0lvdce1O0OVuBij0tPbdQwb3fxxZ8SaOgcHr+HefyJskaJPw5Dof7wQwt/123MtSX2l0U8
1McLC29gkYhPgfG0NyhCzMoZZhG0Csrztfqj33Thm+M7Tf434FzJkODicABCALPyxcm5eE8TH2Vr
vO3TFgUNgQEO52JWWqkiXO9gUidbC6D3d7a+n9H/vaF/39p41Jup0H8l4qYs9iTcwjI602uZmxQQ
zrf0QefirX6COmVQbO3dcz6lc1E+RVF9CPCUdLw+gnqEJHbLIU0y1/g1w+5cBRXvlfsj4nybSOqg
erEeihdOE7Gj2jsVHhHZDmRDzALFxWKOkJAbJaBgDcm5Ik79A2S1ihHCvFgcsVCq1ZBsNECla0BZ
jq5FOGksSniEv+LxZsiwqHbwjiPaz/scAh7xxfoCY0kvD84DnyEuAD6j/lJCcGuDnFJ09KVBFvfh
kHIhf0kxbhu9wF3pVT7iGmIc278mAZ3zvPMo2bBGyXEDV+JMUxtG0kWmIyK1KcN4vpii4jJ4qDVZ
YjfT3eMqPp7lzhczxmYr9KFpYHcj8k5FxSUvs80gAGZKFNzxvQfs0yhcD2mJa2iyRyVO3y0NTGdL
YhKxmmw/Pkvz7WZZVPUJd/uisSRU6G36AlyXy8YCxVxCgb/7tyc+F5kBKN77LkS3GgMpQ2LVwIaS
LWVNkKa1lBGpmlIV6omEB39uSufIbhYruUL+L3DJClcKcmb0M4xGS/Rh//JPHee2jx5RI3gDVECt
Xg5tI0nnDM8Cjm7nsGny7ntAuPhzbTVwuCytgvxwZtJvm4SNnwfevAw6y27uAOaFCVevVGd/aVTO
xz1XhzafB5QJRZ3nJdXlZR0NqwPKZRNgpscs4rLNrtEcTOMJjxdAEriJTI6v8jdn1pOc5uCfGwAQ
lZI2e2OZuLwwq1qMtBrTvzYNyotP0WDpTjDUp3nEp96ZiS0s2aeG8O5HSCH1TUoivb/kKMrsA+4+
ErADqiRkKoMFspNOgYu7f2GlB67pdkARL2k21fSohe8OLTCSl44DJ3rP6VWYsuhwEXTr412LQG2X
KFL9GA6JbdUsXp6CmAHCvDLYjUStFX5ouz0zZqcgiY+2K+34JDiAKJiPCC38c5kv4RGWqX0/Q2p1
ELL74DnX9sDDhBaW1aL10P7vUsZbc6jkwsLwklU+G45/VfmU5itR5F4Fy4e7KRvAml7RwaFzdubI
wXFgS6If9RNkOP0MqygHW2Phn4mv6SUFgVEcA3yAmooqwi4MnonN5Z/k1fQKo+OcsdQwEzu+Z1Eb
jqMuLFPiq9PcyTZLThqecq5SGH1b+3U3JpB+Pb8EXIUlfXMv1HV7BUX5BdcBisohR0lqFrty70+T
qN02RjA9BIljNaw9NHfu2apZNqLm0BpHTyct3bSjp5PJqA6AdCup9RkdO5qRNuhwyg2dBVceDI+P
xH2JF2kT+TSepz2MhZG4llwmtCKS8NOPx45oQZsOsepM26hMXX/DLpDNaK2ShOXPLZE8dHg36jc4
xgb7yEPuUyLdU3KmhUegwZK2Ety9IR40tHWvuWWA1X0qJIc4CDGl5qLxyMK2YIyHWU0O9viCct0d
LLTdLbIZRwc92vwkA6cLuJ5VqQSdoq4JbzRdZvZMDDQDmEC8txUB59yHwuGS3z3fUYBrW3jSYoEG
9aJ9gQbRZqwrPFnCwiw5QgNDY7EoNBnqNgjyVLxOtf8A9PujgzwIu1ozb6grjwT/CePXwQlq72GW
7ZUGX3bPQPwyRC5soRH6t+F7F1pqO0ljlOn2u3FcxCy7cGlFTwAjgkzxFBgYoI79DPbTklkC2iZC
a7lLZVEg8hoWYGxV9wqbOQj0Vu/sltMrzIkxRh9wt/8ps6wG54WGyvCU7k0/u0T40uklGNIsg2LL
1Iw0I/EZh7MvGp1dMSNoIYJZ16C0TbfJOPjCaCnYEqMXMxr4Twj3q3xZVa8a4TLvBIadTWnYCcvS
Z1y97exEq/+gUhMFhBrAAWskrMp5OQ7/S11JXGaX37Y6kxKFjlBBFszc5SX/upnh2kr5tjq7QcP7
q13FkqwqvcuXHup4ObMkU8UxXgAslNse7648A70xa63t0IhyBhsSrAfmcp/tsFF5t8rPS1Cb36cN
kx1KInDi+8x59q3FHDiFCKXS5k9OtoHo+6BXwxqzYjC/gRMEZRv5gJ9xvEvu3POkCWuG1dWJaqYx
tjVoV38HJliycigCTbzNJzcwmmpfliaxHLMjfIEm+5IZdIASE2ANsA/bkxIYmyRd6pjNUkeYYJRD
v1dmudDgJjTcZTFRTUWedZpKspIG4/8Y2jSPp29+N/JNDpXDTkrh+IogZ/qSZI6iGmP7KZ2DaGZZ
/LrG1zAAwUyjtdZr30LiWu76bI0jEOClW9JV3CfONjI4dEx3Lc1FVzTi5S/zpgqQxH8r+kfzZZrY
9kxG4qrMXBzZuXqZW0i4xSiBEABtM/3pQEkBa6zP0Fs5yOtbfsISQD3TC3pu/rEXTlIbdJ2AtWUy
KKxLTTjSZUCKZLWLclEkcUP3Zil5AqwpRS1AdCNFJVhzn7i6M3kJLLHI6jrNfUKrL1cAl1GNg4H7
MFQkSCGACTS3jQvNjfVi0GNhhEv48BIVxDLfl+Wus26Jld2/ekv2y9R0eFPBEuzirkPROLKYOwU0
ons0KUURGPYLmOEqPpFfzpDLpfvIMyF5FBcIB3XuyPFiVaytpIXI06YZna93ozNf8APhIhIvZBS6
ingd7OpwpgyyVwTU/G/lIM3V3F5iib5xc6KbqOqIkfS85FaItExc2oLmMd2i6XvUekbsJAMcyZYa
wXZfIFdpQyQcqB8O+2UCssq4DACW+5xRpWZzLBUN5UkHgbOvP35SgetZiekg30IjY0GeENVAtURI
9vPuLGMmXr2eJhcau4hp/lpyO0uQk/yeLkRb+drlID0lfoTjY7nMnd/LheW09ctjhH3EzaA8k5sh
ClXpUzE6vjXHuF1PkZrpm7zrPu1ZtWXzkMDqTXbA7Hlp5gtTEIWtJJLI6RT+Q0UoKkLPOdTQgLgk
eIZ6/0Tti4iwHd3g4/GNKUIj7Gsv7pgwm6uL5oISurdvdHzYu3lf6vqEoy1wsu6xRgRnL2MRR8Au
pcUkjYygtn260H3t5C7HfPEnRSttWM6+05DSvq0sFPO8Tm1oFlv5F2MotE5r6mKraNP+1QF8clMj
98Xo0zM5PzqBRp6KKPjJrQ+T5EWtq5Z93hh1I3qupSqhoPL50hftd5jF83aCCGCTvDFeK6bjDVBX
nUyiUHRurD0o90NzbU4YZXz12fwG6gjrn9Z83eG0acmMTtB1gVudnbn5H4wPHNm5M2957sbmYItm
CfY1NvedP/6Y3x7w7xoFf427sljn9uWvycHugn9EumeVIjdaNzvynAVZTO1wiRS8AHnRyWVV5Ek2
B4xnf3M4u7FAB4EJdLOcbBjMXqZnE1GbWO6fcS4sQLzIKhFU3Z70cf/zC3vhMcZNtLchgVgDv8fr
8nVTkvbRu6XShyF0Z7YfnlNrJou4499vPI1cvEESW23lEqmE8xBraRn886S1ydt4pAb5Y8xzxC6E
8N3VFHTtEF76aU5Hn4OjWE6fHFbdxzZCDyKcwAQYZ19Tp9veYdgWqTk+OlXp/PgXTbVH0lF8XljI
d/PFHdqbplHncub84NxBew+i91YaAH1qkIaNJHlndVfBD+AeTRcCj6AcAssh9GIrpjg+5SY+3Gzx
6mJmI3U2VuwpRbf0T3okQBNL8+g+brro1Grv+nWA/YHVzwuRuFqfzO3DDPcbwKlH6LD28JrTMZ1o
rHsxF2YUdFpegCGTRRz1O1F4hCx50pxorP9tBfoGNI/6XfWv69e1eH+z/kLFaTlqmpAbKVzb/iVg
AYGFxQCoNuaMcubdBriNLD2fa1mzle6nj8JWvbY+AnQzGPFpvMevpuCrebnqmHqns+jztsCfpl28
pwKjvc2S+/PTdJjUxq2RNE1Wag/mavXu8aIeLYyn4gXpZTFscEXUvSEI07h+6IYph+d1ZIrWnJwL
dnAo2ipkieYo3MCoTWD4V77wEXwKe68eavYIVbdAEj8S9V2AorwfPdjQph56NvbaMeCA1DSNQtmZ
dTSb/OH5QDsAnwUD/eeVKwbfIzMkYFGsGZZiH75ra4bnqnOUAj3OwB35n6ciBcbRcsYHi/02Zn5c
iTqu0JmMBHQagzGIF9tDQiqAc2nujIiBYZ/M/u6dRjvbfPRlQuL2g0XSQW3l6/I2eyxYq/zvTg5d
MPrE4ev/RzDFBFRwLKuEBc9L2FkPKmp1OfbH11/CWNGl1uGWpdeKnS6IEJvGVb0VpvqxHoguXKEu
AoWe0gNjeZIfvkLqE3lXXGdKwgsjvHbu4uQZtdGhs7V7dcJr50gxz5KPUL+UIPGUcZK8pvN+t496
aB1XFUqAGNi31btQITPdHv2YRC67WzjHHDtD7POJxIpZjGI+NI18PODwXHoBZ0a8uzTFLZsQDaF3
EnQ4+2Sa/ye1FTE3X8Oe3588hWi1ywkpL8wbeLNlXgViRxJO6/NbhjkEvpYIIqilo5efKOyOt+cn
Rum40K1iXultJ0yqioM7Ew7ZLORtWTSCanV05gxxI/4nwwJMEVjMwK6nWcScuMxlBMzB7kDlOq+h
4wphu3/AxGV4GBSYrlITu/GrHL7/+0VSW/gppnxGCBlLYYq1YssuHEDiDdWq66holh5A1LT5Mbsg
LZJjrokqXdb3mDMp5ZTsr/dffs0lV+00OcL7Ib1gEvaIibJ+/zzeNM53NeOzvmRB/olZqk9fV4iv
bZ19naBjn3rwlM28vJZ1M7uPHIYOBjVpa/8GNjS7tYkmdpDlpHnsNvsQraZtVVmqmgRSqIz/+2Gp
Df9fcJi7khuznCbOpx6x07vwvQ80ditwG4I3VBTUsLXbmwNniHEN7Ql+/xmTQXzyjKfm/VfkYQfA
yoft7OetSqkFLwJaIKl0dGSG1Opxkyd74fMNI+rWdezFaPrq6WQVh0LDI5Mubq85+TEM6s+oqXUR
8qlQSRKOMtK66lSv+u04ZH1MCcbEPLJ8ktIvWk5LIwETEP0ZiU7uTvkOgIq8N+sUBx4Zi1HN1Kds
aNLG0UnVfopwt3Nyfw0Z9v2QYwmQu9m9P+NB6Zso8NO+PurzPbpeMwFAnhmJtpEC0iGq8CvMhaMZ
H7PM8ceBwgpddj/35R4zVxh4ImOqBHvPPtw+HmZFQ2vZYolQGwSbOk1cgm3h3TvMBeMq31gKSw8x
e9F9osc5GZkcmm4AkM/S2e6W9KBCuYPas2EeZD3VxBXagMAjyybANjZeC3WnpizWoiP8vWhWFzA/
VCnCpmX6VKrTuWERw0/2JaeUJ2+S6opEYoby/7DqxlmtSo7DwBGfboSxGtX/7t6P1eTBQkjnm5eT
qxd8jYu+sl+Fei9WXSuhqUG5NUQ+bJPDm1SoNhrWJddJjAXZ1yw4PE+6ITUX/BDsdRHYBid+PHS6
9gowhX911cRmvhO8aOXLEO475by0eyrFDL8DDkW8i6CcGepfBfoj69s6q5fkiayDj+9wCZR/VbWj
3HkVtRSX/+gi1Gg0qA3lltcghIaPuYlaz5/WzCRhVCul4QJlv8yx9dj4OrrrLWr1JCsgTzakcoL8
PBzLHbPoIWK833mqKXqrLuscsJOAlpIHoYXHvQODx3/0f59m6s3mLiOoy05HGNbvqYgrSQeEblIY
CmMDkvKkHCku63pQQNHKMvIle9uIqc8H2Zh6HseTYGqY6vqCPChU0ijNbk+LppyzKkDMzeP1h3e2
OWIav8Y+udLN4N5g1jRHQjKqCNJZX3//jtcdzDQYNNFrgzHP9/wBDrkifZv0DkNBJ/TCNHvqKCaH
Pi6zSjPLoRUrMyMqpHoOKyfvqxi6I2VgfnN8dLkLNj4gWxoiA4YEd921sfrDAOYSI9iuWpIqHM4d
ivKDckUCOyljL9Ae5gtfBGL8Lfbffa3MgJMp2NGtIxorjr82iOjRigvHrRq+l+3qVNYoZXfNssgB
dAiJNKNTYyt1Y4dfiXF0kQ6+MItJ7jKZTQ9xEXDLHu6dkCyj35LiQRje4/ZEYRTemOSYIIrQnANd
AZuE5svbExg8l5yV5i/V6kcqVA1+s2xyzErkXSYA+QRwoWcNo/uop7DTIlRPnHUAZh4KlNpMxTLc
/zQgwW0cQBAcT3ysi6W/91WtGOixNahm6IPbsAjOvE99L7HCHuWDzoDxVp+dl4XRfNO5MC0C1XKI
cOh3CDlpmvc5s+9CERlT/K+2q5PpvQUH9Mxljd0CTyKfmzq8dk0Z44SrwjH7CKpQuHCKw7nJp3HU
4RcNHy3OttaFooky9nyWyP00i5UlB25LtTxmU++g/GGJk2xaxCNBi7uH6iuJOBweSkD/7BFbptbo
r30LkVNnfkqUwewgrSqBZj/witrHlQDHTJHhHO9zuFPG3SB9xEAYjc0YJZTQcLpgrLqHG1x50sga
ePZFOy1Qq8EdtN2AzsymQ3MRAk9U1yqrBBvfuv9BAn1Q62l+t5GT+XTwZy9ufbzKnwjQhBIsWiIQ
tZAVQE3z3PQZzvqlM0irCymyy4K2qZ4z/I+HGg0dbXQ9wX6i5ek9+LBzqIHxr2c9YGerUemybu4w
j8P+0ejLBclemP2I9rxbjzCUg1eVr9TTVCQNsvbjl0clBmx8j8F98oiygIAj/KX0ZLHEA/EnkBiA
IEU3vHTqRNMPjxwfH/XEZ1p+G/LT5OMVi6pli1Jc8/2SwHgrgP5aV7mnZz49YTAXfkKk6keGj4Bq
U9XY0agGjSVyARQpk3fLAXGU1m67oj9DcDc4NJ6QdBCFSlPXBNJrWGC+QnGQBeqSZchMlFXfBX2Q
f+8IkJR4fZthlophul23IDCt6WdjiXqIEoCqiT91N1Zl6/Hbx/n9qxBU2C7+K3KJ3amcltrvfQtI
YMJILP5SAQORfOvCJAbuDqDQ9rduqxCQvGnUVj6p9S0FAAtlnsOHDodhFm6h+VgM+Jc32S9fbdCE
t0Y/lb1w7OYkYeHN+o2CIwDpdYamz86uxHNqBSHpyL2mUsrrdWq5KmxhyfdxB5cXBUOubZcq+HK0
bVSuYwqnE5omaSajleLQv1iDKi+rdsItfCPmJbJMoQLO7PYJQf650AY9PXWbOcinPXjx8FdDx5Eq
otRMAN20bYTaebAJ35f9roYwKeY0Wefk4Rr210D8dlE5fasXyh92lRHYUjPpeMv7+jAqp09S0snE
fCZMRh0DSh4wDO68YnKwMQCTSVDiPWjbK9v6f+vz035nLGpzsJbdidmpicAOwaU9vCZi6qkxq1nR
Zn11sS34OHYjVuEY/osh/N3FR6cf+H+UGb+5J+T86aKrF+0ZmiJTXdNEldQR17O1RuLvs/U58iqd
KsD9v7gYBHJFM0WtD1/C8iF0sqiSu846VlVAbaWdGjvGdo3FCYdxfm55jU8nVfuyeEsOjgBEC1wi
UJGhAddGjoH7v0cBWegfMRLrJ+irgQ5ht2sOEcoNa7VXJutQdMsPMpyivNXWjGmAdg+OtmNHjagb
h2dpk7rQ8RCpdocSrWqxjHB6xT8dr5xrcUmi07hIToANMxU6B6ePGXXCuGFNyUR+9Ff5u5emQy1k
v1r6rJHJ2UNn40w+wKFfz5pFie+Wyg6kaCNNYDfx+EyArnuKkBqc6c20ODC1fnoZtxj7k5W6aAFe
hDfcgKWyU2W25J7rRP+4uJCE0wyYsKb0sNBohQLrGiHBCS258K9+RbtR2WQdiE2eUp8eXfM8M+tS
jj45JpJ5ihR7h5VJYOAjGCOOyuXsFNbol59KT9CF+zwseRNbkK0pq8opVjjSSn34hn3+byYOXlCu
fApZrpJZ5XI5KeGOdWa2ZORzDCvS+pTE3i6ywPJ3aidLxJKqWIN6BN5ONvoylttFZvWsZuGiZQVz
UW4ygdDaJSuAz5rRd0FcRz21vSDBAem4gBW6h1vA1t4dRJSXbb7dPTV5W0rfnUqDuFa1V1VUpSDc
yMjHSSttEXIBg0BnvTUaemBJiLVUJh/jfy94ZQJNbed8c1uVkUC8yeapL4pdM2EGEzYsMmpp9p3Q
EuyWUBo5M3p6FDqP1gB3XIhc+MVj64udnuBuAYQu6h3zDSCLsAcWv4R7oVi/YCr38Y08HscgdLLG
AtrYHT0GIknQuB7B3OY4YFcH21f7KdSazIA1ngkIfSng+wuAsZeX+vbKv3OqNqbVWgH+vGj88ZDq
2PKQ+ZFGdG9SqCE5xKKbOu8bG7dyEFun+LWuWGRc5LsnhWB5GFoQer314pzULlCOTZF+WqJaS2GN
Vysj64cPsrkSWvYfFCO1/hX9sqM9C3YzWq/tFPO0XpxzQxSJqUJOWmvPsxN7M5bUsBdS2OzSivmE
oLJNmdIBGt+J3At/rc/30FtSnLAkBzzvBlUQ+C2/882DNxRgbxgb4VNPFdQ6cZO6xtRAaHhzXLo9
DJqFQLOOxf8/tAU8Uzn06+E1kL9pXMbGVyf50WsM/RJEcXlQhsdIqhpPdD9usg2zp7IMNpbcv6Rx
2DKS9boIWdlRfn/WPsojKmIFCUYIYjfWXI9yyWGqXC+/sy42321gvExHufAT+l6MmWFUfevW5Zs2
Z2ku/0XklX4Vxxi7esiSHJRetbhDR3tTT/H1cuKqehjO8qP0Wwl5aC6YPboKyvFF+Zelmtrm+n8a
UvGbI6qeoNOwcjjsgtZSfwM1OdrurjFNnzIHlNPopqoWxw5TNQ6o7PAFCvdHp3pPd+Zku3ulKanU
Cf7V1DvXXPBFRf0ajc0BrHpoSLoLEYy3jDS7ZqwJjazNyLfSHK+QksLydtY4P1SviPNxTbijt0on
kUm9rUe6oYPda1C9/DzqjgKXswKscDLwNDrpUN/DADOD8aS4jUeWyiUZyuB1ujqeYEm1HOOO0TVo
6/6JEjc6KrBiRvEFsvptbk5PN8cmj+siELzBILRTwP7faExjDspWFq7KOrF8zzhHY6yW1sa5P9EI
3Wkj1HDcGGDvy2hWj6HvAcyKHfMPG3n9OIz3YGEAf1fLIWb1/9tMYKZWnZXh6/gmGbJKJWemM7JY
+YE3tyLKl+Yx8GhcS2CwHjtXxw+wjVSLi1n0RY03zdAHSBRqG3zZB1DYX7H2nt6mn6oJaug84Wck
NGzUyZPN/rwb6a/28Mh06Up0Xc+BYGh4t4t6I/nTA2FZkKskG+gCRHYkPA0pHiA5HFo7VTmVOwRQ
AshUHSXOgCNWI9z0i+qF6vi6PlaQiPSSHCJWshjplDe+FCxc4tsJt06ML7Jkz4CgrcC4+WEnF3w0
QVbmXFpn6Y6TvZ6oaE+eDslucvrJxg1fWsexBEnXYKAu+w5YFSWjzAr3EIlzAfOqNiiaQXzPKOah
J//sDUHsJYlkIQmzzbbSNWQCZacLPrb2XcZE2zLBxQPvhliny4EDQbtWqsf95tQRftiRqM5eNjLj
XLX3jRKve3zqTABprNwsi+uo6mS9Zo7uqoq9Rfd4oWLSqGqShaCz+jd1BhllKKBKTe4QWWGg2HF2
pU4GT2Go1ncwbL5KwEkgxZCDJ3BvYoE0Xgpvtqo9Rc0mC7A7La3STcxA+1KXRqwEqYbDGdI1Dd3I
dK+Xs2nOrcX1CtrHipFUzDmPany5/Ywn3V4hfIuCRCGme0b0UQ3DhUJ6LaEJuiRZ4PvWYCPvhqbp
AEt+HfIqMlzeix50hN/CopDoEDGKIiR7Z1jkDQuhTlHXl75PiKWqm+3P2p1s4ZVijdMtu5FlP+zc
TVkdlUAAIhjs/CU3iEUfGeyqw6BNCOvSrabl3SuDDnJ2YYf1JeJrXzU1TmctA7NW9bBAF5IkgZMO
H0Pux+Ry76iJbnzKAKmwiuTHfTpyGfGwX4zTdxuWUh2d3B8LufAxH2t0iyN9u/hLOTjC1ybW3hgH
hLa7mUDZiuoZGEnuWJdfgbpZCeFKdwUE7edj+r7t6qDZRjZxKvx4uxYov8qvv3d2MB2sEhH4Sa28
4RelVGWimzo/5H4Q1wHM1+91GF1IuTlrdigXhfqB19bRMYrUnUBMRGwM/Z+K34FB1wMgfitd7taV
kGRsBQziUQexqTDoLimnAMgxffnocVyG5TBy0vb/vVkg/nSkYqUmZeUOviZ5OuBkSgPX/w7hdhyK
BgoEAvsD2bQW4uKBEWQ/IMave7H+t4TccEET/JulnAeYn3GQgo/M9f8ErTZOLdzcqokjDmufbcFz
3o83ovkE8E0GYGQmIfVNaLM60RFN0y6US5dNhCBVUvagZIrxU/sRruiDJrlzUGcEjHKoSk1RKDe4
lLHD9RCWqPlft8ouCeR+E8VUJl/kZHlU2rWyau1WsVPd5SjZg/xVjoBfyw1tN2cScmgqebiqwOUv
Tkj1/C3u8+eFfzb95ajozVQP231adEJ/q492ht3sTk2jW8aFvN34UvkY2ZWW6qZ2UB1BJ+tociY7
gYpIYKHhI8R448nDccAeHydKe9uJDtTQIGRb8cjY+eA3I0xn+FhBl5I9d7OGDNYIi60pIArluHlu
fviGjEtT5OTXzWMgZSp8zAQlSyQmyloKOivEr7fHSgMmQu8YFG0J/4l69JeQc7gqZ0Qjlcw5GE/w
KJ/rJaB83fPN5LC0wPSmDH02GuiKwr/xwxgTkQLpvSo2BnqKf4G8HWDu4JmxUevpzrf43S4UQ+ja
7nG5fDcPeVbZXc8rxjFfAa+0hflXkBwxsUZExO3TWGPHH0n3zJl0JOsocOUpA2t5uJ1atACOmKKY
dXrcjtsg1JzztuBcloTa1rLrLCX2GSSLtUcA9FafiLsE7KFOPc25AuIBqdXPFfajF1rrKGIUIA0r
03z6QKHXCb8mN9tiCx3+4okFHajwTphAlSAvaCFKcWGrgS+a0yCOUvoYv+MVR0Cx1v6xiKEe8nq/
Ph6aU1/K7p+THhz2of+N7ur7iir4G0SslRjEPmTLp+vXeU76ZfKUtT9GGNUOVohWhVHhhBnMk+ki
cx0kBy61B3KX+L3/DHLdDl4i9LQKMXXsAdnWJnAc9X44ZdqZoLpMarI8bwFgpq+JpCJBIkPNWRZI
K7UJHgfJ8nGSbN7sl+QK24bJ8sd6O6VjlyhWKjTidbIHvUQBTiD4JJCqXomRCwANTLll7hVaMgZJ
USFvOHMhC6WL4QSJfznhUAh/yTq1BvdURTelDwti+q9YHIoqS0uCszBVsqT3Lsl41rWd6C6Kw7ck
Zhf3pkevJ7G0qjkJ2W7TUPuXVSc3yQxuxCbNMYR9WYx1c0aRUUvdBGCzvq8Slag7lc8ufeBTepkV
J0ClXOG/j4a2zy+5t3BsSlp8t197Pnv1W0cZZr4aZ6BI6QSDRooFeQTUT79Ou2yGS4k5yqfXBryc
jNT4luWkmO7xZBldQB1BlEGfwVUVXT5Aeb85jYCvHzYmy2iJ7O6trJ8RYVzZQevJhXaFPacGrbpo
30ybVhs+2GmlJPoMKjiqaTAqjSXcRZQyiMhzzyIZs58rgUTIEZABVUMddtx7fVct8WOgpXieAf6i
THdwA/BsLtokyEY3Q5Un6t2ju7PSOvMhop4+cLfcdUtL6mya6DjsPx6V+6fsv9BSgNhnZGU1i1Nx
qIRbgAHPkn2n5zfnXoAlN1fo7herxlrviKut6Y8dPB+3TxxJvPANZhCY520/bwD2mm1D5UIb7Kbm
xE9Nmy1F+Xj1ybV/5k1mhgigBukNQMAe2J/HHSPgd1qbcdt7o27+HgKbDjbR0UjcoIzv7pPoIg1e
6ZgYsq3+hRM1DZKGVeYyPmCR/ooCnQbKYDcySj9FDrkt6mFHGJwehqQHGGMN73dbCjyGBZEIEDzk
rMfddEXx/UAvwVHpd4TT+ggstV/WyZYf/dbi9J0YugzaqsvXrsz63cBra+3DLA5JXGBmoSEoe7cv
ZX+FLusxkGE1LljIA3O7qf6/T1UdwaBeg49joGerbpQYwPGHYD/ax4fRlzJBTcAjQdRBvxIB5g8E
NnxWhSF6S/0Z+2kDP87gNHwOpO50rRqG8RsaGm0+RvlkkLMFZCwUMl1Cs0Tb2IZLxiAiMXd8LCDJ
/tOg8Y6l1uFmA9k2+9YiCa14P7XntD/iEgvbBfGOSm5eaXxHgzuoEIPPB+/pTLPxeHa/7hosXedH
mW/SThCuWHi+uQGpz7NNcolKvxaSY5WuhQSJemXa3yhycIfEqEeQTVgumsOGM9rWADdyFfz+D4Lk
5umKS+9lkj7valhp9CTkzfzmfw8c0oiSv4zupAXfUUln6SXh2SOcYBfFlSZemv+t03H0PbzDN1+/
hPvUEpOXCz/PGIQAkHmIEAXu7qB8Z4tW5DjusOa0b+4ByNbProu4lAPW1KlOstrFTj70sYNopkJh
skkI5kgYTzUNz2Laa003ytYzHxTfo+JBe0AcRNhtkbhOW5sHIuX/1uWfi0SruHtZfgxO084CLGb9
IGBRAD/YHkX4dRRL2KBj7NjHoVhgDEY5rtrvXu6M2ZSlZiB1kQP6G78IviMKp7WlQZN8AtHsE9hF
VHA3/UgYXE1Tt0pi0vSBdFYOkAvR3kOLFNrRNehOKUkhXChVljhqnSzTC1ylgUZSlh1WnRAyGat0
Byml6nPbB8DiWT1A1I7ON8miMkgSfC+O2jx1oLj2LcLAB+k0gi0bXX6Xvy+wdsAxN9wO/mmHkKyp
kVpdUdpaKkKXueVvwL3SsS64v8I1xWfnz+rF0Xhiy6iVl7i2b89++6crL5siBzknsomAtiTpSRNg
p3e7pzWQJwrwI0cLSPqKQrpVAKzBRI5eVTbuW6KjJQ23yNBJhH6hlGbihDv2+KFD8du8SUiK7wTU
FUH38BtGxkatsO75P5YnBAnPjT1Qg0Wdqe2HYeb1TzJjdq6MM70fkv7Uon02R121Zy+TAZWZhUNs
cE1GK8BOf6P6OG9/+bxWPXSpMuZWDKJatLhhyIY68Rbv9iZMyCUz3g+AaGXpLb6c8f1oz0SEuW+o
eFSJxdXZiGk6R4nfaOQTYEZWTkSecVwaRSUl7QgffBuXwmpSNl6eRr+RsTc8/UPm9d3U1v4sNOx+
NC6tBC7j5iNEW/Bvd+OCcarlH0zJTQiMIZHcDlXr6mZXf4qqxUOlpQ3q0BWO6nzQjNz03tg+OGgN
o1ad6C9qx2pIndpmaTXUPlBwrfSLULg0T/cGqh4wko9l3uGs/0I65vr/hXlEBTRqqCIpBqrtmlyt
zHe5d5QjyPfD0J1XAb8CJE/LlKx+PeYLGoaGCYPF8TrdNbHfedeQMXQvTrvo++piR/57pbzeKy6L
osCX7iOGmVoKA9fMvMLSOox8VK3RweaXcS8l2pBohHqWXWzwJzQKCWD51EP8qlI9pSOsBQie33tY
ZxplxA+5o+L64oFNzWlfmquRdNG4ye3T5C1WaD3LYgAIZm1zd3HyVr67nfHu9gYFMOXL0ItRtDH5
6z0KCmPz2Im9wi3F7c6wai1p8rRUDBWY1QKNcoqQ74R9pGG4rx0sXgR6uGsz4bSnCkQRqgpY4jOQ
0Crs/CVRp60tAI4+EYrxGWbBw+3VzmEatnlBUnZ7El6fSFuTlYOV5SdRplq/SdBs3PFi2AlZprS5
5zk/bH2T6a1fKLn/BAT6UEYVAI4400FItVfrdaevFOAansLxQmymt20+r2jiI51KNKBbO0Bw6JY7
lwPWMt7WOOI5+txPsH+rZevsMq7y9kXkl/YreyAF9jDSNZfVMPe97WGAgARjnd0h1Y/V0d+ZFipd
VK80uB9D4gqJuorQzFyHZo/hv6MNuOIvK7Eh2zms4DGxLGxq9md/G72lGckO4VNSHam/XQyWxISf
xzlRDEMzl0jf826L3qdAAe6BeVXSKAByf3KOq2u7D2nwddm8cekB1AOcr6QTfg1d2FQuXDWy7Nzx
uu0cLaSgxACEm3gXD08tncQScFsoqWg/A6c4hFSLufGs/8poJEIzl0FLKFPIUqm9t9HBze5rjneb
kd2qN8ue6aOrwK36nZLBOmOTIJJJ5ZruVwNlXSMtyVexFV6GEZYJf0Keua4kVAWcCcVS2JA8Y1ON
BU0bFr3au/8+aHFXj1pyf5EOsDWeYwbGANz2qLj8urygIz00AGOtrEhNIIrUCkih4UrukVGqxeOE
I+sNW+VWdvzV63njm3Z/8XuxVQIiZD8GOPfF3XzLduojGTBj2FGs+CTsrzZAeq02KnTz4TaNfMVs
MsRjD0Tpe21mM/ljmWHhi6PkdX8UVnXA3sqjwhFIfUO1K7yqKnmFIWgmC6AKmsITAZVZ1IxCSiVN
02wx56o/GS1o6KJExHTDT5JZ503uxBoeEkxDsI01sUE5UulylnDfo+v1CIpcn2iuh35v5PaMLAgM
hlhCN0wvZjY4Ts4nY9a70zb8oOesFrdDEsOQ0fvUxlWJqIM13dl02n/bLL559zvvBlyC1uOUmQC6
rn5IAnX89ryvYvlKzQ2KNGQEG9pe+vDvRIED1XFW+byJvebclMcGVYToNyxQ26meknCIop/xxEZu
OdICB5KMkWpCnmh35eiWp/TZdcVGyxo3vhV4yTIVr6UONS8Jz8fOl5Q3IlB+llCnVNCdApVXmW7R
v6Bavi7orOjPbim1UONCpZY4UN7mN6M6oPvAep4uEgLp5FP0XrVyFqZT0SddB9nEIlT+Ef1NaDbl
8Z7V1HkdpohLemmOsn0P66Y/fAI75fwz4Sm4+yZOEooMcwrVIXcMlc2MPdhON1zmAirWb7acuPlT
CPLA2AGGzAVPEw52ILefz9A6Xl043HjDmfsWICRRTm44Gds6K2AF+4zyFbfcjCGIjHxGxMvfbDLq
c99NyVF26Gj1a1MnisAxd3ZRju+qP0Uhl/8WwDSXQeMsvRbVcYe8ltNklSRf3zzpkpU70l1+ixjI
2QU3sAHPKfmO3nEmr3pYQFn8Di/jQ1OB7j8VfcprzJDL6v8SAsNbaKJKsh4XUr8I+MKi8S37Lc2+
8tB6Xl+lptVMftOuGGE/L2vcpbyzEjpEjjuX8wMgqKmJwP5HBI5/9ytEafMFFyaIMXgCDWS7CIqb
SHjdp5lNYFjJmqR/Qd/NS/XR2grAYMAU0O5Dev4tKH9iQDXzl7/MCnBDOu0k2OJrGbf6hS7GXCMj
X3sVpihWZ5mvGwot3xcS/Wq54xpc9eSHwqSpS1EF8qaPtX0J6UQvy63GFPcEaI3aRtUuED3lDJ7/
qhFTLE7AW0P9A9dZHnfCbzmTbdGAp4mDgCvZ6i2jucKTB4fXiVDmAn9SfC/n3VrxLeju/T49e+Yy
zquO+2okv3LeAHm0FwNXTC5/r2AdUY6Nu4OH7W7J8S660X6/EbzsNO48OYR9pUnbvdl9JeBChPec
ukf04dNKHwoSwvg9vDxh/ITG30Mle3hQpexaZoZgSvlHzlk0iKrFZn5iuPUI99ey/4s0RrNR0Eh6
eOBlmLraQc1a3P9qq9shyKH8e6je22b32911g5T962CW8Zgu9Mf9LXQ1VoKkUfzCYwwfturBf3sJ
upcrbDPQOtv7KvbOWuWJTZcr1k70NV4tJrkGiPtRAJv8g371x4zvwZEjNGHuB4sXAH4GaqLZyfXE
SC5JbVZQT3xnoqElPPaZzt/0bUoPvSajyXFhT6yFRLPc7YwszetT3R2l+2cEane6wIdZYOFNZBXA
bf1LobBJa/v40Ju+czPBgy0vs6YT2jKWMQawcGilCpEQ7kGvpoEUJdP2Vd7kchbBQJ/p4ZREV7/P
RFTHmpK9ETVni4YL81M7cUEOsG9G7LODv6YyTWCVZfYMfZuBlq7adaOPB1nkAxutx/L5b3zXnTaF
w3L9awF4z+hd6BlDLKyoGqwVQ8X6C0F1LXkfqMLFSqoWJOOcohqbVRUOk1PSb/ocSMmHh5YNZTay
FqEjpewziHMGcQSmI/ti5ub9JUXix8WyGZv6NxlPCkvKTEQbBr1yG8AJjO0TXEHl0IayXR/sSkc/
LFL6/dQ+eDDJ4IV03Hwr/76blDHJ7A/WkdNmA4uKkO8RQ5x6Ya8PwETiQulbZSfniIN+a9ty+Kvm
M76kVJzfpvizR09v0ajgMedRahB2Bm2tkov9tvmxAVR9MPjJYaZ7lLT4NXs3EmkI4oQKeGLKZ8Y0
3vIxSjMXGlfBXL+9Njpph1lIB1Tnv2MyCei4zGnYi0Yxde0kmKWkaM4BJxdywEeCNw+VbChfVsiG
FbeE3gS+J84teBkEhlF435LFE9SG0h8zeQ3juYIAyZqfrTf+3XhgtX2WoUv1h92ydlHXo+9TPojm
1KOwso0pLZ/O7rUZVey9wt8Of8ZzjyS3Mrs+OYKSB5xRR642R71xn3OygCRCN3uxbgmuy1s90aFv
78Gmx3okBCuRLebT985WU9vCwsnp4Gf2APriY0kPZ1gaqE8XpgL0a6/gM8c1aNmJQDtP7EMiE8jr
XheRedsORByxia3HVNbb+ml7jacbMQkbxfugS60FRTN3xMOEhX7/fPZmAqn1PLe5qfyep9I8DflY
TEoksbUX5WKBqsif6fRyeUOIN8kIQaRKLImGcJcHhRBpCShUVG7VgCN323/g7SzUxHIzztcYXXO8
/Ukhi757FTC9N6nSOVa5iaKhl1fjM6TJhWkJtmhhSbeyu4BQ25Wa9+QhUgkJCLOzjoPPet5XVWLB
vJv1TOeXyt+9Et+p9/g2Zn43+6n1xri9W7FNGuBJ0VFE6bqrVGr7V4mmtAQhPpnt6UkeSkjLvEiK
meREdY+IKfOkOnOATTBWIYCArihhuYUfa8DsSRjQYytjdACIWHoqIdtACGU97ob4+wFC6fRlvSHl
WEPMGC7pQS472sq0nzZZ2nJjTFRQDNyqofUqJFouq9roQ9MhNuqXjWXqBjyeedSXpJvAVn87Uh6G
MpAz/A6PSR+L9RTN70lcLUYWnkyaWf/PhBxHYJYwKLfarypV8jLDAZ3O5TsuuRf89MKtSLXSdyJX
qKrb/pdCZXSdr9laOfbHU1f0uErh3+b961Rr00JEfItI9idP125JOSlB9Z1u2mDtNvBWmz85TR6n
8p1xKsqjFdLMlpWwBfhJp3WYgoY++b1CDPDtkfvmycUiXek0eJAh6LGuPxVWM++8SUUN2ewQgIOV
2Bqr+YHb/RUKQtgxzIIOKNx3A5efbuRu6x7SZd0tmBvZI2j1OcOkDS0gx/deLZanio5PVNqyqsZ8
RreaxqhrUyU2EQ4tVze8o1TvsyKSLz27tlP38C92F3y8x3EkNmsyTO8EjNNYY2MSQXdP209+h8oc
muDSK9n//IlHe44zE34aws+7iVkFWWTYQw7sIA3JaiZ60o73y5E2EaD/88JsjbKaorCQsg/ibV3S
oKKKkOHrbNcSpd2fRJGBi2I+5t3ghLBOvJX/YRPQ6Fl6kb9fkBVwLVA7oWfMLz0aT4nhZDW5bGPT
yB0vmnd4HLfDBlah1Yo3NbCcM2o+ELl3pCYXGCe073ufSimzg+4aR9ltuB+qgMY6yW0S42otka8K
aua3LAJjvhOsn3kNoVGHd7cMVaWtm08IMlFJH9olLBNI4pkMhsahYyO8yEKxa8ToRuC1zqy0muzR
4GmBKaSSp93d35x3cF0dJJ/Csnp7EYeeu7Nvc6TUfQ1nd57aMBR6uROwuMi6Ou0pKpkgXL0L1Lve
65/EfFF3r94dofZEOxcFtOEwX+epQFDxpxze6Nb7PauRicl7zk+HyKIRnBmLeNab4HdO18D28MkC
/1qmD3P95X03ft3kB7fQa8Eelb3Y2u7OgSAXwf+FAhZdwJd4wT/aXqUl1CurdAzW8/KN2CKLnVt6
Pb0nWmvxAfteKZVKzQYlWuX/X8GrduUuy7KJM8pVstXmTqizYCtEBD6dAXuM/1f0oGc2ifEEOiL+
EK9QxE6wFcXg1pCfWC0xhOKOAxyJ9/mgQHQjVTC3HYRWZI1BmRIPllsB01aIXy0LeQycx2KVxMXT
7x7KmJrOhw+CXU30nYFBOFr6lLLbXwfg5q4iaUzSp0b3ty0iZH6snFew2AdYjZ6wWV7Z8htEKk78
gWuwH4QWqdv65AXZbXCdFMEqZmtrdVkaFDAz8Po44tIwOzqHC1NTiRPXt39ZPGnISyA3Oxg0lWoo
4quY/5QfghLhjantHGf4hYKxNzlyU+PTJpyOfjI/N1FbBMPC+aoDITA85zDkgx66VrpecO2WCPZJ
AGTlwicWWR1ikEtkwoyK/4rBSfmeblOFMop+CefiZSPWJEIMG/S7oNfvXocNK8gZwtwfmlAGeG/8
SdewCAEEY7EJxWthD3JUvUsYdlT5nVnvvzacgFqiE/wU8uZ7zRsl0p5xjQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
OevQvFsolXiIelwFTsJirV6Gbn6iqq2k558/BxYyB28z6OkU85T9HqNSCCKfNwP4wWWVkgv4GHAx
Jy0sN/6OCw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
dIYJawsr6cc7wucJUmqeKNx9RcAAdwvxb/0+8/MkD/yxO/GHE7ox5BMSIar4TGvN9RmtdLN0/Qlf
UJ4U6fSCLNEE2L+cLdo0TK+3cATagUATZF49wcN2Gt+IMvECvEHpqOzhEN9Pe61AjMFoWK1DmGd1
ol2/dF/uiDIeGSY1QKw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Umz29ds1G/359pCCXvaJxi73V8DX/ioC3NcFoPC/SPcFGzWa7G8h2ThMxyPfXJAhQJjSebl9fGDz
dIYTNUINO8B9xnoSwI5nSZq+WJthT/6f5Bcp4p1MqD244kjH/mVO5WRtoMSm+CUIRtojI0yFWB/T
6A6+4moYwJn2DzIGok9AVsQ3pmnqfjI3gpj4azqwY+WQDTbVZiIRPzYSqcJBqIxUb9DYJWdMkH64
rVMKUFKxLfIFvaoYZqtxG+NQBdYXIj20xO6xX2kuHcw3DvHYw9oMcwAQ2ylDpzXGS7g3gNmUR9UD
xxN6o7fHwNKPcDsYQAokyFHG62z5tKXsUSadsg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
pnAee803TJmFvFZoLC4XIJASlUZRXo/S7hEz3wrtiERaDmVjbkRRPWuiGVmgskihOAumT4MUKGZg
sM/hVBGHHnDHBONKQor7stSCullCDfm3Rbu8rmZhc7l+AUfnyJAESUh9xiox8ywwatYPnqwcGXPx
j95FPrW7pCG8i0dLOII=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
iXyE+SxITwpDwXoaBvO/onK49w+Tvz8LJvGpaCKtwDLw8dzSbW1q4wde8Rf8Jn5vAPHCPr4in186
YtVtwfzWJBMl8JW9zJmIP/dvNMQA9aIQBRwGuVpv/NzzwTzYQ6CsLiBj1WMe3MtgQ3vcnHi/L3R1
pNLJ6zAivALPSp+wqnPl7wJtSXIpBP/PKa1uFFmdMmRbViq17xygeziH7twe+s01beq4jP8obnyl
zF8RNKkQKgaG5Bj/QVdUBisFAnzrclRkCOyGnoF0af34byGOHv7XdGoOccq+cceJWb8Yd/svve49
nJpwSP+CysAMBELoxw59Ks7S7Rdwhmp9Q05xCw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 89248)
`protect data_block
y8o9mpKG3xq4+7rclTtlyUiUYQh74vpgG/qbMuWuwSqCczeroC10EnmkPDSzbqRRfKxB2tAuJogk
cwIcrN8qx/rNTH/PYTUpf3sEKS6ytBr8v+qkvR16WylupvRaByswJPg1sczmvwwzCDXUaMpamiAu
LyurB63C5jShtsRzBVYDHvgRRyd84lZXk7Mkt+c9Z+5LQLASEKFaPiSLroPHJP4eN19n92PCiq1H
0MB4o86VG9kdm29FeBECgjTqiwxnFlpyxN7jrSfeQ+hzKjdHHP+kvN8ESAmdN9v674jdVlbJl3c3
TFzGF6VGJEPoYef2y9g/K0xYUiZfDhQNuwuuEvCwLzHP1nl9LntdSaRXK7rBsAps8dODEA+3p4Aw
qjtpsWi/ySls6L1ZblUFJCjlA7K+1PSdLQOtsV1od0evT5NB2V1dQkpMpcoCvdH6LpRDses52Fes
E2lVQKUjUoE4S/2Mete/WOJHaadyicvmepXrJm+hJKm58VH5Qfej3DEryGoJB3w9+bByXQRX2V5h
rcqZrQihw+qcd9vIcPRi1t2j1SLbWWFyOrui7EO7R4iFO5i7rzds5b2cnAKgW4EHm0z20VAn+xhe
kN5D5pukE2flQgGTH+n6KhzjQzX42wlMQtgkvfyvf5lkAYs6jfTtkZqTX3Et/tzw1Jn1xvPf4Laj
+K0EAJYc1M7zS3USwz6WIa4gLP6RChNDTBFptNrLinYb9WtHgVY1HbBsjbYIbz7HW6JOqmcPrq+0
l29zboIqW+LgsekKaeP9nHmQPRC0LBbsn6QE7lMSkIdFjIxq+uWeLhlT0KX2TBMYqRGU37jCZ7AF
w7tkXEcEZ90rqUb6Eac45GV9t3SF8ZMrbB/rdAx+OduOQq8yrbjcsbXDN+XpeJVtCizq93BX2Bvg
T5tSLLWvbTyJSzoTfXrGCJYDh/v9N/8bosVgj9nGirvlNTbcbn6CR+Fl97R/B3uQY/y+QP3bLhLZ
g1cyb53aXlqkHn4GY8MjrR5N1FURuKdOyM33Jq8yw2zk05QIEJs2xlmuF14bXfNCrsSNvq27BCCh
L25ZF8xeRjnrd/xKgVkzG0c+o87ipGXZsHrxmAkDdN1E29nAbnmZgB0zyIKaK5mn5D51sK0W+OJx
tLD1Hpf8hwfI2USj5gr6s77FjkM+MbEGWQDbTianvoJp6z5/mhyn/kBluVsRfArTTNRAkR7fc6rL
lT8XlY+XoK5z3/fR1du78/qYbbrv7KBYEsO8WDItNJuK1ov3lGwpfcRYwGG9k6OSQxm7hUdiEVTv
NJ36H2ms0lJ92VYFXbYrv0KZ3Qy8Pwl1P3jQl9TC/ZnenwNmtT2wqngmsNKuZD2xfp6SMWKyGKKb
6LXuXv1qtpygykVfKcF8SJ+2oXuDRDxgKi/JB7ZACjvexS6v1NqKp/Gv99rsW/5x0D9ceYXCpifP
GgVCCgxcea90Yuh3yXz/82G1koQGKn/3p219T/OnLBQkz8Wk5QJkw6RTbc5r+HQon9Anr9v4oBAT
5wvST/SvX+z11V7hjr5Vz5GWRX3NNwDrKSCnaEX+D3TI0zZnEOp3waXcTJfZwKlLPaDUietSZO5Z
QhvpzKfAd1crZC0itoEo5k5pqrxddKj+xcJbWUDOmPNgFjup5qLVDeoyJti2ZyFaTnh6suvKXn3p
PmFWcLxWkMSKRwuzGBElPSda03KQ1jfCImD/XnkbBcsro8AeHXIBWkASs/CG+QQGyF1/M8QkKX5/
tD3kk9LzWtNS/gGtNYFGCYSp/+Yl7CQJVAT1w5sM1ujtS9UPHf3Z2Sg8Y9JYUYg9CQ45RwpbkCwW
gtk975dR331sCbLtDzqCtAwOEWhnWlaf8kPp+DPgFgRx+ZUq5B/nCuxxOYSumBaDpJ3w/6kpxh65
9RMtm26dd9mU33qy3AAi8SyaAPERGCOYpYv8+i3WMhN8c+KwHEedCQzoSYKy/R2qmGQZC5vJrklm
Z3THy+cn+mSf3z9cRdcgkxECz2pLc2912CNBLxe9SvUNnfFJFWBGZWvJlVgs8Vri08/+BsuUpe3Z
LG2TpOcZK9sGC+45rGKmVTEzGCXA6wp1LwgNyNTn35UlM3fU96DHjWPnAZ0ifQM/E/0UWkXa+YoP
QBA7H5Yu63RfRmXtKHhu2yamVHGOg8NwBtXr10bHRUA+EPW4/1Hc65Oc8H2LdlK0uaJnS/BY1uQd
0qd0Xw0kn7HB/KHwb7K9hh59h/n0HjR2/Ize1ZWZfyufm7s2HxlOkuPb3s1tkoJRxv8zG1VghiSH
yDQ+PcXut4GTw0gHRHNUsEL7PT45xgGBCCuI/M+DNoYaBycx5urT6n/MIREeoX/1iXWSKtSlzL60
PFQAllhETO1uRg9TtgfJjvOLulRAcCDHQ9oe8l5SgA3JqHwhH2i/Bruxf35UTj4kQh4VozvCkcLL
EPW6g+SbcjEpRpG13xrqWpVDyRHHH+EywPW9vq2GhMfwp1PjNPhXwhye1Uqkab+9CELVyF+Ah/TL
LritE5PrSLog1hQU7As8zpxTzLw/h2a0xoEo2kxP3deBiJuyQNLakxctDlUGqWFg8a7RV9fU6Z6u
Yllbpnwy9PRPOo126ZdTIoXEjLJGh8eZbUd9AlEM7aF8Uf0whOibDphbqTFLki+XJo/KOajSD4zI
i7teQDuOnw2uHmCNC7isnk/8IotunWPjw4ZxWUi2MyEpj3Jg5IsQZTrgDQVgLuD7jQ5DgctWw68G
4ZNN0oITEfw/5cZTnBhtNsk7H73ltBO1bG5GAWKUk8RCmLTyv1VHtftOWHTgWDOBZHRf72GsNEr/
AV3vGlgf1GZSeJH7HCyyexfeuz5lEOYwAlN0Y88IOCWaXLXQlyppZe9WlQq940/CBXsc45dJFKbw
PT9pSixKjAZ2p1QrIATlPLdICAtCF1xiR++tLidziRXAQCDouNIloxREtSB03ZbLzCUdRu4l9FRX
d+BPyy6mubXPnOCZ43WU4w9Qo34fZu0gW68rTssrFKToGIxT4s/YSCbLI8154ifPPFi7+/De3hj2
Gq2ZddSVZNbkA8sOnQ1qJSXP0r8ThHQvfYVSTNjje8n8PJyOxYqhtmUaJuraUgB8o7TbPVcCXIHe
bX5W9ajCQPqJvXKPykQPYuuyfkIgvuPGdtXeRQY1/BYHkiXYtO7SeJFFzlLA1b9NoUTf5GXHXRYN
cC7rFDheCyoJ9xLrXZ0Vapsoa/r9PDJbcioZ3say2g4da4pyj+XG9JAfAw11MZfp8dIdnDr0qlPy
YkXZZrJGPOZVBEZF8r8tsaaMJ0FN8KJU8vtmpX/ajHVqbV2Ggk2E+qdbsm75L6xweuCtWHLe3h1R
yir8uHHAuFszoCK/rGxRFXQrqEDgXOKwuU72q8opbgObxgWzD1JKptHDRYFtUZRScTAFW9aWhrmM
YoIDMWReYTdVhw0V/q13kLsFEwLPd0X67CI7saT69cNcSfOkSGIBCU7/N6LTmcTYG1DMx1t0LQGu
mRKZmOUU13y7aLo+Rw9Gyna35Y4+rf9NCv5Eu2YPTR67ZErBYj+BTmF/P5Azd4zUyRtm7PTPWVYq
YCXpoo+Wjc425KTwGe65WZKSGSFepYyx1P3xB7yEWAqPziK9FBFGm/Q9fI6wIus4mwJ9bTt3Sti9
5Gx1cnV1VETOcjNfz8VLjVNOUBm6SVvJL4qEVobCkFZnMyx7vTKbrZJgD9ytYMe3OUPHBTzZ3x7F
5qLv0ZFxu0c/Ndv2E075/QOWPZ9fCaLiVJsvDyLq1dkiqVuXLTtilXJBhFi1PV2VVv2/GfwAFkjx
qKWUblRkmpEgyxJQnTSqCwGXe2iqQ68WY4FgPbKxPOyVpFDMCEDqD+RPFYBVY/CyUlUAh+3RrkaQ
EeuK3Nf+u378uLHMrIm435IToR+47iq1QQpvmCG32/I6bjFiHIDJPXpTAKktRo5hSjpd2FPYxdhs
fk12J5E0pWQnnmSg5kbS6r+VlaM6S9vnQa8IOZp2lWTiE0FHPj67Bg9X6wg9HORHBZQXGjAd33wt
LX+R9VlQxc075vlNxhwQLCkZtL15BOmm6vmZfF+Y2EuvKlWEV1rUjmjON8ZmHVzjXYqZi948LDo7
MQ+iEOyFmdyytsL5ARFer3/v+FaFVFz3+J5/9s120WJqv7uC45mIdq5oR+QUXfGpE6MJTdEzh6SX
l2iGUhtoHKGshRyWkJDKgoZaT79cwy5D1ol0V1N69xyNRhCTbZyFhx4cxoRNJWhQ1foGouDre1tG
7GQ6gVghExCUY5zdAKKDMJ0VENewHWFQriPMtVKszo+/milZWF3EfytMsBAItqkemi2Cny/UAphw
0AUBbCEvl8Z7NjyrsqAuoDnxDGnlncap84yMWbLHAMXjO8GX8lndDcMUIkLWiE33Ypz0IpGNj1Aa
pFQxoiMuUBOvomnYqsC8IxfoIAWutB2ucxvhEIR6Wc7WRRwrRSvq/+n1hU+UeR7qKR249PkeoyFA
aCrIn0+XwLDjaFW64JSoBExfJlL/B9RCsTesKTQKtgYwgtU87zYWme+hjShDSjbeEKRQo8o+m3Qe
Fx7XpPxE/oovPyV30aCN/COvK4bYVZaXJq1VIUKGSK0+cahZVSRRS3/eqmvSWcjYvzYXttWgGlxP
Z5Ohpz0AumMA04PqorEOjo579f3X1w/Ar3jqfIYyC+5L2p+Pn3cEWFQpcNlfPrWNDpClIASD0w/K
LsdjoZpB9IW/YF+kUZfHrq7eftCSSv4QzEBs5Xlr/Cztj/Td31HJSdeYZv3RX6h0TLdJgaYM88Ze
8Bdnetav9B8XnVhSUd4I9eiTe+e/R+ttwKRonFAp+xFQ9SQ9xLjX0SAejqeHRF64l60JAkIetKt8
Zp3OVNosHebJVehsiCZ5v9Vzecj+K1kdNkXWYZIa8gcwO/maD6eGrz230g7deC2DxO3iJcicS20R
wwsX/uSIJYkb5PXIdW7sGkAdMl7n0j3WRjFPVSgDcBb64KfxumYmBj7VmJGAEdNmTAogE0oaZGYV
GjaLbnSOfQSgPGfyAb7c451VYvyhPjTxZopcTyv/+34c6yY+R9rWKTPHS3EGxppeAZCHqXsTkcLR
3NPltW8dp0pyj71iRjRPYYcFRe1wkEcJ4AwqKY3pm5ITJMYi2aeaFBvVCyt8cX64kOqBo6k1Sqy0
+rDIeeErw1fEYTd7iL1I/xbgmSd4vai8U5BDDe0GwfeQqP5ZsanXrcP/C0qmfMZ+jncNFtGEllVL
7bvh4PsfftD2a3TweSdzOJYbAxT/NWIEw03mTc0WD156ldVFgvQmjWHHvtKW3QxF598q0+MWpv12
IPYDyphQMZwJksTcGvnF6AnvBJN1TJZA+5rzyFRYg9cyG078CeBf5tNrHabRRPbxE4vFipMxSbXF
EBxoLOjN+hbjt+hpV4CgzkllS3+ygYI7srdOs7eD/HfvOtg3Jj2/IAA6JxZcajteWbhklTrXyExW
TynIu0IDSaRI9/3MXM3OExNpdscEEtyuOp0MstcxP5/uo1E3onGPj436T45psNl9Emiq+hXyfUsj
csoD/omdAEJVIg1lcI+IOSmn29KoxAeMhxlZBPjodayriUpi/AeNdIwWDl8XTRw0aT4oHeaENKEx
mgwu2s1qij+yLAXVd+CIEdXmAmIgUQhCSNZypsSrmclu+HZG6zeWpUoig+24mO+b2LmiSWPpKKch
/lRAvhcOqvpltP3VqjRLX+zsq67SjYigIYvJsl3PGEI3IXVsUU4TfL8LXmA0sUUlObesVVie2/Em
pL8QfY+OETgI6ukMFvaCdO5Vne35+WrBGB70i2wVVNCNq1q5kXc5rUlOhlIthueNPfrj42X6Uwxz
hAM8cC0RJY1uytuinBLnihJgHAJbv/+nyR05dRwwLDc1dNexTivn0hVg4InB1OuL+fE5kpFpqyHg
t/ymc6GFA/CXhn1QXdXgsyZn9Zg3rBB+gCy08yKzRe/Z12Dbsmi7Vnp7QMW42kWSbZSJ228NFNpP
7M6JxGko5EZyvZ31Dh+UOSmMJn2TkkrHzvMNTQ0IkTZllGWMPvgV02YwAKFcO83Aibn06TScb4WB
CjoQ0kK48srEVQkBHQt5VPmo3idOCD4CwqCSn2//LkEAktaKguFpAgVf1vcOaGgAStgwzdQB7b2q
Oe9Qn0FOUIALdWzIxsmcCd2Fl6PuGwITT1vANJDhbl9TuoomP8vzmRtzfm2FVFjPjosoxYAHTcAM
hg2tnkk7hF/MjILLVd/vhtGsmSoH8N6+K1lnvrUTsi8UO+X0TE2wFeTZIbsySJj6kSv5ffR9+dJf
G+eNfbbYSs8CQCCnbx6dfX3m+BOGBFIFF4TGdS0OshMh5D8AYMpn6CYpd9xTE5FbzsfQtxn5uzUy
tqoKFCx9/RVQgh496g4PjQokzP1EJaAbSj4wuTbqyCcRwPDBsl5ooDxzF+MnyFQpjcyt/WjRQzHD
3C8m+iO/4If0g7YFBvb2mUYblrLn052kQQcx7HRD04WHHKw/uV9NbUaG7K+2lA64Moz0Q1eHXXFG
bM68/ylg0pyiUBvVRFHDliQSiW0vAF/89Z8j3CyJYIklWmGuW8NcgcIYEKk1mc9F6taH/aFYzfYe
stPkS0ygLUkpX9zP9unlAaN+iRwssAI9ND5UbbtcPmWs5po+H0bu19XtNqd9E3RDzhNVvcs4DMb9
grZYU7FYk0jCXr/ZXkxnKCJv5+feAM3t+yTE2Gx09kgTfTKt1RUe7GhSMiFSPZ6LPkTs+mTy+jSz
cW3qI4Rles59npqjhYVa7BgJ1eTYJgGbrccr+WPnZ3lYseQXHigWJTpt7HCChhu6tnRJJPSFss2w
VbpbsT2bt3QSoEFMI4CuaAIL4rbHCxEsTU00VqYlWUY0AhknCrlt0wkRYCNExuVV02VZtxlpZsyB
2fV4TqV99GVtUUt8gHd2Y2kxTA44t7RArqToo96sXoADeqFsKZYNkISco+CI9nHQDhv/PI+E30Zp
Mc9kKOorFwQ3uwFi85EI0gLm8zqJ47D3rXCoRWb410F0/mr2G4ZGKVzjs98lmOoeNYSf8sgYeoJl
EqGupEnDTePbCrZ4dpR9jAWBo043jD4Yf68zMA2jcvNYhsXYnidU5FXL4jM2oN58UTpxe2jsZgKE
BSdtKT7kfdLVv45moCEOW5hHuGhn5rlPduCRgj2Wt+EO/PGCI96GWaOcC9hhusrkl7AuXjov6UZP
Zzp2AdjG3ZtMdwTQv/rV6ZK9Anu2k48m+UA7c/dPImsfw5f0QHTrX4RnJUu/3Veunw4nlKG7uF55
VJ+rRP0IAbmmuchy/CmuzVUJYV6mqURCNEXC+e39n47mS6X10X/VIRzHdQi59rTpShgLQWO+TZt7
xoSc/BaLo2PE41TviukAkz8StuWBb9EEkunlNlxU83IOpBtMhEzRENK0sbZ9sBC0Ns15mc2ulw2S
vOOLAJ1X7leC9BEDw2p58NTqd8FKdgNblp4W1Zdt1RbphwuyT/8PWhb485vip2ZSdmG/xZt+a4ro
Y+Ic9jcxseb2de4ylTzUc64m88DpZW7byhNS3Q/Eay5Q7EjWnZnBdLgGUT8odMQZ0fhE+YO5A3Df
BMZQ7yvhrBerMHJD5UG2avVBBSmB7p71COY7QfUEUDWBaL4f0VMGtm3BgnjT/VxGGbdDJKHUcx+Z
zOz6MaBKCpc1KE+RUKMzEKnWJWnUaXIg/9FdJJzdhTktA4akQ1QLgX9YP6kRcRZYeZzE1y4SaWkB
pnFMzXeLepfAQiAUJcdFivh1bZB9rCOJ9T/tYY+ZfPVR2ABX5MXeEJfzynaQCKS2rEW5QgwwVIQq
KKBpvclZDyogv9JIi20Y7DcqwvqNYV58UqQYOxMcaz38plADedpnpn3VBt2jrUw3K/SdKTVyRu0F
g31xxWE/nYg2251gFm35udJIIz39MedV7WjLu9nzTK/NdJdRaP3KxTyHKFBqSCzpgbO6H8dhWUvb
tQLKfVvZkM1jf55UpDdVVHQoseqpfx4YjfKeeVZtfaMXZUttZUKK62eO7J3LaDGskpWSufJnaM/+
U9izLRLtX9U6u8bSGyiW4tiYFta3WIAS2UR+xMCPlz7xWaHyrvdFtGE6+BAg3Rfc/okeYhgs8qm1
ni/sAoYmcNTq+CYiKkxAwwv2tRlO9hvOqSLBRXSVK6/mW924ewHp6Ce+IXdUFOHjgL1q8p/xi+sK
soc/n+T8+gZtLzsRDBH0vBwWhLS1GyDG9E0SPtnzRT4ataJPW0rXsEnxibqacTaJvtGIfkfh12hm
gE8+kW5ZWe8dtcMeLtLLOGtdrlv5RxmfeFpFWSXJkSk9q/e3pk/HP0sK93wYrr/GqnQLtmDyz5vy
zkfxl4+Ggvhrc2hOwzgUzzdcxetSfPAlLiEUD4QzqmTovnb+LicFpMN+xW1gjzJg5JA3hBRN0FkL
ZsPZQh0zKGZJcOzT/FJruebOEamolJqT/lugewY1dBFeJUDC9qhjblj/cjnhCsLJ2yVPRIcw9j11
yHn/p0wMmaT8/BJdZPzeH8EQE/IN05rOhofcayJ0tUndX7nyMGVGd3GNvSIsEKrjE7dqmheBWuSZ
xn4Gg/LLoEBT7R5lTkZM/QSB7CtvkODMzWpxZ6hiKg9m32YXn4lZDVjbC7EAW8G8wIFU/tQEqkfF
5mlicIaZQnwcn5Q+ZCDvGPzT3a7qukBsfWfeaZGOEP3BArfOqsgGhhjn0kjDXWwvqM8t8wJG0UUB
wzzJDBx9q+QOYcHLbNy6fpJ11NNoXND6Lo6B/fylLVKMzA1Yw1JScLnPpH0tviOsWpuUqr3xauxo
jKHnU/c8rxaGuffiXQoeiS4hYGEic3WojR1aCaUjHlaVqoIEFs0i3E8Vd2m2fcl8ZBr1nydcJ7Ud
np7ZS8ydgbbYDKK8SXumxBvj2A+SkOvnjLMttGh5fOEiecEe+po/3xjD0N1AP0Q9ttL5zjo00YAE
LopCr8YlIHS6oqSQOIBro/KiLaZOSLr9A1vVUy70pMvwMWsIf1ekis3E5LwW0gmaq6UfLPvOkD+t
KlTi4jVSnDVH5xOd/Un+bkFz+j2/0d2gVjnHQY08M7DzksmoP8zDPm/siHTCoPEiY0BS+6zkj0ta
vbOfTkWlodAXQi0cZb0NIoCvi7UtyaXUO0ooeFjR+Hd/MVb+7/C0c0yZWuVCJPJiMLrazON0CLkL
hkNU1S+JUd0dC7cr12pUAGkZS4Uyhk9G57G+26h6iUg9zg6eSUl4nv2Sai6RjKAUTiKpcdZkqqN+
tXHHBXyfQNlpHgu6M2a8AjuqeVWAEieCBDgahSFNm36uD1y8De62C+XV+k+6e8m/xg4FYNVpl2d4
NGr+Cbjy/RoH48ciOdlZ9FUUgJZMRns6MUxhwo3NKSthjEePvCfOnU2vp7ccZgfoNHTZPLW14ICV
5fDg0FLM1gNf6fePKLc1W1K9mUohH/AsXg3nRXV2r9THMyq/Il+ukmSrdjdHe8Z2uZQehnPp4q7m
IJIDV61opkYJAd4v+YHogGJvlNxkTKF3x+NosdrlLAvU/ZjTr0TDF4sjEfFNSj2TLnantNjd4/TD
UOzIT50/XKiklUHxzyYQW2DBpentGQJh0GYPpF6qZ1Uu6HhMKjVaOwbPmVtp/6lyd8AQFTn/tNB7
exIVQws/AZTsuUGKk6oyNfX/y8nJllEL2TRU/V6C8HQEoQFd2znHK/lSO3Resji4G5gDee4F18AZ
0jD66sFZVJeBpWlnjo4UN0/PqPoL3RsQOYPBHcDY7rQumztjbnkYjoXLkO+j4CNXjDDNE9wcJdZC
r5K6JF6UwTIPS0ZN1ZjESkwJyctAnEpRNciM1ZahG9gT/GcFYgaZiTGdk+4gxRmLNYEm2m3rM94R
asKIVg+WR1KfsYFyfIdT29zQ6kfo2D3RAiulB7ttN4FiCLbH9MZtUMyEHlJz5rrI5rNydy5SAYoC
HiX7ZjcFJ0SS7CcH/nL2f+PWQvcVyxocQhyly3kWYmZFyTCXYDiFFNP52YJjPW9oQZdlPCBTtGlU
B5yy8y1KhlnS5t9JvlKoFNaa6iYHZUq3TO2+ywtq5HZlwJ34LrfVov2iBIajo5jkyVB/2hHmXnQC
u+jEzX8MpxLHBwkeI9J0xHb8OZUax6TUIawNiORAMMf43dkvnVBPm6dKeWOJnPFM/Gtv06+X6PY1
wuIN6mBkTVA9TZnjx0jQo6sI26B0DNlmYARqWzbStW/PrO6MsOnxRiwnDH/R4EthaGo4GnXySIv7
4qIrjpkHgsRexmxYoBZHu9lzxkjv4BVYmeksmT31NSmjSe3nSeeZpEmaYAkz21ITuOLObv/LkByk
piOp0xhkAIsRWPfDfkSGiYZReWCUp0+6TIylv3JtnSeM7gUXyZTM7JB9/3O8ehhcOFgXETdduqMO
RfKgPkeeV5q4FJiJnX4zBtCnfsBp5rcZoTQ/lquuMwQlDNVVxS06BNoZxqtvGqphJlAnYxEW5HWo
Dg0LRs0LYKsFE7xZKEaGI1REN2Y2aDZkwOt/TKDAmV7PfGP1qS3RF5YhPGzGQoi/utZhXMVZ7F0+
M8nSy19NvIHCWuwzzcrSd38U0IxTJgrNyZVqN1bDAZ5EQxDOBFE1sd9CGpQE89kmDVFuKMhBus7B
euQsSyNL/Tp6JEvRkeEoTLakyIMMKrGS8wRB5BhzujTX/0GXQhRQpTjLfNHeWsXHNPUEiZbp3KPY
FPDWHqrAAZ7VHP3xZENRb0aS/EdbLcC8rM6vXQXRcccbpiRXdE74bSn+w3ZZW8ul9nb+3JMDbHfw
IQON4oy0BtM+f8EO183w908KXdMDgzcChmGnrc4VIUPA8RrIn8+pe8MIXb3tzxSPOqKedA7ePbty
YShBdPDQSyZZLxXXZcjncNq7hbzPfQizXyTKb5KdQGY7B73LQnG2kU78eXBvDsyyVgvjVFtRmCMW
8xevCv+ZDJZBNV9rRJaM3sLHyjpIIwZSIA8mVXjk5nF2SMwkfcui6tOd/6UrfSg7GcNtaj/WM5q2
5r4/UT5b+NYlitjEV/k2I1hQsBKtwrGP0TKiIp5FxRJgIGHoaJ7sX9hAfKmKdO3JfVNxc1tIlUS3
2Lh6B3GWoac9cVqYBBtVEKjCMOexr83p0DcmxF7nmw8haZTp605djku7UkuPgOP//efmMLecbsSU
twXE0amfQfE7XYc+kACkjI8O+4K1kpNv36Ak9AjDYzhxjOR5HrnSYOxtvbQhDUpIWpuDjmKal+DJ
R35ZRVDN52KtWha9iiDtDZd8YJo3ySxn/rBhTK9OKonG9G86S7es5brtISaeKrkqMoJhmtydTT64
v2j4Y4iuDqnV0H1dXo8Ag56r5hwUuhD/3EkNVmNRabHlWpCkjTsgalQ0tlKSmufxBLqNA7tATZpn
mYhrnJ2UnMJF7c/9FNR+vYEv0EpfAoXU/1MAuAxHLTVASpREo24Ma/mf7w+AgJYQvLikKxktY3SL
/nEW5rDCIKGi5TAk7EVnBnPsgtgIaJ7NncpIi4eWBJoUy3sTgOG3L8UMxszFqS6JzxcG/oQM74o2
ziLnEht6oqeRbn3R7gnXcu40Z2H0pWPFsVRPyJXs66zgDTQS9LDSA30+pRu8ktMIKUO13Dfuq2SE
KNil3NiO17sdHndbz32ttmnKf2XitxVmUFIbSQ7RnvODMK719b0419TPYjxeS8WiBL/DQ9CwTv50
jhZMnQptkqYEZwg35AjJLzbE9ipqrkUh67/+nwhyo6LgCpXLbz1s3b//6sIjTWhQMq0oiNA/mvJn
y2ocVmAc4ug/LcGRVr+2TPZQXEpGjYL4iZX//dzHimv0IH5mAEGTgYQ76Pb8oVbk23izFEJvvGoK
8ACM7tLZ9PpjyZZlBvOvWPWcCM8nmo7W2gsG74yOqqqbW4Dj0SnYRTNXPH8nTZ7hYsx7mZQRO6yk
32kcH3auou+NcFlhdlH8Ai1EuE3WsQ3lPel3fqpzHwYq5I/QT313w5ocQn8Ane8Bs+M3avoCYZG7
mHGFMbvriVxqKz2nXQYSHTK6zt9KlcIkOTBmzz+1MuMLXlG7coTro8HeSXDk/ePZFAVggVmta99i
ily847NGoQ0ZDeBSP34rvhhvwYxUnCBBCag5MZ/4mwmuT2LeJdOlnWDwaHRZxZortEjBJFfKYhUs
DyWAt6g8GuKaFs5UOnkJfrdSldf/+PLC0h8JPEA6WhslKtHnKBywGfoZ0VNWIUfAXhDigRLwLEdq
m/cA3o7RzVFEag+EiEcxJLF4YCsdzUU4hHTZweUTz1BnN2ffYUj2JTCXCZ9fQqnZm578aLJ3tddu
8qvwB/rKwZc4rbZaUUKo7nbHtrGwAXeOR1gNJaMo0hn7CXeHkI6v3lqEQzJXVnhu96tr7go1E1cA
Mp3Y/oub0jXY7NGddBTKqlANE2rSyV67BpxcQ+WhCOHsexrkfLz4qgSQ0PjvT3heGL1BYenhOzfK
AcAwykf/EGaclBfItMY4aXcu+K65s/Vym799VG2cbU7Vk68BN6mH8wvYjvLDlW4RHylXBL3jBD/N
KjlCCyE6ibg+iCISUKko+8/1URSamyulSArlxnmWdMEti6mnl+fXOIUU1htHA9rVppQoASjekbX8
DyYg8ysdOSfwBYpckXS3rw4Xuegp9MBTYGUpSsq32fRiGSyN0ij1WWMnCWoezsSxxjLNU2KgOGDo
oUe5wwmgwrpZadCT4ZHa1WtrNIz5M9tvwY+GufV2on9f0UtGiL3j042mAMzBQQDSPps5upAJxdse
CCrzG16/chM+m3pctYsxEKiIg3gGWQb9CFZU9pemP4wU52jgBTtRw6lVVnNdC3x/q0eQUzLGZFJ6
2VaMVdz8JcsnWT+qFstfcsFvGAHIxAws70T69jyCG4suGHaEykmDa5q8m1X+UUjOUG/nzfCpzK9n
UEPgdrH4K9pUrZ5NSCn6tc5rYe2VN98HDA0zWaDVutau5Hvq3hD1xuiGFXguIKoyWqIRNLiYbYIz
HalvNahBPt59+m5LaVGs5w4LgBXOg0FU3WyIUMcxH+nifo8h6oUAix8xhuY6ehSlJ48pygwp66k4
6nQWc/2V3iUl7kj9h5bF6RD4gT9PQR5aj4J4K2aR+mCd+ekK9Foa4SQ+5djV+2QHv/QxHqJpP1ul
bu6ax050tFCJnzNEmSr8ca4Ztdcq2xajS8IfMjn8DmPU/7tMlPsL/SQOxhUYOk8wvZvnNnAqKvrU
+q20q9NqeJ0tkNsCeYj6emTS9JRGj0Dh1Dvrri9aqWiHBvRPxWZ2hG3k2/j3I6KVa2wTc/bsBR48
QC8LS609tR23BZXhq/qgaVrfothQ/NRGS/xzjUi5ndV634ebqQzvBROJ1zN+3B3mg2D3Wfr5yj/O
KLZWVECcDHs6w1DOF806sF69YOaA2b/YeawgA45i28h8/BVv3QDnBBBQFL6tC5JMtaXnnk7UYgvH
QV1Baars5Xd0ScTQC5ZjK/7spYGBUmXUHKsSiimqCr9aQJX1RACQIWaoVS6G7wolzcdjbF/xBdPM
nIeApD/Pmn9ws7JYzTfLYqX0TG5AUrFxQUVKlZdgmgUKVf6Tkj1RZ/G5in7ZH4iq6dohHpE59V8X
Ab7mN+W9lToLdZqRG+WmhhWCbM6lBDQiq/AaZGv8NZZ/WkHBfSPZulssQbj3a/OH3nhHHmyryv3P
WaAsZucwglWNaNM24rfmxQBLCMKjKXakMMY31is+J6vTs95Jgphot6TpNWTeSzRCoBaW7HYTwAMR
uxd0OOBDdYbpvbje1PxUWmmt621FfUWSFJbLFSCZUax7wLMhn2XC8wStJL8y5ALjg27mpXj4rh91
H/2quMnlWI4xvQjMc2Y33BSqUkCSUhVWXen8ee5Nc3gMLxbYcbXpQC0YvSkOkKybLTXqEu4YAS7G
9TRCQHNEQDBl7HSpQBpPqrBbO0sl3SRgRuIm0d1Yo5Kn2gNEmKslJ0F1lJVn+6xpM2arByt+Etuc
nlACcJvwiMxtKT4B4bCE4ZlD9SPxBfZvGs4jcrI0MktPZ+Pm19rQn2T3PRM+CHotMBJfmlyykH3T
8/CHE+49uMaMhDdLBrIxERnRK4gOr+Z1ZPuzz9ub2yv0wgiI7vU+Zr5FlAheUQb8xBALAuy+a87Y
+6gQSuAyFUuELkM4k58bGMtPQgIH6KdD87YF49koXOrSu7rDM+5+/PraGCbiwONkkbGzoT1XR6nw
3LwI/bpKn1Vx2Y+rSsI4fFtBovPJnUaUf6jKGpa39Sa8lHc7e3TbN/hL4ENoyimvE6BaJGR4MN7p
NRmNaCPWTufw3ISvViyAwhYKIBzrl8VWY8ljKGXUYY+ouV3e124yQjC1v19N/+mJ6ZxvoKlTGeVH
TPA9yjlg0E9l9NVBIkhtCXAL9COmU2csjJ94pphI9ddg6PSLibO7b9ruda1n1XxBTVnzYNJIbDEd
JDX1mrp0c5hCANbjtYcmsaTHu5l9WFAm5Djjaf+s9snfBDOr4t42yhj5dsHpcGdRfnp2IZquh374
7nDz/+x3Ekr2lZrBsIBrDrVglcowSPVpYZo/KqBuVIL5Dz48DF623ynRyyFviDTEequXxJW6QtLU
60iBQMmP8hWANJdBxLW41qnFKTmVPW49AaNpSkIg6eivMDiP1snw1zXaZ/Q8gRTx6YYpRzRSe5HU
XmlgPTL9sNjzr0GDGG/dj4eL1Jvx50SFH7yezR4jPjHIN3oA65ZWgf7z34oQEoJQ13Bs006J1u+u
CSxPzsatmflaw8zl3FWs0Rb4mjjtgR4r0VJi6Ga8JCpkfFJZOHkIROWh0dh5EgIjqZyl88AgY6vL
XtaBmJ2iiqL0JxSKYcgT3IbfeplS7xF4AE2uqSwGARD2Y328b4KdQE6o3URcUomxJNovW/m5kWrE
2deEYsmN6s1F+APbS3s4dRpif0jSoP8GgHKIYaDqhVL7GeJ8j0A1u5QisfPvFudyhB1ArK87VhbV
QPXWrtAuTAXYzaUrZfUNy3i4SbjE8ANGHCv4MW1fvtNKvla9v+z+XuhzubaZ2kPtigVYGEDX6hdP
AB8kkHRo3LnlR+xCUy/KdrqKC5pJ48RasTOiTl3LSu4Wx4UhnuWQ0pa9iybwOALHUWvhEuppgqL6
2uUcIgni+UUDmD3wHSfP/j+AqnZHEUhZaLZgBMNRgs1zkpV7QSWetBNK/vIPzXmgvW18OhXRZaia
6Ihf3sOHFEE2tIiW5yumUkDQmT26YaFpAhsZiPQWHJLHq6GpHLdtQOI4bP0gwqKoxWpd2AsCMkJ4
sLeDUiWVoWpoVE+lwqodBzBWv6hrQz+kl/B2ho3LcE+NYvFDvEyDbGxmfJOCgVUQneJV1sAk53BE
GEXKWem3yHiSAJx+2S+fuzrzGnHvRb6RoFcXCCK6BW3HqlZEyG2EEQlVVZeuxOfru/RkNcv16fju
EMqZjg26grps8cWCzUcnUXWnr5lttK5WMYpd1+cgCH83mWx3eSqgfoN+9t988KEWjVhuWUWENjXZ
Jr/G2sLVEhg34kkidVY9ELyA43YUtccrPyE2k7Ud5/aAjV421NcDi1yEByrAzNs6VAqMDg/UYZmy
R4UXGISB/MqIO4wRfl8Yn5q+Z5GBQDFgQJOV/qRUxBMBCNWjrhRqtPWlIWX3CwRYN++siaD3n4Lo
90sShZK79H09wMYcGkK4zjQhffu/ztRbMp7T5KaYAPWp4Z85QaKQGvdPkB17i8N+PlRRDnU6wESs
nZ5MA0C9Tu/vyQWJZohcyoWWe2NfHwyu1aFCE+9vgC4EkPkZXrYiEZCxjy+bylX6oCLQ2dL9KuRZ
2atEQLScPvk+T8QAVfcrk8UrUHflwTzhuR340GeGpM57G+HoV8Uvjo2v4BAcFO9e7UqrhsOp3YKT
Fz5S6li+wAtGWi+hAaqCkYA9IuztN3G/XYhO6+03BPCNq4Vq/K1MxpnnTn3CDIa0FJPfyapQgmRa
HO2DxfIZQsN3j+LaHe3HJEO1dvB1tNVznCKt52l2Vx04S8QpW+XAK9Xu+6fd/qVuPWIRVz7hmhsK
15S7wrakdsNoaaaTCPY08c0K22SjZ+sO7qNy4gDGMocBDaOiokY9+zHjR76pti0H4YIg4MUvgU3H
Ghjk53yYLa55SlP19V8834TsHqpndCwaT3xzvsoGwDQ78QFQrewCYDRVkAjPH8LgFxnAQk6iR/2S
b+KDmy5WUK0nCm8wHSROolJq2GE9ab+/G6G9QO29GythXdRPP6pcOvTFIfSAESHsagBWrpNNcIo8
6Cmtde5xNHXNn1n/S0UHdXviWmq8UjAZ/RgA+aE3lZJwqNYwr6h/J2W8m3ZlJr7CroeWHxveIuAk
yP64t0wMAY/5TEuBjDs50lFBzzSk3T7ATk/XUkb7uCCRWFF2xp0JdiQVfm5hPrSDuL6OPV22KVEQ
d6F2gNNIdmSVSyaGQjNzj831HzvtDnG8K5QU6P6OD95MFw+7HQmJk80BdWzYnMYm1JNxVKTq6qQ5
Wohre9YIRZNaEQAussIVOw2WxQ+08ypN9EgFKwcxC9iU487szj5o2s2fE2Jyr5PpdOTiP9miMxvD
0zsJF/7oS1AUFxHLQ5oAtxhLrrJhBf9BC+dCNP4TSGFjqP5h3o9UDDXlYXWqdgdjz+SDASH1Qr/5
VTEqptwbqoC1r5B3g/WcJL7vsl9nODj2gBjfcRPK91avT2EISkfBiTde0q5O7I4YAKoFB/lOgbIo
GLJsF1ag8N6hmwJvk4bsGzDPDofsUq+v3tKAfMvH9QMoyplsL2hIrSO6wm8PbiBALXVDfI0m6zP2
Dn2RGcao7r0kyyqIFS4fT4lDJuy7+Dt3aR3wA00Q28dJ7C6TCOWs5fQe4cCXMDm1W1jmQ+tpzf7T
dc/tyauWsew/5ZWrgF+ynRJDSGygHZbPoojAyjVgLLFYZheMFBPFkkhK2ONZKkMqi9aXKN9zg3oo
6eLfscjo9V5Qg7mBllvUYFuSC/6ZWrqGdVF5es/mis6wV2c6VgX0rS3dtqMr+59Ben2ZhuOabd9U
2PB4N5oFl44d05blPcUafhfrz5s6NhKdKX2j5SD9PlMDZsMxVGT8IDZleDq3HrSosp6XRowX0J9R
0FlxJUNmeASvAPWNg126tVk1sK7HnsWXr3C4+iduByta0jSxGnVSgh08q5f/VDqQH0EFwH2dZO/G
/w6nRgitbIxf6G5SdXcuZGMAKV7OCmD1YjMicSnAEXme1ve7ITM1AjG/9d/N9R8ehp2zihxNPY+p
uQsG2zrHgxh9Qxh5fNI/HJXDzT2fqHK2kwFGGs0LXyJf3avqzFpU6vs9E5AcN4HdgrlTxnjW39Cz
UsB9APTZWTIF9g0OqnddxM9krt5zrk6NRv9b14HTjx6dJVmnygptJRnvzLUU/K76xqjQIPHdcZoC
K1Q5DPcl2T+X8gFE6gcZOpjALCwzpPb7ScCbuoTlF5ycxcnG0J9xsEzuQFcCOsk2ZMKobGYJ24K5
aAHHG5LnnI8/g5G/4/Lt79Dej5Wd6yfC6WAmp68oTzNajg/ZYzYqtDfXWlwM9FaCD6EFQU6W3Ivx
e7fwF0Q41xb0SNprhNkzybpvu4nOxSKhQ8qUqKSJRHI21hAAe7zHDEWfeHqT6zGUy5lS8Q6SSY/2
44g/nm9oxGP2hDil6I+ht18TPq/lPthmmGmJ0V4fW9dI0/7SO9qKM/WKpVHDU/T1OWje4rdbE87y
Q82MX1YsMcu0DzPH9XjIv4iOtaZQRNeytSKk+lG/ipASVqJGi5DgTG8X48bZRiLmc+OZp7qoAoBD
rfNmE6AsCjanmwUDolp6trb6C3aSUBlWR0e6zB6+J2ApIofBYGQtP/LzMuBAYKhGEzmtFdYDs7FJ
vqPDMNqZbUk/rNZeSZ/bVbm4gA9NBqOXktHh1RIjJ8ybqpePQGO+7ohE99JnehBZj0/2TQ739cpG
uV4rOVstOB8JlfmnAC1tnCDOgJuUoKdKdXj0NfUlRkomBs8c86YrDgrFjI2/NN2hF+kue60bKE7F
zoBbrXr+f4hmrBv3I8OUQlbGEnmasiNcgdNQu4FWtS9ql+UOMDf5azknXl32Idm0HLynuv6JDz5o
mLw63y8kLq4YXnl4G/5hc5j2eZPzgkV096uImsOSFOZ2TR+zLXi6il1cOihR/BwCGect3HrOSrqe
QDpKnmFGHVhtOv4QDeHCStb3U+O4Z9kQKMK4c2u6Q4a9DUTEQLNfMJRG5U+68w+wECuwc3CAiISs
9hafI+JvdSTNepvqK/T54bKXmfw3GDRs9unpmGBrcM0oDFsRdqqFfwygeVgr/ShDls5/ZtwmJiUQ
6DHwrttApknbCRYm7LAcJTlN7gImneOFQAF+wSMK3yITxry31HbzehKSaFArc173w8ZOV2iZK7wo
h71oSTIxJOeHgQ/PAlGj7K5RCWK5ecDKZ1NCXMi59+gXxxll7aQMoMkjyYBLz2GFP+mWpm9KdAmT
NpnN65TqWy502HaF5bq/7umMWwiNNctj0mk8/CLcNGehb2Kd7OnfZJ4R58WG3FKkQv25hMA5wuXt
9hfa7YCcKZITOkrpvLLPKj3A0TGGObCMAmvt/v4bP9dSwptBoAPE0ExbMq8+JanbEVymU2bEy2QL
Csin3f/WY3loKPxZA75erunW/FjAvKaE3KAk3DmCOPo0F75/FV0QOIKODSchLBa6TrAgWrbTVcYx
ChoHZQb4EGVx9GUbtq8/Zn0yVoAnDZTc6b+h/ee3sH1fYLehA/hK0gLt7ESdYPKJIChOA7uYwyBl
IGcUlv7rpqlQFFu0VS7rDOBPbK1KwOY8SpERS8wpajvj7vcSnWoRa6cHNbc7BT2eCyexWO4fo+pi
QDcrYfPpoW7VKA0L8dia2DTGJh7aZAOELD5vNpbgPlhXHa3M+mWZgwU4o8vmOYiHY6vuL1JkiURA
232DJ5hMI164pdfsn/PKTv3S0bsqN/l3d9TddFC5BMxioTqeLuFNC8fToAl4YCbEe5VhDTYMiQG1
VWYBn9IyCHKaRdnnahOJxOClM7aMXGrSJ7lg/zMw0sh2ijb5Zb7+H+FGGDeEBXjJaMVRnxjnebF8
0MBHvAXPdPPh/ZgPzPyGXWnmUMDWo+B05RCQMJXBc03uhnEQSxeRIaosyjbBtgohqfmUk9Yt988A
aiFw7H+CcmvlSt1m9d/gcRzo/k+jyDrsrv9ok0dtCKVa9SXcvlQWYl27TLQkOAcbVmVGM8NdKSNg
m2IZzwoZJJZvQ16X859LFWyfMQDt3ESyqDyxwG+RN1ELXHOWhD+MU9YIObMZkXQTKme+qvuXpROZ
G2MmmeO5z5VLRiNQOY8Ewu6atRALHEA7o1zaD/Mis6UF3gUauCzg2pMg85qAdmkIq2cduIP17297
b+X+WogZmL7oy7/R17GIEO75VplR9TRDeuUHewP8ReUsWMB2ud0Bh1nh8qAM1vtFPmNnHY5eo3bw
n/KBYFFHF9bdOFlq0EGBtxu9LnVPb1QGDWGYPHFq23Sh8szvgqF4mS2Synu8hz2QNeDKgeV71Opf
GOWGvfmvmELijAuhcgQT4GSjUeyDUMdDG60f/SUw3Mn0+AHBiIY45lJPeNdWpoGZGvcz6dWEoz0y
T3sxb69f1kLoBh+BHh8EXdgmjq5NSSCfcMQX04dj3w44HjXEz/Xw/ATz149HPWIr02r/UkcHxmiE
mLEdn+yKfwyUxJq2UtzPHPftBSCs6WkiVPEeLRP26H+Ss8hCUKx6bkgZYy59Vh2FhDc+9i9/b/Yx
vyD7CZjPhE4HfzMnVJtYgxeNYXKpkAK6Ix7Pi0q8bRU9J54e9ootSkhWEZKxzY8XZYBz5vnGKVF/
mqTDEO1JKA4TdLRviKFkIL3dx4IwHmYaCcsGfzuoeCiJ9lZmt4qsJyO9uf9JpFo/PfE0AxYjvtpH
uWyeM0+C3jlBtBZ7RtrWD2wzo1B3jaqUqglvU9GC8QZeuEGiV1Rpr9FJQ7sXEHORrPhYCH3JDBI1
6zTw1EQEaqfInxLr24oRbKtcX80UyYKYb0UJHtmUz23JpQvLyUbKGxilxxggdXjvvRVgPtNbExRm
BxKAdT1fULphg1HyaEDlRxwLWMwV9z4d1tdLngoAR5WRUD1dQWnt8YyDStpXdMY++6jcv8swRcnN
oxHaAraWVg/DVammalcFb5ftlTiJelvKVFsmJa7ZhVQM7agXmerld6RrmG3JJ3ATgw91fB99BhV/
Hz0+E20f2llCkmffcCYB1a1mtSb9h4I9S0CazsnUwmgGU25YukmN8fpTc+TwwxUNc0Njr931bBS9
+VXLiOsRT+zFLqWFbxPO7Bo87Q/JJGBdJTUJbDPjGDKubE93V7/PhUkR3xYuaMpzzxkgQCkAen1q
4BzZRR8PxkCuopx72Vd9I+oEDLrPqqT5pElXXB8Xu22jbyHRzf5SLXKrn06KUSrsXjgsNUnPZMG4
zTimJXYyX6zYed8KdCN5Qi30xKGVTqyEPv0XVq/qi/MluEcvyIilTPtJUAlHlpKN+bJxiN2WZj27
oiP3Uea6Cn5c/5Mn0RfAJ9YnirChdBf8QXiUtsex13ewF+jtqSi93PaDC+5IfwWMqJHx5HF2nvcu
bAxR7RFNsADUcqMODxF6876HwDdKgoXA+/KwMYdFofvf0p1Wcmnh5kB0R/kKwGg4O2Qc8YRUJSgc
JfZBNbUiEczjQe88pVpDXr2ILsBrI4sU5veBOYJzQ9/b5P2e4DEpiSRudboQxq1uvnSLT/hvoaRK
Ew4BBLHEtMRJFX1QWIMeKyxZ+XyWAKXK/RR9TnfmYVR6hyE4fUcXN6jOQuPj2b6sb3vE2cCL58wa
siKHDAgk/XBPwV+6T1GzptpCLEJQLenaBZBBedqqvF1MTdyyLu66nyJ453yqcF9TLklfrQolHNdu
H6FCgFSP0dKH4mV/z4gk4ya59VDrBbZWrSjOIbjPbJGZeqH9gA59LvT1pOnAbc9XUaiZUJo06nu8
I8Nwuaa+GZGUpLjD4NyGVvn00q9b62FAH3tIgvPBsVdYl5KyFdcENxKtEiLHzGhnMcW4rWp7CtTY
pHi8tCgwCvCoOgb1+rcAO4T2472g6tCaV/EQU0Zrp4tW6C4/qeXzUQT5jPRbCgnVKBVMtf+lw5WV
0wYHWEMX0PLCPXhpR7T5phuUgKoqHmCMcastxQVov9ZpMsMoXpY76vkbC/Ra/0Qr1ZLIVloEZhT5
366ERafOp8sZUylTvq54ZqOJjbb0VApNWdbq9yuh4vqa0AR4O/jHuyaR8bv2jaRy5eNnD2ndDREO
pJSYZD8n3Wx8F0Twx3/2zcZRAvDyN7AUErVqnvm43G8QWDgwgocoDaBbm+2G2BkrP0FIascZP/eg
6NpaJd0tmYNMokpGnIVvrneCnm+CjyiyEbhOzuaHYhzkRIVBzrd/PRqOEi6SB8st0nd59MLZ3lEF
idSaancqMJZxCHWKlbiSnvKSSc3ybVsyPRRc+zJq79IUPKA7O2jQYmj9xOcRbKhVl4KGbDCUa5Ki
sFehQoPPiSACBUgfEJPAbw6B1C4K1UTIMb2jQDgDdU2/y5E33DvTlCBqugOUJSOfcbUs8bxgrZlc
p8T96w/BSJZ+DjmHY4w9Pjc5jb7c2qGIxOhWNljWNdp8bE9ZVogO4TbNv9L0bTwmOfP/8p6AmO2t
6iNk63fS9hdG16xpWUc8ygFmYEQjSAtbx8UvrDOCgeJnceZ3dWmliZ1m61EXfW0ehmoW1oRI01qM
dB+AHYLNFyeTivMWHlm1OC5Qoddj1Mvhduh9VACDLK/UpufX3U3Mkg+u8/frTEruG63zH/Z7TLKx
ZOJWaQhnvYXb+yDJFNUWntdD9cN0m31dGK55toySFgabXdSiqDnbniQOU10/c3Al0mbfXnCnjSUI
Q8ib+Q8ChRAuh7hQELhW+mhJYbSqBaZamnpZqUYRpQcQgqM1zVq3SqH3R+qe3UHxpLNLqNkoavCL
A/SLdQ7lq3ZZxIIdkZgTV0uR16Al1rXkDgYLx19/j76HAheu5Z5aJuQyXvxkhb1QW4l3KnwNDUyH
CW9hJSiPGoD7Am1ChNbZ2dP8KcxmE1O2J91TevWMhA5uvUJ/n2ANKSlO1EiOtw1TtjHcSJRWZpTq
N8PDNnUUlcy3TE2blUx9oYp0CXANg9jTi9LgECKKQkakjua773WwulgqWsL4SFhb/jDg5kOSe7//
/rll53TC+yXR3gs2nC0XQJ5WUI/jm/O6c7u31356hAkoiP/miFvzlfhusC9Z81sKeq8WBXv/J5Wq
Dg+FrSXg6erOvFYES8T53fxmMj+fxDoVMWNn9TbFHZ4Ty1hVHX9RW0Z9+9f3NVnSRsoVb4VIyfdf
i2u7T7OResr8eSVvMxu4OdfqSvT09evR92+GbtD4P+vwjYJb50KfCWByOxKFYtluV85oYs/SV1dY
dRODzfBCg+TxR3EVPuG0MXIyeLOmLYXDS5+a1gqkOQYH97YvQ8HlTJDSGtm3jTYqsDNAo4iyIKLH
KDOq6OOQ1UvtEQh7oEnzunVdwhbWS9TvXR9AnfnchJLSMuqaSDq1mm0vU1vzNPZwOA/e69tx3i9f
26GEN1hPVgy2kNw2LFrg4kGx2HLMMaWKf2zWfPgpz14hGvYVv0MMcdNcKrwTMtIaI3lG21JpbgUu
wESaiDODcTym0LM73c2y5tyo0JWjPhDJEnUQyR5iIF8RM/y0/4mnzHQr1F+wuflsb5UMOHCxAB/7
iF/Rvz6zmY0vTKZjs7De3dJJQZaP75GAEe77S0C6JgBtiXygLDXBpPardrKIoAs9oOSRu/ewJRvc
/cxB53btCC1vqWMgImJdUxf4+pmzGy4WTBRocdA6ZvUYLQE8cIyMF2hSgjMPDRhdXXxBDVuWhxa+
NVO1kzq6aMep9La8FtxMZyV/MhRkoNivBSDFjsS1E4RcXOHx50fBsjNvAvaCYhLx2nPZiRBjoZRQ
XluwAqXCd1sZNuuSbSdgEQht2afrKccT157WZei/34Cx0xVb99UBJaBcjracAYIUWOdRd9eNoRh0
Y9SQ2fg8p5C7VdHCOpqvyZDGqUR/N7SlmEmesTLNJwjnGSipriEZ9jsykHnswW+7tU4lPj5qpjx4
1de5gQhjoLCAuYuh4Ltu38Us+C8KT2zW4nS/c1/Juaq9EqyMTdL2IHBFrjSQo0j8rjv4Q2BrflDv
e0NetwmY3iVohgabx/orTUffGKeGX04ESBQCdrJo8dJvYKrnu67R+8h2Dp1DSYaf1XwLp4IxytUc
ChzK7I6dhT98qGgNZXCbLCtD918SXpqLYGDOGAbCq9kV4J/1fuGgUqlaSida1a+vWhCGS+szRWXA
aq3c0U3RhmiT9HRM/aQWxuCK5zkKgxrLDnpQLhVQpy7wnAsXqMTGGOH6u09+Ni4FFvFLPAsm7Lr5
Xe9ao8uMneKu96k/9Ms2SVmNrFXa1K7a7byDP8Nrao6fP5+euxySlrMXNBONAMjS/E4uyRTpw8Mh
ZNR/qDYm7YkghT0W4Yfrk/3UKghfH39WDDOtH5cuUY1GDhCGcI2yRTghhfdLGA/cymk7nNzgMjix
1vNOl2GkvmSK2amQhHQej8iX9gJYHlptD4QTQe9RJjW+modiNn/70LSxFeoR+ye0zoh6pItmLQXR
RgTFHUo8oi0wpRjEy/fZ2SxlnE9nuwgx782dvyn0XQimMevyY5a8Ky2wVHeWF9jCobUHMjWWPFUE
Sn10aId2sfjkfq1JS3Mr0uLYYKQ7lBKwq7XTGxYfrFhE56Rwx7tD8ZweNKd6oviJXc0vgH5aQ0Tn
oO/sVL4ptvDjkPxLUqLURmdMyFkwOQ2Gp96mfkgqFO6pMoNwM8gw2jzthsT5rG3CFwOAVYAV00n+
I73WqnP/NevUZ4Lyjo2GOdBXohUfTHzGs3vPZiWa8ATYfyEGJXLWy6rPsmxjYxeL/MwV/56Nysu7
Sz++rhkFbz825fSLR7PRA0yJ+n7hNQ2OUrSzCxu8uNnOttG1v7HD32df1nUpEnzQ9Tw8V/GgaI2E
vqUw7cjJaIylxII3K85GZ6EnciUy3tsd6uy4QZEpJaRBWfo/vFz0cZPaHogDbAwCs4YHSSLke5Em
N5VI+ZzsrCKfofsdnhnLf3tRjimOgiGog8yfC8Z3dRIze/yDSB5ZSVh+mizxQF2pn/LvuAT6Wq/v
IuXciqdPYpv6xz2m4xKaY4uZ++15+hOzTEtrbM8kwEt7R9W4bA+84ptJ/CAOCJjVtGA0JVrWSyXS
4FwhfEgWcnPLmqWFLgREo1/ZnNBBk444oDOf7apH8kiUc5wcb9FS6OeJGusemgpbktzGQvyRU4x5
Z4VgmpKfX3Z4bcmm1+Ys1i4hJH18EhWqAigB+tphxNMZSK/NCC9MleSrktHLenOzbz4dELxvhMsp
cp0NhIgf0o3GNGSzxtG/+5kzS9SXa2pscGrHIeq8pqB4baAUQb7doAg7KiXTtuT89jSVhYFKBl/a
/PPm74boEEtxlQr+obBqAV3qihx2Tkz/i+pq4lT39OXOAx6fc2dAlfYbj8aY5Tzc17ulyz9IXOOw
k5o+MYIinlLEeeU6xQ9nggu5957U8aPXaFalV3ApWxrLeUQFiOLh2sndGupFzfHsa9CMMny5P+XM
DFz8ZGcKDinEHNmZkm3JG8+ZoWkNbiL99HDiqON9AF9LeofeaBASYHU9VhNrgK3vRzFfT2mJiEPs
51fdJ2sPWyLz24O0bEfUd5X4eS+xvX/fBbptDTyZQxTgdguxXaw0kXSQ+jtg7KZKaCj69UYl05KQ
V1FAc5hYnUE4SLRsv6S2ZOBUJDS7Q7x+PCdz+kIiPIfgADfEIHHvP+eYARWW5iILhu92PFx6jTC3
Y8obs+Vpy0aZpHg4h9ZSiQg7pjnymrvkct6nv2MCSzdFolcWJThmhtiGoNtawg5qiMPjsavgA1jN
TnLwHNdjm7itJX9zHEVUAxP7x9HfTQvBAhcplkENBIdsaGvlHK8AvTXZmnqwvAFOzuBpOlPcvS2l
aYVIRK919ai/iid1emYyYf4TfV1nEIYQ4uNgHxZAqfTT5OBJSfBoR2HiwE0mrnlLrdbh/r6Pew4w
tsufd8SfymZjvvSRQ50NGEXAo2gMYOoWdxJymo3nqE1bBHx7pZYXHm2WvCsW7hl8ozJ6lgUJiig4
v9uMBbcMGqkeAksZ5AW8L3F5VDax2nabIZ9g0F26DEG06moybZf26aBfi/p9XI+gaH1TP2Xnm1EH
g8MOzXeS3Qu17CA/1cIUgUbDi5vLXhe6eDqusrOmuCo1wG+Z6MGRHXAqvDaWZ6l9LwlH4MsuEPiw
ldUGoP2I0DPCcOHzWq51maXAH3obCsIFa5W8f1QsWzFgaCo2Fi6UoluPuAHIYt2xorObICUJq7Sc
Fpo5zKLO+PyCKs8iFHOyuAQYMEiRkgb4mxhu2AmpIBLklN6U8l0xf+jC/F1XvFagRQ+MMuUk/0Vs
2xgtzStPLjSn3jQn2lkTnZ9tz1iZMDrMolToQtPgDh2E6sOfad544p8thtWMg9RNruI4Jv78qrbm
1oFm4uAm1zoIPpSRcsi/VViyIEYAuz47bImfU6QKg8Of3dOH5JdbWVF0QgB6MylC/mEMOtqpMThk
tV/CHh3xWkxCq/62brB2FXMUYGrsVmWK3MSDo8qHAeOXYkkoUqAM+L4SLssPJ2tchM7Im8ChPC8w
QvzQSm9FnqE9Y5qbKDpYpghgkY+3Tog46vG7wb9Idu1uD8OoD91/WkDWIuYFZpuoDdxggfFT77vc
yF5m/U8Ko8y+LCO3OUWFapiZytt8AggvY1IXtT3CnKiXQsGXr9Z91qcly7eAD0XA+4LTO30yC55N
BSAKhe5+lfd9F5e6njo8hOfoVMt/pk4reaWGz6gYenDhvDJGbW77r6ubryrBfs7yWs8Gt3AytRyD
6FgF2ba3518C1PZgv+wOzxAaxHKvX9R1ulZdD02ZC49t3ElIR48JVbor5FC+6jsxh/CyqC/zROp5
/Sk3dM/2PZcR6oFXdXV64GbRJWOvinrPU+BjCjMB93yXyywtyFMa6KZBjNbd5kUw6eO3n/fwr8HV
nGE5bEah8rM0pLavBAbcVPLFEcj6S63nWkwqqk4QwnYsREmcNxwxPYogCbIfmUu9uAeycHB4dHzu
4eJ6lwhq7SHbBnN6ZIyZuRt2iMTWpObWr4284DItuxTUa3BnGeBL7vU1xGZIhlslHcyOZ0YZYOUo
rS37+GaH2pUfJIB8WizQ2BSxxrKyoGKSHhZgwqi1thV5muviZu0GqOgnWGxF2FrqSriYOlBo+RT7
wsXgu72kOQasOLtIctOpukIFJtzjVyjx495NVxN228rQ7QKZIW/Nff5neZfw38JJfuY0EX0kTvLb
7QmP22LRySs+hvR9lxCWML2fJ5CQ3vq+Kqn96gPuuExCAHvzmEjPYboTB+bl8+u4yJ/UlZURU9WU
D8iGjJkUuV1noVdMsMDOB8CBSyekCO5pVyUM6MSJTFXR4pEtnE+le+eZjzhCKFZcLe30XphJ0pcM
QDN0mNVD178oYnVUgzIv6WF6IHXmYeYjMvAW4eejKpF2P/3o1+ECr+K9S536pvF8qtxzeorz7vTi
43AhN1FZoWluVh1FjjxNI2stjLwZYRMNM2TWH/S/0ul7wGQgQFV939PxCh4S6faHMAAaddjO+mr6
XK860i9f8Xrrlxp6dhmYKhAwgnCea0emHSpiPHuig4SuJIu25WHAPYinD5KDkZTx06mi/AWne3rg
Tu6VSE/S5/NJAileQ73eQ3PYUkEREkONOswU45Sy7gdc+5UmwgEIei7EOyLG9VPUVvwq51dxlwNH
ZRWV+EvBWlF+pHxjBevXtZmbuztxaDeSyz24aXcHmL1oXI3f0dT/QXOAlHlERReCjG92/0HpqLEC
w9pPUozysmDKyOHXNwxs1v+VIWEsLHyW08UWODazE6slwBgatKmqdqXXtP7ug8LrWtFCKTgZq/nQ
zHP/ChZdw4Eip0zOKmE9M7j4JeYJPU9oBB2+af7BdV0Pva6Xq2WNIKIBC43nvie4ymjBf8aoLcWJ
q4dkm9iQjO4iRCCFkcjrYvU8kx7oeD0xSGRU4+6EjWAPC/8d5V/Bc8mXWynBuP7ZvZSUtUEdmmbd
hWPBCesHeOwIXvuvr7Rqz/DLXlkcOKX3rzkiMcSSZVQrIVtd6iFBYFYW5dpNfb76/8JSeGiNJFbJ
aedQh7ec9cMgZo32Kz5gY2g5XcVfm2nUjfunKvCDxWJirGEA8deQxrqjbZ2rZeK1bRRnBukG+I3D
EA812faZdxSoNONS4epVjeMXeOw8kRAF3wTyFZ9i0FGKezKibyh7dwQZe6z/njO0wx3BLvACXMzF
c48eg/RzWujgGt9sZhkKuh2oBWPX5uPfQhGJsg/Ynm/rKaWIP/hnwzRfi8GyTs8Yk7KBmd852xaQ
1EGBEyBOxEK3n4RNkLP7j3B/UbdmlcrPIeGY0wYS9XOC+hztnj7hAbt57t4WsRrddokDDtF01yKT
695ZmXEXM8zgN8mTjNoe/waIc54xABuL5NEGsd/RHfO+0Vczcft5l5SIFhtM+QWhFRX/Xaf2wHqb
s2Yquk50NGnEzPzlSVngUwmQEx8/9DtYeYIAkGkebnvR8j3BYeaBvXKCmRXW/wT+4eNDHdhvZ/oi
D1cHsjoDoL5E9ZQBrOd2SQMe2j63Corvs9OjvncvV6Wm151tWa5lpTueYmXucGzQ68bDw22elqUo
JHWbRpbALkQo/gttVO7vQy84jrAv4UPJzofQlG7ZApenASnQL9XbkMGyWn31fAifE8vam08koak+
IAl5w/broMPLw+ZmKW0sN5RZj6ei0Ky8nMun76cBI8mxu8VD4pcwpJiPegi6V1WZqNh9gVjbMz+0
NhTxpT9a3IH4nWHIU2zAShbROxwdnRd2Je+g938GUn8+H4KHmAG/WOdV8ksFbuDLmNJYMF9OWiAd
yVMTWeGD0r/ByBecvNKtZFMh5DwDDyOKOeGoMa3Yqqg1Pkzeh1Kfcj/D+ELinMraO6TDAT5rWjdz
ynkn9gvnX5zfzCahvsrYB4XpXzM+Uu9kpBcIAXRHZBTF+wX+hd8izH/b9HbtsisEpfMZ0IPb6q1p
zBv/TP+5ePP0+423BXAK0YZ8TVgKPHxpzLa2BMa5DQY0mnTo/WyAQdjDk+J53sE5sFrjL11Q/WNP
PMNc1yvtPppsXLedLPq0su82VqOm0Q7oqO8UbvQk52D5wJXD05ap6Af//cNxsh4XvRjjsnusm9SH
FG1k8pWSbw3GmvkfRR3S+naGk/vZkYlmWTjYlaKGXHEaAeWSErp+SIIyorTM8PCjUOpl+WVhHvLr
06cMcMAKbwIIddzks+HfpNlbrPMRJZpXZFt+ebR/OLKoLA6Ge7sm2qG5XCHKwKofBzClSlUr8d8P
tq6S+NxQE7hybptJiUcQ7BrItC330gXQyQb5qbsLFjFOT/P41BontQnid4YRec48zyXaTW3QS3H6
4yoXjHSdLqwMwmnIJvTN6GnMn/YwacXwrcvXks6sN+KoLWGO9jOZpRvRt+SNF70CpQNhjdRFCUVu
vPmMsKslr0Bdd+W1G+Y4a+j/LvXKgBNWbvfx9S1O/wowIfNV3DfKkrQU4hv4Z52cnhHXvsTGGYkT
jg8ZELPs5RG1QhIYh1x02n4eXhPBRp0vgmW3ewDN9m+Ozr40Yzj6nDZI1OkBbVn8aEtzeLWixpDS
nwIYj6VHN/D22/zq531Lk4JSAXW1CAF1dz/qS722TO9is2U3FMouxYnNrwyfZLQyZJMHKrg+d30k
LX9E+tPIjtWG9O/IkPjy9rG0BM+CvWBh3yE25c/jmf4S56e7TtT2/9qRKylKsrXIr62FXdSlD+SZ
/oAGVPuTfWou8jcP+KMYPIJuG0yQOz49r+Zg0rQ5ka49lDDL2Ipb7Ba0HiJKDTj7+rm1WZSNzYxs
eZOwTCRIVuKruhTDUdmHuztuyCb0YSZulQUTpd4Fg4A/VbBwd7nqGdDaOD4pv3+cABZW59fBiyLN
N3gXYi1W3t5Vt7OmmWhkgy30hc/E/CrI98JqYWJ9vXlFH4NioZUsPbYR3rZ4TIOfbNDvdYiyR/98
tvbSTQPkobdQn/K98pWOIn2vrGOLgF44lHAfSEWadaJ5yAZ6kpPgfM0R1/BjNX1X8BOd4zwTe558
aJxCFro5Rwoolv0MCHfnbpBxBqAbTNhoBLCJARFIP1d3K8nebvRbqqmXkQOtpvFeS/X4IhR8YYDv
3qndW9Aw1PUmvUMPmXDkr56YObL/2gltzd+bSaI8R+w+bsSzNLf+wkbSRqnyQhhc4U8ZgvMO0Rqe
ZpwlMPZ5mN/0kr2gbOY0wEKDx8J0iHcY60lg9r02b83jJ4Ry01KFaLVoA71Oj61G48A9azFAxK49
lvfHjBPNLmVQ64R2hE8BRmOUZIa7krhvc6je0gt1Tg9yHmW8LoHYi136m8Br6zhMy3IDEMoq19S+
21QFXx2DJp2dPVMxYcb74bQCA5aOAxX3WQGd5VQJVa5VRfGqQsba4m8oez6RPI8j4+DaQ5PGng/q
/OjlSQj2rxQvwhodu9LxSC8QTeLNco4Pex1pTd46W7YPV/fZmqfMWAGl0kREBPRv5yNvkuvsjhM6
J22mV2QnvF6J1bQEOBEDaOSaLou56HwdWD55/mBHDWf9h+UOb2FyBRhUP9DClsFNl4JWpCGdEZDe
M4/jnwWTGa6RvDF6JGFTPhgVFb+trDCL5rHAKPxqmi4DT7L9dX6T0YR2YzFFAPb2l4ihpRqC4LIF
my7dBecO/BLoXqLHP2QTkwWbqmiwx3LzjtlikoJ8kHWXfFvP3RHhYvXxX2VlLOvMvC24mxU2WHRk
jod6jfu6q1NOnUIkbaXTKUlWWPTO4leOft9ICOOU2jwVy3IR8SIm2uoMjaOZgfqLzuOUKB+r2E5P
Xr0fQW6N4rn5d8nLOJlDHPM9wrZOp5pakETqHsaAJAg1xAQmJwUorzZFgW4aA2oqludzZUDUudGH
p6BBqOntbf67JsbOXCX393xW8J+kTpO6Saixm9nfe13R71yHMz6+RGq0icDoIyrNsgd8K8apDZOg
r19n/VwZj0APOjlFQJuOXLzfcs+kjfSrfv+ewZCNOjVDGZBCkKXxejwdMjMnGC42nUPNlm2rJ7Tz
nIVOcIk9eRCgIItTGgQInWHpMhR6psC808rnoKBatFODmXtujWaDXTjvbqZ0bSGvvOv8RbkXjsdJ
NmmMDWbPzU9enCWPHEVF+8WYoaeG02Ca+leduSY1ub1dtwkJbdw4xYxpLoMn0XZEjT+xapvQbgdH
nx+ZtgmQKQzqO63xDvxm0u+RtVV4Ov/KTyU9nLvyHYc9F49lIxGuNUOcOwgTF4plsI05ZbwRUYBU
evqHioU6nj9YHUa/QkCnh5/obe85ZWk5B/FtjRjz5cvfLxZM9PlwaR4JDhXTTIqtTWVso9S2QyKc
m4KmzvFj3oP9EDpkXDC3ZtJM309zlEbltYp1JzqDPPvfK3iNbbA0HtaLD1dNGV8dmZzEU7OC75a/
APQ/KbTechpSZhR7PpKWS78FtHC/ITOn64NiUb+36cwKhxNvAqeTxzfJ3rI8stMwdBiqQKH0EvsW
FBKOaRyJMeie8pOlBt0k2VnleKLzU2KDnt5Str6X/Tmj4JCqYggV5GbVfsROvQrp0SOjxlkZ37dQ
Le+ely2674JDxFqykpuomLxdKBgVPgzTRmZicbcxhWFXjgRI4wUywFjp3ZRP3OKukjO7L/CoXIlt
l/8irzf+mo0+97hYMVD78/tAvUlOGfLfGVgvha7Wir18DvfN5qyHst/excaiITip9eLwlrUASpjE
raeAP76GI/Mx2GLjcSlbz4QliLcx1zYd+stPTTm4yPGT034y2BRAuMphk7FIVYP0wd+YG0L9fnW1
9m15ch+sypH/lGhgRaKfvSwnGPpdlUbn/cp+KnP35Z767UJT/gG+4fZc4+kjDS7TNYS3lpOmVmu3
8ta8r3eoScTCU1IN4Tr3IY6uT6Bo/71qTPGxeXIrXIPE7bqS6UFahn/NPS00RSzEgxwrm38IwMru
GCz7xk5HjcTdr6MU/iOeqn31S6PXtqsKmVgGTiuuhHQFC4tbdoaH6dVihL4pGo809BIEER6ie9Vv
sd89dhSVbVJVdHJpw3xr9osfuIcPEPqGhiMdqxmqlCx9X+82RJJAEvFpEcuVbF2+r0k8shdVCyPg
Aw09dNH8EeEsOYzlQ6gwo/Arn82epO4NR1zbhqUfAsrH0HDbU3zF7F1d64HfjWwClY9/XDdVEvLP
WKY6c22e1OWhdmCnXEJ9vDQqZgbRjSZdMaVJRNsEGGDx9/3wwiKIvBmem2Y3vetNgaWa1zeczmvr
47NPBJ219qV/apHjp55wrtU+IiHyFZLb15L9pMqSj8n7VnoAiCNpuWwO6L/pmFw4ZfomlXk5qkUG
9M0oj3Rt029uUJhkZiBnzDXzCZMFNFJuOmNeyjgzaaPcQFbAvfLnOO86Jd7Aem9/c7YIFLH3NEKK
OUjNDKJDOtOvSalUijxKaQZjZaz08fz6YtvebNJ+9WUjMbG0ctYSYpB9Yv0lasHOj4cJ514u7Ml9
3eX+7ckn7i+2L3K0mhYTBfLRSqNWpglJ7l7XrEq+SYTcknjqvBrSXlMdHPeUQqG+4Q0oVX3Rvde6
haXN2eDYqA1eeJAbKzP4BdZXqlU0hXee7TJzdsXdrK4g6jVsMa0qw7rpSAoGGqRfwJIgaO1S7pjk
wSbTZCrhaLutMLy0oIDRwiV49bRcnMDCYuaTBvSjZUxpN/1YLDJVrR5f5rcwINPUKJ+JFM35Bmm6
nhf7+2JXDzzH9raANyG1NzH4aQWE7a617T3NTsUtvHR8bUCH6ujOOZKzkaRcwgdgaHLFLSA/b9wn
pA67vEuWT0Dfx9ygqRgalEjaMY8hHmd7kWurEzTQhl2/O65FbIV+ETnjrqb/CUS7PVT9sB0RdFOQ
yJ1Hn3JmDTqrLAXJ7/f4/zMX0Ir12xkZun1nwExwZ7LzaKE+mH59iQN8X25SBm9sfQqMcCmpbCjg
nhJXD7BxaxKlDCuhDJWjoaQCjStjEbmiNJLX6+2Q1hkYV8BlG3g/E27hPJRNVa5xCQRFG2rNxEBL
+8oVnXXHsi7INVG8tJqkG60r6/jQcLZRAOiTFyEnmFkHJiF0GNHII8FVMUi/kS1/o0u7eBM/tuss
6p77zcWKZ9lfnTsE1NSKn6Rl1mrpK5bRuUvEpKSoC5e5l7zaEXSiLyE/D1nI/H+7Lir3PKTkwVan
3PVNhkLChQv9YBWQERvtFplq8f71yU4dnPmKvmLhStFtItz6cworRnTjNKBSsCr8fWIg2bbcelDq
PgHscB+DJER7KqVgcJr+ncHIyRhJ4t8BlOWf5xtpaAjj3zzyXXDmqJ1U1Mb4RDaJ9x8HAIUebYfJ
lxFJD/RYbhmdXApGP0KiEn+dN5+hPpmTAMy/hZTNTvPFhNqVCZWDnO2CKT833AH/h4HYh6QK0p4g
QoNLjmDya6FiEfg4B1gOfw7a3HWOc/9fk57QD31VtLnLd+pSAYZDDcHGbe/fR7yTLrXs5xnCOqvm
54d0qV0RDeKKpSlLgP7idRPGx+fZYai+KPfDjNjj818vngNzkoGoaycutlrnLVfDL2sN8DOqsOUF
anIEkAv8PSJLzVcdxcn2XpSZMDxvZdwWsJ0SEzV6EU9POUgZUaGZXHE+ByUIfKHk74vM/DAWi53G
p+dY9QH/pqZxgcXcmofCv6my8N22pZT/meaVSL/HRO3btA7E5ltO6OZ9+PGbuUf71iGEZHUKSnEA
uStDkey3lzHkKhRkJwJ8t47rufxugEc7s+wCF8kz6Wk8V3sPNTA+cVR8AHyDwCRItUDfbHKMYYVu
ac14qeZHZLkd4nRFvO+Em3QST+2+yegKGj9H93f89ecS0eJvzyolK3fC0qzAlK0irCKALZJ9jP1H
HzrDCYn4xSWhvLCdbHXzkC0TzO8oSSvHg0BBmHqHFBxNbh6Nk4DAQRXVU8cnOeiJMPhv387g42ZH
73iTlzOUJl66qmzJJuNyYqt/ubDiNOsFDpJtNNRl5QFbanyqqiUani21UPELtfq+sDoDY7g6bEAp
tBOOts4Vblo885yOx0GbwNibhMp9KQPANtr3qKfNKyeKdjZOx+xqnWgtGrkMmqfPIvnllTm0oj7p
+vBjPng0zjYgWrmZL6y9WOktf4v2eMTq3vCJ/J33xrbyjYc3OdeKLh3K+I7Gwl1I6X4T8WuHYTjU
ULzye/rMnc/z5oOuR+YwEVAw8W24eTkcE/xYGhGFwMq0TSHuW+n4+NOhSCulHsdp0fsjul90X4Cu
Kxd347bnGlgx7KqdYsd1oH1kZ5Oo5xdNfX5KxjfS8XuWVoqyPZTWJwKy9I76aMWpp+1NpxCcWR87
SgSgWRyFLf1IZx1OHJxxtl75BivAftBveK56SRkHaI3qsjVeNmw2bYTX61P4vO2Oh2tTy7nbOIJX
TtFBo+U2EBSl2WTbTdhIafa2LxAkKr/G8rS0VgqiM2k+gqWLd7VcozKGDUtx/X2+88QKn4LoTFKQ
G3tobdR3/htbahvzWKQYok8RKS7yVjslGiCJlOUL276HdskCQrDYl0IiuXpyhTQZTxVxqWqoWvBp
1coYD+LrQlbRFnBu0XDTDZiGtjldlnL1XhfiaN34KnDqeYfgQZFeRCOHPb90UONzHvGWuluWfvGS
wfWFz4qWNM6lquL4RaDh9FxsAbOwUBqeNIoTS1AaPGzvpU9nA9+yReBGSJXRTAf7pIH0T5rkYPkU
WI5+5s21MboQ55OyVoMMpx0pIJG1J6RUuS0IkeTWRZskbX1LUIZiorERIwEHW2lvZbXQp1nK5fB6
Z7haI/rejvwIf1sSWF11r8ibF2FWnFq1/XORp6IGaA3VUkG00TVn0TmBZtMSJdUnX4RgP4wemH96
5HwhcGBe93dVG+z9Sz6fn+UCeE5SMeLRMkkTpal5EjMN2MkRByrgCJNI3tiU1p9Lg2+EYEYQGkZX
OTP2dz2UenQExHKRY9JCvRXmpDAWbQH+5e8bZ8Lxr6J8AvyLw5wONs89S8wSxGrIktYOFFwkaWtg
N45JD72dOXWKcsnni5q6YF+h1bSYfgAVx1wOMlLgD1WDJ710kgL2aqHGB6iUkA54BEpnxMa5MPaj
WrLdgniyx9mRB7xIjxE61Ekj53uAJrIKekZTTf2o187QQbm4CYt/fByTXaUPjlI66XrNxprnkeDy
lNlW+bZIHZoC0I9jMxYPvNECB2TfpiJdgsI1ouMPCyuRIgtesb7kHtfXgNb+w/AoyzTWIb2VJMMs
01mpLUYfO6dAA9VeWQERwZTGA+OFFmcetRKY+BAFv4JORmKET1Da+rPOcXfKeiCzEyMqsRmLnDtY
+TXf8jg9X655awXFjkIv55uaBsRQ84gEgZRF5kFbwjGaNomdD+MLUFPvjrRoEMMEGRZDTIExnicv
xHNnM7rodwsA/Yd9jK+R/9qdblP5e3V0DgvI45nl8hsWOkFyAIc26oBHxF8x1DlZd89qV6+4lxT+
sR0sXejYItyKNnRops7tLl52Z3gO4KD0TyvyQehandZycVdlpZTIgASiLZvNNmC/8bgOPq7adJwM
1A+Hfwv0WFZBdzszr8tW5EI/FlLJ32gwwEplE+tY3sMpS68cHqrozQugh2r5ubx2u8fcp7KtgMsV
aDq4Zuguz5XqyEipHJIP68tm42NtsicL80vDaYvvNvoR5symGxwwVGArxCXxDhiyjkF71IghuXuD
RdZjGJVZ5W7OldXqYqCHuOIFqAQLC+gAZ3zN0y+mo0O9YGbXHpGxj7OKvv2sBNOCmcXgLQVu8ekK
/6cIILwYZ4/LP1ijzQDyki9xYLbB9RSMrmASTBPLhaMOkonQy34IooxzBIpHGSi86oJbYnY+5/l1
rLNYsSKUWy2Evi2qLVMpkQs87Le+2acehB6L+mGkZraJxoZuizYGJFEVsWFIGXUoCiMZu2LN6XJX
JTMGFGovEMfxYK9eHBRYMdD/gjeQ/lVXhS9rDRnZYvES6vy/l9QSuELlFJYHmhdYQr5LOP9MCAks
gyNj+i0IP4zXbpTFOnZviygPf2KV6MZVK0t5P+23e0I77n9JxTq9RSF0i+NpL8YLEnKg+Hph6W6F
x5Rw2a8IFayzl8gV50ds+OjExM0FYBNIh2Ye9EhINoWVGiSoH5flnTxNDbB2EWetB/uiWWcr6lrZ
4r1YBBfrEB/mbkSXUqTeO+76lEsCTusQ6ZWO4Lwmu29M/jy+cgoRxypzsR9XflYOL9MUP2vc1y/o
AukvyINfUE5H1NSxN/8LVdvbyTqN9YHQ5tuklayq9HFpuMolFgGVWee/Pir0VvBz/1GyQEwLqyHj
AQ6Z2OrCrwii3B+Vy+KLjgmJxJmIkFkJEonxHoEmxEJgQ9GHoXfVI1dUbPJ4sOVYUlJe6uhtzDZb
vI/yoNvUZSlKw+gDfklmndCf4htLUc2hXV47vO3k+XwbA6TLXEmeNq6yVclyj70VDgZ6f0RuCl8N
4L0gHYTOuOP5o4DpO7SQZmaTD4OmmGcPrxUblovxIbYxJMQzho2pfGWdwPnIdNUFITigvd6VrKmm
6jzjGomkciGg0cZywajVW1Ib4q1GcmyKco0yD1BbaTH1aXj7GAxqMw7czrtIMk/eR73Y8Km4sqEw
cnFWYcNYzgH2BNUGSNgMA3HrhQcBfeAiyh2KGzKoHGHaFzVy5L+nQL4BjBHLXVK+/HhHqAvYlVCC
Z0In3RaE4KzvWsnx2xT7en5Lni1AmUgb4IxqMj8UCHnQPcVHL2Hug/kgeT42cHXC/WGRNLUR/W4+
qQXNy3qLPSL/OONW8AdOK4yAZppKghHCgWQH9N8KyUCySSz4ppqN3EsVJHg4lJoMtjTo1BafuwH3
G+33nX55CUTCudetTgzvmwUe8dj2eSiKX1ON9pSDYou+qm4CowtcrjwGU7nz39DGT7ZbFzo8MHNm
kG+PPkAyfJRkHv0fR+gF0LIqZT7drSYMrmpXAmmuk/qUlgfU6IMdusOu3QEDI0te3JfKeJDSmH8s
kOVgkbTnNq0eFyYMctirnmS6MCzOKhIRNr1KlS6rLMPc//BhG/YS5eNoStH0ZF1KP0/RjdYYznEW
LHLgS66yqxzKdoChH10uigIXwsOhzU5YdTna8jUfzH4p1cvYfhQxtHqOFoCMbzeMh2tfvOxRukGp
uFDRWSMuQYC+j9ZEXUsGHYdejwyE7ovm1ywKv3U3h8RrXmfAYgJxRRMeirC7OgLF3/4UjSY/ANgg
FKvlMu3MT46V+CtLAktyT/+QcmD3/SN3GST/X2DDlRqMWUkvVM2m8VP4xioocp+8cBUaDuSNje3q
zEDenLYH1o56UbUivZ2XjRCJFgHRWn+DirzKfbaXgu12eOQHHTAkB/FgMc1Hz8rLv3Q0e+zkb1oj
O7ENlCQU0/6PM0SZ6ZS4vU8ms+LQrTuvtHwwRYBA8xxNs8KwIKPfCswMi/Rl8TsWB0kf3S1MAMCr
n2qeY2tY3OCtxio7vwIw4eASNOA55Wdrydk+r2otR8NjPNJ82+IbbnCnEqV46O7cX2kFMqwQu0LV
dQGARF3gz9mXjCfesD/I+VRAF+K36vgHQdT7ScF4wPjjfEHDpbZ3XiN1lBN0N3DJWcVJ4eZbRck2
tY5FUqhoPVlWFgDGxphAV1zMNpc5iHkdzs4m/cqlUsoJ1tD5jRDrhDw0yUWDrNqfjeEgvfC/r7qw
neNT/zv13O2OFjypNmULf4Zx6fzqJy/Bc4XxeUNWv5j/bhbw/npI8Z6kDla/yqq+TTzIe3do3Dzd
oW0ZqjhruqozhKt8ZpaXyPbYmF+pFXgtu20fjABg+NnJbcf+rOihyRcqSUaVAFSuGMT/zuvA2J2S
OlTskPe+jINlgdwmeilH91QBzC/GQZuVrjYLfdLGAJDNJIPhvAHQNPP+yU8AoOfilpKHjrWj3/S6
fiffZQ4WD3hFuZ6Ybl7zfw4bVKcqJexhblDJAB9D0gEvn7iOBIZd9hTf3BjEQGgmoDYBquJUC8Tz
T6sjpHhvX9V4MXCNeQjXFl/66gCI8JIh6LyF8OnnMbhKsBDK/ULALLAXOlvorwf/BsdJYat4lrA+
Kryglm9rKEPz3YwP4yqckP/AlnEw5lxgAjuts/PxuU5FEK+cb8qh8Bc/HkJ9NB674NixByndkc67
YoXGjj33dKPs8pLT4oR1fMznSR3ETJkCD7WcWhW2GRlz3QDF/+tu+sUxq6IhamkPdfgw/w3bd8nc
NB0CeQUQBE+wuLvQtU8Zcp9vlXpTFijLOpGWY0bTHH2vDqR88/iBHJ/jFWOeqGcd0Muk/5d5tNrb
4uAe0pSKaLU46gJl1xaDYZUUYAS967BmPeY86czqCDuGTV+rYHZegfhpitaJk+23Uo4mG+AqTIiI
0PEsAgxyB3KYxhh331O7VWED8nBEh9W/ta7iqTOrI5yABfX7/vm/hm7V5+qbJ4J8Yk22CmmLGSKB
TeWi1tBeEUySbXJdrllqDrYTKhz5K3pRI9hfU3HPITwPly7jNlqPmraqlmsJ11j21TCB1cyfqJij
WE3Bi/tMye3KkkYE+pqYZJzSqHxsKR3W61uBDtAdle/ajqryvXh2YMRgJWb6rLJFkNbOB78rKkVe
il2S4u+3FsodqhTgZvu5fY1/bdegw+e7jPgPsdilATcwnTKsAuoVi8hdFmsIj94FEmGTsCXG95dN
gjFYuA+qFVKpc0hixO0y0JMp6BYZqofnJsu6jF1vNglR/avv4q+03DaYrn/LXvvlmj3ublfpigaL
ONjb0om1ujh1FrRcWdwe2Y9FojkkqvgL+yxZXH7K2IPkt29q22xEOW90RRW1CcdScCzK6mZ9ccGu
Z4H0wbGH/762iYWb1iaIv5DOH/4Kpi8+T0xnBsGSeDxGi21jh/+z/FLGwgr8hxJdVjaprPbcFuYL
TUnqyV9xmATemrk/PstYptCO79cPs6oDPhcz/n0t/+gWou3SXVx5TeViBALHoPhd8pBCa+p6d7BK
tsyDX3FcGrhvtZdqddDglfOKoOnKSCH6asOUv9roYM08JMtvrt1FOKQkZr6eX06h10uQD73I7eP+
LfWo9zN6i21pdBD4YTqtPvdqbc5QAb7bRqYR9Y9jAyNxJkcJitziaiueQD6MMrxlofbfs9zmPnzY
IjnhCn2lnO6s9DR4Aym5U6wN/wJxXIFVbYTaEVhXXIbTBANMpK1wEIig7weWrcLEN0OV6M8FT5pC
q9lMhPcKvMmWfBbrCLx1HDVxER7JSKNqbLgpZV3z1MsLh3t/oPEH9UoQfYac5xCXRkC5PEbEqt4a
mw27VXWjMvGDs9I3UrIX/zM823t+jN7z0c7uvsAGF4ztAnse/BFHL8tzg0WuY/aP8Fc+Wm7eX05R
TuwXhlmZ0ChDxF2J7+PiEPDFRHI6tsgRXF7LF/nkV663nwXF6r8vZpf2d9QyY0oHKiZ2s80PlDqt
qyjaMc0HnQs4LwCaxTzJHTEV0ExTyOng3O7vyW8k1maoYc8tIanempNd88dJK6veh4wDHoxJgMlB
Yt2LVXa3g2mxzArUIiy3SExbKb/ULe6815egTvaJL5cHPal1fYv5i8RLWtQDecbPqFnQ3bXv8snt
CAoqwM6WmjHVsJsu+ru50+JNkb1IJHcBJtqa+h7Xq3E30H2ryT+LlxKzWsnOj095LMrQMaVvafdO
KoTl53ZXTs+h7YosT5wqmvRPYqioZ1g/AHqXKEqXWPjFZrsBp7gZcR2/BkvJDZMJphzVkZGot2G1
02cTMBY1Ttb51/c/leWtfYrjZE8dnbhWWmE4LggKJJVlzOEh3RKAUWUC2HXMBb0ecKH2mtTEx71e
98wVUPpJbVdncz+ziiJN2C+yU8v9ADm9ldW/EyJt51GwgSvxw6COBSzBu179JRH7Kz5+HOOpCV01
fpCvgkSfH/iPTAiT8D+RnK1QgcA+Ozomn+z1QZo41qPleEzjQAm85MKF7ZDMUUo5Hkiqncr3THIT
1RucMf+mEC1Ok1XE/Wf4V0U8uMRIM7OZRNYofUtn4W36dEtbm7CoIUFfbDsF9EE86M7HgZiKWcbR
3XKK9YwP5q8Y6d+hwYQg8LKt5Y6s7KUOZdaVGBuewYY+v+5jHRhCH1NYeUu/9xWW9zt6ADpscDGc
YRyQA6HrciExPIZ2IA04q7olScJ7JWq1U0jgVFAFTEYQ0dx3eItKIiQkv879H2IsWnXcWimEawKo
gMjFNLeR/HLlgiqPy9OTIE8MyX4pRzKuGrnQ2fddRQ4mZKhh5dGuJ+ElVzFn49avcrNQjKAIyvwM
Ugrivu1KmtXh2citpMaS36gu5jZCH0p8+JMmyQF5RAsDtFKQgjXb+B17lZL/U+dgyGPxXswf0wLD
Nvc+lJitfJs5o7PvtV5bVkPEThWkFcx5PwaGZqBpl7WH+e6uiSaTSg8pyA9NVWG2nEswUBd6OBIh
3bBN4K+QVNMLPAxt33D/ymGR7+gRtbmW63YWZgYXM/GcKlmcxGhnYx+qZO5ps+AalTIQtmihkswm
ROezwwCeo1KJJExaa+gCAiNRx8cg64TUmLlvktlpeqOoliJslLRI0NXWlk6N+KTSgOAXmUj/4S6g
wL18S28+fCRIlFaqfI4muHVxI9eewGjlXsd/zF/ZDD1ZFPmjq7QPUT1BYcUvnrxrvNUA4A77UYti
bbXmVwyJiIOYM1unKRfSMfoQ1PkTaW+g0Wk6rwCuLF+fRiiHlC4thI9a2bKh2zmQTkPRoXTxlqL2
ht5uJvGlGdC53MoplF7Zpma8pcHSoxom7t0uQehxeGyuwCN/bSSZxRoKCZtWFQYh/jcqqUR397y/
mDJE4oyxQYp4guz09AnC/0JfCgrG093h1xPUm4AzE2kyxxAZfRI67nkSV/tfqu6TZNYXCOL/Yze5
pUj74+zLB0s56JzIxPjH+LaEG/T1WvKeNWc8I06sa1i/S4Gnx23Va3e2EPt8ByGos2kiRGpKF6C8
5umOP3UzBExQxfbIhKxqCoYLYDaVqUe8TIWrmsi27zQ2AqD37O+tuQjr9KqkJqst/5486hGNG4dn
zL7Y1AY+qQFUx1qjDT+NzVev2jvG/qgH3M02HBHSGaKJNQbiSc3FV/7i/r1RYoj1ZzzY8qy3bob0
pJqX1sLm/w4vMDiQxIMcZokYtj20Vuu9P+cadnXFx3+B7KIEwTBYktQm5tOD0LTreYq5QnmXIXcu
7MPnKEcpoZrAnaU3TReDqVkBAB2LTjSWesp/HqNk+RKZevzSrDgPc6q2vDwwO3b9I+2LexPMGbvl
QLoK2yK42w61vKAoR1sGwN9jWWWXDusq3p6D0ofPglZMHvvxfVspN7V9w74s3nn7RrGyUuGN1VfF
dU0ojZBrvtPkCA7hDAMMZIOecP/IsSmVQVL1oz//qglZWmVB7eIWMSWbZDxmgBkU6DgFuxNomSm2
xMubm1miqSxqlCNWRN4LD7qbw6hKzEbM2r+oDR+7ceibU+3wrGSxSomgJpbOURQeIsD//iRwGDFq
fyiMAYF2sQsC9buzM0P0Da3LLGepf7+jT2dfag+FCqCZPLqUlFKkbIup4js8ILMbQFhakvWkiHZf
PwXWfzpoIR9NPBeGSkhJCOLNiLB83vLjgpuxTdGUOTLzGprt9MDiutLKHU1PykwPcUj6JpuZvG9N
79mIeshOSpBGMMU1F+I8R57kZTTtPi70pL382PWXo4poHujqGfyMaf0w9r9F4sNb5cfwZwEra80e
drlppIwOEjrK7MM3N7xfk8fxGCQEpjR8ITBdDAg7El6QAEWJiVUt3IvaQHudVdirI/S0JSz7/j4j
ulHmnAH+RdtRl7P6sEWZqsxdpY2IUiuwYg/XoHzGXqPsM7LHPlyULO5uc2kelx0Svo4B7qPdgvXQ
kvdffWf/HuWjLJPy2MzidVUSaAvl/zJmIZtM0vSai4xGhR9wnhS7nYceKRUgJG8i+xODZTxx2JEq
WapvBD6UgyIqrw4sTjHusR3FOlUbv/SEqzEAoEG7heL2WQliqnAAKeYu5dGPoBsLcsiYWcEnIqal
Pi/gDd1wUDb9UIRvF55ZlkxYCjJhK9+JeUEf8S7xF71ynNn9NXSbYLuDVLlPbTsNY+YCVDMkUO/E
3OAifiyIN/+X1VU0nAKO5y0Qsd1E+6eQSlOAp8EdVQUu6suapb3Enq1Q6eCPnb4nmKffaLQsOdzC
5+C6BQBsW3U3USDzeOC19r2Q+R3/9gDfRNXEU1KwpXTn2RFnayQUaT76HGhlQW2ikhrC+tP9K43t
wcQ0fIc4vaEFSFkNexGEUfIpNFef7/X+qibdS7gG4aiT5bBRVf+kBQQlT8hcDyPXJ3QxU1SUmCQX
DSjr1Z/nMYBROHjVXAtrcE23bDjH2aWnyTYCjrsolJ8T13aQDNhapOeTRLtkZnCXoYtSPaCgUPon
XaFgDTJAGg0zP3Oxp/f5O3w/+BkJVb8Vcn0X68OXWnioQZS9c4SIdgQ5Bn/ad7S5IJMGmRWZivcS
GYyYOyJ0OSi39ORtxoGfH0LKm2UEXsNAxKeKyieH9U9NDVmWRZQ0uIWB4FBdDM/tHC/UrlsVnva8
p9af2vpelyvLr4hwZnXXznMy4BNK9fJxxMshe+emD2OTbOdwIgm+iLbAQwTgHIafBdg/3wKqQiJp
MnNE6lJ3sqkVzoga6H0qT1R+urbKVRKRBI4NErf8drwW7gcckygV40bQ0eS4r7bbSmZoyccksBn5
8CGyAApl4t7u5HrdN92h+UrtZtfvYWGoA46Vlo3lI2AOlQDkV2CIMizQHNb83cQBss2YnyFcwy/J
IkECdDpZ19/GCeujmZqgHNArpuseRfZAXF8z1W1CqplOBRIaz8NeoLkpfArL+0K4jx13wMY8kHos
UmQBaexnSIP/JvgBOeqMJaI8A9kY2QY+Q6dAuC9IEjV73b8zlR05QAYWi9BygFTHUxx8adM1mNQ9
MJs0hRkqqUlyWpMdhkzdyOG0ta+eJbbGb00Iz9yfCat8nq88mfyQYT/bsyBFFkI1BfefQ9GKnZ76
4ImqJY+EX7FD6IkT8Og+LyJFP0T5XMJAnYgxZso8psQCrKXzksEZ/WWd+kFNjxmrOKGmQIV5Xoww
L8v6aF0WkvPTm4YTy7JSYXf92kWx3SBojz2R5ulvk8CQjDI9CO66yysBm9gXncoSkwpyu9IQsiII
tmqYxWPMfXTryeoYCyA2VAPmVcV+712ifcGLXJASh0Wx2XOU5ahZqKlPXx7ejmmh+72CclP+4qPt
OXt58shdIh2hFZcoysoZEDSeeP8fQDruEZTBTN8BqP2Y4hhi6Aq4vQl58KidDXXrn/fbDlTXJdI9
/APstevzFqeRQTcmF+BU6hPS19NlgCCYbQgVa2/xr4R6b3O2RUNUhOcB5cXLLH6Wv52lbpn5CKcK
ncqbBbHVePRq+ATMZytJ8dpoIFSYR9h/Djhx5MLHprsj+AztwsANDHPmEARNTEQtxQH9Km6w+Js8
VcIIKxCjAz5QL4LaWEez3rE8EJb1F1TmlI6ECSK83fZzKEuO8x5qCcNxHnJoLhxdF2mZa6eyvFJB
mRm29SVJhZoFywx9hEOaVydlMFIX/RDD2pO3qAvaicPT6ERqUBRaErmx+AFxsqj5SXubf1/5ZluR
hglEcYgmq9pg23zHpX/i9h8q8tOKYdRCjXR75O/GalN7PuwodCoLZK1zx8J4rv36HIKB5ul+y7oF
1s9zYTqIO/8mUHALp1V3U2un1JV2YFG2Gyh9/RV3kjeR3oFsKegoeH7YOe5+cpy4IHJfWrl5/RK8
ZtZSp1eP8wQvHUIe8HY2Dg5i0oYJyb9Mol2kGt6cjDpVcknHqnhHr4YaDG+h790GaU/wb2TvCSs8
QSFMYALuzgVj0Woqs5qbDkBOy5P7V4zDnnWzIK/jrzeHNDsAdYA6GQj7pt+cQjrpbRBrUtuqujpf
DhQ7Q3rkGzGHfitK8gcLyQHpUP1RCZMGJA+QFEm9BVyB5Gx7D6wpkJMcjaefHw1uneq4rR0dL8aW
QbDPbheIHzRrXjKLs58wmNsfulrVTFdQidm7zYI+kdZwuTdjDH0A2st5BVoSInL+27VNT8DXtUqe
Y4ZokDe42U+M0s6g34Pp4DMYFUqoI8DVU5JETXBguIeJ2DpZxb4Rwr/N8hx2Jxhvua02721Kd0WA
lO2icG85IYwta74v5zLZyAHY1VqJMETDgVcMpfpvSipDCGQZXcRPUn+LGOqDtt1Cz3im+Pmce2RK
Tro8J6XEuKMb7uXAPjW5pidWKiJSyeOQBwIRQux8KuaSA68ABEBFym8lS/XLrKD7KZTrCTm5Asj5
16aU9nTWOjNolk8J+yKom+ki/lbm+F6NvYuyeWY1M38o7FU6tQTTFl2NXpt4Ej3ogxXDZKGaxyqd
WGVi4vW8DNkZv4xMPjoUgUGWe4af8nTx0w8pJCGTcHAFGxmy1PDH1jpIzJrMMUQeB7tKXVBrQo9Y
jQ/0nrrRiZO2foMS9PG31nMe3XZeZrFZXFwHO11Z2Cp3df2HrYDTy0g7uSWqPwtipoubBWAcoUln
woAHLTLiYYunofCU0ytzI2OPxZUly/fUA4VE+DSPnQieH2tpNPC5xjQYZ8lztf3XXsVNczxW4aNI
IHWWDoKIcSKQPCC4cPoUwMwp2piQ4nhjenMc3M2G9gTzPyfvXAJ2giA9kBBnejYF8HvNVb/ynLpN
YKQfaZHAbXlp4G81LL2rNmoPIGZ0JShQFIxuWvm4Y5+h9addcCzTGTDgaCX0jgTFh5PZmhAV3+yZ
V7Z2v7wXcbvnQZv08V3CYOkiFCzxrOXUHV6Z3+cuV4CkO/pX5n/ufkzPq8zwvswn2fz1Yy75773G
3ap+//y593g9PjWZSrR/rhqp7J2I8tGNtW8/72SFMZYfehvqJH/YJ0tDF8mB6mMfKQKkjPFYUTE0
dL9Oldqb3cvQAJQQIKinC8qCBKcZHUC9BcEyV57ORTbZOgAaQh+EfECNKc7T23vt1cNAbZp0Rb+N
S4JNGtnUJpyajR8zgEQU8wftxtyi7Nf/IkPPA+MAOlrG0JCpexHQY+LmcvcJXJaEUGI19+WtqLDB
2wgb6LGeoGL1FtMrctvUcJun329GIc7OfySqXhMOu+F3q1S94rmIxdLZaLoW1a5pBt3Fcbjq03wS
QLj/1yc/1QXpRRw5oTXCykx/abgreaN63W+eZeGmUYmr62rPzgPzUhQ424CHtOux+cc85gNSsNWE
M3y7aEIbBEPumWDYiOSYamis5fyBt9t9YeHLlVhcI64g4k2MF+sTouU1XQhpAy1KWb4uZa62NoDZ
TgG1CJZkuFhD+xgZZAv0TVnV+1aFO+gziCK946t+Lk0+I9/fwAbTio/i+idUaGK8/fHa2td4E/19
daQ3RhrqDdMLnDHcKTFyCUdhpLJVqKOpmKzUo5j0+RdGqOdPll+kKxZLC/aT4tV8oM0L9zR8ELXE
WGHFMjcs6HFmBV/B5u7DKSn32o7LiWgmjwZK0a4OO1LwYZjFg1eGM13dXVCK0A8nNQSpqdxF3G6d
K9QLbmnvSir3vaYuHopx9uwTgAKlaNpZhzgEYDOrBpF42jP41uuD5Eg6F39ipaCtE/fYsCJmZ3h3
2FC4v3YRL7q5IZPu9iVpqr1YrLwBl4CJjEWkOt94R5Ne2ndWbxM85R3jvf3rA7BUAM7fuUL0qXbX
8Npq9KjG8VCTcciOxDYX/nD8xR0W6mleIWAqkLAPH+BjgMyoUG3b9McNhlAQo/iu1ELRR8G6tARh
OVYeCGVxF8nhcImvhU5jwWLnszOipU3pyaHd6EVFMTKPS6q1eh0YrSIPg1jFTs4dkCsmQcxu4l/d
gOEcrpqCM5d8AlnKjdhS9wUpX3b07a4n1KDLTInO3BKyY6XVFIQKD34TAmjCq0wyT66rs8AAoNpM
rSLAs0o7S5JxJH9Q1G5NnvKfJ4b7ymSl5kW1oJP7qsCGwKnYlHSN2EpTBXhWqjm/lC2ZIoI+NzCb
75O9PJuYLRTX9MvbW7nDAHYM04CaO84YE90IUQkXfGp+YEYA+9g/t379MZc29115VBPTKS5GYRY2
C78MvlfCEoLbGb1F30PKoaWS9vYu5G5CiH/f+Jyrqk+mqjGipxPRgHYgzMhDfK5iikmtrTntbwqx
XOdI8QsfHjU0LEKPRhIBv5xsqMyzg4IrjHQ+vjcvhDDgpUOAq4TO6wfhcN+PRhrGRSh1tufg+wGj
QYWvDMtekgDTskZulCh0d3tOrIH8w+JWI6hXj6epMavkYfHNR8Agx9vCvr4i1yUOw45CN6mQdB1b
wouvbIM60fk3STd9j2tuivlVs83j8SYwe+yW914WZkpcx0fgdwICL5dZ8U8aLW3h8P+yAqAaCMmr
Kes6ljYgK6pCqYRvHvMVCIbjPXWSu8lw1iaqHGJ2vsWGhe2F+4w0ZtFHUF9XhMrj/LRVuKhB8e+p
ktZhrbdGDUWEDTqUP9VMQrp/hjBQKLAQK6VJ6k2i0dh72hoJfZhRkxmzXnqSS1A91+M5/vUyNSvo
7vkhM1+1+fQjU8oKdEowST2makSGbIOHA9cteePGMr40CfEfF6QDzFtCU6VMt2QpQdLqHLRu+OaR
r6e6jcDgruzRPRN+rr8eunZmYsJfT5eWPt2sfLvFLGL2dBekmDbjGcGql7TcyPH0EoHmSL89JjG+
vjK1fTjw9bFLs17NBo8fgbKqaIcTKfTcLZ5T0kBRKqomRphrI7hD/0JL1bDIpY93ZkiEt32yRaqy
1MBV8GOdAPdpy1JMMb5nphMbG8AqK+nTTdoHO2L7MmDj6ZW0guFwgKpHMbL+Gi5nfzkWh33/4a/0
s5kkFpaoL1i5+I71EC6SAy7YDnmkbf1Pr0zOYsKRawg1XXoFy+mGcvZCL+Dn3gs6lKmAHWQ2geqZ
0ofp7tqomxy4O/xJ05QAURZGQWvQP6IhNgaxOqtEA+TQXNBjCDNefkVONYVT5GDC2qsfJF5Xtf9P
8LQb0hktmYloaX4WHDXMa37WEGwylTm6vKZqGZJ0zuqIhpseykJS7p/uTvtE3wnLCNTap7tmp/Y2
rS1jXJOHs7MeUpBOIoT1yN1tgomQkNnP9rgrSVWNnqH3mXzy0EXrCv3z4NVJy2MFTEL4bmc9Xxce
lb8xZBWpLvrZfQd4HUabJw0ZPUhjixZbK6NNzTesoiviPf9+/U+wH7K0/giof++Nup+pogmDcEF+
dxQfJvfutjJOBiebyIskP+1RAcF5cyc4R6/AJpFUJdkwG3B7o8rL/2giWp4n+KdfSK0ge/6eRkh6
x7pkCX2A+zIs3A183BPkF1afhK/+naNaLNhxY30+OwbiA6v5TMg9n6psVW68KEjsxDvmw67WjXvV
oZf2yM9lZzbjfI0V78gyFRtzM6Z1/GPkNbdpTxhkU9JVatiMrSTCPoR+63XW3wljCZJivGw9KqYr
5MQr+6uSpxA354odX7bUhID/rGeOiWgye4r1AhVxT0TyXYDaEmBVtlumhdKuvjFESjG+X26nrNS+
mNp+G63EQWzT4ALkHlnN3AtJqXaHXQ72vdr4PrFiscoQBivqe4N5kgUJzQxmaA/udaGr5EkMgLi1
0xus1u24x695N5rSsJmmQ9X2YHGXG0DaXsRWYSJoV1S817fLTDmgVY6GYRZFKxeq2hHyz30fg9w0
5+bbwlIYnlIkf85pcXz+yJAWtC1zFLNN1lSmmKli/dXBSqo/kWDlPZSNnF+XIxlOSvlID5wbfmmT
wqIoF1fFN+DZPsvt0Uj577/n7O5VqT5TEt5BrxpYrT377Q4pD/lIfv+7EJyjEwgVkW0ozlmXMqyn
ibZaStNTPs7k1ypJlcXvXJFInAK0IZwlTHxQh67QdrzIp1QWUKFlYPAeOMRWedNHHGKk1KW+4Llu
YRdKumgx+k3D767kLkBXjMt0zxB/GSXMTSm84/bC76HzdkGmt+cn6eh7SZ5l2Tad0FCh4apjgb7u
6wNEj2gPHKq3buWr5VfrBJF84JMKcw1rdlWUOGSCeqR7nJCx6NP/BjYYPjTa9a0fWFVQ2SOq0nJC
I54GzIAs0asIll9Ow06CWww2MtrXU5bKdGxjTNGQXCwPjUYRavCsgGTO7Esty8GzmTh5Uwo1LBNu
PGfD1jhfKUtXytYfCtdpJz5EirynFwSaj55jzb3NUFT+k7/ggn2eNK04ZA/b4FE37MBvsKaUlKRE
m/Ikpx4OnCxVBWmzINj5eaHHS+RB0YOIKq37bYfSyB6pQSJkAqNXEa/5um+MaKmKRVl2EQYbPCRY
fF8qcLKDmonHX2pKoz7cyLgMBLRXRNrwYDOttFkhCK0nCwYipqVzqpUKm5S28QVoSu0zqjXtBPmO
cVx0U4U/J6jry0n77ZS+BbSeJnVH1Kqnpm+patBoc3nKvXkU4kI7EaRZo2wPyS8bRZtIRAdmZpfD
XJC5l7MLtXjJsGEfrLg99Vinr+/sSFSg4398BNT55rZbjfzcShwNYnVngWrxaU5+Ghm88QrMMDlw
15+DoohgUQF6kg064lpqXeHD2jJcnMVykT+dGJUA3rFc37UBA1nkVh1yWR0dIlOYV0HIwwh3R6iK
BP1/2LraSEMTv25FD1gT+tl6uG2hzZqvbGKfkvaf8G64WYhumD7Bv27NBJJW4/ed6NguiUYhBAVo
4MBtv1WV/WoaC/g+G9HzGLRt7+5IUERVtAEyjfTO5HV1lW6WPAUkbgI19oLsUbz1SGHiY37ILbid
lmYbuvixrg5rCZFF78CPnRGE9C5TSrq3ai7u9PyEOrFZ9pcMldUZmx4mfIRmDCiqyHXNTSUpRtxa
QFcE9/EHe/Z8mGFzV5bJm6jZGK0tW3dRKSfKY94v7S9V1qDrushQ4F9SUQhHMxXLMsFjIojyZA5J
4SsrAHAn8eWG4mNK5n295Rd4z4nz5rNqG07JfcIdz7rNXh931UaNCDs30z3cyoEKR7rJAg6kJ0xi
6dTAVcoLn5EXgs6QmwAlbdq31YYWuRbz8GIevwtJl9DvxpIYeaW4e3rkG9zdwjS3YPYT/oWygc89
Hui7u3Q4EXEKSjqdP37dlXleslzfXiYNQ+AX8R+s7X1fN4igH8WF4Kz1GV6Rm/w1RZZsSZ8Gw1M7
FuzGNANb6KQhMTdnRCdfBvAJAy3GvdNGKm1z2qANvy6Bv5sLELz3c5itJqzhbhGw7wbECKldY7Xa
Vvtcjuqciw2SkwI1cQ6HW1mtAGDgae8ZTNJv3p/NmGm4LY2kiGBafph81wJjLyL62/rOq2nQuPkj
fbG3yCtuKfGfQ+u3iCHWfUZWq1wLmznia6rrNJACGwadIS90MNFkj8vWP/vn6oDbWLaegkrH7SZ0
ciCWfpWCPqDwUnvGM7zO1ostmC3/MBQIvqF3MAKMPTtH2MjoMgUtZ/Hvc6BjOvIx+RtC4Y4Gmbly
8zAe1OW83uPumLVXVQ5AOBaimRyClwrunEVfcPWWS3ApygxYc2CLGNq7fL6FYBrhWsR5x4dr/vlV
B/FSBIWlrgssy5DyZNTAcPV4SRLIITgcu3/32PENIerXfd268xAYitRIDCpQiF4kVtl1kWSY9CbQ
HTH4NLgUfsSkHWkH2PDEp/1z+j64iVA9ynLLeP4Cipendnw6wb0uafXDqXTwb3L/Cuine2bZ6lKi
iekT1zVAVqHIfuzq01XgIdVP0aZYjIkK92xBVGUiMcFY9NpequNyQ3rjcTmWfXNxNjHZ93zrdMUJ
sJUnN/FUKAMLx6W+Z9rAFv6bbdq6k5HC79b2cmQEPzDvvrtu08bKgyhxpmp6NK3t6RW5I9CfmBws
/xXtMWfJ1RBETMkiIhGxB0rZWHEJdFz9GJtEXWoM3hvnJ+lAYDNai6Zbt5FVQHQ+dX2shlijgt7y
EfiNw5aK4x2K2g7JkrbitnQ/ftpByOPvDFORb+Y87IP6HDtzB0eQ6fEe6BTM58She+QD8ebIQk+8
tMP4EcjvvgCCUqVOCEL6M9c9G1GIF+/eeyBZ+XMyZwUEdn4ggZ1aY2MZWAr/qa/LMxYjH8vit3Iz
jFk9Me1LIv9LWXd1J0lihNUL2qAPagr5F+mvhId2KZs5bJrSo3FYwnUa3fxmN6IPiR/RAxZV8z0Y
c3rtQgIIH467qd0pd7gUwUA9+yJilQDbny0FQAip1QLU4kMHXrSpM8m9r9AjRJ6iV/GggPaeWPpi
8MEgogzyhznPmua0KikvNWjWwujZ1iBjQKCmjt4ADdfTYhAWKse4oKl9U1JiHSmpcGom5i0AbWCw
qx0Dyi5bIsAFAxIr6LiclipxFiL7Gm4BJ5luzAU7/ioBzwGTDzPEacpQAbFQCM0bsi9owyChD2bU
Kk4+tCCcWSHM7FoeLOrj52G7Uf0Ft8owD04euda8EIEGLyTkuOcZFkF1DHbXFE00HUeYbb/2RLRV
lAtiuS0OTiY8GuSQ3FOQMuWbKMPMCdQs2IeNiqPxf0WQEI2vHSmS96Qniu4w+jGmVLUGHZjQIYPu
fIvXg07RyudENVwuM6anuye/kvCTyjhJhkgReWJYc6ksmtRgx3toOCLiPVlEBjQRR1USQqSflbIt
Q6NghVrbk32fq8WBkRQsSv+MEzrYtxlPuejOS2a4RxinBBBrEZwKK+C0vNC3lrTWh7QzDuaWejE0
v0r2MXk56rId/Wd580CIYclnFupAKnXHk692/dGWAcp1TzuehQM+hyRTsvxUv3z+Bgz/RZs7KBFU
LvRKFxRJ+x4KyFwKT8W11BgiG9tu/HmzOYQcy6Y28vG//iBk7vkI5OyQNx2f24H2RJ48q08EzTci
DbChatVoExVvx6mz0LG97FL4pdYjI5lpk2D3pt684/OV2BhQnhh9HwUZ3eOhFEHjfLtbAHWSetyu
u/qFA2ug8tx3Ks9Y3M8yDY/mfNmCHss9uo7uLqsH389oPyPNUuzM+GaI33PBnAGfAJSmLMF45eXL
qfPMUT1lPdTf4+i4qyOKAaQ6/oNRFnQ558alQQ2bUFyKFxS6FY0awmVJ0O1ih/dvANXTRDoabrcU
ddu7raHa88boYN3gi+fw0jlSID00gYGz4wwaq6vA3F+61ptIaVNDeXRc7Kt6SEGepCQ0sH9+PNy6
qveT8rbJYN1LHUtPDCRiqfmY14VC3udqB5inXfILdYJ4RkckfgX5EB8Cgy8FLMLCb/XsVDT8tYA7
TW5VAkVmR2gHo+r45+LqC1dsYD8Dp8/COURp4mHd0z7DFYOvzTCWYX6RBpzLkT2Tlu5AGz7WmjRw
pneYBCeUWglNV2sC6QpwCBZ4sMPPtt/uRAlld7ArgmEHkl/VMS4RbW3zdmy5qmwEFQnLMJBeiosb
KjKJY4tTtQgZA6EAzGoJEu/7wujPTk0joNRWQAt8aqVZ8ZaQuTIeu39B6ZAUJwKyDJFKQVaxZoQU
RsHxUVpyysT2czeQE8ABjgx0Drb65xYV4Uo87wJ++B2utDyrnDfrzU6iZDnzolxCmO5fZU8dNmh4
6FtU37150sfkFkAfhc6nPYT7z7Hnn9ZN0Ot3fZRT341sj3yIj1Z7X/+Y1s0ASVmotXkaOgrvKKzi
9T6Pj/j56RaUYYib12j5t8+D3HYEh7P0681pipukcEdLS39MiAoQJ7waAGy8s5e+kfvdM1218xAA
jNS0YwQAJCBVeOtGcyvO8L1mzGtMDoyvrbdhUhpm1NuoqJ1PbQuz0tnH8gZRDnkJwYfb9LO/Aw9z
xUjoWgsbZKN/Vr0fTAPX+VCU2DUZsVH2N006XjshqXpR2bP8c2C3ABHxFvEUNtasA2k5/lPlI9Or
kIz7cNzg6NsohfdWRpJoX6gBjhm1NjOFdWrf5IjjEJDcxWBmF5AAM8tibIgYij3Q6KS04lbHXk4h
Uk3xJm701shFwSJkFdvLS0fJ7MGAAfUku94z06kROU6AcUBMx/xVM7QfcwuoycwWLN2S4X/44vdI
4t9/ojHDoRlasO7lkc8oQ/B2Yhvq3z0RBb7nvfUrBOgzisUFSS50v3JL/LcCvYKoMZV48te6zZ7G
oBoyjzxfehZkwvEdqRG614sjz5RziKESv/BzjwQJkJ/abA9U68lqtNCqgadp6P72VQXhafqF7/0M
/T4BEnZyglv6SL9DiBhmOVdT9Im3g4TXYOAAPWwu4GHveI3gSC1nGssiOoeSvW6hvrWFiybJ/9pS
jKLqqbwh6ixolKkmvbrNzYCmrriT7d6SDU3jSVxCPkgYpfsimgQ0ay0WB54cmB2iN7LcNZx6RnwG
/thNguQsvJxyJ++c2LsbVQxSKxjBQzUmQ1K13YfG9f+yA9xXY4rUCNJ8k4zHLLYrRcb84irItVcc
lV2yR/zdD8Fp8IAHWwvJ8LAyWosIQ3CnFaUEObfsGTNCKA6l3rw0LH2LSpOgv4WjCQSmGGg9PaUK
LTAELRQ1XVXrb5auREoMwrWHDWLUMUyOiuuQ3CY6ZQluv4FM/1izHj38Qxl8hPS/fqbbYY2kY+Vy
phbe1NndQrpjHa0WkFZULkI0Pnqxy1YXNr4vBPn/d326yJBTJKANJzpNOhgNz6KcuydmGJgsocIh
xKlbkoUHBVDpdmxtyuzOpBjExBnsZZOOL72I6iUq/I6lMBNlXe82UR3HsVvIEx355IYlEaEgOSWa
vZkkik2+1WwDr5pORD1LS6AKQSdX+gT0AGsu4i5eBUuKzyaauOizY8rwJBLnpcmbaeMxLKcRvAyE
qV6tak1PKhZ9zapa4hREPZ/iEuxxk3z9JmZ41bAqPbAKERGpFYdS7nZc0eG0pHXJbcHjstvegF1P
BvyEo34X7cLLV51I4bzNlpxJEnpgu2K8IpG+HGfrgOW6AvBCuZKm1MK3Vs4WRD2JFbvYKEv8vg9F
pG1RwT8BgPhI4V9ZV1rCWxsXYunoW7ULsNE3jXTmHQlNLIV8g9U42O1etnusE201wfzUPW0QHyvs
o0E6C57dHxSwTsTTn0lTlcUWf60N36Gl9YSq5N5S11Efya4Cy7LH19cuRMwysW3gwTK0Nw8rKHib
IUL6wvRyiccmAe6O1D6GF2B6KSWWX9YgEtfpHup7H0eU8zaW9b2b6jeGoN+EPvvJQxpCeXbA+EgG
2wsv18gAXKZZ8KpijWUj4C1kI1cahbTvteVOGjzoCGBjLYolwpkLTVGGneXRp0KWakn3WODzUoN1
KfP1zsQnr+x5mnJZyX/BQ9cpq1pjaD3siayBq0zHBNKgXVfi7Osd9hcqbenM5t2FXM8EyZHA/GHP
Zp5nuAiVlNwat4wenqzi1imI5YtrwFEJdB5ei6Uv99DSgbfs/IFX/FsZWqbpp1djXVO9ueDCo6yN
VvmVgijF4LNAtJbrkraUYcTc5GjhHwI0MyXB9L3YIgXRBYVqbqZxEnrTTSibFrjHJQBjrBgFEkbZ
ut/ktdlZCuu3X6a9BIUyXDvceRctOzYTbgzZ+q6cu6tqjby/Ku1jB8bfJWx7E31fZGMrOwb3vlG8
y+7/OBxeEpEcUnZNNn4STMIsgUNNEKN3exXwszYKZtOGp0aJJr6r3LYPZNzdzSk+oJQxS25U7RuY
jsotRQZKMdWAkJsW6jGDe+fNxTcetolm1xRWdzG7nwMOdM4m5L5MEXi+Tm5PMhSRJmnvrBIhGLTt
AM4rwVqCo6ibkzbWWtV8KJ8bWCP1T4dcucYebXSHRoC9pXjnD4BHty0djDyHTqeLy4HpMmKrjzJq
+hfS3l1aGWpkz9Bf3bGVWGtBYVjo8fjwUoLycjzR7jcfZmw6K+uZkpt7ko1PjTCux1LJ2bMbI6U6
5vrsL9Mejd2wze5KvCx+HeOPjxTDzc3PsbGFL4CvarKLqXKeKDZ00Pn1sTICWxR3GoYPdkVHnf2T
WHU9YcPxTPw4luznvgmcPhGCt+d+0SoGdoUjOkUXLHSuJuAbqbX9VuHk+gKQsEOKWDNyRHPYGc5j
MkgQAkSDLT6eYWObzAi//8fDLnLgLj0sm7r+mshQCNuMGAH2jVRdIs7G9Lz+e7xfWH0UWRN/Wyh4
4TIzfYtvGKbqU1+DFg0JK1pEPbUo97SqpnKuUt9hF6jzSxZ0NbteWfql9p/7S3l/+QNAidfxPhsY
qF47saGeNLmMBu9Kc1O515a3mqnPRAzeTRJ13AKRP/b300kBrkrCPOpnGpR7cU5RbNj6uu2hVhWv
YE3orzg2pSD7ZB0n7K2cJROkKkppZN1ndN3GTsvjBaPvADdgG+C6Dh8+dn4I3ix0hDPIVXDJ2eR0
Si/3pxFXkaE3O4EOZ34m4hrT91LJthv544syE1Utk96GXBy/ipawXCrUB2pu9vDRdhIEjlYgFhZe
fI8U6IcOjp0Uv/Gw4iN+eiqCfxTEoVOkjuSxAyOhYFn4mOzEfp2nqrdqr5PNZdbT/RFEQ0KWsael
7ZQrLBBrQvPtj5VXfJ3Kbj1xrPmymEr02mOYwdWkfW/01k8/ovIizqH1XtT/sBN1iUNizBvNo+jd
QvsIoqSpMSejQV2bDO7QKYvTKApFM4T0hultcBhJ/euOOaweOGxpndYCMfn3K27sz5/bOSplVape
NmeO0xGLs/AahuarkWiGFHCIZqXlDGTSroijbUaG3gs5JJfPcgQkQKZXnOt31364UUzHyVJKaEUk
pcpGEUBTwq7dw1NkuW5MMgN//uEf6BkbVT2lZ1A4X7QHLZC+YjEPKnla+ObM5yd5Z/TVuDrfC+Ie
KPnp9XOEnA+9awu0cceOIOe9CgQzCxEI4EWkojIWmOViB8ieijV/3x7WqQb3f9GYasKtMH6QMh9t
rOkFezYfO3DgKd+WWiOUphW7RcLKB0MNnLqbU0DYwqCPpl7dgC44BmuTPn4aLhn4uGUAOF+vFc3g
6zUnvC4/Up8GEjtHXnhv3ZmOzD41dAKmUK6S22S8K7et2IcOrd1jygjrrgHDZWpYFoty5LawTBVT
NryjWYC0+Zc1DnxTZycZ1U9RCTc2XjTztFB5/LKx/9HLMNrlM8at5CcaYCLrzdXp9F4+/S6f0bwS
uX/EY1PNWn7VEWHZ2Vi7//yN58ado1VYkWGXYLO6pOi2HeDkBmUs7CoMbCeWlKIbrWCc7xePUM4U
ewyyZIggMYnIRCm6o1IiNBMWFnjlr7HkLV2i3GFsUDPKGze9ctuF9NYeAOf7Wb3Y3LFJEfiDw+dY
DuN3n9lct3L+pXnrsfdixrxst2LYmw+C/MzDQN42JPdxijxeH68XJn19gyiMmtOblTQFXPFnXWp8
owlk1DZaRjDDVpxV/n4pDGBD9ugJ+FSQLJ9MLvWkznKmejO7r+LnREvHHTn3QCcwof2yrOydSAvd
4ypjPoKBsGV7GeeDReUQtrVFSY20RPKiLpeS3znNfTxPJmOpO4MAnYcsCUsOVdmExDUUKyH0H4eZ
fBJwlK4koMCZ3pwW5nuI+6StnE3HBHe3UxnanuQAKKaN12rqDF6RHedu0LTntAmgElytnvGqmjNQ
QzZ3XOpCMFzxzEEhUP82gUUvjdaze/E82RMBbipl2X/g3A3hHe9MhFe/9/IRVFUUv8Y+w+LsJyQd
sVCgu6oSTtmp9aB86cfpysjdl3RY9QgNPkUuVCPxGZ6Jhm2ZlOqWcLzRg5CP82EqKVaRfxxCr/yu
XkcILjTIv6secE/emPYukM4vVkJW21bkbk6eyxmUycRUpzPGJEcDW8ahaPknxGwTYMcw7l5eqwV2
Xus86gFXVDnVJr0ELfY3BwB5Tq5XXPxx69u4E5Sj3Aodc/nIuTihpxi8EkYw7+PKSuZ1UoQh7Q2O
VqKOAUi6u9uLe3sGOC4sGUE/4TjerGRtTy5JsHR3NoEPsERLHlSrWaR+NR7YwkczMNdvD1n6+p4f
sjE7njwKFGF/mBsBOrHFxJAigQl/VnOOMfwDitCUjc3FiBZJJV34ceOkO0dYxtY4B0x2z/1/NFgn
TPfGtMJr9/xWb8Yvf21pes99TyLA/fAg7A5z7oT6RRx0n1an/UkrnMMBYHpUutDWGuoD/GbxwvFP
AZbbpIltaCnlp1gfcHhfE0/2KOUESJgex4oG/4lDtmFUR72vymSaR+ibZXwooPMqRyPRtaBUGXCQ
dSOa2eySkYDJFS5+usQA0KW19pr0FKgtaBUHpkwRBKZn00P8U3pu18SKUpbYBvHXm3FQWvq7/LND
daH6V24g10kyCnBdXSGCgq0rMGhqVMo09E/0+Q632IUeLxl+uRi5GYi2RSRKxb60Erq9UUJD2/KT
Rf1fQkVSqHJZ/uc/8rKElnKuaFDqhKx6Zli1hrOaIDjtFvznruH7Zd4xSSAdU2Dkik5ClZ3DH/UM
SeR6q6+NHY8NB2Da1k5bOgh/YP0DA2klp6dK/tSURNX9342gQQfmnynYC9+1CaLIC61k2u/PAhpf
lS1NaG8+NgLOLuNtQnXkaJ3y8oQc+5i0sukHNbcE6/glDZ3nlEbCMzdJSIQj3pP2+DdmKzxOqnNm
TAD7xwuhzfJr/C82CB/c20GVp/C7z39BMhRcMme/ed9xZYGPOzBEp6PpeW5LylgPTogUNyy75UDl
Xg1yyFSrq3rhsSU46xlWlqWcFryUW6MeP989NU89jaez2gBjh8jRoUVMl24X4QzbRpfTTug4DOeX
6DpEMxmqFCxiYP2m7XtXy2w6/p9ta+Ncndcb+lBNZjMB7JdCzcBlbBnJ6Hlh+t9/rib9Clt3FEWn
tz3wH1AC0AvjXLzUHfTT0/3fuklk4LBLuRcgOePbvrMFDteSUaEpqeyX9pgjCxTIlqUQXerfR+2S
9nJVg5jaKMhVUolMSKVjw1c4lqMIFRt97+lIOFM1YJXVTCJn8UMCLNj4GHgqP+PoJ6aJRylbFJAZ
rsr9xEjhgUFnUbctZQEsP2YiQVGAnL5H/dU1K7DoNg107iQs9I74AWckfwR9OyhpmRpEBvwpDuKx
PSwOH5a8xttbtR4dZkEgLbVsEs749zjQG1UPldVAjku6H4HYH+GMc5UeDl/vGvdZTdgFnUMEQOig
XMx/N1m/3J3LBE4R+1s1qC4Turl9Gz+pSPPGdtKCvTC8t6wBbnUKvGEbPpgH0HrTLBaXzQ2Zj8lL
J+9ToFMnkaoSV4K23xVTC0/LbY1U4gyVFpDUnEsWmUILZT1Lzf408sJwoHJYI70MIUA9Mst1TGY7
v43JUWCuxsE4n1LeUBGqOpiRQcYnoLREdQE1Vcoqn3OrS5L42Zj/1jaLvmaKahaYUz/Hlx0h1ORd
meaqmo0VH4n32qnW5jSLGwtG1/u1dowulDScO1jD/d1QDCYD678hMtaH+rexxpTy2lOC0J0F1gYC
K65zae5lDfnr5DDhSQzxMOTCKjI251HC6UYw5Jw6Q6dXvn7THYZkGyRK6fMGpmi5I4BHVQg+KVH/
60BOylEGzh8+Ee6FnK3iKL2saoQbSwrSDCKdlZk8840IJDq9zUvt27OAhOMpvMQeOX1lgmA2C3IT
M4zzLsML9envuVkH7w8swAf/bn1OoV2aNBv5XENU1VaWf608LJ/b4hcsaH1LV7EyDnCvKjD4fJtr
TVFeLU+gRA2edBm60o3mTSR/gTusH9jxQ0QbYe7uH0hds4JXoRCL3IgpW3WqxnvR3lWTYgUdAFqP
TNCG9N7cdX/k6wD9zQ2vEiNhGA2Ter9y5WdV4qcISoWTBbROiJjy462tjG1+nB9JIpFxJaqSqwtg
CpcqCh5QsWnBkNIObGcLCWbjfJHHCvdi9U68FUsGXN28MZvcs3FNq77eLgR2pSBaECYpMt2hj6MV
pHcPGRxdrJ4ZU1IO5AKdL5oXDoYHqZmUbiuXQuCFUtpPap11/JFB/0CSnIJJQQ8QxK/UzQ53qVXC
m91gbwoTlJg2SZIpyh7QvCYk7myXn5hsNXFgygUGJ86vVQO8tu8Z3go1RFgcXjaVKOooXU1UqNeZ
+PEKQSje0yu36W1VZzDdR/DtjdL3OtoM/0v4VpRvsKocSwnUZePOdCkI2ymP0HUy+eGZJZl5G7EP
7Pa4YZbUQc2NO4blr7SExndtw2jh6Y3NMpVadHbEmDPlllEuOHq7i65XMRI9U9T5SdUpCx3euN1u
WJXJerTIh38BpECODgQJxMGFyeqSC0XxX445zlyL5asUirfUpHBzcguVTV3wH+eFJ1ALM0jfbLAh
kCGw6WETSTk563+ep1vL0+EUAHmNFFvRIRhsaYiR2xr3idhf8GqjcxkIM9/f4zTMgJzw2cysm4Z3
08lMeTOr7CcqrwlQsonKFb2N/UFA32a1pbX6cT2r4YnlQ+e3nLohwMZa27ouX1/pHCB+0neol56k
wVVFWutdaM+xPiGI7dIyrWZgZcYrQcvdsfeNT2pSuqaUWJdZq5OwDluE5WKO3jrgHTjVYa86hh6m
NEexzleeVK1wkyrunquFPQ8SX2qy6+64CMyJ/GteHxJsm9fHBHlCaDj+16Gqc3HEi2uIzYI/dRwU
VxtbD6+tQoxrpZg/ax8ZGJUAIhUmfDfeCcl1beyShdG5lBLWjcxy+kBd5tCqKfU1P3aHqso+UFgD
A5Jsw7CcPAMRDaPKnTybfItGVAxgSbVOxR0CmxyUukbI+fht2ZT5IrtSb01cRnDb6shln6vuomuR
N6SS3UXBu1kf9tDsS7Xl13rb5aTY0NOIIIL1YJpjWYnCsLz88BhJP6GkhOLX5xtw+ojoLAtwSS32
VHweCKFheisTYEBIxX0XNsOxqCkTh2Ot0ISPZZ7GFa34YS6MJQQEJ67gsWuTy0B5tTE4QkSibPAE
rk2b0NZNjFcBFgSYqnwBBMS2eKriRIYQwg0WiJs2OrU6dNeCGkjU7OfDSx8SZOl/720+B4SbTygO
DqCqom77vG+T4fiB1Zh0txCM1hVH+bwy8lDlbht/aaLztDfzePAB09iE4jBlRsdBOQnGd3CyWvfR
RAWADJPtGiqX9yFw1Vp294AFYfj/yeIzAfDCMsGkSXOlr1z4EkSPKMSqOrlJGVw8wgbTF9FXZB2B
TY8PBiBabWAWPfwJB11WM8gjTsBuSqagjyMIc4wo8zFJVljBL5kyTYbSV2du3zt0ep4ZypUrrFo7
0duxwcYVe8Ov4WhkoiedQ4veH0ZfSuSXY33tFAdc51UirsN9f4r8esYg7kutZSgjdNdXxOHDPfSr
gHaoiOT5VrxSPJ2lWSPJ1o5EMpO+6xPJAREdTqRJV9WdCDjOL8Ilny8BWGarmXZnexlCpc+ZyG0h
14fVtTpKe7zi0XJmPTwjYB36sTBZPcIYrA5ymmsKvAKKwAl1bGB4+69UMVHqAKHECo5OzIBqPp/0
CLeOC5CK5kPi3KvEqat/pRO0bKgGkNmEFV0USREagPAHcCRWKn+XpB7tn8MAC4GQ3FxHtw2+6JOm
iPo96+9wO9kp0JhlHEGyVVO+2l0988L+b/re+jIQ6oFxNhB1KY2geOyz/Rbf7H4eo9S41ypsaBXQ
1xOS8HhTopjApHQIL+nQ3pJJEqj+eH2M4DcoGnAgi1Xc+2caJphPB/Tu+coSo/bLa031C71a3XQs
/YKDkb53JJBTzyiQUoeinOGjKNqSi+b7JiK4h68ncGsfCf6y/ax1SH9iC397+1NqBWaX2x9lNAWX
m9X0iWXvCGJJrfJtE0aRddRIkX30UuTYW70y9ul55Q/6/NeQHiGlHWztvv8zvLQbteMPQgQ/yfAh
8kVZF3B4zti+DM7+wnNMoGeMfqXHxltQ7x4hdjcmdFKsJ/2dBU01PQGI8nacBzeRdZYMnrTf96Nz
h81eUjAPb8qHVYjObzeEqRJXmM+2nG0JjtdcdgrhrejSbiCTRhCri9x3Yb8O6SOPEJDjIVdvnZ5U
k3kTjOtPQCUPoVT//sbNayGNSnjktjz0fseQHE0LEMPGj/HfC13ejiX70lu3bsS/JCQF+feo2t5W
vjNvDA6Q9a6X1iUi268GKYLckZ7zBHClZ8uAeWQq/MkPideFed3r1RnpGw8dMDA9SBBxNA2hnIn3
+JOc+nrajDdqLVh6PdBAvaM7KgmCDngNsoA9a0pdV1Ligs7DvzaBJo2HuHPJNcBA1JML5xnRL2sZ
qCNtCipMsKCkNkUVAlrZxmIS+oY07jdcsoco7PeMcSven99mfWYHr7B0XxkWjoREkzIncTSftQlG
Wz2YlKEQ5r+laCjFgvFKGZ1+v6024xWVz65uYM0TaXxr0BsUnh6MHkGA91gbrmsQTitItOiV23sy
xjaz04ipi6OD1keOol5CjDDZ82LJV6XjVQvIMSLM2s4NDXyXJnL0PmOtSr7vmTlqJiFllLAlO9K5
T/0daQ9lJOxxthJpEGxuTHaONatahRDXjH1o+vOOwStgXplBbdvP4bxiZG384c9JlXx0q+qa0882
IEpXy+2dREuk9VLfCcHj0H4mi/i0vFWysAxbBxxwGeXjt++NQuE8Xb8SAJDdOdtzvw40bqK6lu6t
RgJfC1Ot63IP6LQKwOmenMooxf5+ICCa93pDRdHiW9AmE55rD8Uz09HSOm5I1F6OEQLz3+WGCvZp
lIyr+7iHoOqET6lYy19gC8jdlg2G+u3McnkornvE53lJlwm5Rd94waMB/zbBlQiJsQFaz6f7LkDK
2qsI6uQWnEWVWzbX3YQ+z2xMV4hXBnEXACm8NWMShobsYPEuEfxHKI4BS8Z9/a0DhBlAQTbC2ES7
uDjIh71Rha99OFkjuvSI15FGcSqJuqQ8/yWnykxq+GWXNikezdOhhdyOwqqUJ/h71GnsYpF0lUHE
xmMLNSddySrgdeuoJ1WmqVoMSQkZmKp8Gbu3tGGv/ygSsJAm/0pBVUgDUDquCNQ9gtXF80S9Aux5
QMyNlTn14rrWTeHBGp5rDqg2LL7ETGq9ndTLu3I8lrCQcjex66DGICGpclCZCFVX7CPYgr39/sTw
VAo9iCTopno4Odtve6etuxAfNZrgQqy9V5VSRHlpXNluxLWHf7Xe3fi6pjp0jhil+26jjum7tCdF
iTcDL/2CFxdQ9awPOEgZ5Ji/kXSbWMTz1GRjglVFuWPlL3h6+dEi2d3rJoOZb42byXDWSidoNoXG
Ee42GYpeVxHFU1sKD0LwbUNxGiEocHpj+mSS65yH5mKBxX8F9a06wVh8xOj6LKADvs04t1EQtxNN
tUCR4fDxK9dbEbQhMZqBLXwUBdmUg5K+PRHsp50gLQqA34Yc2QC1sswvy4ao4eFsA6ft8H1cdwgB
a7LhvssJxlop+7+/tYbbllPPu3HdYEC9mijWnXisKZQHj50+9QjyBnm+kuaVbQra2ITqDOJfvbps
LODhZHW82clcCRNSf4Dd3vKXnrQjPgl+WiRt34LCZmPt6A8qIpaZ8KCd8xZarv6kz8ZUkOKBam6v
k+98BggOJVFg2epL8gO3nlnfHz7v+XUlncQxOc17vKgI3ltbWOLd1Our/SQZuZN0kFzSfmtAZCbp
orz0uK3XiHUhs4vJsPm75cIG1K/Hn5mkSQzcH++yQeNsYEh5t/1f8eahHZKIL+5FNoGDpZZanmf5
aP8qpA/eGEIJE7Zx12s2eAgG/b0++YdfH85yAoCmdwK2AOSSfJjiM9nxSXAkgA9qLGEQlQiGSwOc
sMfbNgTi9z4mE4poahbGhrHaxxpsh40c43RqrmhBj8ksPZM/ZQHWq4B+fzMv0l/Ki0Okcf9NlIAG
M4RZ+HPF8yj+F67PsyFpW4eznjI4MAVAjOxy/rb5CWrxxm4eTvQRwQ59MpQJITLEX35ofwVDtYjx
qkfEdRoPwvD8jmG0/kUEJtT+4WTzgEVbbB3D74KZBk6awdT/BMfLss4BSvNl8SypTHYREHI6tgST
QKC3CCxbi+IxhvsTnNhfmCNPzQk066fQz0LSQyALTtipRTbDKRBz0jrFt3cc3FKYtHCFU33yFmpa
M62aux2vKBiBoeF9HpHTlG+tiFdiPRWB3LuFecCLXHxUEdVonAsD/x4juEexGVZ90ErRy5/zxZer
EYc6v91IsOAfcL2xeesQZp1ullmALAlDHErtTKOG1r4uzSw/0GuWgMhXnIfIomiUEQvyPCgSCCaI
nn2pdcV3T4EPbHU4MwY6r/5i5xhBAdbsvVqtuTIshcOn9iQ4sMgzhd7vw4n8as0YEenu/vvbPFw+
OCghkal8bGZZgnBTisX51ZFPfUIZw7qzno1TAoLyWYW0mFjZL3h8bk2SPQZ6q1nupfOlNPLqNNYF
SYN/evaJ3QzDfqwLR2+pBAR9pcybbm/yuyvKf+IQcdMrhwRCefwRNrUr+uSHP4zxNFHntKyG+R7U
1g1OAmuNbQWNDL7eNx1Z18lgbcdIUX5lffCnEddUUf5cF66lpcI1Z/a86+gt9ZzZeDC3V3qJ1Btu
rSI/uUwz4ZPl3fXKXYAMCKxlGHVmQI5dl3BWuVC+/+wwf5yORCM1HUKSmdg7eoJveKpk7xS6iA0o
xsqo3jK02OOqfGhwvddSO6ISlC/sOutQ+ByUtSqYw8+ULh4VgeVsPLQRj3ciHXaKO0xcZVRuSPzd
5BJbBuFR29QhIr9fS5/B6K+A5abSlDngR+IGlxymYJoH9UR1e0lcxDhfsYLbFMGL1ABJp+G3i+LA
KoqHQPGBkbrI2Ii078e0Q/7qajrRlMaK96ZcqnJlpSsNou47CWRK4cJZelGcndF2aho21rmsmQWO
Kkx9nrA4/K0W9gKbRFSjGkET7g/apLz/REsoexy05bOwT1hAe1hHX0Am/b8qoYV0wl4JQ8cwyTkC
KuNCcIyJTyDrG5whcwjxy1ylF2MOj7spCvm/p+/5tioTjnk/+b6eBPdooF1ErXeWDk6vtjPdusKA
5fbZyVZBihXEwNzrUcAq0hS98OnULRTaMRyD2xpRICamx9uYN1/b+pQ3qPXXIKtOXobbrWqTA59K
UJdjGwdQ8HzaMf1to57btpHVwH6gRbcqc61QA5hVW36LeEtydeN0ZFTGKbLPUNyNrZD0Hdvwnl8W
6BIueTjwNNkv5PVcIMuJUDFcROW10055Gt/Q1a29CQgpbaVIwlhDjcYYB5zg22St/h9iqBlQwJ0b
iP8hXWbJp3LuCG4BcIOXdboWPVKmOUFEEl2D5TjjhLTPO1xGBSVNzpXYhxEsQJigOsZw+IFHm1Hp
84MT1cPoOwXa0z/uf3rQWGTTb7xxhWfQ14Vz+sFkX5wP6Cc3CB7rVkLbOTd2KhRxq9Dj3Ql0VbcT
npoQPpHBd7x94F08XraXrTQz5rBthbcHyrPNGvU/RLJs6SX+mAp3zI51cvmmyDah9POf0aZ+2CYl
sstdiGXPwora+wNhfPfwnJHlZvMO5CcrvDKziCq3Sy1hFyTZKzTSLLs+dqwpw2p1BFuJ5fNRWx7H
LboKNsx4wGX7iNZPVMlzgZtqh/QoZTgmf6gD4HRGTgrtNjSPVSPy0xoFq5HxyAisxt+yaJxuRmw3
yuJ1Z2We2/cjwdIwReitDkEjotQfSRQaHObaUzSCEhslbZaMLibpSSLcmwMrfk9ZtUBXGhpUx86e
B+HYLZGs8fdSJ3WWkvufKmSDfEBXB+KmJhRYfN3FX+pX/s2KIsURn1wDqge/X87rCEY1l++59khX
q6ATpTUKcgWb5U85KA66fK5p0nHkeIU2oGV27Mxd7MGqgEDJpMb8rFzn3ENIh2yvj3pcKmQmdR+C
JHp5rGyDf22zb7SzLwQplUD+nXx4BqzicAPMmj/xmoN1NRmo6Iwqg6dOyXt9kOyXyLHJESkmpRU9
1IRHuvWTx5CeiF8PcAK1cIanginwLfRVyotT7UbYVEcS9+/LjoYId6klKIIINRN/g+IKhC+pBTgB
RwLGZTiqB5k4OIbVpiJ2Bvzq17yUYqGHxQca7ufWuMCG6UY0BXmXwpsphFzdqF77cxpgmksqTruB
/Sa3OPakpn89i3HUGGp93A4PhcllXdYvOr9DgV13P6lWPsoEtfQ+xna3u0+FKyipmlBskp/FV9Rl
yzpjMxMs9nhi3Nq9cK3agR4AUGitHGKWAPxm0tUN+2Yz6BqRJy2zmc9igPbM1y7YoPJRKpPUUvPp
ZUz52meO1kwLujF8o6SOfkRsjQ1VhhOX+d1/+PveJQ8m3aDBBtN1RufsR+2RM0aH5U48P+7ZaM81
sd1TnIIWAhCllmYVFzlNvZVYxnn8jb1cIYcTb6Lzo/1n2t73xmIHIzCktwqPg/JePu0vIjXj4oQ0
wOxvJATTuCdJxayPbnQbslK72/Pcpma5Np8ZpAkWNJAtkm96NrHxMA4vOsEAk2N5+QWLJPG8QfZj
t7xNhdLBbo+pUOSf1XMjyre6A6B6vbt2FheWJmUE5ZPOu+PxU2l8qDru+/+1Qfwo/jKWQd7974ZA
8qiQAPwfRiUAQuHnZamdkF0ZF+IwvgYheLmNnYNBphF2dkXwSQnNQyaCwLEZW4B3RFAtZdZMudtO
6sEXNNRBrtXOSc3fjC+Y8sYkg/pEdxlZOf/JaBS27ASZwrXTCfWQr8ayT8Tp01gkl6VlLuuRf3Uj
FeTp5pIleTeyfXwDx5V/eNPNa5FjIWSK0QYXO+2mohIE3TAhNh3HA9EcbY7kENwvGnPzkoS8O+D8
iQ6/LfzRo1l7L9PVIViO9ITIB9GXAgtAZmvJiLMosv7uYprqpyDCm3coqxyUvccW7B9HD67eD3Mx
8c4dIsPncJVIvmdpCiHfSH+N3MEbaw77bZJoYDO88O2pMMHvLSXDePiSsoyVsRL8etBBbzvW8VEx
xQKsrjDVbkx1bVXQ/QjE7fZrV8n3C6WsC59WbqQBwHNFisZHMUtXv6GnXoeKMJgyOr7gVrzJx0ek
vo0JypvKz3g4kB9oLbVut27+8rKLy+PHMkvMgbZVfZMuo1FIxkMdQo14Du3TcHvDZPqZH1NUKIpA
curabw30cPgODUq41ktSKwZm8LTzyF8WzBtL6uy7AYWn1CxR+LY8C+GIxW5jBVtDYyi1jGp3cgpQ
8W1FDkENWgoQRiZqzBWu1rBZ78wou7BgeyNrMZ9paC44hYrKeFkjxf7DxXt4PpKQQR3CP5VNm6Sy
4lhP8CY7T6GLRENfarGv13gyTph6RCKCwIh1UkN5Do/aEf+g2nHFA61ALfYOXUIvOGnLeBancpZl
djHll9TZyOv5qN5pjCIFcEC1Gdl2273T2csueo2KdP0PNkl/OvpYQ77XR0tEhB3lODQefLpv30I6
CsXhiVdtfrB2xHD/jEBN01hKSliaWSTozagE+p6Lu9DZPLPV8idA4RLUNV0x2O2uIk/7oXk8FvSz
d6tn0INbqWlz9VToTB/cFJJFcMydzrjCFgyuVEWo41XUTtJAp6K3an48cG2gS3z39LamkG6Mix7m
Z4JG6TKJaSNyPgBMOpQ5MARmYIqkNNiUTWfW0GPT6JqCsr18RkHkUtCpmD/ows3seabwbSdfsa08
EcCZf70uAih9BroVfvMdp5AUTYir3iF/DErgvcUt/EQQSMuNQXO7/0ss5he2yvBq2bed8PgwzuYm
0R0x2Fq8Jj0A0rr0AxTndyvkw28UwF0fws1lUDbhPydPmhemqXegMnOpW8dRQxZpA78vf2HoCG9q
XS8eoCg4LMfKMv1jblNQZ8fzNgVX7vgKYEot/s4LxtfhBoTlL7savfwZh4cATvJC4DUtkrsico8o
VnAtRSrgqRv86AiA+GdwjpJ8IHWB4jDE+i8wvEllSVEwJtGtJy5OSUmpjO4oeTUReT15NZlPv23k
nWy8VE7u2K1J/SI2mpAUG2LZ3jEoOMeZRNjKr689WEc5S676ZUsVqDE7Rjxlle6KuQRDLqas9it5
0TekjVpu0D9OnLAzZo+KPJRCgaMmUNIQkc9HQU5Efxk5ytYoMht+C3grLrYvsEygB3CPaZF1xMsg
p8qjm4eBqwI/V/sbBLCpzbyujmTmtOXMbM0YOz6Xi+pDdkiiJc3u6bIh7+1b1+xbrsyoZUgxmY1V
rP1d170dvCYBhqaLF+W5z3rFcGCeKRWhdfBTOCdb7Z1G6FzZ6yh3ZIDtaRj/cGXQpgCTUmwzrDtF
8fxxOrFVY5QVE/W9jSlG9TlCjhJgifAWzIZptG/POCiuMFJKKGP2PRS5QtliQUS3oVXTFLBAt98z
xeC7TvUVyy0fshq3XsFcfy6un+hfHmyYIXBQAjdJFGAM1yuphu3aFstB2mtHxTjzhHuZycjGRokD
kwn0f9o44ZEJvNResMV+/ASrPoZnDY/toHvWPRxGFYYHzSe8QCyCauq7lHUMuyl1BRAwFCsCkznK
GLMphDzD1rBb+k2gC/75632ve+cCbKlC0kx0bm6KB067O6qnNqxp7aH1Ql4OXSWuLpIDWyYB4x3L
NEdT7+PyJLaRPunMr9rww1sV4AixEQsjM3psfr1t4dIzOordT887UuxPWKXKjRJOdjY2WzsFl7FC
eZskqc+2upCD2vcgzVgD/UHa0Id4Vjalp+ucMe1Fej4lOsou1q0e+e2ulZEEt7b5lDayqdVvpiPY
YMOJsx3V9meRT5cSSm0IyuK5APwRMnLwp9Gl1Bxz7B3dG6Zzn52grIl1wsVDKMKeW7Lvh4S/TIN9
4T2kr1Z9apoc/qa9nIzBTPvOS3Ap3bccub/zgt8QaNIWFqBDRgmnxpjFJZzP8wkxmwM4Ix221MPW
WKG/LZgbM4JcOD3iJ8P9bwo+MAgteyYrJuWpkKKIZCK9X+MYq6LjlxMTS23sFD2mmAdROCOryz5S
fCPQtZdLb9CLh1ANpFzJXNWVQ15bGQAubjZxGtIHUY/Qo5FWbUgF0oNbIYZrJp94BWD6qH4dk0SO
t8CtSmY2E0tUdHXCIbpfbMO9Foxv1K5/2eJfulCFv2aulC0BHxAymKU/4+qLgv2mGDPKztM29L5e
nC8KAvOdM8ee9FxdoTYh1qzX2Tp4J7r2Kgv1qlCn4ZpLI4XiMV1kZ1RzvolmuUX2gsAlmCl8tx6F
NDuryVMbaAgazig1FfeVS2qJyedfuymnlU8anZLk6obX54u8TIyJ0nQnPicNHvUkswjo4We7+4E8
7E64rehzW41GEfWMoKB8CGPWzgpQ1fPOt3btGmgReW5LzhdjkGbmS9TwHZPNUMf5Q+ify/L0BvPY
9FrZJFY2Ehh9hAMI3A2h6JinVBfOJEcf+Fw/1veRalhWklv/O3uAdMhUQ3E0vRekvn9czv7mnn9W
JdtcEkTIkJv8faXv0mvuAnuqFtBSHdhTjgxxLTTz22E20V5sAw/+BHWwuCvArPdLUHxFOKwPIToO
/YuhUhpvOiZydtJ4qhoqJ+PVpOtV85vQQz58QnW0NDh3RA8T2rClumXj12RW5uQN0rEarMPfGyLb
E3oIzIN/l0aAWyd2vFgCgEc3A7mNHV1/5Fb0aYqCJ3GsD8F3hyflC76pQRKy9O5s31lqewoS1Xc7
a2HR54ZDhj1LW8niSGNnJ7o0iuLhk9Wt7XyVB1xJlhcAQ0wBS5XgEmzx73e0gu1iNUDcPo8Rczqu
NhTe3xMnk8lBmSkPCgy3t5q+4QLraFw+Dxp4oRztViDT+4CtGpc6IVXXMA/8T6yLXzUu9KCuOMYD
Tt2Fv9EdJ5TAZS/8/9YPaVTEHnpNxUbSvHffgZpPPSaht4YLRA0WOLvS24Mc72wS1TaoOG+bklyQ
QCAARBOKZLoe7tS8HARj+rA0ir5AENOdfLzUGA/NjYN2fQ20k6eIaBJaFx45/PcPfAzkedExjP2P
ZfBpb1zaAyH3b+HYDXkc9l6rlVh5ngq8eQ7/3H1VoH2UfHRE+4QaAxzBsExVe/jlmNQz3QRlYyb4
V8VSuxP7QDS29TU7nl7YS9ujwT8VaBSn5Voqz6HhzfIaiiW36XpC9lfRqe9+iNHLYpGB6sh1GQ8M
2UaFvRwkUc+rqzJRMXRu8h4dkY1b7Ww6I8ZiDTG8WZKTh0kZVIQ71hKikDU/QgJv/la12KnhMw+1
H0M9Z1lyNmYq/1+/JDqDOFwfehCJTDKIOlczbAg8MoLYMau0H63L9p5qFoNkha+Eo3MousyCOaIl
udtyVDW8Yhr0C3dLdqUtm2PRv6FjEiJdBuMwsp2tPLY3mTwnqvJCH4v5ys/1Mzygab0fwA0FygFs
WBJ3hBM2GV5G/ITk+UTXG5MZrVG30uXzHLt8JN7dmE2POKFrVkW8ts0o8ZbxLnnC3r/GoajUxgfP
6Lq0C8VDDf+fHGlV3ZBL0NXWr3tBQtZikWxk7cStEAmaJs1JqYX1DJEugkcdjGPpLd2sgZxkpCmA
hdl1NMyahmhe5RRYdKkmjoBcAUsdCIxzgmIANYdR4LwqYjqTOxWBcuLNzt2HMjxY5LPR762YRoJD
MA54IcZ8UhpTTqPdClUJ8Aa4MOKOjGE2R82pZ8qhtJC0kOPSKZJBI+LFaT7gtPXqUWmL1FmJnYou
jEctl4T8AVPRXmIUj3vr/6UBxSlXxZoTs+ksTEIy1cX5SaIco+C97oJEpMYQWoJJ64mfmCLE5oTV
lH1ev0D4gHT/LjnfqjrCSd7+6TGdCUFdUf4VCUk7avprqPYFDNQofY2YMWS6uG+YnFy2uPcP+rRW
cUwXWg63vhc0YiN5583G4aW3iaDlMQ5UujiWgpSOveMhRNPZA/m836IeQefMB8ZIf9I6kpZUCr36
oeXVEpcqUSuq+n7y6ocvsy//O/le2n9vbdnVQHhKEiZH6X/NgjEApx3ZQVBBnUHa+E2muWBgL/Jw
DstAqo30XtjzcVhP+LGJ8Y2Q0CZcID2/AZy/1i1NggElV+7KhUP0xyHk7ZhaepRmD+UgO5bwd9ed
gwoxvNSh3mF7n2OWeC+vLSW5S4/xPtN9R/vbUdpN3G2VCaJVPolfsmoFBg535khxAybQ39O/+dEZ
Iy4l7Wyk+oDopGHsMCJhwsZUm6f9ZNQM49WHA8EecS427vCWtCFLn0rvjMLOB/VnxiEgUt/Poz3A
gK10YR0ZYsFd0cPhzHlXkQJh3YdIFpe/wkSBy9MnnSCDRPwHbWDvZnZfhVNySgU4OvvX/PP0ig6o
mep/b3g+9bqjkWxXp2ezl2S1k4eq+yXB4Mv07lqzzTGJh1c2vYdReKGVB78RwYrfO04fm3egxrFE
xEWKMidn5jHknqxiuUeVQAxfS1CDqIhJFvYt9mqiPcArbKLeWlWcitxG/mD1tO6wSYnC0s/psvOj
LHm9DSirI9lpqZcf1+meWCvwlRZAinBllHwb2UrTgh+TWkj8I9O5dw/OOub+Z8sjzMfkBAmYbyMJ
pF6bl+yucUNCvAiMTRhs4VH7syK/lu+uEoL/SR1JNELyu2TopcvVIbFNAozA1K+LB5s0N8UnbAAg
+XxCoB+ie6yBj3swxSSeVhCICp4Kd2CC582OBcrbVq/Yav5oFL4il4MAUnwgvGN/MdADTLvhO5n4
sivWm1spHuS4peX7c7KirZ6/bjjzWHMeRz2j7JV9PljS1PXDhwpxw5ZzX6oVL6G30XdLMcnBmx0+
/sMMHXMN0gPHIeDRjdnA9BNxGTrTht8LXbIrcuSiK0Dkpf5q3PZuDYf0bEn1GhsTzE00c1WRcePJ
CsTbraJ1Y9530xkSWdqeHLlMnax/VHpswChN/aLvjuZ+87dwTPOy0yVh9qClQP7qwm5YwOl1XMOW
xCOdKIyf4JKVsEEAqrr/4qwoMV4mZ4AEK/w16StBDWnk4E9kbvvRzX5JfDud7ifOisVPIfffVtqx
d0vIUcuEP/KI4B8WnBXFp8UWHAR9ktdmM3Q76uGZCwDpqWBgKxFvU8Dxq5fwdqATwzNiicAEz2x4
Hzj/GhBR5qtF/jLyzgSEXee2z5F0xF5SmGKEkoBu6H37Wa1mRA1s/eyYnIXRbPFnQCdWjy59LN20
ZUozinzK6EzHyTgeQeogLUzzGEarOezmHKPVlyiNOjdQCfmXkhCO1XYTe/xiQ7x6s02IVjQwv/cl
fytVYvv8hdSCRxaBug4mSW13tzUL0S8t/z3QDHPcqLkuEGjjtfuYo0MuWPLo8htl/AZFYjtmmVpL
W9syvINx1nwVvK1qYK+zyTEINw2LYKL/VAXQyM0MEEdDoYmp7OghPkPXvtaOPIcxIgy2kf++1aeM
oQOv30/TMpR3UbF7CdyKPUcJRaZkhyVwYiHESHsNN4aCGfrrsmrrfPMWGrXFAzU0ReK6lG5/bDlS
iyXpD7Adlq7T3dzUzp7TULqCKaSxaXpnGF16dcfRXWuQcEHDujPkN/Iod8vMBr/x0VSVGpGFHhD2
cgpV6xR3zc3I7c4HIjmeF5STmxN/LrD5yr1EpSCb1LFQyKKwmUUYI1njLxOCuZ2fZ2ruBdmLJxkR
4GYJ0ZtlqVgu0gGKvywqvR4kqxMjhPpisBRGPeioXSd8OHjpmGD/9VhJ9+e96VA4Z5Ml6Vl24CXT
Fu30lw+znJN/24j2+UqYPaRHNzx9Dk6w5yZ0NYtfSpxpUSlH3aADUFlKXeXjH0JnWzdowU0zjXoF
DGSObrB7Gijyce3oCqPRFqmgViwOhENhBMr0WsLiZ77R4GfoDCkdAU9vWV1sfMnuY5xMFw0Ft7u0
lSDSQz3zIEe2hYhABRexp5v+48eZE5fglstt0ojZ8tcZ9z5EBqMfvp34MNaGSEEwPdsbAaMmOnl7
24o/8wzUSJ8u5h4QFAUS+kZxyNQI7vYY66k3e26Hda3lufQn9yqYoptbzP+sdACGVzRtBMq1V7jB
sWlFr2mgxXwOFJd84wKa9gvDvgHJzMvWbqU61hvYQBU1vq96iYWJzKW7KPylfV4794PT1rvaEG4I
cc9YO0mWiqhpeKrZ+nww6YOWBySrCGJjvGa0F1PGWHmnx2hSkPSXgRtS0ZIwpqiNzthLixPvQBRD
v+gennATBUriNLGff2tdMS59gHE3J7xqsxCz8bt3l236rV2pCCcAgAt0tn5n/y4+f1y6pPIU87co
OM/Cyqulp9XpByLOXYU7jjE8+P0ar2Bkom8ju+Vx7Enp/Ug1EXSi5DHr5HxCGrQme+ctTTH7GcBc
6tQ8RIpa4yrP19RipEp6b0aW0UGOoMJnMaiOVReS11FZjxSXafdk/pbmP4M8IH2HHPK/AdAQjmwv
qpE/tH7AMrkOHgtmlks5y9X6mTfOKB4Vshb5a2ezIVOrz+AREoRpJgMP7gQminWDePxj/xvTXyv4
fqdfpqagYsRXSh2rYyPhCfdVTiqGcQ83HDJQNhSyr5+D6pMpS7hxP2sJyqjBS4qRYI/B0LGEXgE6
WOTCS7QOagRNwyCgDCztiW4GfjSMoI1l1ooiqq7dQFCC3P09eHcwEkeBc0bKeCBaU7KRExzeqYMz
fJYmH0pvorESHyi0h1bSJa87VKq+yZba/Ju7fv02eQNHV7PPbjvoHo1jqlscbBWRY0IYQ8YoHKYh
vPCOxWyRniCVOcoSCN9Md6TXD2UOV79KLBTmhvxWqEm6kZ16ha3iL4ASLg2JfQxryOW8dJ8W913v
OGZTX1Lyur9+1jQi2dHboM6qVr316e/EWwkXv37UTVrwhaq1WrvVTXAaL3s0NqIFhjfrYwgLFXGp
O9mVXbv6XSy550LsNzha3l37Drb9CVdxy5/aC4THtKkhTCDi0aNQ/DNy/E9EkDBEMgOqbW1WupwQ
611FhGSqPQwOLMI5WvDS9CrXEK0Kw15h08Vxg6foCkki4lXGxwG0O4XTARBT9Y1/gWOlVswr0per
aqOlBbiOMXsqLaUirnw8iNtBtMyEY/okrQWA8MxkX+tyAK/76rUeaj4c7R6n1TS1PycH0yv9JefB
WTBgYho7tz+kGHJ985BweJlqg0cOpeKbfWrNhSmGJnypInsbxAIn+/1x2dyQwg/zpNB/AjdejxA4
Nnkoq7V4AneNKCwMuBb9xlTr/f6jJExZTkDZ2grPdteMjIVCW5RthAbVEbUPlqT/5JdPs9QDVlFg
78gEQzkfIV0TZ3VHkufpccbzkGbLt8quu+B6auTZV5mqtOHoPKgK1MnMQ4cOc+YfCIAFOdOShi2Z
t+vsSMTPqt7GW9wm+2ZTUTudhTedxogVUopjNUyag3Owx1+s1Pd4LIDwY5JX3v5Uak62UfVklYB/
7KMIoMOziLF1Lfcpl2nIZsoSGdURGH2RYEwQjFkT+EHqWjyEkjZaZHSqjdBZiQ4dcrMwMQMkiefM
KeXJX/sV4yjbGLxOz+M1mlsHM17JlOo0PEJjt6YiZjmy/jVjIrQUeDwdGZrZLiDbOmguxtGOiBPt
UyKTfk8r5n9TZPtYMgYIITg5PbKzA1ug/ySBvoiUedWoIa+zGlYSMsJ2dX74F7hTcNx78R3sd3aF
0u/DBhel6VxJkq0y/kb7v4ANndngOy3hXVMYvQbZDoPjuGLUeYzwfdXWeakzcy1LDmal6whCzi6c
yKimVQZEO4m2aigv60dTr7RH9LKvSlL+qDUIbyQ3xBQTQP2PxGJv8HfKepS6Tvo2ZCn1mu/BcNYS
7cLt5OlgDlIplrASVcoVs+Rj2aqPI1vioAiifqih2s1emc4ulWT99z+NPK5jssJyDNJwVQnMjFIC
YgTXJYymo/WD+HHTPLkPd4KJRujgc0Db3xxej0OA9Qf6Zk3k+f/gJBT4T2Lo3mJ8xEdErPC1neiL
K+JQmVMqmflyGeD/CA4dmTSYUtiGCQZxae195zrori0gAi1Bm3eIPF4JMK5jL15BJbnzpsBE47h9
97DOj79ZdhLfAnQPkJ/gKSg9vbBLcO1N0PdUHMcZtC1fXC0mUr8WMuOexPzr8Rtvq27p74c9CIF+
F7H9brTPwLtt05OZRhD1Y+q9Iyn8dj3Kb5I+R/ZAPDNj2pA8TXrli7kpojPDbr07ydz/2fPOoS7D
MV4IjJPKgGGFXynOKs7G0I6ozPTlHDiQzgmYyOFkuGRw7xKYLLvg9AIw84/j+iO3n4laSWM8z85b
67NpU8Nl0WqpIYgF+HeJ8uXDV76Wmuy2NL1OeQa8Lk/mUCTw7SFAhUNw1Tx7WNu9gJMB38iuCUEe
DIgpwP/+FTGuQOn9jdzyVFwOwwec5vRlqWAn0wc7uoT/VbPOanDHSmzp4JBaAsRSe2uI4HC7PDH1
h3ElZjyhLsgajzxYcTQa9xX7lac7y6a38+4GBdOA64xAAgML7IIXTzKIBfOas/noPPjJtqUkWBCu
r84cAaWOlHR7rWHbNVcG9Vz2UW2cUooj/r3VrW9tFc41ferI104P5ZT+mN1W8QEhtASN8qe5YwED
RNXN2n6/cyqIeJruaxxYLVs10sGu4UKuZ95hY24r2u/DNaYyHDizKBt86j5RmsiyMLNDsk8jOSzu
1ecvwco6mmmkBvaPH3LW/HiaEYUiVofNoqd3DLsQujnYucJgQufIJVJvD72D08DOj5sn0bXjprHB
ySJtlUeuWSLVLCR4ebW+ckgyJ/7UYanuzjyG35twT0Hj4yacxc+phkK5f2skfppd0iPW6gX6iBgw
YD6qMTVi9qmdRxypPL9T0hXsefPUkm7Rco5ifEstLqzIbxUEZfcEgQLYMG3+ni16X6e/f5enA1cp
qGO5mQ42ortCX7aIlZDsqxxjeXXh8/bcbFaIzTEyAH34pZ9/DBGZlncQnxyG/Ov/dbSrN+Y6i7yH
hNWkHav5/eoFkcJeh5uzeSnhvqQwNsHIkwwHQFzSwJ1DTDWFpT1hvN3YhRz+4OG2hQVi3TarK8XL
uOHvxGOwjNLYReRbKAIHPFIdm/PEcKGsQSVfo5SxMEdeizM7sr+H3Icd5DtyTYwzv78vvGJ67j9H
zoTi6jN5JSPUj3VETfw9OA0xIor1dpWPIFnNrGcEqyndfcBef+S5oqS5hzeoiLlzoD6p6HfC5ANc
oyRXG0DP3jv8Y6SAx+XXjPPnICcrQXfbQNP8Ti8WM1Aj1lJuZACbYVmHPpCjpTcoYKhlYrNGgp+c
pBpd2VKPv3DGFRU4V8oYBikgG+Tt5rhOpK5nQ3lWYjGUg//GFGo548TxZ3lf3wFmpBRe9AX2a0/T
eeTECEG6FFFflad5OPM+suMRyQwWymOIZes6xbJgP/Pk9bYdpoOcXT7zqR6TmFBQebC8hsWaMOXY
wIElbskGBAL4JVKqvIofcbRpcb6MFeMpj+whRHduE6IZshiOKUSs4zUL3nz5mP/I52JwBkJFNr/S
HYvO2vHiJQ4XspMxeFI+RldyvR32GcvdcTYUSM6SDgA1ELzgYtZ3UZ9y7BynU0svde+y2Gtj5pqR
m2IxNYbWbQEHce54EMlzYuRNrj4KVGTChK64JFehaGQzNbiK0GLLtIwW6dNUXN50rJG6gr+Lo2eq
gIeJlFUK8Zd03uHL3/KnZSgcMK0+Y5VP48dCK07142IHeOR2D3GpdoDO4ekCAjn1U9zTPASPgjAz
DWuSUlOfOOxhFR5BX6lgITp5Fu0KqLfDm0/Guk6MPJ3sGDnvF2PL16bXFVHFiZe0LKJ03XwPfzsi
YL/asr6nt5XONDt57r00qZRWjY+DL1hGN/HDCSGRA+v0/Blr9BDdgU4WoLnLkNWm1Pb59DCgQQAw
jWaxQLAnwCzrer8jEpjhZQv3t18SIgO/88Dj+0WvkeUUojys9/kh/ugVByAqE4ekTRc0qxM4n/XR
srBtJig48cD//YMrGipeeo2sQaAnisZ7rJ4ZJ1lZZCbromkp2QnIwtt0xyC/OKDYBhKq+pTgX7Mm
NnnncSKSFgQyfvotCmQcUKPVIrxtbTnLx4afa9eZGf08qQCafGx7MPy10buZCa5TrX0sa7ir8SEX
KvGp/vxjR6eQ642cGgJuBKUMJCltLln9hFz/1pgGf3d8wI52GFwu98ehEosa/LFP0Gr/D7vI3LZe
2LPDLPFpCPJPIt84+J5e2iwJm1mUMWRTC+TT28TeNEE0cx1OlQq0L/Tm5gqyycv9KeYleRsDeEY8
cWQHmErdcWrU9qoHVvlYQT8UdJrdksXw9CwA2CPF1n2eT4tPcHYiJUxDrva+UXR0BQwpL8EBflL1
ty608b2ByJ/YEpq4HowEzVhv5fApH4gKeM8dTanGaFKS6bzZXme1xanb2sn0mRyxhW1YXIv4cRcK
2CIRCTGl2Grr7LG3NyGj7nrsgTDyRgvZxlicu39D4Ju9+fBPx4l2WJo+6NRfWqneg5hYyiWpEwde
gHTQscqFJHVzOjfG0Gz6wZOacd8YoC1Uk8edYrou7YBe0lTXgAZ64VZixFLRILCt6y8lI2MjJRld
iQZJ8mAxCaWm69ccl+JxgHEk9fsZbFeIFixidrQXV+oatq5HohWL/g3GKYoYelTYI4pdYcT6m98q
UmgCnb8VBSb8uZgwwTBGMOJNpO3avukA2XspjEDPiPGFJsceZlLN7cs5RtLzaGKooYfAyjEDq1wi
PNcQY7MMh1SWvLlYNhY+FmSxnMrlS2F5DmvWECqnw5LLXigDjiBO2pyASFPqTRSF9MKjzdeu8Cy5
daIDToDp4S+cxOmJGLiebwXdnQNEIb2iQhKo+qI/3wZpIj83yj677CHC6YBGn8bvUTD8ZByhK/L4
7wCJTzaHfGQ1B6Icq+6R6GG+//Op9uf3lydXPCU8sYmGJd+De6I5OzepqHmn8W0SRg9VIjAo6Kor
6CLrMIeymNth1u6jgbIuDCLNerrFnGLrEl4VDGhOQ6Vg8hzCZxHJhwM2MK7iKDCTqJonvDLTa7+m
tBKCZA16rdVAVNibOyFPriRiCnFiEUd0B2l4wpL7MqMByZ/8n7sIXtbbf3DxS4jADLWebsjQPX7O
N7Ik0XyTEqwCJYJetYuFE7npdI6Atds570fsKM0WBuymIzik7KqvNbETJ+X6Q3xjPN/jmw7+xb7i
A9bEIYZttpEMdgfLRTT2U+VQosir7fONngKTZ0/2KN8b3pcHNHO2LN1nYSXKmMDH7a9ZA/jnsBB1
LQ8AXsy2tdGOtC9GiXq+L3Ia5akXesFYEK9+6kjMrImcmPrd/MX3jPpU84mRThIl1Gixtgv3NA+Y
lqFcF1OtBNKul9DGiOsB1vrzkbj3ZBLQvTN4s5150o5WRZ+r+vg0tLdElXK0RM/X7MecJ9C29wUZ
Qp4DFwxKKwxJA9+iqd1OFCNwKR7Q0DQOR89a0M5+2mL13GZGbYJ3XQpK5iiVTIm+4reY98Wj2gUX
XLWkraW0teF8LgGikp3u25S7/hZH3uJxaf0MyiyINl7cnJMPoSp7ySWNMvUKPfvVZlK2jg7bzBmq
uKLcw35MOQasEp/tiyieGt4QQmhXT53v1E0yZV7wYuHJDYsnHMC/fIl5Ob7OkH+jejJnBR9i8iRB
1Jy5zh6rJtwHqiAVmxzX69AqccS+IsMKYC97dRnGekgL3E6k7J4B+2ug+vhfH4MqSNJ/GnmexOGw
Zu0Vyiek+zNsHSSM8CPslA2ElesMHyhJCNvtg90MTG8ZJ3VfAjrojf4uVSQKUCG/W28a0MA89YaV
ErqfAOJcVApyehIheBVXtHxYVEAlxffP2nT9dcB2UdZa2bUFX+u8W8dxDtt17C4mrXDeUPJbAw+2
DXhVhuzuG1O2kWMNHLLXepLV4bmJgvCW0cfA7pcp1DD3BwtZnPLx0/CJlb81qkeCm6/G+zo3P5Bu
ifPpOtWygahIqrHrAUg/GKfv+ava4vorpedx42LabMdh3prkzLhWuSdbpfxHlHFv8ElczXSCNRYF
lHGgEvXIY1+yZMzXNc2TeHfqE8AWNLPuXt1gnMUyEm/h0yi1Eo5JYVReVim98C4lFYyowWrtLZ7B
bDXJGN4KO65EAb4sXt37p7JieTEobfMcOZoFS00oNycrYTxKMrujImrQwTrD072SGu/PAwajHhlL
HsymzW5TNRDvuJfVSHZn2Xd9WlI96l/DSJPZeiPL1VzQLwDIKywkGleSj9jdI/dZQ62Llqs20rdH
Q2OJulmVHCKNfNnuj6nv8FLYmFXP/caVqtiOwfc7KmJEhKiqGUL6Se8NOWm9sSbETvKZh0THNrci
sPUUBA5BHqzIBbrF8MlFdjifopR73QKUa9u/SZadvjmj31QVzd2qbVaPd7OEsDPDfBaoYiRFI6YV
24yymUdp/Dx/k8o7ZeIcrjlz0ZqAWOqTPl4nIRdPwGeDOGfATlthL4x6BnLrSd1UQ6rXZyQeqc9M
CKuNWotnGXA5sCLgGkg9tVLSB6Nk5iZ0RKfhDUaTRxJrKSd0ucRzcsN8OLd+yoe7ZH633/jtRMe3
8Ll9+yUILC0x8dnkVk0cyJ3rtrP6LiyYDpWS7c2q8ei4Kozkv8HOKmUXOi2TYC5b0i5Chh79t5Dw
JI5oeiDr63C9rE+sy+2vahvYovTZ5gqxgOfZ/EZDplXKuI8VnwUEaMjGst3cD/LKMnaQrbHI4jYA
fudp3bwY1s0q+rA4/jVBBvcDdq8OEwfRN22Q4kKNoMDkeIwuTjK18203OmQraavE8ohKyT3OH6dI
wHRg+3t6BZXJyGJcmPzplro7348LWnrQ88WFJay2CXxGl8diZHrHqnFNlTbOt+MK+YAJ8yH3mz3o
wm5eIdoPY8wdYJhKEdS/3s8u2lhF4qYbuC+QtE4ait7wZBX9gO1IDAC4YXiK5Lv+X4O792Uhhw2Z
OoRCGm6D7GU5sy/k6ienqzFyjf6MzX59a/emBxZ4iMoZ/Y6QIoawD01KxDd/OCF/Q7J7AXHloLGJ
nSTJLEd4RfpEUeAw6dtHlduxkk3Ivq5QP2gexxDSCGf2k6nYJ5DqvAjvloQBuwZiER/mbQ7c8PSa
hWePVltJs2RmLrBXm/a4aPxeoz/1E3NGp0KxfFqSEqoxR0lzoKyKnTpWa8hutfCsIn9Bnv/bIZnY
kh2voyOgTWWgUGSHMwgWwP7CnwHKwBmrLskj2qgS1StZCeTDuvifej/eV2H/br9SBlhIpOWRgphs
hL8pDQIbVXQfIjQY4pCG4wSFYyu9cPLWnKMWmOoFPCYrh+pK7+avSlDl7fyhYfvthcb6Dh31vQT4
blpTmsDRDL4sMQlPyFnsSJlYNWmfrCJC2Xwr1cZDBXLmyEXGBZfKe9H8FNSfsR0TsuapuWzOMSOV
+ARZBdEiqcL9FTly8rVCgfxooPtHytXsazfjxLQZ1dfKddk5vGNyVlxsxCQIabF7VtJDZqsYkqOd
vvlsnKpMwiiXQp63IkuL/VF+B0KRPVH0czoxtRtBCww+q3ML6jbM4VouFUMw2GQxFS/D1SYaXEjy
E/I3lZtzKx5QZgcpniXTlYedSLM5AkKjKpPsBsDDVrpj8lysCakcOApZcFnX9noAL5A1tMnhIfUc
f3tSUL168B+ySPHe65kX3AilnBShZFCTjEe5xpea+AoN/U6y5h1MlUzOM3PoSjgR1BBVko1XCKph
sxRsKSaCdN63VnP1hhRrTlQe+YhjmkAp1f7YAP80DcBuGo15yWX5k5cPFzI94UV4QVHAKqlg6jqR
uJUIV3dfgJJX1K+zU9WlIXWVAbMBwz1ZqgVjImUAi4Wa0VQqV53poTLIanA0/vJXsjhAltPj/5Yj
u1Ynx7AKtQuv07xBO65+FwEHmBCWLx21NN2JfW6Uf7ereoJXc0YD++IVQjDNfF47EYkjdVf+tn+w
6Ns0shMf/v5r92rHnJZHOys63oCvnjTOzdXjlZevl9HccfylFGtQeim7oC1JrEySwE17CrJgjI1C
lOwlDrgLJQTUeOSPbABDl51ZgZ/BWbvxkiU9DVGW5HhfxGkvggDkZzo9MAwlqgOyOalOIPk71Nrb
EqoDbGYKFFAgjIq/dqWsu4VPvNSgInHvCNX8UWnttyBdbAA92h6FRP6tPNDP7moxCG59CF5He+yp
KW3hif9F+/OgNswK7BoxVlKtqxPTDzkvycU1Z3zumowTThf4ULAKgdV4hb4el1ksdL5Z/6byAGZe
TnjutOyUr0FUfiqrZpyWCfnmx/veBX9EZyYErLWtnRPwzuBi8iXhA+O62SCWTV7jcfXaaEF3RgEA
8JZ9imcJ5ZlYEhcWShZ5HCTW1Vi9N2zy82YF+m+tYIbth6t9WYMgcwp6AdQzvv4IuUXbGulFA/w3
TNeiNauE/7+uax5XXOHGgb7O0vYZ1spTFE3Ocp7LgDuV2bXdNHlQ1QTPjZQAZlCvPtQy+6Bx5Va+
qkqUliV/bwb+cxQ3lr111s2CRFvKUAg4MZm4skFs6OAKjDbgqxzCSq8Iy1cJJTArVKUyGaE9AvDJ
B8QNtHxMgtzJz3Zf2A2omKV9ny57Nmd3/y/KpAUVpGuQNZBNHTE4XvfnGNWvdeamKD/piWy5n4YJ
NTgViOiDLEGyrhhnBI/Jwu89pRWVU8usDoip0HcVBhHrhbm6z6lEqK/HBAQycJQR0Wlb4tDhd3Ct
iHNzJ0UR2r436bNgMuE7l/ph2JA3V7TkK9CbpQCQ2qUZIVwOQ2GdpvcHpa8fW04/joRHBh8CZ3NA
pNIxEaGlrhRVB/I4SPQ9r1UlsNKk2ffbP0KEiOCiFCChgu+allJnCbG7HUqfcDRFG9D2EMmwDWAY
I4eCsRrbE5M7JeHZcj5MIBeQK2v2yi0jZVo/3t+E6Hxbo51SFKyuMrT7gagsoOvsG51l74m4XthA
/shMY53Z6tc9wPxqZAby4dbLyNwm78l/RCXFDxGGjtlYRBBx656xRWutfrAZ6TBDAW/1U/DBa46H
u7fPD9oXAPJ4zeZNvk1uP4yK+7ExkkUmT2pQxGgyBMQZsayFz0h27Uie6sF76b2OOwoX3SUxvmMD
iPPRGKDg/JKhtYQFoWFM5Ud7KZ7l7FKyHAPbh3Z7zhS7zr4P0KN/4GWJ9hJZbkVVch/vhZvkPXHq
1zq8/Dg8N1agCq03lO1WTuiOcDfMubhNlyb30gsZy8YQyQMUKyy1NOepAGleMBYTlR0amEHKT7pt
mNf2srZzEgbYtCPg2LmeJFM+Y/cMLSavN0iE7qSs8H31SF6XM+tMjc74pvy0L8ZIyYGYqMZR0lRs
GyjTbH+gZAzJKXxhfjQTg+1pOTUL9cqF6j8fRG0cGiXUL5MwuzVYqEwf6FnZoJQmyalkbcuZTMSM
D8gkJOSskV9cnmKVoKJcpqWpOLOWNruZz2+RZsQi+gg9Yo+xNEesppm9DvRfuh97G44Bc18kUvhk
ye9FHOFhPGkDt0HHgsgAudOJzjp7albn9Jwufw5jRof4siOS5lbbJHtHDuYb0aGkx1DZFEbvTydL
DtZTbLC6RKR+L6AAMvkA7nDUahciJu5JE+V3R3TBOJaI5Zf1uh+TaV7MMQ21e6n57R4Txj3XT7FG
N2G1ghh5kfhfW7/ZA4LoMqQ0+ZtgdD+hMZw5ENj4wiDu5t9jXakktlvPfyU3zC6F7Ec6pfJJsYON
E/QL317qxUlDLvxKZhM1dio6X1Db47lN7rND3w6jvGfr7R6oZKPKsymXrcGtHIyhkWBf0qLmAHnU
8mrcsiAg8i4cNCHO2e2nIKNyCuY4EPFnG6ehH7Xfp+yNrhWctRhLrfVm/tAlf+RANjxwkaufuTFX
fmOH/NsiCQhS8r/nrsIfnSyeaPTs9+UbvqkqS1VV2tIGerK7pa6ziEsG6IZ0mQlXAvx0VGsk+948
abAIDaLOezv6zkWnw53vjesfEMKoNWzWY+NVbcuLDMmSXG9x4ny5MvJLvi5ePkXr2pznNy9cZyTX
Zm7QNGJsVfOhlfegqkVFk6hdwbvLmE9Go6JTYGb4fXZ7Ac6YDu02v/KHvzNRKmDaEwsMh2ULfdOO
ZYYR4XAD5GQMZZSgcEq0Lqxka0DvaJJ+fZA27FixOT4lsLByaIWa6uSLHjR3SljgCXjWJ1hUNfnC
O1+NvJ/1ItoLSZHGBgElOZQ5oWmic9a5Om1SMP1BFJATLE99ISeRnB23PD93AE6ELkwBfgdIRAzv
rKz2eGvY/KQM+LUclQT6WTV/VQdedapcW2S9bxnyoBdfkQAMPNSiXWr4DFiiU1eLLcBDvBY3N4X/
iW4DYGDuxtz4GnxVAy+Z1ut3XUEk0wAFyZpPIcGZxIMQnb9F2TEI+0zAuM/4nLLiy6G+GxnMAFpA
i97UF+zSZKEuhW2R7x5Thnld3DBUCaf37BMqjDA6RmnksnHcUiKFdcHux5662AGmoslzvwNo37E9
NYzcL4weTn+JIKINGRKT1a4hDwNiAnc4Tb9JSksFOXpi64Oqu5QZb6xnQlZXHGl+04GuVasHkpis
zhxddbhw+gHNy+IlauOSbemc6R0R7ldqv91s3jH4O58up7+ZVrKx357mqXMUzTvZA4Jgu8cafCYG
8U2XoehZX5vAyc+YVdyZ2YU5aNbumFidXSHRpUIl8k+ofhjotDO6tpSZepuArgcnndAgHhPzEoV1
IFFT0TOVdX6OnZvJlJKBKEKew0vJGG6mGwZtmce4w99oFsSXg9ZIpw04I/eYl1FxwxGHzsd8Xpk/
EWLFrEk9RY/vKWo41IxVcH2MugD0qnSPATlUkR5IVXazd8u0GaQ7n9qaiLIxovP8hHEKGNEg+2PH
MocDOjxZ2u9v7DUUE4PdYWUVSY/TWKplkcF9BT9j83VUz1TO6z5t41c6IEOW2Ac5krH8ect/Eok+
vpB2c3OlOdyJTBBwgFw+svz/l8f7r50Xx14CfKhZIjELCif7BRrlFwwr/Y9IxHwpbg4MPZJW/QGo
bNVSH+g3GawV57fXqBZV0Sp4tNrKEnUnvif4S5AJzM4qpK8QdirKnzS1raTvx0N0vfGRAQ64bIaS
hL0nQ7lo7unW7gSOlPIn8c+67yxgGvz8W6YiPURUvlNW4jsfDwTQRiQzd/eoiOSnSVwfi2KbyGef
CXBNQkBg6Jft6WZGVMmft3bhyJdrybDGsyhq4d2pO091PXJDibQrlA+pjywKBMuQPBNj7jNwdSBT
Bzn8lWNo3GVnX67Sk5omdqcYGjKpe8af6j5V5+HaCkkBRY9dU4BaaE6SjOm5bX50z9bk+fy14vD2
DGGHHDHMj8kUZmh+7LJUfKdAHnvJdd9zEsIvBEM1xhVUR6mAdI4/JAUUA7ruTQyjMDgbWU1eIqNA
qJQRNM6KKsLvo9qVuaD/hD/x327PAeFiecLLaot9Jb8XWZ+BDj6f11M+U9qfA8Ayv3mXQBpKhNgS
qETazLlLE/+wiu7y3tb641PKGGhQWnfEfoC+mOqNfmYy+3cA5UuCpmUut1yruRMYZihpRCAODP0O
6OpU5tSM11a6Si835skciyR4RdLzRSvU/mIdIpxoPf1FtlDqMFxyShtOUisbDqRjZ3wLnKju6yXo
GN4c8oayW97DbDeMgg4oPPAnl0e8pi8I5ZauEBrJcQBHD7Cr1EF1fMg2YqC/bP1CTOsH2G8n2FOz
VePCvUARzPkQZ0KKg+HojWiOeiE8pee6+HZor0yvgMh3EPFv68a4GKVkoOo9F1Vjv/mNDNZLD5Af
ZYdQltgEmsSafWrhMKABZFPRP50GJ3Ww9Lc5/jaP3Uzfa8wV06cakfFOOtLzQvBwHUvNC9icnZbx
VotG1xTHIWFSlE6oWcXtIzzYcJasKhUhSP1CT6x2k7b3pbJvXI0RWzpPiTbTk5QK7CMLUd/AfmsX
LTTbWuW40pJkJukwyXRfzr7IVvyXJHDT36pZgU0LyIyduCuNpjDheU14ZGaiCSBquaT0rqqrCyOS
OHjBIVcy5DJR+m+WIQzrkAO5i+fbVePq35mFWkKYv8Zcg/PgXY1qdSeT4e/+XA4VdefSDq+A3aag
XbAYR2PG1ZMuXaBx1dgLkLdKCj3VAU5XMzA6XxrztuNZ7V523ZCkVFW40/RA20aLKdSJTv4Z94zO
1sR14Mtijc9cPqljEHpLLUmlGasmL0l/4nOJGYhoSEL1uVvprj1ddnhUucOjQjz1LXEZgRWJjNcI
6mpS/15PsyEpWdrU2vmfM9TMbSk0Jdq978kLuqjj6ITenE/PqdgvF4YKeCVmuyMpOvJOgsSFztPm
BAfl0UYiqYNrBb2TS8XHIcCyBXMcv0RaM2K7QWeaiiLv+IuJMVee9RSJbgOr4OR2sx7cqCKaNA2j
g1VL78fiWftPtjW91z2lYFj+k66UIZR75HXrFgRbucHfCspTta63aLC6wf2FZzcLvjWyq/6q1Ixq
mKfjLACRHDfINNitJhn4/LV0tHlGThtI1kajnOEfM4izIXPs+2ZWuH+zbHfzvSfwzuSkuWTP/RP8
HJBKgT5XVY1ihVIz7Rbh8vbbsBaKgkp8iZYLB+8HwSfuS5b36hTLM4XgHXytsvOerYAA7rMa/seH
5qYVuqCFCRhgmzihxl/R3bTXcoQH+lagm4g35Udycv2aqZpvGXN0L7PbWaAa13w+SdkMEszi97pE
j4gnzg2bBi9jQnbQb36Ntaf/c3I3vq5oYcC0hsJtPrmf4kqbaIQmYV99Q1c2/KQPqNl/XgrJISCo
qXm56dQGz+YRj6BP8GHKjfQgixp0CWDa4YC6PwvybDMN6LLM0hzfaIV2pb5Yj3H0vODrfQTIn6k/
BT1r7hWVsgk5B3ZMDuJssDcIUk6M36GEFA30VefrN9MoxoMG93e/tI1+Pw5TbYwuCf7X8HQzYygB
cCXfxM+ChcP86Ei8IASWpqRCMuHGxso2w5Xfwa7Ut14uMH54yHZvPEFESad8gGGG0oVk4wODQ5Ci
tOHfhpHozA7KN2j04OLewy4QSfg/+W3NmEtxw+elNyjtHeiZXV2NIsCB3zvuztzesOJcpWkbAGQr
wYVzphTQmERV8s8eTemI1OZa0I7zeWTiWkY7b3g4pdKkRTYUNtEJK3hud1paFwPcLA99hYT+C4Lf
9YZG189vXr/eNJ/oOpQDXhKxVF9rk7kNLuCMJNQiIjlN2XC72lclQLSSYjrAkCmPgJzOVe/QJAaN
tQ+PBlFNSVRYY/COF7E025PMv4MAD3KPi2BKoB8S3fh54+CvnbOhl+mRNfwAOChr4dvO+jjM3FXc
RHZPmXTsfJQvHsCqwqculvvD64LL1ZZMrxCa69TeYcPuwzFxsrVQ0Hcc2Qnv+Ak9V+lFBZVnmxfo
jHytiqzZ/1BPt3XIWSjJpropd4yrbDlGaIcmmFzaSrSoZHLXS8Ct2rxqUAQMx9Ia5u09Fq4coSF9
IJZkltRcKVnA1lw8SJhZGAtJCrcATvc0YzaKKiunuBJb9z55QBolwRZDdLu+KVyj3vZfu830cByo
hhdVLk6DhxoucYI6T9e5nK0Lu7rMfB9vaWN3xdsKWcYJ4FVbqImpbQ1fZlHrtJa28aUaIsWlQrug
0Jgvk9y6G8h8/KiejFGa81B3QkOyzVR26Mc45znTCZQXBJjLcYznPtBcGtxGSsIpI7iR33Azr9Et
fQkX1PmlaRRc+YY78rAZ0zXIxiKIpeggH1uWMDi6mmgLZ5GUxjgvKuBn+VcmAWix40wEJzROi6qs
Pkoxj/OPTqBSVBs4oCLWWLD7X5aZmgA/naJ5uF5J1Y6wUbuoed9AWoEoAWmnBA3h3AW0ZT8zF78T
IJmcX7cHmiTOOq/99ZcpKWsVSB8RmG6gNNkYPpqFvhUMmS2wvH5lDTEE2rvBA8X3m6wxVicEFSx7
Mhudo6JQOP5Jyv3EckQgnBBX1q1Z7wsdBk2Z8O0BBL+eLiWqY5IijEQmB2elcW2VysS8e0/g3KeX
WzHByFjFgRxZ60QkkjjvZGirF94b7MCf5ciXvO8zCkIyfbdkE6ztTey7ZZ5hu3ujoM1JBdlrnPG5
pvOGYkvT3FZtOJTL6Yo9GUBwSaD+gj8QLLLlK8lr8KMfpM8dihE1Afbr3Aso24KvFOLSwTJ2fnjZ
exjHRcpVCFBEsO5frinulfCnFplbfj2atF/iQQjjd+TmRzh7tiux1cD+y2I1hGUduwd5HSux3b2X
A0iApW32QjBJct8vA89P+l4npsIZPI9y0syLgL8gcd+NVrLxXAvcZtc2GutaOGtASaZFY7Vez8qG
EVrccvhy5T1EQW7NcmRAN/Wuliaf65lGffg7p/CMzrGnc4J1UO31vKvFDGmPiQTtljcMt+wO9MOo
bKC1/Lgezn6h4uP8PKlLtXF6nhb12kS1dn5CACrJwbn5Om+dbwO8W0awasvaep9u1MFiQ7WEp76A
eaqgJnThnq2ViF/OgEtWl8/3cAYDkaMxE6PzfzLF+IoLN1JDhC2JJQMUROHqI3RTZR9rweciJAVq
erA7rM8tnjo4ETq8CfVdRTTE2HViXS2HRCZ4QLf2iEbViLCPaAejESvOOGQfBz0bTEyJInvyqmzL
QI76NrDnjLln9vqQ/3LyAtI34LfnvGq7beuuNiVHQ9xPN1N102GmlaOqd0OqSI7UYYp5UBj+wFGp
bX1pIoeR8lJzO8c9YMwYLNBHAmZZqVCDn0gy30ff6sfkKDPH0COW7Bhv8BfdhAm0AnG63i7iB0+8
4PzOEMkApEQrKiqx3q0ypIi7d0rgUQ0Wl80DFxbhEbTCZuaVcpfjWZ5/j2oAYBLBaYgZg1s+zxGW
oS7h5gk7oxwY6piS2gpaOtY7n30iA5DOMBn7j3oNv/us2yom8nmCAncKKFOH6BC6FPHFUpbJ2N/T
dsT62CLXmvBbOE1IIHE4hNZZL+VCFqLtkQgAyaMZ/rgyO+bTVWr6ZOC7PcOCWshGjAxduUTsOTCz
ozURvHfe/54vXiLzVob3NMDWtEnLwVvGJU736cZmPuOYvLMyLoxu17nypD2lRfQeUk02MDS2e3J+
8U5P8b4StDjhXViLpPjROwGpjSnX8DtOhl78uG7NyawejbEl0xU2R/qHmX9TGZJEwMC7IcuBIkmN
VJjQBFEWGJXW6wSDynmvDH4GZVB4wrkrJs3sONWquDuC2Ty0ZtxmsPfVBvBnFbpAaT2dJ8N83HeJ
Yu6OWfgxWpbpTPmri5nuXV8m0iGNrCbmJWGQjnKw2zWBV+YmdaFCDDBpNsKvwo2zQuW51K14QKS/
VUBr4rUH8welQ1ysJkjQMbmX25IMxTLwvmLYhOufcQBPIywQKpIseCbR9YUVC+kT1gKFouy4oWkz
0JFCqmkm9/cO/8D5pGiEngda92nGM/sVm94GI1t+DFNaxq0vS/3hT0Ntd7yKd8VpLGhhoX08DZvO
MF2B8U3WhlCtXr4kBIYSreT/btxFFZEs0f68Bf4bKJj1orsTZ7LNdI009YzJrKL51oU9eWSwyuJG
nFgcZLes9Nl2V6+p7vHIbmV4vxuuWiOld4m7RUo1200b++X2U0ZOI0QXK8mCmFiSffAIWGnRuDHU
9fVW2uJoSP4jmoWNdCZ+LK127JXQWoK+IICPaZ8vi5XupX7/PSTvaxl5Dw/mx/dIWPkMnM38Cqsu
CC0jOiSawEdCdlmCOdiK7a2xVtsbFp4uNu63qgC+o7NAQ5/KUF0DIKtTuCJJYDk2i/X3LcofgM8Z
OhK7F+E/F7mdSMHcM03e8DHOj8JuJQFq+ykWM7GmR1iGUxX/DayIyPi7TeTOc2JyFxZUhaQLwkzP
iZ0TkgghM7H/DA49lZ/4x1aMWNetzaUMQ3X6exap5W9HX+nqgL7O1OSGIKiDxZ18KnF8EOZCgjob
CxjCKCd4O26Z+cIxoERyjzjMzC6C3WGm7di5AhyYcQUsoZwDG2wuCYOFm5/CNqprcpGV5RWPa5t/
RHOLkJJhmqpG6Uue2AQsxN9/gJD79FQmkYXWmGzr8nagb5z8K/7534BzjK+IngCqb1TH67y/WiF8
gnCoY2KuRAZuSrWoLxRGW6aMrsi3Eash+1+9WC94pUUJxACL+LAW+8gb2ik1IK07+DZTCYbXByXt
veAz96w2l5nAkJeo16GxOY8Fuxrm1xWmam/UJXGq5oS7VJWvmqn03vM3aU+n2TSucdgepNIYBbfb
F7mV61QoVcEK11wLVrWawpdRuo4hF2MGxVtEkVHJ4andZM15qmn//ymGeJg7ZzgsZDHUGEA8xHeM
W9qV1ZSz8zgSyQ9sIRnADKer84rhDz3bNJ9t2oQd2q7U9RZ0haPUTL5OKpHYD/bWR3wnar1WPaeF
Ro5PPfevTv6zXG9/3JKSVYW7dIBOVoZOT6xTjBoDmOlR6BjYqpADfPGcT3mD8UbyIhV8WOjctcBw
mFwRDqQpGCq287B1/CkRZm+9FST+Ua3hC6z7etHdOPKx257RHfKGZYCkCisaZfSZFFA1i5UbHiuR
sVnvoKJFNGLU+1jPzTeZHoPYseEsvRiQi6EuJMGHgWwlM95IH2yjAMlqooG8HFKluIUHgZdwt7Zd
Av+Az67la4HpU/D1NQZuDY9TfIMmD7L8xJXPbIjCAxmSjayre/2qU+q0EkB0uvBFPpt93b6fR4Ne
8cAlP/N5RU3JvX6VvWS66AD/kD51DkCskNxxiJ8xktIRbgrAtr5OazZz8mJN3dleBoDyNjizE+9b
QDt3BA9oDOLKp/2Mmn+pzhmLWfPDGuk3mBzm5kUanHlQwyYKLoQe2bBJAx46FF4gdmX9gRzwW6Yt
aH8+mDUhIv7DoohghzH4UsboHtnLD0XP/eOShxMVddZrfcplyKCBo07wj9oo8aeUVbKR96jNCh7W
4daHEgSgXO1n459IU28fPYCcVenEsEd5kd69gxD0k4L/fR5e6k38Zk1oPrrRl5pXop/NgPhaFTXQ
P7xpiS2G1ZEfxBYROgSLn5lH3DPapMkyQB+WpWwwzaItSNgPLVi35UhEkMzz59jR4GguNfTvSRr/
LZL2ikHRxhZ4n2Z+op8NZLmMd37+zuc7DNy0D7sc14EdOfFofWu574KXLbbkGGNVHWFFJrvcM+dS
e0D7zwSh44Es8cQPdwge+W/Qt4qnLs2Foox9j4AGMS0br03LWpNrE/eXjVjDnXmYHh4AR+okBanr
/YFflGLP9mBs5NKFdUmtYDsnzGSLMauZivKUw92408hf1PIoReRtgSOLgoAaaPBI3kZICyUMQNt6
fMNnoMUTmrrOMVibgWlbWyJFf3m2g7U07gkRO5ta7R7mKvWcDfMzQ04M9kvnNmWt647ZOeIvMoMD
AYs3VQjnALCb98Um5mPB/c5kIWDVifmfkQ3OAtgPgSINz8XtVjtN//N/u+iX0PNwmeHel+ialNUD
yybp6BuqwTYTWa8ba5JMeI76YhTSaFa0TypWRNI2aqhrrH5r5Pq6jR/2yYzXm17J6KIA+tRotnvX
TpcMBPMwmrUQHeQ5bUOOTVGdkotQG9Le/snBwgPMqk05fTjVQ5ITLBLAZhgEq9zZekQlw7kVIg1M
8IcZdt0kHet+hu3VCvQ2bBLw5ysLxAZxRRwM3U84GAarm9qkwwaBWGDGnrJujNejR01Ir5DMY+lF
vp8fqEYL9SzLaXYXWquzAU7vMk/CUd78Ls9UNV5fNgH2oMoEaNXiptUTqbafYEzpjAzuE8JsuT+r
vvm23akWwE8ZR8uTFxwaoycPfDpQXMrFDbSb/oRp1kSWNTEZVWy77+GhQNbBaToFEoDwapyD/es3
b18MurqhNUxbfdGaJX4iZ+r3pCGTDmu9aAfdOLDpXG0+h5xyDwL8sOP94q509dI5HMj+c65v6S1H
8ylwyTWcjyEwFMrlaY9ReR1MBm0CuByFNJ/2kXULNqXo2gWJTD5dZxQyVxqoK9u8v3NmxWgTlkwX
oWs3u98FJG6589Bny28kGNbxBOWXCry/PHHcbVZH/AGfr2XozyxwfGHmSA8jTOSRsUe4uctZEZo8
gINOnC5eHi92WJKVU+RAaG5QE3SY15Eufd/oWhTk+5bUwUcAViTeVwCpAInP5+VXk7Y0rYV6SAnA
UTT/1ntmMZ0k8CwG26Fra69c/BXk3zi+HCQcFYtqTBdOjfPoINkgOnQqskmPlMBX3apBeDYjoWKQ
zMwhUqSVgofBjSSjdDgkG1YDSOeMwL393Rhdmf2FURlMJME0YSU2DxURo2hy2T+InUqtG9qhhv1C
a0HP/4W5+qijudcEHBL+VrSIrE1BzYmNfnv0BY9Idcl5tldmY4JINq/yUpaOXAXHAwfddDHL7aX0
xjP07TmH2qlIV5n9HK2t1LW7bnbr1uWzxkK/B74Pv1irLZabqw+kLlukLSDt0dqmd9If/wI/2OZF
otVGF3FKHsjF3gf4ho/sm4qQtWymEq9f9ZhmTDTaJh6drsDBCyl+JFOgcbcI/CYxsknVFVfBB4EF
NfJTXFleRHmnniLQeuUJdcnFdKL57ZMs3G/VUiUUB/r8hPlomdAnM2j6+5FJuJkWn+GU8nnyWdc/
XeVBOBwa8Ep+87isCf0UbHEBWd72wd61tFBbrC9W0mEFgNpp7oarup1We9fqHDdlpuF5ypGRhP4v
X9mzKBsQ6fyIDc+BRpDNCAktFQfQmQWUeSGjsuAaEZpQqZaiUnUnBXpbdrweKlHGsLi8l5SwlGQ+
/mZyjMAXPUBvcgp6dqgJUrMPn3781QEWYZYUusdq6P7KTi3yc0OhY9m785yemV8QCQk8Er4uulQF
PXGS9O3aLurnLw0O8YUKEfSmL/bOwPLMgg2JEhLafhLrcV2B5lLQ9gOe6zqDRBhcKzJYGJMplhTw
Sr64C0/Wvg8UTQUbh9mxykPjlLidzp05Wtpa9CLqA4oG+p0P/5IrClsr4hkl77+3HpSu6SC6/wIo
EtBCJU7a73hE+eO/lfmW94DpYR+6YDtk92h3AEqzpKB2bXs6SPeDAmWCzLYaKUM4AYwB23a1QlwA
XaX1CLHqEeak6i7DxxSscvMNudm1fqLMHuN1QrSHHdTMtpMtEHP28ZNZQZXyZGMUvUiKLr4Cw6cf
9zZPoTxA4gCIBLVHhG2jxEntaD19iEXg785+9oNGo/ksJbRGdLuruha0MfZ5pUESaTJckrkuxmwS
trU4IuPyl25PqJK1PiIlcwEkSEPYhytVuqfPsBh6oGS/PveWB/uB90Bcd+wupqn18rmKMLWTQZlN
PYKsqqLphbq/i8vDXLtMzlALSZ762jCaMcYlRpUKPTgJtjlU3RABJr6FkueK7M0cKl2GpRjQ0caU
xqOdPKxjWc4htoKzRp7bzA3XJiPI9JVkqbyoIy4PYBoUvOsg3QwXu0VHG0sU8jDEL7y9WC3OdooZ
Yj7/EoVZbPG4nZotaioisiXtu1ZeHFabFxied72yc0Q/fZX6ZXPgrCQy6hovsWbFkKpSZGiQ6UeH
fJJ7rGH/Spejop6yfzfcv1iyVOBNvc8rlc00Se0nBHkwughW6F0GEdKkRKVstqK8mfXYzvjOwE/e
AUi7tZAKt2/Pk0gmVPsCx6HtpnWFEH6o6muQK5ny3nvfCv/SNfr3/Fh1XazD9ddRaplPP7WbmgAP
U2w+3UcLtsiSAqt2Tj5qP+DTPVyl6pmouiaZiw8+KVJmoCAX88bvfFg2wAiWq4c3mg1lHLXyLPq5
01hHRy7VEkzKahlYIoEjJBlx4G9FO1ZOcC364d3wwhBBQKrai3azH9wPYHzzKNYq8SwIRlkQvFki
vNdeskdulUYutWKPtkJGeaRBSxgg/NqxiPud3AjQ3jbFbbcvjIfN1AOY9RMW3lEPiZXRYvtHrtji
Oq8x1e+2zqVYEXEWqE3gFsQCiMqyEwcP0/FkXeHwSE0D5UDM4YtbdFEsqQVJyqIlC5SO3uNV/yWy
QY1EWmeahmoiZmScC2KmtYzizHb/TA3OC+QR9pKVwAL6XO1UxTCtVe5sI+WDYYsNuZwwaUgzOoVR
HYivpKMr6mG+KKk78miin4TqlURofOVOgO/7kFw56DZNamUHYMzPbKTcR6mqqn/ZxA9HQICRmhC0
BgjYGKRlNqWRk7fEPxLFSc3Yg/zFN1xFQNHsqom+ffziWdrcJAQlH4nbDsCQ3+DIYy18UJwoKnaa
fUOQhWZc+aa77qLE1qGyT2HeV7KCKc7HJ6PgvfbU+Zy7wKsJHCCSyS208v5F+RLdHVfxjYbyZF+X
y5OKFjx3Pr5PP1MgAmqleFO6wwmAEgMKUPsE9+2qzMxzQj4m3rPQGCmvjwt/xHkaJAP1fk5gOQ54
MrhKDLErPRcP1LjpSiC/x45ezvyVRDG31ldts7LK03ue6RtF2TT+mIgCLCIhN8i1MMNSAcfEdnkt
gxymxLNS6fvJkyslOACdbbo0ficlYhEYIzRSkE/K0U+5TlzX5xFNEwtjmvcu0Mri8i95nnEsvr8c
D8mTwNru78Rxe7xpPBVAcKQtPKCqNQBJamIsDHlTc3GBYNLGiIqPOq9d54ZdChJLEY4yQU32z1ou
C+l7kU/rsgQFg0z5ArCwFPlKjcGCcrLjjGqQOTcnyZsKnNIrw6HAwjuOwCgzCtjb72A3t5Zhsctf
oHXUOfygAHs4+GzJSn41ZyebNeWjo4QpnNhygX3o/KpGfV++R/ViZW3dTlU5I8/N6nGUtfoLJTxD
6/z82J1qIxmWP7+ExRC6NIeK4fxt9vEBxUmWp06hxcv6f7hB7/FsyoA/y/k6pPLdpmU7GMikW1A6
cTrs0/tf49IIokIM2GlNHWVFgp15dj6aV2R1IK41rSG942wJY6N1Pbgj9dsNzdtasXLIoq4W/LJC
sJgyUjlPwvjHUIxKQgZo/ubDA/Vu70vkphvxkb05spyYmns3UmcnbslfdH+9kWMwQD8jgKRJ65o7
YzWg1/6UPHzUxeqNOCg+w9FRp4LBM+krp+ni0H06/cBFP/PcC51UF1CKj28qiIfQw/c1oOb3Rlk0
HoobCmlXUjqXlCJ6aGrOj6Pb7pCL7bYnSv893RQ93SH7V+mQclJAkNfikzQ0uY2SsnI65vD9KMKT
yqqqcu2Gtn4BvbZiHMq+jITEKuGoWfKj+ZWNvOKoL6Xu3yvQF69bELzNG1Ze3SU5VyXabaC0/gXS
HzyTIZ0gshhVhvho2xzBBEpU6WdTQFrWbxEMVUNDs1oYMk3aBHUEv+gpi/ExEV3uBiabl8y0rAQA
TphG7OIw1cbdFe6Dcbl8OBU7mvH0oIO6zevseg7rkb8lH8kF+gIVOW1VzSTybXPZ3pQq7sjca0ZL
DaXFJaJ5KvGSTPML7GddW76GAustVU5VWtLGMQhOdbQ+9qEEUdynCsFcAW/bEr+tvSD7K2IAZUn2
cahKM23/zxANFaLvh361v2iUAfLODrX7kUH+O5z/ePyUv0VBZFdKqYuzK9x+aV8EgbsrWEJsyJvL
PoL74UGiXsJB0SoQzfxlG+NwO7jJ52EH/EqB7YtP/gVMcfl7+EcoMjm1ZCPFxuDNDu0XZ2OrFFBs
rMDaNgqrFpkWNacSlXN4weQh4+VtlyujR/onAtHbBiYvw0nI4Dxb14jEWKPqKLMmbsmI0LxNBXQq
PN74FoCD/fpc6Qb+hWKQzgA6ieYyIhExWR7T8A8lJEw2BlLPR08KaeXuYx5AdQ97CbdPE3lFgGDa
Ax4zG090TOtw4Sjq3/8Ji5fRMWxwM2hCQfQwzcHBVTcbqm76VehUvQZfBCuC4vINZjK+kSoae1kp
N5XOgsX6eE/ZmqAKPr4BbdBtO18kInVNglHPXQxE6HinZYjeWL/ZrIJSE3JW4asqUzOfMChEJn2d
z31EwdMzLig5LrYk/F1CIdXNDnXw6POpplZ8kroW5RREd3iKskKO7ixkOJc1CnAUHVkFr1Uhgltr
jznOZ3DMy/yk/v6Ueet5JKomLT8JoiKWqd6mWlHOQO40d1DogVlrOqPDASEATNx9oG7I4TAZR3yI
70FZwRAaJAk8x94bbQfS8IYOBs7hZYLW14QgQm0J/qi7lGdAF4PHUixmDYygNbGlyERNywASPRk8
fRzISFuXiJ2HfaLsd6omK0XfTP+9ARyi4L2o1UGsU/QltndW3rK/n8Hlo8JYKLgmIsbCqsR6cz/z
K11YSAzmieVb5q8ZtEv2jAAoIuNEesMnOxLeDqtG60TNGyoePTN17HzZKhpjeKCq9jNOFr30gELC
4eIibQ+PbklDKtRWwTtYwWgLx2dSuPmtAOYRsdwTva8mwRCtpDW/Y+zhkS9fNxhzmg6QpUZfUlzl
GTmy0xy6YrQ1Rzd4QnQnYuIRolCNGN/PytoYizpyJx4quO+MOTLdn3ubcW6taNoFZp64rXIGkY6S
mDAcK1ckAEbWfR1TXRcw72m9XiKRIPxhpqcqXCyg2UmEfX6nebTaD0TM3A+OcNh6akvVPwavvggy
6xFjdnBU6GOjyWY6T2YQnnt8KRQcu9YozhVvbzEZGY+7b2DYz56OIUxAnVXJ43ZOsV/d19+fzctc
NuShvvzSW02uK0i9m3d4lUy+Oe5zf/54Qsfe6WAOvKA/jHGF26AIf7t8y2lpAJ5r600zyPCNbHhm
wjJKVfK2D24witxt5VXJZ7CGBTGXLoVbvEcp6KI6/zeUDEtDXca4jouu4ZyELHCWrmJUziWzcD60
NE9Oj3DbSPKBEaGUBlFdSeHXdanE3BHZABk0R0MeDWHaQf2DNGRzsDZW5qD1zymPICLaTlurW69R
+FevGLaZfCMhc2DFJ0lJIPegZ7Qj1WKl8k1hVjy9YZLL16O0uZ7B08JuJ0HYbPKAC1iC98Eo2Ign
j8EIhBDTbxvmPPI380hwqzYox2KGUQ5dFUXGVUQ+f+RkYmyBbspZc93ttvOz1WE8UGhyCH0mdMuy
vqEQltNiyf9U52utD+qICOnQ5FyY2fQT6+oeAIG7QHfDUpChPmJS7dCMbd3jt2qssx1SEw4nnEKa
1xmTxWPmJ4ws7xJ5lU9bFKmY9egD2ah13kQtGNBIxOOXCFnaqUJPEzVA3EtphekVO5euDHOxf1LB
SsWAm1gqdC6yUEjg9/QQyx8jgd+krfZUhpZ6g/HJG0JxQO6RGf58n7nKsUM5HVJg7W8bk1K702Z2
yUYbyjANqHPovEormnSs5OE0sMgd27/Lzhfl821TkGycBstxWLr8CyBzF6fWwyiic9+wMwNWl/Gc
U6aKaVZlYV711hzl0QGcG91DINR4jPC9LTBACTPX1zjUN1eGUjK/YX2AQpqOHyFXyXDRKCy2fqO4
3eLfI9SJ6FfRJ3X16PChroW14LvibNbz3jdsEUjjGfRR+xxit/lELSKMjtIcZt28cHF+dIo4YSFY
YpsP+FxDj22qsLXXDkpFChtkUYPNWxJJFCUF7SC6PrDLjGmadY99casjvATDwaaYpcZcCuWS/xgk
ZFdsL31eZbw/JqcDXxxv7pyRF1pht85sUN6nHZC8kJznl1TnbYD1zuKDJU59ONzugLMPDvAYmf+Q
ADJh747NNI6wto5Y9IoaFgrggL/tOCi9Q/C4dMAUdUvSUdBi3BbHkuevwCpBAqCurAErEyxVcNqV
i7QriOovGobr+XIKyLWbh4pvAUby6p3M09CySTPRL741JubajROgytQdhn4yvux13g2T1n2rHcp2
vHkqMr94LMVsYtuZHztldBcZjSZdV8UZoulA5ZqoSrNp/Zeo9B32Ge6DFMuSkkX3ELCmv255ip4l
pkJUhRk29UyOuvwCZYjR00cJQYJFj/MTRchyIAtuYCy01Zhho5EGVWDYYZHJmp6M1KXGVGIJEuLf
/FUgnGjMHHYS6ySgF3YLXBzLSIaK8DP5HeZqXvunSnPHDaa4SIuGC6RfvgVldEAXyjfXmgs05WeS
rkkmu2BS7BHQR6xlqrJHWgrOzUhNpNwjt9tjlZObLR/88F2YU7qtOMS116A8zLEkZ1hcSjM2+H9S
tyvfp+2aYFquw6lr5ig4gVIvg5ivU5vtbhp6xr8jtRf0wi28ERcEbN4aJlx72JfKeCi2wlqw3Az0
0kdDgM/GuS8Ih1nKt/FrQQO2kncttULzJG//b7zbFuB5abpXiC4Ll+1I4qjFFieoVO4vcMw53AdI
f8EZSlIijaIrEI1reQOTPPgtkhBAgQOtrLPD1ftRFTW3zKL7taJOVTNikrcjHY7DpBiPpvC6GQl+
UnRU+eRCzJYF4sR5rR/M4bXH+9BkoeL0PCUuIfOa/cfb8DLH6qddEnyw7Yd0feZOsQltQcfkkOsS
klfP3R39MHJIvXZmdYdmp15gti6DQfcUeGtDl/m86/kFIwnDWmqdJFjSSTQ28xCFAQM2YCyoA5Qj
8jjz+sSaESPH8ok94Q0a128G5017AAH9+XDzRHJpNC2yeda7pGnV22uPE5ELNXs8GR79pQSG2DJZ
RKtFavQU6BJkyfB+g3Cwv0di1yoVrdnB9ywjp7kkizw+LxGUzrXitmvqxmfB5JaWiQnK6pTQNiTa
kgnnUjIz5NkVCykPlGrHTZCfL10fWbH+rZAPzk6qsKK4ttF7cCmhhM9N9+rVNKGBfUP1YoLRmCSx
O/rvZvD+doJNbufeebe1IDmj3VsJ660othwvcONisbyGDkPW7gHYB1+B4hk3glz/0T77Eygev+U2
e39oa1FsQwL/jmfKZPWK+HvgEVi+L7bn90fY+HCy7q4CtE9VN6FsZv8ufrSXtd2dkPqj1gvoab9C
b4RdpOJpvETa+HZY3g8+i0XjfGaCfKn1beFyHSPlU7RFqre8ul19HMu/tCuxekJlDlcF0emj/HGr
O/yvpvEpq1nBLgO1sxLMs/rzkhj5eArwSpIlr0I1h4Tpu7xP+oAoI9IQPu4ZUPEYCE+iSDaIX+VQ
RsQlkRtcacQ27he/cG7Dog7A8hlyI9t2vKuzn5/0Mq+Y1nboEVDt5XOp7fjLHa/JlCiYF2/fbQCR
m8vGcskVl/EJIS6rrl12yyYU9rs0VjHHMdBaZ0ioAmsOKnGvs/fyVYQLSCgIgVR5Np8utGTQ719R
WYc2S5BKwcx8eUc9zXgHye7+8kDPNpCy0kb2ltZd1D9eXSo5H/BBGYHG41T4/1zFVTH88D+ANkUi
aSvKcox9pir6QPEeXIV4YtgMKuT0K7l+ckNUWGszp/uPl68tHD+bsgsb1fGz3eYNaoy22OOM0QfJ
uvk/t+wsaIUV3xLWwDyZIl4dl7E3oxYwWi57p/jhwh3v8jQriYF1IOCn2HrPIV7wg3YkpXCqMKfj
TyHqne15km71wxRdwYjFoQg2XDHfjSfCoLmgyPxiD2Jmb/OTDpxnQL6pUgONx83y74rpdPZ+COpv
tsX/IVZWzcaK8lv3v+KIteTjPsvN5fTtEaXK6OcgmLpLM5MqChJzpwrKj+2K5M676dsSIxb0kJeQ
t3Vjk8dEVXOq4DvJcHSDsX8xW2/tkErCk5uYM/q7tnoXGWme9a1lRPc1aJr6maSn1FCIlzUwb5Ss
TOLGQ/MUFzVC+W2lHPfa59r7pgg1tbzt1Nj1/KeIT2c322bqvYqKoEUafI9VrFvP7u1Z1TMshrfI
VldUqUj72OUV3XIjoM4wGuIQuFylyWZtqbqG4LVVnWbvf4LZm8l22djK8LlXZLJktsU04c24x+/P
EEsIHEXYy4DltAJRjlknWSh1Cbtm/SS7vHD/yj+nNC9vKog1jvLC6IxfvY1tnY32stVisHQClspa
0VgkT6SKXJ552kTz9bbi1fWCR4RdM/LgztqdAh3O7vapJDVXeFRXlpHE5Fj2PZxNRUQzNqVGlN/U
r7kIfksO/CAkVD5pwGNlLflHWbcqvrlpOiwSMtGrTiiAgf9bqHCVo24usBU0dyDvkz4XlsE4i0tq
AxPRlEnLQTBA7f4P6tDn0IhNFNivhTuYnWrTcocUqgVypp9OAG6mXqV/YksQp+Gl/3SPbctffVop
ozyymZlLhAyr+aIqVILW7rLnSqDpRnNQ3KiaJ45TtXr9qCxs/anSf1StttWTj2PxzUPbjQEq7Ooe
7SLWATnBLZtZKFILe7PdHTwNgev9dIEOnbFe+UUjI8TABo1B0xxXIpixGrdVnfZY37LQyCsUMPbI
fNYVHt69LXWErRPoR8qgcKBo3R7mAj7v1h+clTVd/qJQjXhM60k9Y7YegpJdIdd5k+2RxDu9+KMd
5aXpqWGE4N1IepUGVM6/ioDA0OHDpBAdQ9iSvh6Q7vZpO9DkOOiQDz6a0/rP8HaTYxz3YcilSjjY
pAx4QUsiuHRUi0KogLZOTeOP+gNh7fQA10Jdb7VvJ6Amx8CQltJQOb4CYzYJkWAt8qfaplhhjID1
SzxeD2AX8bt6Av0su9vr2h7qzBnDKmRTvYqp5eWkbaQD31hCjDotLR7KvFEuRdW51sEJ0FfpxTpj
yqaapc5TdazzAxXIg0zXI77J3ieX01S82SwxWkQKFsDdXk6ORNAzTE1AIrA13XHa9Yow9V3zsyLM
IRQKd62lNmYXtCFC81CNjxpSpeFcBGV3pZgSON3aZTairMk3W6FFrN96q2D2Rl6cZJfsDR5E+rua
K+V0BiClEPj9xRo3WYC/8NApK92I1HmUdzrQXQpndtj+ng2A+w0dvhFNyWBMBXsM6FUMZZIlpy8g
EBiVxnaRF7s9zeVV0pnOgMNxdKRG09Fa2OdnZRn51vymoDfPtiZOG+JnaEunlfQn2HfWs8GIWy3l
9gpDRS+OLLAB+T+bmQ8W64EuaGyV4+dS+i/Jz9yS3TVJUGLOxoXOKc3zdpQe4ZyvLfuAjE7pKpdo
AMNVsbtcB8kJvMuueGyANfPXjMn7lYFx4w/g3icpYZUWu+Y95NIeiWuaIDJAxRvQdeqYQ6h0Y84n
9y472OFg7MVP3X5CfKc0rpW59Anu/swefkPBD93oeEXTKda5iT2uPYR9hCf7V2X2tH7VS6fYigZg
N7SS/vY80VS1QoLTLSYkqRKr/Ro+vxcsqPNY90807Fp5pGo/gyzKi2ukwMiwDaoU4+hs37U0wBT3
2qEOXJOVjRDqFTCvJhTI/TR619y+bcIX+Ujyd5smMY6H0y4pJ9cKcE1IIQonuuF18LpzEBsKoxh0
3R6s8P1wN7wl8tZ3Sm+5lXeITfXvMn+1ypn+oyomoItLhoe0yrYashX7mHhqaTkfMUL7irh1jbXH
vwAO+8EGYaLrfHxzSNrAsZ9SLaiG6CsVf0HNJmrJRiz1UVGG5S3JSaAZfVXlzMmKbJfcPGD+VoUx
eGNDEKeIrp/jW8PQscsOH7lyiOvPtGxeLrSh5CsZZ5YVjVJTx9WZUDBgW42rFU6d9rdUHeVjd7T1
rJHKBZBSohU0PiIBIndVNCkiehWvBjCLvnpD8h4NtbwIeH55fqN6OS2AuRp8/0v5vMIJ5N8x1fhR
8OmjycuDRRD4d4UAgrSxbXUyKUIO16ZUwkcWTln/fUEXT9w2Yx16X4RjOtANAV6kAW9hZ76SFVOd
eMdn1VWLalsD67c8ZKfI4EiOXXuATWjEKRko4yZTV3bEk1E3AR3VcOi0WVMpCyNmnsueE1zoBOES
cZEFzy8+Ms7ai8DJ6xZkuEdqdkYbV9vyVigMJR7EOx1fdeAXIiOn6fB9mwO0tzjlf85a6nmrgBUm
ZenISy9965JCh21VZzPWg1t2Bq3VDvf+JlRo/HNzsWXYE7HzCzaHjKBX3HSZl634KbhUep2JFhO7
loSYQ3yR4QYtkk5MDTvYfDocvEBaII13UqHXwOc52YMqp4LVEkk1/tmkHV6Ma1sDstBSv5qCJUsq
a7+d9zfEy/6OP1apYMpgZQBkXCIgH90Byl64ug3YFRmovFg02V5BR1k+uwsD74wneH/TEVWYu+h1
T9CXZ0inLVWca7fwecZFUAI5U+nS1QfxA+lFUWB1zqRTIgMJ9i2bOvD2xwBjHUOL2G58UEITPftR
2/IibYv1xxQa+ulM9UBDon1sMoP8QFgmd7MuSCcieDWC1TuaNqSKApB+K8NeUhD7CVl8haldnI49
f/tb9hbrCWG8tvTd7P/jN5p1YR2SnadRvLm2lVmlM9G+lqCC3ryPfYWlMLOWGWvPGwk61BaXKoSv
JykS8IuU2bkDKY2G0C2L0iPMz9hUjiYub6tsGcfCFprDewrgIY43MmfUPGS9payuXQI8A8ToNz/g
AlpLubdNZ5zBxsB4itp5biM195DgU/6XPY6tuwv8GBZ1FruUpeMNn6gHRqb+B2893qXWB544OmFz
uZLwkIc5E+lYR5vJYVpmD26oB5lpJr7NrUKubBQweMZztlFHtnjXqVd19sexwGOplFRUW51F0MrL
ffsT1km8OXPpGHkOCcUOU5TU/8+myqNKsNxNMBYXiEnQXvHnBXB1a/h0afL2FB4018MggmS/zs0Q
M9eLF/msmmCvdpS3BvIvjeRU7Rna4RL2O3mHyII5HHfKs+IoBO4JHQ305m7iiMSJbr3e6khCWMak
pAcvv35TbjKpb7YO31AQP/xk8xgXwGib6KisNdTgQ/FmHypgQsaTlb4WZb+nB3J3NnN//iApnS3i
mcegl+xycoEdvr6HYLASDiGaBxH/a0UzZ2Kgvdk4vGIqPyIDWpGCWEpAWZe8CXZEDYzzgsxemnFE
GVr9DRx1Kbzuyd7M5Oa23X6KyRq79Px21hHPinSzjzwfnmmkvTuHQnewXpT9/3h1AErNCuGgrDBd
PpWwgCBSCQZqgkmeY2Pp/CdEkoGgMTYp2lVSYL9AyZaXQdkYHcHqX+U8jTtBYs0Y6hX63mlSrxlW
JIi99QkRgXKX53q1zstaP3cdxAI/v08qgCXMIpiYaR8C7B85zdYL4UsdhW+0P5aASYFobO/VG/6d
FgrEsG3tYgHLKeOf+3i4baakVnKEmeIIToH01rMA4Cn1E+dH4ZOSx4Qyb2ONSevXaVs2ckIHcGPs
+xfUkmakGB+jNi6rF6TZp2iOvA6FQJe1Bwk4zX5dmWvRTkmgGRuHFa7hLwTRDpmUsHQB7fRr3Ha2
tzseLALcsEyf3ovQKSb8ZNeb+byosvuMZm9cxUpMDOijlnIrYWn2dM56N+gnGu27ykWHalAwBj5S
UDQX6KeSHr2sJmL/RBGof1RYJurHjCIpPv9TwZdTQiJuBAuGCHPRMs59x3OvZ2DYb8x2SK9hvGKn
ny8W4CF0TLyoeUCJd5M6yjeAQ3oHv7XnuxEyUluGTI3lHUcYxENU2XZLgfZVpNhmFOXUqyT+9v6B
M6L4WUPMQZxwLPh/+zWC5+Ut+UxwKYedZXhyTY9LA+B2wUwDPLF0Z09MLzPHwrY4eqneitYn06A1
TWN9uFIVmksYcCIaW/W4E/tUAt1ZsQLJytZ0seLwTZ1P5vY0Dd6OM+Cxlx5fdwDososrWFHQw+EJ
8m8+nyNuvizUI1AiPkRO6/nkxL/qHccOJn3VuYyisc8P2oZFBXVFC+rkmtOB5npjbM6w69BRd5PR
GfxcWpSYVimpBsC5etgoc+B1zf48P7+WeeQJu4UHp5MWv1mQF6zBBSqYUgr8dNeiTVi1xZpa3uuA
NrJQffPQ6AnTCpx5a1SpxXMVNwZa3fUwSx9IAPgLRZ3rnyyH2qVFvvPcvol0JzHn7dNVsuB6QsUu
SOVZgfxqvFVajuGfm+4NzvpUu9QHcEXLgw8W+3EF8j21SKJyOqhj6oq7hhbORLokSY0EuAutdm1J
pLOcuww6uzWsYyf6wghkX4vHgmKmtApGq54hc1DZSPZXpIfqsw9YM4j3IUVvhcE5inor6OyZ+iFl
LBKpJek5M6tHEBhP7P4y28RMr7YG9A8olGoOeTZZAAwjQeM61VrCxCDnjHaboWGx52PQHrS5DwTJ
ueGbGQLpnfR2DGQUVdH/ixllwv8eVzEowDFNNvG7zEWx4dC2mB/3KIRtuL908YPCuhQ8CpIBGfVh
R3hx9h5qKr/RLCH99rmFyoS/HX+tnX/6sPY2bQhNyE+GWrExCTuegYhdH7sI3Syji6RBg5fRyU+j
GxqZCi3QglMtp6jwGXCbAUouhhT8rh0oujlH04UtJuGvlL7Px5DJzj2JInz1qnz6Mx2DFzRq8qAP
qoTbZcfwvd66qfqE094StrRZPekmwUVkkS+1PJmWeZJTLCcBP40EOG7PYxJPF5Qehov3qCgIlj47
8U9GTq+A05+MwUpKTxA68dlEC9rCy+4qYuuc/B9lw+9FSCzzNIEFvbNBBCg/W3mvy84I40l07TT8
lq/LFSo5/qiQTwitbRsO9Y4bfZhcRm8CjU+gUoQJ2n+epjjNNOnUSciHqwRWzI05iVv0L+cf+0/U
MddgIanq6ov6qO1jg4OMumzD5/131eW7NYRRJhgFMufmUozjFWB+Fxv81CuTN24KFS+swe4FbUxi
Bn5PNgJmQKL4fdsxzswEOLL/rQJCDjjT1jERLL+VrHiDxyXS8NJ109Hz8o4J+/XGSDVlehrPUEer
JSWjhg49QPLeSmfrCxgvPDBQmZpzi5Lr6XlRDLjHUMLg3TzXL409T9YbDIZFhT2aynXFtuxGPtgj
f3+66YXJJ4/AFwgJaU2qF4KuHQBMjxfS513HzzkRmLTuP4RaijE6yx5qdBkn7ZpzZq/eCermee2H
AxD6Q3txA8/rmaVgAgqVnIUdDAyUgsRdHqW20Qj2ChvnwbAzz62FrCweeeUwsKqvM92RwLa9/phl
sS5kM/OYsslIohkkUUnJ6J11vmzM1WD+sq1VqkkUUhGv9E+4RtNxxFWcnoIQhNOQI0AZj9gfdE8f
3YEcCB1zfAEcN+9/hslsuA0cp2zhjf7cUHcxkVxL2Q/uTorP6XJrBrU8KdUwCh817JxT9ySSHLtT
CAADj2rZHmuuZYas7pghHX/iJhNo8GDfAEtb6EP+RwLD1jpxyXuaM7OJQ5/c1XrLQpJW0lEe2ofU
05TQEBnJTGTzIisCRE7WQNB5ysa66kT+QziuRuNJsV9kznfqbn0BOAUaxRjPIjoDPaI5lXd9rEcd
6DzbZvC+f2K3wDpmnxhPMofMTpdQf4kcPiWW9fhQy9Y4e7po4GV7/NKZKjSVNxQmhuqXBsd/X9C+
+zTuwazizDB0A4lPEM/VO5xo6il+2Y4DUxHEEUmLFex2Kn227pfN9bXovPe/jCnJ+OQT4Vrny3WX
tJTTKFHAT7kPiYrebCDiXp9e4gNu9hhFoeZ4hlqPmEAed+vw9t77D+jwAg0N2RTvONHmYVjsuwaV
ad4fSkns5PSZpPDLu7yB2UF+DJC7h5KYo+Adhw/bLNcaS8qlHfilvOfH6ZNsII+SzhvxGpGsxSPW
0n6xAJpHTrMyBsucpOvqTKGap5p6uYoXM0oH3g7u9oPwCBK6OSLtT1G+cDOqyf7wAiGcbsF8jdcj
pn4VUu0lvdce1O0OVuBij0tPbdQwb3fxxZ8SaOgcHr+HefyJskaJPw5Dof7wQwt/123MtSX2l0U8
1McLC29gkYhPgfG0NyhCzMoZZhG0Csrztfqj33Thm+M7Tf434FzJkODicABCALPyxcm5eE8TH2Vr
vO3TFgUNgQEO52JWWqkiXO9gUidbC6D3d7a+n9H/vaF/39p41Jup0H8l4qYs9iTcwjI602uZmxQQ
zrf0QefirX6COmVQbO3dcz6lc1E+RVF9CPCUdLw+gnqEJHbLIU0y1/g1w+5cBRXvlfsj4nybSOqg
erEeihdOE7Gj2jsVHhHZDmRDzALFxWKOkJAbJaBgDcm5Ik79A2S1ihHCvFgcsVCq1ZBsNECla0BZ
jq5FOGksSniEv+LxZsiwqHbwjiPaz/scAh7xxfoCY0kvD84DnyEuAD6j/lJCcGuDnFJ09KVBFvfh
kHIhf0kxbhu9wF3pVT7iGmIc278mAZ3zvPMo2bBGyXEDV+JMUxtG0kWmIyK1KcN4vpii4jJ4qDVZ
YjfT3eMqPp7lzhczxmYr9KFpYHcj8k5FxSUvs80gAGZKFNzxvQfs0yhcD2mJa2iyRyVO3y0NTGdL
YhKxmmw/Pkvz7WZZVPUJd/uisSRU6G36AlyXy8YCxVxCgb/7tyc+F5kBKN77LkS3GgMpQ2LVwIaS
LWVNkKa1lBGpmlIV6omEB39uSufIbhYruUL+L3DJClcKcmb0M4xGS/Rh//JPHee2jx5RI3gDVECt
Xg5tI0nnDM8Cjm7nsGny7ntAuPhzbTVwuCytgvxwZtJvm4SNnwfevAw6y27uAOaFCVevVGd/aVTO
xz1XhzafB5QJRZ3nJdXlZR0NqwPKZRNgpscs4rLNrtEcTOMJjxdAEriJTI6v8jdn1pOc5uCfGwAQ
lZI2e2OZuLwwq1qMtBrTvzYNyotP0WDpTjDUp3nEp96ZiS0s2aeG8O5HSCH1TUoivb/kKMrsA+4+
ErADqiRkKoMFspNOgYu7f2GlB67pdkARL2k21fSohe8OLTCSl44DJ3rP6VWYsuhwEXTr412LQG2X
KFL9GA6JbdUsXp6CmAHCvDLYjUStFX5ouz0zZqcgiY+2K+34JDiAKJiPCC38c5kv4RGWqX0/Q2p1
ELL74DnX9sDDhBaW1aL10P7vUsZbc6jkwsLwklU+G45/VfmU5itR5F4Fy4e7KRvAml7RwaFzdubI
wXFgS6If9RNkOP0MqygHW2Phn4mv6SUFgVEcA3yAmooqwi4MnonN5Z/k1fQKo+OcsdQwEzu+Z1Eb
jqMuLFPiq9PcyTZLThqecq5SGH1b+3U3JpB+Pb8EXIUlfXMv1HV7BUX5BdcBisohR0lqFrty70+T
qN02RjA9BIljNaw9NHfu2apZNqLm0BpHTyct3bSjp5PJqA6AdCup9RkdO5qRNuhwyg2dBVceDI+P
xH2JF2kT+TSepz2MhZG4llwmtCKS8NOPx45oQZsOsepM26hMXX/DLpDNaK2ShOXPLZE8dHg36jc4
xgb7yEPuUyLdU3KmhUegwZK2Ety9IR40tHWvuWWA1X0qJIc4CDGl5qLxyMK2YIyHWU0O9viCct0d
LLTdLbIZRwc92vwkA6cLuJ5VqQSdoq4JbzRdZvZMDDQDmEC8txUB59yHwuGS3z3fUYBrW3jSYoEG
9aJ9gQbRZqwrPFnCwiw5QgNDY7EoNBnqNgjyVLxOtf8A9PujgzwIu1ozb6grjwT/CePXwQlq72GW
7ZUGX3bPQPwyRC5soRH6t+F7F1pqO0ljlOn2u3FcxCy7cGlFTwAjgkzxFBgYoI79DPbTklkC2iZC
a7lLZVEg8hoWYGxV9wqbOQj0Vu/sltMrzIkxRh9wt/8ps6wG54WGyvCU7k0/u0T40uklGNIsg2LL
1Iw0I/EZh7MvGp1dMSNoIYJZ16C0TbfJOPjCaCnYEqMXMxr4Twj3q3xZVa8a4TLvBIadTWnYCcvS
Z1y97exEq/+gUhMFhBrAAWskrMp5OQ7/S11JXGaX37Y6kxKFjlBBFszc5SX/upnh2kr5tjq7QcP7
q13FkqwqvcuXHup4ObMkU8UxXgAslNse7648A70xa63t0IhyBhsSrAfmcp/tsFF5t8rPS1Cb36cN
kx1KInDi+8x59q3FHDiFCKXS5k9OtoHo+6BXwxqzYjC/gRMEZRv5gJ9xvEvu3POkCWuG1dWJaqYx
tjVoV38HJliycigCTbzNJzcwmmpfliaxHLMjfIEm+5IZdIASE2ANsA/bkxIYmyRd6pjNUkeYYJRD
v1dmudDgJjTcZTFRTUWedZpKspIG4/8Y2jSPp29+N/JNDpXDTkrh+IogZ/qSZI6iGmP7KZ2DaGZZ
/LrG1zAAwUyjtdZr30LiWu76bI0jEOClW9JV3CfONjI4dEx3Lc1FVzTi5S/zpgqQxH8r+kfzZZrY
9kxG4qrMXBzZuXqZW0i4xSiBEABtM/3pQEkBa6zP0Fs5yOtbfsISQD3TC3pu/rEXTlIbdJ2AtWUy
KKxLTTjSZUCKZLWLclEkcUP3Zil5AqwpRS1AdCNFJVhzn7i6M3kJLLHI6jrNfUKrL1cAl1GNg4H7
MFQkSCGACTS3jQvNjfVi0GNhhEv48BIVxDLfl+Wus26Jld2/ekv2y9R0eFPBEuzirkPROLKYOwU0
ons0KUURGPYLmOEqPpFfzpDLpfvIMyF5FBcIB3XuyPFiVaytpIXI06YZna93ozNf8APhIhIvZBS6
ingd7OpwpgyyVwTU/G/lIM3V3F5iib5xc6KbqOqIkfS85FaItExc2oLmMd2i6XvUekbsJAMcyZYa
wXZfIFdpQyQcqB8O+2UCssq4DACW+5xRpWZzLBUN5UkHgbOvP35SgetZiekg30IjY0GeENVAtURI
9vPuLGMmXr2eJhcau4hp/lpyO0uQk/yeLkRb+drlID0lfoTjY7nMnd/LheW09ctjhH3EzaA8k5sh
ClXpUzE6vjXHuF1PkZrpm7zrPu1ZtWXzkMDqTXbA7Hlp5gtTEIWtJJLI6RT+Q0UoKkLPOdTQgLgk
eIZ6/0Tti4iwHd3g4/GNKUIj7Gsv7pgwm6uL5oISurdvdHzYu3lf6vqEoy1wsu6xRgRnL2MRR8Au
pcUkjYygtn260H3t5C7HfPEnRSttWM6+05DSvq0sFPO8Tm1oFlv5F2MotE5r6mKraNP+1QF8clMj
98Xo0zM5PzqBRp6KKPjJrQ+T5EWtq5Z93hh1I3qupSqhoPL50hftd5jF83aCCGCTvDFeK6bjDVBX
nUyiUHRurD0o90NzbU4YZXz12fwG6gjrn9Z83eG0acmMTtB1gVudnbn5H4wPHNm5M2957sbmYItm
CfY1NvedP/6Y3x7w7xoFf427sljn9uWvycHugn9EumeVIjdaNzvynAVZTO1wiRS8AHnRyWVV5Ek2
B4xnf3M4u7FAB4EJdLOcbBjMXqZnE1GbWO6fcS4sQLzIKhFU3Z70cf/zC3vhMcZNtLchgVgDv8fr
8nVTkvbRu6XShyF0Z7YfnlNrJou4499vPI1cvEESW23lEqmE8xBraRn886S1ydt4pAb5Y8xzxC6E
8N3VFHTtEF76aU5Hn4OjWE6fHFbdxzZCDyKcwAQYZ19Tp9veYdgWqTk+OlXp/PgXTbVH0lF8XljI
d/PFHdqbplHncub84NxBew+i91YaAH1qkIaNJHlndVfBD+AeTRcCj6AcAssh9GIrpjg+5SY+3Gzx
6mJmI3U2VuwpRbf0T3okQBNL8+g+brro1Grv+nWA/YHVzwuRuFqfzO3DDPcbwKlH6LD28JrTMZ1o
rHsxF2YUdFpegCGTRRz1O1F4hCx50pxorP9tBfoGNI/6XfWv69e1eH+z/kLFaTlqmpAbKVzb/iVg
AYGFxQCoNuaMcubdBriNLD2fa1mzle6nj8JWvbY+AnQzGPFpvMevpuCrebnqmHqns+jztsCfpl28
pwKjvc2S+/PTdJjUxq2RNE1Wag/mavXu8aIeLYyn4gXpZTFscEXUvSEI07h+6IYph+d1ZIrWnJwL
dnAo2ipkieYo3MCoTWD4V77wEXwKe68eavYIVbdAEj8S9V2AorwfPdjQph56NvbaMeCA1DSNQtmZ
dTSb/OH5QDsAnwUD/eeVKwbfIzMkYFGsGZZiH75ra4bnqnOUAj3OwB35n6ciBcbRcsYHi/02Zn5c
iTqu0JmMBHQagzGIF9tDQiqAc2nujIiBYZ/M/u6dRjvbfPRlQuL2g0XSQW3l6/I2eyxYq/zvTg5d
MPrE4ev/RzDFBFRwLKuEBc9L2FkPKmp1OfbH11/CWNGl1uGWpdeKnS6IEJvGVb0VpvqxHoguXKEu
AoWe0gNjeZIfvkLqE3lXXGdKwgsjvHbu4uQZtdGhs7V7dcJr50gxz5KPUL+UIPGUcZK8pvN+t496
aB1XFUqAGNi31btQITPdHv2YRC67WzjHHDtD7POJxIpZjGI+NI18PODwXHoBZ0a8uzTFLZsQDaF3
EnQ4+2Sa/ye1FTE3X8Oe3588hWi1ywkpL8wbeLNlXgViRxJO6/NbhjkEvpYIIqilo5efKOyOt+cn
Rum40K1iXultJ0yqioM7Ew7ZLORtWTSCanV05gxxI/4nwwJMEVjMwK6nWcScuMxlBMzB7kDlOq+h
4wphu3/AxGV4GBSYrlITu/GrHL7/+0VSW/gppnxGCBlLYYq1YssuHEDiDdWq66holh5A1LT5Mbsg
LZJjrokqXdb3mDMp5ZTsr/dffs0lV+00OcL7Ib1gEvaIibJ+/zzeNM53NeOzvmRB/olZqk9fV4iv
bZ19naBjn3rwlM28vJZ1M7uPHIYOBjVpa/8GNjS7tYkmdpDlpHnsNvsQraZtVVmqmgRSqIz/+2Gp
Df9fcJi7khuznCbOpx6x07vwvQ80ditwG4I3VBTUsLXbmwNniHEN7Ql+/xmTQXzyjKfm/VfkYQfA
yoft7OetSqkFLwJaIKl0dGSG1Opxkyd74fMNI+rWdezFaPrq6WQVh0LDI5Mubq85+TEM6s+oqXUR
8qlQSRKOMtK66lSv+u04ZH1MCcbEPLJ8ktIvWk5LIwETEP0ZiU7uTvkOgIq8N+sUBx4Zi1HN1Kds
aNLG0UnVfopwt3Nyfw0Z9v2QYwmQu9m9P+NB6Zso8NO+PurzPbpeMwFAnhmJtpEC0iGq8CvMhaMZ
H7PM8ceBwgpddj/35R4zVxh4ImOqBHvPPtw+HmZFQ2vZYolQGwSbOk1cgm3h3TvMBeMq31gKSw8x
e9F9osc5GZkcmm4AkM/S2e6W9KBCuYPas2EeZD3VxBXagMAjyybANjZeC3WnpizWoiP8vWhWFzA/
VCnCpmX6VKrTuWERw0/2JaeUJ2+S6opEYoby/7DqxlmtSo7DwBGfboSxGtX/7t6P1eTBQkjnm5eT
qxd8jYu+sl+Fei9WXSuhqUG5NUQ+bJPDm1SoNhrWJddJjAXZ1yw4PE+6ITUX/BDsdRHYBid+PHS6
9gowhX911cRmvhO8aOXLEO475by0eyrFDL8DDkW8i6CcGepfBfoj69s6q5fkiayDj+9wCZR/VbWj
3HkVtRSX/+gi1Gg0qA3lltcghIaPuYlaz5/WzCRhVCul4QJlv8yx9dj4OrrrLWr1JCsgTzakcoL8
PBzLHbPoIWK833mqKXqrLuscsJOAlpIHoYXHvQODx3/0f59m6s3mLiOoy05HGNbvqYgrSQeEblIY
CmMDkvKkHCku63pQQNHKMvIle9uIqc8H2Zh6HseTYGqY6vqCPChU0ijNbk+LppyzKkDMzeP1h3e2
OWIav8Y+udLN4N5g1jRHQjKqCNJZX3//jtcdzDQYNNFrgzHP9/wBDrkifZv0DkNBJ/TCNHvqKCaH
Pi6zSjPLoRUrMyMqpHoOKyfvqxi6I2VgfnN8dLkLNj4gWxoiA4YEd921sfrDAOYSI9iuWpIqHM4d
ivKDckUCOyljL9Ae5gtfBGL8Lfbffa3MgJMp2NGtIxorjr82iOjRigvHrRq+l+3qVNYoZXfNssgB
dAiJNKNTYyt1Y4dfiXF0kQ6+MItJ7jKZTQ9xEXDLHu6dkCyj35LiQRje4/ZEYRTemOSYIIrQnANd
AZuE5svbExg8l5yV5i/V6kcqVA1+s2xyzErkXSYA+QRwoWcNo/uop7DTIlRPnHUAZh4KlNpMxTLc
/zQgwW0cQBAcT3ysi6W/91WtGOixNahm6IPbsAjOvE99L7HCHuWDzoDxVp+dl4XRfNO5MC0C1XKI
cOh3CDlpmvc5s+9CERlT/K+2q5PpvQUH9Mxljd0CTyKfmzq8dk0Z44SrwjH7CKpQuHCKw7nJp3HU
4RcNHy3OttaFooky9nyWyP00i5UlB25LtTxmU++g/GGJk2xaxCNBi7uH6iuJOBweSkD/7BFbptbo
r30LkVNnfkqUwewgrSqBZj/witrHlQDHTJHhHO9zuFPG3SB9xEAYjc0YJZTQcLpgrLqHG1x50sga
ePZFOy1Qq8EdtN2AzsymQ3MRAk9U1yqrBBvfuv9BAn1Q62l+t5GT+XTwZy9ufbzKnwjQhBIsWiIQ
tZAVQE3z3PQZzvqlM0irCymyy4K2qZ4z/I+HGg0dbXQ9wX6i5ek9+LBzqIHxr2c9YGerUemybu4w
j8P+0ejLBclemP2I9rxbjzCUg1eVr9TTVCQNsvbjl0clBmx8j8F98oiygIAj/KX0ZLHEA/EnkBiA
IEU3vHTqRNMPjxwfH/XEZ1p+G/LT5OMVi6pli1Jc8/2SwHgrgP5aV7mnZz49YTAXfkKk6keGj4Bq
U9XY0agGjSVyARQpk3fLAXGU1m67oj9DcDc4NJ6QdBCFSlPXBNJrWGC+QnGQBeqSZchMlFXfBX2Q
f+8IkJR4fZthlophul23IDCt6WdjiXqIEoCqiT91N1Zl6/Hbx/n9qxBU2C7+K3KJ3amcltrvfQtI
YMJILP5SAQORfOvCJAbuDqDQ9rduqxCQvGnUVj6p9S0FAAtlnsOHDodhFm6h+VgM+Jc32S9fbdCE
t0Y/lb1w7OYkYeHN+o2CIwDpdYamz86uxHNqBSHpyL2mUsrrdWq5KmxhyfdxB5cXBUOubZcq+HK0
bVSuYwqnE5omaSajleLQv1iDKi+rdsItfCPmJbJMoQLO7PYJQf650AY9PXWbOcinPXjx8FdDx5Eq
otRMAN20bYTaebAJ35f9roYwKeY0Wefk4Rr210D8dlE5fasXyh92lRHYUjPpeMv7+jAqp09S0snE
fCZMRh0DSh4wDO68YnKwMQCTSVDiPWjbK9v6f+vz035nLGpzsJbdidmpicAOwaU9vCZi6qkxq1nR
Zn11sS34OHYjVuEY/osh/N3FR6cf+H+UGb+5J+T86aKrF+0ZmiJTXdNEldQR17O1RuLvs/U58iqd
KsD9v7gYBHJFM0WtD1/C8iF0sqiSu846VlVAbaWdGjvGdo3FCYdxfm55jU8nVfuyeEsOjgBEC1wi
UJGhAddGjoH7v0cBWegfMRLrJ+irgQ5ht2sOEcoNa7VXJutQdMsPMpyivNXWjGmAdg+OtmNHjagb
h2dpk7rQ8RCpdocSrWqxjHB6xT8dr5xrcUmi07hIToANMxU6B6ePGXXCuGFNyUR+9Ff5u5emQy1k
v1r6rJHJ2UNn40w+wKFfz5pFie+Wyg6kaCNNYDfx+EyArnuKkBqc6c20ODC1fnoZtxj7k5W6aAFe
hDfcgKWyU2W25J7rRP+4uJCE0wyYsKb0sNBohQLrGiHBCS258K9+RbtR2WQdiE2eUp8eXfM8M+tS
jj45JpJ5ihR7h5VJYOAjGCOOyuXsFNbol59KT9CF+zwseRNbkK0pq8opVjjSSn34hn3+byYOXlCu
fApZrpJZ5XI5KeGOdWa2ZORzDCvS+pTE3i6ywPJ3aidLxJKqWIN6BN5ONvoylttFZvWsZuGiZQVz
UW4ygdDaJSuAz5rRd0FcRz21vSDBAem4gBW6h1vA1t4dRJSXbb7dPTV5W0rfnUqDuFa1V1VUpSDc
yMjHSSttEXIBg0BnvTUaemBJiLVUJh/jfy94ZQJNbed8c1uVkUC8yeapL4pdM2EGEzYsMmpp9p3Q
EuyWUBo5M3p6FDqP1gB3XIhc+MVj64udnuBuAYQu6h3zDSCLsAcWv4R7oVi/YCr38Y08HscgdLLG
AtrYHT0GIknQuB7B3OY4YFcH21f7KdSazIA1ngkIfSng+wuAsZeX+vbKv3OqNqbVWgH+vGj88ZDq
2PKQ+ZFGdG9SqCE5xKKbOu8bG7dyEFun+LWuWGRc5LsnhWB5GFoQer314pzULlCOTZF+WqJaS2GN
Vysj64cPsrkSWvYfFCO1/hX9sqM9C3YzWq/tFPO0XpxzQxSJqUJOWmvPsxN7M5bUsBdS2OzSivmE
oLJNmdIBGt+J3At/rc/30FtSnLAkBzzvBlUQ+C2/882DNxRgbxgb4VNPFdQ6cZO6xtRAaHhzXLo9
DJqFQLOOxf8/tAU8Uzn06+E1kL9pXMbGVyf50WsM/RJEcXlQhsdIqhpPdD9usg2zp7IMNpbcv6Rx
2DKS9boIWdlRfn/WPsojKmIFCUYIYjfWXI9yyWGqXC+/sy42321gvExHufAT+l6MmWFUfevW5Zs2
Z2ku/0XklX4Vxxi7esiSHJRetbhDR3tTT/H1cuKqehjO8qP0Wwl5aC6YPboKyvFF+Zelmtrm+n8a
UvGbI6qeoNOwcjjsgtZSfwM1OdrurjFNnzIHlNPopqoWxw5TNQ6o7PAFCvdHp3pPd+Zku3ulKanU
Cf7V1DvXXPBFRf0ajc0BrHpoSLoLEYy3jDS7ZqwJjazNyLfSHK+QksLydtY4P1SviPNxTbijt0on
kUm9rUe6oYPda1C9/DzqjgKXswKscDLwNDrpUN/DADOD8aS4jUeWyiUZyuB1ujqeYEm1HOOO0TVo
6/6JEjc6KrBiRvEFsvptbk5PN8cmj+siELzBILRTwP7faExjDspWFq7KOrF8zzhHY6yW1sa5P9EI
3Wkj1HDcGGDvy2hWj6HvAcyKHfMPG3n9OIz3YGEAf1fLIWb1/9tMYKZWnZXh6/gmGbJKJWemM7JY
+YE3tyLKl+Yx8GhcS2CwHjtXxw+wjVSLi1n0RY03zdAHSBRqG3zZB1DYX7H2nt6mn6oJaug84Wck
NGzUyZPN/rwb6a/28Mh06Up0Xc+BYGh4t4t6I/nTA2FZkKskG+gCRHYkPA0pHiA5HFo7VTmVOwRQ
AshUHSXOgCNWI9z0i+qF6vi6PlaQiPSSHCJWshjplDe+FCxc4tsJt06ML7Jkz4CgrcC4+WEnF3w0
QVbmXFpn6Y6TvZ6oaE+eDslucvrJxg1fWsexBEnXYKAu+w5YFSWjzAr3EIlzAfOqNiiaQXzPKOah
J//sDUHsJYlkIQmzzbbSNWQCZacLPrb2XcZE2zLBxQPvhliny4EDQbtWqsf95tQRftiRqM5eNjLj
XLX3jRKve3zqTABprNwsi+uo6mS9Zo7uqoq9Rfd4oWLSqGqShaCz+jd1BhllKKBKTe4QWWGg2HF2
pU4GT2Go1ncwbL5KwEkgxZCDJ3BvYoE0Xgpvtqo9Rc0mC7A7La3STcxA+1KXRqwEqYbDGdI1Dd3I
dK+Xs2nOrcX1CtrHipFUzDmPany5/Ywn3V4hfIuCRCGme0b0UQ3DhUJ6LaEJuiRZ4PvWYCPvhqbp
AEt+HfIqMlzeix50hN/CopDoEDGKIiR7Z1jkDQuhTlHXl75PiKWqm+3P2p1s4ZVijdMtu5FlP+zc
TVkdlUAAIhjs/CU3iEUfGeyqw6BNCOvSrabl3SuDDnJ2YYf1JeJrXzU1TmctA7NW9bBAF5IkgZMO
H0Pux+Ry76iJbnzKAKmwiuTHfTpyGfGwX4zTdxuWUh2d3B8LufAxH2t0iyN9u/hLOTjC1ybW3hgH
hLa7mUDZiuoZGEnuWJdfgbpZCeFKdwUE7edj+r7t6qDZRjZxKvx4uxYov8qvv3d2MB2sEhH4Sa28
4RelVGWimzo/5H4Q1wHM1+91GF1IuTlrdigXhfqB19bRMYrUnUBMRGwM/Z+K34FB1wMgfitd7taV
kGRsBQziUQexqTDoLimnAMgxffnocVyG5TBy0vb/vVkg/nSkYqUmZeUOviZ5OuBkSgPX/w7hdhyK
BgoEAvsD2bQW4uKBEWQ/IMave7H+t4TccEET/JulnAeYn3GQgo/M9f8ErTZOLdzcqokjDmufbcFz
3o83ovkE8E0GYGQmIfVNaLM60RFN0y6US5dNhCBVUvagZIrxU/sRruiDJrlzUGcEjHKoSk1RKDe4
lLHD9RCWqPlft8ouCeR+E8VUJl/kZHlU2rWyau1WsVPd5SjZg/xVjoBfyw1tN2cScmgqebiqwOUv
Tkj1/C3u8+eFfzb95ajozVQP231adEJ/q492ht3sTk2jW8aFvN34UvkY2ZWW6qZ2UB1BJ+tociY7
gYpIYKHhI8R448nDccAeHydKe9uJDtTQIGRb8cjY+eA3I0xn+FhBl5I9d7OGDNYIi60pIArluHlu
fviGjEtT5OTXzWMgZSp8zAQlSyQmyloKOivEr7fHSgMmQu8YFG0J/4l69JeQc7gqZ0Qjlcw5GE/w
KJ/rJaB83fPN5LC0wPSmDH02GuiKwr/xwxgTkQLpvSo2BnqKf4G8HWDu4JmxUevpzrf43S4UQ+ja
7nG5fDcPeVbZXc8rxjFfAa+0hflXkBwxsUZExO3TWGPHH0n3zJl0JOsocOUpA2t5uJ1atACOmKKY
dXrcjtsg1JzztuBcloTa1rLrLCX2GSSLtUcA9FafiLsE7KFOPc25AuIBqdXPFfajF1rrKGIUIA0r
03z6QKHXCb8mN9tiCx3+4okFHajwTphAlSAvaCFKcWGrgS+a0yCOUvoYv+MVR0Cx1v6xiKEe8nq/
Ph6aU1/K7p+THhz2of+N7ur7iir4G0SslRjEPmTLp+vXeU76ZfKUtT9GGNUOVohWhVHhhBnMk+ki
cx0kBy61B3KX+L3/DHLdDl4i9LQKMXXsAdnWJnAc9X44ZdqZoLpMarI8bwFgpq+JpCJBIkPNWRZI
K7UJHgfJ8nGSbN7sl+QK24bJ8sd6O6VjlyhWKjTidbIHvUQBTiD4JJCqXomRCwANTLll7hVaMgZJ
USFvOHMhC6WL4QSJfznhUAh/yTq1BvdURTelDwti+q9YHIoqS0uCszBVsqT3Lsl41rWd6C6Kw7ck
Zhf3pkevJ7G0qjkJ2W7TUPuXVSc3yQxuxCbNMYR9WYx1c0aRUUvdBGCzvq8Slag7lc8ufeBTepkV
J0ClXOG/j4a2zy+5t3BsSlp8t197Pnv1W0cZZr4aZ6BI6QSDRooFeQTUT79Ou2yGS4k5yqfXBryc
jNT4luWkmO7xZBldQB1BlEGfwVUVXT5Aeb85jYCvHzYmy2iJ7O6trJ8RYVzZQevJhXaFPacGrbpo
30ybVhs+2GmlJPoMKjiqaTAqjSXcRZQyiMhzzyIZs58rgUTIEZABVUMddtx7fVct8WOgpXieAf6i
THdwA/BsLtokyEY3Q5Un6t2ju7PSOvMhop4+cLfcdUtL6mya6DjsPx6V+6fsv9BSgNhnZGU1i1Nx
qIRbgAHPkn2n5zfnXoAlN1fo7herxlrviKut6Y8dPB+3TxxJvPANZhCY520/bwD2mm1D5UIb7Kbm
xE9Nmy1F+Xj1ybV/5k1mhgigBukNQMAe2J/HHSPgd1qbcdt7o27+HgKbDjbR0UjcoIzv7pPoIg1e
6ZgYsq3+hRM1DZKGVeYyPmCR/ooCnQbKYDcySj9FDrkt6mFHGJwehqQHGGMN73dbCjyGBZEIEDzk
rMfddEXx/UAvwVHpd4TT+ggstV/WyZYf/dbi9J0YugzaqsvXrsz63cBra+3DLA5JXGBmoSEoe7cv
ZX+FLusxkGE1LljIA3O7qf6/T1UdwaBeg49joGerbpQYwPGHYD/ax4fRlzJBTcAjQdRBvxIB5g8E
NnxWhSF6S/0Z+2kDP87gNHwOpO50rRqG8RsaGm0+RvlkkLMFZCwUMl1Cs0Tb2IZLxiAiMXd8LCDJ
/tOg8Y6l1uFmA9k2+9YiCa14P7XntD/iEgvbBfGOSm5eaXxHgzuoEIPPB+/pTLPxeHa/7hosXedH
mW/SThCuWHi+uQGpz7NNcolKvxaSY5WuhQSJemXa3yhycIfEqEeQTVgumsOGM9rWADdyFfz+D4Lk
5umKS+9lkj7valhp9CTkzfzmfw8c0oiSv4zupAXfUUln6SXh2SOcYBfFlSZemv+t03H0PbzDN1+/
hPvUEpOXCz/PGIQAkHmIEAXu7qB8Z4tW5DjusOa0b+4ByNbProu4lAPW1KlOstrFTj70sYNopkJh
skkI5kgYTzUNz2Laa003ytYzHxTfo+JBe0AcRNhtkbhOW5sHIuX/1uWfi0SruHtZfgxO084CLGb9
IGBRAD/YHkX4dRRL2KBj7NjHoVhgDEY5rtrvXu6M2ZSlZiB1kQP6G78IviMKp7WlQZN8AtHsE9hF
VHA3/UgYXE1Tt0pi0vSBdFYOkAvR3kOLFNrRNehOKUkhXChVljhqnSzTC1ylgUZSlh1WnRAyGat0
Byml6nPbB8DiWT1A1I7ON8miMkgSfC+O2jx1oLj2LcLAB+k0gi0bXX6Xvy+wdsAxN9wO/mmHkKyp
kVpdUdpaKkKXueVvwL3SsS64v8I1xWfnz+rF0Xhiy6iVl7i2b89++6crL5siBzknsomAtiTpSRNg
p3e7pzWQJwrwI0cLSPqKQrpVAKzBRI5eVTbuW6KjJQ23yNBJhH6hlGbihDv2+KFD8du8SUiK7wTU
FUH38BtGxkatsO75P5YnBAnPjT1Qg0Wdqe2HYeb1TzJjdq6MM70fkv7Uon02R121Zy+TAZWZhUNs
cE1GK8BOf6P6OG9/+bxWPXSpMuZWDKJatLhhyIY68Rbv9iZMyCUz3g+AaGXpLb6c8f1oz0SEuW+o
eFSJxdXZiGk6R4nfaOQTYEZWTkSecVwaRSUl7QgffBuXwmpSNl6eRr+RsTc8/UPm9d3U1v4sNOx+
NC6tBC7j5iNEW/Bvd+OCcarlH0zJTQiMIZHcDlXr6mZXf4qqxUOlpQ3q0BWO6nzQjNz03tg+OGgN
o1ad6C9qx2pIndpmaTXUPlBwrfSLULg0T/cGqh4wko9l3uGs/0I65vr/hXlEBTRqqCIpBqrtmlyt
zHe5d5QjyPfD0J1XAb8CJE/LlKx+PeYLGoaGCYPF8TrdNbHfedeQMXQvTrvo++piR/57pbzeKy6L
osCX7iOGmVoKA9fMvMLSOox8VK3RweaXcS8l2pBohHqWXWzwJzQKCWD51EP8qlI9pSOsBQie33tY
ZxplxA+5o+L64oFNzWlfmquRdNG4ye3T5C1WaD3LYgAIZm1zd3HyVr67nfHu9gYFMOXL0ItRtDH5
6z0KCmPz2Im9wi3F7c6wai1p8rRUDBWY1QKNcoqQ74R9pGG4rx0sXgR6uGsz4bSnCkQRqgpY4jOQ
0Crs/CVRp60tAI4+EYrxGWbBw+3VzmEatnlBUnZ7El6fSFuTlYOV5SdRplq/SdBs3PFi2AlZprS5
5zk/bH2T6a1fKLn/BAT6UEYVAI4400FItVfrdaevFOAansLxQmymt20+r2jiI51KNKBbO0Bw6JY7
lwPWMt7WOOI5+txPsH+rZevsMq7y9kXkl/YreyAF9jDSNZfVMPe97WGAgARjnd0h1Y/V0d+ZFipd
VK80uB9D4gqJuorQzFyHZo/hv6MNuOIvK7Eh2zms4DGxLGxq9md/G72lGckO4VNSHam/XQyWxISf
xzlRDEMzl0jf826L3qdAAe6BeVXSKAByf3KOq2u7D2nwddm8cekB1AOcr6QTfg1d2FQuXDWy7Nzx
uu0cLaSgxACEm3gXD08tncQScFsoqWg/A6c4hFSLufGs/8poJEIzl0FLKFPIUqm9t9HBze5rjneb
kd2qN8ue6aOrwK36nZLBOmOTIJJJ5ZruVwNlXSMtyVexFV6GEZYJf0Keua4kVAWcCcVS2JA8Y1ON
BU0bFr3au/8+aHFXj1pyf5EOsDWeYwbGANz2qLj8urygIz00AGOtrEhNIIrUCkih4UrukVGqxeOE
I+sNW+VWdvzV63njm3Z/8XuxVQIiZD8GOPfF3XzLduojGTBj2FGs+CTsrzZAeq02KnTz4TaNfMVs
MsRjD0Tpe21mM/ljmWHhi6PkdX8UVnXA3sqjwhFIfUO1K7yqKnmFIWgmC6AKmsITAZVZ1IxCSiVN
02wx56o/GS1o6KJExHTDT5JZ503uxBoeEkxDsI01sUE5UulylnDfo+v1CIpcn2iuh35v5PaMLAgM
hlhCN0wvZjY4Ts4nY9a70zb8oOesFrdDEsOQ0fvUxlWJqIM13dl02n/bLL559zvvBlyC1uOUmQC6
rn5IAnX89ryvYvlKzQ2KNGQEG9pe+vDvRIED1XFW+byJvebclMcGVYToNyxQ26meknCIop/xxEZu
OdICB5KMkWpCnmh35eiWp/TZdcVGyxo3vhV4yTIVr6UONS8Jz8fOl5Q3IlB+llCnVNCdApVXmW7R
v6Bavi7orOjPbim1UONCpZY4UN7mN6M6oPvAep4uEgLp5FP0XrVyFqZT0SddB9nEIlT+Ef1NaDbl
8Z7V1HkdpohLemmOsn0P66Y/fAI75fwz4Sm4+yZOEooMcwrVIXcMlc2MPdhON1zmAirWb7acuPlT
CPLA2AGGzAVPEw52ILefz9A6Xl043HjDmfsWICRRTm44Gds6K2AF+4zyFbfcjCGIjHxGxMvfbDLq
c99NyVF26Gj1a1MnisAxd3ZRju+qP0Uhl/8WwDSXQeMsvRbVcYe8ltNklSRf3zzpkpU70l1+ixjI
2QU3sAHPKfmO3nEmr3pYQFn8Di/jQ1OB7j8VfcprzJDL6v8SAsNbaKJKsh4XUr8I+MKi8S37Lc2+
8tB6Xl+lptVMftOuGGE/L2vcpbyzEjpEjjuX8wMgqKmJwP5HBI5/9ytEafMFFyaIMXgCDWS7CIqb
SHjdp5lNYFjJmqR/Qd/NS/XR2grAYMAU0O5Dev4tKH9iQDXzl7/MCnBDOu0k2OJrGbf6hS7GXCMj
X3sVpihWZ5mvGwot3xcS/Wq54xpc9eSHwqSpS1EF8qaPtX0J6UQvy63GFPcEaI3aRtUuED3lDJ7/
qhFTLE7AW0P9A9dZHnfCbzmTbdGAp4mDgCvZ6i2jucKTB4fXiVDmAn9SfC/n3VrxLeju/T49e+Yy
zquO+2okv3LeAHm0FwNXTC5/r2AdUY6Nu4OH7W7J8S660X6/EbzsNO48OYR9pUnbvdl9JeBChPec
ukf04dNKHwoSwvg9vDxh/ITG30Mle3hQpexaZoZgSvlHzlk0iKrFZn5iuPUI99ey/4s0RrNR0Eh6
eOBlmLraQc1a3P9qq9shyKH8e6je22b32911g5T962CW8Zgu9Mf9LXQ1VoKkUfzCYwwfturBf3sJ
upcrbDPQOtv7KvbOWuWJTZcr1k70NV4tJrkGiPtRAJv8g371x4zvwZEjNGHuB4sXAH4GaqLZyfXE
SC5JbVZQT3xnoqElPPaZzt/0bUoPvSajyXFhT6yFRLPc7YwszetT3R2l+2cEane6wIdZYOFNZBXA
bf1LobBJa/v40Ju+czPBgy0vs6YT2jKWMQawcGilCpEQ7kGvpoEUJdP2Vd7kchbBQJ/p4ZREV7/P
RFTHmpK9ETVni4YL81M7cUEOsG9G7LODv6YyTWCVZfYMfZuBlq7adaOPB1nkAxutx/L5b3zXnTaF
w3L9awF4z+hd6BlDLKyoGqwVQ8X6C0F1LXkfqMLFSqoWJOOcohqbVRUOk1PSb/ocSMmHh5YNZTay
FqEjpewziHMGcQSmI/ti5ub9JUXix8WyGZv6NxlPCkvKTEQbBr1yG8AJjO0TXEHl0IayXR/sSkc/
LFL6/dQ+eDDJ4IV03Hwr/76blDHJ7A/WkdNmA4uKkO8RQ5x6Ya8PwETiQulbZSfniIN+a9ty+Kvm
M76kVJzfpvizR09v0ajgMedRahB2Bm2tkov9tvmxAVR9MPjJYaZ7lLT4NXs3EmkI4oQKeGLKZ8Y0
3vIxSjMXGlfBXL+9Njpph1lIB1Tnv2MyCei4zGnYi0Yxde0kmKWkaM4BJxdywEeCNw+VbChfVsiG
FbeE3gS+J84teBkEhlF435LFE9SG0h8zeQ3juYIAyZqfrTf+3XhgtX2WoUv1h92ydlHXo+9TPojm
1KOwso0pLZ/O7rUZVey9wt8Of8ZzjyS3Mrs+OYKSB5xRR642R71xn3OygCRCN3uxbgmuy1s90aFv
78Gmx3okBCuRLebT985WU9vCwsnp4Gf2APriY0kPZ1gaqE8XpgL0a6/gM8c1aNmJQDtP7EMiE8jr
XheRedsORByxia3HVNbb+ml7jacbMQkbxfugS60FRTN3xMOEhX7/fPZmAqn1PLe5qfyep9I8DflY
TEoksbUX5WKBqsif6fRyeUOIN8kIQaRKLImGcJcHhRBpCShUVG7VgCN323/g7SzUxHIzztcYXXO8
/Ukhi757FTC9N6nSOVa5iaKhl1fjM6TJhWkJtmhhSbeyu4BQ25Wa9+QhUgkJCLOzjoPPet5XVWLB
vJv1TOeXyt+9Et+p9/g2Zn43+6n1xri9W7FNGuBJ0VFE6bqrVGr7V4mmtAQhPpnt6UkeSkjLvEiK
meREdY+IKfOkOnOATTBWIYCArihhuYUfa8DsSRjQYytjdACIWHoqIdtACGU97ob4+wFC6fRlvSHl
WEPMGC7pQS472sq0nzZZ2nJjTFRQDNyqofUqJFouq9roQ9MhNuqXjWXqBjyeedSXpJvAVn87Uh6G
MpAz/A6PSR+L9RTN70lcLUYWnkyaWf/PhBxHYJYwKLfarypV8jLDAZ3O5TsuuRf89MKtSLXSdyJX
qKrb/pdCZXSdr9laOfbHU1f0uErh3+b961Rr00JEfItI9idP125JOSlB9Z1u2mDtNvBWmz85TR6n
8p1xKsqjFdLMlpWwBfhJp3WYgoY++b1CDPDtkfvmycUiXek0eJAh6LGuPxVWM++8SUUN2ewQgIOV
2Bqr+YHb/RUKQtgxzIIOKNx3A5efbuRu6x7SZd0tmBvZI2j1OcOkDS0gx/deLZanio5PVNqyqsZ8
RreaxqhrUyU2EQ4tVze8o1TvsyKSLz27tlP38C92F3y8x3EkNmsyTO8EjNNYY2MSQXdP209+h8oc
muDSK9n//IlHe44zE34aws+7iVkFWWTYQw7sIA3JaiZ60o73y5E2EaD/88JsjbKaorCQsg/ibV3S
oKKKkOHrbNcSpd2fRJGBi2I+5t3ghLBOvJX/YRPQ6Fl6kb9fkBVwLVA7oWfMLz0aT4nhZDW5bGPT
yB0vmnd4HLfDBlah1Yo3NbCcM2o+ELl3pCYXGCe073ufSimzg+4aR9ltuB+qgMY6yW0S42otka8K
aua3LAJjvhOsn3kNoVGHd7cMVaWtm08IMlFJH9olLBNI4pkMhsahYyO8yEKxa8ToRuC1zqy0muzR
4GmBKaSSp93d35x3cF0dJJ/Csnp7EYeeu7Nvc6TUfQ1nd57aMBR6uROwuMi6Ou0pKpkgXL0L1Lve
65/EfFF3r94dofZEOxcFtOEwX+epQFDxpxze6Nb7PauRicl7zk+HyKIRnBmLeNab4HdO18D28MkC
/1qmD3P95X03ft3kB7fQa8Eelb3Y2u7OgSAXwf+FAhZdwJd4wT/aXqUl1CurdAzW8/KN2CKLnVt6
Pb0nWmvxAfteKZVKzQYlWuX/X8GrduUuy7KJM8pVstXmTqizYCtEBD6dAXuM/1f0oGc2ifEEOiL+
EK9QxE6wFcXg1pCfWC0xhOKOAxyJ9/mgQHQjVTC3HYRWZI1BmRIPllsB01aIXy0LeQycx2KVxMXT
7x7KmJrOhw+CXU30nYFBOFr6lLLbXwfg5q4iaUzSp0b3ty0iZH6snFew2AdYjZ6wWV7Z8htEKk78
gWuwH4QWqdv65AXZbXCdFMEqZmtrdVkaFDAz8Po44tIwOzqHC1NTiRPXt39ZPGnISyA3Oxg0lWoo
4quY/5QfghLhjantHGf4hYKxNzlyU+PTJpyOfjI/N1FbBMPC+aoDITA85zDkgx66VrpecO2WCPZJ
AGTlwicWWR1ikEtkwoyK/4rBSfmeblOFMop+CefiZSPWJEIMG/S7oNfvXocNK8gZwtwfmlAGeG/8
SdewCAEEY7EJxWthD3JUvUsYdlT5nVnvvzacgFqiE/wU8uZ7zRsl0p5xjQ==
`protect end_protected
|
-------------------------------------------------------------------------------
-- Model: dc voltage source
--
-- Author: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <[email protected]>
-- Date: 21.06.2011
-- Library: kvl in hAMSter
-------------------------------------------------------------------------------
-- ID: v_dc.vhd
-- ver. 1.0
-- status: OK
-------------------------------------------------------------------------------
library ieee;
use work.electromagnetic_system.all;
use work.all;
use ieee.math_real.all;
entity v_dc is
generic (dc_value:real); -- parameters
port (terminal p,n:electrical); -- pins
end entity v_dc;
architecture basic of v_dc is
quantity v across i through p to n;
begin
v == - dc_value;
end architecture basic;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Model: dc voltage source
--
-- Author: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <[email protected]>
-- Date: 21.06.2011
-- Library: kvl in hAMSter
-------------------------------------------------------------------------------
-- ID: v_dc.vhd
-- ver. 1.0
-- status: OK
-------------------------------------------------------------------------------
library ieee;
use work.electromagnetic_system.all;
use work.all;
use ieee.math_real.all;
entity v_dc is
generic (dc_value:real); -- parameters
port (terminal p,n:electrical); -- pins
end entity v_dc;
architecture basic of v_dc is
quantity v across i through p to n;
begin
v == - dc_value;
end architecture basic;
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
library alib;
use alib.acomp;
entity tb is
end;
architecture arch of tb is
signal clk: std_logic := '0';
signal lclk: std_ulogic;
signal stop: boolean := false;
signal lclk_count: integer := 0;
component acomp is
port (x: in std_ulogic; y: out std_ulogic);
end component;
begin
clk <= not clk after 10 ns when (not stop) else '0';
ainst: acomp
port map (clk, lclk);
process (lclk) is
begin
if rising_edge(lclk) then
lclk_count <= lclk_count + 1;
end if;
end process;
process is
begin
report "start test";
wait for 1 ms;
report "end test";
report "lclk_count = " & integer'image(lclk_count);
assert lclk_count > 20000 report "test failed";
if lclk_count > 20000 then report "test passed"; end if;
stop <= true;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library alib;
use alib.acomp;
entity tb is
end;
architecture arch of tb is
signal clk: std_logic := '0';
signal lclk: std_ulogic;
signal stop: boolean := false;
signal lclk_count: integer := 0;
component acomp is
port (x: in std_ulogic; y: out std_ulogic);
end component;
begin
clk <= not clk after 10 ns when (not stop) else '0';
ainst: acomp
port map (clk, lclk);
process (lclk) is
begin
if rising_edge(lclk) then
lclk_count <= lclk_count + 1;
end if;
end process;
process is
begin
report "start test";
wait for 1 ms;
report "end test";
report "lclk_count = " & integer'image(lclk_count);
assert lclk_count > 20000 report "test failed";
if lclk_count > 20000 then report "test passed"; end if;
stop <= true;
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity globalcontrolreg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadgcr: in STD_LOGIC;
ctrclear: out STD_LOGIC;
ctrlatch: out STD_LOGIC;
pwmclear: out STD_LOGIC;
irqclear: out STD_LOGIC;
reloadwd: out STD_LOGIC
);
end globalcontrolreg;
architecture behavioral of globalcontrolreg is
signal ctrclearreg: STD_LOGIC;
signal ctrlatchreg: STD_LOGIC;
signal pwmclearreg: STD_LOGIC;
signal irqclearreg: STD_LOGIC;
signal reloadwdreg: STD_LOGIC;
begin
agcrreg: process (clk,
ibus,
reset,
loadgcr,
ctrclearreg,
ctrlatchreg,
pwmclearreg,
irqclearreg,
reloadwdreg
)
begin
if clk'event and clk = '1' then
if loadgcr = '1' then
ctrclearreg <= ibus(0);
ctrlatchreg <= ibus(1);
pwmclearreg <= ibus(2);
irqclearreg <= ibus(3);
reloadwdreg <= ibus(4);
end if;
if ctrclearreg = '1' then
ctrclearreg <= '0';
end if;
if ctrlatchreg = '1' then
ctrlatchreg <= '0';
end if;
if pwmclearreg = '1' then
pwmclearreg <= '0';
end if;
if irqclearreg = '1' then
irqclearreg <= '0';
end if;
if reloadwdreg = '1' then
reloadwdreg <= '0';
end if;
end if;
if ctrclearreg = '1' or reset = '1' then
ctrclear <= '1';
else
ctrclear <= '0';
end if;
if ctrlatchreg = '1' or reset = '1' then
ctrlatch <= '1';
else
ctrlatch <= '0';
end if;
if pwmclearreg = '1' or reset = '1' then
pwmclear <= '1';
else
pwmclear <= '0';
end if;
if irqclearreg = '1' or reset = '1' then
irqclear <= '1';
else
irqclear <= '0';
end if;
if reloadwdreg = '1' or reset = '1' then
reloadwd <= '1';
else
reloadwd <= '0';
end if;
end process;
end behavioral;
|
-- Copyright (c) 2013, Jahanzeb Ahmad
-- All rights reserved.
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation and/or
-- other materials provided with the distribution.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-- * http://opensource.org/licenses/MIT
-- * http://copyfree.org/licenses/mit/license.txt
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity image_buffer is
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3200;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port(
no_frame_read : out std_logic; --debug signal
write_img_s : out std_logic; --debug signal
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
img_in : in std_logic_vector(23 downto 0);
img_in_en : in std_logic;
img_out : out std_logic_vector(23 downto 0);
img_out_en : out std_logic;
jpg_fifo_afull : in std_logic;
raw_fifo_afull : in std_logic;
clk : in std_logic;
clk_out : out std_logic;
jpg_or_raw : in std_logic; -- 1 = jpg, 0 = raw
vsync : in std_logic;
jpg_busy : in std_logic;
jpg_done : in std_logic;
jpg_start : out std_logic;
resX : in std_logic_vector(15 downto 0);
resY : in std_logic_vector(15 downto 0);
to_send : out std_logic_vector(23 downto 0);
rst : in std_logic;
uvc_rst : in std_logic;
error : out std_logic
);
end image_buffer;
architecture rtl of image_buffer is
component ddr2ram
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3200;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
clk_img : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic
);
end component;
COMPONENT rgbfifo
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-------------------------------------------------------------------------------
signal c3_calib_done : std_logic;
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_p2_cmd_en : std_logic;
signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p2_cmd_empty : std_logic;
signal c3_p2_cmd_full : std_logic;
signal c3_p2_rd_en : std_logic;
signal c3_p2_rd_data : std_logic_vector(31 downto 0);
signal c3_p2_rd_full : std_logic;
signal c3_p2_rd_empty : std_logic;
signal c3_p2_rd_count : std_logic_vector(6 downto 0);
signal c3_p2_rd_overflow : std_logic;
signal c3_p2_rd_error : std_logic;
signal c3_p3_cmd_en : std_logic;
signal c3_p3_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p3_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p3_cmd_empty : std_logic;
signal c3_p3_cmd_full : std_logic;
signal c3_p3_wr_en : std_logic;
signal c3_p3_wr_mask : std_logic_vector(3 downto 0):="0000";
signal c3_p3_wr_data : std_logic_vector(31 downto 0);
signal c3_p3_wr_full : std_logic;
signal c3_p3_wr_empty : std_logic;
signal c3_p3_wr_count : std_logic_vector(6 downto 0);
signal c3_p3_wr_underrun : std_logic;
signal c3_p3_wr_error : std_logic;
signal wrAdd : std_logic_vector(29 downto 0);
signal wrAdd_q : std_logic_vector(29 downto 0);
signal rdAdd : std_logic_vector(29 downto 0);
signal counter_rd : std_logic_vector(5 downto 0);
signal counter_wr : std_logic_vector(5 downto 0);
type write_states is (write_cmd,reset,write_data,write_wait,write_cmd_skip);
signal wr_state : write_states;
type read_states is (read_cmd,reset,read_data,read_wait,wait_data);
signal rd_state : read_states;
type rd_wr_states is (s_reset,wait_for_start1,wait_for_line_ready,wait_for_busy,wait_for_done,wait_for_write_finish,wait_for_read_finish);
signal rd_wr_state : rd_wr_states;
-- fifo signals
signal wr_en : std_logic;
signal rd_en : std_logic;
signal fullr : std_logic;
signal almost_fullr : std_logic;
signal emptyr : std_logic;
signal almost_emptyr : std_logic;
signal validr : std_logic;
signal dinr : std_logic_vector(7 downto 0);
signal doutr : std_logic_vector(7 downto 0);
signal fullg : std_logic;
signal almost_fullg : std_logic;
signal emptyg : std_logic;
signal almost_emptyg : std_logic;
signal validg : std_logic;
signal ding : std_logic_vector(7 downto 0);
signal doutg : std_logic_vector(7 downto 0);
signal fullb : std_logic;
signal almost_fullb : std_logic;
signal emptyb : std_logic;
signal almost_emptyb : std_logic;
signal validb : std_logic;
signal dinb : std_logic_vector(7 downto 0);
signal doutb : std_logic_vector(7 downto 0);
signal clk_img : std_logic;
signal write_img : std_logic;
signal read_img : std_logic;
signal vsync_rising_edge : std_logic;
signal vsync_q : std_logic;
signal line_ready : std_logic;
begin -- Architecture
process(uvc_rst, clk_img)
begin
if uvc_rst = '1' then
rd_wr_state <= s_reset;
write_img <= '0';
read_img <= '0';
jpg_start <= '0';
elsif rising_edge(clk_img) then
vsync_rising_edge <= ((vsync xor vsync_q) and vsync) ;
vsync_q <= vsync;
case rd_wr_state is
when s_reset =>
write_img <= '0';
read_img <= '0';
jpg_start <= '0';
rd_wr_state <= wait_for_start1;
-- Wait for start of frame
when wait_for_start1 =>
if vsync_rising_edge = '1' then
rd_wr_state <= wait_for_line_ready;
write_img <= '1';
end if;
-- Wait for 8 line to be written
when wait_for_line_ready =>
if line_ready = '1' then
if jpg_or_raw = '1' then
rd_wr_state <= wait_for_busy;
jpg_start <= '1';
wrAdd_q <= (others=>'1');
else
rd_wr_state <= wait_for_write_finish;
end if;
end if;
-- Wait for encoder to start
when wait_for_busy =>
if jpg_busy = '1' then
rd_wr_state <= wait_for_write_finish;
jpg_start <= '0';
end if;
-- Wait for end of frame
when wait_for_write_finish =>
read_img <= '1';
if vsync_rising_edge = '1' then
wrAdd_q <= wrAdd;
to_send <= resX(10 downto 0)*resY(10 downto 0)*"10";
write_img <= '0';
rd_wr_state <= wait_for_read_finish;
end if;
when wait_for_read_finish =>
if wrAdd_q = rdAdd then
read_img <= '0';
if jpg_or_raw = '1' then
rd_wr_state <= wait_for_done;
else
rd_wr_state <= wait_for_start1;
end if;
end if;
when wait_for_done =>
if jpg_done = '1' then
rd_wr_state <= wait_for_start1;
end if;
when others =>
rd_wr_state <= s_reset;
end case;
end if; -- uvc_rst -- clk
end process;
-- Controls the no_frame_read signal
debug:process(clk_img,rst)
begin
if rst = '1' then
no_frame_read <= '0';
elsif rising_edge(clk_img) then
if rd_wr_state = wait_for_line_ready then
no_frame_read <= '1';
elsif rd_wr_state = wait_for_start1 then
no_frame_read <= '0';
end if;
end if;
end process;
-- debug signal
write_img_s <= write_img;
clk_out <= clk_img;
clk_img <= c3_clk0;
-----------------------------------------------------------------
-- ram read
img_out <= c3_p2_rd_data(23 downto 0);
ramread : process(rst,clk_img)
begin
if rst = '1' then
c3_p2_cmd_en <= '0'; -- stop read command fifo
c3_p2_rd_en <= '0'; -- read data fifo
img_out_en <= '0';
counter_rd <= (others => '0');
rdAdd <= "000000000000000000000000000000";
c3_p2_cmd_byte_addr <= (others => '0');
rd_state <= reset;
elsif rising_edge(clk_img) then -- read_img
c3_p2_cmd_instr <= "001"; -- prepare to read
c3_p2_cmd_bl <= "111111"; --total words to read (must be -1 from total)
c3_p2_cmd_en <= '0'; -- stop read command fifo
c3_p2_rd_en <= '0'; -- read data fifo
img_out_en <= '0';
case rd_state is
when reset =>
counter_rd <= (others => '0');
rdAdd <= (others => '0');
if (c3_calib_done = '1' ) then
rd_state <= read_cmd;
end if;
when read_cmd =>
if read_img = '1' then
rd_state <= wait_data;
c3_p2_cmd_byte_addr <= rdAdd; -- address increments in 4
c3_p2_cmd_en <= '1';
rdAdd <= rdAdd +256;
else
rdAdd <= (others => '0');
-- c3_p2_rd_en <= not c3_p2_rd_empty;
end if;
when wait_data =>
if c3_p2_rd_full = '1' then
rd_state <= read_data;
counter_rd <= (others => '0');
end if;
when read_data =>
if (jpg_fifo_afull = '0' and jpg_or_raw = '1') or (raw_fifo_afull = '0' and jpg_or_raw = '0') then
img_out_en <= '1';
c3_p2_rd_en <= '1';
counter_rd <= counter_rd +1;
if counter_rd = 63 then
rd_state <= read_cmd;
end if;
end if;
when others =>
rd_state <= reset;
end case;
end if; -- clk
end process;
-- ram write
ramwrite: process(rst,clk_img)
begin
if rst = '1' then
wrAdd <= "000000000000000000000000000000";
counter_wr <= (others => '0');
c3_p3_cmd_byte_addr <= (others => '0');
c3_p3_cmd_en <= '0'; -- stop Write to command FIFO
c3_p3_wr_en <= '0'; -- write data fifo
rd_en <= '0';
c3_p3_cmd_instr <= "000"; -- prepare to write
c3_p3_cmd_bl <= "111111"; --total words to write
line_ready <= '0';
wr_state <= reset;
elsif falling_edge(clk_img) then
c3_p3_cmd_instr <= "000"; -- prepare to write
c3_p3_cmd_bl <= "111111"; --total words to write
c3_p3_cmd_en <= '0'; -- stop Write to command FIFO
c3_p3_wr_en <= '0'; -- write data fifo
rd_en <= '0';
case wr_state is
when reset =>
wrAdd <= (others => '0');
counter_wr <= (others => '0');
line_ready <= '0';
if (c3_calib_done = '1' ) then
wr_state <= write_data;
end if;
when write_data =>
if write_img = '1' then
if emptyr = '0' and validr = '1' and emptyg = '0' and validg = '1' and emptyb = '0' and validb = '1' then
rd_en <= '1';
c3_p3_wr_en <= '1';
c3_p3_wr_data <= ("00000000" & doutb & doutg & doutr );
counter_wr <= counter_wr +1;
if counter_wr = 63 then
wr_state <= write_cmd_skip;
counter_wr <= (others => '0');
end if;
end if;
else
wrAdd <= (others => '0');
-- c3_p3_cmd_en <= not c3_p3_wr_empty;
rd_en <= not emptyb;
end if;
when write_cmd_skip =>
if c3_p3_wr_full = '1' then
wr_state <= write_cmd;
end if;
when write_cmd =>
wr_state <= write_wait;
c3_p3_cmd_instr <= "000"; -- prepare to write
c3_p3_cmd_bl <= "111111"; --total words to write
c3_p3_cmd_byte_addr <= wrAdd; -- address
c3_p3_cmd_en <= '1'; --Write to command FIFO
wrAdd <= wrAdd +256;
when write_wait =>
-- Checks whether 8 lines have been written
if conv_integer(unsigned(wrAdd)) > conv_integer(unsigned(resX * ("100000"))) then
line_ready <= '1';
end if;
if c3_p3_wr_empty = '1' then
wr_state <= write_data;
end if;
when others =>
wr_state <= reset;
end case;
end if; -- clk
end process ramwrite;
-- fifo write
fifowrite: process(rst,clk_img) -- additional buffering
begin
if rst = '1' then
wr_en <= '0';
dinr <= (others => '0');
ding <= (others => '0');
dinb <= (others => '0');
elsif falling_edge(clk_img) then
wr_en <= '0';
dinr <= (others => '0');
ding <= (others => '0');
dinb <= (others => '0');
if write_img = '1' and img_in_en = '1' then
dinb <= img_in(23 downto 16);
ding <= img_in(15 downto 8);
dinr <= img_in(7 downto 0);
wr_en <= '1';
end if;
end if; -- rst clk
end process fifowrite;
rgbfifo_r : rgbfifo
PORT MAP (
clk => clk_img,
rst => rst,
din => dinr,
wr_en => wr_en,
rd_en => rd_en,
dout => doutr,
full => fullr,
almost_full => almost_fullr,
empty => emptyr,
almost_empty => almost_emptyr,
valid => validr
);
rgbfifo_g : rgbfifo
PORT MAP (
clk => clk_img,
rst => rst,
din => ding,
wr_en => wr_en,
rd_en => rd_en,
dout => doutg,
full => fullg,
almost_full => almost_fullg,
empty => emptyg,
almost_empty => almost_emptyg,
valid => validg
);
rgbfifo_b : rgbfifo
PORT MAP (
clk => clk_img,
rst => rst,
din => dinb,
wr_en => wr_en,
rd_en => rd_en,
dout => doutb,
full => fullb,
almost_full => almost_fullb,
empty => emptyb,
almost_empty => almost_emptyb,
valid => validb
);
---------------------------------------------------
ramComp : ddr2ram
generic map (
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C3_SIMULATION => C3_SIMULATION,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH
)
port map (
c3_sys_clk => clk,
c3_sys_rst_i => rst,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
-- clk_img => clk_img,
-- read port
c3_p2_cmd_clk => clk_img,
c3_p2_cmd_en => c3_p2_cmd_en,
c3_p2_cmd_instr => c3_p2_cmd_instr,
c3_p2_cmd_bl => c3_p2_cmd_bl,
c3_p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
c3_p2_cmd_empty => c3_p2_cmd_empty,
c3_p2_cmd_full => c3_p2_cmd_full,
c3_p2_rd_clk => clk_img,
c3_p2_rd_en => c3_p2_rd_en,
c3_p2_rd_data => c3_p2_rd_data,
c3_p2_rd_full => c3_p2_rd_full,
c3_p2_rd_empty => c3_p2_rd_empty,
c3_p2_rd_count => c3_p2_rd_count,
c3_p2_rd_overflow => c3_p2_rd_overflow,
c3_p2_rd_error => c3_p2_rd_error,
-- write port
c3_p3_cmd_clk => clk_img,
c3_p3_cmd_en => c3_p3_cmd_en,
c3_p3_cmd_instr => c3_p3_cmd_instr,
c3_p3_cmd_bl => c3_p3_cmd_bl,
c3_p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
c3_p3_cmd_empty => c3_p3_cmd_empty,
c3_p3_cmd_full => c3_p3_cmd_full,
c3_p3_wr_clk => clk_img,
c3_p3_wr_en => c3_p3_wr_en,
c3_p3_wr_mask => c3_p3_wr_mask,
c3_p3_wr_data => c3_p3_wr_data,
c3_p3_wr_full => c3_p3_wr_full,
c3_p3_wr_empty => c3_p3_wr_empty,
c3_p3_wr_count => c3_p3_wr_count,
c3_p3_wr_underrun => c3_p3_wr_underrun,
c3_p3_wr_error => c3_p3_wr_error
);
end rtl;
|
-- Copyright (c) 2013, Jahanzeb Ahmad
-- All rights reserved.
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation and/or
-- other materials provided with the distribution.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-- * http://opensource.org/licenses/MIT
-- * http://copyfree.org/licenses/mit/license.txt
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity image_buffer is
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3200;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port(
no_frame_read : out std_logic; --debug signal
write_img_s : out std_logic; --debug signal
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
img_in : in std_logic_vector(23 downto 0);
img_in_en : in std_logic;
img_out : out std_logic_vector(23 downto 0);
img_out_en : out std_logic;
jpg_fifo_afull : in std_logic;
raw_fifo_afull : in std_logic;
clk : in std_logic;
clk_out : out std_logic;
jpg_or_raw : in std_logic; -- 1 = jpg, 0 = raw
vsync : in std_logic;
jpg_busy : in std_logic;
jpg_done : in std_logic;
jpg_start : out std_logic;
resX : in std_logic_vector(15 downto 0);
resY : in std_logic_vector(15 downto 0);
to_send : out std_logic_vector(23 downto 0);
rst : in std_logic;
uvc_rst : in std_logic;
error : out std_logic
);
end image_buffer;
architecture rtl of image_buffer is
component ddr2ram
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3200;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
clk_img : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic
);
end component;
COMPONENT rgbfifo
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-------------------------------------------------------------------------------
signal c3_calib_done : std_logic;
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_p2_cmd_en : std_logic;
signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p2_cmd_empty : std_logic;
signal c3_p2_cmd_full : std_logic;
signal c3_p2_rd_en : std_logic;
signal c3_p2_rd_data : std_logic_vector(31 downto 0);
signal c3_p2_rd_full : std_logic;
signal c3_p2_rd_empty : std_logic;
signal c3_p2_rd_count : std_logic_vector(6 downto 0);
signal c3_p2_rd_overflow : std_logic;
signal c3_p2_rd_error : std_logic;
signal c3_p3_cmd_en : std_logic;
signal c3_p3_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p3_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p3_cmd_empty : std_logic;
signal c3_p3_cmd_full : std_logic;
signal c3_p3_wr_en : std_logic;
signal c3_p3_wr_mask : std_logic_vector(3 downto 0):="0000";
signal c3_p3_wr_data : std_logic_vector(31 downto 0);
signal c3_p3_wr_full : std_logic;
signal c3_p3_wr_empty : std_logic;
signal c3_p3_wr_count : std_logic_vector(6 downto 0);
signal c3_p3_wr_underrun : std_logic;
signal c3_p3_wr_error : std_logic;
signal wrAdd : std_logic_vector(29 downto 0);
signal wrAdd_q : std_logic_vector(29 downto 0);
signal rdAdd : std_logic_vector(29 downto 0);
signal counter_rd : std_logic_vector(5 downto 0);
signal counter_wr : std_logic_vector(5 downto 0);
type write_states is (write_cmd,reset,write_data,write_wait,write_cmd_skip);
signal wr_state : write_states;
type read_states is (read_cmd,reset,read_data,read_wait,wait_data);
signal rd_state : read_states;
type rd_wr_states is (s_reset,wait_for_start1,wait_for_line_ready,wait_for_busy,wait_for_done,wait_for_write_finish,wait_for_read_finish);
signal rd_wr_state : rd_wr_states;
-- fifo signals
signal wr_en : std_logic;
signal rd_en : std_logic;
signal fullr : std_logic;
signal almost_fullr : std_logic;
signal emptyr : std_logic;
signal almost_emptyr : std_logic;
signal validr : std_logic;
signal dinr : std_logic_vector(7 downto 0);
signal doutr : std_logic_vector(7 downto 0);
signal fullg : std_logic;
signal almost_fullg : std_logic;
signal emptyg : std_logic;
signal almost_emptyg : std_logic;
signal validg : std_logic;
signal ding : std_logic_vector(7 downto 0);
signal doutg : std_logic_vector(7 downto 0);
signal fullb : std_logic;
signal almost_fullb : std_logic;
signal emptyb : std_logic;
signal almost_emptyb : std_logic;
signal validb : std_logic;
signal dinb : std_logic_vector(7 downto 0);
signal doutb : std_logic_vector(7 downto 0);
signal clk_img : std_logic;
signal write_img : std_logic;
signal read_img : std_logic;
signal vsync_rising_edge : std_logic;
signal vsync_q : std_logic;
signal line_ready : std_logic;
begin -- Architecture
process(uvc_rst, clk_img)
begin
if uvc_rst = '1' then
rd_wr_state <= s_reset;
write_img <= '0';
read_img <= '0';
jpg_start <= '0';
elsif rising_edge(clk_img) then
vsync_rising_edge <= ((vsync xor vsync_q) and vsync) ;
vsync_q <= vsync;
case rd_wr_state is
when s_reset =>
write_img <= '0';
read_img <= '0';
jpg_start <= '0';
rd_wr_state <= wait_for_start1;
-- Wait for start of frame
when wait_for_start1 =>
if vsync_rising_edge = '1' then
rd_wr_state <= wait_for_line_ready;
write_img <= '1';
end if;
-- Wait for 8 line to be written
when wait_for_line_ready =>
if line_ready = '1' then
if jpg_or_raw = '1' then
rd_wr_state <= wait_for_busy;
jpg_start <= '1';
wrAdd_q <= (others=>'1');
else
rd_wr_state <= wait_for_write_finish;
end if;
end if;
-- Wait for encoder to start
when wait_for_busy =>
if jpg_busy = '1' then
rd_wr_state <= wait_for_write_finish;
jpg_start <= '0';
end if;
-- Wait for end of frame
when wait_for_write_finish =>
read_img <= '1';
if vsync_rising_edge = '1' then
wrAdd_q <= wrAdd;
to_send <= resX(10 downto 0)*resY(10 downto 0)*"10";
write_img <= '0';
rd_wr_state <= wait_for_read_finish;
end if;
when wait_for_read_finish =>
if wrAdd_q = rdAdd then
read_img <= '0';
if jpg_or_raw = '1' then
rd_wr_state <= wait_for_done;
else
rd_wr_state <= wait_for_start1;
end if;
end if;
when wait_for_done =>
if jpg_done = '1' then
rd_wr_state <= wait_for_start1;
end if;
when others =>
rd_wr_state <= s_reset;
end case;
end if; -- uvc_rst -- clk
end process;
-- Controls the no_frame_read signal
debug:process(clk_img,rst)
begin
if rst = '1' then
no_frame_read <= '0';
elsif rising_edge(clk_img) then
if rd_wr_state = wait_for_line_ready then
no_frame_read <= '1';
elsif rd_wr_state = wait_for_start1 then
no_frame_read <= '0';
end if;
end if;
end process;
-- debug signal
write_img_s <= write_img;
clk_out <= clk_img;
clk_img <= c3_clk0;
-----------------------------------------------------------------
-- ram read
img_out <= c3_p2_rd_data(23 downto 0);
ramread : process(rst,clk_img)
begin
if rst = '1' then
c3_p2_cmd_en <= '0'; -- stop read command fifo
c3_p2_rd_en <= '0'; -- read data fifo
img_out_en <= '0';
counter_rd <= (others => '0');
rdAdd <= "000000000000000000000000000000";
c3_p2_cmd_byte_addr <= (others => '0');
rd_state <= reset;
elsif rising_edge(clk_img) then -- read_img
c3_p2_cmd_instr <= "001"; -- prepare to read
c3_p2_cmd_bl <= "111111"; --total words to read (must be -1 from total)
c3_p2_cmd_en <= '0'; -- stop read command fifo
c3_p2_rd_en <= '0'; -- read data fifo
img_out_en <= '0';
case rd_state is
when reset =>
counter_rd <= (others => '0');
rdAdd <= (others => '0');
if (c3_calib_done = '1' ) then
rd_state <= read_cmd;
end if;
when read_cmd =>
if read_img = '1' then
rd_state <= wait_data;
c3_p2_cmd_byte_addr <= rdAdd; -- address increments in 4
c3_p2_cmd_en <= '1';
rdAdd <= rdAdd +256;
else
rdAdd <= (others => '0');
-- c3_p2_rd_en <= not c3_p2_rd_empty;
end if;
when wait_data =>
if c3_p2_rd_full = '1' then
rd_state <= read_data;
counter_rd <= (others => '0');
end if;
when read_data =>
if (jpg_fifo_afull = '0' and jpg_or_raw = '1') or (raw_fifo_afull = '0' and jpg_or_raw = '0') then
img_out_en <= '1';
c3_p2_rd_en <= '1';
counter_rd <= counter_rd +1;
if counter_rd = 63 then
rd_state <= read_cmd;
end if;
end if;
when others =>
rd_state <= reset;
end case;
end if; -- clk
end process;
-- ram write
ramwrite: process(rst,clk_img)
begin
if rst = '1' then
wrAdd <= "000000000000000000000000000000";
counter_wr <= (others => '0');
c3_p3_cmd_byte_addr <= (others => '0');
c3_p3_cmd_en <= '0'; -- stop Write to command FIFO
c3_p3_wr_en <= '0'; -- write data fifo
rd_en <= '0';
c3_p3_cmd_instr <= "000"; -- prepare to write
c3_p3_cmd_bl <= "111111"; --total words to write
line_ready <= '0';
wr_state <= reset;
elsif falling_edge(clk_img) then
c3_p3_cmd_instr <= "000"; -- prepare to write
c3_p3_cmd_bl <= "111111"; --total words to write
c3_p3_cmd_en <= '0'; -- stop Write to command FIFO
c3_p3_wr_en <= '0'; -- write data fifo
rd_en <= '0';
case wr_state is
when reset =>
wrAdd <= (others => '0');
counter_wr <= (others => '0');
line_ready <= '0';
if (c3_calib_done = '1' ) then
wr_state <= write_data;
end if;
when write_data =>
if write_img = '1' then
if emptyr = '0' and validr = '1' and emptyg = '0' and validg = '1' and emptyb = '0' and validb = '1' then
rd_en <= '1';
c3_p3_wr_en <= '1';
c3_p3_wr_data <= ("00000000" & doutb & doutg & doutr );
counter_wr <= counter_wr +1;
if counter_wr = 63 then
wr_state <= write_cmd_skip;
counter_wr <= (others => '0');
end if;
end if;
else
wrAdd <= (others => '0');
-- c3_p3_cmd_en <= not c3_p3_wr_empty;
rd_en <= not emptyb;
end if;
when write_cmd_skip =>
if c3_p3_wr_full = '1' then
wr_state <= write_cmd;
end if;
when write_cmd =>
wr_state <= write_wait;
c3_p3_cmd_instr <= "000"; -- prepare to write
c3_p3_cmd_bl <= "111111"; --total words to write
c3_p3_cmd_byte_addr <= wrAdd; -- address
c3_p3_cmd_en <= '1'; --Write to command FIFO
wrAdd <= wrAdd +256;
when write_wait =>
-- Checks whether 8 lines have been written
if conv_integer(unsigned(wrAdd)) > conv_integer(unsigned(resX * ("100000"))) then
line_ready <= '1';
end if;
if c3_p3_wr_empty = '1' then
wr_state <= write_data;
end if;
when others =>
wr_state <= reset;
end case;
end if; -- clk
end process ramwrite;
-- fifo write
fifowrite: process(rst,clk_img) -- additional buffering
begin
if rst = '1' then
wr_en <= '0';
dinr <= (others => '0');
ding <= (others => '0');
dinb <= (others => '0');
elsif falling_edge(clk_img) then
wr_en <= '0';
dinr <= (others => '0');
ding <= (others => '0');
dinb <= (others => '0');
if write_img = '1' and img_in_en = '1' then
dinb <= img_in(23 downto 16);
ding <= img_in(15 downto 8);
dinr <= img_in(7 downto 0);
wr_en <= '1';
end if;
end if; -- rst clk
end process fifowrite;
rgbfifo_r : rgbfifo
PORT MAP (
clk => clk_img,
rst => rst,
din => dinr,
wr_en => wr_en,
rd_en => rd_en,
dout => doutr,
full => fullr,
almost_full => almost_fullr,
empty => emptyr,
almost_empty => almost_emptyr,
valid => validr
);
rgbfifo_g : rgbfifo
PORT MAP (
clk => clk_img,
rst => rst,
din => ding,
wr_en => wr_en,
rd_en => rd_en,
dout => doutg,
full => fullg,
almost_full => almost_fullg,
empty => emptyg,
almost_empty => almost_emptyg,
valid => validg
);
rgbfifo_b : rgbfifo
PORT MAP (
clk => clk_img,
rst => rst,
din => dinb,
wr_en => wr_en,
rd_en => rd_en,
dout => doutb,
full => fullb,
almost_full => almost_fullb,
empty => emptyb,
almost_empty => almost_emptyb,
valid => validb
);
---------------------------------------------------
ramComp : ddr2ram
generic map (
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C3_SIMULATION => C3_SIMULATION,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH
)
port map (
c3_sys_clk => clk,
c3_sys_rst_i => rst,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
-- clk_img => clk_img,
-- read port
c3_p2_cmd_clk => clk_img,
c3_p2_cmd_en => c3_p2_cmd_en,
c3_p2_cmd_instr => c3_p2_cmd_instr,
c3_p2_cmd_bl => c3_p2_cmd_bl,
c3_p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
c3_p2_cmd_empty => c3_p2_cmd_empty,
c3_p2_cmd_full => c3_p2_cmd_full,
c3_p2_rd_clk => clk_img,
c3_p2_rd_en => c3_p2_rd_en,
c3_p2_rd_data => c3_p2_rd_data,
c3_p2_rd_full => c3_p2_rd_full,
c3_p2_rd_empty => c3_p2_rd_empty,
c3_p2_rd_count => c3_p2_rd_count,
c3_p2_rd_overflow => c3_p2_rd_overflow,
c3_p2_rd_error => c3_p2_rd_error,
-- write port
c3_p3_cmd_clk => clk_img,
c3_p3_cmd_en => c3_p3_cmd_en,
c3_p3_cmd_instr => c3_p3_cmd_instr,
c3_p3_cmd_bl => c3_p3_cmd_bl,
c3_p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
c3_p3_cmd_empty => c3_p3_cmd_empty,
c3_p3_cmd_full => c3_p3_cmd_full,
c3_p3_wr_clk => clk_img,
c3_p3_wr_en => c3_p3_wr_en,
c3_p3_wr_mask => c3_p3_wr_mask,
c3_p3_wr_data => c3_p3_wr_data,
c3_p3_wr_full => c3_p3_wr_full,
c3_p3_wr_empty => c3_p3_wr_empty,
c3_p3_wr_count => c3_p3_wr_count,
c3_p3_wr_underrun => c3_p3_wr_underrun,
c3_p3_wr_error => c3_p3_wr_error
);
end rtl;
|
-- Copyright (c) 2013, Jahanzeb Ahmad
-- All rights reserved.
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation and/or
-- other materials provided with the distribution.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-- * http://opensource.org/licenses/MIT
-- * http://copyfree.org/licenses/mit/license.txt
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity image_buffer is
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3200;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port(
no_frame_read : out std_logic; --debug signal
write_img_s : out std_logic; --debug signal
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
img_in : in std_logic_vector(23 downto 0);
img_in_en : in std_logic;
img_out : out std_logic_vector(23 downto 0);
img_out_en : out std_logic;
jpg_fifo_afull : in std_logic;
raw_fifo_afull : in std_logic;
clk : in std_logic;
clk_out : out std_logic;
jpg_or_raw : in std_logic; -- 1 = jpg, 0 = raw
vsync : in std_logic;
jpg_busy : in std_logic;
jpg_done : in std_logic;
jpg_start : out std_logic;
resX : in std_logic_vector(15 downto 0);
resY : in std_logic_vector(15 downto 0);
to_send : out std_logic_vector(23 downto 0);
rst : in std_logic;
uvc_rst : in std_logic;
error : out std_logic
);
end image_buffer;
architecture rtl of image_buffer is
component ddr2ram
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3200;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
clk_img : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic
);
end component;
COMPONENT rgbfifo
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-------------------------------------------------------------------------------
signal c3_calib_done : std_logic;
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_p2_cmd_en : std_logic;
signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p2_cmd_empty : std_logic;
signal c3_p2_cmd_full : std_logic;
signal c3_p2_rd_en : std_logic;
signal c3_p2_rd_data : std_logic_vector(31 downto 0);
signal c3_p2_rd_full : std_logic;
signal c3_p2_rd_empty : std_logic;
signal c3_p2_rd_count : std_logic_vector(6 downto 0);
signal c3_p2_rd_overflow : std_logic;
signal c3_p2_rd_error : std_logic;
signal c3_p3_cmd_en : std_logic;
signal c3_p3_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p3_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p3_cmd_empty : std_logic;
signal c3_p3_cmd_full : std_logic;
signal c3_p3_wr_en : std_logic;
signal c3_p3_wr_mask : std_logic_vector(3 downto 0):="0000";
signal c3_p3_wr_data : std_logic_vector(31 downto 0);
signal c3_p3_wr_full : std_logic;
signal c3_p3_wr_empty : std_logic;
signal c3_p3_wr_count : std_logic_vector(6 downto 0);
signal c3_p3_wr_underrun : std_logic;
signal c3_p3_wr_error : std_logic;
signal wrAdd : std_logic_vector(29 downto 0);
signal wrAdd_q : std_logic_vector(29 downto 0);
signal rdAdd : std_logic_vector(29 downto 0);
signal counter_rd : std_logic_vector(5 downto 0);
signal counter_wr : std_logic_vector(5 downto 0);
type write_states is (write_cmd,reset,write_data,write_wait,write_cmd_skip);
signal wr_state : write_states;
type read_states is (read_cmd,reset,read_data,read_wait,wait_data);
signal rd_state : read_states;
type rd_wr_states is (s_reset,wait_for_start1,wait_for_line_ready,wait_for_busy,wait_for_done,wait_for_write_finish,wait_for_read_finish);
signal rd_wr_state : rd_wr_states;
-- fifo signals
signal wr_en : std_logic;
signal rd_en : std_logic;
signal fullr : std_logic;
signal almost_fullr : std_logic;
signal emptyr : std_logic;
signal almost_emptyr : std_logic;
signal validr : std_logic;
signal dinr : std_logic_vector(7 downto 0);
signal doutr : std_logic_vector(7 downto 0);
signal fullg : std_logic;
signal almost_fullg : std_logic;
signal emptyg : std_logic;
signal almost_emptyg : std_logic;
signal validg : std_logic;
signal ding : std_logic_vector(7 downto 0);
signal doutg : std_logic_vector(7 downto 0);
signal fullb : std_logic;
signal almost_fullb : std_logic;
signal emptyb : std_logic;
signal almost_emptyb : std_logic;
signal validb : std_logic;
signal dinb : std_logic_vector(7 downto 0);
signal doutb : std_logic_vector(7 downto 0);
signal clk_img : std_logic;
signal write_img : std_logic;
signal read_img : std_logic;
signal vsync_rising_edge : std_logic;
signal vsync_q : std_logic;
signal line_ready : std_logic;
begin -- Architecture
process(uvc_rst, clk_img)
begin
if uvc_rst = '1' then
rd_wr_state <= s_reset;
write_img <= '0';
read_img <= '0';
jpg_start <= '0';
elsif rising_edge(clk_img) then
vsync_rising_edge <= ((vsync xor vsync_q) and vsync) ;
vsync_q <= vsync;
case rd_wr_state is
when s_reset =>
write_img <= '0';
read_img <= '0';
jpg_start <= '0';
rd_wr_state <= wait_for_start1;
-- Wait for start of frame
when wait_for_start1 =>
if vsync_rising_edge = '1' then
rd_wr_state <= wait_for_line_ready;
write_img <= '1';
end if;
-- Wait for 8 line to be written
when wait_for_line_ready =>
if line_ready = '1' then
if jpg_or_raw = '1' then
rd_wr_state <= wait_for_busy;
jpg_start <= '1';
wrAdd_q <= (others=>'1');
else
rd_wr_state <= wait_for_write_finish;
end if;
end if;
-- Wait for encoder to start
when wait_for_busy =>
if jpg_busy = '1' then
rd_wr_state <= wait_for_write_finish;
jpg_start <= '0';
end if;
-- Wait for end of frame
when wait_for_write_finish =>
read_img <= '1';
if vsync_rising_edge = '1' then
wrAdd_q <= wrAdd;
to_send <= resX(10 downto 0)*resY(10 downto 0)*"10";
write_img <= '0';
rd_wr_state <= wait_for_read_finish;
end if;
when wait_for_read_finish =>
if wrAdd_q = rdAdd then
read_img <= '0';
if jpg_or_raw = '1' then
rd_wr_state <= wait_for_done;
else
rd_wr_state <= wait_for_start1;
end if;
end if;
when wait_for_done =>
if jpg_done = '1' then
rd_wr_state <= wait_for_start1;
end if;
when others =>
rd_wr_state <= s_reset;
end case;
end if; -- uvc_rst -- clk
end process;
-- Controls the no_frame_read signal
debug:process(clk_img,rst)
begin
if rst = '1' then
no_frame_read <= '0';
elsif rising_edge(clk_img) then
if rd_wr_state = wait_for_line_ready then
no_frame_read <= '1';
elsif rd_wr_state = wait_for_start1 then
no_frame_read <= '0';
end if;
end if;
end process;
-- debug signal
write_img_s <= write_img;
clk_out <= clk_img;
clk_img <= c3_clk0;
-----------------------------------------------------------------
-- ram read
img_out <= c3_p2_rd_data(23 downto 0);
ramread : process(rst,clk_img)
begin
if rst = '1' then
c3_p2_cmd_en <= '0'; -- stop read command fifo
c3_p2_rd_en <= '0'; -- read data fifo
img_out_en <= '0';
counter_rd <= (others => '0');
rdAdd <= "000000000000000000000000000000";
c3_p2_cmd_byte_addr <= (others => '0');
rd_state <= reset;
elsif rising_edge(clk_img) then -- read_img
c3_p2_cmd_instr <= "001"; -- prepare to read
c3_p2_cmd_bl <= "111111"; --total words to read (must be -1 from total)
c3_p2_cmd_en <= '0'; -- stop read command fifo
c3_p2_rd_en <= '0'; -- read data fifo
img_out_en <= '0';
case rd_state is
when reset =>
counter_rd <= (others => '0');
rdAdd <= (others => '0');
if (c3_calib_done = '1' ) then
rd_state <= read_cmd;
end if;
when read_cmd =>
if read_img = '1' then
rd_state <= wait_data;
c3_p2_cmd_byte_addr <= rdAdd; -- address increments in 4
c3_p2_cmd_en <= '1';
rdAdd <= rdAdd +256;
else
rdAdd <= (others => '0');
-- c3_p2_rd_en <= not c3_p2_rd_empty;
end if;
when wait_data =>
if c3_p2_rd_full = '1' then
rd_state <= read_data;
counter_rd <= (others => '0');
end if;
when read_data =>
if (jpg_fifo_afull = '0' and jpg_or_raw = '1') or (raw_fifo_afull = '0' and jpg_or_raw = '0') then
img_out_en <= '1';
c3_p2_rd_en <= '1';
counter_rd <= counter_rd +1;
if counter_rd = 63 then
rd_state <= read_cmd;
end if;
end if;
when others =>
rd_state <= reset;
end case;
end if; -- clk
end process;
-- ram write
ramwrite: process(rst,clk_img)
begin
if rst = '1' then
wrAdd <= "000000000000000000000000000000";
counter_wr <= (others => '0');
c3_p3_cmd_byte_addr <= (others => '0');
c3_p3_cmd_en <= '0'; -- stop Write to command FIFO
c3_p3_wr_en <= '0'; -- write data fifo
rd_en <= '0';
c3_p3_cmd_instr <= "000"; -- prepare to write
c3_p3_cmd_bl <= "111111"; --total words to write
line_ready <= '0';
wr_state <= reset;
elsif falling_edge(clk_img) then
c3_p3_cmd_instr <= "000"; -- prepare to write
c3_p3_cmd_bl <= "111111"; --total words to write
c3_p3_cmd_en <= '0'; -- stop Write to command FIFO
c3_p3_wr_en <= '0'; -- write data fifo
rd_en <= '0';
case wr_state is
when reset =>
wrAdd <= (others => '0');
counter_wr <= (others => '0');
line_ready <= '0';
if (c3_calib_done = '1' ) then
wr_state <= write_data;
end if;
when write_data =>
if write_img = '1' then
if emptyr = '0' and validr = '1' and emptyg = '0' and validg = '1' and emptyb = '0' and validb = '1' then
rd_en <= '1';
c3_p3_wr_en <= '1';
c3_p3_wr_data <= ("00000000" & doutb & doutg & doutr );
counter_wr <= counter_wr +1;
if counter_wr = 63 then
wr_state <= write_cmd_skip;
counter_wr <= (others => '0');
end if;
end if;
else
wrAdd <= (others => '0');
-- c3_p3_cmd_en <= not c3_p3_wr_empty;
rd_en <= not emptyb;
end if;
when write_cmd_skip =>
if c3_p3_wr_full = '1' then
wr_state <= write_cmd;
end if;
when write_cmd =>
wr_state <= write_wait;
c3_p3_cmd_instr <= "000"; -- prepare to write
c3_p3_cmd_bl <= "111111"; --total words to write
c3_p3_cmd_byte_addr <= wrAdd; -- address
c3_p3_cmd_en <= '1'; --Write to command FIFO
wrAdd <= wrAdd +256;
when write_wait =>
-- Checks whether 8 lines have been written
if conv_integer(unsigned(wrAdd)) > conv_integer(unsigned(resX * ("100000"))) then
line_ready <= '1';
end if;
if c3_p3_wr_empty = '1' then
wr_state <= write_data;
end if;
when others =>
wr_state <= reset;
end case;
end if; -- clk
end process ramwrite;
-- fifo write
fifowrite: process(rst,clk_img) -- additional buffering
begin
if rst = '1' then
wr_en <= '0';
dinr <= (others => '0');
ding <= (others => '0');
dinb <= (others => '0');
elsif falling_edge(clk_img) then
wr_en <= '0';
dinr <= (others => '0');
ding <= (others => '0');
dinb <= (others => '0');
if write_img = '1' and img_in_en = '1' then
dinb <= img_in(23 downto 16);
ding <= img_in(15 downto 8);
dinr <= img_in(7 downto 0);
wr_en <= '1';
end if;
end if; -- rst clk
end process fifowrite;
rgbfifo_r : rgbfifo
PORT MAP (
clk => clk_img,
rst => rst,
din => dinr,
wr_en => wr_en,
rd_en => rd_en,
dout => doutr,
full => fullr,
almost_full => almost_fullr,
empty => emptyr,
almost_empty => almost_emptyr,
valid => validr
);
rgbfifo_g : rgbfifo
PORT MAP (
clk => clk_img,
rst => rst,
din => ding,
wr_en => wr_en,
rd_en => rd_en,
dout => doutg,
full => fullg,
almost_full => almost_fullg,
empty => emptyg,
almost_empty => almost_emptyg,
valid => validg
);
rgbfifo_b : rgbfifo
PORT MAP (
clk => clk_img,
rst => rst,
din => dinb,
wr_en => wr_en,
rd_en => rd_en,
dout => doutb,
full => fullb,
almost_full => almost_fullb,
empty => emptyb,
almost_empty => almost_emptyb,
valid => validb
);
---------------------------------------------------
ramComp : ddr2ram
generic map (
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C3_SIMULATION => C3_SIMULATION,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH
)
port map (
c3_sys_clk => clk,
c3_sys_rst_i => rst,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
-- clk_img => clk_img,
-- read port
c3_p2_cmd_clk => clk_img,
c3_p2_cmd_en => c3_p2_cmd_en,
c3_p2_cmd_instr => c3_p2_cmd_instr,
c3_p2_cmd_bl => c3_p2_cmd_bl,
c3_p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
c3_p2_cmd_empty => c3_p2_cmd_empty,
c3_p2_cmd_full => c3_p2_cmd_full,
c3_p2_rd_clk => clk_img,
c3_p2_rd_en => c3_p2_rd_en,
c3_p2_rd_data => c3_p2_rd_data,
c3_p2_rd_full => c3_p2_rd_full,
c3_p2_rd_empty => c3_p2_rd_empty,
c3_p2_rd_count => c3_p2_rd_count,
c3_p2_rd_overflow => c3_p2_rd_overflow,
c3_p2_rd_error => c3_p2_rd_error,
-- write port
c3_p3_cmd_clk => clk_img,
c3_p3_cmd_en => c3_p3_cmd_en,
c3_p3_cmd_instr => c3_p3_cmd_instr,
c3_p3_cmd_bl => c3_p3_cmd_bl,
c3_p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
c3_p3_cmd_empty => c3_p3_cmd_empty,
c3_p3_cmd_full => c3_p3_cmd_full,
c3_p3_wr_clk => clk_img,
c3_p3_wr_en => c3_p3_wr_en,
c3_p3_wr_mask => c3_p3_wr_mask,
c3_p3_wr_data => c3_p3_wr_data,
c3_p3_wr_full => c3_p3_wr_full,
c3_p3_wr_empty => c3_p3_wr_empty,
c3_p3_wr_count => c3_p3_wr_count,
c3_p3_wr_underrun => c3_p3_wr_underrun,
c3_p3_wr_error => c3_p3_wr_error
);
end rtl;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 1;
constant CFG_AHB_MONERR : integer := 1;
constant CFG_AHB_MONWAR : integer := 1;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#02007A#;
constant CFG_ETH_ENL : integer := 16#CC0001#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (200);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (512);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 64;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
|
--------------------------------------------------------------------------------
-- Title : Definitions and Constants for WBB2VME
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_pkg.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 02/02/12
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
--
--
--------------------------------------------------------------------------------
-- Hierarchy:
--
--
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- Revision 1.4 2017/06/13 07:00:14 MMiehling
-- changed vme_acc_type setting for CR/CSR and D32 to be compliant to DMA configuration bits
--
-- Revision 1.3 2014/02/07 17:00:14 MMiehling
-- bugfix: IACK addressing
--
-- Revision 1.2 2012/08/27 12:57:11 MMiehling
-- changed polarity of swapped bit in constants
--
-- Revision 1.1 2012/03/29 10:14:34 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE vme_pkg IS
CONSTANT CONST_VME_REGS : std_logic_vector(6 DOWNTO 0):="1000000";
CONSTANT CONST_VME_IACK : std_logic_vector(6 DOWNTO 0):="0100011";
CONSTANT CONST_VME_A16D16 : std_logic_vector(6 DOWNTO 0):="0100010";
CONSTANT CONST_VME_A16D32 : std_logic_vector(6 DOWNTO 0):="0100110";
CONSTANT CONST_VME_A24D16 : std_logic_vector(6 DOWNTO 0):="0100000";
CONSTANT CONST_VME_A24D32 : std_logic_vector(6 DOWNTO 0):="0100100";
CONSTANT CONST_VME_CRCSR : std_logic_vector(6 DOWNTO 0):="0101000";
CONSTANT CONST_VME_A32D32 : std_logic_vector(6 DOWNTO 0):="0100101";
CONSTANT CONST_VME_A16D16S : std_logic_vector(6 DOWNTO 0):="0000010";
CONSTANT CONST_VME_A16D32S : std_logic_vector(6 DOWNTO 0):="0000110";
CONSTANT CONST_VME_A24D16S : std_logic_vector(6 DOWNTO 0):="0000000";
CONSTANT CONST_VME_A24D32S : std_logic_vector(6 DOWNTO 0):="0000100";
CONSTANT CONST_VME_A32D32S : std_logic_vector(6 DOWNTO 0):="0000101";
CONSTANT CONST_VME_A24D16B : std_logic_vector(6 DOWNTO 0):="0110000";
CONSTANT CONST_VME_A24D32B : std_logic_vector(6 DOWNTO 0):="0110100";
CONSTANT CONST_VME_A32D32B : std_logic_vector(6 DOWNTO 0):="0110101";
CONSTANT CONST_VME_A32D64B : std_logic_vector(6 DOWNTO 0):="0111101";
CONSTANT CONST_VME_A24D16BS : std_logic_vector(6 DOWNTO 0):="0010000";
CONSTANT CONST_VME_A24D32BS : std_logic_vector(6 DOWNTO 0):="0010100";
CONSTANT CONST_VME_A32D32BS : std_logic_vector(6 DOWNTO 0):="0010101";
CONSTANT CONST_VME_A32D64BS : std_logic_vector(6 DOWNTO 0):="0011101";
TYPE io_ctrl_type IS record
d_dir : std_logic; -- external driver control data direction (1: drive to vmebus 0: drive to fpga)
d_oe_n : std_logic; -- external driver control data output enable low active
am_dir : std_logic; -- external driver control address modifier direction (1: drive to vmebus 0: drive to fpga)
am_oe_n : std_logic; -- external driver control address modifier output enable low activ
a_dir : std_logic; -- external driver control address direction (1: drive to vmebus 0: drive to fpga)
a_oe_n : std_logic; -- external driver control address output enable low activ
END record;
TYPE test_vec_type IS record
ato : std_logic; -- arbitration time out
END record;
END vme_pkg;
PACKAGE BODY vme_pkg IS
END;
|
library ieee;
use ieee.std_logic_1164.all;
entity issue2 is
end issue2;
architecture beh of issue2 is
type t_rec is
record
elem : std_logic_vector (3 downto 0);
end record;
function fun (arg : std_logic_vector) return t_rec is
begin
return t_rec'(elem => arg);
end function;
begin
-- wrong length
-- -a accepts
-- -synth error + bug report
assert fun ("000") = fun ("000");
end architecture beh;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: usbhc_net
-- File: usbhc_net.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: USBHC netlist wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity usbhc_net is
generic (
tech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end usbhc_net;
architecture rtl of usbhc_net is
component usbhc_unisim is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end component;
component usbhc_stratixii is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end component;
begin
xil : if (tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e) generate
usbhc0 : usbhc_unisim
generic map(
nports => nports,
ehcgen => ehcgen,
uhcgen => uhcgen,
n_cc => n_cc,
n_pcc => n_pcc,
prr => prr,
portroute1 => portroute1,
portroute2 => portroute2,
endian_conv => endian_conv,
be_regs => be_regs,
be_desc => be_desc,
uhcblo => uhcblo,
bwrd => bwrd,
utm_type => utm_type,
vbusconf => vbusconf,
ramtest => ramtest,
urst_time => urst_time,
oepol => oepol)
port map(
clk => clk,
uclk => uclk,
rst => rst,
ursti => ursti,
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel => ehc_apbsi_psel,
ehc_apbsi_penable => ehc_apbsi_penable,
ehc_apbsi_paddr => ehc_apbsi_paddr,
ehc_apbsi_pwrite => ehc_apbsi_pwrite,
ehc_apbsi_pwdata => ehc_apbsi_pwdata,
ehc_apbsi_testen => ehc_apbsi_testen,
ehc_apbsi_testrst => ehc_apbsi_testrst,
ehc_apbsi_scanen => ehc_apbsi_scanen,
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata => ehc_apbso_prdata,
ehc_apbso_pirq => ehc_apbso_pirq,
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant => ahbmi_hgrant,
ahbmi_hready => ahbmi_hready,
ahbmi_hresp => ahbmi_hresp,
ahbmi_hrdata => ahbmi_hrdata,
ahbmi_hcache => ahbmi_hcache,
ahbmi_testen => ahbmi_testen,
ahbmi_testrst => ahbmi_testrst,
ahbmi_scanen => ahbmi_scanen,
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel => uhc_ahbsi_hsel,
uhc_ahbsi_haddr => uhc_ahbsi_haddr,
uhc_ahbsi_hwrite => uhc_ahbsi_hwrite,
uhc_ahbsi_htrans => uhc_ahbsi_htrans,
uhc_ahbsi_hsize => uhc_ahbsi_hsize,
uhc_ahbsi_hwdata => uhc_ahbsi_hwdata,
uhc_ahbsi_hready => uhc_ahbsi_hready,
uhc_ahbsi_testen => uhc_ahbsi_testen,
uhc_ahbsi_testrst => uhc_ahbsi_testrst,
uhc_ahbsi_scanen => uhc_ahbsi_scanen,
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq => ehc_ahbmo_hbusreq,
ehc_ahbmo_hlock => ehc_ahbmo_hlock,
ehc_ahbmo_htrans => ehc_ahbmo_htrans,
ehc_ahbmo_haddr => ehc_ahbmo_haddr,
ehc_ahbmo_hwrite => ehc_ahbmo_hwrite,
ehc_ahbmo_hsize => ehc_ahbmo_hsize,
ehc_ahbmo_hburst => ehc_ahbmo_hburst,
ehc_ahbmo_hprot => ehc_ahbmo_hprot,
ehc_ahbmo_hwdata => ehc_ahbmo_hwdata,
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq => uhc_ahbmo_hbusreq,
uhc_ahbmo_hlock => uhc_ahbmo_hlock,
uhc_ahbmo_htrans => uhc_ahbmo_htrans,
uhc_ahbmo_haddr => uhc_ahbmo_haddr,
uhc_ahbmo_hwrite => uhc_ahbmo_hwrite,
uhc_ahbmo_hsize => uhc_ahbmo_hsize,
uhc_ahbmo_hburst => uhc_ahbmo_hburst,
uhc_ahbmo_hprot => uhc_ahbmo_hprot,
uhc_ahbmo_hwdata => uhc_ahbmo_hwdata,
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready => uhc_ahbso_hready,
uhc_ahbso_hresp => uhc_ahbso_hresp,
uhc_ahbso_hrdata => uhc_ahbso_hrdata,
uhc_ahbso_hsplit => uhc_ahbso_hsplit,
uhc_ahbso_hcache => uhc_ahbso_hcache,
uhc_ahbso_hirq => uhc_ahbso_hirq,
-- usbhc_out_type_vector unwrapped
xcvrsel => xcvrsel,
termsel => termsel,
suspendm => suspendm,
opmode => opmode,
txvalid => txvalid,
drvvbus => drvvbus,
dataho => dataho,
validho => validho,
host => host,
stp => stp,
datao => datao,
utm_rst => utm_rst,
dctrlo => dctrlo,
-- usbhc_in_type_vector unwrapped
linestate => linestate,
txready => txready,
rxvalid => rxvalid,
rxactive => rxactive,
rxerror => rxerror,
vbusvalid => vbusvalid,
datahi => datahi,
validhi => validhi,
hostdisc => hostdisc,
nxt => nxt,
dir => dir,
datai => datai,
-- EHC transaction buffer signals
mbc20_tb_addr => mbc20_tb_addr,
mbc20_tb_data => mbc20_tb_data,
mbc20_tb_en => mbc20_tb_en,
mbc20_tb_wel => mbc20_tb_wel,
mbc20_tb_weh => mbc20_tb_weh,
tb_mbc20_data => tb_mbc20_data,
pe20_tb_addr => pe20_tb_addr,
pe20_tb_data => pe20_tb_data,
pe20_tb_en => pe20_tb_en,
pe20_tb_wel => pe20_tb_wel,
pe20_tb_weh => pe20_tb_weh,
tb_pe20_data => tb_pe20_data,
-- EHC packet buffer signals
mbc20_pb_addr => mbc20_pb_addr,
mbc20_pb_data => mbc20_pb_data,
mbc20_pb_en => mbc20_pb_en,
mbc20_pb_we => mbc20_pb_we,
pb_mbc20_data => pb_mbc20_data,
sie20_pb_addr => sie20_pb_addr,
sie20_pb_data => sie20_pb_data,
sie20_pb_en => sie20_pb_en,
sie20_pb_we => sie20_pb_we,
pb_sie20_data => pb_sie20_data,
-- UHC packet buffer signals
sie11_pb_addr => sie11_pb_addr,
sie11_pb_data => sie11_pb_data,
sie11_pb_en => sie11_pb_en,
sie11_pb_we => sie11_pb_we,
pb_sie11_data => pb_sie11_data,
mbc11_pb_addr => mbc11_pb_addr,
mbc11_pb_data => mbc11_pb_data,
mbc11_pb_en => mbc11_pb_en,
mbc11_pb_we => mbc11_pb_we,
pb_mbc11_data => pb_mbc11_data,
bufsel => bufsel);
end generate;
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = cyclone3) generate
usbhc0 : usbhc_stratixii
generic map(
nports => nports,
ehcgen => ehcgen,
uhcgen => uhcgen,
n_cc => n_cc,
n_pcc => n_pcc,
prr => prr,
portroute1 => portroute1,
portroute2 => portroute2,
endian_conv => endian_conv,
be_regs => be_regs,
be_desc => be_desc,
uhcblo => uhcblo,
bwrd => bwrd,
utm_type => utm_type,
vbusconf => vbusconf,
ramtest => ramtest,
urst_time => urst_time,
oepol => oepol)
port map(
clk => clk,
uclk => uclk,
rst => rst,
ursti => ursti,
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel => ehc_apbsi_psel,
ehc_apbsi_penable => ehc_apbsi_penable,
ehc_apbsi_paddr => ehc_apbsi_paddr,
ehc_apbsi_pwrite => ehc_apbsi_pwrite,
ehc_apbsi_pwdata => ehc_apbsi_pwdata,
ehc_apbsi_testen => ehc_apbsi_testen,
ehc_apbsi_testrst => ehc_apbsi_testrst,
ehc_apbsi_scanen => ehc_apbsi_scanen,
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata => ehc_apbso_prdata,
ehc_apbso_pirq => ehc_apbso_pirq,
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant => ahbmi_hgrant,
ahbmi_hready => ahbmi_hready,
ahbmi_hresp => ahbmi_hresp,
ahbmi_hrdata => ahbmi_hrdata,
ahbmi_hcache => ahbmi_hcache,
ahbmi_testen => ahbmi_testen,
ahbmi_testrst => ahbmi_testrst,
ahbmi_scanen => ahbmi_scanen,
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel => uhc_ahbsi_hsel,
uhc_ahbsi_haddr => uhc_ahbsi_haddr,
uhc_ahbsi_hwrite => uhc_ahbsi_hwrite,
uhc_ahbsi_htrans => uhc_ahbsi_htrans,
uhc_ahbsi_hsize => uhc_ahbsi_hsize,
uhc_ahbsi_hwdata => uhc_ahbsi_hwdata,
uhc_ahbsi_hready => uhc_ahbsi_hready,
uhc_ahbsi_testen => uhc_ahbsi_testen,
uhc_ahbsi_testrst => uhc_ahbsi_testrst,
uhc_ahbsi_scanen => uhc_ahbsi_scanen,
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq => ehc_ahbmo_hbusreq,
ehc_ahbmo_hlock => ehc_ahbmo_hlock,
ehc_ahbmo_htrans => ehc_ahbmo_htrans,
ehc_ahbmo_haddr => ehc_ahbmo_haddr,
ehc_ahbmo_hwrite => ehc_ahbmo_hwrite,
ehc_ahbmo_hsize => ehc_ahbmo_hsize,
ehc_ahbmo_hburst => ehc_ahbmo_hburst,
ehc_ahbmo_hprot => ehc_ahbmo_hprot,
ehc_ahbmo_hwdata => ehc_ahbmo_hwdata,
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq => uhc_ahbmo_hbusreq,
uhc_ahbmo_hlock => uhc_ahbmo_hlock,
uhc_ahbmo_htrans => uhc_ahbmo_htrans,
uhc_ahbmo_haddr => uhc_ahbmo_haddr,
uhc_ahbmo_hwrite => uhc_ahbmo_hwrite,
uhc_ahbmo_hsize => uhc_ahbmo_hsize,
uhc_ahbmo_hburst => uhc_ahbmo_hburst,
uhc_ahbmo_hprot => uhc_ahbmo_hprot,
uhc_ahbmo_hwdata => uhc_ahbmo_hwdata,
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready => uhc_ahbso_hready,
uhc_ahbso_hresp => uhc_ahbso_hresp,
uhc_ahbso_hrdata => uhc_ahbso_hrdata,
uhc_ahbso_hsplit => uhc_ahbso_hsplit,
uhc_ahbso_hcache => uhc_ahbso_hcache,
uhc_ahbso_hirq => uhc_ahbso_hirq,
-- usbhc_out_type_vector unwrapped
xcvrsel => xcvrsel,
termsel => termsel,
suspendm => suspendm,
opmode => opmode,
txvalid => txvalid,
drvvbus => drvvbus,
dataho => dataho,
validho => validho,
host => host,
stp => stp,
datao => datao,
utm_rst => utm_rst,
dctrlo => dctrlo,
-- usbhc_in_type_vector unwrapped
linestate => linestate,
txready => txready,
rxvalid => rxvalid,
rxactive => rxactive,
rxerror => rxerror,
vbusvalid => vbusvalid,
datahi => datahi,
validhi => validhi,
hostdisc => hostdisc,
nxt => nxt,
dir => dir,
datai => datai,
-- EHC transaction buffer signals
mbc20_tb_addr => mbc20_tb_addr,
mbc20_tb_data => mbc20_tb_data,
mbc20_tb_en => mbc20_tb_en,
mbc20_tb_wel => mbc20_tb_wel,
mbc20_tb_weh => mbc20_tb_weh,
tb_mbc20_data => tb_mbc20_data,
pe20_tb_addr => pe20_tb_addr,
pe20_tb_data => pe20_tb_data,
pe20_tb_en => pe20_tb_en,
pe20_tb_wel => pe20_tb_wel,
pe20_tb_weh => pe20_tb_weh,
tb_pe20_data => tb_pe20_data,
-- EHC packet buffer signals
mbc20_pb_addr => mbc20_pb_addr,
mbc20_pb_data => mbc20_pb_data,
mbc20_pb_en => mbc20_pb_en,
mbc20_pb_we => mbc20_pb_we,
pb_mbc20_data => pb_mbc20_data,
sie20_pb_addr => sie20_pb_addr,
sie20_pb_data => sie20_pb_data,
sie20_pb_en => sie20_pb_en,
sie20_pb_we => sie20_pb_we,
pb_sie20_data => pb_sie20_data,
-- UHC packet buffer signals
sie11_pb_addr => sie11_pb_addr,
sie11_pb_data => sie11_pb_data,
sie11_pb_en => sie11_pb_en,
sie11_pb_we => sie11_pb_we,
pb_sie11_data => pb_sie11_data,
mbc11_pb_addr => mbc11_pb_addr,
mbc11_pb_data => mbc11_pb_data,
mbc11_pb_en => mbc11_pb_en,
mbc11_pb_we => mbc11_pb_we,
pb_mbc11_data => pb_mbc11_data,
bufsel => bufsel);
end generate;
ax : if tech = axcel generate
usbhc0 : usbhc_axcelerator
generic map(
nports => nports,
ehcgen => ehcgen,
uhcgen => uhcgen,
n_cc => n_cc,
n_pcc => n_pcc,
prr => prr,
portroute1 => portroute1,
portroute2 => portroute2,
endian_conv => endian_conv,
be_regs => be_regs,
be_desc => be_desc,
uhcblo => uhcblo,
bwrd => bwrd,
utm_type => utm_type,
vbusconf => vbusconf,
ramtest => ramtest,
urst_time => urst_time,
oepol => oepol)
port map(
clk => clk,
uclk => uclk,
rst => rst,
ursti => ursti,
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel => ehc_apbsi_psel,
ehc_apbsi_penable => ehc_apbsi_penable,
ehc_apbsi_paddr => ehc_apbsi_paddr,
ehc_apbsi_pwrite => ehc_apbsi_pwrite,
ehc_apbsi_pwdata => ehc_apbsi_pwdata,
ehc_apbsi_testen => ehc_apbsi_testen,
ehc_apbsi_testrst => ehc_apbsi_testrst,
ehc_apbsi_scanen => ehc_apbsi_scanen,
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata => ehc_apbso_prdata,
ehc_apbso_pirq => ehc_apbso_pirq,
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant => ahbmi_hgrant,
ahbmi_hready => ahbmi_hready,
ahbmi_hresp => ahbmi_hresp,
ahbmi_hrdata => ahbmi_hrdata,
ahbmi_hcache => ahbmi_hcache,
ahbmi_testen => ahbmi_testen,
ahbmi_testrst => ahbmi_testrst,
ahbmi_scanen => ahbmi_scanen,
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel => uhc_ahbsi_hsel,
uhc_ahbsi_haddr => uhc_ahbsi_haddr,
uhc_ahbsi_hwrite => uhc_ahbsi_hwrite,
uhc_ahbsi_htrans => uhc_ahbsi_htrans,
uhc_ahbsi_hsize => uhc_ahbsi_hsize,
uhc_ahbsi_hwdata => uhc_ahbsi_hwdata,
uhc_ahbsi_hready => uhc_ahbsi_hready,
uhc_ahbsi_testen => uhc_ahbsi_testen,
uhc_ahbsi_testrst => uhc_ahbsi_testrst,
uhc_ahbsi_scanen => uhc_ahbsi_scanen,
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq => ehc_ahbmo_hbusreq,
ehc_ahbmo_hlock => ehc_ahbmo_hlock,
ehc_ahbmo_htrans => ehc_ahbmo_htrans,
ehc_ahbmo_haddr => ehc_ahbmo_haddr,
ehc_ahbmo_hwrite => ehc_ahbmo_hwrite,
ehc_ahbmo_hsize => ehc_ahbmo_hsize,
ehc_ahbmo_hburst => ehc_ahbmo_hburst,
ehc_ahbmo_hprot => ehc_ahbmo_hprot,
ehc_ahbmo_hwdata => ehc_ahbmo_hwdata,
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq => uhc_ahbmo_hbusreq,
uhc_ahbmo_hlock => uhc_ahbmo_hlock,
uhc_ahbmo_htrans => uhc_ahbmo_htrans,
uhc_ahbmo_haddr => uhc_ahbmo_haddr,
uhc_ahbmo_hwrite => uhc_ahbmo_hwrite,
uhc_ahbmo_hsize => uhc_ahbmo_hsize,
uhc_ahbmo_hburst => uhc_ahbmo_hburst,
uhc_ahbmo_hprot => uhc_ahbmo_hprot,
uhc_ahbmo_hwdata => uhc_ahbmo_hwdata,
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready => uhc_ahbso_hready,
uhc_ahbso_hresp => uhc_ahbso_hresp,
uhc_ahbso_hrdata => uhc_ahbso_hrdata,
uhc_ahbso_hsplit => uhc_ahbso_hsplit,
uhc_ahbso_hcache => uhc_ahbso_hcache,
uhc_ahbso_hirq => uhc_ahbso_hirq,
-- usbhc_out_type_vector unwrapped
xcvrsel => xcvrsel,
termsel => termsel,
suspendm => suspendm,
opmode => opmode,
txvalid => txvalid,
drvvbus => drvvbus,
dataho => dataho,
validho => validho,
host => host,
stp => stp,
datao => datao,
utm_rst => utm_rst,
dctrlo => dctrlo,
-- usbhc_in_type_vector unwrapped
linestate => linestate,
txready => txready,
rxvalid => rxvalid,
rxactive => rxactive,
rxerror => rxerror,
vbusvalid => vbusvalid,
datahi => datahi,
validhi => validhi,
hostdisc => hostdisc,
nxt => nxt,
dir => dir,
datai => datai,
-- EHC transaction buffer signals
mbc20_tb_addr => mbc20_tb_addr,
mbc20_tb_data => mbc20_tb_data,
mbc20_tb_en => mbc20_tb_en,
mbc20_tb_wel => mbc20_tb_wel,
mbc20_tb_weh => mbc20_tb_weh,
tb_mbc20_data => tb_mbc20_data,
pe20_tb_addr => pe20_tb_addr,
pe20_tb_data => pe20_tb_data,
pe20_tb_en => pe20_tb_en,
pe20_tb_wel => pe20_tb_wel,
pe20_tb_weh => pe20_tb_weh,
tb_pe20_data => tb_pe20_data,
-- EHC packet buffer signals
mbc20_pb_addr => mbc20_pb_addr,
mbc20_pb_data => mbc20_pb_data,
mbc20_pb_en => mbc20_pb_en,
mbc20_pb_we => mbc20_pb_we,
pb_mbc20_data => pb_mbc20_data,
sie20_pb_addr => sie20_pb_addr,
sie20_pb_data => sie20_pb_data,
sie20_pb_en => sie20_pb_en,
sie20_pb_we => sie20_pb_we,
pb_sie20_data => pb_sie20_data,
-- UHC packet buffer signals
sie11_pb_addr => sie11_pb_addr,
sie11_pb_data => sie11_pb_data,
sie11_pb_en => sie11_pb_en,
sie11_pb_we => sie11_pb_we,
pb_sie11_data => pb_sie11_data,
mbc11_pb_addr => mbc11_pb_addr,
mbc11_pb_data => mbc11_pb_data,
mbc11_pb_en => mbc11_pb_en,
mbc11_pb_we => mbc11_pb_we,
pb_mbc11_data => pb_mbc11_data,
bufsel => bufsel);
end generate;
-- pragma translate_off
nonet : if not ((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e) or (tech = axcel) or
(tech = stratix3) or (tech = cyclone3) or
(tech = stratix1) or (tech = stratix2) or (tech = altera)) generate
err : process
begin
assert false report "ERROR : No USBHC netlist available for this process!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: usbhc_net
-- File: usbhc_net.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: USBHC netlist wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity usbhc_net is
generic (
tech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end usbhc_net;
architecture rtl of usbhc_net is
component usbhc_unisim is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end component;
component usbhc_stratixii is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end component;
begin
xil : if (tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e) generate
usbhc0 : usbhc_unisim
generic map(
nports => nports,
ehcgen => ehcgen,
uhcgen => uhcgen,
n_cc => n_cc,
n_pcc => n_pcc,
prr => prr,
portroute1 => portroute1,
portroute2 => portroute2,
endian_conv => endian_conv,
be_regs => be_regs,
be_desc => be_desc,
uhcblo => uhcblo,
bwrd => bwrd,
utm_type => utm_type,
vbusconf => vbusconf,
ramtest => ramtest,
urst_time => urst_time,
oepol => oepol)
port map(
clk => clk,
uclk => uclk,
rst => rst,
ursti => ursti,
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel => ehc_apbsi_psel,
ehc_apbsi_penable => ehc_apbsi_penable,
ehc_apbsi_paddr => ehc_apbsi_paddr,
ehc_apbsi_pwrite => ehc_apbsi_pwrite,
ehc_apbsi_pwdata => ehc_apbsi_pwdata,
ehc_apbsi_testen => ehc_apbsi_testen,
ehc_apbsi_testrst => ehc_apbsi_testrst,
ehc_apbsi_scanen => ehc_apbsi_scanen,
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata => ehc_apbso_prdata,
ehc_apbso_pirq => ehc_apbso_pirq,
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant => ahbmi_hgrant,
ahbmi_hready => ahbmi_hready,
ahbmi_hresp => ahbmi_hresp,
ahbmi_hrdata => ahbmi_hrdata,
ahbmi_hcache => ahbmi_hcache,
ahbmi_testen => ahbmi_testen,
ahbmi_testrst => ahbmi_testrst,
ahbmi_scanen => ahbmi_scanen,
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel => uhc_ahbsi_hsel,
uhc_ahbsi_haddr => uhc_ahbsi_haddr,
uhc_ahbsi_hwrite => uhc_ahbsi_hwrite,
uhc_ahbsi_htrans => uhc_ahbsi_htrans,
uhc_ahbsi_hsize => uhc_ahbsi_hsize,
uhc_ahbsi_hwdata => uhc_ahbsi_hwdata,
uhc_ahbsi_hready => uhc_ahbsi_hready,
uhc_ahbsi_testen => uhc_ahbsi_testen,
uhc_ahbsi_testrst => uhc_ahbsi_testrst,
uhc_ahbsi_scanen => uhc_ahbsi_scanen,
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq => ehc_ahbmo_hbusreq,
ehc_ahbmo_hlock => ehc_ahbmo_hlock,
ehc_ahbmo_htrans => ehc_ahbmo_htrans,
ehc_ahbmo_haddr => ehc_ahbmo_haddr,
ehc_ahbmo_hwrite => ehc_ahbmo_hwrite,
ehc_ahbmo_hsize => ehc_ahbmo_hsize,
ehc_ahbmo_hburst => ehc_ahbmo_hburst,
ehc_ahbmo_hprot => ehc_ahbmo_hprot,
ehc_ahbmo_hwdata => ehc_ahbmo_hwdata,
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq => uhc_ahbmo_hbusreq,
uhc_ahbmo_hlock => uhc_ahbmo_hlock,
uhc_ahbmo_htrans => uhc_ahbmo_htrans,
uhc_ahbmo_haddr => uhc_ahbmo_haddr,
uhc_ahbmo_hwrite => uhc_ahbmo_hwrite,
uhc_ahbmo_hsize => uhc_ahbmo_hsize,
uhc_ahbmo_hburst => uhc_ahbmo_hburst,
uhc_ahbmo_hprot => uhc_ahbmo_hprot,
uhc_ahbmo_hwdata => uhc_ahbmo_hwdata,
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready => uhc_ahbso_hready,
uhc_ahbso_hresp => uhc_ahbso_hresp,
uhc_ahbso_hrdata => uhc_ahbso_hrdata,
uhc_ahbso_hsplit => uhc_ahbso_hsplit,
uhc_ahbso_hcache => uhc_ahbso_hcache,
uhc_ahbso_hirq => uhc_ahbso_hirq,
-- usbhc_out_type_vector unwrapped
xcvrsel => xcvrsel,
termsel => termsel,
suspendm => suspendm,
opmode => opmode,
txvalid => txvalid,
drvvbus => drvvbus,
dataho => dataho,
validho => validho,
host => host,
stp => stp,
datao => datao,
utm_rst => utm_rst,
dctrlo => dctrlo,
-- usbhc_in_type_vector unwrapped
linestate => linestate,
txready => txready,
rxvalid => rxvalid,
rxactive => rxactive,
rxerror => rxerror,
vbusvalid => vbusvalid,
datahi => datahi,
validhi => validhi,
hostdisc => hostdisc,
nxt => nxt,
dir => dir,
datai => datai,
-- EHC transaction buffer signals
mbc20_tb_addr => mbc20_tb_addr,
mbc20_tb_data => mbc20_tb_data,
mbc20_tb_en => mbc20_tb_en,
mbc20_tb_wel => mbc20_tb_wel,
mbc20_tb_weh => mbc20_tb_weh,
tb_mbc20_data => tb_mbc20_data,
pe20_tb_addr => pe20_tb_addr,
pe20_tb_data => pe20_tb_data,
pe20_tb_en => pe20_tb_en,
pe20_tb_wel => pe20_tb_wel,
pe20_tb_weh => pe20_tb_weh,
tb_pe20_data => tb_pe20_data,
-- EHC packet buffer signals
mbc20_pb_addr => mbc20_pb_addr,
mbc20_pb_data => mbc20_pb_data,
mbc20_pb_en => mbc20_pb_en,
mbc20_pb_we => mbc20_pb_we,
pb_mbc20_data => pb_mbc20_data,
sie20_pb_addr => sie20_pb_addr,
sie20_pb_data => sie20_pb_data,
sie20_pb_en => sie20_pb_en,
sie20_pb_we => sie20_pb_we,
pb_sie20_data => pb_sie20_data,
-- UHC packet buffer signals
sie11_pb_addr => sie11_pb_addr,
sie11_pb_data => sie11_pb_data,
sie11_pb_en => sie11_pb_en,
sie11_pb_we => sie11_pb_we,
pb_sie11_data => pb_sie11_data,
mbc11_pb_addr => mbc11_pb_addr,
mbc11_pb_data => mbc11_pb_data,
mbc11_pb_en => mbc11_pb_en,
mbc11_pb_we => mbc11_pb_we,
pb_mbc11_data => pb_mbc11_data,
bufsel => bufsel);
end generate;
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = cyclone3) generate
usbhc0 : usbhc_stratixii
generic map(
nports => nports,
ehcgen => ehcgen,
uhcgen => uhcgen,
n_cc => n_cc,
n_pcc => n_pcc,
prr => prr,
portroute1 => portroute1,
portroute2 => portroute2,
endian_conv => endian_conv,
be_regs => be_regs,
be_desc => be_desc,
uhcblo => uhcblo,
bwrd => bwrd,
utm_type => utm_type,
vbusconf => vbusconf,
ramtest => ramtest,
urst_time => urst_time,
oepol => oepol)
port map(
clk => clk,
uclk => uclk,
rst => rst,
ursti => ursti,
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel => ehc_apbsi_psel,
ehc_apbsi_penable => ehc_apbsi_penable,
ehc_apbsi_paddr => ehc_apbsi_paddr,
ehc_apbsi_pwrite => ehc_apbsi_pwrite,
ehc_apbsi_pwdata => ehc_apbsi_pwdata,
ehc_apbsi_testen => ehc_apbsi_testen,
ehc_apbsi_testrst => ehc_apbsi_testrst,
ehc_apbsi_scanen => ehc_apbsi_scanen,
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata => ehc_apbso_prdata,
ehc_apbso_pirq => ehc_apbso_pirq,
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant => ahbmi_hgrant,
ahbmi_hready => ahbmi_hready,
ahbmi_hresp => ahbmi_hresp,
ahbmi_hrdata => ahbmi_hrdata,
ahbmi_hcache => ahbmi_hcache,
ahbmi_testen => ahbmi_testen,
ahbmi_testrst => ahbmi_testrst,
ahbmi_scanen => ahbmi_scanen,
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel => uhc_ahbsi_hsel,
uhc_ahbsi_haddr => uhc_ahbsi_haddr,
uhc_ahbsi_hwrite => uhc_ahbsi_hwrite,
uhc_ahbsi_htrans => uhc_ahbsi_htrans,
uhc_ahbsi_hsize => uhc_ahbsi_hsize,
uhc_ahbsi_hwdata => uhc_ahbsi_hwdata,
uhc_ahbsi_hready => uhc_ahbsi_hready,
uhc_ahbsi_testen => uhc_ahbsi_testen,
uhc_ahbsi_testrst => uhc_ahbsi_testrst,
uhc_ahbsi_scanen => uhc_ahbsi_scanen,
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq => ehc_ahbmo_hbusreq,
ehc_ahbmo_hlock => ehc_ahbmo_hlock,
ehc_ahbmo_htrans => ehc_ahbmo_htrans,
ehc_ahbmo_haddr => ehc_ahbmo_haddr,
ehc_ahbmo_hwrite => ehc_ahbmo_hwrite,
ehc_ahbmo_hsize => ehc_ahbmo_hsize,
ehc_ahbmo_hburst => ehc_ahbmo_hburst,
ehc_ahbmo_hprot => ehc_ahbmo_hprot,
ehc_ahbmo_hwdata => ehc_ahbmo_hwdata,
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq => uhc_ahbmo_hbusreq,
uhc_ahbmo_hlock => uhc_ahbmo_hlock,
uhc_ahbmo_htrans => uhc_ahbmo_htrans,
uhc_ahbmo_haddr => uhc_ahbmo_haddr,
uhc_ahbmo_hwrite => uhc_ahbmo_hwrite,
uhc_ahbmo_hsize => uhc_ahbmo_hsize,
uhc_ahbmo_hburst => uhc_ahbmo_hburst,
uhc_ahbmo_hprot => uhc_ahbmo_hprot,
uhc_ahbmo_hwdata => uhc_ahbmo_hwdata,
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready => uhc_ahbso_hready,
uhc_ahbso_hresp => uhc_ahbso_hresp,
uhc_ahbso_hrdata => uhc_ahbso_hrdata,
uhc_ahbso_hsplit => uhc_ahbso_hsplit,
uhc_ahbso_hcache => uhc_ahbso_hcache,
uhc_ahbso_hirq => uhc_ahbso_hirq,
-- usbhc_out_type_vector unwrapped
xcvrsel => xcvrsel,
termsel => termsel,
suspendm => suspendm,
opmode => opmode,
txvalid => txvalid,
drvvbus => drvvbus,
dataho => dataho,
validho => validho,
host => host,
stp => stp,
datao => datao,
utm_rst => utm_rst,
dctrlo => dctrlo,
-- usbhc_in_type_vector unwrapped
linestate => linestate,
txready => txready,
rxvalid => rxvalid,
rxactive => rxactive,
rxerror => rxerror,
vbusvalid => vbusvalid,
datahi => datahi,
validhi => validhi,
hostdisc => hostdisc,
nxt => nxt,
dir => dir,
datai => datai,
-- EHC transaction buffer signals
mbc20_tb_addr => mbc20_tb_addr,
mbc20_tb_data => mbc20_tb_data,
mbc20_tb_en => mbc20_tb_en,
mbc20_tb_wel => mbc20_tb_wel,
mbc20_tb_weh => mbc20_tb_weh,
tb_mbc20_data => tb_mbc20_data,
pe20_tb_addr => pe20_tb_addr,
pe20_tb_data => pe20_tb_data,
pe20_tb_en => pe20_tb_en,
pe20_tb_wel => pe20_tb_wel,
pe20_tb_weh => pe20_tb_weh,
tb_pe20_data => tb_pe20_data,
-- EHC packet buffer signals
mbc20_pb_addr => mbc20_pb_addr,
mbc20_pb_data => mbc20_pb_data,
mbc20_pb_en => mbc20_pb_en,
mbc20_pb_we => mbc20_pb_we,
pb_mbc20_data => pb_mbc20_data,
sie20_pb_addr => sie20_pb_addr,
sie20_pb_data => sie20_pb_data,
sie20_pb_en => sie20_pb_en,
sie20_pb_we => sie20_pb_we,
pb_sie20_data => pb_sie20_data,
-- UHC packet buffer signals
sie11_pb_addr => sie11_pb_addr,
sie11_pb_data => sie11_pb_data,
sie11_pb_en => sie11_pb_en,
sie11_pb_we => sie11_pb_we,
pb_sie11_data => pb_sie11_data,
mbc11_pb_addr => mbc11_pb_addr,
mbc11_pb_data => mbc11_pb_data,
mbc11_pb_en => mbc11_pb_en,
mbc11_pb_we => mbc11_pb_we,
pb_mbc11_data => pb_mbc11_data,
bufsel => bufsel);
end generate;
ax : if tech = axcel generate
usbhc0 : usbhc_axcelerator
generic map(
nports => nports,
ehcgen => ehcgen,
uhcgen => uhcgen,
n_cc => n_cc,
n_pcc => n_pcc,
prr => prr,
portroute1 => portroute1,
portroute2 => portroute2,
endian_conv => endian_conv,
be_regs => be_regs,
be_desc => be_desc,
uhcblo => uhcblo,
bwrd => bwrd,
utm_type => utm_type,
vbusconf => vbusconf,
ramtest => ramtest,
urst_time => urst_time,
oepol => oepol)
port map(
clk => clk,
uclk => uclk,
rst => rst,
ursti => ursti,
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel => ehc_apbsi_psel,
ehc_apbsi_penable => ehc_apbsi_penable,
ehc_apbsi_paddr => ehc_apbsi_paddr,
ehc_apbsi_pwrite => ehc_apbsi_pwrite,
ehc_apbsi_pwdata => ehc_apbsi_pwdata,
ehc_apbsi_testen => ehc_apbsi_testen,
ehc_apbsi_testrst => ehc_apbsi_testrst,
ehc_apbsi_scanen => ehc_apbsi_scanen,
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata => ehc_apbso_prdata,
ehc_apbso_pirq => ehc_apbso_pirq,
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant => ahbmi_hgrant,
ahbmi_hready => ahbmi_hready,
ahbmi_hresp => ahbmi_hresp,
ahbmi_hrdata => ahbmi_hrdata,
ahbmi_hcache => ahbmi_hcache,
ahbmi_testen => ahbmi_testen,
ahbmi_testrst => ahbmi_testrst,
ahbmi_scanen => ahbmi_scanen,
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel => uhc_ahbsi_hsel,
uhc_ahbsi_haddr => uhc_ahbsi_haddr,
uhc_ahbsi_hwrite => uhc_ahbsi_hwrite,
uhc_ahbsi_htrans => uhc_ahbsi_htrans,
uhc_ahbsi_hsize => uhc_ahbsi_hsize,
uhc_ahbsi_hwdata => uhc_ahbsi_hwdata,
uhc_ahbsi_hready => uhc_ahbsi_hready,
uhc_ahbsi_testen => uhc_ahbsi_testen,
uhc_ahbsi_testrst => uhc_ahbsi_testrst,
uhc_ahbsi_scanen => uhc_ahbsi_scanen,
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq => ehc_ahbmo_hbusreq,
ehc_ahbmo_hlock => ehc_ahbmo_hlock,
ehc_ahbmo_htrans => ehc_ahbmo_htrans,
ehc_ahbmo_haddr => ehc_ahbmo_haddr,
ehc_ahbmo_hwrite => ehc_ahbmo_hwrite,
ehc_ahbmo_hsize => ehc_ahbmo_hsize,
ehc_ahbmo_hburst => ehc_ahbmo_hburst,
ehc_ahbmo_hprot => ehc_ahbmo_hprot,
ehc_ahbmo_hwdata => ehc_ahbmo_hwdata,
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq => uhc_ahbmo_hbusreq,
uhc_ahbmo_hlock => uhc_ahbmo_hlock,
uhc_ahbmo_htrans => uhc_ahbmo_htrans,
uhc_ahbmo_haddr => uhc_ahbmo_haddr,
uhc_ahbmo_hwrite => uhc_ahbmo_hwrite,
uhc_ahbmo_hsize => uhc_ahbmo_hsize,
uhc_ahbmo_hburst => uhc_ahbmo_hburst,
uhc_ahbmo_hprot => uhc_ahbmo_hprot,
uhc_ahbmo_hwdata => uhc_ahbmo_hwdata,
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready => uhc_ahbso_hready,
uhc_ahbso_hresp => uhc_ahbso_hresp,
uhc_ahbso_hrdata => uhc_ahbso_hrdata,
uhc_ahbso_hsplit => uhc_ahbso_hsplit,
uhc_ahbso_hcache => uhc_ahbso_hcache,
uhc_ahbso_hirq => uhc_ahbso_hirq,
-- usbhc_out_type_vector unwrapped
xcvrsel => xcvrsel,
termsel => termsel,
suspendm => suspendm,
opmode => opmode,
txvalid => txvalid,
drvvbus => drvvbus,
dataho => dataho,
validho => validho,
host => host,
stp => stp,
datao => datao,
utm_rst => utm_rst,
dctrlo => dctrlo,
-- usbhc_in_type_vector unwrapped
linestate => linestate,
txready => txready,
rxvalid => rxvalid,
rxactive => rxactive,
rxerror => rxerror,
vbusvalid => vbusvalid,
datahi => datahi,
validhi => validhi,
hostdisc => hostdisc,
nxt => nxt,
dir => dir,
datai => datai,
-- EHC transaction buffer signals
mbc20_tb_addr => mbc20_tb_addr,
mbc20_tb_data => mbc20_tb_data,
mbc20_tb_en => mbc20_tb_en,
mbc20_tb_wel => mbc20_tb_wel,
mbc20_tb_weh => mbc20_tb_weh,
tb_mbc20_data => tb_mbc20_data,
pe20_tb_addr => pe20_tb_addr,
pe20_tb_data => pe20_tb_data,
pe20_tb_en => pe20_tb_en,
pe20_tb_wel => pe20_tb_wel,
pe20_tb_weh => pe20_tb_weh,
tb_pe20_data => tb_pe20_data,
-- EHC packet buffer signals
mbc20_pb_addr => mbc20_pb_addr,
mbc20_pb_data => mbc20_pb_data,
mbc20_pb_en => mbc20_pb_en,
mbc20_pb_we => mbc20_pb_we,
pb_mbc20_data => pb_mbc20_data,
sie20_pb_addr => sie20_pb_addr,
sie20_pb_data => sie20_pb_data,
sie20_pb_en => sie20_pb_en,
sie20_pb_we => sie20_pb_we,
pb_sie20_data => pb_sie20_data,
-- UHC packet buffer signals
sie11_pb_addr => sie11_pb_addr,
sie11_pb_data => sie11_pb_data,
sie11_pb_en => sie11_pb_en,
sie11_pb_we => sie11_pb_we,
pb_sie11_data => pb_sie11_data,
mbc11_pb_addr => mbc11_pb_addr,
mbc11_pb_data => mbc11_pb_data,
mbc11_pb_en => mbc11_pb_en,
mbc11_pb_we => mbc11_pb_we,
pb_mbc11_data => pb_mbc11_data,
bufsel => bufsel);
end generate;
-- pragma translate_off
nonet : if not ((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e) or (tech = axcel) or
(tech = stratix3) or (tech = cyclone3) or
(tech = stratix1) or (tech = stratix2) or (tech = altera)) generate
err : process
begin
assert false report "ERROR : No USBHC netlist available for this process!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc907.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s03b00x00p05n01i00907pkg is
function FA ( B : INTEGER ) return INTEGER;
function FB ( B : INTEGER ) return INTEGER;
end c10s03b00x00p05n01i00907pkg;
package body c10s03b00x00p05n01i00907pkg is
function FA ( B : INTEGER ) return INTEGER is
constant C : INTEGER := 6;
begin
return B;
end FA;
function FB ( B : INTEGER ) return INTEGER is
begin
return C; -- Failure_here
-- error: entity not within the region it is immediately declared
end FB;
end c10s03b00x00p05n01i00907pkg;
ENTITY c10s03b00x00p05n01i00907ent IS
END c10s03b00x00p05n01i00907ent;
ARCHITECTURE c10s03b00x00p05n01i00907arch OF c10s03b00x00p05n01i00907ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00907 - Entity is not within the region it is immediately declared in."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00907arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc907.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s03b00x00p05n01i00907pkg is
function FA ( B : INTEGER ) return INTEGER;
function FB ( B : INTEGER ) return INTEGER;
end c10s03b00x00p05n01i00907pkg;
package body c10s03b00x00p05n01i00907pkg is
function FA ( B : INTEGER ) return INTEGER is
constant C : INTEGER := 6;
begin
return B;
end FA;
function FB ( B : INTEGER ) return INTEGER is
begin
return C; -- Failure_here
-- error: entity not within the region it is immediately declared
end FB;
end c10s03b00x00p05n01i00907pkg;
ENTITY c10s03b00x00p05n01i00907ent IS
END c10s03b00x00p05n01i00907ent;
ARCHITECTURE c10s03b00x00p05n01i00907arch OF c10s03b00x00p05n01i00907ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00907 - Entity is not within the region it is immediately declared in."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00907arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc907.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s03b00x00p05n01i00907pkg is
function FA ( B : INTEGER ) return INTEGER;
function FB ( B : INTEGER ) return INTEGER;
end c10s03b00x00p05n01i00907pkg;
package body c10s03b00x00p05n01i00907pkg is
function FA ( B : INTEGER ) return INTEGER is
constant C : INTEGER := 6;
begin
return B;
end FA;
function FB ( B : INTEGER ) return INTEGER is
begin
return C; -- Failure_here
-- error: entity not within the region it is immediately declared
end FB;
end c10s03b00x00p05n01i00907pkg;
ENTITY c10s03b00x00p05n01i00907ent IS
END c10s03b00x00p05n01i00907ent;
ARCHITECTURE c10s03b00x00p05n01i00907arch OF c10s03b00x00p05n01i00907ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00907 - Entity is not within the region it is immediately declared in."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00907arch;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity scf_nov is
port(
clock: in std_logic;
input: in std_logic_vector(26 downto 0);
output: out std_logic_vector(55 downto 0)
);
end scf_nov;
architecture behaviour of scf_nov is
constant state1: std_logic_vector(6 downto 0) := "1000101";
constant state2: std_logic_vector(6 downto 0) := "1100001";
constant state3: std_logic_vector(6 downto 0) := "1111101";
constant state4: std_logic_vector(6 downto 0) := "1110101";
constant state5: std_logic_vector(6 downto 0) := "0010111";
constant state6: std_logic_vector(6 downto 0) := "1001101";
constant state7: std_logic_vector(6 downto 0) := "1101001";
constant state8: std_logic_vector(6 downto 0) := "1100111";
constant state9: std_logic_vector(6 downto 0) := "1100100";
constant state10: std_logic_vector(6 downto 0) := "1011101";
constant state11: std_logic_vector(6 downto 0) := "1000001";
constant state12: std_logic_vector(6 downto 0) := "1101111";
constant state13: std_logic_vector(6 downto 0) := "1110100";
constant state14: std_logic_vector(6 downto 0) := "0101101";
constant state15: std_logic_vector(6 downto 0) := "0101001";
constant state16: std_logic_vector(6 downto 0) := "1101101";
constant state17: std_logic_vector(6 downto 0) := "1010101";
constant state18: std_logic_vector(6 downto 0) := "1101110";
constant state19: std_logic_vector(6 downto 0) := "1110001";
constant state20: std_logic_vector(6 downto 0) := "0001110";
constant state21: std_logic_vector(6 downto 0) := "1100011";
constant state22: std_logic_vector(6 downto 0) := "0010000";
constant state23: std_logic_vector(6 downto 0) := "1101100";
constant state24: std_logic_vector(6 downto 0) := "0010011";
constant state25: std_logic_vector(6 downto 0) := "0001101";
constant state26: std_logic_vector(6 downto 0) := "1111110";
constant state27: std_logic_vector(6 downto 0) := "1100000";
constant state28: std_logic_vector(6 downto 0) := "0010101";
constant state29: std_logic_vector(6 downto 0) := "0010001";
constant state30: std_logic_vector(6 downto 0) := "0101111";
constant state31: std_logic_vector(6 downto 0) := "1001010";
constant state32: std_logic_vector(6 downto 0) := "1011110";
constant state33: std_logic_vector(6 downto 0) := "0001010";
constant state34: std_logic_vector(6 downto 0) := "0000001";
constant state35: std_logic_vector(6 downto 0) := "1011010";
constant state36: std_logic_vector(6 downto 0) := "1101010";
constant state37: std_logic_vector(6 downto 0) := "1111111";
constant state38: std_logic_vector(6 downto 0) := "0100000";
constant state39: std_logic_vector(6 downto 0) := "1011111";
constant state40: std_logic_vector(6 downto 0) := "0111010";
constant state41: std_logic_vector(6 downto 0) := "1000000";
constant state42: std_logic_vector(6 downto 0) := "0111110";
constant state43: std_logic_vector(6 downto 0) := "0101010";
constant state44: std_logic_vector(6 downto 0) := "0111111";
constant state45: std_logic_vector(6 downto 0) := "1110000";
constant state46: std_logic_vector(6 downto 0) := "0001111";
constant state47: std_logic_vector(6 downto 0) := "0011101";
constant state48: std_logic_vector(6 downto 0) := "0011001";
constant state49: std_logic_vector(6 downto 0) := "1101000";
constant state50: std_logic_vector(6 downto 0) := "0000110";
constant state51: std_logic_vector(6 downto 0) := "0011000";
constant state52: std_logic_vector(6 downto 0) := "0110001";
constant state53: std_logic_vector(6 downto 0) := "0011011";
constant state54: std_logic_vector(6 downto 0) := "1011100";
constant state55: std_logic_vector(6 downto 0) := "0100011";
constant state56: std_logic_vector(6 downto 0) := "1011011";
constant state57: std_logic_vector(6 downto 0) := "0100100";
constant state58: std_logic_vector(6 downto 0) := "1011000";
constant state59: std_logic_vector(6 downto 0) := "0100111";
constant state60: std_logic_vector(6 downto 0) := "1011001";
constant state61: std_logic_vector(6 downto 0) := "1100110";
constant state62: std_logic_vector(6 downto 0) := "0100101";
constant state63: std_logic_vector(6 downto 0) := "0001100";
constant state64: std_logic_vector(6 downto 0) := "1100101";
constant state65: std_logic_vector(6 downto 0) := "1110011";
constant state66: std_logic_vector(6 downto 0) := "0100010";
constant state67: std_logic_vector(6 downto 0) := "0001011";
constant state68: std_logic_vector(6 downto 0) := "0110100";
constant state69: std_logic_vector(6 downto 0) := "0000010";
constant state70: std_logic_vector(6 downto 0) := "1010110";
constant state71: std_logic_vector(6 downto 0) := "1000010";
constant state72: std_logic_vector(6 downto 0) := "1001001";
constant state73: std_logic_vector(6 downto 0) := "0010010";
constant state74: std_logic_vector(6 downto 0) := "0111100";
constant state75: std_logic_vector(6 downto 0) := "0110010";
constant state76: std_logic_vector(6 downto 0) := "1000011";
constant state77: std_logic_vector(6 downto 0) := "1010010";
constant state78: std_logic_vector(6 downto 0) := "0111101";
constant state79: std_logic_vector(6 downto 0) := "1110010";
constant state80: std_logic_vector(6 downto 0) := "1100010";
constant state81: std_logic_vector(6 downto 0) := "0011100";
constant state82: std_logic_vector(6 downto 0) := "0100110";
constant state83: std_logic_vector(6 downto 0) := "1010011";
constant state84: std_logic_vector(6 downto 0) := "0101000";
constant state85: std_logic_vector(6 downto 0) := "1010111";
constant state86: std_logic_vector(6 downto 0) := "1001000";
constant state87: std_logic_vector(6 downto 0) := "0011111";
constant state88: std_logic_vector(6 downto 0) := "0011010";
constant state89: std_logic_vector(6 downto 0) := "0111011";
constant state90: std_logic_vector(6 downto 0) := "1000100";
constant state91: std_logic_vector(6 downto 0) := "0111000";
constant state92: std_logic_vector(6 downto 0) := "1000111";
constant state93: std_logic_vector(6 downto 0) := "0111001";
constant state94: std_logic_vector(6 downto 0) := "0011110";
constant state95: std_logic_vector(6 downto 0) := "1000110";
constant state96: std_logic_vector(6 downto 0) := "0110110";
constant state97: std_logic_vector(6 downto 0) := "1111001";
constant state98: std_logic_vector(6 downto 0) := "0001000";
constant state99: std_logic_vector(6 downto 0) := "1110111";
constant state100: std_logic_vector(6 downto 0) := "0001001";
constant state101: std_logic_vector(6 downto 0) := "1110110";
constant state102: std_logic_vector(6 downto 0) := "0000111";
constant state103: std_logic_vector(6 downto 0) := "1111000";
constant state104: std_logic_vector(6 downto 0) := "0000100";
constant state105: std_logic_vector(6 downto 0) := "1101011";
constant state106: std_logic_vector(6 downto 0) := "0000101";
constant state107: std_logic_vector(6 downto 0) := "1111010";
constant state108: std_logic_vector(6 downto 0) := "0000011";
constant state109: std_logic_vector(6 downto 0) := "1111100";
constant state110: std_logic_vector(6 downto 0) := "0000000";
constant state111: std_logic_vector(6 downto 0) := "0010100";
constant state112: std_logic_vector(6 downto 0) := "1111011";
constant state113: std_logic_vector(6 downto 0) := "0010110";
constant state114: std_logic_vector(6 downto 0) := "0110111";
constant state115: std_logic_vector(6 downto 0) := "1001100";
constant state116: std_logic_vector(6 downto 0) := "0110101";
constant state117: std_logic_vector(6 downto 0) := "1001110";
constant state118: std_logic_vector(6 downto 0) := "0110011";
constant state119: std_logic_vector(6 downto 0) := "1010000";
constant state120: std_logic_vector(6 downto 0) := "0101110";
constant state121: std_logic_vector(6 downto 0) := "1001011";
signal current_state, next_state: std_logic_vector(6 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------"; output <= "--------------------------------------------------------";
if std_match(input, "0--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
else
case current_state is
when state1 =>
if std_match(input, "1--------------------------") then next_state <= state3; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state2 =>
if std_match(input, "1--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state3 =>
if std_match(input, "1--------------------------") then next_state <= state4; output <= "00000010010000001-0000000-00-0001001000010-0-----00-0---";
end if;
when state4 =>
if std_match(input, "1--------------------------") then next_state <= state5; output <= "00000010000000000-0000000-00-0000000110101-0-----00-0---";
end if;
when state5 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state6 =>
if std_match(input, "1--------------------------") then next_state <= state2; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state7 =>
if std_match(input, "1-----0--------------------") then next_state <= state9; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----1--------------------") then next_state <= state8; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state8 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000010000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state9 =>
if std_match(input, "1----0---------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----1---------------------") then next_state <= state10; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state10 =>
if std_match(input, "1--------------------------") then next_state <= state11; output <= "00000010000000000-0000001-00-0000000000001-0-----00-0---";
end if;
when state11 =>
if std_match(input, "1--------------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000010000000-0-----00-0---";
end if;
when state12 =>
if std_match(input, "1---0----------------------") then next_state <= state15; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---1----------------------") then next_state <= state13; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state13 =>
if std_match(input, "1--------------------------") then next_state <= state29; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state14 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state15 =>
if std_match(input, "1--------------------------") then next_state <= state59; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state16 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state17 =>
if std_match(input, "1--------------------------") then next_state <= state18; output <= "0000000000010100001000000-10-000000000000011-----00-0---";
end if;
when state18 =>
if std_match(input, "1--------------------------") then next_state <= state19; output <= "00100000000000000-0000000-00-0000000000000-0000--00-0---";
end if;
when state19 =>
if std_match(input, "1--0-----------------------") then next_state <= state21; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state20; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state20 =>
if std_match(input, "1--------------------------") then next_state <= state21; output <= "00000001000000000-0000000-00-0000000100000-0-----00-0---";
end if;
when state21 =>
if std_match(input, "1--------------------------") then next_state <= state22; output <= "01000000000100000-0000000-10-100000000000000000001001---";
end if;
when state22 =>
if std_match(input, "1--------------------------") then next_state <= state23; output <= "00010000000000000-0000000-00-0000000000000-0000--01-0---";
end if;
when state23 =>
if std_match(input, "1--------------------------") then next_state <= state24; output <= "00000000100000000-0000000-00-0000000000000-0---0000-0---";
end if;
when state24 =>
if std_match(input, "1-0------------------------") then next_state <= state26; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-1------------------------") then next_state <= state25; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state25 =>
if std_match(input, "1--------------------------") then next_state <= state26; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state26 =>
if std_match(input, "10-------------------------") then next_state <= state28; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "11-------------------------") then next_state <= state27; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
end if;
when state27 =>
if std_match(input, "1--------------------------") then next_state <= state28; output <= "00000000000000000-0000000-00-0010000000000-0-----00-0---";
end if;
when state28 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state29 =>
if std_match(input, "1------1-------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state34; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state32; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state30; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state30 =>
if std_match(input, "1--------------------------") then next_state <= state38; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state31 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state32 =>
if std_match(input, "1--------------------------") then next_state <= state55; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state33 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state34 =>
if std_match(input, "1--------------------------") then next_state <= state57; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state35 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state36 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state37 =>
if std_match(input, "1--------------------------") then next_state <= state14; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state38 =>
if std_match(input, "1----------1---------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------01--------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------001-------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0001------------") then next_state <= state41; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0000------------") then next_state <= state39; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state39 =>
if std_match(input, "1--------------------------") then next_state <= state45; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state40 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state41 =>
if std_match(input, "1--------------------------") then next_state <= state50; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state42 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state43 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state44 =>
if std_match(input, "1--------------------------") then next_state <= state31; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state45 =>
if std_match(input, "1--------------0-----------") then next_state <= state48; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state46; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state46 =>
if std_match(input, "1--------------------------") then next_state <= state47; output <= "0000000001000101001000000-00-0000000000000-0-----00-0---";
end if;
when state47 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state48 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state49 =>
if std_match(input, "1--------------------------") then next_state <= state40; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state50 =>
if std_match(input, "1--------------0-----------") then next_state <= state52; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state51; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state51 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state52 =>
if std_match(input, "1--------------------------") then next_state <= state53; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state53 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state54 =>
if std_match(input, "1--------------------------") then next_state <= state42; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state55 =>
if std_match(input, "1--------------------------") then next_state <= state56; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state56 =>
if std_match(input, "1--------------------------") then next_state <= state33; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state57 =>
if std_match(input, "1--------------------------") then next_state <= state58; output <= "00000000001000001-0001000-00-0000000000000-0-----00-0---";
end if;
when state58 =>
if std_match(input, "1--------------------------") then next_state <= state35; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state59 =>
if std_match(input, "1---------------0----------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---------------1----------") then next_state <= state60; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state60 =>
if std_match(input, "1------1-------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state65; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state63; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state61; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state61 =>
if std_match(input, "1--------------------------") then next_state <= state82; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state62 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state63 =>
if std_match(input, "1--------------------------") then next_state <= state83; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state64 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state65 =>
if std_match(input, "1--------------------------") then next_state <= state89; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state66 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state67 =>
if std_match(input, "1------1-------------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------011-----------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0101----------------") then next_state <= state78; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0100----------------") then next_state <= state76; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state74; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state72; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state70; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state68; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state68 =>
if std_match(input, "1--------------------------") then next_state <= state96; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state69 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state70 =>
if std_match(input, "1--------------------------") then next_state <= state98; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state71 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state72 =>
if std_match(input, "1--------------------------") then next_state <= state103; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state73 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state74 =>
if std_match(input, "1--------------------------") then next_state <= state107; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state75 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state76 =>
if std_match(input, "1--------------------------") then next_state <= state115; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state77 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state78 =>
if std_match(input, "1--------------------------") then next_state <= state117; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state79 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state80 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state81 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state82 =>
if std_match(input, "1--------------------------") then next_state <= state62; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state83 =>
if std_match(input, "1--------------------------") then next_state <= state84; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state84 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00001000000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state85 =>
if std_match(input, "1--------------------------") then next_state <= state64; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state86 =>
if std_match(input, "1----------------0---------") then next_state <= state88; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------------1---------") then next_state <= state87; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state87 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000001000000000-0000000-00-0000100001000-0-----00-0---";
end if;
when state88 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state89 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00001001000000000-0000000-00-0001000001000-0-----00-0---";
end if;
when state90 =>
if std_match(input, "1--------------------------") then next_state <= state66; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state91 =>
if std_match(input, "1--------------------------") then next_state <= state92; output <= "00000010000000000-0000000-00-0000000000000-0010--00-0---";
end if;
when state92 =>
if std_match(input, "1--0-----------------------") then next_state <= state95; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state93; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state93 =>
if std_match(input, "1--------------------------") then next_state <= state94; output <= "00000000000100001-0000000-10-0000000000000-0-----00-0---";
end if;
when state94 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state95 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00000000000000000-0000000-00-0010100000000-0-----00-0---";
end if;
when state96 =>
if std_match(input, "1--------------------------") then next_state <= state97; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state97 =>
if std_match(input, "1--------------------------") then next_state <= state69; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state98 =>
if std_match(input, "1--------------0-----------") then next_state <= state101; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state99; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state99 =>
if std_match(input, "1--------------------------") then next_state <= state100; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state100 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state101 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state102 =>
if std_match(input, "1--------------------------") then next_state <= state71; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state103 =>
if std_match(input, "1--------------0-----------") then next_state <= state105; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state104; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state104 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state105 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state106 =>
if std_match(input, "1--------------------------") then next_state <= state73; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state107 =>
if std_match(input, "1--------------0-----------") then next_state <= state112; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state108; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state108 =>
if std_match(input, "1-----------------00000000-") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------1--------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------01-------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------001------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0001-----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00001----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------000001---") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0000001--") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00000001-") then next_state <= state109; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state109 =>
if std_match(input, "1--------------------------") then next_state <= state112; output <= "0000000000001100101000000-00-0000000000000-0-----00-0100";
end if;
when state110 =>
if std_match(input, "1--------------------------") then next_state <= state111; output <= "0000010000000101001010000-0000100000000000111000110-0100";
end if;
when state111 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000100001-0000000000001-0-----00-0---";
end if;
when state112 =>
if std_match(input, "1--------------------------") then next_state <= state113; output <= "00000100000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state113 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state114 =>
if std_match(input, "1--------------------------") then next_state <= state75; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state115 =>
if std_match(input, "1--------------------------") then next_state <= state116; output <= "00001000000010001-0010000-00-0000000000000-01011010-0101";
end if;
when state116 =>
if std_match(input, "1--------------------------") then next_state <= state77; output <= "10000001000000000-0000100-00-0001000001101-0-----00-0---";
end if;
when state117 =>
if std_match(input, "1--------------------------") then next_state <= state118; output <= "00000010000000000-0000000-00-0000000000000-0-----00-0011";
end if;
when state118 =>
if std_match(input, "1-------------------------0") then next_state <= state121; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-------------------------1") then next_state <= state119; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state119 =>
if std_match(input, "1--------------------------") then next_state <= state120; output <= "0000010000001000001000000-00-0000000000000111011010-0101";
end if;
when state120 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00010010000000010-000000000110100000000100-0-----00-0---";
end if;
when state121 =>
if std_match(input, "1--------------------------") then next_state <= state79; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when others => next_state <= "-------"; output <= "--------------------------------------------------------";
end case;
end if;
end process;
end behaviour;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN4_direct is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN4_direct;
architecture Behavioral of EPROC_IN4_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b : std_logic_vector (7 downto 0) := (others=>'0');
signal inpcount : std_logic := '0';
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input counter 0 to 1
-------------------------------------------------------------------------------------------
input_count: process(bitCLK, rst)
begin
if rst = '1' then
inpcount <= '0';
elsif bitCLK'event and bitCLK = '1' then
inpcount <= not inpcount;
end if;
end process;
-------------------------------------------------------------------------------------------
-- input mapping
-------------------------------------------------------------------------------------------
input_map: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case inpcount is
when '0' => word8b(3 downto 0) <= edataIN;
when '1' => word8b(7 downto 4) <= edataIN;
when others =>
end case;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word8bRdy <= inpcount;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN4_direct is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN4_direct;
architecture Behavioral of EPROC_IN4_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b : std_logic_vector (7 downto 0) := (others=>'0');
signal inpcount : std_logic := '0';
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input counter 0 to 1
-------------------------------------------------------------------------------------------
input_count: process(bitCLK, rst)
begin
if rst = '1' then
inpcount <= '0';
elsif bitCLK'event and bitCLK = '1' then
inpcount <= not inpcount;
end if;
end process;
-------------------------------------------------------------------------------------------
-- input mapping
-------------------------------------------------------------------------------------------
input_map: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case inpcount is
when '0' => word8b(3 downto 0) <= edataIN;
when '1' => word8b(7 downto 4) <= edataIN;
when others =>
end case;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word8bRdy <= inpcount;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN4_direct is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN4_direct;
architecture Behavioral of EPROC_IN4_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b : std_logic_vector (7 downto 0) := (others=>'0');
signal inpcount : std_logic := '0';
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input counter 0 to 1
-------------------------------------------------------------------------------------------
input_count: process(bitCLK, rst)
begin
if rst = '1' then
inpcount <= '0';
elsif bitCLK'event and bitCLK = '1' then
inpcount <= not inpcount;
end if;
end process;
-------------------------------------------------------------------------------------------
-- input mapping
-------------------------------------------------------------------------------------------
input_map: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case inpcount is
when '0' => word8b(3 downto 0) <= edataIN;
when '1' => word8b(7 downto 4) <= edataIN;
when others =>
end case;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word8bRdy <= inpcount;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN4_direct is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN4_direct;
architecture Behavioral of EPROC_IN4_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b : std_logic_vector (7 downto 0) := (others=>'0');
signal inpcount : std_logic := '0';
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input counter 0 to 1
-------------------------------------------------------------------------------------------
input_count: process(bitCLK, rst)
begin
if rst = '1' then
inpcount <= '0';
elsif bitCLK'event and bitCLK = '1' then
inpcount <= not inpcount;
end if;
end process;
-------------------------------------------------------------------------------------------
-- input mapping
-------------------------------------------------------------------------------------------
input_map: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case inpcount is
when '0' => word8b(3 downto 0) <= edataIN;
when '1' => word8b(7 downto 4) <= edataIN;
when others =>
end case;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word8bRdy <= inpcount;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
|
-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module Version: 5.8
-- Thu May 9 17:13:50 2019
-- parameterized module component declaration
component fmexg_fifo_5
port (Data: in std_logic_vector(11 downto 0);
WrClock: in std_logic; RdClock: in std_logic;
WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
RPReset: in std_logic; Q: out std_logic_vector(11 downto 0);
Empty: out std_logic; Full: out std_logic;
AlmostEmpty: out std_logic; AlmostFull: out std_logic);
end component;
-- parameterized module component instance
__ : fmexg_fifo_5
port map (Data(11 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__,
RdEn=>__, Reset=>__, RPReset=>__, Q(11 downto 0)=>__, Empty=>__,
Full=>__, AlmostEmpty=>__, AlmostFull=>__);
|
-- fichier testenv.vhdl (C) Yann Guidon 2010
-- version jeu. sept. 2 06:38:43 CEST 2010
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
use work.ghdl_env.all;
entity testEnv is
generic(
environnement: string := "GHDL";
-- exemple d'initialisation très anticipée :
Test_nr : integer := getenv("TEST_NR", 1);
-- définition de la taille d'un tableau :
table_size : integer := getenv("TABLESIZE",24)
);
end testEnv;
architecture test of testEnv is
type int_table is
array (integer range 0 to table_size) of integer;
signal table : int_table;
begin
process
variable a, i: integer;
begin
-- exemple de lecture explicite :
a := getenv(environnement, 5);
for i in 1 to a loop
report "La variable " & environnement
& " est égale à " & integer'image(a);
end loop;
report "$PATH=" & getenv("PATH");
report "$PIKA=" & getenv("PIKA");
wait;
end process;
Test1: if Test_nr=1 generate
assert false report "test par défaut" severity note;
end generate;
Test2: if Test_nr=2 generate
assert false report "test n°2 lancé !" severity note;
end generate;
end test;
|
entity test is
package a is new b generic map(c => (bar) foo);
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:30:27 10/04/2016
-- Design Name:
-- Module Name: instruction_memory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all;
entity instructionMemory is
Port (
--clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (31 downto 0);
reset : in STD_LOGIC;
outInstruction : out STD_LOGIC_VECTOR (31 downto 0));
end instructionMemory;
architecture arqInstructionMemory of instructionMemory is
type rom_type is array (0 to 63) of std_logic_vector (31 downto 0);
impure function InitRomFromFile (RomFileName : in string) return rom_type is
FILE RomFile : text open read_mode is RomFileName;
variable RomFileLine : line;
variable temp_bv : bit_vector(31 downto 0);
variable temp_mem : rom_type;
begin
for I in rom_type'range loop
readline (RomFile, RomFileLine);
read(RomFileLine, temp_bv);
temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
signal instructions : rom_type := InitRomFromFile("testJMPL.data");
begin
--reset,address, instructions)
process(reset,address, instructions)--clk)
begin
--if(rising_edge(clk))then
if(reset = '1')then
outInstruction <= (others=>'0');
else
outInstruction <= instructions(conv_integer(address(5 downto 0)));
end if;
--end if;
end process;
end arqInstructionMemory;
|
library verilog;
use verilog.vl_types.all;
entity FSM_core_vlg_sample_tst is
port(
CLK : in vl_logic;
reset : in vl_logic;
X : in vl_logic;
sampler_tx : out vl_logic
);
end FSM_core_vlg_sample_tst;
|
library verilog;
use verilog.vl_types.all;
entity FSM_core_vlg_sample_tst is
port(
CLK : in vl_logic;
reset : in vl_logic;
X : in vl_logic;
sampler_tx : out vl_logic
);
end FSM_core_vlg_sample_tst;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of ent_a
--
-- Generated
-- by: wig
-- on: Thu Oct 20 06:53:04 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-struct-a.vhd,v 1.2 2005/12/14 12:49:24 wig Exp $
-- $Date: 2005/12/14 12:49:24 $
-- $Log: ent_a-struct-a.vhd,v $
-- Revision 1.2 2005/12/14 12:49:24 wig
-- Updated some testcases (verilog, padio)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.38 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of ent_a
--
architecture struct of ent_a is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_aa
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
x_des_01 : in std_ulogic; -- des_01 lengthy comment
a_des_02 : in std_ulogic; -- des_02 0123456789 0123456789 0123456789
k_des_03 : in std_ulogic; -- des_03 0123456789
-- des_03 0123456789
-- des_03 0123456789
d_des_04 : in std_ulogic; -- des_04 0TEST_MACRO123456789 0123456789
v_des_05 : in std_ulogic; -- des_05 0123456789 0TEST_MACRO123456789 0123456789
t_des_06 : in std_ulogic; -- des_06 0123456789 0123456TEST_MACRO789 0123456789
b_des_07 : in std_ulogic; -- des_07 0123456789 0123456789TEST_MACRO 0123456789
c_des_08 : in std_ulogic; -- des_08 0123456789
-- des_08 0TEST_MACRO123456789
-- des_08 0123456789
c_des__09 : in std_ulogic; -- des_09 0123456789
-- des_09 0123456TEST_MACRO789
-- des_09 0123456789
c_des_10 : in std_ulogic -- des10 0123456789
-- des_10 0123456789TEST_MACRO
-- des_10 0123456789
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal a_des_02 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal b_des_07 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal c_des_08 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal c_des_10 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal c_des__09 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal d_des_04 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal k_des_03 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal t_des_06 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal v_des_05 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal x_des_01 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
a_des_02 <= p_mix_a_des_02_gi; -- __I_I_BIT_PORT
b_des_07 <= p_mix_b_des_07_gi; -- __I_I_BIT_PORT
c_des_08 <= p_mix_c_des_08_gi; -- __I_I_BIT_PORT
c_des_10 <= p_mix_c_des_10_gi; -- __I_I_BIT_PORT
c_des__09 <= p_mix_c_des__09_gi; -- __I_I_BIT_PORT
d_des_04 <= p_mix_d_des_04_gi; -- __I_I_BIT_PORT
k_des_03 <= p_mix_k_des_03_gi; -- __I_I_BIT_PORT
t_des_06 <= p_mix_t_des_06_gi; -- __I_I_BIT_PORT
v_des_05 <= p_mix_v_des_05_gi; -- __I_I_BIT_PORT
x_des_01 <= p_mix_x_des_01_gi; -- __I_I_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
a_des_02 => a_des_02, -- des_02 01...
b_des_07 => b_des_07, -- des_07 01...
c_des_08 => c_des_08, -- des_08 01...
c_des_10 => c_des_10, -- des10 012...
c_des__09 => c_des__09, -- des_09 01...
d_des_04 => d_des_04, -- des_04 0T...
k_des_03 => k_des_03, -- des_03 01...
t_des_06 => t_des_06, -- des_06 01...
v_des_05 => v_des_05, -- des_05 01...
x_des_01 => x_des_01 -- des_01 le...
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
;
-- End of Generated Instance Port Map for inst_ab
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux2a1 is
port( i0, i1, s : in std_logic;
o : out std_logic
);
end mux2a1;
architecture flow of mux2a1 is
begin
o <= i0 when s='0' else i1;
end flow;
-- 2 to 1 mux with XLEN number of inputs and outputs.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.constants.all;
entity muxXLEN2a1 is
port( i0, i1 : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic;
o : out std_logic_vector(XLEN -1 downto 0)
);
end muxXLEN2a1;
architecture flow of muxXLEN2a1 is
begin
o <= i0 when s='0' else i1;
end flow;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_mBuf_128x72_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.k7_mBuf_128x72_pkg.ALL;
ENTITY k7_mBuf_128x72_tb IS
END ENTITY;
ARCHITECTURE k7_mBuf_128x72_arch OF k7_mBuf_128x72_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from k7_mBuf_128x72_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of k7_mBuf_128x72_synth
k7_mBuf_128x72_synth_inst:k7_mBuf_128x72_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 75
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY LatchSR_AB_TB IS
END LatchSR_AB_TB;
ARCHITECTURE behavior OF LatchSR_AB_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LatchSR_AB
PORT(
Sn : IN std_logic;
Rn : IN std_logic;
Q : OUT std_logic;
Qn : OUT std_logic
);
END COMPONENT;
--Inputs
signal Sn : std_logic := '0';
signal Rn : std_logic := '0';
--Outputs
signal Q : std_logic;
signal Qn : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LatchSR_AB PORT MAP (
Sn => Sn,
Rn => Rn,
Q => Q,
Qn => Qn
);
-- Stimulus process
stim_proc: process
begin
-- S = '0' y R = '0'
wait for 100 ns;
-- S = '0' y R = '1'
Rn <= '1';
wait for 100 ns;
-- S = '1' y R = '0'
Rn <= '0';
Sn <= '1';
wait for 100 ns;
-- S = '1' y R = '1'
Rn <= '1';
wait;
end process;
END;
|
library verilog;
use verilog.vl_types.all;
entity mist1032sa_uart_receiver_async2sync is
generic(
N : integer := 1
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iSIGNAL : in vl_logic_vector;
oSIGNAL : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of N : constant is 1;
end mist1032sa_uart_receiver_async2sync;
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.op_codes.all;
entity reg_file is
generic (
debug : boolean := false;
scratch_pad_memory_size : integer := 64
);
port (
clk : in std_logic;
value : in unsigned (7 downto 0);
write_en : in std_logic;
reg0 : out unsigned (7 downto 0);
reg1 : out unsigned (7 downto 0);
reg_address : in unsigned (7 downto 0);
reg_select : in std_logic;
reg_star : in std_logic;
spm_addr_ss : in unsigned (7 downto 0);
spm_ss : in std_logic; -- 0: spm_addr = reg1, 1: spm_addr = spm_addr_ss
spm_we : in std_logic;
spm_rd : in std_logic
);
end reg_file;
architecture Behavioral of reg_file is
-- Logarithms: log*ceil*
-- From PoC-Library https://github.com/VLSI-EDA/PoC
-- ==========================================================================
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then return 0; end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
type reg_file_t is array (31 downto 0) of unsigned(7 downto 0);
signal reg : reg_file_t := (others=>(others=>'0'));
type scratchpad_t is array(integer range <>) of unsigned(7 downto 0);
signal scratchpad : scratchpad_t((scratch_pad_memory_size-1) downto 0) := (others=>(others=>'0'));
constant spm_addr_width : integer := log2ceil(scratch_pad_memory_size); -- address failsafes into a truncated one
signal spm_addr : unsigned ( spm_addr_width-1 downto 0);
signal spm_read : unsigned (7 downto 0);
signal reg0_buf : unsigned ( 7 downto 0);
signal reg0_o : unsigned ( 7 downto 0);
signal reg1_buf : unsigned ( 7 downto 0);
signal reg1_o : unsigned ( 7 downto 0);
signal reg_wr_data : unsigned ( 7 downto 0);
begin
reg0 <= reg0_o;
reg1 <= reg1_o;
reg_wr_data <= spm_read when spm_rd = '1' else value when reg_star = '0' else reg1_buf;
spm_addr <= spm_addr_ss(spm_addr_width -1 downto 0) when spm_ss = '1' else reg1_buf(spm_addr_width -1 downto 0);
spm_read <= scratchpad(to_integer(spm_addr));
reg0_o <= reg(to_integer(reg_select & reg_address(7 downto 4)));
reg1_o <= reg(to_integer(reg_select & reg_address(3 downto 0)));
write_reg : process (clk) begin
if rising_edge(clk) then
if (write_en = '1') then
reg(to_integer(reg_select & reg_address(7 downto 4))) <= reg_wr_data;
end if;
end if;
end process write_reg;
write_spm : process (clk) begin
if rising_edge(clk) then
if (spm_we = '1') then
scratchpad(to_integer(spm_addr)) <= reg0_buf;
end if;
end if;
end process write_spm;
buf_reg0_p : process (clk) begin
if rising_edge(clk) then
reg0_buf <= reg0_o;
reg1_buf <= reg1_o;
end if;
end process buf_reg0_p;
end Behavioral;
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.op_codes.all;
entity reg_file is
generic (
debug : boolean := false;
scratch_pad_memory_size : integer := 64
);
port (
clk : in std_logic;
value : in unsigned (7 downto 0);
write_en : in std_logic;
reg0 : out unsigned (7 downto 0);
reg1 : out unsigned (7 downto 0);
reg_address : in unsigned (7 downto 0);
reg_select : in std_logic;
reg_star : in std_logic;
spm_addr_ss : in unsigned (7 downto 0);
spm_ss : in std_logic; -- 0: spm_addr = reg1, 1: spm_addr = spm_addr_ss
spm_we : in std_logic;
spm_rd : in std_logic
);
end reg_file;
architecture Behavioral of reg_file is
-- Logarithms: log*ceil*
-- From PoC-Library https://github.com/VLSI-EDA/PoC
-- ==========================================================================
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then return 0; end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
type reg_file_t is array (31 downto 0) of unsigned(7 downto 0);
signal reg : reg_file_t := (others=>(others=>'0'));
type scratchpad_t is array(integer range <>) of unsigned(7 downto 0);
signal scratchpad : scratchpad_t((scratch_pad_memory_size-1) downto 0) := (others=>(others=>'0'));
constant spm_addr_width : integer := log2ceil(scratch_pad_memory_size); -- address failsafes into a truncated one
signal spm_addr : unsigned ( spm_addr_width-1 downto 0);
signal spm_read : unsigned (7 downto 0);
signal reg0_buf : unsigned ( 7 downto 0);
signal reg0_o : unsigned ( 7 downto 0);
signal reg1_buf : unsigned ( 7 downto 0);
signal reg1_o : unsigned ( 7 downto 0);
signal reg_wr_data : unsigned ( 7 downto 0);
begin
reg0 <= reg0_o;
reg1 <= reg1_o;
reg_wr_data <= spm_read when spm_rd = '1' else value when reg_star = '0' else reg1_buf;
spm_addr <= spm_addr_ss(spm_addr_width -1 downto 0) when spm_ss = '1' else reg1_buf(spm_addr_width -1 downto 0);
spm_read <= scratchpad(to_integer(spm_addr));
reg0_o <= reg(to_integer(reg_select & reg_address(7 downto 4)));
reg1_o <= reg(to_integer(reg_select & reg_address(3 downto 0)));
write_reg : process (clk) begin
if rising_edge(clk) then
if (write_en = '1') then
reg(to_integer(reg_select & reg_address(7 downto 4))) <= reg_wr_data;
end if;
end if;
end process write_reg;
write_spm : process (clk) begin
if rising_edge(clk) then
if (spm_we = '1') then
scratchpad(to_integer(spm_addr)) <= reg0_buf;
end if;
end if;
end process write_spm;
buf_reg0_p : process (clk) begin
if rising_edge(clk) then
reg0_buf <= reg0_o;
reg1_buf <= reg1_o;
end if;
end process buf_reg0_p;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity CMMaster1Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
COM_ERRORSTATUS : out vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HMASTLOCK : in vl_logic;
HSIZE : in vl_logic_vector(2 downto 0);
HTRANS1 : in vl_logic;
HWRITE : in vl_logic;
HRESP : out vl_logic;
HRDATA : out vl_logic_vector(31 downto 0);
HREADY_M : out vl_logic;
sAddrReady : in vl_logic_vector(7 downto 0);
sDataReady : in vl_logic_vector(7 downto 0);
sHResp : in vl_logic_vector(7 downto 0);
gatedHADDR : out vl_logic_vector(31 downto 0);
gatedHMASTLOCK : out vl_logic;
gatedHSIZE : out vl_logic_vector(2 downto 0);
gatedHTRANS1 : out vl_logic;
gatedHWRITE : out vl_logic;
sAddrSel : out vl_logic_vector(7 downto 0);
sDataSel : out vl_logic_vector(7 downto 0);
prevDataSlaveReady: out vl_logic;
HRDATA_S0 : in vl_logic_vector(31 downto 0);
HREADYOUT_S0 : in vl_logic;
HRDATA_S1 : in vl_logic_vector(31 downto 0);
HREADYOUT_S1 : in vl_logic;
HRDATA_S2 : in vl_logic_vector(31 downto 0);
HREADYOUT_S2 : in vl_logic;
HRDATA_S3 : in vl_logic_vector(31 downto 0);
HREADYOUT_S3 : in vl_logic;
HRDATA_S4 : in vl_logic_vector(31 downto 0);
HREADYOUT_S4 : in vl_logic;
HRDATA_S5 : in vl_logic_vector(31 downto 0);
HREADYOUT_S5 : in vl_logic;
HRDATA_S6 : in vl_logic_vector(31 downto 0);
HREADYOUT_S6 : in vl_logic;
HRDATA_S7 : in vl_logic_vector(31 downto 0);
HREADYOUT_S7 : in vl_logic
);
end CMMaster1Stage;
|
library verilog;
use verilog.vl_types.all;
entity CMMaster1Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
COM_ERRORSTATUS : out vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HMASTLOCK : in vl_logic;
HSIZE : in vl_logic_vector(2 downto 0);
HTRANS1 : in vl_logic;
HWRITE : in vl_logic;
HRESP : out vl_logic;
HRDATA : out vl_logic_vector(31 downto 0);
HREADY_M : out vl_logic;
sAddrReady : in vl_logic_vector(7 downto 0);
sDataReady : in vl_logic_vector(7 downto 0);
sHResp : in vl_logic_vector(7 downto 0);
gatedHADDR : out vl_logic_vector(31 downto 0);
gatedHMASTLOCK : out vl_logic;
gatedHSIZE : out vl_logic_vector(2 downto 0);
gatedHTRANS1 : out vl_logic;
gatedHWRITE : out vl_logic;
sAddrSel : out vl_logic_vector(7 downto 0);
sDataSel : out vl_logic_vector(7 downto 0);
prevDataSlaveReady: out vl_logic;
HRDATA_S0 : in vl_logic_vector(31 downto 0);
HREADYOUT_S0 : in vl_logic;
HRDATA_S1 : in vl_logic_vector(31 downto 0);
HREADYOUT_S1 : in vl_logic;
HRDATA_S2 : in vl_logic_vector(31 downto 0);
HREADYOUT_S2 : in vl_logic;
HRDATA_S3 : in vl_logic_vector(31 downto 0);
HREADYOUT_S3 : in vl_logic;
HRDATA_S4 : in vl_logic_vector(31 downto 0);
HREADYOUT_S4 : in vl_logic;
HRDATA_S5 : in vl_logic_vector(31 downto 0);
HREADYOUT_S5 : in vl_logic;
HRDATA_S6 : in vl_logic_vector(31 downto 0);
HREADYOUT_S6 : in vl_logic;
HRDATA_S7 : in vl_logic_vector(31 downto 0);
HREADYOUT_S7 : in vl_logic
);
end CMMaster1Stage;
|
library verilog;
use verilog.vl_types.all;
entity CMMaster1Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
COM_ERRORSTATUS : out vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HMASTLOCK : in vl_logic;
HSIZE : in vl_logic_vector(2 downto 0);
HTRANS1 : in vl_logic;
HWRITE : in vl_logic;
HRESP : out vl_logic;
HRDATA : out vl_logic_vector(31 downto 0);
HREADY_M : out vl_logic;
sAddrReady : in vl_logic_vector(7 downto 0);
sDataReady : in vl_logic_vector(7 downto 0);
sHResp : in vl_logic_vector(7 downto 0);
gatedHADDR : out vl_logic_vector(31 downto 0);
gatedHMASTLOCK : out vl_logic;
gatedHSIZE : out vl_logic_vector(2 downto 0);
gatedHTRANS1 : out vl_logic;
gatedHWRITE : out vl_logic;
sAddrSel : out vl_logic_vector(7 downto 0);
sDataSel : out vl_logic_vector(7 downto 0);
prevDataSlaveReady: out vl_logic;
HRDATA_S0 : in vl_logic_vector(31 downto 0);
HREADYOUT_S0 : in vl_logic;
HRDATA_S1 : in vl_logic_vector(31 downto 0);
HREADYOUT_S1 : in vl_logic;
HRDATA_S2 : in vl_logic_vector(31 downto 0);
HREADYOUT_S2 : in vl_logic;
HRDATA_S3 : in vl_logic_vector(31 downto 0);
HREADYOUT_S3 : in vl_logic;
HRDATA_S4 : in vl_logic_vector(31 downto 0);
HREADYOUT_S4 : in vl_logic;
HRDATA_S5 : in vl_logic_vector(31 downto 0);
HREADYOUT_S5 : in vl_logic;
HRDATA_S6 : in vl_logic_vector(31 downto 0);
HREADYOUT_S6 : in vl_logic;
HRDATA_S7 : in vl_logic_vector(31 downto 0);
HREADYOUT_S7 : in vl_logic
);
end CMMaster1Stage;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_10_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 06:48:17 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_10_e-e.vhd,v 1.3 2005/11/30 14:04:04 wig Exp $
-- $Date: 2005/11/30 14:04:04 $
-- $Log: inst_10_e-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:04 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_10_e
--
entity inst_10_e is
-- Generics:
generic(
-- Generated Generics for Entity inst_10_e
FOO : integer -- Generic generator __W_NODEFAULT
-- End of Generated Generics for Entity inst_10_e
);
-- Generated Port Declaration:
-- No Generated Port for Entity inst_10_e
end inst_10_e;
--
-- End of Generated Entity inst_10_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
USE ieee.numeric_std.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module is a buffer that can be used the transfer streaming data from *
-- * one clock domain to another. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Dual_Clock_FIFO IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
DW :INTEGER := 29; -- Frame's data width
EW :INTEGER := 1 -- Frame's empty width
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk_stream_in :IN STD_LOGIC;
reset_stream_in :IN STD_LOGIC;
clk_stream_out :IN STD_LOGIC;
reset_stream_out :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bi-Directional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Dual_Clock_FIFO;
ARCHITECTURE Behaviour OF Video_System_Dual_Clock_FIFO IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL fifo_wr_used :STD_LOGIC_VECTOR( 6 DOWNTO 0);
SIGNAL fifo_empty :STD_LOGIC;
SIGNAL q :STD_LOGIC_VECTOR((DW + 2) DOWNTO 0);
-- Internal Registers
-- State Machine Registers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT dcfifo
GENERIC (
intended_device_family :STRING;
lpm_hint :STRING;
lpm_numwords :INTEGER;
lpm_showahead :STRING;
lpm_type :STRING;
lpm_width :INTEGER;
lpm_widthu :INTEGER;
overflow_checking :STRING;
rdsync_delaypipe :INTEGER;
underflow_checking :STRING;
use_eab :STRING;
wrsync_delaypipe :INTEGER
);
PORT (
-- Inputs
wrclk :IN STD_LOGIC;
wrreq :IN STD_LOGIC;
data :IN STD_LOGIC_VECTOR((DW + 2) DOWNTO 0);
rdclk :IN STD_LOGIC;
rdreq :IN STD_LOGIC;
-- Outputs
wrusedw :BUFFER STD_LOGIC_VECTOR( 6 DOWNTO 0);
rdempty :BUFFER STD_LOGIC;
q :BUFFER STD_LOGIC_VECTOR((DW + 2) DOWNTO 0)
-- synopsys translate_off
-- synopsys translate_on
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output assignments
stream_in_ready <= NOT (AND_REDUCE (fifo_wr_used( 6 DOWNTO 4)));
stream_out_empty <= (OTHERS => '0');
stream_out_valid <= NOT fifo_empty;
stream_out_data <= q((DW + 2) DOWNTO 2);
stream_out_endofpacket <= q(1);
stream_out_startofpacket <= q(0);
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
Data_FIFO : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone II",
lpm_hint => "MAXIMIZE_SPEED=7,",
lpm_numwords => 128,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => DW + 3,
lpm_widthu => 7,
overflow_checking => "OFF",
rdsync_delaypipe => 5,
underflow_checking => "OFF",
use_eab => "ON",
wrsync_delaypipe => 5
)
PORT MAP (
-- Inputs
wrclk => clk_stream_in,
wrreq => stream_in_ready AND stream_in_valid,
data => stream_in_data & stream_in_endofpacket & stream_in_startofpacket,
rdclk => clk_stream_out,
rdreq => stream_out_ready AND NOT fifo_empty,
-- Outputs
wrusedw => fifo_wr_used,
rdempty => fifo_empty,
q => q
-- synopsys translate_off
-- synopsys translate_on
);
END Behaviour;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mul_61x61
-- File: mul_61x61.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: 61x61 multiplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity mul_61x61 is
generic (multech : integer := 0;
fabtech : integer := 0);
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of mul_61x61 is
component dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component axcel_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex4_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex6_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex7_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component kintex7_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
begin
gen0 : if multech = 0 generate
mul0 : gen_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
dw0 : if multech = 1 generate
mul0 : dw_mul_61x61 port map (A, B, CLK, PRODUCT);
end generate;
tech0 : if multech = 3 generate
axd0 : if fabtech = axdsp generate
mul0 : axcel_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
xc5v : if fabtech = virtex5 generate
mul0 : virtex4_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
xc6v : if fabtech = virtex6 generate
mul0 : virtex6_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
gen0 : if not ((fabtech = axdsp) or (fabtech = virtex5) or (fabtech = virtex6)) generate
mul0 : gen_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
end generate;
end;
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2011(c) Analog Devices, Inc.
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
-- this module simply generates an fpga output clock from an input clock net
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.all;
entity util_outclk_lvds is
port (
ref_clk : in std_logic; -- clock input
clk_out_p : out std_logic; -- output clock (lvds)
clk_out_n : out std_logic
);
end util_outclk_lvds;
architecture IMP of util_outclk_lvds is
component ODDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port (
R : in std_ulogic;
S : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
C : in std_ulogic;
Q : out std_ulogic
);
end component;
component OBUFDS
generic (
IOSTANDARD : string := "LVDS_25";
CAPACITANCE : string := "DONT_CARE";
DRIVE : integer := 12
);
port (
I : in std_ulogic;
O : out std_ulogic;
OB : out std_ulogic
);
end component;
signal clk_s : std_ulogic;
begin
-- oddr is used to drive output (this reduces skew to IOB->PAD)
i_ddr : ODDR
generic map (
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC"
)
port map (
R => '0',
S => '0',
CE => '1',
D1 => '1',
D2 => '0',
C => ref_clk,
Q => clk_s
);
i_obuf : OBUFDS
generic map (
IOSTANDARD => "LVDS_25"
)
port map (
I => clk_s,
O => clk_out_p,
OB => clk_out_n
);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
|
library ieee;
use ieee.std_logic_1164.all;
entity assert3 is
port (v : std_logic_Vector (7 downto 0);
en : std_logic;
res : out natural);
end;
architecture behav of assert3 is
begin
process (v, en)
begin
res <= 0;
if en = '1' then
for i in v'range loop
if v (i) = '1' then
res <= i;
exit;
end if;
assert i > 3 report "bad v value";
end loop;
end if;
end process;
end behav;
|
-- SIMON 64/128
-- feistel round function operation phi test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_neg_reg_32 IS
END tb_neg_reg_32;
ARCHITECTURE behavior OF tb_neg_reg_32 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT neg_reg_32 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal data_in : std_logic_vector(31 downto 0) := (others => '0'); -- input
--Outputs
signal data_out : std_logic_vector(31 downto 0); -- output
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: neg_reg_32 PORT MAP (
clk => clk,
rst => rst,
data_in => data_in,
data_out => data_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
rst <= '1';
wait for clk_period;
assert data_out = X"00000000"
report "NEG_REG_32 ERROR (r_1)" severity FAILURE;
rst <= '0';
data_in <= X"CAFECAFE";
wait for clk_period;
assert data_out = X"CAFECAFE"
report "NEG_REG_32 ERROR (r_1)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
-- SIMON 64/128
-- feistel round function operation phi test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_neg_reg_32 IS
END tb_neg_reg_32;
ARCHITECTURE behavior OF tb_neg_reg_32 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT neg_reg_32 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal data_in : std_logic_vector(31 downto 0) := (others => '0'); -- input
--Outputs
signal data_out : std_logic_vector(31 downto 0); -- output
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: neg_reg_32 PORT MAP (
clk => clk,
rst => rst,
data_in => data_in,
data_out => data_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
rst <= '1';
wait for clk_period;
assert data_out = X"00000000"
report "NEG_REG_32 ERROR (r_1)" severity FAILURE;
rst <= '0';
data_in <= X"CAFECAFE";
wait for clk_period;
assert data_out = X"CAFECAFE"
report "NEG_REG_32 ERROR (r_1)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
-- SIMON 64/128
-- feistel round function operation phi test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_neg_reg_32 IS
END tb_neg_reg_32;
ARCHITECTURE behavior OF tb_neg_reg_32 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT neg_reg_32 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal data_in : std_logic_vector(31 downto 0) := (others => '0'); -- input
--Outputs
signal data_out : std_logic_vector(31 downto 0); -- output
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: neg_reg_32 PORT MAP (
clk => clk,
rst => rst,
data_in => data_in,
data_out => data_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
rst <= '1';
wait for clk_period;
assert data_out = X"00000000"
report "NEG_REG_32 ERROR (r_1)" severity FAILURE;
rst <= '0';
data_in <= X"CAFECAFE";
wait for clk_period;
assert data_out = X"CAFECAFE"
report "NEG_REG_32 ERROR (r_1)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 08:22:22 PM
-- Design Name:
-- Module Name: decryptionLoopCore_V1_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decryptionLoopCore_V1_tb is
end decryptionLoopCore_V1_tb;
architecture Behavioral of decryptionLoopCore_V1_tb is
component decryptionLoopCore_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
memorySourceSelector : in STD_LOGIC;
keySelector : in STD_LOGIC_VECTOR (1 downto 0);
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component controlUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
loadSourceSelector : out STD_LOGIC;
addRoundKeySelector1 : out STD_LOGIC_VECTOR(1 downto 0);
addRoundKeySelector2 : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
constant clk_period : time := 2ns;
signal CLK, RESET, ENABLE, memorySourceSelector : STD_LOGIC := '0';
signal keySelector : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal cipherKey : STD_LOGIC_VECTOR(127 downto 0) := (others => '0');
signal WORD_IN, WORD_OUT : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
ENABLE <= '1';
uut: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => memorySourceSelector,
keySelector => keySelector,
cipherKey => cipherKey,
WORD_IN => WORD_IN,
WORD_OUT => WORD_OUT);
controlUnit0: controlUnit port map( CLK => CLK,
RESET => RESET,
ENABLE => ENABLE,
loadSourceSelector => memorySourceSelector,
addRoundKeySelector1 => open,
addRoundKeySelector2 => keySelector);
clk_process: process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process;
--Source http://kavaliro.com/wp-content/uploads/2014/03/AES.pdf decrypt ROUND 10
stim_process: process
begin
--Wait for one clk_period to synchronize the control unit.
--During this clk_period, the first addRoundKey would occur.
wait for clk_period;
cipherKey <= x"BFE2BF904559FAB2A16480B4F7F1CBD8";
WORD_IN <= x"013E8EA7";
wait for clk_period;
WORD_IN <= x"3AB004BC";
wait for clk_period;
WORD_IN <= x"8CE23D4D";
wait for clk_period;
WORD_IN <= x"2133B81C";
wait for clk_period;
WORD_IN <= (others => '0');
end process;
end Behavioral;
|
-- --------------------------------------------------------------------
-- "fixed_float_types" package contains types used in the fixed and floating
-- point packages..
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 1.21 $
-- Date : $Date: 2007-09-11 14:52:13-04 $
-- --------------------------------------------------------------------
package fixed_float_types is
-- Types used for generics of fixed_generic_pkg
type fixed_round_style_type is (fixed_round, fixed_truncate);
type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
-- Type used for generics of float_generic_pkg
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round toward positive infinity
round_neginf, -- Round toward negative infinity
round_zero); -- Round toward zero (truncate)
end package fixed_float_types;
|
-- --------------------------------------------------------------------
-- "fixed_float_types" package contains types used in the fixed and floating
-- point packages..
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 1.21 $
-- Date : $Date: 2007-09-11 14:52:13-04 $
-- --------------------------------------------------------------------
package fixed_float_types is
-- Types used for generics of fixed_generic_pkg
type fixed_round_style_type is (fixed_round, fixed_truncate);
type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
-- Type used for generics of float_generic_pkg
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round toward positive infinity
round_neginf, -- Round toward negative infinity
round_zero); -- Round toward zero (truncate)
end package fixed_float_types;
|
-- --------------------------------------------------------------------
-- "fixed_float_types" package contains types used in the fixed and floating
-- point packages..
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 1.21 $
-- Date : $Date: 2007-09-11 14:52:13-04 $
-- --------------------------------------------------------------------
package fixed_float_types is
-- Types used for generics of fixed_generic_pkg
type fixed_round_style_type is (fixed_round, fixed_truncate);
type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
-- Type used for generics of float_generic_pkg
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round toward positive infinity
round_neginf, -- Round toward negative infinity
round_zero); -- Round toward zero (truncate)
end package fixed_float_types;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE spi_master_pkg IS
COMPONENT spi_master IS
GENERIC(
BASE_CLK : INTEGER := 33000000; -- frequency of the isl_clk signal
SCLK_FREQUENCY : INTEGER := 10000; -- frequency of the osl_sclk signal can not be bigger than BASE_CLK/2;
CS_SETUP_CYLES : INTEGER := 10; -- number of isl_clk cycles till the first osl_sclk edge is coming out after oslv_Ss is asserted.
TRANSFER_WIDTH : INTEGER := 32; -- number of bits per transfer
NR_OF_SS : INTEGER := 1; -- number of slave selects
CPOL: STD_LOGIC := '0'; -- clock polarity: 0 = The inactive state of SCK is logic zero, 1 = The inactive state of SCK is logic one.
CPHA: STD_LOGIC := '0'; -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
MSBFIRST: STD_LOGIC := '1'; -- msb first = 0 Data is shifted out with the lsb first, msb first = 1 data is shifted out with the msb first.
SSPOL: STD_LOGIC := '0' -- slave select 0 = slave select zero active. 1 = slave select one active.
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_tx_data : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
isl_tx_start : IN STD_LOGIC;
oslv_rx_data : OUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
osl_rx_done : OUT STD_LOGIC;
islv_ss_activ : IN STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END COMPONENT spi_master;
END PACKAGE spi_master_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.spi_master_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY spi_master IS
GENERIC(
BASE_CLK : INTEGER := 33000000; -- frequency of the isl_clk signal
SCLK_FREQUENCY : INTEGER := 10000; -- frequency of the osl_sclk signal can not be bigger than BASE_CLK/2;
CS_SETUP_CYLES : INTEGER := 10; -- number of isl_clk cycles till the first osl_sclk edge is coming out after oslv_Ss is asserted.
TRANSFER_WIDTH : INTEGER := 32; -- number of bits per transfer
NR_OF_SS : INTEGER := 1; -- number of slave selects
CPOL: STD_LOGIC := '0'; -- clock polarity: 0 = The inactive state of SCK is logic zero, 1 = The inactive state of SCK is logic one.
CPHA: STD_LOGIC := '0'; -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
MSBFIRST: STD_LOGIC := '1'; -- msb first = 0 Data is shifted out with the lsb first, msb first = 1 data is shifted out with the msb first.
SSPOL: STD_LOGIC := '0' -- slave select 0 = slave select zero active. 1 = slave select one active.
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_tx_data : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0); -- data to transmit, should not be changed after tx_start is asserted till rx_done is received
isl_tx_start : IN STD_LOGIC; --if this signal is set to one the transmission starts
oslv_rx_data : OUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0); --received data only valid if rx_done is high
osl_rx_done : OUT STD_LOGIC; --if this signal goes high the receiving of data is finished
islv_ss_activ : IN STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0); -- decides which ss line should be active always write a logic high to set the ss active. the block itselve handles the logic level of the ss depending on the sspol value
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END ENTITY spi_master;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF spi_master IS
CONSTANT NR_OF_TICKS_PER_SCLK_EDGE : INTEGER := BASE_CLK/SCLK_FREQUENCY/2;
CONSTANT CYCLE_COUNTHER_WIDTH : INTEGER := integer(ceil(log2(real(SCLK_FREQUENCY))))+1;
TYPE t_states IS (idle,wait_ss_enable_setup,process_data,wait_ss_disable_setup);
TYPE t_internal_register IS RECORD
state :t_states;
-- synchronize signals
sync_miso_1 : STD_LOGIC;
sync_miso_2 : STD_LOGIC;
clk_count : UNSIGNED(CYCLE_COUNTHER_WIDTH-1 DOWNTO 0);
sclk : STD_LOGIC;
ss : STD_LOGIC_VECTOR(NR_OF_SS-1 DOWNTO 0);
bit_count : INTEGER;
mosi : STD_LOGIC;
leading_edge : STD_LOGIC;
rx_data_buf : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
rx_done : STD_LOGIC;
END RECORD;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,isl_tx_start,islv_ss_activ,islv_tx_data,isl_miso)
VARIABLE vi: t_internal_register;
PROCEDURE change_bitcount IS
BEGIN
IF MSBFIRST = '0' THEN
IF vi.bit_count >= TRANSFER_WIDTH-1 THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := wait_ss_disable_setup;
vi.bit_count := 0;
ELSE
vi.bit_count := vi.bit_count + 1;
END IF;
ELSE
IF vi.bit_count <= 0 THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := wait_ss_disable_setup;
vi.bit_count := TRANSFER_WIDTH-1;
ELSE
vi.bit_count := vi.bit_count - 1;
END IF;
END IF;
END change_bitcount;
BEGIN
-- keep variables stable
vi:=ri;
--standard values
vi.rx_done := '0';
--synchronisation
vi.sync_miso_2 := vi.sync_miso_1;
vi.sync_miso_1 := isl_miso;
CASE vi.state IS
WHEN idle =>
vi.mosi := '0';
vi.ss := (OTHERS => NOT SSPOL);
vi.sclk := CPOL;
IF isl_tx_start = '1' THEN
vi.state := wait_ss_enable_setup;
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
FOR i IN 0 TO NR_OF_SS-1 LOOP
IF islv_ss_activ(i) = '1' THEN
vi.ss(i) := SSPOL;
END IF;
END LOOP;
END IF;
WHEN wait_ss_enable_setup =>
vi.clk_count := vi.clk_count + 1;
IF vi.clk_count >= CS_SETUP_CYLES THEN
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.leading_edge := '1';
vi.rx_data_buf := (OTHERS => '0');
vi.state := process_data;
END IF;
WHEN process_data =>
--toggle sclk
IF vi.clk_count = to_unsigned(0,CYCLE_COUNTHER_WIDTH) THEN
vi.sclk := NOT vi.sclk;
vi.clk_count := to_unsigned(NR_OF_TICKS_PER_SCLK_EDGE,CYCLE_COUNTHER_WIDTH);
IF CPHA = '0' THEN -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK.
IF vi.leading_edge = '1' THEN
vi.rx_data_buf(vi.bit_count) := vi.sync_miso_2;
ELSE --trailing edge
vi.mosi := islv_tx_data(vi.bit_count);
change_bitcount;
END IF;
ELSE -- clock phase 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
IF vi.leading_edge = '1' THEN
vi.mosi := islv_tx_data(vi.bit_count);
ELSE --trailing edge
vi.rx_data_buf(vi.bit_count) := vi.sync_miso_2;
change_bitcount;
END IF;
END IF;
vi.leading_edge := NOT vi.leading_edge;
ELSE
vi.clk_count := vi.clk_count - 1;
END IF;
WHEN wait_ss_disable_setup =>
IF vi.clk_count >= CS_SETUP_CYLES THEN
vi.ss := (OTHERS => NOT SSPOL);
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.state := idle;
vi.rx_done := '1';
ELSE
vi.clk_count := vi.clk_count + 1;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset
IF isl_reset_n = '0' THEN
vi.state := idle;
vi.sclk := CPOL;
vi.clk_count := to_unsigned(0,CYCLE_COUNTHER_WIDTH);
vi.ss := (OTHERS => NOT SSPOL);
IF MSBFIRST = '0' THEN
vi.bit_count := 0;
ELSE
vi.bit_count := TRANSFER_WIDTH-1;
END IF;
vi.mosi := '0';
vi.leading_edge := '0';
vi.rx_data_buf := (OTHERS => '0');
vi.rx_done := '0';
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
--output assignement
osl_sclk <= ri.sclk;
oslv_Ss <= ri.ss;
osl_mosi <= ri.mosi;
osl_rx_done <= ri.rx_done;
oslv_rx_data <= ri.rx_data_buf;
END ARCHITECTURE rtl;
|
package deferred is
type t_int_array is array (natural range <>) of integer;
constant def_arr : t_int_array;
end package;
package body deferred is
constant def_arr : t_int_array := (0 to 2 => 10);
end package body;
|
package deferred is
type t_int_array is array (natural range <>) of integer;
constant def_arr : t_int_array;
end package;
package body deferred is
constant def_arr : t_int_array := (0 to 2 => 10);
end package body;
|
package deferred is
type t_int_array is array (natural range <>) of integer;
constant def_arr : t_int_array;
end package;
package body deferred is
constant def_arr : t_int_array := (0 to 2 => 10);
end package body;
|
package deferred is
type t_int_array is array (natural range <>) of integer;
constant def_arr : t_int_array;
end package;
package body deferred is
constant def_arr : t_int_array := (0 to 2 => 10);
end package body;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MAXIMUM_32b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MAXIMUM_32b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
ASSERT false REPORT "(IMS) MAXIMUM_32b : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
process (INPUT_1, INPUT_2)
begin
if( SIGNED(INPUT_1) > SIGNED(INPUT_2) ) then
OUTPUT_1 <= INPUT_1;
else
OUTPUT_1 <= INPUT_2;
end if;
end process;
-------------------------------------------------------------------------
end;
|
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Timing the entire decoding sequence blocks.
-- provide a proper speed data clock for the interceptor to output data at the same speed as USB.
ENTITY timer is
port(clk, rst:IN STD_LOGIC;
egde_det, f_egde_det, EOP:IN STD_LOGIC; -- edge use to re-synchronize the timer, falling edge start the timer, EOP ends the timer.
data_clk:OUT STD_LOGIC; -- output proper data clock
shift_en:OUT STD_LOGIC -- enable shifting for shift register AND update the NRZI decoder.
);
end timer;
architecture FSM of timer is
type states is (P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12);
signal CS, NS: states;
signal dclk_cur, dclk_nxt: STD_LOGIC;
signal cur_shift_en, nxt_shift_en: STD_LOGIC;
begin
shift_en <= cur_shift_en;
data_clk <= dclk_cur;
seq1:process(clk, rst)
begin
if rst = '0' then
-- reset here
cur_shift_en <= '0';
dclk_cur <= '0';
CS <= P0;
elsif (clk'event and clk = '1') then
CS <= NS;
cur_shift_en <= nxt_shift_en;
dclk_cur <= dclk_nxt;
end if;
end process;
seq2:process(CS, f_egde_det, egde_det, EOP)
begin
NS <= CS;
case CS is
when P0 =>
if f_egde_det = '1' then
NS <= P1;
else
NS <= P0;
end if;
when P1 =>
if egde_det = '1' then
NS <= P1; -- resynchronize
elsif EOP = '1' then
NS <= P0; -- end of packed, return and wait for new SYNC
else
NS <= P2; -- move forward
end if;
when P2 =>
if egde_det = '1' then
NS <= P1; -- resynchronize
elsif EOP = '1' then
NS <= P0; -- end of packed, return and wait for new SYNC
else
NS <= P3; -- move forward
end if;
when P3 =>
if egde_det = '1' then
NS <= P1; -- synchronize
elsif EOP = '1' then
NS <= P0; -- end of packed, return and wait for new SYNC
else
NS <= P4; -- move forward
end if;
when P4 =>
if egde_det = '1' then
NS <= P1; -- resynchronize
elsif EOP = '1' then
NS <= P0; -- end of packed, return and wait for new SYNC
else
NS <= P5; -- move forward
end if;
when P5 =>
if egde_det = '1' then
NS <= P1; -- resynchronize
elsif EOP = '1' then
NS <= P0; -- end of packed, return and wait for new SYNC
else
NS <= P6; -- move forward
end if;
when P6 =>
if egde_det = '1' then
NS <= P1; -- resynchronize
elsif EOP = '1' then
NS <= P0; -- end of packed, return and wait for new SYNC
else
NS <= P7; -- move forward
end if;
when P7 =>
if egde_det = '1' then
NS <= P1; -- resynchronize
elsif EOP = '1' then
NS <= P0; -- end of packed, return and wait for new SYNC
else
NS <= P8; -- move forward
end if;
when P8 =>
if egde_det = '1' then
NS <= P1; -- resynchronize
elsif EOP = '1' then
NS <= P0; -- end of packed, return and wait for new SYNC
else
NS <= P9; -- move forward
end if;
when P9 =>
if egde_det = '1' then
NS <= P1; -- resynchronize
elsif EOP = '1' then
NS <= P0; -- end of packed, return and wait for new SYNC
else
NS <= P10; -- move forward
end if;
when P10 =>
if egde_det = '1' then
NS <= P1; -- resynchronize
elsif EOP = '1' then
NS <= P0; -- end of packed, return and wait for new SYNC
else
NS <= P11; -- move forward
end if;
when P11 =>
if egde_det = '1' then
NS <= P1; -- resynchronize
elsif EOP = '1' then
NS <= P0; -- end of packed, return and wait for new SYNC
else
NS <= P12; -- move forward
end if;
when P12 =>
if egde_det = '1' then
NS <= P1; -- resynchronize
elsif EOP = '1' then
NS <= P0; -- end of packed, return and wait for new SYNC
else
NS <= P1; -- move forward, NOTICE not back to P0, which is a lock state
end if;
end case;
end process;
seq3: process(CS)
begin
case CS is
when P0 =>
dclk_nxt <= '0';
nxt_shift_en <= '0';
when P1 =>
dclk_nxt <= '1'; -- data clock stay high until the middle of packet.
nxt_shift_en <= '0';
when P2 =>
dclk_nxt <= '1'; -- data clock stay high until the middle of packet.
nxt_shift_en <= '0';
when P3 =>
dclk_nxt <= '1'; -- data clock stay high until the middle of packet.
nxt_shift_en <= '0';
when P4 =>
nxt_shift_en <= '1'; -- shift in data at the middle of the entire data packet (a little forward since out clock is slightly less than 12 times faster than USB data.)
dclk_nxt <= '1'; -- data clock stay high until the middle of packet.
when P5 =>
nxt_shift_en <= '0';
dclk_nxt <= '1'; -- data clock stay high until the middle of packet.
when P6 =>
nxt_shift_en <= '0';
dclk_nxt <= '1'; -- data clock stay high until the middle of packet.
when others =>
nxt_shift_en <= '0';
dclk_nxt <= '0';
end case;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity o_ALU_Control is
Port (
-- inputs
i_ALUOp : in STD_LOGIC_VECTOR(1 downto 0); -- From Main Control Unit
i_Inst_Funct : in STD_LOGIC_VECTOR(5 downto 0); -- From Instruction memory
-- outputs
o_ALU_Control : out STD_LOGIC_VECTOR(3 downto 0) -- Control lines to ALU
);
end o_ALU_Control;
architecture Behavioral of o_ALU_Control is
begin
o_ALU_Control(0) <= i_ALUOp(1) and ((not(i_Inst_Funct(3)) and not(i_Inst_Funct(1)) and i_Inst_Funct(2) and i_Inst_Funct(0)) or (i_Inst_Funct(3) and i_Inst_Funct(1) and not(i_Inst_Funct(2)) and not(i_Inst_Funct(0))));
o_ALU_Control(1) <= not(i_ALUOp(1)) or (not(i_Inst_Funct(2)) and not(i_Inst_Funct(0)));
o_ALU_Control(2) <= (not(i_ALUOp(1)) and i_ALUOp(0)) or (i_ALUOp(1) and not(i_Inst_Funct(2)) and i_Inst_Funct(1) and not(i_Inst_Funct(0)));
o_ALU_Control(3) <= '0';
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity o_ALU_Control is
Port (
-- inputs
i_ALUOp : in STD_LOGIC_VECTOR(1 downto 0); -- From Main Control Unit
i_Inst_Funct : in STD_LOGIC_VECTOR(5 downto 0); -- From Instruction memory
-- outputs
o_ALU_Control : out STD_LOGIC_VECTOR(3 downto 0) -- Control lines to ALU
);
end o_ALU_Control;
architecture Behavioral of o_ALU_Control is
begin
o_ALU_Control(0) <= i_ALUOp(1) and ((not(i_Inst_Funct(3)) and not(i_Inst_Funct(1)) and i_Inst_Funct(2) and i_Inst_Funct(0)) or (i_Inst_Funct(3) and i_Inst_Funct(1) and not(i_Inst_Funct(2)) and not(i_Inst_Funct(0))));
o_ALU_Control(1) <= not(i_ALUOp(1)) or (not(i_Inst_Funct(2)) and not(i_Inst_Funct(0)));
o_ALU_Control(2) <= (not(i_ALUOp(1)) and i_ALUOp(0)) or (i_ALUOp(1) and not(i_Inst_Funct(2)) and i_Inst_Funct(1) and not(i_Inst_Funct(0)));
o_ALU_Control(3) <= '0';
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOT1 is port(
a: in std_logic;
z: out std_logic
);
end NOT1;
--
architecture NOT1 of NOT1 is
begin
z <= not a;
end NOT1; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOT1 is port(
a: in std_logic;
z: out std_logic
);
end NOT1;
--
architecture NOT1 of NOT1 is
begin
z <= not a;
end NOT1; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11.02.2016 21:28:53
-- Design Name:
-- Module Name: DataSequencer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DataSequencer is
Port (
clk :in STD_LOGIC;
reset : in STD_LOGIC;
S_FIFO_WriteEn : out STD_LOGIC;
S_FIFO_DataIn : out STD_LOGIC_VECTOR ( 7 downto 0);
S_FIFO_Full : in STD_LOGIC;
--sensor 1
I2C1_FIFO_ReadEn : out STD_LOGIC;
I2C1_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C1_FIFO_Empty : in STD_LOGIC;
--sensor 2
I2C2_FIFO_ReadEn : out STD_LOGIC;
I2C2_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C2_FIFO_Empty : in STD_LOGIC;
--sensor 3
I2C3_FIFO_ReadEn : out STD_LOGIC;
I2C3_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C3_FIFO_Empty : in STD_LOGIC;
--sensor 4
I2C4_FIFO_ReadEn : out STD_LOGIC;
I2C4_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C4_FIFO_Empty : in STD_LOGIC;
--sensor 5
I2C5_FIFO_ReadEn : out STD_LOGIC;
I2C5_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C5_FIFO_Empty : in STD_LOGIC;
--sensor 6
I2C6_FIFO_ReadEn : out STD_LOGIC;
I2C6_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C6_FIFO_Empty : in STD_LOGIC;
--sensor 7
I2C7_FIFO_ReadEn : out STD_LOGIC;
I2C7_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C7_FIFO_Empty : in STD_LOGIC;
--sensor 8
I2C8_FIFO_ReadEn : out STD_LOGIC;
I2C8_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C8_FIFO_Empty : in STD_LOGIC;
--sensor 9
I2C9_FIFO_ReadEn : out STD_LOGIC;
I2C9_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C9_FIFO_Empty : in STD_LOGIC;
--sensor 10
I2C10_FIFO_ReadEn : out STD_LOGIC;
I2C10_FIFO_DataOut : in STD_LOGIC_VECTOR ( 7 downto 0);
I2C10_FIFO_Empty : in STD_LOGIC
);
end DataSequencer;
architecture Behavioral of DataSequencer is
type state_type is ( STATE_WAIT, STATE_STARTREAD, STATE_ENDREAD, STATE_WAITFULL, STATE_STARTWRITE, STATE_FINISHWRITE,STATE_CLOCKIN, STATE_UPDATEMUX, STATE_EOL);
signal state_reg: state_type := STATE_WAIT;
constant Maxtimeout : positive := 4000;
signal multiplexerState : INTEGER RANGE 0 to 9 := 0;
signal timeoutCount : INTEGER RANGE 0 to Maxtimeout +5:= 0; -- wait 1ms before a timeout.
signal currentByteCount : INTEGER RANGE 0 to 8:= 0; --6 bytes of data per sensor.
begin
process (clk, S_FIFO_Full, reset) -- process to handle the next state
begin
if (reset = '1') then
--reset state:
S_FIFO_WriteEn <= '0';
state_reg <= STATE_WAIT;
multiplexerState <= 0;
timeoutCount <= 0;
I2C1_FIFO_ReadEn <= '0';
I2C2_FIFO_ReadEn <= '0';
I2C3_FIFO_ReadEn <= '0';
I2C4_FIFO_ReadEn <= '0';
I2C5_FIFO_ReadEn <= '0';
I2C6_FIFO_ReadEn <= '0';
I2C7_FIFO_ReadEn <= '0';
I2C8_FIFO_ReadEn <= '0';
I2C9_FIFO_ReadEn <= '0';
I2C10_FIFO_ReadEn <= '0';
else
if rising_edge (clk) then
case state_reg is
when STATE_WAIT =>
case multiplexerState is
when 0 =>
if (I2C1_FIFO_Empty = '1') then
if (currentByteCount = 0) then
-- timeoutCount <= timeoutCount + 1; -- increase the timeout count.
-- if (timeoutCount = Maxtimeout) then
-- state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
-- else
state_reg <= STATE_WAIT; -- else carry on waiting.
-- end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 1 =>
if (I2C2_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 2 =>
if (I2C3_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 3 =>
if (I2C4_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 4 =>
if (I2C5_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 5 =>
if (I2C6_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 6 =>
if (I2C7_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 7 =>
if (I2C8_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 8 =>
if (I2C9_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when 9 =>
if (I2C10_FIFO_Empty = '1') then
if (currentByteCount = 0) then
timeoutCount <= timeoutCount + 1; -- increase the timeout count.
if (timeoutCount = Maxtimeout) then
state_reg <= STATE_UPDATEMUX; -- timeout has occured, move to the next sensor.
else
state_reg <= STATE_WAIT; -- else carry on waiting.
end if;
else
state_reg <= STATE_WAIT;
end if;
else
state_reg <= STATE_STARTREAD;
end if;
when others =>
end case;
when STATE_STARTREAD =>
-- request the data
case (multiplexerState) is
when 0 =>
I2C1_FIFO_ReadEn <= '1';
when 1 =>
I2C2_FIFO_ReadEn <= '1';
when 2 =>
I2C3_FIFO_ReadEn <= '1';
when 3 =>
I2C4_FIFO_ReadEn <= '1';
when 4 =>
I2C5_FIFO_ReadEn <= '1';
when 5 =>
I2C6_FIFO_ReadEn <= '1';
when 6 =>
I2C7_FIFO_ReadEn <= '1';
when 7 =>
I2C8_FIFO_ReadEn <= '1';
when 8 =>
I2C9_FIFO_ReadEn <= '1';
when 9 =>
I2C10_FIFO_ReadEn <= '1';
when others =>
end case;
state_reg <= STATE_ENDREAD;
when STATE_ENDREAD =>
--finish the request
case (multiplexerState) is
when 0 =>
I2C1_FIFO_ReadEn <= '0';
when 1 =>
I2C2_FIFO_ReadEn <= '0';
when 2 =>
I2C3_FIFO_ReadEn <= '0';
when 3 =>
I2C4_FIFO_ReadEn <= '0';
when 4 =>
I2C5_FIFO_ReadEn <= '0';
when 5 =>
I2C6_FIFO_ReadEn <= '0';
when 6 =>
I2C7_FIFO_ReadEn <= '0';
when 7 =>
I2C8_FIFO_ReadEn <= '0';
when 8 =>
I2C9_FIFO_ReadEn <= '0';
when 9 =>
I2C10_FIFO_ReadEn <= '0';
when others =>
end case;
state_reg <= STATE_CLOCKIN;
when STATE_CLOCKIN =>
--clock the data out
case (multiplexerState) is
when 0 =>
S_FIFO_DataIn <= I2C1_FIFO_DataOut;
when 1 =>
S_FIFO_DataIn <= I2C2_FIFO_DataOut;
when 2 =>
S_FIFO_DataIn <= I2C3_FIFO_DataOut;
when 3 =>
S_FIFO_DataIn <= I2C4_FIFO_DataOut;
when 4 =>
S_FIFO_DataIn <= I2C5_FIFO_DataOut;
when 5 =>
S_FIFO_DataIn <= I2C6_FIFO_DataOut;
when 6 =>
S_FIFO_DataIn <= I2C7_FIFO_DataOut;
when 7 =>
S_FIFO_DataIn <= I2C8_FIFO_DataOut;
when 8 =>
S_FIFO_DataIn <= I2C9_FIFO_DataOut;
when 9 =>
S_FIFO_DataIn <= I2C10_FIFO_DataOut;
when others =>
end case;
if ('0' = S_FIFO_Full) then
state_reg <= STATE_STARTWRITE;
else
state_reg <= STATE_WAITFULL;
end if;
when STATE_WAITFULL =>
if (S_FIFO_Full = '0') then
state_reg <= STATE_STARTWRITE;
else
state_reg <= STATE_WAITFULL;
end if;
when STATE_STARTWRITE =>
S_FIFO_WriteEn <= '1';
state_reg <= STATE_FINISHWRITE;
currentByteCount <= currentByteCount +1; --- update the byte count.
when STATE_FINISHWRITE =>
S_FIFO_WriteEn <= '0';
state_reg <= STATE_UPDATEMUX;
when STATE_UPDATEMUX => -- when a read has just completed or a timeout has occured.
-- this is called when one of these things have happened:
--> TIMEOUT - reading a sensor has timed out -->
--> IF A TIMEOUT HAS HAPPENED ON SENSOR 10 --> WRITE EOL
--> ELSE just move onto next sensor
--> FINISH BYTE WRITE --> A byte has just finished writing
--> FINISH EOL - an EOL has just been written --> an EOL has just been written
--> FINISH SENSOR READ - 6 bytes have been read --> move onto the next sensor
--> FINISH BYTE READ - a byte has just been read --> read the next one
if (timeoutCount >= (MaxTimeout) AND CurrentByteCount = 0) then -- this has been called by a timeout.
if (multiplexerState = 9) then -- sensor 10 timeout, write the EOL.
state_reg <= STATE_EOL; -- write the EOL.
else
timeoutCount <= 0; -- reset the timeout counter
multiplexerState <= multiplexerState +1; -- move onto the next sensor.
state_reg <= STATE_WAIT;
end if;
else
-- a byte was just written.
if ((multiplexerState = 9 AND timeoutCount >= (MaxTimeout)) OR (currentByteCount = 7)) then -- the EOL was just written, start the read all over again.
timeoutCount<=0;
multiplexerState <= 0;
currentByteCount <=0;
state_reg <= STATE_WAIT;
elsif (currentByteCount = 6) then -- the final byte of a sensor read was written
if (multiplexerState = 9) then
timeoutCount <=0;
state_reg <= STATE_EOL;
else
timeoutCount<=0;
multiplexerState <= multiplexerState +1;
currentByteCount<=0;
end if;
else -- a byte has been read
state_reg <= STATE_WAIT;--don't need to do anything, just continue.
end if;
end if;
when STATE_EOL =>
S_FIFO_DataIn <= "11111111";
state_reg <= STATE_STARTWRITE;
when others =>
state_reg <= STATE_WAIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 8;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity freq_man is
port
(
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
clk_out1 : out std_logic;
clk_out2 : out std_logic;
clk_out3 : out std_logic;
locked : out std_logic
);
end freq_man;
architecture syn of freq_man is
signal clk_in1 : std_logic;
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_int1 : std_logic;
signal clkout0b_unused : std_logic;
signal clk_int2 : std_logic;
signal clkout1b_unused : std_logic;
signal clk_int3 : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
signal psdone_unused : std_logic;
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
clkin1_ibufgds : IBUFDS
port map
(O => clk_in1,
I => clk_in1_p,
IB => clk_in1_n);
iplle : PLLE2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 32,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 10.0)
port map
(
CLKFBOUT => clkfbout,
CLKOUT0 => clk_int1,
CLKOUT1 => clk_int2,
CLKOUT2 => clk_int3,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKFBIN => clkfbout,
CLKIN1 => clk_in1,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
LOCKED => locked,
PWRDWN => '0',
RST => '0');
clkout1_buf : BUFG
port map
(O => clk_out1,
I => clk_int1);
clkout2_buf : BUFG
port map
(O => clk_out2,
I => clk_int2);
clkout3_buf : BUFG
port map
(O => clk_out3,
I => clk_int3);
end syn;
|
architecture RTL of FIFO is
ATTRIBUTE max_delay : time;
ATTRIBUTE MAX_DELAY : TIME;
begin
end architecture RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity OR2 is port(
a,b: in std_logic;
z: out std_logic
);
end OR2;
--
architecture OR2 of OR2 is
begin
z <=a or b;
end OR2; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package constraints is
-- code from book (in text)
group port_pair is ( signal, signal );
attribute max_prop_delay : time;
-- end code from book
end package constraints;
-- code from book
library ieee; use ieee.std_logic_1164.all;
use work.constraints.port_pair, work.constraints.max_prop_delay;
entity clock_buffer is
port ( clock_in : in std_logic;
clock_out1, clock_out2, clock_out3 : out std_logic );
group clock_to_out1 : port_pair ( clock_in, clock_out1 );
group clock_to_out2 : port_pair ( clock_in, clock_out2 );
group clock_to_out3 : port_pair ( clock_in, clock_out3 );
attribute max_prop_delay of clock_to_out1 : group is 2 ns;
attribute max_prop_delay of clock_to_out2 : group is 2 ns;
attribute max_prop_delay of clock_to_out3 : group is 2 ns;
end entity clock_buffer;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package constraints is
-- code from book (in text)
group port_pair is ( signal, signal );
attribute max_prop_delay : time;
-- end code from book
end package constraints;
-- code from book
library ieee; use ieee.std_logic_1164.all;
use work.constraints.port_pair, work.constraints.max_prop_delay;
entity clock_buffer is
port ( clock_in : in std_logic;
clock_out1, clock_out2, clock_out3 : out std_logic );
group clock_to_out1 : port_pair ( clock_in, clock_out1 );
group clock_to_out2 : port_pair ( clock_in, clock_out2 );
group clock_to_out3 : port_pair ( clock_in, clock_out3 );
attribute max_prop_delay of clock_to_out1 : group is 2 ns;
attribute max_prop_delay of clock_to_out2 : group is 2 ns;
attribute max_prop_delay of clock_to_out3 : group is 2 ns;
end entity clock_buffer;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package constraints is
-- code from book (in text)
group port_pair is ( signal, signal );
attribute max_prop_delay : time;
-- end code from book
end package constraints;
-- code from book
library ieee; use ieee.std_logic_1164.all;
use work.constraints.port_pair, work.constraints.max_prop_delay;
entity clock_buffer is
port ( clock_in : in std_logic;
clock_out1, clock_out2, clock_out3 : out std_logic );
group clock_to_out1 : port_pair ( clock_in, clock_out1 );
group clock_to_out2 : port_pair ( clock_in, clock_out2 );
group clock_to_out3 : port_pair ( clock_in, clock_out3 );
attribute max_prop_delay of clock_to_out1 : group is 2 ns;
attribute max_prop_delay of clock_to_out2 : group is 2 ns;
attribute max_prop_delay of clock_to_out3 : group is 2 ns;
end entity clock_buffer;
-- end code from book
|
-- NEED RESULT: *** An assertion violation should follow
-- NEED RESULT: ARCH00026: Assertion Violation only occurs when condition is false passed
-- NEED RESULT: *** No assertion violation should follow
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00026
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.2 (6)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00026_Test_Bench(ARCH00026_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
--
-- NOTES:
--
-- Verify that assertion messages match output comment messages
--
entity ENT00026_Test_Bench is
signal False_Signal : Boolean := false ;
end ENT00026_Test_Bench ;
use WORK.STANDARD_TYPES.all;
architecture ARCH00026_Test_Bench of ENT00026_Test_Bench is
begin
P1 :
process ( False_Signal )
begin
print ( "*** An assertion violation should follow " ) ;
assert False_Signal
report "ARCH00026: Assertion Violation only occurs when " &
"condition is false passed"
severity NOTE ;
end process P1 ;
P2 :
process ( False_Signal )
begin
print ( "*** No assertion violation should follow " ) ;
assert Not False_Signal
report "ARCH00026: Assertion Violation only occurs when " &
"condition is false failed"
severity NOTE ;
end process P2 ;
end ARCH00026_Test_Bench ;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2011 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_mapper is
port (
clock : in std_logic;
reset : in std_logic;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
control : in t_sid_control;
sid_addr : out unsigned(7 downto 0);
sid_wren : out std_logic;
sid_wdata : out std_logic_vector(7 downto 0);
sid_rdata : in std_logic_vector(7 downto 0) );
end sid_mapper;
architecture mapping of sid_mapper is
signal sid_wren_l : std_logic;
signal sid_wren_r : std_logic;
signal sid_wren_d : std_logic;
signal sid_addr_l : unsigned(7 downto 0);
signal sid_addr_r : unsigned(7 downto 0);
signal sid_addr_d : unsigned(7 downto 0);
signal sid_wdata_l : std_logic_vector(7 downto 0);
signal sid_wdata_d : std_logic_vector(7 downto 0);
begin
slot_resp.data <= sid_rdata;
sid_wren <= sid_wren_l or sid_wren_d;
sid_addr <= sid_addr_d when sid_wren_d='1' else sid_addr_l;
sid_wdata <= sid_wdata_l; -- should work, but it's not neat!
process(clock)
begin
if rising_edge(clock) then
sid_wren_l <= '0';
sid_wren_r <= '0';
sid_wren_d <= sid_wren_r;
sid_addr_d <= sid_addr_r;
sid_wdata_l <= slot_req.data;
sid_wdata_d <= sid_wdata_l;
if slot_req.io_write='1' then
sid_addr_l <= slot_req.io_address(7 downto 0);
sid_addr_r <= slot_req.io_address(7 downto 0);
else
sid_addr_l <= slot_req.bus_address(7 downto 0);
sid_addr_r <= slot_req.bus_address(7 downto 0);
end if;
-- check for left channel access
if control.enable_left='1' then
if slot_req.bus_write='1' then
if control.snoop_left='1' and slot_req.bus_address(15 downto 12)=X"D" then
if control.extend_left='1' then
if slot_req.bus_address(11 downto 7)=control.base_left(11 downto 7) then
sid_addr_l(7) <= '0';
sid_wren_l <= '1';
end if;
else -- just 3 voices
if slot_req.bus_address(11 downto 5)=control.base_left(11 downto 5) then
sid_wren_l <= '1';
sid_addr_l(7 downto 5) <= "000"; -- truncated address
end if;
end if;
end if;
elsif slot_req.io_write='1' then
if control.snoop_left='0' then
if control.extend_left='1' and slot_req.io_address(8 downto 7)=control.base_left(8 downto 7) then
sid_addr_l(7) <= '0';
sid_wren_l <= '1';
elsif control.extend_left='0' and slot_req.io_address(8 downto 5)=control.base_left(8 downto 5) then
sid_addr_l(7 downto 5) <= "000";
sid_wren_l <= '1';
end if;
end if;
end if;
end if;
-- check for right channel access
if control.enable_right='1' then
if slot_req.bus_write='1' then
if control.snoop_right='1' and slot_req.bus_address(15 downto 12)=X"D" then
if control.extend_right='1' then
if slot_req.bus_address(11 downto 7)=control.base_right(11 downto 7) then
sid_addr_r(7) <= '1';
sid_wren_r <= '1';
end if;
else -- just 3 voices
if slot_req.bus_address(11 downto 5)=control.base_right(11 downto 5) then
sid_wren_r <= '1';
sid_addr_r(7 downto 5) <= "100"; -- truncated address
end if;
end if;
end if;
elsif slot_req.io_write='1' then
if control.snoop_right='0' then
if control.extend_right='1' and slot_req.io_address(8 downto 7)=control.base_right(8 downto 7) then
sid_addr_r(7) <= '1';
sid_wren_r <= '1';
elsif control.extend_right='0' and slot_req.io_address(8 downto 5)=control.base_right(8 downto 5) then
sid_addr_r(7 downto 5) <= "100";
sid_wren_r <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
slot_resp.nmi <= '0';
slot_resp.irq <= '0';
slot_resp.reg_output <= '0';
end mapping;
-- Mapping options are as follows:
-- STD $D400-$D41F: Snoop='1' Base=$40. Extend='0' (bit 11...5 are significant)
-- STD $D500-$D51F: Snoop='1' Base=$50. Extend='0'
-- STD $DE00-$DE1F: Snoop='0' Base=$E0. Extend='0' (bit 8...5 are significant)
-- STD $DF00-$DF1F: Snoop='0' Base=$F0. Extend='0'
-- EXT $DF80-$DFFF: Snoop='0' Base=$F8. Extend='1' (bit 8...7 are significant)
-- EXT $D600-$D67F: Snoop='1' Base=$60. Extend='1' (bit 11..7 are significant)
-- .. etc
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: pre-normalization entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library work;
use work.fpupack.all;
entity pre_norm_mul is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
exp_10_o : out std_logic_vector(EXP_WIDTH+1 downto 0);
fracta_24_o : out std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
fractb_24_o : out std_logic_vector(FRAC_WIDTH downto 0)
);
end pre_norm_mul;
architecture rtl of pre_norm_mul is
signal s_expa, s_expb : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_fracta, s_fractb : std_logic_vector(FRAC_WIDTH-1 downto 0);
signal s_exp_10_o, s_expa_in, s_expb_in : std_logic_vector(EXP_WIDTH+1 downto 0);
signal s_opa_dn, s_opb_dn : std_logic;
begin
s_expa <= opa_i(30 downto 23);
s_expb <= opb_i(30 downto 23);
s_fracta <= opa_i(22 downto 0);
s_fractb <= opb_i(22 downto 0);
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
exp_10_o <= s_exp_10_o;
end if;
end process;
-- opa or opb is denormalized
s_opa_dn <= not or_reduce(s_expa);
s_opb_dn <= not or_reduce(s_expb);
fracta_24_o <= not(s_opa_dn) & s_fracta;
fractb_24_o <= not(s_opb_dn) & s_fractb;
s_expa_in <= ("00"&s_expa) + ("000000000"&s_opa_dn);
s_expb_in <= ("00"&s_expb) + ("000000000"&s_opb_dn);
s_exp_10_o <= s_expa_in + s_expb_in - "0001111111";
end rtl;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: pre-normalization entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library work;
use work.fpupack.all;
entity pre_norm_mul is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
exp_10_o : out std_logic_vector(EXP_WIDTH+1 downto 0);
fracta_24_o : out std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
fractb_24_o : out std_logic_vector(FRAC_WIDTH downto 0)
);
end pre_norm_mul;
architecture rtl of pre_norm_mul is
signal s_expa, s_expb : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_fracta, s_fractb : std_logic_vector(FRAC_WIDTH-1 downto 0);
signal s_exp_10_o, s_expa_in, s_expb_in : std_logic_vector(EXP_WIDTH+1 downto 0);
signal s_opa_dn, s_opb_dn : std_logic;
begin
s_expa <= opa_i(30 downto 23);
s_expb <= opb_i(30 downto 23);
s_fracta <= opa_i(22 downto 0);
s_fractb <= opb_i(22 downto 0);
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
exp_10_o <= s_exp_10_o;
end if;
end process;
-- opa or opb is denormalized
s_opa_dn <= not or_reduce(s_expa);
s_opb_dn <= not or_reduce(s_expb);
fracta_24_o <= not(s_opa_dn) & s_fracta;
fractb_24_o <= not(s_opb_dn) & s_fractb;
s_expa_in <= ("00"&s_expa) + ("000000000"&s_opa_dn);
s_expb_in <= ("00"&s_expb) + ("000000000"&s_opb_dn);
s_exp_10_o <= s_expa_in + s_expb_in - "0001111111";
end rtl;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: pre-normalization entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library work;
use work.fpupack.all;
entity pre_norm_mul is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
exp_10_o : out std_logic_vector(EXP_WIDTH+1 downto 0);
fracta_24_o : out std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
fractb_24_o : out std_logic_vector(FRAC_WIDTH downto 0)
);
end pre_norm_mul;
architecture rtl of pre_norm_mul is
signal s_expa, s_expb : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_fracta, s_fractb : std_logic_vector(FRAC_WIDTH-1 downto 0);
signal s_exp_10_o, s_expa_in, s_expb_in : std_logic_vector(EXP_WIDTH+1 downto 0);
signal s_opa_dn, s_opb_dn : std_logic;
begin
s_expa <= opa_i(30 downto 23);
s_expb <= opb_i(30 downto 23);
s_fracta <= opa_i(22 downto 0);
s_fractb <= opb_i(22 downto 0);
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
exp_10_o <= s_exp_10_o;
end if;
end process;
-- opa or opb is denormalized
s_opa_dn <= not or_reduce(s_expa);
s_opb_dn <= not or_reduce(s_expb);
fracta_24_o <= not(s_opa_dn) & s_fracta;
fractb_24_o <= not(s_opb_dn) & s_fractb;
s_expa_in <= ("00"&s_expa) + ("000000000"&s_opa_dn);
s_expb_in <= ("00"&s_expb) + ("000000000"&s_opb_dn);
s_exp_10_o <= s_expa_in + s_expb_in - "0001111111";
end rtl;
|
entity tb_block02 is
end tb_block02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_block02 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.block02
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
entity clear_video_ram is
generic(
N_bits_row: natural := 2;
N_bits_col: natural := 2;
N_ROWS: natural := 2;
N_COLS: natural := 2
);
port(
clock: in std_logic;
reset: in std_logic;
enable: in std_logic;
row_counter: out std_logic_vector(N_bits_row-1 downto 0);
col_counter: out std_logic_vector(N_bits_col-1 downto 0);
carry_out: out std_logic
);
end;
architecture clear_video_ram_arch of clear_video_ram is
signal row_enable_aux : std_logic := '0';
signal row_enable : std_logic := '0';
begin
col_counter_inst: entity work.counter
generic map(
N_bits => N_bits_col,
MAX_COUNT => N_COLS-1
) port map(
clock => clock,
reset => reset,
enable => enable,
counter_output => col_counter,
carry_out => row_enable_aux
);
-- Contador de filas
row_enable <= enable AND row_enable_aux;
row_counter_inst: entity work.counter
generic map(
N_bits => N_bits_row,
MAX_COUNT => N_ROWS-1
) port map(
clock => clock,
reset => reset,
enable => row_enable,
counter_output => row_counter,
carry_out => carry_out
);
end clear_video_ram_arch;
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
PACKAGE int_to_7seg_pack IS
TYPE logic_vector_array IS ARRAY (0 TO 9) OF STD_LOGIC_VECTOR (7 DOWNTO 0);
END PACKAGE int_to_7seg_pack;
PACKAGE BODY int_to_7seg_pack IS
PROCEDURE int_to_bcd(SIGNAL int_val : IN INTEGER; SIGNAL bcd2, bcd1, bcd0: OUT INTEGER) IS
VARIABLE temp: INTEGER:=int_val;
BEGIN
bcd0<=temp MOD 10;
temp:=temp/10;
bcd1<=temp MOD 10;
bcd2<=temp/10;
END int_to_bcd;
END int_to_7seg_pack; |
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_im is
port(
clk : in vl_logic;
jdo : in vl_logic_vector(37 downto 0);
jrst_n : in vl_logic;
reset_n : in vl_logic;
take_action_tracectrl: in vl_logic;
take_action_tracemem_a: in vl_logic;
take_action_tracemem_b: in vl_logic;
take_no_action_tracemem_a: in vl_logic;
trc_ctrl : in vl_logic_vector(15 downto 0);
tw : in vl_logic_vector(35 downto 0);
tracemem_on : out vl_logic;
tracemem_trcdata: out vl_logic_vector(35 downto 0);
tracemem_tw : out vl_logic;
trc_enb : out vl_logic;
trc_im_addr : out vl_logic_vector(6 downto 0);
trc_wrap : out vl_logic;
xbrk_wrap_traceoff: out vl_logic
);
end finalproject_cpu_nios2_oci_im;
|
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DSP-Crowd project --
-- https://www.dsp-crowd.com --
-- --
-- Author(s): --
-- - Johannes Natter, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2017 Authors and www.dsp-crowd.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tbd_rr_base is
generic
(
use_sdram_pll : std_ulogic := '1';
num_gpios : natural := 64
);
port
(
clock_50mhz : in std_ulogic;
keys : in std_ulogic_vector(1 downto 0);
switches : in std_ulogic_vector(3 downto 0);
leds : out std_ulogic_vector(7 downto 0);
spi_cs : in std_ulogic_vector(1 downto 0);
spi_clk : in std_ulogic;
spi_mosi : in std_ulogic;
spi_miso : out std_ulogic;
spi_epcs_cs : out std_ulogic;
spi_epcs_clk : out std_ulogic;
spi_epcs_mosi : out std_ulogic;
spi_epcs_miso : in std_ulogic;
arReconf : in std_ulogic;
gpios : inout std_logic_vector(0 to num_gpios - 1)
);
end tbd_rr_base;
architecture rtl of tbd_rr_base is
signal reset_done : std_ulogic := '0';
signal n_reset_async : std_logic;
signal inputs_unsynced : std_ulogic_vector(switches'length downto 0);
signal inputs_synced : std_ulogic_vector(inputs_unsynced'range);
signal inputs_synced_debounced : std_ulogic_vector(inputs_synced'range);
signal key_0_synced_debounced : std_ulogic;
signal switches_synced_debounced : std_ulogic_vector(switches'range);
signal spi_unsynced : std_ulogic_vector(2 downto 0);
signal spi_synced : std_ulogic_vector(2 downto 0);
signal spi_cs_user_synced : std_ulogic;
signal spi_clk_synced : std_ulogic;
signal spi_mosi_synced : std_ulogic;
signal spi_slave_miso : std_ulogic;
signal spi_slave_data : std_ulogic_vector(7 downto 0);
signal spi_slave_data_is_id : std_ulogic;
signal spi_slave_data_valid : std_ulogic;
signal spi_slave_input_state : std_ulogic_vector(0 to num_gpios - 1);
signal spi_slave_input_state_valid : std_ulogic_vector(0 to num_gpios - 1);
signal spi_slave_cmd_done : std_ulogic_vector(0 to num_gpios - 1);
signal spi_slave_input_state_res : std_ulogic_vector(0 to num_gpios - 1);
signal spi_slave_input_state_valid_res : std_ulogic_vector(0 to num_gpios - 1);
signal spi_slave_cmd_done_res : std_ulogic_vector(0 to num_gpios - 1);
signal gpio_in : std_logic_vector(0 to num_gpios - 1);
signal gpio_out : std_logic_vector(0 to num_gpios - 1);
signal gpio_en : std_logic_vector(0 to num_gpios - 1);
begin
-- Reconfiguration unit
reconfUnit: entity work.altremotePulsed(rtl)
port map
(
clock => clock_50mhz,
nResetAsync => n_reset_async,
reconf => arReconf
);
-- Give epcs64 signals to external user
-- No need to synchronize. Signals are not used within system clock
spi_epcs_cs <= spi_cs(0);
spi_epcs_clk <= spi_clk;
spi_epcs_mosi <= spi_mosi;
-- Important: MISO must not drive signal if epcs64 is not selected
spi_miso <= spi_epcs_miso when spi_cs(0) = '0' else
spi_slave_miso when spi_cs_user_synced = '0' else 'Z';
-- Synchronize inputs
inputs_unsynced <= switches & keys(0);
key_sync: entity work.input_sync(rtl)
generic map
(
num_inputs => inputs_unsynced'length,
num_sync_stages => 1
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
unsynced_inputs => inputs_unsynced,
synced_outputs => inputs_synced
);
-- Debounce inputs
key_debounce: entity work.input_debounce(rtl)
generic map
(
num_inputs => inputs_synced'length
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
synced_inputs => inputs_synced,
debounced_outputs => inputs_synced_debounced
);
key_0_synced_debounced <= inputs_synced_debounced(0);
switches_synced_debounced <= inputs_synced_debounced(inputs_synced_debounced'high downto 1);
-- Synchronize SPI
spi_unsynced <= spi_cs(1) & spi_clk & spi_mosi;
spi_sync: entity work.input_sync(rtl)
generic map
(
num_inputs => spi_unsynced'length,
num_sync_stages => 2
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
unsynced_inputs => spi_unsynced,
synced_outputs => spi_synced
);
spi_cs_user_synced <= spi_synced(2);
spi_clk_synced <= spi_synced(1);
spi_mosi_synced <= spi_synced(0);
-- Hardware-is-alive-LED
hardware_is_alive_led: entity work.frequencyDivider(rtl)
generic map
(
divideBy => 25E7
)
port map
(
clock => clock_50mhz,
nResetAsync => n_reset_async,
output => leds(0)
);
leds(7 downto 1) <= (others => '0');
-- SPI-Slave
spislave: entity work.spi_slave(rtl)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
spi_cs => spi_cs_user_synced,
spi_clk => spi_clk_synced,
spi_mosi => spi_mosi_synced,
spi_miso => spi_slave_miso,
data => spi_slave_data,
data_is_id => spi_slave_data_is_id,
data_valid => spi_slave_data_valid,
input_state => spi_slave_input_state_res(0),
input_state_valid => spi_slave_input_state_valid_res(0),
cmd_done => spi_slave_cmd_done_res(0)
);
-- GPIOs
gpio_ext_all: for i in 0 to num_gpios - 1 generate
gpio_ext_n: entity work.gpio_ext(rtl)
generic map
(
my_id => i
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
spi_cs => spi_cs_user_synced,
data => spi_slave_data,
data_is_id => spi_slave_data_is_id,
data_valid => spi_slave_data_valid,
input_state => spi_slave_input_state(i),
input_state_valid => spi_slave_input_state_valid(i),
cmd_done => spi_slave_cmd_done(i),
gpio_in => gpio_in(i),
gpio_out => gpio_out(i),
gpio_en => gpio_en(i)
);
gpios(i) <= gpio_out(i) when gpio_en(i) = '1' else 'Z';
end generate;
gpio_in <= gpios;
or_blocks: for i in 0 to num_gpios - 2 generate
spi_slave_input_state_res (i) <= spi_slave_input_state_res (i + 1) or spi_slave_input_state (i);
spi_slave_input_state_valid_res (i) <= spi_slave_input_state_valid_res (i + 1) or spi_slave_input_state_valid (i);
spi_slave_cmd_done_res (i) <= spi_slave_cmd_done_res (i + 1) or spi_slave_cmd_done (i);
end generate;
spi_slave_input_state_res(num_gpios - 1) <= '0';
spi_slave_input_state_valid_res(num_gpios - 1) <= '0';
spi_slave_cmd_done_res(num_gpios - 1) <= '0';
-- Reset
proc_reset: process(clock_50mhz)
begin
if clock_50mhz'event and clock_50mhz = '1' then
reset_done <= '1';
end if;
end process;
n_reset_async <= reset_done and keys(1);
end architecture rtl;
|
--
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity syncflag is
generic(
n : integer := 3
);
port(
clk_input : in std_logic;
clk_output : in std_logic;
input : in std_logic;
output : out std_logic
);
end syncflag;
-- http://forums.xilinx.com/t5/Implementation/Attributes-in-Asynchronous-Input-Synchronization-issue-warnings/td-p/122912
--
-- TIG="TRUE" - Specifies a timing ignore for the asynchronous input
-- IOB="FALSE" = Specifies to not place the register into the IOB allowing
-- both synchronization registers to exist in the same slice
-- allowing for the shortest propagation time between them
-- ASYNC_REG="TRUE" - Specifies registers will be receiving asynchronous data
-- input to allow for better timing simulation
-- characteristics
-- SHIFT_EXTRACT="NO" - Specifies to the synthesis tool to not infer an SRL
-- HBLKNM="sync_reg" - Specifies to pack both registers into the same slice
architecture behavioral of syncflag is
signal sync : unsigned(n-1 downto 0) := (others=>'0');
signal flag_toggle : std_logic := '0';
signal sync_in : std_logic := '0';
attribute TIG : string;
attribute IOB : string;
attribute ASYNC_REG : string;
attribute SHIFT_EXTRACT : string;
attribute HBLKNM : string;
attribute TIG of sync_in : signal is "TRUE";
--attribute ASYNC_REG of sync_in : signal is "TRUE";
--attribute SHIFT_EXTRACT of sync : signal is "NO";
--attribute HBLKNM of sync : signal is "sync_reg";
begin
process (clk_input)
begin
if rising_edge(clk_input) then
flag_toggle <= flag_toggle xor input;
sync_in <= flag_toggle;
end if;
end process;
process (clk_output)
begin
if rising_edge(clk_output) then
sync <= sync(sync'high-1 downto 0) & sync_in;
end if;
end process;
output <= sync(sync'high) xor sync(sync'high-1);
end behavioral;
|
-------------------------------------------------------------------------------
-- Title : HDLC async Encoder
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Encode 8-Bit input + frame boundary marker to 8 bit HDLC Async framing
--
-- Frame-seperator is encoded as 0x100.
--
-- 0x000 to 0x007C -> 0x00 to 0x7C
-- 0x07f to 0x0ff -> 0x7f to 0xff
-- 0x1XX -> 0x7e (Frame boundary marker)
-- 0x07E -> 0x7D, 0x5E
-- 0x07D -> 0x7D, 0x5D
--
-- Input port can't take in data while it outputs an escape sequence!
--
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.hdlc_pkg.all;
-------------------------------------------------------------------------------
entity hdlc_enc is
port(
din_p : in hdlc_enc_in_type;
dout_p : out hdlc_enc_out_type;
busy_p : out std_logic;
clk : in std_logic
);
end hdlc_enc;
-------------------------------------------------------------------------------
architecture behavioural of hdlc_enc is
type hdlc_enc_state_type is (
NOM, -- previous char was nominal
ESC -- previous char was an escape
);
type hdlc_enc_type is record
state : hdlc_enc_state_type;
strobe : std_logic;
next_char : std_logic_vector(7 downto 0);
dout : std_logic_vector(7 downto 0);
busy : std_logic;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : hdlc_enc_type := (state => NOM, strobe => '0', next_char => (others => '0'), dout => (others => '0'), busy => '0');
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
dout_p.data <= r.dout;
dout_p.enable <= r.strobe;
busy_p <= r.busy;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(din_p, r)
variable v : hdlc_enc_type;
begin
v := r;
v.strobe := '0';
v.busy := '0';
case r.state is
when NOM =>
if din_p.enable = '1' then
if din_p.data(8) = '1' then
v.dout := x"7e";
v.strobe := '1';
elsif (din_p.data(7 downto 0) = x"7e") or (din_p.data(7 downto 0) = x"7d") then
v.dout := x"7d";
v.next_char := din_p.data(7 downto 6) & not din_p.data(5) & din_p.data(4 downto 0);
v.strobe := '1';
v.state := ESC;
v.busy := '1';
else
v.dout := din_p.data(7 downto 0);
v.strobe := '1';
end if;
end if;
when ESC =>
v.strobe := '1';
v.dout := v.next_char;
v.state := NOM;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
|
-------------------------------------------------------------------------------
-- Title : HDLC async Encoder
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Encode 8-Bit input + frame boundary marker to 8 bit HDLC Async framing
--
-- Frame-seperator is encoded as 0x100.
--
-- 0x000 to 0x007C -> 0x00 to 0x7C
-- 0x07f to 0x0ff -> 0x7f to 0xff
-- 0x1XX -> 0x7e (Frame boundary marker)
-- 0x07E -> 0x7D, 0x5E
-- 0x07D -> 0x7D, 0x5D
--
-- Input port can't take in data while it outputs an escape sequence!
--
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.hdlc_pkg.all;
-------------------------------------------------------------------------------
entity hdlc_enc is
port(
din_p : in hdlc_enc_in_type;
dout_p : out hdlc_enc_out_type;
busy_p : out std_logic;
clk : in std_logic
);
end hdlc_enc;
-------------------------------------------------------------------------------
architecture behavioural of hdlc_enc is
type hdlc_enc_state_type is (
NOM, -- previous char was nominal
ESC -- previous char was an escape
);
type hdlc_enc_type is record
state : hdlc_enc_state_type;
strobe : std_logic;
next_char : std_logic_vector(7 downto 0);
dout : std_logic_vector(7 downto 0);
busy : std_logic;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : hdlc_enc_type := (state => NOM, strobe => '0', next_char => (others => '0'), dout => (others => '0'), busy => '0');
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
dout_p.data <= r.dout;
dout_p.enable <= r.strobe;
busy_p <= r.busy;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(din_p, r)
variable v : hdlc_enc_type;
begin
v := r;
v.strobe := '0';
v.busy := '0';
case r.state is
when NOM =>
if din_p.enable = '1' then
if din_p.data(8) = '1' then
v.dout := x"7e";
v.strobe := '1';
elsif (din_p.data(7 downto 0) = x"7e") or (din_p.data(7 downto 0) = x"7d") then
v.dout := x"7d";
v.next_char := din_p.data(7 downto 6) & not din_p.data(5) & din_p.data(4 downto 0);
v.strobe := '1';
v.state := ESC;
v.busy := '1';
else
v.dout := din_p.data(7 downto 0);
v.strobe := '1';
end if;
end if;
when ESC =>
v.strobe := '1';
v.dout := v.next_char;
v.state := NOM;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: config
-- File: config.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: GRLIB Global configuration package. Can be overriden
-- by local config packages in template designs.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
package config is
-- AHBDW - AHB data with
--
-- Valid values are 32, 64, 128 and 256
--
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant CFG_AHBDW : integer := 64;
-- CORE_ACDM - Enable AMBA Compliant Data Muxing in cores
--
-- Valid values are 0 and 1
--
-- 0: All GRLIB cores that use the ahbread* programs defined in this package
-- will read their data from the low part of the AHB data vector.
--
-- 1: All GRLIB cores that use the ahbread* programs defined in this package
-- will select valid data, as defined in the AMBA AHB standard, from the
-- AHB data vectors based on the address input. If a core uses a function
-- that does not have the address input, a failure will be asserted.
--
constant CFG_AHB_ACDM : integer := 0;
-- GRLIB_CONFIG_ARRAY - Array of configuration values
--
-- The length of this array and the meaning of different positions is defined
-- in the grlib.config_types package.
constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := (
grlib_debug_level => 0,
grlib_debug_mask => 0,
grlib_techmap_strict_ram => 0,
others => 0);
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- flash/ethernet bus
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(31 downto 0);
romsn : out std_ulogic;
oen : out std_logic;
writen : out std_logic;
byten : out std_logic;
wpn : out std_logic;
-- SSRAM
ssram_ce1n : out std_logic;
ssram_ce2 : out std_logic;
ssram_ce3n : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (0 to 3);
ssram_oen : out std_ulogic;
ssaddr : out std_logic_vector(20 downto 2);
ssdata : inout std_logic_vector(31 downto 0);
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
ssram_adsp_n : out std_ulogic;
ssram_adv_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
ddr_clkin : in std_logic;
ddr_clk : out std_logic;
ddr_clkn : out std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console/debug UART
rxd1 : in std_logic;
txd1 : out std_logic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal ssd, prd : std_logic_vector(31 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector;
signal clkm, rstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal dsubre : std_ulogic;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
freq => freq)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => ssram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
sden => 0, ram8 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
end generate;
wpn <= '1'; byten <= '0';
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if CFG_MCTRL_LEON2 = 1 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
ssram_adv_n_pad : outpad generic map (tech => padtech)
port map (ssram_adv_n, vcc(0));
ssram_adsp_n_pad : outpad generic map (tech => padtech)
port map (ssram_adsp_n, gnd(0));
ssaddr_pad : outpadv generic map (width => 19, tech => padtech)
port map (ssaddr, memo.address(20 downto 2));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, vcc(0));
ssram_ce1n_pad : outpad generic map (tech => padtech)
port map (ssram_ce1n, gnd(0));
ssram_ce2_pad : outpad generic map (tech => padtech)
port map (ssram_ce2, vcc(0));
ssrams_pad : outpad generic map ( tech => padtech)
port map (ssram_ce3n, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.oen);
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.wrn);
ssram_wri_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.writen);
ssram_data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (ssdata, memo.data, memo.vbdrive, ssd);
memi.data(31 downto 0) <= ssd when memo.ramsn(0) = '0' else prd;
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, prd);
end generate;
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16)
port map (
resetn, rstn, ddr_clkin, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, open, gnd(0),
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
ddrsp1 : if (CFG_DDRSP = 0) generate
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
upads : if CFG_AHB_UART = 0 generate
u1i.rxd <= rxd1; txd1 <= u1o.txd;
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2C60 SSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc_tb is
end token_crc_tb;
architecture tb of token_crc_tb is
signal clock : std_logic := '0';
signal token_in : std_logic_vector(10 downto 0);
signal crc : std_logic_vector(4 downto 0);
signal total : std_logic_vector(15 downto 0);
begin
i_mut: entity work.token_crc
port map (
clock => clock,
sync => '1',
token_in => token_in,
crc => crc );
clock <= not clock after 10 ns;
p_test: process
begin
token_in <= "0001" & "0000001"; -- EP=1 / ADDR=1
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "111" & X"FB";
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "000" & X"01";
wait;
end process;
total <= crc & token_in;
end tb;
|
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc_tb is
end token_crc_tb;
architecture tb of token_crc_tb is
signal clock : std_logic := '0';
signal token_in : std_logic_vector(10 downto 0);
signal crc : std_logic_vector(4 downto 0);
signal total : std_logic_vector(15 downto 0);
begin
i_mut: entity work.token_crc
port map (
clock => clock,
sync => '1',
token_in => token_in,
crc => crc );
clock <= not clock after 10 ns;
p_test: process
begin
token_in <= "0001" & "0000001"; -- EP=1 / ADDR=1
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "111" & X"FB";
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "000" & X"01";
wait;
end process;
total <= crc & token_in;
end tb;
|
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc_tb is
end token_crc_tb;
architecture tb of token_crc_tb is
signal clock : std_logic := '0';
signal token_in : std_logic_vector(10 downto 0);
signal crc : std_logic_vector(4 downto 0);
signal total : std_logic_vector(15 downto 0);
begin
i_mut: entity work.token_crc
port map (
clock => clock,
sync => '1',
token_in => token_in,
crc => crc );
clock <= not clock after 10 ns;
p_test: process
begin
token_in <= "0001" & "0000001"; -- EP=1 / ADDR=1
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "111" & X"FB";
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "000" & X"01";
wait;
end process;
total <= crc & token_in;
end tb;
|
entity repro is
end repro;
architecture behav of repro is
function inc (a : integer) return integer is
begin
return a + 1;
end inc;
function inc (a : time) return time is
begin
return a + 1 ns;
end inc;
procedure inc (a : inout integer) is
begin
a := inc (a);
end inc;
begin -- behav
process
variable a : integer := 2;
begin
inc (a);
assert a = 3 report "bad value of a";
wait;
end process;
end behav;
|
entity repro is
end repro;
architecture behav of repro is
function inc (a : integer) return integer is
begin
return a + 1;
end inc;
function inc (a : time) return time is
begin
return a + 1 ns;
end inc;
procedure inc (a : inout integer) is
begin
a := inc (a);
end inc;
begin -- behav
process
variable a : integer := 2;
begin
inc (a);
assert a = 3 report "bad value of a";
wait;
end process;
end behav;
|
entity repro is
end repro;
architecture behav of repro is
function inc (a : integer) return integer is
begin
return a + 1;
end inc;
function inc (a : time) return time is
begin
return a + 1 ns;
end inc;
procedure inc (a : inout integer) is
begin
a := inc (a);
end inc;
begin -- behav
process
variable a : integer := 2;
begin
inc (a);
assert a = 3 report "bad value of a";
wait;
end process;
end behav;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 8.5e-07,
W => Wdiff_0,
Wdiff_0init => 3.275e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net3
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 8.5e-07,
W => Wdiff_0,
Wdiff_0init => 3.275e-05,
scope => private
)
port map(
D => out1,
G => out1,
S => net3
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => W_0,
W_0init => 6.305e-05
)
port map(
D => net3,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.25e-06,
W => Wcm_1,
Wcm_1init => 8.4e-06,
scope => private
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.25e-06,
W => Wcmcout_1,
Wcmcout_1init => 4.82e-05,
scope => private
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.4e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.4e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.4e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.4e-06
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.4e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.4e-06
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net5,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net5,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net5,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06a is
end entity inline_06a;
----------------------------------------------------------------
architecture test of inline_06a is
-- code from book:
subtype resistance is real tolerance "default_resistance";
type resistance_array is array (1 to 4) of resistance;
quantity resistances : resistance_array := (10.0, 20.0, 50.0, 75.0);
-- end of code from book
begin
block_1_f : block is
-- code from book:
quantity resistances : resistance_array := (1 => 10.0, 2 => 20.0, 3 => 50.0, 4 => 75.0);
-- end of code from book
begin
end block block_1_f;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06a is
end entity inline_06a;
----------------------------------------------------------------
architecture test of inline_06a is
-- code from book:
subtype resistance is real tolerance "default_resistance";
type resistance_array is array (1 to 4) of resistance;
quantity resistances : resistance_array := (10.0, 20.0, 50.0, 75.0);
-- end of code from book
begin
block_1_f : block is
-- code from book:
quantity resistances : resistance_array := (1 => 10.0, 2 => 20.0, 3 => 50.0, 4 => 75.0);
-- end of code from book
begin
end block block_1_f;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06a is
end entity inline_06a;
----------------------------------------------------------------
architecture test of inline_06a is
-- code from book:
subtype resistance is real tolerance "default_resistance";
type resistance_array is array (1 to 4) of resistance;
quantity resistances : resistance_array := (10.0, 20.0, 50.0, 75.0);
-- end of code from book
begin
block_1_f : block is
-- code from book:
quantity resistances : resistance_array := (1 => 10.0, 2 => 20.0, 3 => 50.0, 4 => 75.0);
-- end of code from book
begin
end block block_1_f;
end architecture test;
|
-- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : top_test_uart
-- Date : 07/25/2016
--
-- Description :
--
-- --------------------------------------------------------------------------------
-- Modifications
-- --------------------------------------------------------------------------------
-- Date : Ver. : Author : Modification comments
-- --------------------------------------------------------------------------------
-- : : :
-- 07/25/2016 : 1.0 : B.Lemoine : First draft
-- : : :
-- **********************************************************************************
-- MIT License
--
-- Copyright (c) 2016, Benjamin Lemoine
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- **********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.pkg_utils.all;
entity top_test_uart is
port (
-- CLK & RST
clk : in std_logic; -- 50 MHz
rst : in std_logic; -- Button 0
-- Liaison serie
RsTx : out std_logic;
RsRx : in std_logic;
-- 7 segment display
seg : out std_logic_vector(6 downto 0);
dp : out std_logic;
an : out std_logic_vector(3 downto 0);
-- Switch
sw : in std_logic_vector(7 downto 0);
-- Leds
Led : out std_logic_vector(7 downto 0)
);
end top_test_uart;
architecture rtl of top_test_uart is
-- Component declaration
entity component is
generic (
CLK_IN : integer := 50000000;
BAUDRATE : integer := 9600;
DATA_BITS : integer range 7 to 8 := 8;
STOP_BITS : integer range 1 to 2 := 1;
USE_PARITY : integer range 0 to 1 := 0;
ODD_PARITY : integer range 0 to 1 := 0;
USE_FIFO_TX : integer range 0 to 1 := 1;
USE_FIFO_RX : integer range 0 to 1 := 1;
SIZE_FIFO_TX : integer range 0 to 10 := 4; -- Log2 of fifo size
SIZE_FIFO_RX : integer range 0 to 10 := 4 -- Log2 of fifo size
);
port (
clk : in std_logic;
rst_n : in std_logic;
--
addr : in std_logic_vector(7 downto 0);
data_wr : in std_logic_vector(7 downto 0);
wr_en : in std_logic;
data_rd : out std_logic_vector(7 downto 0);
--
RX : in std_logic;
TX : out std_logic
);
end component;
-- Reset
signal r_rsl_reset : std_logic_vector(4 downto 0) := (others => '0');
signal reset_global : std_logic := '0';
signal reset_global_n : std_logic := '1';
-- Clocks
signal clk_50M : std_logic := '0';
signal clk_10M_dcm : std_logic := '0';
signal dcm_locked : std_logic := '0';
-- Main FSM (for Miniblaze)
type main_fsm is (RESET_STATE, RUN_STATE);
signal r_state : main_fsm := RESET_STATE;
signal r_last_state : main_fsm := RESET_STATE;
-- Send FSM
type fsm_tx is (st_wait_start, st_send_byte, st_wait_ack);
signal r_fsm_tx : fsm_tx := st_wait_start;
signal r_start_sending : std_logic := '0';
signal r_last_sent_done : std_logic := '0';
signal r_cnt_sent : unsigned(3 downto 0) := (others => '0');
signal r_data_to_send : std_logic_vector(15 downto 0) := (others => '0');
-- Enable
constant c_1second_50M : integer := 50000000;
signal r_cnt_1s : unsigned(31 downto 0) := (others => '0');
signal r_cnt_10s : unsigned(31 downto 0) := (others => '0');
signal r_cnt_1min : unsigned(31 downto 0) := (others => '0');
signal r_cnt_10min : unsigned(31 downto 0) := (others => '0');
signal r_enable_1s : std_logic := '0';
signal r_enable_10s : std_logic := '0';
signal r_enable_1min : std_logic := '0';
signal r_enable_10min : std_logic := '0';
signal r_srl_enable_1s : std_logic_vector(2 downto 0) := (others => '0');
signal r_srl_enable_10s : std_logic_vector(1 downto 0) := (others => '0');
signal r_srl_enable_1min : std_logic := '0';
signal enable_1s : std_logic := '0';
signal enable_10s : std_logic := '0';
signal enable_1min : std_logic := '0';
signal enable_10min : std_logic := '0';
-- Time
signal r_display_1s : unsigned(3 downto 0) := (others => '0');
signal r_display_10s : unsigned(3 downto 0) := (others => '0');
signal r_display_1min : unsigned(3 downto 0) := (others => '0');
signal r_display_10min : unsigned(3 downto 0) := (others => '0');
-- 7 segments display
signal r_display_7_seg_tx : std_logic_vector(15 downto 0) := (others => '0');
signal r_display_7_seg_rx : std_logic_vector(15 downto 0) := (others => '0');
signal r_display_7_seg : std_logic_vector(15 downto 0) := (others => '0');
-- UART
signal r_data_tx : std_logic_vector(7 downto 0) := (others => '0');
signal r_data_tx_en : std_logic := '0';
signal data_rx : std_logic_vector(7 downto 0) := (others => '0');
signal data_rx_en : std_logic := '0';
signal r_data_tx_loopback : std_logic_vector(7 downto 0) := (others => '0');
signal r_data_tx_loopback_en : std_logic := '0';
signal data_tx_ack : std_logic := '0';
signal s_data_tx : std_logic_vector(7 downto 0) := (others => '0');
signal s_data_tx_en : std_logic := '0';
-- Leds
signal led_vect : std_logic_vector(7 downto 0) := (others => '0');
signal led_enable_1s : std_logic := '0';
begin
------------------------------------------
-- Debounce input reset
------------------------------------------
p_debounce_reset : process(clk)
begin
if rising_edge(clk) then
r_rsl_reset <= r_rsl_reset(r_rsl_reset'left-1 downto 0) & rst;
end if;
end process;
reset_global <= AND_VECT(r_rsl_reset);
reset_global_n <= not reset_global;
------------------------------------------
-- BUFG for the 50MHz
------------------------------------------
i_feedback_dcm : BUFG
port map(
I => clk,
O => clk_50M
);
------------------------------------------
-- UART peripheral
------------------------------------------
i_uart : peripheral_uart
port (
clk => clk_50M,
rst_n => reset_global_n,
--
addr => addr_bus,
data_wr => data_wr_bus,
wr_en => data_wr_en_bus,
data_rd => data_rx_bus,
--
RX => RsRx,
TX => RsTx
);
------------------------------------------
-- 7 segments module
------------------------------------------
i_7segment : peripheral_7_segments
port map(
clk => clk_50M,
reset => reset_global,
--
addr => addr_bus,
data_wr => data_wr_bus,
wr_en => data_wr_en_bus,
data_rd => open,
--
segments => seg,
dp => dp,
anode_selected => an
);
------------------------------------------
-- Enable 1s, 10s, 1 min, 10 min
------------------------------------------
process(clk_50M)
begin
if rising_edge(clk_50M) then
if r_cnt_1s = c_1second_50M - 1 then
r_enable_1s <= '1';
r_cnt_1s <= (others => '0');
else
r_enable_1s <= '0';
r_cnt_1s <= r_cnt_1s + 1;
end if;
r_enable_10s <= '0';
if r_enable_1s = '1' then
if r_cnt_10s = 9 then
r_enable_10s <= '1';
r_cnt_10s <= (others => '0');
else
r_cnt_10s <= r_cnt_10s + 1;
end if;
end if;
r_enable_1min <= '0';
if r_enable_10s = '1' then
if r_cnt_1min = 5 then
r_enable_1min <= '1';
r_cnt_1min <= (others => '0');
else
r_cnt_1min <= r_cnt_1min + 1;
end if;
end if;
r_enable_10min <= '0';
if r_enable_1min = '1' then
if r_cnt_10min = 9 then
r_enable_10min <= '1';
r_cnt_10min <= (others => '0');
else
r_cnt_10min <= r_cnt_10min + 1;
end if;
end if;
-- Delay to have the enables synchrone
r_srl_enable_1s <= r_srl_enable_1s(1 downto 0) & r_enable_1s;
r_srl_enable_10s <= r_srl_enable_10s(0 downto 0) & r_enable_10s;
r_srl_enable_1min <= r_enable_1min;
end if;
end process;
enable_1s <= r_srl_enable_1s(2);
enable_10s <= r_srl_enable_10s(1);
enable_1min <= r_srl_enable_1min;
enable_10min <= r_enable_10min;
------------------------------------------
-- Time since start
-- 4 register of 4 bits to display the time
-- in the following manner : MM-SS
------------------------------------------
process(clk_50M)
begin
if rising_edge(clk_50M) then
if reset_global = '1' then
r_display_1s <= (others => '0');
r_display_10s <= (others => '0');
r_display_10s <= (others => '0');
r_display_10min <= (others => '0');
else
if enable_1s = '1' then
if r_display_1s = 9 then
r_display_1s <= (others => '0');
else
r_display_1s <= r_display_1s + 1;
end if;
end if;
if enable_10s = '1' then
if r_display_10s = 5 then
r_display_10s <= (others => '0');
else
r_display_10s <= r_display_10s + 1;
end if;
end if;
if enable_1min = '1' then
if r_display_1min = 9 then
r_display_1min <= (others => '0');
else
r_display_1min <= r_display_1min + 1;
end if;
end if;
if enable_10min = '1' then
if r_display_10min = 9 then
r_display_10min <= (others => '0');
else
r_display_10min <= r_display_10min + 1;
end if;
end if;
end if;
r_display_7_seg_tx <= std_logic_vector(r_display_10min)
& std_logic_vector(r_display_1min)
& std_logic_vector(r_display_10s)
& std_logic_vector(r_display_1s);
end if;
end process;
------------------------------------------
-- LEDs display
-- Led 0 : ON => DCM locked
-- OFF => DCM unlocked
-- Led 1 : ON => FSM main in RX_STATE
-- OFF => FSM main not in RX_STATE
-- Led 2 : ON => FSM main in TX_STATE
-- OFF => FSM main not in TX_STATE
-- Led 3 : ON => FSM main in LOOPBACK_STATE
-- OFF => FSM main not in LOOPBACK_STATE
------------------------------------------
led_vect(0) <= dcm_locked;
led_vect(1) <= '1' when r_state = RX_STATE else '0';
led_vect(2) <= '1' when r_state = TX_STATE else '0';
led_vect(3) <= '1' when r_state = LOOPBACK_STATE else '0';
led_vect(4) <= led_enable_1s;
led_vect(5) <= reset_global;
led_vect(6) <= '0';
led_vect(7) <= '0';
process(clk_50M)
begin
if rising_edge(clk_50M) then
if enable_1s = '1' then
led_enable_1s <= not led_enable_1s;
end if;
end if;
end process;
-- Output buffer
p_leds : process(clk_50M)
begin
if rising_edge(clk_50M) then
Led <= led_vect;
end if;
end process;
end rtl; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1266.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p06n03i01266ent IS
END c08s02b00x00p06n03i01266ent;
ARCHITECTURE c08s02b00x00p06n03i01266arch OF c08s02b00x00p06n03i01266ent IS
BEGIN
TESTING: PROCESS
variable k : boolean;
variable y : severity_level;
BEGIN
assert k = true
report "Assertion violation"
severity y;
assert FALSE
report "***PASSED TEST: c08s02b00x00p06n03i01266"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p06n03i01266arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1266.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p06n03i01266ent IS
END c08s02b00x00p06n03i01266ent;
ARCHITECTURE c08s02b00x00p06n03i01266arch OF c08s02b00x00p06n03i01266ent IS
BEGIN
TESTING: PROCESS
variable k : boolean;
variable y : severity_level;
BEGIN
assert k = true
report "Assertion violation"
severity y;
assert FALSE
report "***PASSED TEST: c08s02b00x00p06n03i01266"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p06n03i01266arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1266.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p06n03i01266ent IS
END c08s02b00x00p06n03i01266ent;
ARCHITECTURE c08s02b00x00p06n03i01266arch OF c08s02b00x00p06n03i01266ent IS
BEGIN
TESTING: PROCESS
variable k : boolean;
variable y : severity_level;
BEGIN
assert k = true
report "Assertion violation"
severity y;
assert FALSE
report "***PASSED TEST: c08s02b00x00p06n03i01266"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p06n03i01266arch;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sat Mar 19 19:16:24 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/SKL/Desktop/ECE532/repo/decoder_ip_prj/decoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_8kb_cnt/dcfifo_32in_32out_8kb_cnt_funcsim.vhdl
-- Design : dcfifo_32in_32out_8kb_cnt
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12 downto 5) => \gc0.count_d1_reg[7]\(7 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12 downto 5) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DIADI(15 downto 0) => din(15 downto 0),
DIBDI(15 downto 0) => din(31 downto 16),
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 0) => dout(15 downto 0),
DOBDO(15 downto 0) => dout(31 downto 16),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\,
ENARDEN => tmp_ram_rd_en,
ENBWREN => WEBWE(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => Q(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => WEBWE(0),
WEBWE(2) => WEBWE(0),
WEBWE(1) => WEBWE(0),
WEBWE(0) => WEBWE(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_rd_bin_cntr is
port (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_en : in STD_LOGIC;
p_18_out : in STD_LOGIC;
\wr_pntr_bin_reg[6]\ : in STD_LOGIC;
\wr_pntr_bin_reg[4]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_rd_bin_cntr : entity is "rd_bin_cntr";
end dcfifo_32in_32out_8kb_cnt_rd_bin_cntr;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gc0.count[7]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_empty_i_i_4_n_0 : STD_LOGIC;
signal ram_empty_i_i_5_n_0 : STD_LOGIC;
signal ram_empty_i_i_6_n_0 : STD_LOGIC;
signal ram_empty_i_i_7_n_0 : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gc0.count[7]_i_2\ : label is "soft_lutpair7";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus1(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(2),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => rd_pntr_plus1(4),
I1 => rd_pntr_plus1(2),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(0),
I4 => rd_pntr_plus1(3),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => rd_pntr_plus1(5),
I1 => rd_pntr_plus1(3),
I2 => rd_pntr_plus1(0),
I3 => rd_pntr_plus1(1),
I4 => rd_pntr_plus1(2),
I5 => rd_pntr_plus1(4),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => rd_pntr_plus1(6),
I1 => rd_pntr_plus1(4),
I2 => \gc0.count[7]_i_2_n_0\,
I3 => rd_pntr_plus1(3),
I4 => rd_pntr_plus1(5),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => rd_pntr_plus1(7),
I1 => rd_pntr_plus1(5),
I2 => rd_pntr_plus1(3),
I3 => \gc0.count[7]_i_2_n_0\,
I4 => rd_pntr_plus1(4),
I5 => rd_pntr_plus1(6),
O => plusOp(7)
);
\gc0.count[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(0),
O => \gc0.count[7]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => Q(0),
Q => rd_pntr_plus1(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(1),
Q => rd_pntr_plus1(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(2),
Q => rd_pntr_plus1(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(5),
Q => rd_pntr_plus1(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(6),
Q => rd_pntr_plus1(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(7),
Q => rd_pntr_plus1(7)
);
ram_empty_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \wr_pntr_bin_reg[6]\,
I1 => \wr_pntr_bin_reg[4]\,
I2 => ram_empty_i_i_4_n_0,
I3 => ram_empty_i_i_5_n_0,
I4 => ram_empty_i_i_6_n_0,
I5 => ram_empty_i_i_7_n_0,
O => ram_empty_i_reg
);
ram_empty_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I1 => WR_PNTR_RD(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I3 => WR_PNTR_RD(3),
O => ram_empty_i_i_4_n_0
);
ram_empty_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(5),
I1 => WR_PNTR_RD(5),
I2 => rd_pntr_plus1(4),
I3 => WR_PNTR_RD(4),
I4 => WR_PNTR_RD(2),
I5 => rd_pntr_plus1(2),
O => ram_empty_i_i_5_n_0
);
ram_empty_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0090000000000090"
)
port map (
I0 => rd_pntr_plus1(6),
I1 => WR_PNTR_RD(6),
I2 => rd_en,
I3 => p_18_out,
I4 => WR_PNTR_RD(7),
I5 => rd_pntr_plus1(7),
O => ram_empty_i_i_6_n_0
);
ram_empty_i_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => WR_PNTR_RD(3),
I2 => rd_pntr_plus1(1),
I3 => WR_PNTR_RD(1),
I4 => WR_PNTR_RD(0),
I5 => rd_pntr_plus1(0),
O => ram_empty_i_i_7_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_rd_dc_as is
port (
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 6 downto 0 );
\wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_rd_dc_as : entity is "rd_dc_as";
end dcfifo_32in_32out_8kb_cnt_rd_dc_as;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_rd_dc_as is
signal minusOp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \rd_dc_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \NLW_rd_dc_i_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\rd_dc_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(0),
D => minusOp(7),
Q => rd_data_count(0)
);
\rd_dc_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[7]_i_2_n_0\,
CO(3) => \NLW_rd_dc_i_reg[7]_i_1_CO_UNCONNECTED\(3),
CO(2) => \rd_dc_i_reg[7]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[7]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => WR_PNTR_RD(6 downto 4),
O(3 downto 0) => minusOp(7 downto 4),
S(3 downto 0) => S(3 downto 0)
);
\rd_dc_i_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rd_dc_i_reg[7]_i_2_n_0\,
CO(2) => \rd_dc_i_reg[7]_i_2_n_1\,
CO(1) => \rd_dc_i_reg[7]_i_2_n_2\,
CO(0) => \rd_dc_i_reg[7]_i_2_n_3\,
CYINIT => '1',
DI(3 downto 0) => WR_PNTR_RD(3 downto 0),
O(3 downto 0) => minusOp(3 downto 0),
S(3 downto 0) => \wr_pntr_bin_reg[3]\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_rd_status_flags_as is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[6]\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_rd_status_flags_as : entity is "rd_status_flags_as";
end dcfifo_32in_32out_8kb_cnt_rd_status_flags_as;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_rd_status_flags_as is
signal \^p_18_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
p_18_out <= \^p_18_out\;
\gc0.count_d1[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^p_18_out\,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \wr_pntr_bin_reg[6]\,
PRE => Q(0),
Q => \^p_18_out\
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \wr_pntr_bin_reg[6]\,
PRE => Q(0),
Q => empty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_reset_blk_ramfifo is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end dcfifo_32in_32out_8kb_cnt_reset_blk_ramfifo;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_reset_blk_ramfifo is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d2 : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal rst_rd_reg1 : STD_LOGIC;
signal rst_rd_reg2 : STD_LOGIC;
signal rst_wr_reg1 : STD_LOGIC;
signal rst_wr_reg2 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
rst_full_ff_i <= rst_d2;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^q\(0),
I1 => p_18_out,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => \gic0.gc0.count_reg[0]\(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => \gic0.gc0.count_reg[0]\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_synchronizer_ff is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_synchronizer_ff : entity is "synchronizer_ff";
end dcfifo_32in_32out_8kb_cnt_synchronizer_ff;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_synchronizer_ff is
signal Q_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
begin
D(7 downto 0) <= Q_reg(7 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_synchronizer_ff_0 is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_synchronizer_ff_0 : entity is "synchronizer_ff";
end dcfifo_32in_32out_8kb_cnt_synchronizer_ff_0;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
begin
D(7 downto 0) <= Q_reg(7 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(7),
Q => Q_reg(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_synchronizer_ff_1 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_synchronizer_ff_1 : entity is "synchronizer_ff";
end dcfifo_32in_32out_8kb_cnt_synchronizer_ff_1;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^wr_pntr_bin_reg[6]\ : STD_LOGIC_VECTOR ( 6 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
begin
\out\(0) <= Q_reg(7);
\wr_pntr_bin_reg[6]\(6 downto 0) <= \^wr_pntr_bin_reg[6]\(6 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(0),
I3 => \^wr_pntr_bin_reg[6]\(3),
O => \^wr_pntr_bin_reg[6]\(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => \^wr_pntr_bin_reg[6]\(3),
O => \^wr_pntr_bin_reg[6]\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(3),
I1 => Q_reg(7),
I2 => Q_reg(5),
I3 => Q_reg(6),
I4 => Q_reg(4),
I5 => Q_reg(2),
O => \^wr_pntr_bin_reg[6]\(2)
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(6),
I2 => Q_reg(5),
I3 => Q_reg(7),
I4 => Q_reg(3),
O => \^wr_pntr_bin_reg[6]\(3)
);
\wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(4),
O => \^wr_pntr_bin_reg[6]\(4)
);
\wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(5),
I2 => Q_reg(7),
O => \^wr_pntr_bin_reg[6]\(5)
);
\wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(7),
O => \^wr_pntr_bin_reg[6]\(6)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_synchronizer_ff_2 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_pntr_bin_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_synchronizer_ff_2 : entity is "synchronizer_ff";
end dcfifo_32in_32out_8kb_cnt_synchronizer_ff_2;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^rd_pntr_bin_reg[6]\ : STD_LOGIC_VECTOR ( 6 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
begin
\out\(0) <= Q_reg(7);
\rd_pntr_bin_reg[6]\(6 downto 0) <= \^rd_pntr_bin_reg[6]\(6 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(7),
Q => Q_reg(7)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(0),
I3 => \^rd_pntr_bin_reg[6]\(3),
O => \^rd_pntr_bin_reg[6]\(0)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => \^rd_pntr_bin_reg[6]\(3),
O => \^rd_pntr_bin_reg[6]\(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(3),
I1 => Q_reg(7),
I2 => Q_reg(5),
I3 => Q_reg(6),
I4 => Q_reg(4),
I5 => Q_reg(2),
O => \^rd_pntr_bin_reg[6]\(2)
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(6),
I2 => Q_reg(5),
I3 => Q_reg(7),
I4 => Q_reg(3),
O => \^rd_pntr_bin_reg[6]\(3)
);
\rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(4),
O => \^rd_pntr_bin_reg[6]\(4)
);
\rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(5),
I2 => Q_reg(7),
O => \^rd_pntr_bin_reg[6]\(5)
);
\rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(7),
O => \^rd_pntr_bin_reg[6]\(6)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_wr_bin_cntr is
port (
ram_full_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gic0.gc0.count_d2_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
p_0_out : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_wr_bin_cntr : entity is "wr_bin_cntr";
end dcfifo_32in_32out_8kb_cnt_wr_bin_cntr;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \gic0.gc0.count[7]_i_2_n_0\ : STD_LOGIC;
signal \^gic0.gc0.count_d2_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair10";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\gic0.gc0.count_d2_reg[7]_0\(7 downto 0) <= \^gic0.gc0.count_d2_reg[7]_0\(7 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
I2 => \^q\(0),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => \^q\(0),
I3 => \^q\(1),
O => \plusOp__0\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(0),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(1),
I3 => \^q\(1),
I4 => \^q\(2),
O => \plusOp__0\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(1),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(0),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(3),
O => \plusOp__0\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count[7]_i_2_n_0\,
I1 => \^q\(4),
O => \plusOp__0\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gic0.gc0.count[7]_i_2_n_0\,
I1 => \^q\(4),
I2 => \^q\(5),
O => \plusOp__0\(7)
);
\gic0.gc0.count[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(0),
I4 => \^q\(0),
I5 => \^q\(2),
O => \gic0.gc0.count[7]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => \^gic0.gc0.count_d2_reg[7]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => wr_pntr_plus2(1),
Q => \^gic0.gc0.count_d2_reg[7]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(0),
Q => \^gic0.gc0.count_d2_reg[7]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[7]_0\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[7]_0\(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[7]_0\(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(4),
Q => \^gic0.gc0.count_d2_reg[7]_0\(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(5),
Q => \^gic0.gc0.count_d2_reg[7]_0\(7)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => \^q\(0)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => \^q\(1)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => \^q\(2)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(5),
Q => \^q\(3)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(6),
Q => \^q\(4)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(7),
Q => \^q\(5)
);
ram_full_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0090000000000090"
)
port map (
I0 => RD_PNTR_WR(0),
I1 => wr_pntr_plus2(0),
I2 => wr_en,
I3 => p_0_out,
I4 => wr_pntr_plus2(1),
I5 => RD_PNTR_WR(1),
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_wr_status_flags_as is
port (
full : out STD_LOGIC;
p_0_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_wr_status_flags_as : entity is "wr_status_flags_as";
end dcfifo_32in_32out_8kb_cnt_wr_status_flags_as;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_wr_status_flags_as is
signal \^p_0_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_0_out <= \^p_0_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_0_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => \^p_0_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_width;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_wrapper
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_clk_x_pntrs is
port (
ram_empty_i_reg : out STD_LOGIC;
WR_PNTR_RD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_empty_i_reg_0 : out STD_LOGIC;
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 1 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\rd_dc_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_i : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst_full_gen_i : in STD_LOGIC;
\rd_pntr_bin_reg[0]_0\ : in STD_LOGIC;
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_clk_x_pntrs : entity is "clk_x_pntrs";
end dcfifo_32in_32out_8kb_cnt_clk_x_pntrs;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_clk_x_pntrs is
signal \^rd_pntr_wr\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wr_pntr_rd\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 );
signal p_0_in6_out : STD_LOGIC_VECTOR ( 6 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 7 downto 2 );
signal p_0_out_0 : STD_LOGIC_VECTOR ( 7 to 7 );
signal p_1_out : STD_LOGIC_VECTOR ( 7 to 7 );
signal p_2_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
signal ram_full_i_i_6_n_0 : STD_LOGIC;
signal ram_full_i_i_7_n_0 : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[5]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
begin
RD_PNTR_WR(1 downto 0) <= \^rd_pntr_wr\(1 downto 0);
WR_PNTR_RD(7 downto 0) <= \^wr_pntr_rd\(7 downto 0);
\gsync_stage[1].rd_stg_inst\: entity work.dcfifo_32in_32out_8kb_cnt_synchronizer_ff
port map (
D(7 downto 0) => p_3_out(7 downto 0),
Q(7 downto 0) => wr_pntr_gc(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.dcfifo_32in_32out_8kb_cnt_synchronizer_ff_0
port map (
D(7 downto 0) => p_2_out(7 downto 0),
Q(7 downto 0) => rd_pntr_gc(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.dcfifo_32in_32out_8kb_cnt_synchronizer_ff_1
port map (
D(7 downto 0) => p_3_out(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_1_out(7),
rd_clk => rd_clk,
\wr_pntr_bin_reg[6]\(6 downto 0) => p_0_in(6 downto 0)
);
\gsync_stage[2].wr_stg_inst\: entity work.dcfifo_32in_32out_8kb_cnt_synchronizer_ff_2
port map (
D(7 downto 0) => p_2_out(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
\out\(0) => p_0_out_0(7),
\rd_pntr_bin_reg[6]\(6) => \gsync_stage[2].wr_stg_inst_n_1\,
\rd_pntr_bin_reg[6]\(5) => \gsync_stage[2].wr_stg_inst_n_2\,
\rd_pntr_bin_reg[6]\(4) => \gsync_stage[2].wr_stg_inst_n_3\,
\rd_pntr_bin_reg[6]\(3) => \gsync_stage[2].wr_stg_inst_n_4\,
\rd_pntr_bin_reg[6]\(2) => \gsync_stage[2].wr_stg_inst_n_5\,
\rd_pntr_bin_reg[6]\(1) => \gsync_stage[2].wr_stg_inst_n_6\,
\rd_pntr_bin_reg[6]\(0) => \gsync_stage[2].wr_stg_inst_n_7\,
wr_clk => wr_clk
);
ram_empty_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^wr_pntr_rd\(6),
I1 => Q(6),
I2 => \^wr_pntr_rd\(1),
I3 => Q(1),
I4 => Q(0),
I5 => \^wr_pntr_rd\(0),
O => ram_empty_i_reg_0
);
ram_empty_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^wr_pntr_rd\(4),
I1 => Q(4),
I2 => \^wr_pntr_rd\(5),
I3 => Q(5),
I4 => Q(7),
I5 => \^wr_pntr_rd\(7),
O => ram_empty_i_reg
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"55554000"
)
port map (
I0 => rst_full_gen_i,
I1 => ram_full_i_i_2_n_0,
I2 => \rd_pntr_bin_reg[0]_0\,
I3 => ram_full_i_i_4_n_0,
I4 => \gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1\,
O => ram_full_i
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_0_out(5),
I1 => \gic0.gc0.count_reg[7]\(3),
I2 => p_0_out(7),
I3 => \gic0.gc0.count_reg[7]\(5),
I4 => \gic0.gc0.count_reg[7]\(4),
I5 => p_0_out(6),
O => ram_full_i_i_2_n_0
);
ram_full_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_0_out(2),
I1 => \gic0.gc0.count_reg[7]\(0),
I2 => p_0_out(3),
I3 => \gic0.gc0.count_reg[7]\(1),
I4 => \gic0.gc0.count_reg[7]\(2),
I5 => p_0_out(4),
O => ram_full_i_i_4_n_0
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => p_0_out(7),
I1 => \gic0.gc0.count_d1_reg[7]\(7),
I2 => p_0_out(6),
I3 => \gic0.gc0.count_d1_reg[7]\(6),
I4 => ram_full_i_i_6_n_0,
I5 => ram_full_i_i_7_n_0,
O => \gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1\
);
ram_full_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^rd_pntr_wr\(0),
I1 => \gic0.gc0.count_d1_reg[7]\(0),
I2 => \^rd_pntr_wr\(1),
I3 => \gic0.gc0.count_d1_reg[7]\(1),
I4 => \gic0.gc0.count_d1_reg[7]\(2),
I5 => p_0_out(2),
O => ram_full_i_i_6_n_0
);
ram_full_i_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_0_out(3),
I1 => \gic0.gc0.count_d1_reg[7]\(3),
I2 => p_0_out(4),
I3 => \gic0.gc0.count_d1_reg[7]\(4),
I4 => \gic0.gc0.count_d1_reg[7]\(5),
I5 => p_0_out(5),
O => ram_full_i_i_7_n_0
);
\rd_dc_i[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(0),
I1 => Q(0),
O => \rd_dc_i_reg[7]\(0)
);
\rd_dc_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(7),
I1 => Q(7),
O => S(3)
);
\rd_dc_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(6),
I1 => Q(6),
O => S(2)
);
\rd_dc_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(5),
I1 => Q(5),
O => S(1)
);
\rd_dc_i[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(4),
I1 => Q(4),
O => S(0)
);
\rd_dc_i[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(3),
I1 => Q(3),
O => \rd_dc_i_reg[7]\(3)
);
\rd_dc_i[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(2),
I1 => Q(2),
O => \rd_dc_i_reg[7]\(2)
);
\rd_dc_i[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(1),
I1 => Q(1),
O => \rd_dc_i_reg[7]\(1)
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_7\,
Q => \^rd_pntr_wr\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_6\,
Q => \^rd_pntr_wr\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_5\,
Q => p_0_out(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_4\,
Q => p_0_out(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_3\,
Q => p_0_out(4)
);
\rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_2\,
Q => p_0_out(5)
);
\rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_1\,
Q => p_0_out(6)
);
\rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_out_0(7),
Q => p_0_out(7)
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \rd_pntr_gc[0]_i_1_n_0\
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \rd_pntr_gc[1]_i_1_n_0\
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \rd_pntr_gc[2]_i_1_n_0\
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \rd_pntr_gc[3]_i_1_n_0\
);
\rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \rd_pntr_gc[4]_i_1_n_0\
);
\rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \rd_pntr_gc[5]_i_1_n_0\
);
\rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \rd_pntr_gc[6]_i_1_n_0\
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => rd_pntr_gc(7)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(0),
Q => \^wr_pntr_rd\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(1),
Q => \^wr_pntr_rd\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(2),
Q => \^wr_pntr_rd\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(3),
Q => \^wr_pntr_rd\(3)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(4),
Q => \^wr_pntr_rd\(4)
);
\wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(5),
Q => \^wr_pntr_rd\(5)
);
\wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(6),
Q => \^wr_pntr_rd\(6)
);
\wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_1_out(7),
Q => \^wr_pntr_rd\(7)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(0),
I1 => \gic0.gc0.count_d2_reg[7]\(1),
O => p_0_in6_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(1),
I1 => \gic0.gc0.count_d2_reg[7]\(2),
O => p_0_in6_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(2),
I1 => \gic0.gc0.count_d2_reg[7]\(3),
O => p_0_in6_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(3),
I1 => \gic0.gc0.count_d2_reg[7]\(4),
O => p_0_in6_out(3)
);
\wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(4),
I1 => \gic0.gc0.count_d2_reg[7]\(5),
O => p_0_in6_out(4)
);
\wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(5),
I1 => \gic0.gc0.count_d2_reg[7]\(6),
O => p_0_in6_out(5)
);
\wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(6),
I1 => \gic0.gc0.count_d2_reg[7]\(7),
O => p_0_in6_out(6)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(4),
Q => wr_pntr_gc(4)
);
\wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(5),
Q => wr_pntr_gc(5)
);
\wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(6),
Q => wr_pntr_gc(6)
);
\wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gic0.gc0.count_d2_reg[7]\(7),
Q => wr_pntr_gc(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_rd_logic is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_en : in STD_LOGIC;
\wr_pntr_bin_reg[6]\ : in STD_LOGIC;
\wr_pntr_bin_reg[4]\ : in STD_LOGIC;
\wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_rd_logic : entity is "rd_logic";
end dcfifo_32in_32out_8kb_cnt_rd_logic;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_rd_logic is
signal p_14_out : STD_LOGIC;
signal \^p_18_out\ : STD_LOGIC;
signal rpntr_n_8 : STD_LOGIC;
begin
p_18_out <= \^p_18_out\;
\gras.grdc1.rdc\: entity work.dcfifo_32in_32out_8kb_cnt_rd_dc_as
port map (
Q(0) => Q(0),
S(3 downto 0) => S(3 downto 0),
WR_PNTR_RD(6 downto 0) => WR_PNTR_RD(6 downto 0),
rd_clk => rd_clk,
rd_data_count(0) => rd_data_count(0),
\wr_pntr_bin_reg[3]\(3 downto 0) => \wr_pntr_bin_reg[3]\(3 downto 0)
);
\gras.rsts\: entity work.dcfifo_32in_32out_8kb_cnt_rd_status_flags_as
port map (
E(0) => p_14_out,
Q(0) => Q(0),
empty => empty,
p_18_out => \^p_18_out\,
rd_clk => rd_clk,
rd_en => rd_en,
\wr_pntr_bin_reg[6]\ => rpntr_n_8
);
rpntr: entity work.dcfifo_32in_32out_8kb_cnt_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0),
E(0) => p_14_out,
Q(0) => Q(0),
WR_PNTR_RD(7 downto 0) => WR_PNTR_RD(7 downto 0),
p_18_out => \^p_18_out\,
ram_empty_i_reg => rpntr_n_8,
rd_clk => rd_clk,
rd_en => rd_en,
\wr_pntr_bin_reg[4]\ => \wr_pntr_bin_reg[4]\,
\wr_pntr_bin_reg[6]\ => \wr_pntr_bin_reg[6]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_wr_logic is
port (
full : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
WEBWE : out STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_en : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_wr_logic : entity is "wr_logic";
end dcfifo_32in_32out_8kb_cnt_wr_logic;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_wr_logic is
signal \^webwe\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out : STD_LOGIC;
begin
WEBWE(0) <= \^webwe\(0);
\gwas.wsts\: entity work.dcfifo_32in_32out_8kb_cnt_wr_status_flags_as
port map (
E(0) => \^webwe\(0),
full => full,
p_0_out => p_0_out,
ram_full_i => ram_full_i,
rst_full_ff_i => rst_full_ff_i,
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.dcfifo_32in_32out_8kb_cnt_wr_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0),
E(0) => \^webwe\(0),
Q(5 downto 0) => Q(5 downto 0),
RD_PNTR_WR(1 downto 0) => RD_PNTR_WR(1 downto 0),
\gic0.gc0.count_d2_reg[7]_0\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
p_0_out => p_0_out,
ram_full_fb_i_reg => ram_full_fb_i_reg,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end dcfifo_32in_32out_8kb_cnt_blk_mem_gen_generic_cstr;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.dcfifo_32in_32out_8kb_cnt_blk_mem_gen_prim_width
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_top : entity is "blk_mem_gen_top";
end dcfifo_32in_32out_8kb_cnt_blk_mem_gen_top;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_top is
begin
\valid.cstr\: entity work.dcfifo_32in_32out_8kb_cnt_blk_mem_gen_generic_cstr
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.dcfifo_32in_32out_8kb_cnt_blk_mem_gen_top
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2 : entity is "blk_mem_gen_v8_2";
end dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2 is
begin
inst_blk_mem_gen: entity work.dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2_synth
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_memory is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_memory : entity is "memory";
end dcfifo_32in_32out_8kb_cnt_memory;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.dcfifo_32in_32out_8kb_cnt_blk_mem_gen_v8_2
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end dcfifo_32in_32out_8kb_cnt_fifo_generator_ramfifo;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_12\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_13\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_14\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_15\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_16\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_17\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_18\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_19\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_1\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_8\ : STD_LOGIC;
signal \gwas.wsts/ram_full_i\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_20_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 7 downto 2 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.dcfifo_32in_32out_8kb_cnt_clk_x_pntrs
port map (
Q(7 downto 0) => p_20_out(7 downto 0),
RD_PNTR_WR(1 downto 0) => p_0_out(1 downto 0),
S(3) => \gntv_or_sync_fifo.gcx.clkx_n_12\,
S(2) => \gntv_or_sync_fifo.gcx.clkx_n_13\,
S(1) => \gntv_or_sync_fifo.gcx.clkx_n_14\,
S(0) => \gntv_or_sync_fifo.gcx.clkx_n_15\,
WR_PNTR_RD(7 downto 0) => p_1_out(7 downto 0),
\gic0.gc0.count_d1_reg[7]\(7 downto 0) => p_8_out(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => p_9_out(7 downto 0),
\gic0.gc0.count_reg[7]\(5 downto 0) => wr_pntr_plus2(7 downto 2),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => wr_rst_i(0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_0\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_i => \gwas.wsts/ram_full_i\,
rd_clk => rd_clk,
\rd_dc_i_reg[7]\(3) => \gntv_or_sync_fifo.gcx.clkx_n_16\,
\rd_dc_i_reg[7]\(2) => \gntv_or_sync_fifo.gcx.clkx_n_17\,
\rd_dc_i_reg[7]\(1) => \gntv_or_sync_fifo.gcx.clkx_n_18\,
\rd_dc_i_reg[7]\(0) => \gntv_or_sync_fifo.gcx.clkx_n_19\,
\rd_pntr_bin_reg[0]_0\ => \gntv_or_sync_fifo.gl0.wr_n_1\,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.dcfifo_32in_32out_8kb_cnt_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) => p_20_out(7 downto 0),
Q(0) => RD_RST,
S(3) => \gntv_or_sync_fifo.gcx.clkx_n_12\,
S(2) => \gntv_or_sync_fifo.gcx.clkx_n_13\,
S(1) => \gntv_or_sync_fifo.gcx.clkx_n_14\,
S(0) => \gntv_or_sync_fifo.gcx.clkx_n_15\,
WR_PNTR_RD(7 downto 0) => p_1_out(7 downto 0),
empty => empty,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_data_count(0) => rd_data_count(0),
rd_en => rd_en,
\wr_pntr_bin_reg[3]\(3) => \gntv_or_sync_fifo.gcx.clkx_n_16\,
\wr_pntr_bin_reg[3]\(2) => \gntv_or_sync_fifo.gcx.clkx_n_17\,
\wr_pntr_bin_reg[3]\(1) => \gntv_or_sync_fifo.gcx.clkx_n_18\,
\wr_pntr_bin_reg[3]\(0) => \gntv_or_sync_fifo.gcx.clkx_n_19\,
\wr_pntr_bin_reg[4]\ => \gntv_or_sync_fifo.gcx.clkx_n_0\,
\wr_pntr_bin_reg[6]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\
);
\gntv_or_sync_fifo.gl0.wr\: entity work.dcfifo_32in_32out_8kb_cnt_wr_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) => p_9_out(7 downto 0),
Q(5 downto 0) => wr_pntr_plus2(7 downto 2),
RD_PNTR_WR(1 downto 0) => p_0_out(1 downto 0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_8\,
full => full,
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => p_8_out(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \^rst\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_1\,
ram_full_i => \gwas.wsts/ram_full_i\,
rst_full_ff_i => rst_full_ff_i,
wr_clk => wr_clk,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.dcfifo_32in_32out_8kb_cnt_memory
port map (
Q(0) => rd_rst_i(0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_8\,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => p_20_out(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => p_9_out(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.dcfifo_32in_32out_8kb_cnt_reset_blk_ramfifo
port map (
Q(2) => RD_RST,
Q(1 downto 0) => rd_rst_i(1 downto 0),
\gic0.gc0.count_reg[0]\(1) => \^rst\,
\gic0.gc0.count_reg[0]\(0) => wr_rst_i(0),
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_fifo_generator_top : entity is "fifo_generator_top";
end dcfifo_32in_32out_8kb_cnt_fifo_generator_top;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_fifo_generator_top is
begin
\grf.rf\: entity work.dcfifo_32in_32out_8kb_cnt_fifo_generator_ramfifo
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_data_count(0) => rd_data_count(0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0_synth;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.dcfifo_32in_32out_8kb_cnt_fifo_generator_top
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_data_count(0) => rd_data_count(0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 7 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 253;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 252;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 256;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 256;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 8;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 : entity is "fifo_generator_v12_0";
end dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0_synth
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_data_count(0) => rd_data_count(0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_cnt is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dcfifo_32in_32out_8kb_cnt : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dcfifo_32in_32out_8kb_cnt : entity is "dcfifo_32in_32out_8kb_cnt,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of dcfifo_32in_32out_8kb_cnt : entity is "dcfifo_32in_32out_8kb_cnt,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=8,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=1,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=253,C_PROG_FULL_THRESH_NEGATE_VAL=252,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=1,C_RD_DEPTH=256,C_RD_FREQ=1,C_RD_PNTR_WIDTH=8,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=8,C_WR_DEPTH=256,C_WR_FREQ=1,C_WR_PNTR_WIDTH=8,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dcfifo_32in_32out_8kb_cnt : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dcfifo_32in_32out_8kb_cnt : entity is "fifo_generator_v12_0,Vivado 2015.1";
end dcfifo_32in_32out_8kb_cnt;
architecture STRUCTURE of dcfifo_32in_32out_8kb_cnt is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 8;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 253;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 252;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 1;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 256;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 8;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 8;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 256;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 8;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.dcfifo_32in_32out_8kb_cnt_fifo_generator_v12_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(7 downto 0) => NLW_U0_data_count_UNCONNECTED(7 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(7) => '0',
prog_empty_thresh(6) => '0',
prog_empty_thresh(5) => '0',
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(7) => '0',
prog_empty_thresh_assert(6) => '0',
prog_empty_thresh_assert(5) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(7) => '0',
prog_empty_thresh_negate(6) => '0',
prog_empty_thresh_negate(5) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(7) => '0',
prog_full_thresh(6) => '0',
prog_full_thresh(5) => '0',
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(7) => '0',
prog_full_thresh_assert(6) => '0',
prog_full_thresh_assert(5) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(7) => '0',
prog_full_thresh_negate(6) => '0',
prog_full_thresh_negate(5) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(0) => rd_data_count(0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(7 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(7 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.